arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include "kvm_cache_regs.h"
  35 #include "x86.h"
  36
  37 #include <asm/io.h>
  38 #include <asm/desc.h>
  39 #include <asm/vmx.h>
  40 #include <asm/virtext.h>
  41 #include <asm/mce.h>
  42 #include <asm/i387.h>
  43 #include <asm/xcr.h>
  44 #include <asm/perf_event.h>
  45 #include <asm/kexec.h>
  46
  47 #include "trace.h"
  48
  49 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  50 #define __ex_clear(x, reg) \
  51         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  52
  53 MODULE_AUTHOR("Qumranet");
  54 MODULE_LICENSE("GPL");
  55
  56 static const struct x86_cpu_id vmx_cpu_id[] = {
  57         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  58         {}
  59 };
  60 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  61
  62 static bool __read_mostly enable_vpid = 1;
  63 module_param_named(vpid, enable_vpid, bool, 0444);
  64
  65 static bool __read_mostly flexpriority_enabled = 1;
  66 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  67
  68 static bool __read_mostly enable_ept = 1;
  69 module_param_named(ept, enable_ept, bool, S_IRUGO);
  70
  71 static bool __read_mostly enable_unrestricted_guest = 1;
  72 module_param_named(unrestricted_guest,
  73                         enable_unrestricted_guest, bool, S_IRUGO);
  74
  75 static bool __read_mostly enable_ept_ad_bits = 1;
  76 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  77
  78 static bool __read_mostly emulate_invalid_guest_state = true;
  79 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  80
  81 static bool __read_mostly vmm_exclusive = 1;
  82 module_param(vmm_exclusive, bool, S_IRUGO);
  83
  84 static bool __read_mostly fasteoi = 1;
  85 module_param(fasteoi, bool, S_IRUGO);
  86
  87 static bool __read_mostly enable_apicv_reg_vid = 1;
  88 module_param(enable_apicv_reg_vid, bool, S_IRUGO);
  89
  90 /*
  91  * If nested=1, nested virtualization is supported, i.e., guests may use
  92  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  93  * use VMX instructions.
  94  */
  95 static bool __read_mostly nested = 0;
  96 module_param(nested, bool, S_IRUGO);
  97
  98 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  99         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
 100 #define KVM_GUEST_CR0_MASK                                              \
 101         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 102 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
 103         (X86_CR0_WP | X86_CR0_NE)
 104 #define KVM_VM_CR0_ALWAYS_ON                                            \
 105         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 106 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 107         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 108          | X86_CR4_OSXMMEXCPT)
 109
 110 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 111 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 112
 113 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 114
 115 /*
 116  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 117  * ple_gap:    upper bound on the amount of time between two successive
 118  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 119  *             According to test, this time is usually smaller than 128 cycles.
 120  * ple_window: upper bound on the amount of time a guest is allowed to execute
 121  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 122  *             less than 2^12 cycles
 123  * Time is measured based on a counter that runs at the same rate as the TSC,
 124  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 125  */
 126 #define KVM_VMX_DEFAULT_PLE_GAP    128
 127 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 128 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 129 module_param(ple_gap, int, S_IRUGO);
 130
 131 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 132 module_param(ple_window, int, S_IRUGO);
 133
 134 extern const ulong vmx_return;
 135
 136 #define NR_AUTOLOAD_MSRS 8
 137 #define VMCS02_POOL_SIZE 1
 138
 139 struct vmcs {
 140         u32 revision_id;
 141         u32 abort;
 142         char data[0];
 143 };
 144
 145 /*
 146  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 147  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 148  * loaded on this CPU (so we can clear them if the CPU goes down).
 149  */
 150 struct loaded_vmcs {
 151         struct vmcs *vmcs;
 152         int cpu;
 153         int launched;
 154         struct list_head loaded_vmcss_on_cpu_link;
 155 };
 156
 157 struct shared_msr_entry {
 158         unsigned index;
 159         u64 data;
 160         u64 mask;
 161 };
 162
 163 /*
 164  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 165  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 166  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 167  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 168  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 169  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 170  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 171  * underlying hardware which will be used to run L2.
 172  * This structure is packed to ensure that its layout is identical across
 173  * machines (necessary for live migration).
 174  * If there are changes in this struct, VMCS12_REVISION must be changed.
 175  */
 176 typedef u64 natural_width;
 177 struct __packed vmcs12 {
 178         /* According to the Intel spec, a VMCS region must start with the
 179          * following two fields. Then follow implementation-specific data.
 180          */
 181         u32 revision_id;
 182         u32 abort;
 183
 184         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 185         u32 padding[7]; /* room for future expansion */
 186
 187         u64 io_bitmap_a;
 188         u64 io_bitmap_b;
 189         u64 msr_bitmap;
 190         u64 vm_exit_msr_store_addr;
 191         u64 vm_exit_msr_load_addr;
 192         u64 vm_entry_msr_load_addr;
 193         u64 tsc_offset;
 194         u64 virtual_apic_page_addr;
 195         u64 apic_access_addr;
 196         u64 ept_pointer;
 197         u64 guest_physical_address;
 198         u64 vmcs_link_pointer;
 199         u64 guest_ia32_debugctl;
 200         u64 guest_ia32_pat;
 201         u64 guest_ia32_efer;
 202         u64 guest_ia32_perf_global_ctrl;
 203         u64 guest_pdptr0;
 204         u64 guest_pdptr1;
 205         u64 guest_pdptr2;
 206         u64 guest_pdptr3;
 207         u64 host_ia32_pat;
 208         u64 host_ia32_efer;
 209         u64 host_ia32_perf_global_ctrl;
 210         u64 padding64[8]; /* room for future expansion */
 211         /*
 212          * To allow migration of L1 (complete with its L2 guests) between
 213          * machines of different natural widths (32 or 64 bit), we cannot have
 214          * unsigned long fields with no explict size. We use u64 (aliased
 215          * natural_width) instead. Luckily, x86 is little-endian.
 216          */
 217         natural_width cr0_guest_host_mask;
 218         natural_width cr4_guest_host_mask;
 219         natural_width cr0_read_shadow;
 220         natural_width cr4_read_shadow;
 221         natural_width cr3_target_value0;
 222         natural_width cr3_target_value1;
 223         natural_width cr3_target_value2;
 224         natural_width cr3_target_value3;
 225         natural_width exit_qualification;
 226         natural_width guest_linear_address;
 227         natural_width guest_cr0;
 228         natural_width guest_cr3;
 229         natural_width guest_cr4;
 230         natural_width guest_es_base;
 231         natural_width guest_cs_base;
 232         natural_width guest_ss_base;
 233         natural_width guest_ds_base;
 234         natural_width guest_fs_base;
 235         natural_width guest_gs_base;
 236         natural_width guest_ldtr_base;
 237         natural_width guest_tr_base;
 238         natural_width guest_gdtr_base;
 239         natural_width guest_idtr_base;
 240         natural_width guest_dr7;
 241         natural_width guest_rsp;
 242         natural_width guest_rip;
 243         natural_width guest_rflags;
 244         natural_width guest_pending_dbg_exceptions;
 245         natural_width guest_sysenter_esp;
 246         natural_width guest_sysenter_eip;
 247         natural_width host_cr0;
 248         natural_width host_cr3;
 249         natural_width host_cr4;
 250         natural_width host_fs_base;
 251         natural_width host_gs_base;
 252         natural_width host_tr_base;
 253         natural_width host_gdtr_base;
 254         natural_width host_idtr_base;
 255         natural_width host_ia32_sysenter_esp;
 256         natural_width host_ia32_sysenter_eip;
 257         natural_width host_rsp;
 258         natural_width host_rip;
 259         natural_width paddingl[8]; /* room for future expansion */
 260         u32 pin_based_vm_exec_control;
 261         u32 cpu_based_vm_exec_control;
 262         u32 exception_bitmap;
 263         u32 page_fault_error_code_mask;
 264         u32 page_fault_error_code_match;
 265         u32 cr3_target_count;
 266         u32 vm_exit_controls;
 267         u32 vm_exit_msr_store_count;
 268         u32 vm_exit_msr_load_count;
 269         u32 vm_entry_controls;
 270         u32 vm_entry_msr_load_count;
 271         u32 vm_entry_intr_info_field;
 272         u32 vm_entry_exception_error_code;
 273         u32 vm_entry_instruction_len;
 274         u32 tpr_threshold;
 275         u32 secondary_vm_exec_control;
 276         u32 vm_instruction_error;
 277         u32 vm_exit_reason;
 278         u32 vm_exit_intr_info;
 279         u32 vm_exit_intr_error_code;
 280         u32 idt_vectoring_info_field;
 281         u32 idt_vectoring_error_code;
 282         u32 vm_exit_instruction_len;
 283         u32 vmx_instruction_info;
 284         u32 guest_es_limit;
 285         u32 guest_cs_limit;
 286         u32 guest_ss_limit;
 287         u32 guest_ds_limit;
 288         u32 guest_fs_limit;
 289         u32 guest_gs_limit;
 290         u32 guest_ldtr_limit;
 291         u32 guest_tr_limit;
 292         u32 guest_gdtr_limit;
 293         u32 guest_idtr_limit;
 294         u32 guest_es_ar_bytes;
 295         u32 guest_cs_ar_bytes;
 296         u32 guest_ss_ar_bytes;
 297         u32 guest_ds_ar_bytes;
 298         u32 guest_fs_ar_bytes;
 299         u32 guest_gs_ar_bytes;
 300         u32 guest_ldtr_ar_bytes;
 301         u32 guest_tr_ar_bytes;
 302         u32 guest_interruptibility_info;
 303         u32 guest_activity_state;
 304         u32 guest_sysenter_cs;
 305         u32 host_ia32_sysenter_cs;
 306         u32 padding32[8]; /* room for future expansion */
 307         u16 virtual_processor_id;
 308         u16 guest_es_selector;
 309         u16 guest_cs_selector;
 310         u16 guest_ss_selector;
 311         u16 guest_ds_selector;
 312         u16 guest_fs_selector;
 313         u16 guest_gs_selector;
 314         u16 guest_ldtr_selector;
 315         u16 guest_tr_selector;
 316         u16 host_es_selector;
 317         u16 host_cs_selector;
 318         u16 host_ss_selector;
 319         u16 host_ds_selector;
 320         u16 host_fs_selector;
 321         u16 host_gs_selector;
 322         u16 host_tr_selector;
 323 };
 324
 325 /*
 326  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 327  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 328  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 329  */
 330 #define VMCS12_REVISION 0x11e57ed0
 331
 332 /*
 333  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 334  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 335  * current implementation, 4K are reserved to avoid future complications.
 336  */
 337 #define VMCS12_SIZE 0x1000
 338
 339 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 340 struct vmcs02_list {
 341         struct list_head list;
 342         gpa_t vmptr;
 343         struct loaded_vmcs vmcs02;
 344 };
 345
 346 /*
 347  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 348  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 349  */
 350 struct nested_vmx {
 351         /* Has the level1 guest done vmxon? */
 352         bool vmxon;
 353
 354         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 355         gpa_t current_vmptr;
 356         /* The host-usable pointer to the above */
 357         struct page *current_vmcs12_page;
 358         struct vmcs12 *current_vmcs12;
 359
 360         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 361         struct list_head vmcs02_pool;
 362         int vmcs02_num;
 363         u64 vmcs01_tsc_offset;
 364         /* L2 must run next, and mustn't decide to exit to L1. */
 365         bool nested_run_pending;
 366         /*
 367          * Guest pages referred to in vmcs02 with host-physical pointers, so
 368          * we must keep them pinned while L2 runs.
 369          */
 370         struct page *apic_access_page;
 371 };
 372
 373 struct vcpu_vmx {
 374         struct kvm_vcpu       vcpu;
 375         unsigned long         host_rsp;
 376         u8                    fail;
 377         u8                    cpl;
 378         bool                  nmi_known_unmasked;
 379         u32                   exit_intr_info;
 380         u32                   idt_vectoring_info;
 381         ulong                 rflags;
 382         struct shared_msr_entry *guest_msrs;
 383         int                   nmsrs;
 384         int                   save_nmsrs;
 385 #ifdef CONFIG_X86_64
 386         u64                   msr_host_kernel_gs_base;
 387         u64                   msr_guest_kernel_gs_base;
 388 #endif
 389         /*
 390          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 391          * non-nested (L1) guest, it always points to vmcs01. For a nested
 392          * guest (L2), it points to a different VMCS.
 393          */
 394         struct loaded_vmcs    vmcs01;
 395         struct loaded_vmcs   *loaded_vmcs;
 396         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 397         struct msr_autoload {
 398                 unsigned nr;
 399                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 400                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 401         } msr_autoload;
 402         struct {
 403                 int           loaded;
 404                 u16           fs_sel, gs_sel, ldt_sel;
 405 #ifdef CONFIG_X86_64
 406                 u16           ds_sel, es_sel;
 407 #endif
 408                 int           gs_ldt_reload_needed;
 409                 int           fs_reload_needed;
 410         } host_state;
 411         struct {
 412                 int vm86_active;
 413                 ulong save_rflags;
 414                 struct kvm_segment segs[8];
 415         } rmode;
 416         struct {
 417                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 418                 struct kvm_save_segment {
 419                         u16 selector;
 420                         unsigned long base;
 421                         u32 limit;
 422                         u32 ar;
 423                 } seg[8];
 424         } segment_cache;
 425         int vpid;
 426         bool emulation_required;
 427
 428         /* Support for vnmi-less CPUs */
 429         int soft_vnmi_blocked;
 430         ktime_t entry_time;
 431         s64 vnmi_blocked_time;
 432         u32 exit_reason;
 433
 434         bool rdtscp_enabled;
 435
 436         /* Support for a guest hypervisor (nested VMX) */
 437         struct nested_vmx nested;
 438 };
 439
 440 enum segment_cache_field {
 441         SEG_FIELD_SEL = 0,
 442         SEG_FIELD_BASE = 1,
 443         SEG_FIELD_LIMIT = 2,
 444         SEG_FIELD_AR = 3,
 445
 446         SEG_FIELD_NR = 4
 447 };
 448
 449 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 450 {
 451         return container_of(vcpu, struct vcpu_vmx, vcpu);
 452 }
 453
 454 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 455 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 456 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 457                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 458
 459 static const unsigned short vmcs_field_to_offset_table[] = {
 460         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 461         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 462         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 463         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 464         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 465         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 466         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 467         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 468         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 469         FIELD(HOST_ES_SELECTOR, host_es_selector),
 470         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 471         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 472         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 473         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 474         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 475         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 476         FIELD64(IO_BITMAP_A, io_bitmap_a),
 477         FIELD64(IO_BITMAP_B, io_bitmap_b),
 478         FIELD64(MSR_BITMAP, msr_bitmap),
 479         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 480         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 481         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 482         FIELD64(TSC_OFFSET, tsc_offset),
 483         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 484         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 485         FIELD64(EPT_POINTER, ept_pointer),
 486         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 487         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 488         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 489         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 490         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 491         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 492         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 493         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 494         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 495         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 496         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 497         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 498         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 499         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 500         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 501         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 502         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 503         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 504         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 505         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 506         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 507         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 508         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 509         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 510         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 511         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 512         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 513         FIELD(TPR_THRESHOLD, tpr_threshold),
 514         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 515         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 516         FIELD(VM_EXIT_REASON, vm_exit_reason),
 517         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 518         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 519         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 520         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 521         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 522         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 523         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 524         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 525         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 526         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 527         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 528         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 529         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 530         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 531         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 532         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 533         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 534         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 535         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 536         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 537         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 538         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 539         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 540         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 541         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 542         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 543         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 544         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 545         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 546         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 547         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 548         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 549         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 550         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 551         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 552         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 553         FIELD(EXIT_QUALIFICATION, exit_qualification),
 554         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 555         FIELD(GUEST_CR0, guest_cr0),
 556         FIELD(GUEST_CR3, guest_cr3),
 557         FIELD(GUEST_CR4, guest_cr4),
 558         FIELD(GUEST_ES_BASE, guest_es_base),
 559         FIELD(GUEST_CS_BASE, guest_cs_base),
 560         FIELD(GUEST_SS_BASE, guest_ss_base),
 561         FIELD(GUEST_DS_BASE, guest_ds_base),
 562         FIELD(GUEST_FS_BASE, guest_fs_base),
 563         FIELD(GUEST_GS_BASE, guest_gs_base),
 564         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 565         FIELD(GUEST_TR_BASE, guest_tr_base),
 566         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 567         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 568         FIELD(GUEST_DR7, guest_dr7),
 569         FIELD(GUEST_RSP, guest_rsp),
 570         FIELD(GUEST_RIP, guest_rip),
 571         FIELD(GUEST_RFLAGS, guest_rflags),
 572         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 573         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 574         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 575         FIELD(HOST_CR0, host_cr0),
 576         FIELD(HOST_CR3, host_cr3),
 577         FIELD(HOST_CR4, host_cr4),
 578         FIELD(HOST_FS_BASE, host_fs_base),
 579         FIELD(HOST_GS_BASE, host_gs_base),
 580         FIELD(HOST_TR_BASE, host_tr_base),
 581         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 582         FIELD(HOST_IDTR_BASE, host_idtr_base),
 583         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 584         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 585         FIELD(HOST_RSP, host_rsp),
 586         FIELD(HOST_RIP, host_rip),
 587 };
 588 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 589
 590 static inline short vmcs_field_to_offset(unsigned long field)
 591 {
 592         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 593                 return -1;
 594         return vmcs_field_to_offset_table[field];
 595 }
 596
 597 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 598 {
 599         return to_vmx(vcpu)->nested.current_vmcs12;
 600 }
 601
 602 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 603 {
 604         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 605         if (is_error_page(page))
 606                 return NULL;
 607
 608         return page;
 609 }
 610
 611 static void nested_release_page(struct page *page)
 612 {
 613         kvm_release_page_dirty(page);
 614 }
 615
 616 static void nested_release_page_clean(struct page *page)
 617 {
 618         kvm_release_page_clean(page);
 619 }
 620
 621 static u64 construct_eptp(unsigned long root_hpa);
 622 static void kvm_cpu_vmxon(u64 addr);
 623 static void kvm_cpu_vmxoff(void);
 624 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
 625 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 626 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 627                             struct kvm_segment *var, int seg);
 628 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 629                             struct kvm_segment *var, int seg);
 630 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 631 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 632
 633 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 634 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 635 /*
 636  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 637  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 638  */
 639 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 640 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 641
 642 static unsigned long *vmx_io_bitmap_a;
 643 static unsigned long *vmx_io_bitmap_b;
 644 static unsigned long *vmx_msr_bitmap_legacy;
 645 static unsigned long *vmx_msr_bitmap_longmode;
 646 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 647 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 648
 649 static bool cpu_has_load_ia32_efer;
 650 static bool cpu_has_load_perf_global_ctrl;
 651
 652 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 653 static DEFINE_SPINLOCK(vmx_vpid_lock);
 654
 655 static struct vmcs_config {
 656         int size;
 657         int order;
 658         u32 revision_id;
 659         u32 pin_based_exec_ctrl;
 660         u32 cpu_based_exec_ctrl;
 661         u32 cpu_based_2nd_exec_ctrl;
 662         u32 vmexit_ctrl;
 663         u32 vmentry_ctrl;
 664 } vmcs_config;
 665
 666 static struct vmx_capability {
 667         u32 ept;
 668         u32 vpid;
 669 } vmx_capability;
 670
 671 #define VMX_SEGMENT_FIELD(seg)                                  \
 672         [VCPU_SREG_##seg] = {                                   \
 673                 .selector = GUEST_##seg##_SELECTOR,             \
 674                 .base = GUEST_##seg##_BASE,                     \
 675                 .limit = GUEST_##seg##_LIMIT,                   \
 676                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 677         }
 678
 679 static const struct kvm_vmx_segment_field {
 680         unsigned selector;
 681         unsigned base;
 682         unsigned limit;
 683         unsigned ar_bytes;
 684 } kvm_vmx_segment_fields[] = {
 685         VMX_SEGMENT_FIELD(CS),
 686         VMX_SEGMENT_FIELD(DS),
 687         VMX_SEGMENT_FIELD(ES),
 688         VMX_SEGMENT_FIELD(FS),
 689         VMX_SEGMENT_FIELD(GS),
 690         VMX_SEGMENT_FIELD(SS),
 691         VMX_SEGMENT_FIELD(TR),
 692         VMX_SEGMENT_FIELD(LDTR),
 693 };
 694
 695 static u64 host_efer;
 696
 697 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 698
 699 /*
 700  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 701  * away by decrementing the array size.
 702  */
 703 static const u32 vmx_msr_index[] = {
 704 #ifdef CONFIG_X86_64
 705         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 706 #endif
 707         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 708 };
 709 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 710
 711 static inline bool is_page_fault(u32 intr_info)
 712 {
 713         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 714                              INTR_INFO_VALID_MASK)) ==
 715                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 716 }
 717
 718 static inline bool is_no_device(u32 intr_info)
 719 {
 720         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 721                              INTR_INFO_VALID_MASK)) ==
 722                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 723 }
 724
 725 static inline bool is_invalid_opcode(u32 intr_info)
 726 {
 727         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 728                              INTR_INFO_VALID_MASK)) ==
 729                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 730 }
 731
 732 static inline bool is_external_interrupt(u32 intr_info)
 733 {
 734         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 735                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 736 }
 737
 738 static inline bool is_machine_check(u32 intr_info)
 739 {
 740         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 741                              INTR_INFO_VALID_MASK)) ==
 742                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 743 }
 744
 745 static inline bool cpu_has_vmx_msr_bitmap(void)
 746 {
 747         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 748 }
 749
 750 static inline bool cpu_has_vmx_tpr_shadow(void)
 751 {
 752         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 753 }
 754
 755 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 756 {
 757         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 758 }
 759
 760 static inline bool cpu_has_secondary_exec_ctrls(void)
 761 {
 762         return vmcs_config.cpu_based_exec_ctrl &
 763                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 764 }
 765
 766 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 767 {
 768         return vmcs_config.cpu_based_2nd_exec_ctrl &
 769                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 770 }
 771
 772 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
 773 {
 774         return vmcs_config.cpu_based_2nd_exec_ctrl &
 775                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
 776 }
 777
 778 static inline bool cpu_has_vmx_apic_register_virt(void)
 779 {
 780         return vmcs_config.cpu_based_2nd_exec_ctrl &
 781                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
 782 }
 783
 784 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
 785 {
 786         return vmcs_config.cpu_based_2nd_exec_ctrl &
 787                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
 788 }
 789
 790 static inline bool cpu_has_vmx_flexpriority(void)
 791 {
 792         return cpu_has_vmx_tpr_shadow() &&
 793                 cpu_has_vmx_virtualize_apic_accesses();
 794 }
 795
 796 static inline bool cpu_has_vmx_ept_execute_only(void)
 797 {
 798         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 799 }
 800
 801 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 802 {
 803         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 804 }
 805
 806 static inline bool cpu_has_vmx_eptp_writeback(void)
 807 {
 808         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 809 }
 810
 811 static inline bool cpu_has_vmx_ept_2m_page(void)
 812 {
 813         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 814 }
 815
 816 static inline bool cpu_has_vmx_ept_1g_page(void)
 817 {
 818         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 819 }
 820
 821 static inline bool cpu_has_vmx_ept_4levels(void)
 822 {
 823         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 824 }
 825
 826 static inline bool cpu_has_vmx_ept_ad_bits(void)
 827 {
 828         return vmx_capability.ept & VMX_EPT_AD_BIT;
 829 }
 830
 831 static inline bool cpu_has_vmx_invept_context(void)
 832 {
 833         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 834 }
 835
 836 static inline bool cpu_has_vmx_invept_global(void)
 837 {
 838         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 839 }
 840
 841 static inline bool cpu_has_vmx_invvpid_single(void)
 842 {
 843         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 844 }
 845
 846 static inline bool cpu_has_vmx_invvpid_global(void)
 847 {
 848         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 849 }
 850
 851 static inline bool cpu_has_vmx_ept(void)
 852 {
 853         return vmcs_config.cpu_based_2nd_exec_ctrl &
 854                 SECONDARY_EXEC_ENABLE_EPT;
 855 }
 856
 857 static inline bool cpu_has_vmx_unrestricted_guest(void)
 858 {
 859         return vmcs_config.cpu_based_2nd_exec_ctrl &
 860                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 861 }
 862
 863 static inline bool cpu_has_vmx_ple(void)
 864 {
 865         return vmcs_config.cpu_based_2nd_exec_ctrl &
 866                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 867 }
 868
 869 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 870 {
 871         return flexpriority_enabled && irqchip_in_kernel(kvm);
 872 }
 873
 874 static inline bool cpu_has_vmx_vpid(void)
 875 {
 876         return vmcs_config.cpu_based_2nd_exec_ctrl &
 877                 SECONDARY_EXEC_ENABLE_VPID;
 878 }
 879
 880 static inline bool cpu_has_vmx_rdtscp(void)
 881 {
 882         return vmcs_config.cpu_based_2nd_exec_ctrl &
 883                 SECONDARY_EXEC_RDTSCP;
 884 }
 885
 886 static inline bool cpu_has_vmx_invpcid(void)
 887 {
 888         return vmcs_config.cpu_based_2nd_exec_ctrl &
 889                 SECONDARY_EXEC_ENABLE_INVPCID;
 890 }
 891
 892 static inline bool cpu_has_virtual_nmis(void)
 893 {
 894         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 895 }
 896
 897 static inline bool cpu_has_vmx_wbinvd_exit(void)
 898 {
 899         return vmcs_config.cpu_based_2nd_exec_ctrl &
 900                 SECONDARY_EXEC_WBINVD_EXITING;
 901 }
 902
 903 static inline bool report_flexpriority(void)
 904 {
 905         return flexpriority_enabled;
 906 }
 907
 908 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
 909 {
 910         return vmcs12->cpu_based_vm_exec_control & bit;
 911 }
 912
 913 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
 914 {
 915         return (vmcs12->cpu_based_vm_exec_control &
 916                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
 917                 (vmcs12->secondary_vm_exec_control & bit);
 918 }
 919
 920 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
 921         struct kvm_vcpu *vcpu)
 922 {
 923         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
 924 }
 925
 926 static inline bool is_exception(u32 intr_info)
 927 {
 928         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 929                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
 930 }
 931
 932 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
 933 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
 934                         struct vmcs12 *vmcs12,
 935                         u32 reason, unsigned long qualification);
 936
 937 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 938 {
 939         int i;
 940
 941         for (i = 0; i < vmx->nmsrs; ++i)
 942                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 943                         return i;
 944         return -1;
 945 }
 946
 947 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 948 {
 949     struct {
 950         u64 vpid : 16;
 951         u64 rsvd : 48;
 952         u64 gva;
 953     } operand = { vpid, 0, gva };
 954
 955     asm volatile (__ex(ASM_VMX_INVVPID)
 956                   /* CF==1 or ZF==1 --> rc = -1 */
 957                   "; ja 1f ; ud2 ; 1:"
 958                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 959 }
 960
 961 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 962 {
 963         struct {
 964                 u64 eptp, gpa;
 965         } operand = {eptp, gpa};
 966
 967         asm volatile (__ex(ASM_VMX_INVEPT)
 968                         /* CF==1 or ZF==1 --> rc = -1 */
 969                         "; ja 1f ; ud2 ; 1:\n"
 970                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 971 }
 972
 973 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 974 {
 975         int i;
 976
 977         i = __find_msr_index(vmx, msr);
 978         if (i >= 0)
 979                 return &vmx->guest_msrs[i];
 980         return NULL;
 981 }
 982
 983 static void vmcs_clear(struct vmcs *vmcs)
 984 {
 985         u64 phys_addr = __pa(vmcs);
 986         u8 error;
 987
 988         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 989                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 990                       : "cc", "memory");
 991         if (error)
 992                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 993                        vmcs, phys_addr);
 994 }
 995
 996 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
 997 {
 998         vmcs_clear(loaded_vmcs->vmcs);
 999         loaded_vmcs->cpu = -1;
1000         loaded_vmcs->launched = 0;
1001 }
1002
1003 static void vmcs_load(struct vmcs *vmcs)
1004 {
1005         u64 phys_addr = __pa(vmcs);
1006         u8 error;
1007
1008         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1009                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1010                         : "cc", "memory");
1011         if (error)
1012                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1013                        vmcs, phys_addr);
1014 }
1015
1016 #ifdef CONFIG_KEXEC
1017 /*
1018  * This bitmap is used to indicate whether the vmclear
1019  * operation is enabled on all cpus. All disabled by
1020  * default.
1021  */
1022 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1023
1024 static inline void crash_enable_local_vmclear(int cpu)
1025 {
1026         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1027 }
1028
1029 static inline void crash_disable_local_vmclear(int cpu)
1030 {
1031         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1032 }
1033
1034 static inline int crash_local_vmclear_enabled(int cpu)
1035 {
1036         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1037 }
1038
1039 static void crash_vmclear_local_loaded_vmcss(void)
1040 {
1041         int cpu = raw_smp_processor_id();
1042         struct loaded_vmcs *v;
1043
1044         if (!crash_local_vmclear_enabled(cpu))
1045                 return;
1046
1047         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1048                             loaded_vmcss_on_cpu_link)
1049                 vmcs_clear(v->vmcs);
1050 }
1051 #else
1052 static inline void crash_enable_local_vmclear(int cpu) { }
1053 static inline void crash_disable_local_vmclear(int cpu) { }
1054 #endif /* CONFIG_KEXEC */
1055
1056 static void __loaded_vmcs_clear(void *arg)
1057 {
1058         struct loaded_vmcs *loaded_vmcs = arg;
1059         int cpu = raw_smp_processor_id();
1060
1061         if (loaded_vmcs->cpu != cpu)
1062                 return; /* vcpu migration can race with cpu offline */
1063         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1064                 per_cpu(current_vmcs, cpu) = NULL;
1065         crash_disable_local_vmclear(cpu);
1066         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1067
1068         /*
1069          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1070          * is before setting loaded_vmcs->vcpu to -1 which is done in
1071          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1072          * then adds the vmcs into percpu list before it is deleted.
1073          */
1074         smp_wmb();
1075
1076         loaded_vmcs_init(loaded_vmcs);
1077         crash_enable_local_vmclear(cpu);
1078 }
1079
1080 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1081 {
1082         int cpu = loaded_vmcs->cpu;
1083
1084         if (cpu != -1)
1085                 smp_call_function_single(cpu,
1086                          __loaded_vmcs_clear, loaded_vmcs, 1);
1087 }
1088
1089 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1090 {
1091         if (vmx->vpid == 0)
1092                 return;
1093
1094         if (cpu_has_vmx_invvpid_single())
1095                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1096 }
1097
1098 static inline void vpid_sync_vcpu_global(void)
1099 {
1100         if (cpu_has_vmx_invvpid_global())
1101                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1102 }
1103
1104 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1105 {
1106         if (cpu_has_vmx_invvpid_single())
1107                 vpid_sync_vcpu_single(vmx);
1108         else
1109                 vpid_sync_vcpu_global();
1110 }
1111
1112 static inline void ept_sync_global(void)
1113 {
1114         if (cpu_has_vmx_invept_global())
1115                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1116 }
1117
1118 static inline void ept_sync_context(u64 eptp)
1119 {
1120         if (enable_ept) {
1121                 if (cpu_has_vmx_invept_context())
1122                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1123                 else
1124                         ept_sync_global();
1125         }
1126 }
1127
1128 static __always_inline unsigned long vmcs_readl(unsigned long field)
1129 {
1130         unsigned long value;
1131
1132         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1133                       : "=a"(value) : "d"(field) : "cc");
1134         return value;
1135 }
1136
1137 static __always_inline u16 vmcs_read16(unsigned long field)
1138 {
1139         return vmcs_readl(field);
1140 }
1141
1142 static __always_inline u32 vmcs_read32(unsigned long field)
1143 {
1144         return vmcs_readl(field);
1145 }
1146
1147 static __always_inline u64 vmcs_read64(unsigned long field)
1148 {
1149 #ifdef CONFIG_X86_64
1150         return vmcs_readl(field);
1151 #else
1152         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1153 #endif
1154 }
1155
1156 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1157 {
1158         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1159                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1160         dump_stack();
1161 }
1162
1163 static void vmcs_writel(unsigned long field, unsigned long value)
1164 {
1165         u8 error;
1166
1167         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1168                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1169         if (unlikely(error))
1170                 vmwrite_error(field, value);
1171 }
1172
1173 static void vmcs_write16(unsigned long field, u16 value)
1174 {
1175         vmcs_writel(field, value);
1176 }
1177
1178 static void vmcs_write32(unsigned long field, u32 value)
1179 {
1180         vmcs_writel(field, value);
1181 }
1182
1183 static void vmcs_write64(unsigned long field, u64 value)
1184 {
1185         vmcs_writel(field, value);
1186 #ifndef CONFIG_X86_64
1187         asm volatile ("");
1188         vmcs_writel(field+1, value >> 32);
1189 #endif
1190 }
1191
1192 static void vmcs_clear_bits(unsigned long field, u32 mask)
1193 {
1194         vmcs_writel(field, vmcs_readl(field) & ~mask);
1195 }
1196
1197 static void vmcs_set_bits(unsigned long field, u32 mask)
1198 {
1199         vmcs_writel(field, vmcs_readl(field) | mask);
1200 }
1201
1202 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1203 {
1204         vmx->segment_cache.bitmask = 0;
1205 }
1206
1207 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1208                                        unsigned field)
1209 {
1210         bool ret;
1211         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1212
1213         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1214                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1215                 vmx->segment_cache.bitmask = 0;
1216         }
1217         ret = vmx->segment_cache.bitmask & mask;
1218         vmx->segment_cache.bitmask |= mask;
1219         return ret;
1220 }
1221
1222 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1223 {
1224         u16 *p = &vmx->segment_cache.seg[seg].selector;
1225
1226         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1227                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1228         return *p;
1229 }
1230
1231 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1232 {
1233         ulong *p = &vmx->segment_cache.seg[seg].base;
1234
1235         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1236                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1237         return *p;
1238 }
1239
1240 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1241 {
1242         u32 *p = &vmx->segment_cache.seg[seg].limit;
1243
1244         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1245                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1246         return *p;
1247 }
1248
1249 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1250 {
1251         u32 *p = &vmx->segment_cache.seg[seg].ar;
1252
1253         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1254                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1255         return *p;
1256 }
1257
1258 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1259 {
1260         u32 eb;
1261
1262         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1263              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1264         if ((vcpu->guest_debug &
1265              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1266             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1267                 eb |= 1u << BP_VECTOR;
1268         if (to_vmx(vcpu)->rmode.vm86_active)
1269                 eb = ~0;
1270         if (enable_ept)
1271                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1272         if (vcpu->fpu_active)
1273                 eb &= ~(1u << NM_VECTOR);
1274
1275         /* When we are running a nested L2 guest and L1 specified for it a
1276          * certain exception bitmap, we must trap the same exceptions and pass
1277          * them to L1. When running L2, we will only handle the exceptions
1278          * specified above if L1 did not want them.
1279          */
1280         if (is_guest_mode(vcpu))
1281                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1282
1283         vmcs_write32(EXCEPTION_BITMAP, eb);
1284 }
1285
1286 static void clear_atomic_switch_msr_special(unsigned long entry,
1287                 unsigned long exit)
1288 {
1289         vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1290         vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1291 }
1292
1293 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1294 {
1295         unsigned i;
1296         struct msr_autoload *m = &vmx->msr_autoload;
1297
1298         switch (msr) {
1299         case MSR_EFER:
1300                 if (cpu_has_load_ia32_efer) {
1301                         clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1302                                         VM_EXIT_LOAD_IA32_EFER);
1303                         return;
1304                 }
1305                 break;
1306         case MSR_CORE_PERF_GLOBAL_CTRL:
1307                 if (cpu_has_load_perf_global_ctrl) {
1308                         clear_atomic_switch_msr_special(
1309                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1310                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1311                         return;
1312                 }
1313                 break;
1314         }
1315
1316         for (i = 0; i < m->nr; ++i)
1317                 if (m->guest[i].index == msr)
1318                         break;
1319
1320         if (i == m->nr)
1321                 return;
1322         --m->nr;
1323         m->guest[i] = m->guest[m->nr];
1324         m->host[i] = m->host[m->nr];
1325         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1326         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1327 }
1328
1329 static void add_atomic_switch_msr_special(unsigned long entry,
1330                 unsigned long exit, unsigned long guest_val_vmcs,
1331                 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1332 {
1333         vmcs_write64(guest_val_vmcs, guest_val);
1334         vmcs_write64(host_val_vmcs, host_val);
1335         vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1336         vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1337 }
1338
1339 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1340                                   u64 guest_val, u64 host_val)
1341 {
1342         unsigned i;
1343         struct msr_autoload *m = &vmx->msr_autoload;
1344
1345         switch (msr) {
1346         case MSR_EFER:
1347                 if (cpu_has_load_ia32_efer) {
1348                         add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1349                                         VM_EXIT_LOAD_IA32_EFER,
1350                                         GUEST_IA32_EFER,
1351                                         HOST_IA32_EFER,
1352                                         guest_val, host_val);
1353                         return;
1354                 }
1355                 break;
1356         case MSR_CORE_PERF_GLOBAL_CTRL:
1357                 if (cpu_has_load_perf_global_ctrl) {
1358                         add_atomic_switch_msr_special(
1359                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1360                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1361                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1362                                         HOST_IA32_PERF_GLOBAL_CTRL,
1363                                         guest_val, host_val);
1364                         return;
1365                 }
1366                 break;
1367         }
1368
1369         for (i = 0; i < m->nr; ++i)
1370                 if (m->guest[i].index == msr)
1371                         break;
1372
1373         if (i == NR_AUTOLOAD_MSRS) {
1374                 printk_once(KERN_WARNING"Not enough mst switch entries. "
1375                                 "Can't add msr %x\n", msr);
1376                 return;
1377         } else if (i == m->nr) {
1378                 ++m->nr;
1379                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1380                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1381         }
1382
1383         m->guest[i].index = msr;
1384         m->guest[i].value = guest_val;
1385         m->host[i].index = msr;
1386         m->host[i].value = host_val;
1387 }
1388
1389 static void reload_tss(void)
1390 {
1391         /*
1392          * VT restores TR but not its size.  Useless.
1393          */
1394         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1395         struct desc_struct *descs;
1396
1397         descs = (void *)gdt->address;
1398         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1399         load_TR_desc();
1400 }
1401
1402 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1403 {
1404         u64 guest_efer;
1405         u64 ignore_bits;
1406
1407         guest_efer = vmx->vcpu.arch.efer;
1408
1409         /*
1410          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1411          * outside long mode
1412          */
1413         ignore_bits = EFER_NX | EFER_SCE;
1414 #ifdef CONFIG_X86_64
1415         ignore_bits |= EFER_LMA | EFER_LME;
1416         /* SCE is meaningful only in long mode on Intel */
1417         if (guest_efer & EFER_LMA)
1418                 ignore_bits &= ~(u64)EFER_SCE;
1419 #endif
1420         guest_efer &= ~ignore_bits;
1421         guest_efer |= host_efer & ignore_bits;
1422         vmx->guest_msrs[efer_offset].data = guest_efer;
1423         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1424
1425         clear_atomic_switch_msr(vmx, MSR_EFER);
1426         /* On ept, can't emulate nx, and must switch nx atomically */
1427         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1428                 guest_efer = vmx->vcpu.arch.efer;
1429                 if (!(guest_efer & EFER_LMA))
1430                         guest_efer &= ~EFER_LME;
1431                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1432                 return false;
1433         }
1434
1435         return true;
1436 }
1437
1438 static unsigned long segment_base(u16 selector)
1439 {
1440         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1441         struct desc_struct *d;
1442         unsigned long table_base;
1443         unsigned long v;
1444
1445         if (!(selector & ~3))
1446                 return 0;
1447
1448         table_base = gdt->address;
1449
1450         if (selector & 4) {           /* from ldt */
1451                 u16 ldt_selector = kvm_read_ldt();
1452
1453                 if (!(ldt_selector & ~3))
1454                         return 0;
1455
1456                 table_base = segment_base(ldt_selector);
1457         }
1458         d = (struct desc_struct *)(table_base + (selector & ~7));
1459         v = get_desc_base(d);
1460 #ifdef CONFIG_X86_64
1461        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1462                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1463 #endif
1464         return v;
1465 }
1466
1467 static inline unsigned long kvm_read_tr_base(void)
1468 {
1469         u16 tr;
1470         asm("str %0" : "=g"(tr));
1471         return segment_base(tr);
1472 }
1473
1474 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1475 {
1476         struct vcpu_vmx *vmx = to_vmx(vcpu);
1477         int i;
1478
1479         if (vmx->host_state.loaded)
1480                 return;
1481
1482         vmx->host_state.loaded = 1;
1483         /*
1484          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1485          * allow segment selectors with cpl > 0 or ti == 1.
1486          */
1487         vmx->host_state.ldt_sel = kvm_read_ldt();
1488         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1489         savesegment(fs, vmx->host_state.fs_sel);
1490         if (!(vmx->host_state.fs_sel & 7)) {
1491                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1492                 vmx->host_state.fs_reload_needed = 0;
1493         } else {
1494                 vmcs_write16(HOST_FS_SELECTOR, 0);
1495                 vmx->host_state.fs_reload_needed = 1;
1496         }
1497         savesegment(gs, vmx->host_state.gs_sel);
1498         if (!(vmx->host_state.gs_sel & 7))
1499                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1500         else {
1501                 vmcs_write16(HOST_GS_SELECTOR, 0);
1502                 vmx->host_state.gs_ldt_reload_needed = 1;
1503         }
1504
1505 #ifdef CONFIG_X86_64
1506         savesegment(ds, vmx->host_state.ds_sel);
1507         savesegment(es, vmx->host_state.es_sel);
1508 #endif
1509
1510 #ifdef CONFIG_X86_64
1511         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1512         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1513 #else
1514         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1515         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1516 #endif
1517
1518 #ifdef CONFIG_X86_64
1519         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1520         if (is_long_mode(&vmx->vcpu))
1521                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1522 #endif
1523         for (i = 0; i < vmx->save_nmsrs; ++i)
1524                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1525                                    vmx->guest_msrs[i].data,
1526                                    vmx->guest_msrs[i].mask);
1527 }
1528
1529 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1530 {
1531         if (!vmx->host_state.loaded)
1532                 return;
1533
1534         ++vmx->vcpu.stat.host_state_reload;
1535         vmx->host_state.loaded = 0;
1536 #ifdef CONFIG_X86_64
1537         if (is_long_mode(&vmx->vcpu))
1538                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1539 #endif
1540         if (vmx->host_state.gs_ldt_reload_needed) {
1541                 kvm_load_ldt(vmx->host_state.ldt_sel);
1542 #ifdef CONFIG_X86_64
1543                 load_gs_index(vmx->host_state.gs_sel);
1544 #else
1545                 loadsegment(gs, vmx->host_state.gs_sel);
1546 #endif
1547         }
1548         if (vmx->host_state.fs_reload_needed)
1549                 loadsegment(fs, vmx->host_state.fs_sel);
1550 #ifdef CONFIG_X86_64
1551         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1552                 loadsegment(ds, vmx->host_state.ds_sel);
1553                 loadsegment(es, vmx->host_state.es_sel);
1554         }
1555 #endif
1556         reload_tss();
1557 #ifdef CONFIG_X86_64
1558         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1559 #endif
1560         /*
1561          * If the FPU is not active (through the host task or
1562          * the guest vcpu), then restore the cr0.TS bit.
1563          */
1564         if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1565                 stts();
1566         load_gdt(&__get_cpu_var(host_gdt));
1567 }
1568
1569 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1570 {
1571         preempt_disable();
1572         __vmx_load_host_state(vmx);
1573         preempt_enable();
1574 }
1575
1576 /*
1577  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1578  * vcpu mutex is already taken.
1579  */
1580 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1581 {
1582         struct vcpu_vmx *vmx = to_vmx(vcpu);
1583         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1584
1585         if (!vmm_exclusive)
1586                 kvm_cpu_vmxon(phys_addr);
1587         else if (vmx->loaded_vmcs->cpu != cpu)
1588                 loaded_vmcs_clear(vmx->loaded_vmcs);
1589
1590         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1591                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1592                 vmcs_load(vmx->loaded_vmcs->vmcs);
1593         }
1594
1595         if (vmx->loaded_vmcs->cpu != cpu) {
1596                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1597                 unsigned long sysenter_esp;
1598
1599                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1600                 local_irq_disable();
1601                 crash_disable_local_vmclear(cpu);
1602
1603                 /*
1604                  * Read loaded_vmcs->cpu should be before fetching
1605                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1606                  * See the comments in __loaded_vmcs_clear().
1607                  */
1608                 smp_rmb();
1609
1610                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1611                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1612                 crash_enable_local_vmclear(cpu);
1613                 local_irq_enable();
1614
1615                 /*
1616                  * Linux uses per-cpu TSS and GDT, so set these when switching
1617                  * processors.
1618                  */
1619                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1620                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1621
1622                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1623                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1624                 vmx->loaded_vmcs->cpu = cpu;
1625         }
1626 }
1627
1628 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1629 {
1630         __vmx_load_host_state(to_vmx(vcpu));
1631         if (!vmm_exclusive) {
1632                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1633                 vcpu->cpu = -1;
1634                 kvm_cpu_vmxoff();
1635         }
1636 }
1637
1638 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1639 {
1640         ulong cr0;
1641
1642         if (vcpu->fpu_active)
1643                 return;
1644         vcpu->fpu_active = 1;
1645         cr0 = vmcs_readl(GUEST_CR0);
1646         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1647         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1648         vmcs_writel(GUEST_CR0, cr0);
1649         update_exception_bitmap(vcpu);
1650         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1651         if (is_guest_mode(vcpu))
1652                 vcpu->arch.cr0_guest_owned_bits &=
1653                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1654         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1655 }
1656
1657 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1658
1659 /*
1660  * Return the cr0 value that a nested guest would read. This is a combination
1661  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1662  * its hypervisor (cr0_read_shadow).
1663  */
1664 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1665 {
1666         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1667                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1668 }
1669 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1670 {
1671         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1672                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1673 }
1674
1675 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1676 {
1677         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1678          * set this *before* calling this function.
1679          */
1680         vmx_decache_cr0_guest_bits(vcpu);
1681         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1682         update_exception_bitmap(vcpu);
1683         vcpu->arch.cr0_guest_owned_bits = 0;
1684         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1685         if (is_guest_mode(vcpu)) {
1686                 /*
1687                  * L1's specified read shadow might not contain the TS bit,
1688                  * so now that we turned on shadowing of this bit, we need to
1689                  * set this bit of the shadow. Like in nested_vmx_run we need
1690                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1691                  * up-to-date here because we just decached cr0.TS (and we'll
1692                  * only update vmcs12->guest_cr0 on nested exit).
1693                  */
1694                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1695                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1696                         (vcpu->arch.cr0 & X86_CR0_TS);
1697                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1698         } else
1699                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1700 }
1701
1702 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1703 {
1704         unsigned long rflags, save_rflags;
1705
1706         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1707                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1708                 rflags = vmcs_readl(GUEST_RFLAGS);
1709                 if (to_vmx(vcpu)->rmode.vm86_active) {
1710                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1711                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1712                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1713                 }
1714                 to_vmx(vcpu)->rflags = rflags;
1715         }
1716         return to_vmx(vcpu)->rflags;
1717 }
1718
1719 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1720 {
1721         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1722         to_vmx(vcpu)->rflags = rflags;
1723         if (to_vmx(vcpu)->rmode.vm86_active) {
1724                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1725                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1726         }
1727         vmcs_writel(GUEST_RFLAGS, rflags);
1728 }
1729
1730 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1731 {
1732         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1733         int ret = 0;
1734
1735         if (interruptibility & GUEST_INTR_STATE_STI)
1736                 ret |= KVM_X86_SHADOW_INT_STI;
1737         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1738                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1739
1740         return ret & mask;
1741 }
1742
1743 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1744 {
1745         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1746         u32 interruptibility = interruptibility_old;
1747
1748         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1749
1750         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1751                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1752         else if (mask & KVM_X86_SHADOW_INT_STI)
1753                 interruptibility |= GUEST_INTR_STATE_STI;
1754
1755         if ((interruptibility != interruptibility_old))
1756                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1757 }
1758
1759 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1760 {
1761         unsigned long rip;
1762
1763         rip = kvm_rip_read(vcpu);
1764         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1765         kvm_rip_write(vcpu, rip);
1766
1767         /* skipping an emulated instruction also counts */
1768         vmx_set_interrupt_shadow(vcpu, 0);
1769 }
1770
1771 /*
1772  * KVM wants to inject page-faults which it got to the guest. This function
1773  * checks whether in a nested guest, we need to inject them to L1 or L2.
1774  * This function assumes it is called with the exit reason in vmcs02 being
1775  * a #PF exception (this is the only case in which KVM injects a #PF when L2
1776  * is running).
1777  */
1778 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1779 {
1780         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1781
1782         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1783         if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
1784                 return 0;
1785
1786         nested_vmx_vmexit(vcpu);
1787         return 1;
1788 }
1789
1790 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1791                                 bool has_error_code, u32 error_code,
1792                                 bool reinject)
1793 {
1794         struct vcpu_vmx *vmx = to_vmx(vcpu);
1795         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1796
1797         if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1798                 nested_pf_handled(vcpu))
1799                 return;
1800
1801         if (has_error_code) {
1802                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1803                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1804         }
1805
1806         if (vmx->rmode.vm86_active) {
1807                 int inc_eip = 0;
1808                 if (kvm_exception_is_soft(nr))
1809                         inc_eip = vcpu->arch.event_exit_inst_len;
1810                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1811                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1812                 return;
1813         }
1814
1815         if (kvm_exception_is_soft(nr)) {
1816                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1817                              vmx->vcpu.arch.event_exit_inst_len);
1818                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1819         } else
1820                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1821
1822         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1823 }
1824
1825 static bool vmx_rdtscp_supported(void)
1826 {
1827         return cpu_has_vmx_rdtscp();
1828 }
1829
1830 static bool vmx_invpcid_supported(void)
1831 {
1832         return cpu_has_vmx_invpcid() && enable_ept;
1833 }
1834
1835 /*
1836  * Swap MSR entry in host/guest MSR entry array.
1837  */
1838 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1839 {
1840         struct shared_msr_entry tmp;
1841
1842         tmp = vmx->guest_msrs[to];
1843         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1844         vmx->guest_msrs[from] = tmp;
1845 }
1846
1847 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
1848 {
1849         unsigned long *msr_bitmap;
1850
1851         if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
1852                 if (is_long_mode(vcpu))
1853                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
1854                 else
1855                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
1856         } else {
1857                 if (is_long_mode(vcpu))
1858                         msr_bitmap = vmx_msr_bitmap_longmode;
1859                 else
1860                         msr_bitmap = vmx_msr_bitmap_legacy;
1861         }
1862
1863         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1864 }
1865
1866 /*
1867  * Set up the vmcs to automatically save and restore system
1868  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1869  * mode, as fiddling with msrs is very expensive.
1870  */
1871 static void setup_msrs(struct vcpu_vmx *vmx)
1872 {
1873         int save_nmsrs, index;
1874
1875         save_nmsrs = 0;
1876 #ifdef CONFIG_X86_64
1877         if (is_long_mode(&vmx->vcpu)) {
1878                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1879                 if (index >= 0)
1880                         move_msr_up(vmx, index, save_nmsrs++);
1881                 index = __find_msr_index(vmx, MSR_LSTAR);
1882                 if (index >= 0)
1883                         move_msr_up(vmx, index, save_nmsrs++);
1884                 index = __find_msr_index(vmx, MSR_CSTAR);
1885                 if (index >= 0)
1886                         move_msr_up(vmx, index, save_nmsrs++);
1887                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1888                 if (index >= 0 && vmx->rdtscp_enabled)
1889                         move_msr_up(vmx, index, save_nmsrs++);
1890                 /*
1891                  * MSR_STAR is only needed on long mode guests, and only
1892                  * if efer.sce is enabled.
1893                  */
1894                 index = __find_msr_index(vmx, MSR_STAR);
1895                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1896                         move_msr_up(vmx, index, save_nmsrs++);
1897         }
1898 #endif
1899         index = __find_msr_index(vmx, MSR_EFER);
1900         if (index >= 0 && update_transition_efer(vmx, index))
1901                 move_msr_up(vmx, index, save_nmsrs++);
1902
1903         vmx->save_nmsrs = save_nmsrs;
1904
1905         if (cpu_has_vmx_msr_bitmap())
1906                 vmx_set_msr_bitmap(&vmx->vcpu);
1907 }
1908
1909 /*
1910  * reads and returns guest's timestamp counter "register"
1911  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1912  */
1913 static u64 guest_read_tsc(void)
1914 {
1915         u64 host_tsc, tsc_offset;
1916
1917         rdtscll(host_tsc);
1918         tsc_offset = vmcs_read64(TSC_OFFSET);
1919         return host_tsc + tsc_offset;
1920 }
1921
1922 /*
1923  * Like guest_read_tsc, but always returns L1's notion of the timestamp
1924  * counter, even if a nested guest (L2) is currently running.
1925  */
1926 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1927 {
1928         u64 tsc_offset;
1929
1930         tsc_offset = is_guest_mode(vcpu) ?
1931                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1932                 vmcs_read64(TSC_OFFSET);
1933         return host_tsc + tsc_offset;
1934 }
1935
1936 /*
1937  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
1938  * software catchup for faster rates on slower CPUs.
1939  */
1940 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1941 {
1942         if (!scale)
1943                 return;
1944
1945         if (user_tsc_khz > tsc_khz) {
1946                 vcpu->arch.tsc_catchup = 1;
1947                 vcpu->arch.tsc_always_catchup = 1;
1948         } else
1949                 WARN(1, "user requested TSC rate below hardware speed\n");
1950 }
1951
1952 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
1953 {
1954         return vmcs_read64(TSC_OFFSET);
1955 }
1956
1957 /*
1958  * writes 'offset' into guest's timestamp counter offset register
1959  */
1960 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1961 {
1962         if (is_guest_mode(vcpu)) {
1963                 /*
1964                  * We're here if L1 chose not to trap WRMSR to TSC. According
1965                  * to the spec, this should set L1's TSC; The offset that L1
1966                  * set for L2 remains unchanged, and still needs to be added
1967                  * to the newly set TSC to get L2's TSC.
1968                  */
1969                 struct vmcs12 *vmcs12;
1970                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1971                 /* recalculate vmcs02.TSC_OFFSET: */
1972                 vmcs12 = get_vmcs12(vcpu);
1973                 vmcs_write64(TSC_OFFSET, offset +
1974                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1975                          vmcs12->tsc_offset : 0));
1976         } else {
1977                 vmcs_write64(TSC_OFFSET, offset);
1978         }
1979 }
1980
1981 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1982 {
1983         u64 offset = vmcs_read64(TSC_OFFSET);
1984         vmcs_write64(TSC_OFFSET, offset + adjustment);
1985         if (is_guest_mode(vcpu)) {
1986                 /* Even when running L2, the adjustment needs to apply to L1 */
1987                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1988         }
1989 }
1990
1991 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1992 {
1993         return target_tsc - native_read_tsc();
1994 }
1995
1996 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1997 {
1998         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1999         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2000 }
2001
2002 /*
2003  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2004  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2005  * all guests if the "nested" module option is off, and can also be disabled
2006  * for a single guest by disabling its VMX cpuid bit.
2007  */
2008 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2009 {
2010         return nested && guest_cpuid_has_vmx(vcpu);
2011 }
2012
2013 /*
2014  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2015  * returned for the various VMX controls MSRs when nested VMX is enabled.
2016  * The same values should also be used to verify that vmcs12 control fields are
2017  * valid during nested entry from L1 to L2.
2018  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2019  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2020  * bit in the high half is on if the corresponding bit in the control field
2021  * may be on. See also vmx_control_verify().
2022  * TODO: allow these variables to be modified (downgraded) by module options
2023  * or other means.
2024  */
2025 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2026 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2027 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2028 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2029 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2030 static __init void nested_vmx_setup_ctls_msrs(void)
2031 {
2032         /*
2033          * Note that as a general rule, the high half of the MSRs (bits in
2034          * the control fields which may be 1) should be initialized by the
2035          * intersection of the underlying hardware's MSR (i.e., features which
2036          * can be supported) and the list of features we want to expose -
2037          * because they are known to be properly supported in our code.
2038          * Also, usually, the low half of the MSRs (bits which must be 1) can
2039          * be set to 0, meaning that L1 may turn off any of these bits. The
2040          * reason is that if one of these bits is necessary, it will appear
2041          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2042          * fields of vmcs01 and vmcs02, will turn these bits off - and
2043          * nested_vmx_exit_handled() will not pass related exits to L1.
2044          * These rules have exceptions below.
2045          */
2046
2047         /* pin-based controls */
2048         /*
2049          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2050          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2051          */
2052         nested_vmx_pinbased_ctls_low = 0x16 ;
2053         nested_vmx_pinbased_ctls_high = 0x16 |
2054                 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
2055                 PIN_BASED_VIRTUAL_NMIS;
2056
2057         /* exit controls */
2058         nested_vmx_exit_ctls_low = 0;
2059         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
2060 #ifdef CONFIG_X86_64
2061         nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
2062 #else
2063         nested_vmx_exit_ctls_high = 0;
2064 #endif
2065
2066         /* entry controls */
2067         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2068                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2069         nested_vmx_entry_ctls_low = 0;
2070         nested_vmx_entry_ctls_high &=
2071                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
2072
2073         /* cpu-based controls */
2074         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2075                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2076         nested_vmx_procbased_ctls_low = 0;
2077         nested_vmx_procbased_ctls_high &=
2078                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2079                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2080                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2081                 CPU_BASED_CR3_STORE_EXITING |
2082 #ifdef CONFIG_X86_64
2083                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2084 #endif
2085                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2086                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2087                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2088                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2089         /*
2090          * We can allow some features even when not supported by the
2091          * hardware. For example, L1 can specify an MSR bitmap - and we
2092          * can use it to avoid exits to L1 - even when L0 runs L2
2093          * without MSR bitmaps.
2094          */
2095         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2096
2097         /* secondary cpu-based controls */
2098         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2099                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2100         nested_vmx_secondary_ctls_low = 0;
2101         nested_vmx_secondary_ctls_high &=
2102                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2103 }
2104
2105 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2106 {
2107         /*
2108          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2109          */
2110         return ((control & high) | low) == control;
2111 }
2112
2113 static inline u64 vmx_control_msr(u32 low, u32 high)
2114 {
2115         return low | ((u64)high << 32);
2116 }
2117
2118 /*
2119  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2120  * also let it use VMX-specific MSRs.
2121  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2122  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2123  * like all other MSRs).
2124  */
2125 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2126 {
2127         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2128                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2129                 /*
2130                  * According to the spec, processors which do not support VMX
2131                  * should throw a #GP(0) when VMX capability MSRs are read.
2132                  */
2133                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2134                 return 1;
2135         }
2136
2137         switch (msr_index) {
2138         case MSR_IA32_FEATURE_CONTROL:
2139                 *pdata = 0;
2140                 break;
2141         case MSR_IA32_VMX_BASIC:
2142                 /*
2143                  * This MSR reports some information about VMX support. We
2144                  * should return information about the VMX we emulate for the
2145                  * guest, and the VMCS structure we give it - not about the
2146                  * VMX support of the underlying hardware.
2147                  */
2148                 *pdata = VMCS12_REVISION |
2149                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2150                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2151                 break;
2152         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2153         case MSR_IA32_VMX_PINBASED_CTLS:
2154                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2155                                         nested_vmx_pinbased_ctls_high);
2156                 break;
2157         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2158         case MSR_IA32_VMX_PROCBASED_CTLS:
2159                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2160                                         nested_vmx_procbased_ctls_high);
2161                 break;
2162         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2163         case MSR_IA32_VMX_EXIT_CTLS:
2164                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2165                                         nested_vmx_exit_ctls_high);
2166                 break;
2167         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2168         case MSR_IA32_VMX_ENTRY_CTLS:
2169                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2170                                         nested_vmx_entry_ctls_high);
2171                 break;
2172         case MSR_IA32_VMX_MISC:
2173                 *pdata = 0;
2174                 break;
2175         /*
2176          * These MSRs specify bits which the guest must keep fixed (on or off)
2177          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2178          * We picked the standard core2 setting.
2179          */
2180 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2181 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2182         case MSR_IA32_VMX_CR0_FIXED0:
2183                 *pdata = VMXON_CR0_ALWAYSON;
2184                 break;
2185         case MSR_IA32_VMX_CR0_FIXED1:
2186                 *pdata = -1ULL;
2187                 break;
2188         case MSR_IA32_VMX_CR4_FIXED0:
2189                 *pdata = VMXON_CR4_ALWAYSON;
2190                 break;
2191         case MSR_IA32_VMX_CR4_FIXED1:
2192                 *pdata = -1ULL;
2193                 break;
2194         case MSR_IA32_VMX_VMCS_ENUM:
2195                 *pdata = 0x1f;
2196                 break;
2197         case MSR_IA32_VMX_PROCBASED_CTLS2:
2198                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2199                                         nested_vmx_secondary_ctls_high);
2200                 break;
2201         case MSR_IA32_VMX_EPT_VPID_CAP:
2202                 /* Currently, no nested ept or nested vpid */
2203                 *pdata = 0;
2204                 break;
2205         default:
2206                 return 0;
2207         }
2208
2209         return 1;
2210 }
2211
2212 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2213 {
2214         if (!nested_vmx_allowed(vcpu))
2215                 return 0;
2216
2217         if (msr_index == MSR_IA32_FEATURE_CONTROL)
2218                 /* TODO: the right thing. */
2219                 return 1;
2220         /*
2221          * No need to treat VMX capability MSRs specially: If we don't handle
2222          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2223          */
2224         return 0;
2225 }
2226
2227 /*
2228  * Reads an msr value (of 'msr_index') into 'pdata'.
2229  * Returns 0 on success, non-0 otherwise.
2230  * Assumes vcpu_load() was already called.
2231  */
2232 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2233 {
2234         u64 data;
2235         struct shared_msr_entry *msr;
2236
2237         if (!pdata) {
2238                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2239                 return -EINVAL;
2240         }
2241
2242         switch (msr_index) {
2243 #ifdef CONFIG_X86_64
2244         case MSR_FS_BASE:
2245                 data = vmcs_readl(GUEST_FS_BASE);
2246                 break;
2247         case MSR_GS_BASE:
2248                 data = vmcs_readl(GUEST_GS_BASE);
2249                 break;
2250         case MSR_KERNEL_GS_BASE:
2251                 vmx_load_host_state(to_vmx(vcpu));
2252                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2253                 break;
2254 #endif
2255         case MSR_EFER:
2256                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2257         case MSR_IA32_TSC:
2258                 data = guest_read_tsc();
2259                 break;
2260         case MSR_IA32_SYSENTER_CS:
2261                 data = vmcs_read32(GUEST_SYSENTER_CS);
2262                 break;
2263         case MSR_IA32_SYSENTER_EIP:
2264                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2265                 break;
2266         case MSR_IA32_SYSENTER_ESP:
2267                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2268                 break;
2269         case MSR_TSC_AUX:
2270                 if (!to_vmx(vcpu)->rdtscp_enabled)
2271                         return 1;
2272                 /* Otherwise falls through */
2273         default:
2274                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2275                         return 0;
2276                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2277                 if (msr) {
2278                         data = msr->data;
2279                         break;
2280                 }
2281                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2282         }
2283
2284         *pdata = data;
2285         return 0;
2286 }
2287
2288 /*
2289  * Writes msr value into into the appropriate "register".
2290  * Returns 0 on success, non-0 otherwise.
2291  * Assumes vcpu_load() was already called.
2292  */
2293 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2294 {
2295         struct vcpu_vmx *vmx = to_vmx(vcpu);
2296         struct shared_msr_entry *msr;
2297         int ret = 0;
2298         u32 msr_index = msr_info->index;
2299         u64 data = msr_info->data;
2300
2301         switch (msr_index) {
2302         case MSR_EFER:
2303                 ret = kvm_set_msr_common(vcpu, msr_info);
2304                 break;
2305 #ifdef CONFIG_X86_64
2306         case MSR_FS_BASE:
2307                 vmx_segment_cache_clear(vmx);
2308                 vmcs_writel(GUEST_FS_BASE, data);
2309                 break;
2310         case MSR_GS_BASE:
2311                 vmx_segment_cache_clear(vmx);
2312                 vmcs_writel(GUEST_GS_BASE, data);
2313                 break;
2314         case MSR_KERNEL_GS_BASE:
2315                 vmx_load_host_state(vmx);
2316                 vmx->msr_guest_kernel_gs_base = data;
2317                 break;
2318 #endif
2319         case MSR_IA32_SYSENTER_CS:
2320                 vmcs_write32(GUEST_SYSENTER_CS, data);
2321                 break;
2322         case MSR_IA32_SYSENTER_EIP:
2323                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2324                 break;
2325         case MSR_IA32_SYSENTER_ESP:
2326                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2327                 break;
2328         case MSR_IA32_TSC:
2329                 kvm_write_tsc(vcpu, msr_info);
2330                 break;
2331         case MSR_IA32_CR_PAT:
2332                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2333                         vmcs_write64(GUEST_IA32_PAT, data);
2334                         vcpu->arch.pat = data;
2335                         break;
2336                 }
2337                 ret = kvm_set_msr_common(vcpu, msr_info);
2338                 break;
2339         case MSR_IA32_TSC_ADJUST:
2340                 ret = kvm_set_msr_common(vcpu, msr_info);
2341                 break;
2342         case MSR_TSC_AUX:
2343                 if (!vmx->rdtscp_enabled)
2344                         return 1;
2345                 /* Check reserved bit, higher 32 bits should be zero */
2346                 if ((data >> 32) != 0)
2347                         return 1;
2348                 /* Otherwise falls through */
2349         default:
2350                 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2351                         break;
2352                 msr = find_msr_entry(vmx, msr_index);
2353                 if (msr) {
2354                         msr->data = data;
2355                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2356                                 preempt_disable();
2357                                 kvm_set_shared_msr(msr->index, msr->data,
2358                                                    msr->mask);
2359                                 preempt_enable();
2360                         }
2361                         break;
2362                 }
2363                 ret = kvm_set_msr_common(vcpu, msr_info);
2364         }
2365
2366         return ret;
2367 }
2368
2369 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2370 {
2371         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2372         switch (reg) {
2373         case VCPU_REGS_RSP:
2374                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2375                 break;
2376         case VCPU_REGS_RIP:
2377                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2378                 break;
2379         case VCPU_EXREG_PDPTR:
2380                 if (enable_ept)
2381                         ept_save_pdptrs(vcpu);
2382                 break;
2383         default:
2384                 break;
2385         }
2386 }
2387
2388 static __init int cpu_has_kvm_support(void)
2389 {
2390         return cpu_has_vmx();
2391 }
2392
2393 static __init int vmx_disabled_by_bios(void)
2394 {
2395         u64 msr;
2396
2397         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2398         if (msr & FEATURE_CONTROL_LOCKED) {
2399                 /* launched w/ TXT and VMX disabled */
2400                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2401                         && tboot_enabled())
2402                         return 1;
2403                 /* launched w/o TXT and VMX only enabled w/ TXT */
2404                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2405                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2406                         && !tboot_enabled()) {
2407                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2408                                 "activate TXT before enabling KVM\n");
2409                         return 1;
2410                 }
2411                 /* launched w/o TXT and VMX disabled */
2412                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2413                         && !tboot_enabled())
2414                         return 1;
2415         }
2416
2417         return 0;
2418 }
2419
2420 static void kvm_cpu_vmxon(u64 addr)
2421 {
2422         asm volatile (ASM_VMX_VMXON_RAX
2423                         : : "a"(&addr), "m"(addr)
2424                         : "memory", "cc");
2425 }
2426
2427 static int hardware_enable(void *garbage)
2428 {
2429         int cpu = raw_smp_processor_id();
2430         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2431         u64 old, test_bits;
2432
2433         if (read_cr4() & X86_CR4_VMXE)
2434                 return -EBUSY;
2435
2436         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2437
2438         /*
2439          * Now we can enable the vmclear operation in kdump
2440          * since the loaded_vmcss_on_cpu list on this cpu
2441          * has been initialized.
2442          *
2443          * Though the cpu is not in VMX operation now, there
2444          * is no problem to enable the vmclear operation
2445          * for the loaded_vmcss_on_cpu list is empty!
2446          */
2447         crash_enable_local_vmclear(cpu);
2448
2449         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2450
2451         test_bits = FEATURE_CONTROL_LOCKED;
2452         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2453         if (tboot_enabled())
2454                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2455
2456         if ((old & test_bits) != test_bits) {
2457                 /* enable and lock */
2458                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2459         }
2460         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2461
2462         if (vmm_exclusive) {
2463                 kvm_cpu_vmxon(phys_addr);
2464                 ept_sync_global();
2465         }
2466
2467         store_gdt(&__get_cpu_var(host_gdt));
2468
2469         return 0;
2470 }
2471
2472 static void vmclear_local_loaded_vmcss(void)
2473 {
2474         int cpu = raw_smp_processor_id();
2475         struct loaded_vmcs *v, *n;
2476
2477         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2478                                  loaded_vmcss_on_cpu_link)
2479                 __loaded_vmcs_clear(v);
2480 }
2481
2482
2483 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2484  * tricks.
2485  */
2486 static void kvm_cpu_vmxoff(void)
2487 {
2488         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2489 }
2490
2491 static void hardware_disable(void *garbage)
2492 {
2493         if (vmm_exclusive) {
2494                 vmclear_local_loaded_vmcss();
2495                 kvm_cpu_vmxoff();
2496         }
2497         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2498 }
2499
2500 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2501                                       u32 msr, u32 *result)
2502 {
2503         u32 vmx_msr_low, vmx_msr_high;
2504         u32 ctl = ctl_min | ctl_opt;
2505
2506         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2507
2508         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2509         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2510
2511         /* Ensure minimum (required) set of control bits are supported. */
2512         if (ctl_min & ~ctl)
2513                 return -EIO;
2514
2515         *result = ctl;
2516         return 0;
2517 }
2518
2519 static __init bool allow_1_setting(u32 msr, u32 ctl)
2520 {
2521         u32 vmx_msr_low, vmx_msr_high;
2522
2523         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2524         return vmx_msr_high & ctl;
2525 }
2526
2527 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2528 {
2529         u32 vmx_msr_low, vmx_msr_high;
2530         u32 min, opt, min2, opt2;
2531         u32 _pin_based_exec_control = 0;
2532         u32 _cpu_based_exec_control = 0;
2533         u32 _cpu_based_2nd_exec_control = 0;
2534         u32 _vmexit_control = 0;
2535         u32 _vmentry_control = 0;
2536
2537         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2538         opt = PIN_BASED_VIRTUAL_NMIS;
2539         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2540                                 &_pin_based_exec_control) < 0)
2541                 return -EIO;
2542
2543         min = CPU_BASED_HLT_EXITING |
2544 #ifdef CONFIG_X86_64
2545               CPU_BASED_CR8_LOAD_EXITING |
2546               CPU_BASED_CR8_STORE_EXITING |
2547 #endif
2548               CPU_BASED_CR3_LOAD_EXITING |
2549               CPU_BASED_CR3_STORE_EXITING |
2550               CPU_BASED_USE_IO_BITMAPS |
2551               CPU_BASED_MOV_DR_EXITING |
2552               CPU_BASED_USE_TSC_OFFSETING |
2553               CPU_BASED_MWAIT_EXITING |
2554               CPU_BASED_MONITOR_EXITING |
2555               CPU_BASED_INVLPG_EXITING |
2556               CPU_BASED_RDPMC_EXITING;
2557
2558         opt = CPU_BASED_TPR_SHADOW |
2559               CPU_BASED_USE_MSR_BITMAPS |
2560               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2561         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2562                                 &_cpu_based_exec_control) < 0)
2563                 return -EIO;
2564 #ifdef CONFIG_X86_64
2565         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2566                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2567                                            ~CPU_BASED_CR8_STORE_EXITING;
2568 #endif
2569         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2570                 min2 = 0;
2571                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2572                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2573                         SECONDARY_EXEC_WBINVD_EXITING |
2574                         SECONDARY_EXEC_ENABLE_VPID |
2575                         SECONDARY_EXEC_ENABLE_EPT |
2576                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2577                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2578                         SECONDARY_EXEC_RDTSCP |
2579                         SECONDARY_EXEC_ENABLE_INVPCID |
2580                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2581                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
2582                 if (adjust_vmx_controls(min2, opt2,
2583                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2584                                         &_cpu_based_2nd_exec_control) < 0)
2585                         return -EIO;
2586         }
2587 #ifndef CONFIG_X86_64
2588         if (!(_cpu_based_2nd_exec_control &
2589                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2590                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2591 #endif
2592
2593         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2594                 _cpu_based_2nd_exec_control &= ~(
2595                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2596                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2597                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2598
2599         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2600                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2601                    enabled */
2602                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2603                                              CPU_BASED_CR3_STORE_EXITING |
2604                                              CPU_BASED_INVLPG_EXITING);
2605                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2606                       vmx_capability.ept, vmx_capability.vpid);
2607         }
2608
2609         min = 0;
2610 #ifdef CONFIG_X86_64
2611         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2612 #endif
2613         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2614         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2615                                 &_vmexit_control) < 0)
2616                 return -EIO;
2617
2618         min = 0;
2619         opt = VM_ENTRY_LOAD_IA32_PAT;
2620         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2621                                 &_vmentry_control) < 0)
2622                 return -EIO;
2623
2624         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2625
2626         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2627         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2628                 return -EIO;
2629
2630 #ifdef CONFIG_X86_64
2631         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2632         if (vmx_msr_high & (1u<<16))
2633                 return -EIO;
2634 #endif
2635
2636         /* Require Write-Back (WB) memory type for VMCS accesses. */
2637         if (((vmx_msr_high >> 18) & 15) != 6)
2638                 return -EIO;
2639
2640         vmcs_conf->size = vmx_msr_high & 0x1fff;
2641         vmcs_conf->order = get_order(vmcs_config.size);
2642         vmcs_conf->revision_id = vmx_msr_low;
2643
2644         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2645         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2646         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2647         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2648         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2649
2650         cpu_has_load_ia32_efer =
2651                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2652                                 VM_ENTRY_LOAD_IA32_EFER)
2653                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2654                                    VM_EXIT_LOAD_IA32_EFER);
2655
2656         cpu_has_load_perf_global_ctrl =
2657                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2658                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2659                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2660                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2661
2662         /*
2663          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2664          * but due to arrata below it can't be used. Workaround is to use
2665          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2666          *
2667          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2668          *
2669          * AAK155             (model 26)
2670          * AAP115             (model 30)
2671          * AAT100             (model 37)
2672          * BC86,AAY89,BD102   (model 44)
2673          * BA97               (model 46)
2674          *
2675          */
2676         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2677                 switch (boot_cpu_data.x86_model) {
2678                 case 26:
2679                 case 30:
2680                 case 37:
2681                 case 44:
2682                 case 46:
2683                         cpu_has_load_perf_global_ctrl = false;
2684                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2685                                         "does not work properly. Using workaround\n");
2686                         break;
2687                 default:
2688                         break;
2689                 }
2690         }
2691
2692         return 0;
2693 }
2694
2695 static struct vmcs *alloc_vmcs_cpu(int cpu)
2696 {
2697         int node = cpu_to_node(cpu);
2698         struct page *pages;
2699         struct vmcs *vmcs;
2700
2701         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2702         if (!pages)
2703                 return NULL;
2704         vmcs = page_address(pages);
2705         memset(vmcs, 0, vmcs_config.size);
2706         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2707         return vmcs;
2708 }
2709
2710 static struct vmcs *alloc_vmcs(void)
2711 {
2712         return alloc_vmcs_cpu(raw_smp_processor_id());
2713 }
2714
2715 static void free_vmcs(struct vmcs *vmcs)
2716 {
2717         free_pages((unsigned long)vmcs, vmcs_config.order);
2718 }
2719
2720 /*
2721  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2722  */
2723 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2724 {
2725         if (!loaded_vmcs->vmcs)
2726                 return;
2727         loaded_vmcs_clear(loaded_vmcs);
2728         free_vmcs(loaded_vmcs->vmcs);
2729         loaded_vmcs->vmcs = NULL;
2730 }
2731
2732 static void free_kvm_area(void)
2733 {
2734         int cpu;
2735
2736         for_each_possible_cpu(cpu) {
2737                 free_vmcs(per_cpu(vmxarea, cpu));
2738                 per_cpu(vmxarea, cpu) = NULL;
2739         }
2740 }
2741
2742 static __init int alloc_kvm_area(void)
2743 {
2744         int cpu;
2745
2746         for_each_possible_cpu(cpu) {
2747                 struct vmcs *vmcs;
2748
2749                 vmcs = alloc_vmcs_cpu(cpu);
2750                 if (!vmcs) {
2751                         free_kvm_area();
2752                         return -ENOMEM;
2753                 }
2754
2755                 per_cpu(vmxarea, cpu) = vmcs;
2756         }
2757         return 0;
2758 }
2759
2760 static __init int hardware_setup(void)
2761 {
2762         if (setup_vmcs_config(&vmcs_config) < 0)
2763                 return -EIO;
2764
2765         if (boot_cpu_has(X86_FEATURE_NX))
2766                 kvm_enable_efer_bits(EFER_NX);
2767
2768         if (!cpu_has_vmx_vpid())
2769                 enable_vpid = 0;
2770
2771         if (!cpu_has_vmx_ept() ||
2772             !cpu_has_vmx_ept_4levels()) {
2773                 enable_ept = 0;
2774                 enable_unrestricted_guest = 0;
2775                 enable_ept_ad_bits = 0;
2776         }
2777
2778         if (!cpu_has_vmx_ept_ad_bits())
2779                 enable_ept_ad_bits = 0;
2780
2781         if (!cpu_has_vmx_unrestricted_guest())
2782                 enable_unrestricted_guest = 0;
2783
2784         if (!cpu_has_vmx_flexpriority())
2785                 flexpriority_enabled = 0;
2786
2787         if (!cpu_has_vmx_tpr_shadow())
2788                 kvm_x86_ops->update_cr8_intercept = NULL;
2789
2790         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2791                 kvm_disable_largepages();
2792
2793         if (!cpu_has_vmx_ple())
2794                 ple_gap = 0;
2795
2796         if (!cpu_has_vmx_apic_register_virt() ||
2797                                 !cpu_has_vmx_virtual_intr_delivery())
2798                 enable_apicv_reg_vid = 0;
2799
2800         if (enable_apicv_reg_vid)
2801                 kvm_x86_ops->update_cr8_intercept = NULL;
2802         else
2803                 kvm_x86_ops->hwapic_irr_update = NULL;
2804
2805         if (nested)
2806                 nested_vmx_setup_ctls_msrs();
2807
2808         return alloc_kvm_area();
2809 }
2810
2811 static __exit void hardware_unsetup(void)
2812 {
2813         free_kvm_area();
2814 }
2815
2816 static bool emulation_required(struct kvm_vcpu *vcpu)
2817 {
2818         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2819 }
2820
2821 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2822                 struct kvm_segment *save)
2823 {
2824         if (!emulate_invalid_guest_state) {
2825                 /*
2826                  * CS and SS RPL should be equal during guest entry according
2827                  * to VMX spec, but in reality it is not always so. Since vcpu
2828                  * is in the middle of the transition from real mode to
2829                  * protected mode it is safe to assume that RPL 0 is a good
2830                  * default value.
2831                  */
2832                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2833                         save->selector &= ~SELECTOR_RPL_MASK;
2834                 save->dpl = save->selector & SELECTOR_RPL_MASK;
2835                 save->s = 1;
2836         }
2837         vmx_set_segment(vcpu, save, seg);
2838 }
2839
2840 static void enter_pmode(struct kvm_vcpu *vcpu)
2841 {
2842         unsigned long flags;
2843         struct vcpu_vmx *vmx = to_vmx(vcpu);
2844
2845         /*
2846          * Update real mode segment cache. It may be not up-to-date if sement
2847          * register was written while vcpu was in a guest mode.
2848          */
2849         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2850         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2851         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2852         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2853         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2854         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2855
2856         vmx->rmode.vm86_active = 0;
2857
2858         vmx_segment_cache_clear(vmx);
2859
2860         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2861
2862         flags = vmcs_readl(GUEST_RFLAGS);
2863         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2864         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2865         vmcs_writel(GUEST_RFLAGS, flags);
2866
2867         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2868                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2869
2870         update_exception_bitmap(vcpu);
2871
2872         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2873         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2874         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2875         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2876         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2877         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2878
2879         /* CPL is always 0 when CPU enters protected mode */
2880         __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2881         vmx->cpl = 0;
2882 }
2883
2884 static gva_t rmode_tss_base(struct kvm *kvm)
2885 {
2886         if (!kvm->arch.tss_addr) {
2887                 struct kvm_memslots *slots;
2888                 struct kvm_memory_slot *slot;
2889                 gfn_t base_gfn;
2890
2891                 slots = kvm_memslots(kvm);
2892                 slot = id_to_memslot(slots, 0);
2893                 base_gfn = slot->base_gfn + slot->npages - 3;
2894
2895                 return base_gfn << PAGE_SHIFT;
2896         }
2897         return kvm->arch.tss_addr;
2898 }
2899
2900 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2901 {
2902         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2903         struct kvm_segment var = *save;
2904
2905         var.dpl = 0x3;
2906         if (seg == VCPU_SREG_CS)
2907                 var.type = 0x3;
2908
2909         if (!emulate_invalid_guest_state) {
2910                 var.selector = var.base >> 4;
2911                 var.base = var.base & 0xffff0;
2912                 var.limit = 0xffff;
2913                 var.g = 0;
2914                 var.db = 0;
2915                 var.present = 1;
2916                 var.s = 1;
2917                 var.l = 0;
2918                 var.unusable = 0;
2919                 var.type = 0x3;
2920                 var.avl = 0;
2921                 if (save->base & 0xf)
2922                         printk_once(KERN_WARNING "kvm: segment base is not "
2923                                         "paragraph aligned when entering "
2924                                         "protected mode (seg=%d)", seg);
2925         }
2926
2927         vmcs_write16(sf->selector, var.selector);
2928         vmcs_write32(sf->base, var.base);
2929         vmcs_write32(sf->limit, var.limit);
2930         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2931 }
2932
2933 static void enter_rmode(struct kvm_vcpu *vcpu)
2934 {
2935         unsigned long flags;
2936         struct vcpu_vmx *vmx = to_vmx(vcpu);
2937
2938         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2939         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2940         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2941         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2942         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2943         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2944         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2945
2946         vmx->rmode.vm86_active = 1;
2947
2948         /*
2949          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2950          * vcpu. Call it here with phys address pointing 16M below 4G.
2951          */
2952         if (!vcpu->kvm->arch.tss_addr) {
2953                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2954                              "called before entering vcpu\n");
2955                 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2956                 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2957                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2958         }
2959
2960         vmx_segment_cache_clear(vmx);
2961
2962         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2963         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2964         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2965
2966         flags = vmcs_readl(GUEST_RFLAGS);
2967         vmx->rmode.save_rflags = flags;
2968
2969         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2970
2971         vmcs_writel(GUEST_RFLAGS, flags);
2972         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2973         update_exception_bitmap(vcpu);
2974
2975         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2976         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2977         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2978         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2979         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2980         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2981
2982         kvm_mmu_reset_context(vcpu);
2983 }
2984
2985 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2986 {
2987         struct vcpu_vmx *vmx = to_vmx(vcpu);
2988         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2989
2990         if (!msr)
2991                 return;
2992
2993         /*
2994          * Force kernel_gs_base reloading before EFER changes, as control
2995          * of this msr depends on is_long_mode().
2996          */
2997         vmx_load_host_state(to_vmx(vcpu));
2998         vcpu->arch.efer = efer;
2999         if (efer & EFER_LMA) {
3000                 vmcs_write32(VM_ENTRY_CONTROLS,
3001                              vmcs_read32(VM_ENTRY_CONTROLS) |
3002                              VM_ENTRY_IA32E_MODE);
3003                 msr->data = efer;
3004         } else {
3005                 vmcs_write32(VM_ENTRY_CONTROLS,
3006                              vmcs_read32(VM_ENTRY_CONTROLS) &
3007                              ~VM_ENTRY_IA32E_MODE);
3008
3009                 msr->data = efer & ~EFER_LME;
3010         }
3011         setup_msrs(vmx);
3012 }
3013
3014 #ifdef CONFIG_X86_64
3015
3016 static void enter_lmode(struct kvm_vcpu *vcpu)
3017 {
3018         u32 guest_tr_ar;
3019
3020         vmx_segment_cache_clear(to_vmx(vcpu));
3021
3022         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3023         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3024                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3025                                      __func__);
3026                 vmcs_write32(GUEST_TR_AR_BYTES,
3027                              (guest_tr_ar & ~AR_TYPE_MASK)
3028                              | AR_TYPE_BUSY_64_TSS);
3029         }
3030         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3031 }
3032
3033 static void exit_lmode(struct kvm_vcpu *vcpu)
3034 {
3035         vmcs_write32(VM_ENTRY_CONTROLS,
3036                      vmcs_read32(VM_ENTRY_CONTROLS)
3037                      & ~VM_ENTRY_IA32E_MODE);
3038         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3039 }
3040
3041 #endif
3042
3043 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3044 {
3045         vpid_sync_context(to_vmx(vcpu));
3046         if (enable_ept) {
3047                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3048                         return;
3049                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3050         }
3051 }
3052
3053 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3054 {
3055         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3056
3057         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3058         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3059 }
3060
3061 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3062 {
3063         if (enable_ept && is_paging(vcpu))
3064                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3065         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3066 }
3067
3068 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3069 {
3070         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3071
3072         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3073         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3074 }
3075
3076 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3077 {
3078         if (!test_bit(VCPU_EXREG_PDPTR,
3079                       (unsigned long *)&vcpu->arch.regs_dirty))
3080                 return;
3081
3082         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3083                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3084                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3085                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3086                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
3087         }
3088 }
3089
3090 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3091 {
3092         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3093                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3094                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3095                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3096                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3097         }
3098
3099         __set_bit(VCPU_EXREG_PDPTR,
3100                   (unsigned long *)&vcpu->arch.regs_avail);
3101         __set_bit(VCPU_EXREG_PDPTR,
3102                   (unsigned long *)&vcpu->arch.regs_dirty);
3103 }
3104
3105 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3106
3107 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3108                                         unsigned long cr0,
3109                                         struct kvm_vcpu *vcpu)
3110 {
3111         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3112                 vmx_decache_cr3(vcpu);
3113         if (!(cr0 & X86_CR0_PG)) {
3114                 /* From paging/starting to nonpaging */
3115                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3116                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3117                              (CPU_BASED_CR3_LOAD_EXITING |
3118                               CPU_BASED_CR3_STORE_EXITING));
3119                 vcpu->arch.cr0 = cr0;
3120                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3121         } else if (!is_paging(vcpu)) {
3122                 /* From nonpaging to paging */
3123                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3124                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3125                              ~(CPU_BASED_CR3_LOAD_EXITING |
3126                                CPU_BASED_CR3_STORE_EXITING));
3127                 vcpu->arch.cr0 = cr0;
3128                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3129         }
3130
3131         if (!(cr0 & X86_CR0_WP))
3132                 *hw_cr0 &= ~X86_CR0_WP;
3133 }
3134
3135 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3136 {
3137         struct vcpu_vmx *vmx = to_vmx(vcpu);
3138         unsigned long hw_cr0;
3139
3140         if (enable_unrestricted_guest)
3141                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
3142                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3143         else {
3144                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
3145
3146                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3147                         enter_pmode(vcpu);
3148
3149                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3150                         enter_rmode(vcpu);
3151         }
3152
3153 #ifdef CONFIG_X86_64
3154         if (vcpu->arch.efer & EFER_LME) {
3155                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3156                         enter_lmode(vcpu);
3157                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3158                         exit_lmode(vcpu);
3159         }
3160 #endif
3161
3162         if (enable_ept)
3163                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3164
3165         if (!vcpu->fpu_active)
3166                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3167
3168         vmcs_writel(CR0_READ_SHADOW, cr0);
3169         vmcs_writel(GUEST_CR0, hw_cr0);
3170         vcpu->arch.cr0 = cr0;
3171
3172         /* depends on vcpu->arch.cr0 to be set to a new value */
3173         vmx->emulation_required = emulation_required(vcpu);
3174 }
3175
3176 static u64 construct_eptp(unsigned long root_hpa)
3177 {
3178         u64 eptp;
3179
3180         /* TODO write the value reading from MSR */
3181         eptp = VMX_EPT_DEFAULT_MT |
3182                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3183         if (enable_ept_ad_bits)
3184                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3185         eptp |= (root_hpa & PAGE_MASK);
3186
3187         return eptp;
3188 }
3189
3190 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3191 {
3192         unsigned long guest_cr3;
3193         u64 eptp;
3194
3195         guest_cr3 = cr3;
3196         if (enable_ept) {
3197                 eptp = construct_eptp(cr3);
3198                 vmcs_write64(EPT_POINTER, eptp);
3199                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3200                         vcpu->kvm->arch.ept_identity_map_addr;
3201                 ept_load_pdptrs(vcpu);
3202         }
3203
3204         vmx_flush_tlb(vcpu);
3205         vmcs_writel(GUEST_CR3, guest_cr3);
3206 }
3207
3208 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3209 {
3210         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3211                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3212
3213         if (cr4 & X86_CR4_VMXE) {
3214                 /*
3215                  * To use VMXON (and later other VMX instructions), a guest
3216                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3217                  * So basically the check on whether to allow nested VMX
3218                  * is here.
3219                  */
3220                 if (!nested_vmx_allowed(vcpu))
3221                         return 1;
3222         } else if (to_vmx(vcpu)->nested.vmxon)
3223                 return 1;
3224
3225         vcpu->arch.cr4 = cr4;
3226         if (enable_ept) {
3227                 if (!is_paging(vcpu)) {
3228                         hw_cr4 &= ~X86_CR4_PAE;
3229                         hw_cr4 |= X86_CR4_PSE;
3230                         /*
3231                          * SMEP is disabled if CPU is in non-paging mode in
3232                          * hardware. However KVM always uses paging mode to
3233                          * emulate guest non-paging mode with TDP.
3234                          * To emulate this behavior, SMEP needs to be manually
3235                          * disabled when guest switches to non-paging mode.
3236                          */
3237                         hw_cr4 &= ~X86_CR4_SMEP;
3238                 } else if (!(cr4 & X86_CR4_PAE)) {
3239                         hw_cr4 &= ~X86_CR4_PAE;
3240                 }
3241         }
3242
3243         vmcs_writel(CR4_READ_SHADOW, cr4);
3244         vmcs_writel(GUEST_CR4, hw_cr4);
3245         return 0;
3246 }
3247
3248 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3249                             struct kvm_segment *var, int seg)
3250 {
3251         struct vcpu_vmx *vmx = to_vmx(vcpu);
3252         u32 ar;
3253
3254         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3255                 *var = vmx->rmode.segs[seg];
3256                 if (seg == VCPU_SREG_TR
3257                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3258                         return;
3259                 var->base = vmx_read_guest_seg_base(vmx, seg);
3260                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3261                 return;
3262         }
3263         var->base = vmx_read_guest_seg_base(vmx, seg);
3264         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3265         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3266         ar = vmx_read_guest_seg_ar(vmx, seg);
3267         var->type = ar & 15;
3268         var->s = (ar >> 4) & 1;
3269         var->dpl = (ar >> 5) & 3;
3270         var->present = (ar >> 7) & 1;
3271         var->avl = (ar >> 12) & 1;
3272         var->l = (ar >> 13) & 1;
3273         var->db = (ar >> 14) & 1;
3274         var->g = (ar >> 15) & 1;
3275         var->unusable = (ar >> 16) & 1;
3276 }
3277
3278 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3279 {
3280         struct kvm_segment s;
3281
3282         if (to_vmx(vcpu)->rmode.vm86_active) {
3283                 vmx_get_segment(vcpu, &s, seg);
3284                 return s.base;
3285         }
3286         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3287 }
3288
3289 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3290 {
3291         struct vcpu_vmx *vmx = to_vmx(vcpu);
3292
3293         if (!is_protmode(vcpu))
3294                 return 0;
3295
3296         if (!is_long_mode(vcpu)
3297             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3298                 return 3;
3299
3300         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3301                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3302                 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
3303         }
3304
3305         return vmx->cpl;
3306 }
3307
3308
3309 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3310 {
3311         u32 ar;
3312
3313         if (var->unusable || !var->present)
3314                 ar = 1 << 16;
3315         else {
3316                 ar = var->type & 15;
3317                 ar |= (var->s & 1) << 4;
3318                 ar |= (var->dpl & 3) << 5;
3319                 ar |= (var->present & 1) << 7;
3320                 ar |= (var->avl & 1) << 12;
3321                 ar |= (var->l & 1) << 13;
3322                 ar |= (var->db & 1) << 14;
3323                 ar |= (var->g & 1) << 15;
3324         }
3325
3326         return ar;
3327 }
3328
3329 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3330                             struct kvm_segment *var, int seg)
3331 {
3332         struct vcpu_vmx *vmx = to_vmx(vcpu);
3333         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3334
3335         vmx_segment_cache_clear(vmx);
3336         if (seg == VCPU_SREG_CS)
3337                 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3338
3339         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3340                 vmx->rmode.segs[seg] = *var;
3341                 if (seg == VCPU_SREG_TR)
3342                         vmcs_write16(sf->selector, var->selector);
3343                 else if (var->s)
3344                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3345                 goto out;
3346         }
3347
3348         vmcs_writel(sf->base, var->base);
3349         vmcs_write32(sf->limit, var->limit);
3350         vmcs_write16(sf->selector, var->selector);
3351
3352         /*
3353          *   Fix the "Accessed" bit in AR field of segment registers for older
3354          * qemu binaries.
3355          *   IA32 arch specifies that at the time of processor reset the
3356          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3357          * is setting it to 0 in the userland code. This causes invalid guest
3358          * state vmexit when "unrestricted guest" mode is turned on.
3359          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3360          * tree. Newer qemu binaries with that qemu fix would not need this
3361          * kvm hack.
3362          */
3363         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3364                 var->type |= 0x1; /* Accessed */
3365
3366         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3367
3368 out:
3369         vmx->emulation_required |= emulation_required(vcpu);
3370 }
3371
3372 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3373 {
3374         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3375
3376         *db = (ar >> 14) & 1;
3377         *l = (ar >> 13) & 1;
3378 }
3379
3380 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3381 {
3382         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3383         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3384 }
3385
3386 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3387 {
3388         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3389         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3390 }
3391
3392 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3393 {
3394         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3395         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3396 }
3397
3398 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3399 {
3400         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3401         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3402 }
3403
3404 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3405 {
3406         struct kvm_segment var;
3407         u32 ar;
3408
3409         vmx_get_segment(vcpu, &var, seg);
3410         var.dpl = 0x3;
3411         if (seg == VCPU_SREG_CS)
3412                 var.type = 0x3;
3413         ar = vmx_segment_access_rights(&var);
3414
3415         if (var.base != (var.selector << 4))
3416                 return false;
3417         if (var.limit != 0xffff)
3418                 return false;
3419         if (ar != 0xf3)
3420                 return false;
3421
3422         return true;
3423 }
3424
3425 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3426 {
3427         struct kvm_segment cs;
3428         unsigned int cs_rpl;
3429
3430         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3431         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3432
3433         if (cs.unusable)
3434                 return false;
3435         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3436                 return false;
3437         if (!cs.s)
3438                 return false;
3439         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3440                 if (cs.dpl > cs_rpl)
3441                         return false;
3442         } else {
3443                 if (cs.dpl != cs_rpl)
3444                         return false;
3445         }
3446         if (!cs.present)
3447                 return false;
3448
3449         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3450         return true;
3451 }
3452
3453 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3454 {
3455         struct kvm_segment ss;
3456         unsigned int ss_rpl;
3457
3458         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3459         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3460
3461         if (ss.unusable)
3462                 return true;
3463         if (ss.type != 3 && ss.type != 7)
3464                 return false;
3465         if (!ss.s)
3466                 return false;
3467         if (ss.dpl != ss_rpl) /* DPL != RPL */
3468                 return false;
3469         if (!ss.present)
3470                 return false;
3471
3472         return true;
3473 }
3474
3475 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3476 {
3477         struct kvm_segment var;
3478         unsigned int rpl;
3479
3480         vmx_get_segment(vcpu, &var, seg);
3481         rpl = var.selector & SELECTOR_RPL_MASK;
3482
3483         if (var.unusable)
3484                 return true;
3485         if (!var.s)
3486                 return false;
3487         if (!var.present)
3488                 return false;
3489         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3490                 if (var.dpl < rpl) /* DPL < RPL */
3491                         return false;
3492         }
3493
3494         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3495          * rights flags
3496          */
3497         return true;
3498 }
3499
3500 static bool tr_valid(struct kvm_vcpu *vcpu)
3501 {
3502         struct kvm_segment tr;
3503
3504         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3505
3506         if (tr.unusable)
3507                 return false;
3508         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3509                 return false;
3510         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3511                 return false;
3512         if (!tr.present)
3513                 return false;
3514
3515         return true;
3516 }
3517
3518 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3519 {
3520         struct kvm_segment ldtr;
3521
3522         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3523
3524         if (ldtr.unusable)
3525                 return true;
3526         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3527                 return false;
3528         if (ldtr.type != 2)
3529                 return false;
3530         if (!ldtr.present)
3531                 return false;
3532
3533         return true;
3534 }
3535
3536 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3537 {
3538         struct kvm_segment cs, ss;
3539
3540         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3541         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3542
3543         return ((cs.selector & SELECTOR_RPL_MASK) ==
3544                  (ss.selector & SELECTOR_RPL_MASK));
3545 }
3546
3547 /*
3548  * Check if guest state is valid. Returns true if valid, false if
3549  * not.
3550  * We assume that registers are always usable
3551  */
3552 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3553 {
3554         if (enable_unrestricted_guest)
3555                 return true;
3556
3557         /* real mode guest state checks */
3558         if (!is_protmode(vcpu)) {
3559                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3560                         return false;
3561                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3562                         return false;
3563                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3564                         return false;
3565                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3566                         return false;
3567                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3568                         return false;
3569                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3570                         return false;
3571         } else {
3572         /* protected mode guest state checks */
3573                 if (!cs_ss_rpl_check(vcpu))
3574                         return false;
3575                 if (!code_segment_valid(vcpu))
3576                         return false;
3577                 if (!stack_segment_valid(vcpu))
3578                         return false;
3579                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3580                         return false;
3581                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3582                         return false;
3583                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3584                         return false;
3585                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3586                         return false;
3587                 if (!tr_valid(vcpu))
3588                         return false;
3589                 if (!ldtr_valid(vcpu))
3590                         return false;
3591         }
3592         /* TODO:
3593          * - Add checks on RIP
3594          * - Add checks on RFLAGS
3595          */
3596
3597         return true;
3598 }
3599
3600 static int init_rmode_tss(struct kvm *kvm)
3601 {
3602         gfn_t fn;
3603         u16 data = 0;
3604         int r, idx, ret = 0;
3605
3606         idx = srcu_read_lock(&kvm->srcu);
3607         fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3608         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3609         if (r < 0)
3610                 goto out;
3611         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3612         r = kvm_write_guest_page(kvm, fn++, &data,
3613                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3614         if (r < 0)
3615                 goto out;
3616         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3617         if (r < 0)
3618                 goto out;
3619         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3620         if (r < 0)
3621                 goto out;
3622         data = ~0;
3623         r = kvm_write_guest_page(kvm, fn, &data,
3624                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3625                                  sizeof(u8));
3626         if (r < 0)
3627                 goto out;
3628
3629         ret = 1;
3630 out:
3631         srcu_read_unlock(&kvm->srcu, idx);
3632         return ret;
3633 }
3634
3635 static int init_rmode_identity_map(struct kvm *kvm)
3636 {
3637         int i, idx, r, ret;
3638         pfn_t identity_map_pfn;
3639         u32 tmp;
3640
3641         if (!enable_ept)
3642                 return 1;
3643         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3644                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3645                         "haven't been allocated!\n");
3646                 return 0;
3647         }
3648         if (likely(kvm->arch.ept_identity_pagetable_done))
3649                 return 1;
3650         ret = 0;
3651         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3652         idx = srcu_read_lock(&kvm->srcu);
3653         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3654         if (r < 0)
3655                 goto out;
3656         /* Set up identity-mapping pagetable for EPT in real mode */
3657         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3658                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3659                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3660                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3661                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3662                 if (r < 0)
3663                         goto out;
3664         }
3665         kvm->arch.ept_identity_pagetable_done = true;
3666         ret = 1;
3667 out:
3668         srcu_read_unlock(&kvm->srcu, idx);
3669         return ret;
3670 }
3671
3672 static void seg_setup(int seg)
3673 {
3674         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3675         unsigned int ar;
3676
3677         vmcs_write16(sf->selector, 0);
3678         vmcs_writel(sf->base, 0);
3679         vmcs_write32(sf->limit, 0xffff);
3680         ar = 0x93;
3681         if (seg == VCPU_SREG_CS)
3682                 ar |= 0x08; /* code segment */
3683
3684         vmcs_write32(sf->ar_bytes, ar);
3685 }
3686
3687 static int alloc_apic_access_page(struct kvm *kvm)
3688 {
3689         struct page *page;
3690         struct kvm_userspace_memory_region kvm_userspace_mem;
3691         int r = 0;
3692
3693         mutex_lock(&kvm->slots_lock);
3694         if (kvm->arch.apic_access_page)
3695                 goto out;
3696         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3697         kvm_userspace_mem.flags = 0;
3698         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3699         kvm_userspace_mem.memory_size = PAGE_SIZE;
3700         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, false);
3701         if (r)
3702                 goto out;
3703
3704         page = gfn_to_page(kvm, 0xfee00);
3705         if (is_error_page(page)) {
3706                 r = -EFAULT;
3707                 goto out;
3708         }
3709
3710         kvm->arch.apic_access_page = page;
3711 out:
3712         mutex_unlock(&kvm->slots_lock);
3713         return r;
3714 }
3715
3716 static int alloc_identity_pagetable(struct kvm *kvm)
3717 {
3718         struct page *page;
3719         struct kvm_userspace_memory_region kvm_userspace_mem;
3720         int r = 0;
3721
3722         mutex_lock(&kvm->slots_lock);
3723         if (kvm->arch.ept_identity_pagetable)
3724                 goto out;
3725         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3726         kvm_userspace_mem.flags = 0;
3727         kvm_userspace_mem.guest_phys_addr =
3728                 kvm->arch.ept_identity_map_addr;
3729         kvm_userspace_mem.memory_size = PAGE_SIZE;
3730         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, false);
3731         if (r)
3732                 goto out;
3733
3734         page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3735         if (is_error_page(page)) {
3736                 r = -EFAULT;
3737                 goto out;
3738         }
3739
3740         kvm->arch.ept_identity_pagetable = page;
3741 out:
3742         mutex_unlock(&kvm->slots_lock);
3743         return r;
3744 }
3745
3746 static void allocate_vpid(struct vcpu_vmx *vmx)
3747 {
3748         int vpid;
3749
3750         vmx->vpid = 0;
3751         if (!enable_vpid)
3752                 return;
3753         spin_lock(&vmx_vpid_lock);
3754         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3755         if (vpid < VMX_NR_VPIDS) {
3756                 vmx->vpid = vpid;
3757                 __set_bit(vpid, vmx_vpid_bitmap);
3758         }
3759         spin_unlock(&vmx_vpid_lock);
3760 }
3761
3762 static void free_vpid(struct vcpu_vmx *vmx)
3763 {
3764         if (!enable_vpid)
3765                 return;
3766         spin_lock(&vmx_vpid_lock);
3767         if (vmx->vpid != 0)
3768                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3769         spin_unlock(&vmx_vpid_lock);
3770 }
3771
3772 #define MSR_TYPE_R      1
3773 #define MSR_TYPE_W      2
3774 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3775                                                 u32 msr, int type)
3776 {
3777         int f = sizeof(unsigned long);
3778
3779         if (!cpu_has_vmx_msr_bitmap())
3780                 return;
3781
3782         /*
3783          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3784          * have the write-low and read-high bitmap offsets the wrong way round.
3785          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3786          */
3787         if (msr <= 0x1fff) {
3788                 if (type & MSR_TYPE_R)
3789                         /* read-low */
3790                         __clear_bit(msr, msr_bitmap + 0x000 / f);
3791
3792                 if (type & MSR_TYPE_W)
3793                         /* write-low */
3794                         __clear_bit(msr, msr_bitmap + 0x800 / f);
3795
3796         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3797                 msr &= 0x1fff;
3798                 if (type & MSR_TYPE_R)
3799                         /* read-high */
3800                         __clear_bit(msr, msr_bitmap + 0x400 / f);
3801
3802                 if (type & MSR_TYPE_W)
3803                         /* write-high */
3804                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
3805
3806         }
3807 }
3808
3809 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3810                                                 u32 msr, int type)
3811 {
3812         int f = sizeof(unsigned long);
3813
3814         if (!cpu_has_vmx_msr_bitmap())
3815                 return;
3816
3817         /*
3818          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3819          * have the write-low and read-high bitmap offsets the wrong way round.
3820          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3821          */
3822         if (msr <= 0x1fff) {
3823                 if (type & MSR_TYPE_R)
3824                         /* read-low */
3825                         __set_bit(msr, msr_bitmap + 0x000 / f);
3826
3827                 if (type & MSR_TYPE_W)
3828                         /* write-low */
3829                         __set_bit(msr, msr_bitmap + 0x800 / f);
3830
3831         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3832                 msr &= 0x1fff;
3833                 if (type & MSR_TYPE_R)
3834                         /* read-high */
3835                         __set_bit(msr, msr_bitmap + 0x400 / f);
3836
3837                 if (type & MSR_TYPE_W)
3838                         /* write-high */
3839                         __set_bit(msr, msr_bitmap + 0xc00 / f);
3840
3841         }
3842 }
3843
3844 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3845 {
3846         if (!longmode_only)
3847                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
3848                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
3849         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
3850                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
3851 }
3852
3853 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
3854 {
3855         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3856                         msr, MSR_TYPE_R);
3857         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
3858                         msr, MSR_TYPE_R);
3859 }
3860
3861 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
3862 {
3863         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3864                         msr, MSR_TYPE_R);
3865         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
3866                         msr, MSR_TYPE_R);
3867 }
3868
3869 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
3870 {
3871         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3872                         msr, MSR_TYPE_W);
3873         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
3874                         msr, MSR_TYPE_W);
3875 }
3876
3877 /*
3878  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3879  * will not change in the lifetime of the guest.
3880  * Note that host-state that does change is set elsewhere. E.g., host-state
3881  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3882  */
3883 static void vmx_set_constant_host_state(void)
3884 {
3885         u32 low32, high32;
3886         unsigned long tmpl;
3887         struct desc_ptr dt;
3888
3889         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
3890         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
3891         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
3892
3893         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
3894 #ifdef CONFIG_X86_64
3895         /*
3896          * Load null selectors, so we can avoid reloading them in
3897          * __vmx_load_host_state(), in case userspace uses the null selectors
3898          * too (the expected case).
3899          */
3900         vmcs_write16(HOST_DS_SELECTOR, 0);
3901         vmcs_write16(HOST_ES_SELECTOR, 0);
3902 #else
3903         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3904         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3905 #endif
3906         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3907         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
3908
3909         native_store_idt(&dt);
3910         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
3911
3912         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
3913
3914         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3915         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3916         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3917         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
3918
3919         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3920                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3921                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3922         }
3923 }
3924
3925 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3926 {
3927         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3928         if (enable_ept)
3929                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3930         if (is_guest_mode(&vmx->vcpu))
3931                 vmx->vcpu.arch.cr4_guest_owned_bits &=
3932                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3933         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3934 }
3935
3936 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3937 {
3938         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3939         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3940                 exec_control &= ~CPU_BASED_TPR_SHADOW;
3941 #ifdef CONFIG_X86_64
3942                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3943                                 CPU_BASED_CR8_LOAD_EXITING;
3944 #endif
3945         }
3946         if (!enable_ept)
3947                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3948                                 CPU_BASED_CR3_LOAD_EXITING  |
3949                                 CPU_BASED_INVLPG_EXITING;
3950         return exec_control;
3951 }
3952
3953 static int vmx_vm_has_apicv(struct kvm *kvm)
3954 {
3955         return enable_apicv_reg_vid && irqchip_in_kernel(kvm);
3956 }
3957
3958 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3959 {
3960         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3961         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3962                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3963         if (vmx->vpid == 0)
3964                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3965         if (!enable_ept) {
3966                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3967                 enable_unrestricted_guest = 0;
3968                 /* Enable INVPCID for non-ept guests may cause performance regression. */
3969                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
3970         }
3971         if (!enable_unrestricted_guest)
3972                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3973         if (!ple_gap)
3974                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3975         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
3976                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
3977                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3978         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
3979         return exec_control;
3980 }
3981
3982 static void ept_set_mmio_spte_mask(void)
3983 {
3984         /*
3985          * EPT Misconfigurations can be generated if the value of bits 2:0
3986          * of an EPT paging-structure entry is 110b (write/execute).
3987          * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3988          * spte.
3989          */
3990         kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3991 }
3992
3993 /*
3994  * Sets up the vmcs for emulated real mode.
3995  */
3996 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
3997 {
3998 #ifdef CONFIG_X86_64
3999         unsigned long a;
4000 #endif
4001         int i;
4002
4003         /* I/O */
4004         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4005         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4006
4007         if (cpu_has_vmx_msr_bitmap())
4008                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4009
4010         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4011
4012         /* Control */
4013         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
4014                 vmcs_config.pin_based_exec_ctrl);
4015
4016         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4017
4018         if (cpu_has_secondary_exec_ctrls()) {
4019                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4020                                 vmx_secondary_exec_control(vmx));
4021         }
4022
4023         if (enable_apicv_reg_vid) {
4024                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4025                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4026                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4027                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4028
4029                 vmcs_write16(GUEST_INTR_STATUS, 0);
4030         }
4031
4032         if (ple_gap) {
4033                 vmcs_write32(PLE_GAP, ple_gap);
4034                 vmcs_write32(PLE_WINDOW, ple_window);
4035         }
4036
4037         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4038         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4039         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4040
4041         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4042         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4043         vmx_set_constant_host_state();
4044 #ifdef CONFIG_X86_64
4045         rdmsrl(MSR_FS_BASE, a);
4046         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4047         rdmsrl(MSR_GS_BASE, a);
4048         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4049 #else
4050         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4051         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4052 #endif
4053
4054         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4055         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4056         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4057         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4058         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4059
4060         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4061                 u32 msr_low, msr_high;
4062                 u64 host_pat;
4063                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4064                 host_pat = msr_low | ((u64) msr_high << 32);
4065                 /* Write the default value follow host pat */
4066                 vmcs_write64(GUEST_IA32_PAT, host_pat);
4067                 /* Keep arch.pat sync with GUEST_IA32_PAT */
4068                 vmx->vcpu.arch.pat = host_pat;
4069         }
4070
4071         for (i = 0; i < NR_VMX_MSR; ++i) {
4072                 u32 index = vmx_msr_index[i];
4073                 u32 data_low, data_high;
4074                 int j = vmx->nmsrs;
4075
4076                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4077                         continue;
4078                 if (wrmsr_safe(index, data_low, data_high) < 0)
4079                         continue;
4080                 vmx->guest_msrs[j].index = i;
4081                 vmx->guest_msrs[j].data = 0;
4082                 vmx->guest_msrs[j].mask = -1ull;
4083                 ++vmx->nmsrs;
4084         }
4085
4086         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
4087
4088         /* 22.2.1, 20.8.1 */
4089         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
4090
4091         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4092         set_cr4_guest_host_mask(vmx);
4093
4094         return 0;
4095 }
4096
4097 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4098 {
4099         struct vcpu_vmx *vmx = to_vmx(vcpu);
4100         u64 msr;
4101         int ret;
4102
4103         vmx->rmode.vm86_active = 0;
4104
4105         vmx->soft_vnmi_blocked = 0;
4106
4107         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4108         kvm_set_cr8(&vmx->vcpu, 0);
4109         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
4110         if (kvm_vcpu_is_bsp(&vmx->vcpu))
4111                 msr |= MSR_IA32_APICBASE_BSP;
4112         kvm_set_apic_base(&vmx->vcpu, msr);
4113
4114         vmx_segment_cache_clear(vmx);
4115
4116         seg_setup(VCPU_SREG_CS);
4117         if (kvm_vcpu_is_bsp(&vmx->vcpu))
4118                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4119         else {
4120                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
4121                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
4122         }
4123
4124         seg_setup(VCPU_SREG_DS);
4125         seg_setup(VCPU_SREG_ES);
4126         seg_setup(VCPU_SREG_FS);
4127         seg_setup(VCPU_SREG_GS);
4128         seg_setup(VCPU_SREG_SS);
4129
4130         vmcs_write16(GUEST_TR_SELECTOR, 0);
4131         vmcs_writel(GUEST_TR_BASE, 0);
4132         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4133         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4134
4135         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4136         vmcs_writel(GUEST_LDTR_BASE, 0);
4137         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4138         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4139
4140         vmcs_write32(GUEST_SYSENTER_CS, 0);
4141         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4142         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4143
4144         vmcs_writel(GUEST_RFLAGS, 0x02);
4145         if (kvm_vcpu_is_bsp(&vmx->vcpu))
4146                 kvm_rip_write(vcpu, 0xfff0);
4147         else
4148                 kvm_rip_write(vcpu, 0);
4149
4150         vmcs_writel(GUEST_GDTR_BASE, 0);
4151         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4152
4153         vmcs_writel(GUEST_IDTR_BASE, 0);
4154         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4155
4156         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4157         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4158         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4159
4160         /* Special registers */
4161         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4162
4163         setup_msrs(vmx);
4164
4165         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4166
4167         if (cpu_has_vmx_tpr_shadow()) {
4168                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4169                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4170                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4171                                      __pa(vmx->vcpu.arch.apic->regs));
4172                 vmcs_write32(TPR_THRESHOLD, 0);
4173         }
4174
4175         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4176                 vmcs_write64(APIC_ACCESS_ADDR,
4177                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
4178
4179         if (vmx->vpid != 0)
4180                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4181
4182         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4183         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
4184         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4185         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
4186         vmx_set_cr4(&vmx->vcpu, 0);
4187         vmx_set_efer(&vmx->vcpu, 0);
4188         vmx_fpu_activate(&vmx->vcpu);
4189         update_exception_bitmap(&vmx->vcpu);
4190
4191         vpid_sync_context(vmx);
4192
4193         ret = 0;
4194
4195         return ret;
4196 }
4197
4198 /*
4199  * In nested virtualization, check if L1 asked to exit on external interrupts.
4200  * For most existing hypervisors, this will always return true.
4201  */
4202 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4203 {
4204         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4205                 PIN_BASED_EXT_INTR_MASK;
4206 }
4207
4208 static void enable_irq_window(struct kvm_vcpu *vcpu)
4209 {
4210         u32 cpu_based_vm_exec_control;
4211         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4212                 /*
4213                  * We get here if vmx_interrupt_allowed() said we can't
4214                  * inject to L1 now because L2 must run. Ask L2 to exit
4215                  * right after entry, so we can inject to L1 more promptly.
4216                  */
4217                 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
4218                 return;
4219         }
4220
4221         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4222         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4223         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4224 }
4225
4226 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4227 {
4228         u32 cpu_based_vm_exec_control;
4229
4230         if (!cpu_has_virtual_nmis()) {
4231                 enable_irq_window(vcpu);
4232                 return;
4233         }
4234
4235         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4236                 enable_irq_window(vcpu);
4237                 return;
4238         }
4239         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4240         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4241         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4242 }
4243
4244 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4245 {
4246         struct vcpu_vmx *vmx = to_vmx(vcpu);
4247         uint32_t intr;
4248         int irq = vcpu->arch.interrupt.nr;
4249
4250         trace_kvm_inj_virq(irq);
4251
4252         ++vcpu->stat.irq_injections;
4253         if (vmx->rmode.vm86_active) {
4254                 int inc_eip = 0;
4255                 if (vcpu->arch.interrupt.soft)
4256                         inc_eip = vcpu->arch.event_exit_inst_len;
4257                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4258                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4259                 return;
4260         }
4261         intr = irq | INTR_INFO_VALID_MASK;
4262         if (vcpu->arch.interrupt.soft) {
4263                 intr |= INTR_TYPE_SOFT_INTR;
4264                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4265                              vmx->vcpu.arch.event_exit_inst_len);
4266         } else
4267                 intr |= INTR_TYPE_EXT_INTR;
4268         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4269 }
4270
4271 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4272 {
4273         struct vcpu_vmx *vmx = to_vmx(vcpu);
4274
4275         if (is_guest_mode(vcpu))
4276                 return;
4277
4278         if (!cpu_has_virtual_nmis()) {
4279                 /*
4280                  * Tracking the NMI-blocked state in software is built upon
4281                  * finding the next open IRQ window. This, in turn, depends on
4282                  * well-behaving guests: They have to keep IRQs disabled at
4283                  * least as long as the NMI handler runs. Otherwise we may
4284                  * cause NMI nesting, maybe breaking the guest. But as this is
4285                  * highly unlikely, we can live with the residual risk.
4286                  */
4287                 vmx->soft_vnmi_blocked = 1;
4288                 vmx->vnmi_blocked_time = 0;
4289         }
4290
4291         ++vcpu->stat.nmi_injections;
4292         vmx->nmi_known_unmasked = false;
4293         if (vmx->rmode.vm86_active) {
4294                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4295                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4296                 return;
4297         }
4298         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4299                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4300 }
4301
4302 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4303 {
4304         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4305                 return 0;
4306
4307         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4308                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4309                    | GUEST_INTR_STATE_NMI));
4310 }
4311
4312 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4313 {
4314         if (!cpu_has_virtual_nmis())
4315                 return to_vmx(vcpu)->soft_vnmi_blocked;
4316         if (to_vmx(vcpu)->nmi_known_unmasked)
4317                 return false;
4318         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4319 }
4320
4321 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4322 {
4323         struct vcpu_vmx *vmx = to_vmx(vcpu);
4324
4325         if (!cpu_has_virtual_nmis()) {
4326                 if (vmx->soft_vnmi_blocked != masked) {
4327                         vmx->soft_vnmi_blocked = masked;
4328                         vmx->vnmi_blocked_time = 0;
4329                 }
4330         } else {
4331                 vmx->nmi_known_unmasked = !masked;
4332                 if (masked)
4333                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4334                                       GUEST_INTR_STATE_NMI);
4335                 else
4336                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4337                                         GUEST_INTR_STATE_NMI);
4338         }
4339 }
4340
4341 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4342 {
4343         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4344                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4345                 if (to_vmx(vcpu)->nested.nested_run_pending ||
4346                     (vmcs12->idt_vectoring_info_field &
4347                      VECTORING_INFO_VALID_MASK))
4348                         return 0;
4349                 nested_vmx_vmexit(vcpu);
4350                 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4351                 vmcs12->vm_exit_intr_info = 0;
4352                 /* fall through to normal code, but now in L1, not L2 */
4353         }
4354
4355         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4356                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4357                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4358 }
4359
4360 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4361 {
4362         int ret;
4363         struct kvm_userspace_memory_region tss_mem = {
4364                 .slot = TSS_PRIVATE_MEMSLOT,
4365                 .guest_phys_addr = addr,
4366                 .memory_size = PAGE_SIZE * 3,
4367                 .flags = 0,
4368         };
4369
4370         ret = kvm_set_memory_region(kvm, &tss_mem, false);
4371         if (ret)
4372                 return ret;
4373         kvm->arch.tss_addr = addr;
4374         if (!init_rmode_tss(kvm))
4375                 return  -ENOMEM;
4376
4377         return 0;
4378 }
4379
4380 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4381 {
4382         switch (vec) {
4383         case BP_VECTOR:
4384                 /*
4385                  * Update instruction length as we may reinject the exception
4386                  * from user space while in guest debugging mode.
4387                  */
4388                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4389                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4390                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4391                         return false;
4392                 /* fall through */
4393         case DB_VECTOR:
4394                 if (vcpu->guest_debug &
4395                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4396                         return false;
4397                 /* fall through */
4398         case DE_VECTOR:
4399         case OF_VECTOR:
4400         case BR_VECTOR:
4401         case UD_VECTOR:
4402         case DF_VECTOR:
4403         case SS_VECTOR:
4404         case GP_VECTOR:
4405         case MF_VECTOR:
4406                 return true;
4407         break;
4408         }
4409         return false;
4410 }
4411
4412 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4413                                   int vec, u32 err_code)
4414 {
4415         /*
4416          * Instruction with address size override prefix opcode 0x67
4417          * Cause the #SS fault with 0 error code in VM86 mode.
4418          */
4419         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4420                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4421                         if (vcpu->arch.halt_request) {
4422                                 vcpu->arch.halt_request = 0;
4423                                 return kvm_emulate_halt(vcpu);
4424                         }
4425                         return 1;
4426                 }
4427                 return 0;
4428         }
4429
4430         /*
4431          * Forward all other exceptions that are valid in real mode.
4432          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4433          *        the required debugging infrastructure rework.
4434          */
4435         kvm_queue_exception(vcpu, vec);
4436         return 1;
4437 }
4438
4439 /*
4440  * Trigger machine check on the host. We assume all the MSRs are already set up
4441  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4442  * We pass a fake environment to the machine check handler because we want
4443  * the guest to be always treated like user space, no matter what context
4444  * it used internally.
4445  */
4446 static void kvm_machine_check(void)
4447 {
4448 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4449         struct pt_regs regs = {
4450                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4451                 .flags = X86_EFLAGS_IF,
4452         };
4453
4454         do_machine_check(&regs, 0);
4455 #endif
4456 }
4457
4458 static int handle_machine_check(struct kvm_vcpu *vcpu)
4459 {
4460         /* already handled by vcpu_run */
4461         return 1;
4462 }
4463
4464 static int handle_exception(struct kvm_vcpu *vcpu)
4465 {
4466         struct vcpu_vmx *vmx = to_vmx(vcpu);
4467         struct kvm_run *kvm_run = vcpu->run;
4468         u32 intr_info, ex_no, error_code;
4469         unsigned long cr2, rip, dr6;
4470         u32 vect_info;
4471         enum emulation_result er;
4472
4473         vect_info = vmx->idt_vectoring_info;
4474         intr_info = vmx->exit_intr_info;
4475
4476         if (is_machine_check(intr_info))
4477                 return handle_machine_check(vcpu);
4478
4479         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4480                 return 1;  /* already handled by vmx_vcpu_run() */
4481
4482         if (is_no_device(intr_info)) {
4483                 vmx_fpu_activate(vcpu);
4484                 return 1;
4485         }
4486
4487         if (is_invalid_opcode(intr_info)) {
4488                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4489                 if (er != EMULATE_DONE)
4490                         kvm_queue_exception(vcpu, UD_VECTOR);
4491                 return 1;
4492         }
4493
4494         error_code = 0;
4495         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4496                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4497
4498         /*
4499          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4500          * MMIO, it is better to report an internal error.
4501          * See the comments in vmx_handle_exit.
4502          */
4503         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4504             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4505                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4506                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4507                 vcpu->run->internal.ndata = 2;
4508                 vcpu->run->internal.data[0] = vect_info;
4509                 vcpu->run->internal.data[1] = intr_info;
4510                 return 0;
4511         }
4512
4513         if (is_page_fault(intr_info)) {
4514                 /* EPT won't cause page fault directly */
4515                 BUG_ON(enable_ept);
4516                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4517                 trace_kvm_page_fault(cr2, error_code);
4518
4519                 if (kvm_event_needs_reinjection(vcpu))
4520                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4521                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4522         }
4523
4524         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4525
4526         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4527                 return handle_rmode_exception(vcpu, ex_no, error_code);
4528
4529         switch (ex_no) {
4530         case DB_VECTOR:
4531                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4532                 if (!(vcpu->guest_debug &
4533                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4534                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4535                         kvm_queue_exception(vcpu, DB_VECTOR);
4536                         return 1;
4537                 }
4538                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4539                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4540                 /* fall through */
4541         case BP_VECTOR:
4542                 /*
4543                  * Update instruction length as we may reinject #BP from
4544                  * user space while in guest debugging mode. Reading it for
4545                  * #DB as well causes no harm, it is not used in that case.
4546                  */
4547                 vmx->vcpu.arch.event_exit_inst_len =
4548                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4549                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4550                 rip = kvm_rip_read(vcpu);
4551                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4552                 kvm_run->debug.arch.exception = ex_no;
4553                 break;
4554         default:
4555                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4556                 kvm_run->ex.exception = ex_no;
4557                 kvm_run->ex.error_code = error_code;
4558                 break;
4559         }
4560         return 0;
4561 }
4562
4563 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4564 {
4565         ++vcpu->stat.irq_exits;
4566         return 1;
4567 }
4568
4569 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4570 {
4571         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4572         return 0;
4573 }
4574
4575 static int handle_io(struct kvm_vcpu *vcpu)
4576 {
4577         unsigned long exit_qualification;
4578         int size, in, string;
4579         unsigned port;
4580
4581         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4582         string = (exit_qualification & 16) != 0;
4583         in = (exit_qualification & 8) != 0;
4584
4585         ++vcpu->stat.io_exits;
4586
4587         if (string || in)
4588                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4589
4590         port = exit_qualification >> 16;
4591         size = (exit_qualification & 7) + 1;
4592         skip_emulated_instruction(vcpu);
4593
4594         return kvm_fast_pio_out(vcpu, size, port);
4595 }
4596
4597 static void
4598 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4599 {
4600         /*
4601          * Patch in the VMCALL instruction:
4602          */
4603         hypercall[0] = 0x0f;
4604         hypercall[1] = 0x01;
4605         hypercall[2] = 0xc1;
4606 }
4607
4608 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4609 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4610 {
4611         if (to_vmx(vcpu)->nested.vmxon &&
4612             ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4613                 return 1;
4614
4615         if (is_guest_mode(vcpu)) {
4616                 /*
4617                  * We get here when L2 changed cr0 in a way that did not change
4618                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4619                  * but did change L0 shadowed bits. This can currently happen
4620                  * with the TS bit: L0 may want to leave TS on (for lazy fpu
4621                  * loading) while pretending to allow the guest to change it.
4622                  */
4623                 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4624                          (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4625                         return 1;
4626                 vmcs_writel(CR0_READ_SHADOW, val);
4627                 return 0;
4628         } else
4629                 return kvm_set_cr0(vcpu, val);
4630 }
4631
4632 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4633 {
4634         if (is_guest_mode(vcpu)) {
4635                 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4636                          (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4637                         return 1;
4638                 vmcs_writel(CR4_READ_SHADOW, val);
4639                 return 0;
4640         } else
4641                 return kvm_set_cr4(vcpu, val);
4642 }
4643
4644 /* called to set cr0 as approriate for clts instruction exit. */
4645 static void handle_clts(struct kvm_vcpu *vcpu)
4646 {
4647         if (is_guest_mode(vcpu)) {
4648                 /*
4649                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4650                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4651                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4652                  */
4653                 vmcs_writel(CR0_READ_SHADOW,
4654                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4655                 vcpu->arch.cr0 &= ~X86_CR0_TS;
4656         } else
4657                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4658 }
4659
4660 static int handle_cr(struct kvm_vcpu *vcpu)
4661 {
4662         unsigned long exit_qualification, val;
4663         int cr;
4664         int reg;
4665         int err;
4666
4667         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4668         cr = exit_qualification & 15;
4669         reg = (exit_qualification >> 8) & 15;
4670         switch ((exit_qualification >> 4) & 3) {
4671         case 0: /* mov to cr */
4672                 val = kvm_register_read(vcpu, reg);
4673                 trace_kvm_cr_write(cr, val);
4674                 switch (cr) {
4675                 case 0:
4676                         err = handle_set_cr0(vcpu, val);
4677                         kvm_complete_insn_gp(vcpu, err);
4678                         return 1;
4679                 case 3:
4680                         err = kvm_set_cr3(vcpu, val);
4681                         kvm_complete_insn_gp(vcpu, err);
4682                         return 1;
4683                 case 4:
4684                         err = handle_set_cr4(vcpu, val);
4685                         kvm_complete_insn_gp(vcpu, err);
4686                         return 1;
4687                 case 8: {
4688                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4689                                 u8 cr8 = kvm_register_read(vcpu, reg);
4690                                 err = kvm_set_cr8(vcpu, cr8);
4691                                 kvm_complete_insn_gp(vcpu, err);
4692                                 if (irqchip_in_kernel(vcpu->kvm))
4693                                         return 1;
4694                                 if (cr8_prev <= cr8)
4695                                         return 1;
4696                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4697                                 return 0;
4698                         }
4699                 }
4700                 break;
4701         case 2: /* clts */
4702                 handle_clts(vcpu);
4703                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4704                 skip_emulated_instruction(vcpu);
4705                 vmx_fpu_activate(vcpu);
4706                 return 1;
4707         case 1: /*mov from cr*/
4708                 switch (cr) {
4709                 case 3:
4710                         val = kvm_read_cr3(vcpu);
4711                         kvm_register_write(vcpu, reg, val);
4712                         trace_kvm_cr_read(cr, val);
4713                         skip_emulated_instruction(vcpu);
4714                         return 1;
4715                 case 8:
4716                         val = kvm_get_cr8(vcpu);
4717                         kvm_register_write(vcpu, reg, val);
4718                         trace_kvm_cr_read(cr, val);
4719                         skip_emulated_instruction(vcpu);
4720                         return 1;
4721                 }
4722                 break;
4723         case 3: /* lmsw */
4724                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4725                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4726                 kvm_lmsw(vcpu, val);
4727
4728                 skip_emulated_instruction(vcpu);
4729                 return 1;
4730         default:
4731                 break;
4732         }
4733         vcpu->run->exit_reason = 0;
4734         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4735                (int)(exit_qualification >> 4) & 3, cr);
4736         return 0;
4737 }
4738
4739 static int handle_dr(struct kvm_vcpu *vcpu)
4740 {
4741         unsigned long exit_qualification;
4742         int dr, reg;
4743
4744         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4745         if (!kvm_require_cpl(vcpu, 0))
4746                 return 1;
4747         dr = vmcs_readl(GUEST_DR7);
4748         if (dr & DR7_GD) {
4749                 /*
4750                  * As the vm-exit takes precedence over the debug trap, we
4751                  * need to emulate the latter, either for the host or the
4752                  * guest debugging itself.
4753                  */
4754                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4755                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4756                         vcpu->run->debug.arch.dr7 = dr;
4757                         vcpu->run->debug.arch.pc =
4758                                 vmcs_readl(GUEST_CS_BASE) +
4759                                 vmcs_readl(GUEST_RIP);
4760                         vcpu->run->debug.arch.exception = DB_VECTOR;
4761                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4762                         return 0;
4763                 } else {
4764                         vcpu->arch.dr7 &= ~DR7_GD;
4765                         vcpu->arch.dr6 |= DR6_BD;
4766                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4767                         kvm_queue_exception(vcpu, DB_VECTOR);
4768                         return 1;
4769                 }
4770         }
4771
4772         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4773         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4774         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4775         if (exit_qualification & TYPE_MOV_FROM_DR) {
4776                 unsigned long val;
4777                 if (!kvm_get_dr(vcpu, dr, &val))
4778                         kvm_register_write(vcpu, reg, val);
4779         } else
4780                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4781         skip_emulated_instruction(vcpu);
4782         return 1;
4783 }
4784
4785 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4786 {
4787         vmcs_writel(GUEST_DR7, val);
4788 }
4789
4790 static int handle_cpuid(struct kvm_vcpu *vcpu)
4791 {
4792         kvm_emulate_cpuid(vcpu);
4793         return 1;
4794 }
4795
4796 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4797 {
4798         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4799         u64 data;
4800
4801         if (vmx_get_msr(vcpu, ecx, &data)) {
4802                 trace_kvm_msr_read_ex(ecx);
4803                 kvm_inject_gp(vcpu, 0);
4804                 return 1;
4805         }
4806
4807         trace_kvm_msr_read(ecx, data);
4808
4809         /* FIXME: handling of bits 32:63 of rax, rdx */
4810         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4811         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4812         skip_emulated_instruction(vcpu);
4813         return 1;
4814 }
4815
4816 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4817 {
4818         struct msr_data msr;
4819         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4820         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4821                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4822
4823         msr.data = data;
4824         msr.index = ecx;
4825         msr.host_initiated = false;
4826         if (vmx_set_msr(vcpu, &msr) != 0) {
4827                 trace_kvm_msr_write_ex(ecx, data);
4828                 kvm_inject_gp(vcpu, 0);
4829                 return 1;
4830         }
4831
4832         trace_kvm_msr_write(ecx, data);
4833         skip_emulated_instruction(vcpu);
4834         return 1;
4835 }
4836
4837 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4838 {
4839         kvm_make_request(KVM_REQ_EVENT, vcpu);
4840         return 1;
4841 }
4842
4843 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4844 {
4845         u32 cpu_based_vm_exec_control;
4846
4847         /* clear pending irq */
4848         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4849         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4850         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4851
4852         kvm_make_request(KVM_REQ_EVENT, vcpu);
4853
4854         ++vcpu->stat.irq_window_exits;
4855
4856         /*
4857          * If the user space waits to inject interrupts, exit as soon as
4858          * possible
4859          */
4860         if (!irqchip_in_kernel(vcpu->kvm) &&
4861             vcpu->run->request_interrupt_window &&
4862             !kvm_cpu_has_interrupt(vcpu)) {
4863                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4864                 return 0;
4865         }
4866         return 1;
4867 }
4868
4869 static int handle_halt(struct kvm_vcpu *vcpu)
4870 {
4871         skip_emulated_instruction(vcpu);
4872         return kvm_emulate_halt(vcpu);
4873 }
4874
4875 static int handle_vmcall(struct kvm_vcpu *vcpu)
4876 {
4877         skip_emulated_instruction(vcpu);
4878         kvm_emulate_hypercall(vcpu);
4879         return 1;
4880 }
4881
4882 static int handle_invd(struct kvm_vcpu *vcpu)
4883 {
4884         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4885 }
4886
4887 static int handle_invlpg(struct kvm_vcpu *vcpu)
4888 {
4889         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4890
4891         kvm_mmu_invlpg(vcpu, exit_qualification);
4892         skip_emulated_instruction(vcpu);
4893         return 1;
4894 }
4895
4896 static int handle_rdpmc(struct kvm_vcpu *vcpu)
4897 {
4898         int err;
4899
4900         err = kvm_rdpmc(vcpu);
4901         kvm_complete_insn_gp(vcpu, err);
4902
4903         return 1;
4904 }
4905
4906 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4907 {
4908         skip_emulated_instruction(vcpu);
4909         kvm_emulate_wbinvd(vcpu);
4910         return 1;
4911 }
4912
4913 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4914 {
4915         u64 new_bv = kvm_read_edx_eax(vcpu);
4916         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4917
4918         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4919                 skip_emulated_instruction(vcpu);
4920         return 1;
4921 }
4922
4923 static int handle_apic_access(struct kvm_vcpu *vcpu)
4924 {
4925         if (likely(fasteoi)) {
4926                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4927                 int access_type, offset;
4928
4929                 access_type = exit_qualification & APIC_ACCESS_TYPE;
4930                 offset = exit_qualification & APIC_ACCESS_OFFSET;
4931                 /*
4932                  * Sane guest uses MOV to write EOI, with written value
4933                  * not cared. So make a short-circuit here by avoiding
4934                  * heavy instruction emulation.
4935                  */
4936                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4937                     (offset == APIC_EOI)) {
4938                         kvm_lapic_set_eoi(vcpu);
4939                         skip_emulated_instruction(vcpu);
4940                         return 1;
4941                 }
4942         }
4943         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4944 }
4945
4946 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
4947 {
4948         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4949         int vector = exit_qualification & 0xff;
4950
4951         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
4952         kvm_apic_set_eoi_accelerated(vcpu, vector);
4953         return 1;
4954 }
4955
4956 static int handle_apic_write(struct kvm_vcpu *vcpu)
4957 {
4958         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4959         u32 offset = exit_qualification & 0xfff;
4960
4961         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
4962         kvm_apic_write_nodecode(vcpu, offset);
4963         return 1;
4964 }
4965
4966 static int handle_task_switch(struct kvm_vcpu *vcpu)
4967 {
4968         struct vcpu_vmx *vmx = to_vmx(vcpu);
4969         unsigned long exit_qualification;
4970         bool has_error_code = false;
4971         u32 error_code = 0;
4972         u16 tss_selector;
4973         int reason, type, idt_v, idt_index;
4974
4975         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4976         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
4977         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
4978
4979         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4980
4981         reason = (u32)exit_qualification >> 30;
4982         if (reason == TASK_SWITCH_GATE && idt_v) {
4983                 switch (type) {
4984                 case INTR_TYPE_NMI_INTR:
4985                         vcpu->arch.nmi_injected = false;
4986                         vmx_set_nmi_mask(vcpu, true);
4987                         break;
4988                 case INTR_TYPE_EXT_INTR:
4989                 case INTR_TYPE_SOFT_INTR:
4990                         kvm_clear_interrupt_queue(vcpu);
4991                         break;
4992                 case INTR_TYPE_HARD_EXCEPTION:
4993                         if (vmx->idt_vectoring_info &
4994                             VECTORING_INFO_DELIVER_CODE_MASK) {
4995                                 has_error_code = true;
4996                                 error_code =
4997                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
4998                         }
4999                         /* fall through */
5000                 case INTR_TYPE_SOFT_EXCEPTION:
5001                         kvm_clear_exception_queue(vcpu);
5002                         break;
5003                 default:
5004                         break;
5005                 }
5006         }
5007         tss_selector = exit_qualification;
5008
5009         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5010                        type != INTR_TYPE_EXT_INTR &&
5011                        type != INTR_TYPE_NMI_INTR))
5012                 skip_emulated_instruction(vcpu);
5013
5014         if (kvm_task_switch(vcpu, tss_selector,
5015                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5016                             has_error_code, error_code) == EMULATE_FAIL) {
5017                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5018                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5019                 vcpu->run->internal.ndata = 0;
5020                 return 0;
5021         }
5022
5023         /* clear all local breakpoint enable flags */
5024         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5025
5026         /*
5027          * TODO: What about debug traps on tss switch?
5028          *       Are we supposed to inject them and update dr6?
5029          */
5030
5031         return 1;
5032 }
5033
5034 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5035 {
5036         unsigned long exit_qualification;
5037         gpa_t gpa;
5038         u32 error_code;
5039         int gla_validity;
5040
5041         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5042
5043         gla_validity = (exit_qualification >> 7) & 0x3;
5044         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5045                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5046                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5047                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5048                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5049                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5050                         (long unsigned int)exit_qualification);
5051                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5052                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5053                 return 0;
5054         }
5055
5056         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5057         trace_kvm_page_fault(gpa, exit_qualification);
5058
5059         /* It is a write fault? */
5060         error_code = exit_qualification & (1U << 1);
5061         /* ept page table is present? */
5062         error_code |= (exit_qualification >> 3) & 0x1;
5063
5064         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5065 }
5066
5067 static u64 ept_rsvd_mask(u64 spte, int level)
5068 {
5069         int i;
5070         u64 mask = 0;
5071
5072         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5073                 mask |= (1ULL << i);
5074
5075         if (level > 2)
5076                 /* bits 7:3 reserved */
5077                 mask |= 0xf8;
5078         else if (level == 2) {
5079                 if (spte & (1ULL << 7))
5080                         /* 2MB ref, bits 20:12 reserved */
5081                         mask |= 0x1ff000;
5082                 else
5083                         /* bits 6:3 reserved */
5084                         mask |= 0x78;
5085         }
5086
5087         return mask;
5088 }
5089
5090 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5091                                        int level)
5092 {
5093         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5094
5095         /* 010b (write-only) */
5096         WARN_ON((spte & 0x7) == 0x2);
5097
5098         /* 110b (write/execute) */
5099         WARN_ON((spte & 0x7) == 0x6);
5100
5101         /* 100b (execute-only) and value not supported by logical processor */
5102         if (!cpu_has_vmx_ept_execute_only())
5103                 WARN_ON((spte & 0x7) == 0x4);
5104
5105         /* not 000b */
5106         if ((spte & 0x7)) {
5107                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5108
5109                 if (rsvd_bits != 0) {
5110                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5111                                          __func__, rsvd_bits);
5112                         WARN_ON(1);
5113                 }
5114
5115                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5116                         u64 ept_mem_type = (spte & 0x38) >> 3;
5117
5118                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
5119                             ept_mem_type == 7) {
5120                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5121                                                 __func__, ept_mem_type);
5122                                 WARN_ON(1);
5123                         }
5124                 }
5125         }
5126 }
5127
5128 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5129 {
5130         u64 sptes[4];
5131         int nr_sptes, i, ret;
5132         gpa_t gpa;
5133
5134         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5135
5136         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5137         if (likely(ret == 1))
5138                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5139                                               EMULATE_DONE;
5140         if (unlikely(!ret))
5141                 return 1;
5142
5143         /* It is the real ept misconfig */
5144         printk(KERN_ERR "EPT: Misconfiguration.\n");
5145         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5146
5147         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5148
5149         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5150                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5151
5152         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5153         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5154
5155         return 0;
5156 }
5157
5158 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5159 {
5160         u32 cpu_based_vm_exec_control;
5161
5162         /* clear pending NMI */
5163         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5164         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5165         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5166         ++vcpu->stat.nmi_window_exits;
5167         kvm_make_request(KVM_REQ_EVENT, vcpu);
5168
5169         return 1;
5170 }
5171
5172 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5173 {
5174         struct vcpu_vmx *vmx = to_vmx(vcpu);
5175         enum emulation_result err = EMULATE_DONE;
5176         int ret = 1;
5177         u32 cpu_exec_ctrl;
5178         bool intr_window_requested;
5179         unsigned count = 130;
5180
5181         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5182         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5183
5184         while (!guest_state_valid(vcpu) && count-- != 0) {
5185                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5186                         return handle_interrupt_window(&vmx->vcpu);
5187
5188                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5189                         return 1;
5190
5191                 err = emulate_instruction(vcpu, 0);
5192
5193                 if (err == EMULATE_DO_MMIO) {
5194                         ret = 0;
5195                         goto out;
5196                 }
5197
5198                 if (err != EMULATE_DONE) {
5199                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5200                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5201                         vcpu->run->internal.ndata = 0;
5202                         return 0;
5203                 }
5204
5205                 if (signal_pending(current))
5206                         goto out;
5207                 if (need_resched())
5208                         schedule();
5209         }
5210
5211         vmx->emulation_required = emulation_required(vcpu);
5212 out:
5213         return ret;
5214 }
5215
5216 /*
5217  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5218  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5219  */
5220 static int handle_pause(struct kvm_vcpu *vcpu)
5221 {
5222         skip_emulated_instruction(vcpu);
5223         kvm_vcpu_on_spin(vcpu);
5224
5225         return 1;
5226 }
5227
5228 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5229 {
5230         kvm_queue_exception(vcpu, UD_VECTOR);
5231         return 1;
5232 }
5233
5234 /*
5235  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5236  * We could reuse a single VMCS for all the L2 guests, but we also want the
5237  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5238  * allows keeping them loaded on the processor, and in the future will allow
5239  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5240  * every entry if they never change.
5241  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5242  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5243  *
5244  * The following functions allocate and free a vmcs02 in this pool.
5245  */
5246
5247 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5248 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5249 {
5250         struct vmcs02_list *item;
5251         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5252                 if (item->vmptr == vmx->nested.current_vmptr) {
5253                         list_move(&item->list, &vmx->nested.vmcs02_pool);
5254                         return &item->vmcs02;
5255                 }
5256
5257         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5258                 /* Recycle the least recently used VMCS. */
5259                 item = list_entry(vmx->nested.vmcs02_pool.prev,
5260                         struct vmcs02_list, list);
5261                 item->vmptr = vmx->nested.current_vmptr;
5262                 list_move(&item->list, &vmx->nested.vmcs02_pool);
5263                 return &item->vmcs02;
5264         }
5265
5266         /* Create a new VMCS */
5267         item = (struct vmcs02_list *)
5268                 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5269         if (!item)
5270                 return NULL;
5271         item->vmcs02.vmcs = alloc_vmcs();
5272         if (!item->vmcs02.vmcs) {
5273                 kfree(item);
5274                 return NULL;
5275         }
5276         loaded_vmcs_init(&item->vmcs02);
5277         item->vmptr = vmx->nested.current_vmptr;
5278         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5279         vmx->nested.vmcs02_num++;
5280         return &item->vmcs02;
5281 }
5282
5283 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5284 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5285 {
5286         struct vmcs02_list *item;
5287         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5288                 if (item->vmptr == vmptr) {
5289                         free_loaded_vmcs(&item->vmcs02);
5290                         list_del(&item->list);
5291                         kfree(item);
5292                         vmx->nested.vmcs02_num--;
5293                         return;
5294                 }
5295 }
5296
5297 /*
5298  * Free all VMCSs saved for this vcpu, except the one pointed by
5299  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5300  * currently used, if running L2), and vmcs01 when running L2.
5301  */
5302 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5303 {
5304         struct vmcs02_list *item, *n;
5305         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5306                 if (vmx->loaded_vmcs != &item->vmcs02)
5307                         free_loaded_vmcs(&item->vmcs02);
5308                 list_del(&item->list);
5309                 kfree(item);
5310         }
5311         vmx->nested.vmcs02_num = 0;
5312
5313         if (vmx->loaded_vmcs != &vmx->vmcs01)
5314                 free_loaded_vmcs(&vmx->vmcs01);
5315 }
5316
5317 /*
5318  * Emulate the VMXON instruction.
5319  * Currently, we just remember that VMX is active, and do not save or even
5320  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5321  * do not currently need to store anything in that guest-allocated memory
5322  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5323  * argument is different from the VMXON pointer (which the spec says they do).
5324  */
5325 static int handle_vmon(struct kvm_vcpu *vcpu)
5326 {
5327         struct kvm_segment cs;
5328         struct vcpu_vmx *vmx = to_vmx(vcpu);
5329
5330         /* The Intel VMX Instruction Reference lists a bunch of bits that
5331          * are prerequisite to running VMXON, most notably cr4.VMXE must be
5332          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5333          * Otherwise, we should fail with #UD. We test these now:
5334          */
5335         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5336             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5337             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5338                 kvm_queue_exception(vcpu, UD_VECTOR);
5339                 return 1;
5340         }
5341
5342         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5343         if (is_long_mode(vcpu) && !cs.l) {
5344                 kvm_queue_exception(vcpu, UD_VECTOR);
5345                 return 1;
5346         }
5347
5348         if (vmx_get_cpl(vcpu)) {
5349                 kvm_inject_gp(vcpu, 0);
5350                 return 1;
5351         }
5352
5353         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5354         vmx->nested.vmcs02_num = 0;
5355
5356         vmx->nested.vmxon = true;
5357
5358         skip_emulated_instruction(vcpu);
5359         return 1;
5360 }
5361
5362 /*
5363  * Intel's VMX Instruction Reference specifies a common set of prerequisites
5364  * for running VMX instructions (except VMXON, whose prerequisites are
5365  * slightly different). It also specifies what exception to inject otherwise.
5366  */
5367 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5368 {
5369         struct kvm_segment cs;
5370         struct vcpu_vmx *vmx = to_vmx(vcpu);
5371
5372         if (!vmx->nested.vmxon) {
5373                 kvm_queue_exception(vcpu, UD_VECTOR);
5374                 return 0;
5375         }
5376
5377         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5378         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5379             (is_long_mode(vcpu) && !cs.l)) {
5380                 kvm_queue_exception(vcpu, UD_VECTOR);
5381                 return 0;
5382         }
5383
5384         if (vmx_get_cpl(vcpu)) {
5385                 kvm_inject_gp(vcpu, 0);
5386                 return 0;
5387         }
5388
5389         return 1;
5390 }
5391
5392 /*
5393  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5394  * just stops using VMX.
5395  */
5396 static void free_nested(struct vcpu_vmx *vmx)
5397 {
5398         if (!vmx->nested.vmxon)
5399                 return;
5400         vmx->nested.vmxon = false;
5401         if (vmx->nested.current_vmptr != -1ull) {
5402                 kunmap(vmx->nested.current_vmcs12_page);
5403                 nested_release_page(vmx->nested.current_vmcs12_page);
5404                 vmx->nested.current_vmptr = -1ull;
5405                 vmx->nested.current_vmcs12 = NULL;
5406         }
5407         /* Unpin physical memory we referred to in current vmcs02 */
5408         if (vmx->nested.apic_access_page) {
5409                 nested_release_page(vmx->nested.apic_access_page);
5410                 vmx->nested.apic_access_page = 0;
5411         }
5412
5413         nested_free_all_saved_vmcss(vmx);
5414 }
5415
5416 /* Emulate the VMXOFF instruction */
5417 static int handle_vmoff(struct kvm_vcpu *vcpu)
5418 {
5419         if (!nested_vmx_check_permission(vcpu))
5420                 return 1;
5421         free_nested(to_vmx(vcpu));
5422         skip_emulated_instruction(vcpu);
5423         return 1;
5424 }
5425
5426 /*
5427  * Decode the memory-address operand of a vmx instruction, as recorded on an
5428  * exit caused by such an instruction (run by a guest hypervisor).
5429  * On success, returns 0. When the operand is invalid, returns 1 and throws
5430  * #UD or #GP.
5431  */
5432 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5433                                  unsigned long exit_qualification,
5434                                  u32 vmx_instruction_info, gva_t *ret)
5435 {
5436         /*
5437          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5438          * Execution", on an exit, vmx_instruction_info holds most of the
5439          * addressing components of the operand. Only the displacement part
5440          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5441          * For how an actual address is calculated from all these components,
5442          * refer to Vol. 1, "Operand Addressing".
5443          */
5444         int  scaling = vmx_instruction_info & 3;
5445         int  addr_size = (vmx_instruction_info >> 7) & 7;
5446         bool is_reg = vmx_instruction_info & (1u << 10);
5447         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5448         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5449         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5450         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5451         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5452
5453         if (is_reg) {
5454                 kvm_queue_exception(vcpu, UD_VECTOR);
5455                 return 1;
5456         }
5457
5458         /* Addr = segment_base + offset */
5459         /* offset = base + [index * scale] + displacement */
5460         *ret = vmx_get_segment_base(vcpu, seg_reg);
5461         if (base_is_valid)
5462                 *ret += kvm_register_read(vcpu, base_reg);
5463         if (index_is_valid)
5464                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5465         *ret += exit_qualification; /* holds the displacement */
5466
5467         if (addr_size == 1) /* 32 bit */
5468                 *ret &= 0xffffffff;
5469
5470         /*
5471          * TODO: throw #GP (and return 1) in various cases that the VM*
5472          * instructions require it - e.g., offset beyond segment limit,
5473          * unusable or unreadable/unwritable segment, non-canonical 64-bit
5474          * address, and so on. Currently these are not checked.
5475          */
5476         return 0;
5477 }
5478
5479 /*
5480  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5481  * set the success or error code of an emulated VMX instruction, as specified
5482  * by Vol 2B, VMX Instruction Reference, "Conventions".
5483  */
5484 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5485 {
5486         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5487                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5488                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5489 }
5490
5491 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5492 {
5493         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5494                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5495                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5496                         | X86_EFLAGS_CF);
5497 }
5498
5499 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5500                                         u32 vm_instruction_error)
5501 {
5502         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5503                 /*
5504                  * failValid writes the error number to the current VMCS, which
5505                  * can't be done there isn't a current VMCS.
5506                  */
5507                 nested_vmx_failInvalid(vcpu);
5508                 return;
5509         }
5510         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5511                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5512                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5513                         | X86_EFLAGS_ZF);
5514         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5515 }
5516
5517 /* Emulate the VMCLEAR instruction */
5518 static int handle_vmclear(struct kvm_vcpu *vcpu)
5519 {
5520         struct vcpu_vmx *vmx = to_vmx(vcpu);
5521         gva_t gva;
5522         gpa_t vmptr;
5523         struct vmcs12 *vmcs12;
5524         struct page *page;
5525         struct x86_exception e;
5526
5527         if (!nested_vmx_check_permission(vcpu))
5528                 return 1;
5529
5530         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5531                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5532                 return 1;
5533
5534         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5535                                 sizeof(vmptr), &e)) {
5536                 kvm_inject_page_fault(vcpu, &e);
5537                 return 1;
5538         }
5539
5540         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5541                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5542                 skip_emulated_instruction(vcpu);
5543                 return 1;
5544         }
5545
5546         if (vmptr == vmx->nested.current_vmptr) {
5547                 kunmap(vmx->nested.current_vmcs12_page);
5548                 nested_release_page(vmx->nested.current_vmcs12_page);
5549                 vmx->nested.current_vmptr = -1ull;
5550                 vmx->nested.current_vmcs12 = NULL;
5551         }
5552
5553         page = nested_get_page(vcpu, vmptr);
5554         if (page == NULL) {
5555                 /*
5556                  * For accurate processor emulation, VMCLEAR beyond available
5557                  * physical memory should do nothing at all. However, it is
5558                  * possible that a nested vmx bug, not a guest hypervisor bug,
5559                  * resulted in this case, so let's shut down before doing any
5560                  * more damage:
5561                  */
5562                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5563                 return 1;
5564         }
5565         vmcs12 = kmap(page);
5566         vmcs12->launch_state = 0;
5567         kunmap(page);
5568         nested_release_page(page);
5569
5570         nested_free_vmcs02(vmx, vmptr);
5571
5572         skip_emulated_instruction(vcpu);
5573         nested_vmx_succeed(vcpu);
5574         return 1;
5575 }
5576
5577 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5578
5579 /* Emulate the VMLAUNCH instruction */
5580 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5581 {
5582         return nested_vmx_run(vcpu, true);
5583 }
5584
5585 /* Emulate the VMRESUME instruction */
5586 static int handle_vmresume(struct kvm_vcpu *vcpu)
5587 {
5588
5589         return nested_vmx_run(vcpu, false);
5590 }
5591
5592 enum vmcs_field_type {
5593         VMCS_FIELD_TYPE_U16 = 0,
5594         VMCS_FIELD_TYPE_U64 = 1,
5595         VMCS_FIELD_TYPE_U32 = 2,
5596         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5597 };
5598
5599 static inline int vmcs_field_type(unsigned long field)
5600 {
5601         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
5602                 return VMCS_FIELD_TYPE_U32;
5603         return (field >> 13) & 0x3 ;
5604 }
5605
5606 static inline int vmcs_field_readonly(unsigned long field)
5607 {
5608         return (((field >> 10) & 0x3) == 1);
5609 }
5610
5611 /*
5612  * Read a vmcs12 field. Since these can have varying lengths and we return
5613  * one type, we chose the biggest type (u64) and zero-extend the return value
5614  * to that size. Note that the caller, handle_vmread, might need to use only
5615  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5616  * 64-bit fields are to be returned).
5617  */
5618 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5619                                         unsigned long field, u64 *ret)
5620 {
5621         short offset = vmcs_field_to_offset(field);
5622         char *p;
5623
5624         if (offset < 0)
5625                 return 0;
5626
5627         p = ((char *)(get_vmcs12(vcpu))) + offset;
5628
5629         switch (vmcs_field_type(field)) {
5630         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5631                 *ret = *((natural_width *)p);
5632                 return 1;
5633         case VMCS_FIELD_TYPE_U16:
5634                 *ret = *((u16 *)p);
5635                 return 1;
5636         case VMCS_FIELD_TYPE_U32:
5637                 *ret = *((u32 *)p);
5638                 return 1;
5639         case VMCS_FIELD_TYPE_U64:
5640                 *ret = *((u64 *)p);
5641                 return 1;
5642         default:
5643                 return 0; /* can never happen. */
5644         }
5645 }
5646
5647 /*
5648  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5649  * used before) all generate the same failure when it is missing.
5650  */
5651 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5652 {
5653         struct vcpu_vmx *vmx = to_vmx(vcpu);
5654         if (vmx->nested.current_vmptr == -1ull) {
5655                 nested_vmx_failInvalid(vcpu);
5656                 skip_emulated_instruction(vcpu);
5657                 return 0;
5658         }
5659         return 1;
5660 }
5661
5662 static int handle_vmread(struct kvm_vcpu *vcpu)
5663 {
5664         unsigned long field;
5665         u64 field_value;
5666         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5667         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5668         gva_t gva = 0;
5669
5670         if (!nested_vmx_check_permission(vcpu) ||
5671             !nested_vmx_check_vmcs12(vcpu))
5672                 return 1;
5673
5674         /* Decode instruction info and find the field to read */
5675         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5676         /* Read the field, zero-extended to a u64 field_value */
5677         if (!vmcs12_read_any(vcpu, field, &field_value)) {
5678                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5679                 skip_emulated_instruction(vcpu);
5680                 return 1;
5681         }
5682         /*
5683          * Now copy part of this value to register or memory, as requested.
5684          * Note that the number of bits actually copied is 32 or 64 depending
5685          * on the guest's mode (32 or 64 bit), not on the given field's length.
5686          */
5687         if (vmx_instruction_info & (1u << 10)) {
5688                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5689                         field_value);
5690         } else {
5691                 if (get_vmx_mem_address(vcpu, exit_qualification,
5692                                 vmx_instruction_info, &gva))
5693                         return 1;
5694                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5695                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5696                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5697         }
5698
5699         nested_vmx_succeed(vcpu);
5700         skip_emulated_instruction(vcpu);
5701         return 1;
5702 }
5703
5704
5705 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5706 {
5707         unsigned long field;
5708         gva_t gva;
5709         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5710         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5711         char *p;
5712         short offset;
5713         /* The value to write might be 32 or 64 bits, depending on L1's long
5714          * mode, and eventually we need to write that into a field of several
5715          * possible lengths. The code below first zero-extends the value to 64
5716          * bit (field_value), and then copies only the approriate number of
5717          * bits into the vmcs12 field.
5718          */
5719         u64 field_value = 0;
5720         struct x86_exception e;
5721
5722         if (!nested_vmx_check_permission(vcpu) ||
5723             !nested_vmx_check_vmcs12(vcpu))
5724                 return 1;
5725
5726         if (vmx_instruction_info & (1u << 10))
5727                 field_value = kvm_register_read(vcpu,
5728                         (((vmx_instruction_info) >> 3) & 0xf));
5729         else {
5730                 if (get_vmx_mem_address(vcpu, exit_qualification,
5731                                 vmx_instruction_info, &gva))
5732                         return 1;
5733                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5734                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5735                         kvm_inject_page_fault(vcpu, &e);
5736                         return 1;
5737                 }
5738         }
5739
5740
5741         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5742         if (vmcs_field_readonly(field)) {
5743                 nested_vmx_failValid(vcpu,
5744                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5745                 skip_emulated_instruction(vcpu);
5746                 return 1;
5747         }
5748
5749         offset = vmcs_field_to_offset(field);
5750         if (offset < 0) {
5751                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5752                 skip_emulated_instruction(vcpu);
5753                 return 1;
5754         }
5755         p = ((char *) get_vmcs12(vcpu)) + offset;
5756
5757         switch (vmcs_field_type(field)) {
5758         case VMCS_FIELD_TYPE_U16:
5759                 *(u16 *)p = field_value;
5760                 break;
5761         case VMCS_FIELD_TYPE_U32:
5762                 *(u32 *)p = field_value;
5763                 break;
5764         case VMCS_FIELD_TYPE_U64:
5765                 *(u64 *)p = field_value;
5766                 break;
5767         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5768                 *(natural_width *)p = field_value;
5769                 break;
5770         default:
5771                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5772                 skip_emulated_instruction(vcpu);
5773                 return 1;
5774         }
5775
5776         nested_vmx_succeed(vcpu);
5777         skip_emulated_instruction(vcpu);
5778         return 1;
5779 }
5780
5781 /* Emulate the VMPTRLD instruction */
5782 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5783 {
5784         struct vcpu_vmx *vmx = to_vmx(vcpu);
5785         gva_t gva;
5786         gpa_t vmptr;
5787         struct x86_exception e;
5788
5789         if (!nested_vmx_check_permission(vcpu))
5790                 return 1;
5791
5792         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5793                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5794                 return 1;
5795
5796         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5797                                 sizeof(vmptr), &e)) {
5798                 kvm_inject_page_fault(vcpu, &e);
5799                 return 1;
5800         }
5801
5802         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5803                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5804                 skip_emulated_instruction(vcpu);
5805                 return 1;
5806         }
5807
5808         if (vmx->nested.current_vmptr != vmptr) {
5809                 struct vmcs12 *new_vmcs12;
5810                 struct page *page;
5811                 page = nested_get_page(vcpu, vmptr);
5812                 if (page == NULL) {
5813                         nested_vmx_failInvalid(vcpu);
5814                         skip_emulated_instruction(vcpu);
5815                         return 1;
5816                 }
5817                 new_vmcs12 = kmap(page);
5818                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5819                         kunmap(page);
5820                         nested_release_page_clean(page);
5821                         nested_vmx_failValid(vcpu,
5822                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5823                         skip_emulated_instruction(vcpu);
5824                         return 1;
5825                 }
5826                 if (vmx->nested.current_vmptr != -1ull) {
5827                         kunmap(vmx->nested.current_vmcs12_page);
5828                         nested_release_page(vmx->nested.current_vmcs12_page);
5829                 }
5830
5831                 vmx->nested.current_vmptr = vmptr;
5832                 vmx->nested.current_vmcs12 = new_vmcs12;
5833                 vmx->nested.current_vmcs12_page = page;
5834         }
5835
5836         nested_vmx_succeed(vcpu);
5837         skip_emulated_instruction(vcpu);
5838         return 1;
5839 }
5840
5841 /* Emulate the VMPTRST instruction */
5842 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5843 {
5844         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5845         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5846         gva_t vmcs_gva;
5847         struct x86_exception e;
5848
5849         if (!nested_vmx_check_permission(vcpu))
5850                 return 1;
5851
5852         if (get_vmx_mem_address(vcpu, exit_qualification,
5853                         vmx_instruction_info, &vmcs_gva))
5854                 return 1;
5855         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5856         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5857                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
5858                                  sizeof(u64), &e)) {
5859                 kvm_inject_page_fault(vcpu, &e);
5860                 return 1;
5861         }
5862         nested_vmx_succeed(vcpu);
5863         skip_emulated_instruction(vcpu);
5864         return 1;
5865 }
5866
5867 /*
5868  * The exit handlers return 1 if the exit was handled fully and guest execution
5869  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5870  * to be done to userspace and return 0.
5871  */
5872 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5873         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
5874         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5875         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5876         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5877         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5878         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5879         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5880         [EXIT_REASON_CPUID]                   = handle_cpuid,
5881         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
5882         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
5883         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
5884         [EXIT_REASON_HLT]                     = handle_halt,
5885         [EXIT_REASON_INVD]                    = handle_invd,
5886         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5887         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
5888         [EXIT_REASON_VMCALL]                  = handle_vmcall,
5889         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
5890         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
5891         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
5892         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
5893         [EXIT_REASON_VMREAD]                  = handle_vmread,
5894         [EXIT_REASON_VMRESUME]                = handle_vmresume,
5895         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
5896         [EXIT_REASON_VMOFF]                   = handle_vmoff,
5897         [EXIT_REASON_VMON]                    = handle_vmon,
5898         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5899         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5900         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
5901         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
5902         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
5903         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
5904         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5905         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5906         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5907         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5908         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5909         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
5910         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
5911 };
5912
5913 static const int kvm_vmx_max_exit_handlers =
5914         ARRAY_SIZE(kvm_vmx_exit_handlers);
5915
5916 /*
5917  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5918  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5919  * disinterest in the current event (read or write a specific MSR) by using an
5920  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5921  */
5922 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5923         struct vmcs12 *vmcs12, u32 exit_reason)
5924 {
5925         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5926         gpa_t bitmap;
5927
5928         if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5929                 return 1;
5930
5931         /*
5932          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5933          * for the four combinations of read/write and low/high MSR numbers.
5934          * First we need to figure out which of the four to use:
5935          */
5936         bitmap = vmcs12->msr_bitmap;
5937         if (exit_reason == EXIT_REASON_MSR_WRITE)
5938                 bitmap += 2048;
5939         if (msr_index >= 0xc0000000) {
5940                 msr_index -= 0xc0000000;
5941                 bitmap += 1024;
5942         }
5943
5944         /* Then read the msr_index'th bit from this bitmap: */
5945         if (msr_index < 1024*8) {
5946                 unsigned char b;
5947                 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5948                 return 1 & (b >> (msr_index & 7));
5949         } else
5950                 return 1; /* let L1 handle the wrong parameter */
5951 }
5952
5953 /*
5954  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5955  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5956  * intercept (via guest_host_mask etc.) the current event.
5957  */
5958 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5959         struct vmcs12 *vmcs12)
5960 {
5961         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5962         int cr = exit_qualification & 15;
5963         int reg = (exit_qualification >> 8) & 15;
5964         unsigned long val = kvm_register_read(vcpu, reg);
5965
5966         switch ((exit_qualification >> 4) & 3) {
5967         case 0: /* mov to cr */
5968                 switch (cr) {
5969                 case 0:
5970                         if (vmcs12->cr0_guest_host_mask &
5971                             (val ^ vmcs12->cr0_read_shadow))
5972                                 return 1;
5973                         break;
5974                 case 3:
5975                         if ((vmcs12->cr3_target_count >= 1 &&
5976                                         vmcs12->cr3_target_value0 == val) ||
5977                                 (vmcs12->cr3_target_count >= 2 &&
5978                                         vmcs12->cr3_target_value1 == val) ||
5979                                 (vmcs12->cr3_target_count >= 3 &&
5980                                         vmcs12->cr3_target_value2 == val) ||
5981                                 (vmcs12->cr3_target_count >= 4 &&
5982                                         vmcs12->cr3_target_value3 == val))
5983                                 return 0;
5984                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5985                                 return 1;
5986                         break;
5987                 case 4:
5988                         if (vmcs12->cr4_guest_host_mask &
5989                             (vmcs12->cr4_read_shadow ^ val))
5990                                 return 1;
5991                         break;
5992                 case 8:
5993                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5994                                 return 1;
5995                         break;
5996                 }
5997                 break;
5998         case 2: /* clts */
5999                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6000                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
6001                         return 1;
6002                 break;
6003         case 1: /* mov from cr */
6004                 switch (cr) {
6005                 case 3:
6006                         if (vmcs12->cpu_based_vm_exec_control &
6007                             CPU_BASED_CR3_STORE_EXITING)
6008                                 return 1;
6009                         break;
6010                 case 8:
6011                         if (vmcs12->cpu_based_vm_exec_control &
6012                             CPU_BASED_CR8_STORE_EXITING)
6013                                 return 1;
6014                         break;
6015                 }
6016                 break;
6017         case 3: /* lmsw */
6018                 /*
6019                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6020                  * cr0. Other attempted changes are ignored, with no exit.
6021                  */
6022                 if (vmcs12->cr0_guest_host_mask & 0xe &
6023                     (val ^ vmcs12->cr0_read_shadow))
6024                         return 1;
6025                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6026                     !(vmcs12->cr0_read_shadow & 0x1) &&
6027                     (val & 0x1))
6028                         return 1;
6029                 break;
6030         }
6031         return 0;
6032 }
6033
6034 /*
6035  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6036  * should handle it ourselves in L0 (and then continue L2). Only call this
6037  * when in is_guest_mode (L2).
6038  */
6039 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6040 {
6041         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
6042         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6043         struct vcpu_vmx *vmx = to_vmx(vcpu);
6044         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6045
6046         if (vmx->nested.nested_run_pending)
6047                 return 0;
6048
6049         if (unlikely(vmx->fail)) {
6050                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6051                                     vmcs_read32(VM_INSTRUCTION_ERROR));
6052                 return 1;
6053         }
6054
6055         switch (exit_reason) {
6056         case EXIT_REASON_EXCEPTION_NMI:
6057                 if (!is_exception(intr_info))
6058                         return 0;
6059                 else if (is_page_fault(intr_info))
6060                         return enable_ept;
6061                 return vmcs12->exception_bitmap &
6062                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6063         case EXIT_REASON_EXTERNAL_INTERRUPT:
6064                 return 0;
6065         case EXIT_REASON_TRIPLE_FAULT:
6066                 return 1;
6067         case EXIT_REASON_PENDING_INTERRUPT:
6068         case EXIT_REASON_NMI_WINDOW:
6069                 /*
6070                  * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
6071                  * (aka Interrupt Window Exiting) only when L1 turned it on,
6072                  * so if we got a PENDING_INTERRUPT exit, this must be for L1.
6073                  * Same for NMI Window Exiting.
6074                  */
6075                 return 1;
6076         case EXIT_REASON_TASK_SWITCH:
6077                 return 1;
6078         case EXIT_REASON_CPUID:
6079                 return 1;
6080         case EXIT_REASON_HLT:
6081                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6082         case EXIT_REASON_INVD:
6083                 return 1;
6084         case EXIT_REASON_INVLPG:
6085                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6086         case EXIT_REASON_RDPMC:
6087                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6088         case EXIT_REASON_RDTSC:
6089                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6090         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6091         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6092         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6093         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6094         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6095                 /*
6096                  * VMX instructions trap unconditionally. This allows L1 to
6097                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
6098                  */
6099                 return 1;
6100         case EXIT_REASON_CR_ACCESS:
6101                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6102         case EXIT_REASON_DR_ACCESS:
6103                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6104         case EXIT_REASON_IO_INSTRUCTION:
6105                 /* TODO: support IO bitmaps */
6106                 return 1;
6107         case EXIT_REASON_MSR_READ:
6108         case EXIT_REASON_MSR_WRITE:
6109                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6110         case EXIT_REASON_INVALID_STATE:
6111                 return 1;
6112         case EXIT_REASON_MWAIT_INSTRUCTION:
6113                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6114         case EXIT_REASON_MONITOR_INSTRUCTION:
6115                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6116         case EXIT_REASON_PAUSE_INSTRUCTION:
6117                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6118                         nested_cpu_has2(vmcs12,
6119                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6120         case EXIT_REASON_MCE_DURING_VMENTRY:
6121                 return 0;
6122         case EXIT_REASON_TPR_BELOW_THRESHOLD:
6123                 return 1;
6124         case EXIT_REASON_APIC_ACCESS:
6125                 return nested_cpu_has2(vmcs12,
6126                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6127         case EXIT_REASON_EPT_VIOLATION:
6128         case EXIT_REASON_EPT_MISCONFIG:
6129                 return 0;
6130         case EXIT_REASON_WBINVD:
6131                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6132         case EXIT_REASON_XSETBV:
6133                 return 1;
6134         default:
6135                 return 1;
6136         }
6137 }
6138
6139 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6140 {
6141         *info1 = vmcs_readl(EXIT_QUALIFICATION);
6142         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6143 }
6144
6145 /*
6146  * The guest has exited.  See if we can fix it or if we need userspace
6147  * assistance.
6148  */
6149 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6150 {
6151         struct vcpu_vmx *vmx = to_vmx(vcpu);
6152         u32 exit_reason = vmx->exit_reason;
6153         u32 vectoring_info = vmx->idt_vectoring_info;
6154
6155         /* If guest state is invalid, start emulating */
6156         if (vmx->emulation_required)
6157                 return handle_invalid_guest_state(vcpu);
6158
6159         /*
6160          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
6161          * we did not inject a still-pending event to L1 now because of
6162          * nested_run_pending, we need to re-enable this bit.
6163          */
6164         if (vmx->nested.nested_run_pending)
6165                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6166
6167         if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
6168             exit_reason == EXIT_REASON_VMRESUME))
6169                 vmx->nested.nested_run_pending = 1;
6170         else
6171                 vmx->nested.nested_run_pending = 0;
6172
6173         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6174                 nested_vmx_vmexit(vcpu);
6175                 return 1;
6176         }
6177
6178         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6179                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6180                 vcpu->run->fail_entry.hardware_entry_failure_reason
6181                         = exit_reason;
6182                 return 0;
6183         }
6184
6185         if (unlikely(vmx->fail)) {
6186                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6187                 vcpu->run->fail_entry.hardware_entry_failure_reason
6188                         = vmcs_read32(VM_INSTRUCTION_ERROR);
6189                 return 0;
6190         }
6191
6192         /*
6193          * Note:
6194          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6195          * delivery event since it indicates guest is accessing MMIO.
6196          * The vm-exit can be triggered again after return to guest that
6197          * will cause infinite loop.
6198          */
6199         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
6200                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
6201                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
6202                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
6203                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6204                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6205                 vcpu->run->internal.ndata = 2;
6206                 vcpu->run->internal.data[0] = vectoring_info;
6207                 vcpu->run->internal.data[1] = exit_reason;
6208                 return 0;
6209         }
6210
6211         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6212             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6213                                         get_vmcs12(vcpu), vcpu)))) {
6214                 if (vmx_interrupt_allowed(vcpu)) {
6215                         vmx->soft_vnmi_blocked = 0;
6216                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
6217                            vcpu->arch.nmi_pending) {
6218                         /*
6219                          * This CPU don't support us in finding the end of an
6220                          * NMI-blocked window if the guest runs with IRQs
6221                          * disabled. So we pull the trigger after 1 s of
6222                          * futile waiting, but inform the user about this.
6223                          */
6224                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6225                                "state on VCPU %d after 1 s timeout\n",
6226                                __func__, vcpu->vcpu_id);
6227                         vmx->soft_vnmi_blocked = 0;
6228                 }
6229         }
6230
6231         if (exit_reason < kvm_vmx_max_exit_handlers
6232             && kvm_vmx_exit_handlers[exit_reason])
6233                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6234         else {
6235                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6236                 vcpu->run->hw.hardware_exit_reason = exit_reason;
6237         }
6238         return 0;
6239 }
6240
6241 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6242 {
6243         if (irr == -1 || tpr < irr) {
6244                 vmcs_write32(TPR_THRESHOLD, 0);
6245                 return;
6246         }
6247
6248         vmcs_write32(TPR_THRESHOLD, irr);
6249 }
6250
6251 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6252 {
6253         u32 sec_exec_control;
6254
6255         /*
6256          * There is not point to enable virtualize x2apic without enable
6257          * apicv
6258          */
6259         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6260                                 !vmx_vm_has_apicv(vcpu->kvm))
6261                 return;
6262
6263         if (!vm_need_tpr_shadow(vcpu->kvm))
6264                 return;
6265
6266         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6267
6268         if (set) {
6269                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6270                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6271         } else {
6272                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6273                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6274         }
6275         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6276
6277         vmx_set_msr_bitmap(vcpu);
6278 }
6279
6280 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6281 {
6282         u16 status;
6283         u8 old;
6284
6285         if (!vmx_vm_has_apicv(kvm))
6286                 return;
6287
6288         if (isr == -1)
6289                 isr = 0;
6290
6291         status = vmcs_read16(GUEST_INTR_STATUS);
6292         old = status >> 8;
6293         if (isr != old) {
6294                 status &= 0xff;
6295                 status |= isr << 8;
6296                 vmcs_write16(GUEST_INTR_STATUS, status);
6297         }
6298 }
6299
6300 static void vmx_set_rvi(int vector)
6301 {
6302         u16 status;
6303         u8 old;
6304
6305         status = vmcs_read16(GUEST_INTR_STATUS);
6306         old = (u8)status & 0xff;
6307         if ((u8)vector != old) {
6308                 status &= ~0xff;
6309                 status |= (u8)vector;
6310                 vmcs_write16(GUEST_INTR_STATUS, status);
6311         }
6312 }
6313
6314 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6315 {
6316         if (max_irr == -1)
6317                 return;
6318
6319         vmx_set_rvi(max_irr);
6320 }
6321
6322 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6323 {
6324         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6325         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6326         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6327         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6328 }
6329
6330 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
6331 {
6332         u32 exit_intr_info;
6333
6334         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6335               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6336                 return;
6337
6338         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6339         exit_intr_info = vmx->exit_intr_info;
6340
6341         /* Handle machine checks before interrupts are enabled */
6342         if (is_machine_check(exit_intr_info))
6343                 kvm_machine_check();
6344
6345         /* We need to handle NMIs before interrupts are enabled */
6346         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
6347             (exit_intr_info & INTR_INFO_VALID_MASK)) {
6348                 kvm_before_handle_nmi(&vmx->vcpu);
6349                 asm("int $2");
6350                 kvm_after_handle_nmi(&vmx->vcpu);
6351         }
6352 }
6353
6354 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6355 {
6356         u32 exit_intr_info;
6357         bool unblock_nmi;
6358         u8 vector;
6359         bool idtv_info_valid;
6360
6361         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6362
6363         if (cpu_has_virtual_nmis()) {
6364                 if (vmx->nmi_known_unmasked)
6365                         return;
6366                 /*
6367                  * Can't use vmx->exit_intr_info since we're not sure what
6368                  * the exit reason is.
6369                  */
6370                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6371                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6372                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6373                 /*
6374                  * SDM 3: 27.7.1.2 (September 2008)
6375                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6376                  * a guest IRET fault.
6377                  * SDM 3: 23.2.2 (September 2008)
6378                  * Bit 12 is undefined in any of the following cases:
6379                  *  If the VM exit sets the valid bit in the IDT-vectoring
6380                  *   information field.
6381                  *  If the VM exit is due to a double fault.
6382                  */
6383                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6384                     vector != DF_VECTOR && !idtv_info_valid)
6385                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6386                                       GUEST_INTR_STATE_NMI);
6387                 else
6388                         vmx->nmi_known_unmasked =
6389                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6390                                   & GUEST_INTR_STATE_NMI);
6391         } else if (unlikely(vmx->soft_vnmi_blocked))
6392                 vmx->vnmi_blocked_time +=
6393                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
6394 }
6395
6396 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
6397                                       u32 idt_vectoring_info,
6398                                       int instr_len_field,
6399                                       int error_code_field)
6400 {
6401         u8 vector;
6402         int type;
6403         bool idtv_info_valid;
6404
6405         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6406
6407         vmx->vcpu.arch.nmi_injected = false;
6408         kvm_clear_exception_queue(&vmx->vcpu);
6409         kvm_clear_interrupt_queue(&vmx->vcpu);
6410
6411         if (!idtv_info_valid)
6412                 return;
6413
6414         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6415
6416         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6417         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6418
6419         switch (type) {
6420         case INTR_TYPE_NMI_INTR:
6421                 vmx->vcpu.arch.nmi_injected = true;
6422                 /*
6423                  * SDM 3: 27.7.1.2 (September 2008)
6424                  * Clear bit "block by NMI" before VM entry if a NMI
6425                  * delivery faulted.
6426                  */
6427                 vmx_set_nmi_mask(&vmx->vcpu, false);
6428                 break;
6429         case INTR_TYPE_SOFT_EXCEPTION:
6430                 vmx->vcpu.arch.event_exit_inst_len =
6431                         vmcs_read32(instr_len_field);
6432                 /* fall through */
6433         case INTR_TYPE_HARD_EXCEPTION:
6434                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6435                         u32 err = vmcs_read32(error_code_field);
6436                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
6437                 } else
6438                         kvm_queue_exception(&vmx->vcpu, vector);
6439                 break;
6440         case INTR_TYPE_SOFT_INTR:
6441                 vmx->vcpu.arch.event_exit_inst_len =
6442                         vmcs_read32(instr_len_field);
6443                 /* fall through */
6444         case INTR_TYPE_EXT_INTR:
6445                 kvm_queue_interrupt(&vmx->vcpu, vector,
6446                         type == INTR_TYPE_SOFT_INTR);
6447                 break;
6448         default:
6449                 break;
6450         }
6451 }
6452
6453 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6454 {
6455         if (is_guest_mode(&vmx->vcpu))
6456                 return;
6457         __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6458                                   VM_EXIT_INSTRUCTION_LEN,
6459                                   IDT_VECTORING_ERROR_CODE);
6460 }
6461
6462 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6463 {
6464         if (is_guest_mode(vcpu))
6465                 return;
6466         __vmx_complete_interrupts(to_vmx(vcpu),
6467                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6468                                   VM_ENTRY_INSTRUCTION_LEN,
6469                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6470
6471         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6472 }
6473
6474 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6475 {
6476         int i, nr_msrs;
6477         struct perf_guest_switch_msr *msrs;
6478
6479         msrs = perf_guest_get_msrs(&nr_msrs);
6480
6481         if (!msrs)
6482                 return;
6483
6484         for (i = 0; i < nr_msrs; i++)
6485                 if (msrs[i].host == msrs[i].guest)
6486                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6487                 else
6488                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6489                                         msrs[i].host);
6490 }
6491
6492 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6493 {
6494         struct vcpu_vmx *vmx = to_vmx(vcpu);
6495         unsigned long debugctlmsr;
6496
6497         if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6498                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6499                 if (vmcs12->idt_vectoring_info_field &
6500                                 VECTORING_INFO_VALID_MASK) {
6501                         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6502                                 vmcs12->idt_vectoring_info_field);
6503                         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6504                                 vmcs12->vm_exit_instruction_len);
6505                         if (vmcs12->idt_vectoring_info_field &
6506                                         VECTORING_INFO_DELIVER_CODE_MASK)
6507                                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6508                                         vmcs12->idt_vectoring_error_code);
6509                 }
6510         }
6511
6512         /* Record the guest's net vcpu time for enforced NMI injections. */
6513         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6514                 vmx->entry_time = ktime_get();
6515
6516         /* Don't enter VMX if guest state is invalid, let the exit handler
6517            start emulation until we arrive back to a valid state */
6518         if (vmx->emulation_required)
6519                 return;
6520
6521         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6522                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6523         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6524                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6525
6526         /* When single-stepping over STI and MOV SS, we must clear the
6527          * corresponding interruptibility bits in the guest state. Otherwise
6528          * vmentry fails as it then expects bit 14 (BS) in pending debug
6529          * exceptions being set, but that's not correct for the guest debugging
6530          * case. */
6531         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6532                 vmx_set_interrupt_shadow(vcpu, 0);
6533
6534         atomic_switch_perf_msrs(vmx);
6535         debugctlmsr = get_debugctlmsr();
6536
6537         vmx->__launched = vmx->loaded_vmcs->launched;
6538         asm(
6539                 /* Store host registers */
6540                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
6541                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
6542                 "push %%" _ASM_CX " \n\t"
6543                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
6544                 "je 1f \n\t"
6545                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
6546                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
6547                 "1: \n\t"
6548                 /* Reload cr2 if changed */
6549                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
6550                 "mov %%cr2, %%" _ASM_DX " \n\t"
6551                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
6552                 "je 2f \n\t"
6553                 "mov %%" _ASM_AX", %%cr2 \n\t"
6554                 "2: \n\t"
6555                 /* Check if vmlaunch of vmresume is needed */
6556                 "cmpl $0, %c[launched](%0) \n\t"
6557                 /* Load guest registers.  Don't clobber flags. */
6558                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
6559                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
6560                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
6561                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
6562                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
6563                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
6564 #ifdef CONFIG_X86_64
6565                 "mov %c[r8](%0),  %%r8  \n\t"
6566                 "mov %c[r9](%0),  %%r9  \n\t"
6567                 "mov %c[r10](%0), %%r10 \n\t"
6568                 "mov %c[r11](%0), %%r11 \n\t"
6569                 "mov %c[r12](%0), %%r12 \n\t"
6570                 "mov %c[r13](%0), %%r13 \n\t"
6571                 "mov %c[r14](%0), %%r14 \n\t"
6572                 "mov %c[r15](%0), %%r15 \n\t"
6573 #endif
6574                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
6575
6576                 /* Enter guest mode */
6577                 "jne 1f \n\t"
6578                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
6579                 "jmp 2f \n\t"
6580                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
6581                 "2: "
6582                 /* Save guest registers, load host registers, keep flags */
6583                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
6584                 "pop %0 \n\t"
6585                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
6586                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
6587                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
6588                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
6589                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
6590                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
6591                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
6592 #ifdef CONFIG_X86_64
6593                 "mov %%r8,  %c[r8](%0) \n\t"
6594                 "mov %%r9,  %c[r9](%0) \n\t"
6595                 "mov %%r10, %c[r10](%0) \n\t"
6596                 "mov %%r11, %c[r11](%0) \n\t"
6597                 "mov %%r12, %c[r12](%0) \n\t"
6598                 "mov %%r13, %c[r13](%0) \n\t"
6599                 "mov %%r14, %c[r14](%0) \n\t"
6600                 "mov %%r15, %c[r15](%0) \n\t"
6601 #endif
6602                 "mov %%cr2, %%" _ASM_AX "   \n\t"
6603                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
6604
6605                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
6606                 "setbe %c[fail](%0) \n\t"
6607                 ".pushsection .rodata \n\t"
6608                 ".global vmx_return \n\t"
6609                 "vmx_return: " _ASM_PTR " 2b \n\t"
6610                 ".popsection"
6611               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
6612                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
6613                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
6614                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
6615                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6616                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6617                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6618                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6619                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6620                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6621                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
6622 #ifdef CONFIG_X86_64
6623                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6624                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6625                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6626                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6627                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6628                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6629                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6630                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6631 #endif
6632                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6633                 [wordsize]"i"(sizeof(ulong))
6634               : "cc", "memory"
6635 #ifdef CONFIG_X86_64
6636                 , "rax", "rbx", "rdi", "rsi"
6637                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6638 #else
6639                 , "eax", "ebx", "edi", "esi"
6640 #endif
6641               );
6642
6643         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6644         if (debugctlmsr)
6645                 update_debugctlmsr(debugctlmsr);
6646
6647 #ifndef CONFIG_X86_64
6648         /*
6649          * The sysexit path does not restore ds/es, so we must set them to
6650          * a reasonable value ourselves.
6651          *
6652          * We can't defer this to vmx_load_host_state() since that function
6653          * may be executed in interrupt context, which saves and restore segments
6654          * around it, nullifying its effect.
6655          */
6656         loadsegment(ds, __USER_DS);
6657         loadsegment(es, __USER_DS);
6658 #endif
6659
6660         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6661                                   | (1 << VCPU_EXREG_RFLAGS)
6662                                   | (1 << VCPU_EXREG_CPL)
6663                                   | (1 << VCPU_EXREG_PDPTR)
6664                                   | (1 << VCPU_EXREG_SEGMENTS)
6665                                   | (1 << VCPU_EXREG_CR3));
6666         vcpu->arch.regs_dirty = 0;
6667
6668         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6669
6670         if (is_guest_mode(vcpu)) {
6671                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6672                 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6673                 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6674                         vmcs12->idt_vectoring_error_code =
6675                                 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6676                         vmcs12->vm_exit_instruction_len =
6677                                 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6678                 }
6679         }
6680
6681         vmx->loaded_vmcs->launched = 1;
6682
6683         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
6684         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
6685
6686         vmx_complete_atomic_exit(vmx);
6687         vmx_recover_nmi_blocking(vmx);
6688         vmx_complete_interrupts(vmx);
6689 }
6690
6691 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6692 {
6693         struct vcpu_vmx *vmx = to_vmx(vcpu);
6694
6695         free_vpid(vmx);
6696         free_nested(vmx);
6697         free_loaded_vmcs(vmx->loaded_vmcs);
6698         kfree(vmx->guest_msrs);
6699         kvm_vcpu_uninit(vcpu);
6700         kmem_cache_free(kvm_vcpu_cache, vmx);
6701 }
6702
6703 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6704 {
6705         int err;
6706         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
6707         int cpu;
6708
6709         if (!vmx)
6710                 return ERR_PTR(-ENOMEM);
6711
6712         allocate_vpid(vmx);
6713
6714         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6715         if (err)
6716                 goto free_vcpu;
6717
6718         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
6719         err = -ENOMEM;
6720         if (!vmx->guest_msrs) {
6721                 goto uninit_vcpu;
6722         }
6723
6724         vmx->loaded_vmcs = &vmx->vmcs01;
6725         vmx->loaded_vmcs->vmcs = alloc_vmcs();
6726         if (!vmx->loaded_vmcs->vmcs)
6727                 goto free_msrs;
6728         if (!vmm_exclusive)
6729                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6730         loaded_vmcs_init(vmx->loaded_vmcs);
6731         if (!vmm_exclusive)
6732                 kvm_cpu_vmxoff();
6733
6734         cpu = get_cpu();
6735         vmx_vcpu_load(&vmx->vcpu, cpu);
6736         vmx->vcpu.cpu = cpu;
6737         err = vmx_vcpu_setup(vmx);
6738         vmx_vcpu_put(&vmx->vcpu);
6739         put_cpu();
6740         if (err)
6741                 goto free_vmcs;
6742         if (vm_need_virtualize_apic_accesses(kvm))
6743                 err = alloc_apic_access_page(kvm);
6744                 if (err)
6745                         goto free_vmcs;
6746
6747         if (enable_ept) {
6748                 if (!kvm->arch.ept_identity_map_addr)
6749                         kvm->arch.ept_identity_map_addr =
6750                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
6751                 err = -ENOMEM;
6752                 if (alloc_identity_pagetable(kvm) != 0)
6753                         goto free_vmcs;
6754                 if (!init_rmode_identity_map(kvm))
6755                         goto free_vmcs;
6756         }
6757
6758         vmx->nested.current_vmptr = -1ull;
6759         vmx->nested.current_vmcs12 = NULL;
6760
6761         return &vmx->vcpu;
6762
6763 free_vmcs:
6764         free_loaded_vmcs(vmx->loaded_vmcs);
6765 free_msrs:
6766         kfree(vmx->guest_msrs);
6767 uninit_vcpu:
6768         kvm_vcpu_uninit(&vmx->vcpu);
6769 free_vcpu:
6770         free_vpid(vmx);
6771         kmem_cache_free(kvm_vcpu_cache, vmx);
6772         return ERR_PTR(err);
6773 }
6774
6775 static void __init vmx_check_processor_compat(void *rtn)
6776 {
6777         struct vmcs_config vmcs_conf;
6778
6779         *(int *)rtn = 0;
6780         if (setup_vmcs_config(&vmcs_conf) < 0)
6781                 *(int *)rtn = -EIO;
6782         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6783                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6784                                 smp_processor_id());
6785                 *(int *)rtn = -EIO;
6786         }
6787 }
6788
6789 static int get_ept_level(void)
6790 {
6791         return VMX_EPT_DEFAULT_GAW + 1;
6792 }
6793
6794 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6795 {
6796         u64 ret;
6797
6798         /* For VT-d and EPT combination
6799          * 1. MMIO: always map as UC
6800          * 2. EPT with VT-d:
6801          *   a. VT-d without snooping control feature: can't guarantee the
6802          *      result, try to trust guest.
6803          *   b. VT-d with snooping control feature: snooping control feature of
6804          *      VT-d engine can guarantee the cache correctness. Just set it
6805          *      to WB to keep consistent with host. So the same as item 3.
6806          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6807          *    consistent with host MTRR
6808          */
6809         if (is_mmio)
6810                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
6811         else if (vcpu->kvm->arch.iommu_domain &&
6812                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6813                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6814                       VMX_EPT_MT_EPTE_SHIFT;
6815         else
6816                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
6817                         | VMX_EPT_IPAT_BIT;
6818
6819         return ret;
6820 }
6821
6822 static int vmx_get_lpage_level(void)
6823 {
6824         if (enable_ept && !cpu_has_vmx_ept_1g_page())
6825                 return PT_DIRECTORY_LEVEL;
6826         else
6827                 /* For shadow and EPT supported 1GB page */
6828                 return PT_PDPE_LEVEL;
6829 }
6830
6831 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6832 {
6833         struct kvm_cpuid_entry2 *best;
6834         struct vcpu_vmx *vmx = to_vmx(vcpu);
6835         u32 exec_control;
6836
6837         vmx->rdtscp_enabled = false;
6838         if (vmx_rdtscp_supported()) {
6839                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6840                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6841                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6842                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6843                                 vmx->rdtscp_enabled = true;
6844                         else {
6845                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6846                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6847                                                 exec_control);
6848                         }
6849                 }
6850         }
6851
6852         /* Exposing INVPCID only when PCID is exposed */
6853         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6854         if (vmx_invpcid_supported() &&
6855             best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
6856             guest_cpuid_has_pcid(vcpu)) {
6857                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6858                 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
6859                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6860                              exec_control);
6861         } else {
6862                 if (cpu_has_secondary_exec_ctrls()) {
6863                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6864                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6865                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6866                                      exec_control);
6867                 }
6868                 if (best)
6869                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
6870         }
6871 }
6872
6873 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6874 {
6875         if (func == 1 && nested)
6876                 entry->ecx |= bit(X86_FEATURE_VMX);
6877 }
6878
6879 /*
6880  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6881  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6882  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6883  * guest in a way that will both be appropriate to L1's requests, and our
6884  * needs. In addition to modifying the active vmcs (which is vmcs02), this
6885  * function also has additional necessary side-effects, like setting various
6886  * vcpu->arch fields.
6887  */
6888 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6889 {
6890         struct vcpu_vmx *vmx = to_vmx(vcpu);
6891         u32 exec_control;
6892
6893         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6894         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6895         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6896         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6897         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6898         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6899         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6900         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6901         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6902         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6903         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6904         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6905         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6906         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6907         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6908         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6909         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6910         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6911         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6912         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6913         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6914         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6915         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6916         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6917         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6918         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6919         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6920         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6921         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6922         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6923         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6924         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6925         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6926         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6927         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6928         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6929
6930         vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6931         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6932                 vmcs12->vm_entry_intr_info_field);
6933         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6934                 vmcs12->vm_entry_exception_error_code);
6935         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6936                 vmcs12->vm_entry_instruction_len);
6937         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6938                 vmcs12->guest_interruptibility_info);
6939         vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6940         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6941         vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6942         vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6943         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6944                 vmcs12->guest_pending_dbg_exceptions);
6945         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6946         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6947
6948         vmcs_write64(VMCS_LINK_POINTER, -1ull);
6949
6950         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6951                 (vmcs_config.pin_based_exec_ctrl |
6952                  vmcs12->pin_based_vm_exec_control));
6953
6954         /*
6955          * Whether page-faults are trapped is determined by a combination of
6956          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6957          * If enable_ept, L0 doesn't care about page faults and we should
6958          * set all of these to L1's desires. However, if !enable_ept, L0 does
6959          * care about (at least some) page faults, and because it is not easy
6960          * (if at all possible?) to merge L0 and L1's desires, we simply ask
6961          * to exit on each and every L2 page fault. This is done by setting
6962          * MASK=MATCH=0 and (see below) EB.PF=1.
6963          * Note that below we don't need special code to set EB.PF beyond the
6964          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6965          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6966          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6967          *
6968          * A problem with this approach (when !enable_ept) is that L1 may be
6969          * injected with more page faults than it asked for. This could have
6970          * caused problems, but in practice existing hypervisors don't care.
6971          * To fix this, we will need to emulate the PFEC checking (on the L1
6972          * page tables), using walk_addr(), when injecting PFs to L1.
6973          */
6974         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6975                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6976         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6977                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6978
6979         if (cpu_has_secondary_exec_ctrls()) {
6980                 u32 exec_control = vmx_secondary_exec_control(vmx);
6981                 if (!vmx->rdtscp_enabled)
6982                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
6983                 /* Take the following fields only from vmcs12 */
6984                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6985                 if (nested_cpu_has(vmcs12,
6986                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6987                         exec_control |= vmcs12->secondary_vm_exec_control;
6988
6989                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6990                         /*
6991                          * Translate L1 physical address to host physical
6992                          * address for vmcs02. Keep the page pinned, so this
6993                          * physical address remains valid. We keep a reference
6994                          * to it so we can release it later.
6995                          */
6996                         if (vmx->nested.apic_access_page) /* shouldn't happen */
6997                                 nested_release_page(vmx->nested.apic_access_page);
6998                         vmx->nested.apic_access_page =
6999                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
7000                         /*
7001                          * If translation failed, no matter: This feature asks
7002                          * to exit when accessing the given address, and if it
7003                          * can never be accessed, this feature won't do
7004                          * anything anyway.
7005                          */
7006                         if (!vmx->nested.apic_access_page)
7007                                 exec_control &=
7008                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7009                         else
7010                                 vmcs_write64(APIC_ACCESS_ADDR,
7011                                   page_to_phys(vmx->nested.apic_access_page));
7012                 }
7013
7014                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7015         }
7016
7017
7018         /*
7019          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7020          * Some constant fields are set here by vmx_set_constant_host_state().
7021          * Other fields are different per CPU, and will be set later when
7022          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7023          */
7024         vmx_set_constant_host_state();
7025
7026         /*
7027          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7028          * entry, but only if the current (host) sp changed from the value
7029          * we wrote last (vmx->host_rsp). This cache is no longer relevant
7030          * if we switch vmcs, and rather than hold a separate cache per vmcs,
7031          * here we just force the write to happen on entry.
7032          */
7033         vmx->host_rsp = 0;
7034
7035         exec_control = vmx_exec_control(vmx); /* L0's desires */
7036         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7037         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7038         exec_control &= ~CPU_BASED_TPR_SHADOW;
7039         exec_control |= vmcs12->cpu_based_vm_exec_control;
7040         /*
7041          * Merging of IO and MSR bitmaps not currently supported.
7042          * Rather, exit every time.
7043          */
7044         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7045         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7046         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7047
7048         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7049
7050         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7051          * bitwise-or of what L1 wants to trap for L2, and what we want to
7052          * trap. Note that CR0.TS also needs updating - we do this later.
7053          */
7054         update_exception_bitmap(vcpu);
7055         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7056         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7057
7058         /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
7059         vmcs_write32(VM_EXIT_CONTROLS,
7060                 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
7061         vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
7062                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7063
7064         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
7065                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
7066         else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
7067                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7068
7069
7070         set_cr4_guest_host_mask(vmx);
7071
7072         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7073                 vmcs_write64(TSC_OFFSET,
7074                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7075         else
7076                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7077
7078         if (enable_vpid) {
7079                 /*
7080                  * Trivially support vpid by letting L2s share their parent
7081                  * L1's vpid. TODO: move to a more elaborate solution, giving
7082                  * each L2 its own vpid and exposing the vpid feature to L1.
7083                  */
7084                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7085                 vmx_flush_tlb(vcpu);
7086         }
7087
7088         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7089                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
7090         if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
7091                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7092         else
7093                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7094         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7095         vmx_set_efer(vcpu, vcpu->arch.efer);
7096
7097         /*
7098          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7099          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7100          * The CR0_READ_SHADOW is what L2 should have expected to read given
7101          * the specifications by L1; It's not enough to take
7102          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7103          * have more bits than L1 expected.
7104          */
7105         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7106         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7107
7108         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7109         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7110
7111         /* shadow page tables on either EPT or shadow page tables */
7112         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7113         kvm_mmu_reset_context(vcpu);
7114
7115         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7116         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7117 }
7118
7119 /*
7120  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7121  * for running an L2 nested guest.
7122  */
7123 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7124 {
7125         struct vmcs12 *vmcs12;
7126         struct vcpu_vmx *vmx = to_vmx(vcpu);
7127         int cpu;
7128         struct loaded_vmcs *vmcs02;
7129
7130         if (!nested_vmx_check_permission(vcpu) ||
7131             !nested_vmx_check_vmcs12(vcpu))
7132                 return 1;
7133
7134         skip_emulated_instruction(vcpu);
7135         vmcs12 = get_vmcs12(vcpu);
7136
7137         /*
7138          * The nested entry process starts with enforcing various prerequisites
7139          * on vmcs12 as required by the Intel SDM, and act appropriately when
7140          * they fail: As the SDM explains, some conditions should cause the
7141          * instruction to fail, while others will cause the instruction to seem
7142          * to succeed, but return an EXIT_REASON_INVALID_STATE.
7143          * To speed up the normal (success) code path, we should avoid checking
7144          * for misconfigurations which will anyway be caught by the processor
7145          * when using the merged vmcs02.
7146          */
7147         if (vmcs12->launch_state == launch) {
7148                 nested_vmx_failValid(vcpu,
7149                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7150                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7151                 return 1;
7152         }
7153
7154         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7155                         !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7156                 /*TODO: Also verify bits beyond physical address width are 0*/
7157                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7158                 return 1;
7159         }
7160
7161         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7162                         !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7163                 /*TODO: Also verify bits beyond physical address width are 0*/
7164                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7165                 return 1;
7166         }
7167
7168         if (vmcs12->vm_entry_msr_load_count > 0 ||
7169             vmcs12->vm_exit_msr_load_count > 0 ||
7170             vmcs12->vm_exit_msr_store_count > 0) {
7171                 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7172                                     __func__);
7173                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7174                 return 1;
7175         }
7176
7177         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7178               nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7179             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7180               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7181             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7182               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7183             !vmx_control_verify(vmcs12->vm_exit_controls,
7184               nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7185             !vmx_control_verify(vmcs12->vm_entry_controls,
7186               nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7187         {
7188                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7189                 return 1;
7190         }
7191
7192         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7193             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7194                 nested_vmx_failValid(vcpu,
7195                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7196                 return 1;
7197         }
7198
7199         if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7200             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7201                 nested_vmx_entry_failure(vcpu, vmcs12,
7202                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7203                 return 1;
7204         }
7205         if (vmcs12->vmcs_link_pointer != -1ull) {
7206                 nested_vmx_entry_failure(vcpu, vmcs12,
7207                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
7208                 return 1;
7209         }
7210
7211         /*
7212          * We're finally done with prerequisite checking, and can start with
7213          * the nested entry.
7214          */
7215
7216         vmcs02 = nested_get_current_vmcs02(vmx);
7217         if (!vmcs02)
7218                 return -ENOMEM;
7219
7220         enter_guest_mode(vcpu);
7221
7222         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
7223
7224         cpu = get_cpu();
7225         vmx->loaded_vmcs = vmcs02;
7226         vmx_vcpu_put(vcpu);
7227         vmx_vcpu_load(vcpu, cpu);
7228         vcpu->cpu = cpu;
7229         put_cpu();
7230
7231         vmcs12->launch_state = 1;
7232
7233         prepare_vmcs02(vcpu, vmcs12);
7234
7235         /*
7236          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
7237          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
7238          * returned as far as L1 is concerned. It will only return (and set
7239          * the success flag) when L2 exits (see nested_vmx_vmexit()).
7240          */
7241         return 1;
7242 }
7243
7244 /*
7245  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
7246  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
7247  * This function returns the new value we should put in vmcs12.guest_cr0.
7248  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
7249  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
7250  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
7251  *     didn't trap the bit, because if L1 did, so would L0).
7252  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
7253  *     been modified by L2, and L1 knows it. So just leave the old value of
7254  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
7255  *     isn't relevant, because if L0 traps this bit it can set it to anything.
7256  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7257  *     changed these bits, and therefore they need to be updated, but L0
7258  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7259  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7260  */
7261 static inline unsigned long
7262 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7263 {
7264         return
7265         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7266         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7267         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7268                         vcpu->arch.cr0_guest_owned_bits));
7269 }
7270
7271 static inline unsigned long
7272 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7273 {
7274         return
7275         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7276         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7277         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7278                         vcpu->arch.cr4_guest_owned_bits));
7279 }
7280
7281 /*
7282  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7283  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7284  * and this function updates it to reflect the changes to the guest state while
7285  * L2 was running (and perhaps made some exits which were handled directly by L0
7286  * without going back to L1), and to reflect the exit reason.
7287  * Note that we do not have to copy here all VMCS fields, just those that
7288  * could have changed by the L2 guest or the exit - i.e., the guest-state and
7289  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7290  * which already writes to vmcs12 directly.
7291  */
7292 void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7293 {
7294         /* update guest state fields: */
7295         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
7296         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
7297
7298         kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
7299         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7300         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
7301         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
7302
7303         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
7304         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
7305         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
7306         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
7307         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7308         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7309         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7310         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7311         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7312         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7313         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7314         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7315         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7316         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7317         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7318         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7319         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7320         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7321         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7322         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7323         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7324         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7325         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7326         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7327         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7328         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7329         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7330         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7331         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7332         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7333         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7334         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7335         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7336         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7337         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7338         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7339
7340         vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
7341         vmcs12->guest_interruptibility_info =
7342                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7343         vmcs12->guest_pending_dbg_exceptions =
7344                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7345
7346         /* TODO: These cannot have changed unless we have MSR bitmaps and
7347          * the relevant bit asks not to trap the change */
7348         vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
7349         if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
7350                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7351         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7352         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7353         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7354
7355         /* update exit information fields: */
7356
7357         vmcs12->vm_exit_reason  = vmcs_read32(VM_EXIT_REASON);
7358         vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7359
7360         vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7361         vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7362         vmcs12->idt_vectoring_info_field =
7363                 vmcs_read32(IDT_VECTORING_INFO_FIELD);
7364         vmcs12->idt_vectoring_error_code =
7365                 vmcs_read32(IDT_VECTORING_ERROR_CODE);
7366         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7367         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7368
7369         /* clear vm-entry fields which are to be cleared on exit */
7370         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
7371                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
7372 }
7373
7374 /*
7375  * A part of what we need to when the nested L2 guest exits and we want to
7376  * run its L1 parent, is to reset L1's guest state to the host state specified
7377  * in vmcs12.
7378  * This function is to be called not only on normal nested exit, but also on
7379  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7380  * Failures During or After Loading Guest State").
7381  * This function should be called when the active VMCS is L1's (vmcs01).
7382  */
7383 void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7384 {
7385         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7386                 vcpu->arch.efer = vmcs12->host_ia32_efer;
7387         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7388                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7389         else
7390                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7391         vmx_set_efer(vcpu, vcpu->arch.efer);
7392
7393         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7394         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
7395         /*
7396          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7397          * actually changed, because it depends on the current state of
7398          * fpu_active (which may have changed).
7399          * Note that vmx_set_cr0 refers to efer set above.
7400          */
7401         kvm_set_cr0(vcpu, vmcs12->host_cr0);
7402         /*
7403          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7404          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7405          * but we also need to update cr0_guest_host_mask and exception_bitmap.
7406          */
7407         update_exception_bitmap(vcpu);
7408         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7409         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7410
7411         /*
7412          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7413          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7414          */
7415         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7416         kvm_set_cr4(vcpu, vmcs12->host_cr4);
7417
7418         /* shadow page tables on either EPT or shadow page tables */
7419         kvm_set_cr3(vcpu, vmcs12->host_cr3);
7420         kvm_mmu_reset_context(vcpu);
7421
7422         if (enable_vpid) {
7423                 /*
7424                  * Trivially support vpid by letting L2s share their parent
7425                  * L1's vpid. TODO: move to a more elaborate solution, giving
7426                  * each L2 its own vpid and exposing the vpid feature to L1.
7427                  */
7428                 vmx_flush_tlb(vcpu);
7429         }
7430
7431
7432         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7433         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7434         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7435         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7436         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7437         vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7438         vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7439         vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7440         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7441         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7442         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7443         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7444         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7445         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7446         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7447
7448         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7449                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7450         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7451                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7452                         vmcs12->host_ia32_perf_global_ctrl);
7453 }
7454
7455 /*
7456  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7457  * and modify vmcs12 to make it see what it would expect to see there if
7458  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7459  */
7460 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7461 {
7462         struct vcpu_vmx *vmx = to_vmx(vcpu);
7463         int cpu;
7464         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7465
7466         leave_guest_mode(vcpu);
7467         prepare_vmcs12(vcpu, vmcs12);
7468
7469         cpu = get_cpu();
7470         vmx->loaded_vmcs = &vmx->vmcs01;
7471         vmx_vcpu_put(vcpu);
7472         vmx_vcpu_load(vcpu, cpu);
7473         vcpu->cpu = cpu;
7474         put_cpu();
7475
7476         /* if no vmcs02 cache requested, remove the one we used */
7477         if (VMCS02_POOL_SIZE == 0)
7478                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7479
7480         load_vmcs12_host_state(vcpu, vmcs12);
7481
7482         /* Update TSC_OFFSET if TSC was changed while L2 ran */
7483         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7484
7485         /* This is needed for same reason as it was needed in prepare_vmcs02 */
7486         vmx->host_rsp = 0;
7487
7488         /* Unpin physical memory we referred to in vmcs02 */
7489         if (vmx->nested.apic_access_page) {
7490                 nested_release_page(vmx->nested.apic_access_page);
7491                 vmx->nested.apic_access_page = 0;
7492         }
7493
7494         /*
7495          * Exiting from L2 to L1, we're now back to L1 which thinks it just
7496          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7497          * success or failure flag accordingly.
7498          */
7499         if (unlikely(vmx->fail)) {
7500                 vmx->fail = 0;
7501                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7502         } else
7503                 nested_vmx_succeed(vcpu);
7504 }
7505
7506 /*
7507  * L1's failure to enter L2 is a subset of a normal exit, as explained in
7508  * 23.7 "VM-entry failures during or after loading guest state" (this also
7509  * lists the acceptable exit-reason and exit-qualification parameters).
7510  * It should only be called before L2 actually succeeded to run, and when
7511  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7512  */
7513 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7514                         struct vmcs12 *vmcs12,
7515                         u32 reason, unsigned long qualification)
7516 {
7517         load_vmcs12_host_state(vcpu, vmcs12);
7518         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7519         vmcs12->exit_qualification = qualification;
7520         nested_vmx_succeed(vcpu);
7521 }
7522
7523 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7524                                struct x86_instruction_info *info,
7525                                enum x86_intercept_stage stage)
7526 {
7527         return X86EMUL_CONTINUE;
7528 }
7529
7530 static struct kvm_x86_ops vmx_x86_ops = {
7531         .cpu_has_kvm_support = cpu_has_kvm_support,
7532         .disabled_by_bios = vmx_disabled_by_bios,
7533         .hardware_setup = hardware_setup,
7534         .hardware_unsetup = hardware_unsetup,
7535         .check_processor_compatibility = vmx_check_processor_compat,
7536         .hardware_enable = hardware_enable,
7537         .hardware_disable = hardware_disable,
7538         .cpu_has_accelerated_tpr = report_flexpriority,
7539
7540         .vcpu_create = vmx_create_vcpu,
7541         .vcpu_free = vmx_free_vcpu,
7542         .vcpu_reset = vmx_vcpu_reset,
7543
7544         .prepare_guest_switch = vmx_save_host_state,
7545         .vcpu_load = vmx_vcpu_load,
7546         .vcpu_put = vmx_vcpu_put,
7547
7548         .update_db_bp_intercept = update_exception_bitmap,
7549         .get_msr = vmx_get_msr,
7550         .set_msr = vmx_set_msr,
7551         .get_segment_base = vmx_get_segment_base,
7552         .get_segment = vmx_get_segment,
7553         .set_segment = vmx_set_segment,
7554         .get_cpl = vmx_get_cpl,
7555         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7556         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7557         .decache_cr3 = vmx_decache_cr3,
7558         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7559         .set_cr0 = vmx_set_cr0,
7560         .set_cr3 = vmx_set_cr3,
7561         .set_cr4 = vmx_set_cr4,
7562         .set_efer = vmx_set_efer,
7563         .get_idt = vmx_get_idt,
7564         .set_idt = vmx_set_idt,
7565         .get_gdt = vmx_get_gdt,
7566         .set_gdt = vmx_set_gdt,
7567         .set_dr7 = vmx_set_dr7,
7568         .cache_reg = vmx_cache_reg,
7569         .get_rflags = vmx_get_rflags,
7570         .set_rflags = vmx_set_rflags,
7571         .fpu_activate = vmx_fpu_activate,
7572         .fpu_deactivate = vmx_fpu_deactivate,
7573
7574         .tlb_flush = vmx_flush_tlb,
7575
7576         .run = vmx_vcpu_run,
7577         .handle_exit = vmx_handle_exit,
7578         .skip_emulated_instruction = skip_emulated_instruction,
7579         .set_interrupt_shadow = vmx_set_interrupt_shadow,
7580         .get_interrupt_shadow = vmx_get_interrupt_shadow,
7581         .patch_hypercall = vmx_patch_hypercall,
7582         .set_irq = vmx_inject_irq,
7583         .set_nmi = vmx_inject_nmi,
7584         .queue_exception = vmx_queue_exception,
7585         .cancel_injection = vmx_cancel_injection,
7586         .interrupt_allowed = vmx_interrupt_allowed,
7587         .nmi_allowed = vmx_nmi_allowed,
7588         .get_nmi_mask = vmx_get_nmi_mask,
7589         .set_nmi_mask = vmx_set_nmi_mask,
7590         .enable_nmi_window = enable_nmi_window,
7591         .enable_irq_window = enable_irq_window,
7592         .update_cr8_intercept = update_cr8_intercept,
7593         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
7594         .vm_has_apicv = vmx_vm_has_apicv,
7595         .load_eoi_exitmap = vmx_load_eoi_exitmap,
7596         .hwapic_irr_update = vmx_hwapic_irr_update,
7597         .hwapic_isr_update = vmx_hwapic_isr_update,
7598
7599         .set_tss_addr = vmx_set_tss_addr,
7600         .get_tdp_level = get_ept_level,
7601         .get_mt_mask = vmx_get_mt_mask,
7602
7603         .get_exit_info = vmx_get_exit_info,
7604
7605         .get_lpage_level = vmx_get_lpage_level,
7606
7607         .cpuid_update = vmx_cpuid_update,
7608
7609         .rdtscp_supported = vmx_rdtscp_supported,
7610         .invpcid_supported = vmx_invpcid_supported,
7611
7612         .set_supported_cpuid = vmx_set_supported_cpuid,
7613
7614         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7615
7616         .set_tsc_khz = vmx_set_tsc_khz,
7617         .read_tsc_offset = vmx_read_tsc_offset,
7618         .write_tsc_offset = vmx_write_tsc_offset,
7619         .adjust_tsc_offset = vmx_adjust_tsc_offset,
7620         .compute_tsc_offset = vmx_compute_tsc_offset,
7621         .read_l1_tsc = vmx_read_l1_tsc,
7622
7623         .set_tdp_cr3 = vmx_set_cr3,
7624
7625         .check_intercept = vmx_check_intercept,
7626 };
7627
7628 static int __init vmx_init(void)
7629 {
7630         int r, i, msr;
7631
7632         rdmsrl_safe(MSR_EFER, &host_efer);
7633
7634         for (i = 0; i < NR_VMX_MSR; ++i)
7635                 kvm_define_shared_msr(i, vmx_msr_index[i]);
7636
7637         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
7638         if (!vmx_io_bitmap_a)
7639                 return -ENOMEM;
7640
7641         r = -ENOMEM;
7642
7643         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
7644         if (!vmx_io_bitmap_b)
7645                 goto out;
7646
7647         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
7648         if (!vmx_msr_bitmap_legacy)
7649                 goto out1;
7650
7651         vmx_msr_bitmap_legacy_x2apic =
7652                                 (unsigned long *)__get_free_page(GFP_KERNEL);
7653         if (!vmx_msr_bitmap_legacy_x2apic)
7654                 goto out2;
7655
7656         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
7657         if (!vmx_msr_bitmap_longmode)
7658                 goto out3;
7659
7660         vmx_msr_bitmap_longmode_x2apic =
7661                                 (unsigned long *)__get_free_page(GFP_KERNEL);
7662         if (!vmx_msr_bitmap_longmode_x2apic)
7663                 goto out4;
7664
7665         /*
7666          * Allow direct access to the PC debug port (it is often used for I/O
7667          * delays, but the vmexits simply slow things down).
7668          */
7669         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7670         clear_bit(0x80, vmx_io_bitmap_a);
7671
7672         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
7673
7674         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7675         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
7676
7677         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7678
7679         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7680                      __alignof__(struct vcpu_vmx), THIS_MODULE);
7681         if (r)
7682                 goto out3;
7683
7684 #ifdef CONFIG_KEXEC
7685         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
7686                            crash_vmclear_local_loaded_vmcss);
7687 #endif
7688
7689         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7690         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7691         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7692         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7693         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7694         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
7695         memcpy(vmx_msr_bitmap_legacy_x2apic,
7696                         vmx_msr_bitmap_legacy, PAGE_SIZE);
7697         memcpy(vmx_msr_bitmap_longmode_x2apic,
7698                         vmx_msr_bitmap_longmode, PAGE_SIZE);
7699
7700         if (enable_apicv_reg_vid) {
7701                 for (msr = 0x800; msr <= 0x8ff; msr++)
7702                         vmx_disable_intercept_msr_read_x2apic(msr);
7703
7704                 /* According SDM, in x2apic mode, the whole id reg is used.
7705                  * But in KVM, it only use the highest eight bits. Need to
7706                  * intercept it */
7707                 vmx_enable_intercept_msr_read_x2apic(0x802);
7708                 /* TMCCT */
7709                 vmx_enable_intercept_msr_read_x2apic(0x839);
7710                 /* TPR */
7711                 vmx_disable_intercept_msr_write_x2apic(0x808);
7712                 /* EOI */
7713                 vmx_disable_intercept_msr_write_x2apic(0x80b);
7714                 /* SELF-IPI */
7715                 vmx_disable_intercept_msr_write_x2apic(0x83f);
7716         }
7717
7718         if (enable_ept) {
7719                 kvm_mmu_set_mask_ptes(0ull,
7720                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
7721                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
7722                         0ull, VMX_EPT_EXECUTABLE_MASK);
7723                 ept_set_mmio_spte_mask();
7724                 kvm_enable_tdp();
7725         } else
7726                 kvm_disable_tdp();
7727
7728         return 0;
7729
7730 out4:
7731         free_page((unsigned long)vmx_msr_bitmap_longmode);
7732 out3:
7733         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
7734 out2:
7735         free_page((unsigned long)vmx_msr_bitmap_legacy);
7736 out1:
7737         free_page((unsigned long)vmx_io_bitmap_b);
7738 out:
7739         free_page((unsigned long)vmx_io_bitmap_a);
7740         return r;
7741 }
7742
7743 static void __exit vmx_exit(void)
7744 {
7745         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
7746         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
7747         free_page((unsigned long)vmx_msr_bitmap_legacy);
7748         free_page((unsigned long)vmx_msr_bitmap_longmode);
7749         free_page((unsigned long)vmx_io_bitmap_b);
7750         free_page((unsigned long)vmx_io_bitmap_a);
7751
7752 #ifdef CONFIG_KEXEC
7753         rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
7754         synchronize_rcu();
7755 #endif
7756
7757         kvm_exit();
7758 }
7759
7760 module_init(vmx_init)
7761 module_exit(vmx_exit)