arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21
  22 #include <linux/kvm_host.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/mm.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/ftrace_event.h>
  30 #include <linux/slab.h>
  31 #include <linux/tboot.h>
  32 #include "kvm_cache_regs.h"
  33 #include "x86.h"
  34
  35 #include <asm/io.h>
  36 #include <asm/desc.h>
  37 #include <asm/vmx.h>
  38 #include <asm/virtext.h>
  39 #include <asm/mce.h>
  40 #include <asm/i387.h>
  41 #include <asm/xcr.h>
  42
  43 #include "trace.h"
  44
  45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  46
  47 MODULE_AUTHOR("Qumranet");
  48 MODULE_LICENSE("GPL");
  49
  50 static int __read_mostly bypass_guest_pf = 1;
  51 module_param(bypass_guest_pf, bool, S_IRUGO);
  52
  53 static int __read_mostly enable_vpid = 1;
  54 module_param_named(vpid, enable_vpid, bool, 0444);
  55
  56 static int __read_mostly flexpriority_enabled = 1;
  57 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  58
  59 static int __read_mostly enable_ept = 1;
  60 module_param_named(ept, enable_ept, bool, S_IRUGO);
  61
  62 static int __read_mostly enable_unrestricted_guest = 1;
  63 module_param_named(unrestricted_guest,
  64                         enable_unrestricted_guest, bool, S_IRUGO);
  65
  66 static int __read_mostly emulate_invalid_guest_state = 0;
  67 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  68
  69 static int __read_mostly vmm_exclusive = 1;
  70 module_param(vmm_exclusive, bool, S_IRUGO);
  71
  72 static int __read_mostly yield_on_hlt = 1;
  73 module_param(yield_on_hlt, bool, S_IRUGO);
  74
  75 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  76         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
  77 #define KVM_GUEST_CR0_MASK                                              \
  78         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  79 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
  80         (X86_CR0_WP | X86_CR0_NE)
  81 #define KVM_VM_CR0_ALWAYS_ON                                            \
  82         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  83 #define KVM_CR4_GUEST_OWNED_BITS                                      \
  84         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
  85          | X86_CR4_OSXMMEXCPT)
  86
  87 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
  88 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
  89
  90 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
  91
  92 /*
  93  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
  94  * ple_gap:    upper bound on the amount of time between two successive
  95  *             executions of PAUSE in a loop. Also indicate if ple enabled.
  96  *             According to test, this time is usually smaller than 128 cycles.
  97  * ple_window: upper bound on the amount of time a guest is allowed to execute
  98  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
  99  *             less than 2^12 cycles
 100  * Time is measured based on a counter that runs at the same rate as the TSC,
 101  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 102  */
 103 #define KVM_VMX_DEFAULT_PLE_GAP    128
 104 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 105 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 106 module_param(ple_gap, int, S_IRUGO);
 107
 108 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 109 module_param(ple_window, int, S_IRUGO);
 110
 111 #define NR_AUTOLOAD_MSRS 1
 112
 113 struct vmcs {
 114         u32 revision_id;
 115         u32 abort;
 116         char data[0];
 117 };
 118
 119 struct shared_msr_entry {
 120         unsigned index;
 121         u64 data;
 122         u64 mask;
 123 };
 124
 125 struct vcpu_vmx {
 126         struct kvm_vcpu       vcpu;
 127         struct list_head      local_vcpus_link;
 128         unsigned long         host_rsp;
 129         int                   launched;
 130         u8                    fail;
 131         u32                   exit_intr_info;
 132         u32                   idt_vectoring_info;
 133         struct shared_msr_entry *guest_msrs;
 134         int                   nmsrs;
 135         int                   save_nmsrs;
 136 #ifdef CONFIG_X86_64
 137         u64                   msr_host_kernel_gs_base;
 138         u64                   msr_guest_kernel_gs_base;
 139 #endif
 140         struct vmcs          *vmcs;
 141         struct msr_autoload {
 142                 unsigned nr;
 143                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 144                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 145         } msr_autoload;
 146         struct {
 147                 int           loaded;
 148                 u16           fs_sel, gs_sel, ldt_sel;
 149                 int           gs_ldt_reload_needed;
 150                 int           fs_reload_needed;
 151         } host_state;
 152         struct {
 153                 int vm86_active;
 154                 ulong save_rflags;
 155                 struct kvm_save_segment {
 156                         u16 selector;
 157                         unsigned long base;
 158                         u32 limit;
 159                         u32 ar;
 160                 } tr, es, ds, fs, gs;
 161         } rmode;
 162         int vpid;
 163         bool emulation_required;
 164
 165         /* Support for vnmi-less CPUs */
 166         int soft_vnmi_blocked;
 167         ktime_t entry_time;
 168         s64 vnmi_blocked_time;
 169         u32 exit_reason;
 170
 171         bool rdtscp_enabled;
 172 };
 173
 174 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 175 {
 176         return container_of(vcpu, struct vcpu_vmx, vcpu);
 177 }
 178
 179 static u64 construct_eptp(unsigned long root_hpa);
 180 static void kvm_cpu_vmxon(u64 addr);
 181 static void kvm_cpu_vmxoff(void);
 182 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
 183
 184 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 185 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 186 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
 187 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 188
 189 static unsigned long *vmx_io_bitmap_a;
 190 static unsigned long *vmx_io_bitmap_b;
 191 static unsigned long *vmx_msr_bitmap_legacy;
 192 static unsigned long *vmx_msr_bitmap_longmode;
 193
 194 static bool cpu_has_load_ia32_efer;
 195
 196 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 197 static DEFINE_SPINLOCK(vmx_vpid_lock);
 198
 199 static struct vmcs_config {
 200         int size;
 201         int order;
 202         u32 revision_id;
 203         u32 pin_based_exec_ctrl;
 204         u32 cpu_based_exec_ctrl;
 205         u32 cpu_based_2nd_exec_ctrl;
 206         u32 vmexit_ctrl;
 207         u32 vmentry_ctrl;
 208 } vmcs_config;
 209
 210 static struct vmx_capability {
 211         u32 ept;
 212         u32 vpid;
 213 } vmx_capability;
 214
 215 #define VMX_SEGMENT_FIELD(seg)                                  \
 216         [VCPU_SREG_##seg] = {                                   \
 217                 .selector = GUEST_##seg##_SELECTOR,             \
 218                 .base = GUEST_##seg##_BASE,                     \
 219                 .limit = GUEST_##seg##_LIMIT,                   \
 220                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 221         }
 222
 223 static struct kvm_vmx_segment_field {
 224         unsigned selector;
 225         unsigned base;
 226         unsigned limit;
 227         unsigned ar_bytes;
 228 } kvm_vmx_segment_fields[] = {
 229         VMX_SEGMENT_FIELD(CS),
 230         VMX_SEGMENT_FIELD(DS),
 231         VMX_SEGMENT_FIELD(ES),
 232         VMX_SEGMENT_FIELD(FS),
 233         VMX_SEGMENT_FIELD(GS),
 234         VMX_SEGMENT_FIELD(SS),
 235         VMX_SEGMENT_FIELD(TR),
 236         VMX_SEGMENT_FIELD(LDTR),
 237 };
 238
 239 static u64 host_efer;
 240
 241 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 242
 243 /*
 244  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 245  * away by decrementing the array size.
 246  */
 247 static const u32 vmx_msr_index[] = {
 248 #ifdef CONFIG_X86_64
 249         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 250 #endif
 251         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 252 };
 253 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 254
 255 static inline bool is_page_fault(u32 intr_info)
 256 {
 257         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 258                              INTR_INFO_VALID_MASK)) ==
 259                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 260 }
 261
 262 static inline bool is_no_device(u32 intr_info)
 263 {
 264         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 265                              INTR_INFO_VALID_MASK)) ==
 266                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 267 }
 268
 269 static inline bool is_invalid_opcode(u32 intr_info)
 270 {
 271         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 272                              INTR_INFO_VALID_MASK)) ==
 273                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 274 }
 275
 276 static inline bool is_external_interrupt(u32 intr_info)
 277 {
 278         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 279                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 280 }
 281
 282 static inline bool is_machine_check(u32 intr_info)
 283 {
 284         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 285                              INTR_INFO_VALID_MASK)) ==
 286                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 287 }
 288
 289 static inline bool cpu_has_vmx_msr_bitmap(void)
 290 {
 291         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 292 }
 293
 294 static inline bool cpu_has_vmx_tpr_shadow(void)
 295 {
 296         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 297 }
 298
 299 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 300 {
 301         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 302 }
 303
 304 static inline bool cpu_has_secondary_exec_ctrls(void)
 305 {
 306         return vmcs_config.cpu_based_exec_ctrl &
 307                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 308 }
 309
 310 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 311 {
 312         return vmcs_config.cpu_based_2nd_exec_ctrl &
 313                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 314 }
 315
 316 static inline bool cpu_has_vmx_flexpriority(void)
 317 {
 318         return cpu_has_vmx_tpr_shadow() &&
 319                 cpu_has_vmx_virtualize_apic_accesses();
 320 }
 321
 322 static inline bool cpu_has_vmx_ept_execute_only(void)
 323 {
 324         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 325 }
 326
 327 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 328 {
 329         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 330 }
 331
 332 static inline bool cpu_has_vmx_eptp_writeback(void)
 333 {
 334         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 335 }
 336
 337 static inline bool cpu_has_vmx_ept_2m_page(void)
 338 {
 339         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 340 }
 341
 342 static inline bool cpu_has_vmx_ept_1g_page(void)
 343 {
 344         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 345 }
 346
 347 static inline bool cpu_has_vmx_ept_4levels(void)
 348 {
 349         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 350 }
 351
 352 static inline bool cpu_has_vmx_invept_individual_addr(void)
 353 {
 354         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
 355 }
 356
 357 static inline bool cpu_has_vmx_invept_context(void)
 358 {
 359         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 360 }
 361
 362 static inline bool cpu_has_vmx_invept_global(void)
 363 {
 364         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 365 }
 366
 367 static inline bool cpu_has_vmx_invvpid_single(void)
 368 {
 369         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 370 }
 371
 372 static inline bool cpu_has_vmx_invvpid_global(void)
 373 {
 374         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 375 }
 376
 377 static inline bool cpu_has_vmx_ept(void)
 378 {
 379         return vmcs_config.cpu_based_2nd_exec_ctrl &
 380                 SECONDARY_EXEC_ENABLE_EPT;
 381 }
 382
 383 static inline bool cpu_has_vmx_unrestricted_guest(void)
 384 {
 385         return vmcs_config.cpu_based_2nd_exec_ctrl &
 386                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 387 }
 388
 389 static inline bool cpu_has_vmx_ple(void)
 390 {
 391         return vmcs_config.cpu_based_2nd_exec_ctrl &
 392                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 393 }
 394
 395 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 396 {
 397         return flexpriority_enabled && irqchip_in_kernel(kvm);
 398 }
 399
 400 static inline bool cpu_has_vmx_vpid(void)
 401 {
 402         return vmcs_config.cpu_based_2nd_exec_ctrl &
 403                 SECONDARY_EXEC_ENABLE_VPID;
 404 }
 405
 406 static inline bool cpu_has_vmx_rdtscp(void)
 407 {
 408         return vmcs_config.cpu_based_2nd_exec_ctrl &
 409                 SECONDARY_EXEC_RDTSCP;
 410 }
 411
 412 static inline bool cpu_has_virtual_nmis(void)
 413 {
 414         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 415 }
 416
 417 static inline bool cpu_has_vmx_wbinvd_exit(void)
 418 {
 419         return vmcs_config.cpu_based_2nd_exec_ctrl &
 420                 SECONDARY_EXEC_WBINVD_EXITING;
 421 }
 422
 423 static inline bool report_flexpriority(void)
 424 {
 425         return flexpriority_enabled;
 426 }
 427
 428 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 429 {
 430         int i;
 431
 432         for (i = 0; i < vmx->nmsrs; ++i)
 433                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 434                         return i;
 435         return -1;
 436 }
 437
 438 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 439 {
 440     struct {
 441         u64 vpid : 16;
 442         u64 rsvd : 48;
 443         u64 gva;
 444     } operand = { vpid, 0, gva };
 445
 446     asm volatile (__ex(ASM_VMX_INVVPID)
 447                   /* CF==1 or ZF==1 --> rc = -1 */
 448                   "; ja 1f ; ud2 ; 1:"
 449                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 450 }
 451
 452 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 453 {
 454         struct {
 455                 u64 eptp, gpa;
 456         } operand = {eptp, gpa};
 457
 458         asm volatile (__ex(ASM_VMX_INVEPT)
 459                         /* CF==1 or ZF==1 --> rc = -1 */
 460                         "; ja 1f ; ud2 ; 1:\n"
 461                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 462 }
 463
 464 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 465 {
 466         int i;
 467
 468         i = __find_msr_index(vmx, msr);
 469         if (i >= 0)
 470                 return &vmx->guest_msrs[i];
 471         return NULL;
 472 }
 473
 474 static void vmcs_clear(struct vmcs *vmcs)
 475 {
 476         u64 phys_addr = __pa(vmcs);
 477         u8 error;
 478
 479         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 480                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 481                       : "cc", "memory");
 482         if (error)
 483                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 484                        vmcs, phys_addr);
 485 }
 486
 487 static void vmcs_load(struct vmcs *vmcs)
 488 {
 489         u64 phys_addr = __pa(vmcs);
 490         u8 error;
 491
 492         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 493                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 494                         : "cc", "memory");
 495         if (error)
 496                 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 497                        vmcs, phys_addr);
 498 }
 499
 500 static void __vcpu_clear(void *arg)
 501 {
 502         struct vcpu_vmx *vmx = arg;
 503         int cpu = raw_smp_processor_id();
 504
 505         if (vmx->vcpu.cpu == cpu)
 506                 vmcs_clear(vmx->vmcs);
 507         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 508                 per_cpu(current_vmcs, cpu) = NULL;
 509         list_del(&vmx->local_vcpus_link);
 510         vmx->vcpu.cpu = -1;
 511         vmx->launched = 0;
 512 }
 513
 514 static void vcpu_clear(struct vcpu_vmx *vmx)
 515 {
 516         if (vmx->vcpu.cpu == -1)
 517                 return;
 518         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 519 }
 520
 521 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
 522 {
 523         if (vmx->vpid == 0)
 524                 return;
 525
 526         if (cpu_has_vmx_invvpid_single())
 527                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 528 }
 529
 530 static inline void vpid_sync_vcpu_global(void)
 531 {
 532         if (cpu_has_vmx_invvpid_global())
 533                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
 534 }
 535
 536 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
 537 {
 538         if (cpu_has_vmx_invvpid_single())
 539                 vpid_sync_vcpu_single(vmx);
 540         else
 541                 vpid_sync_vcpu_global();
 542 }
 543
 544 static inline void ept_sync_global(void)
 545 {
 546         if (cpu_has_vmx_invept_global())
 547                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 548 }
 549
 550 static inline void ept_sync_context(u64 eptp)
 551 {
 552         if (enable_ept) {
 553                 if (cpu_has_vmx_invept_context())
 554                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 555                 else
 556                         ept_sync_global();
 557         }
 558 }
 559
 560 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 561 {
 562         if (enable_ept) {
 563                 if (cpu_has_vmx_invept_individual_addr())
 564                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 565                                         eptp, gpa);
 566                 else
 567                         ept_sync_context(eptp);
 568         }
 569 }
 570
 571 static unsigned long vmcs_readl(unsigned long field)
 572 {
 573         unsigned long value = 0;
 574
 575         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
 576                       : "+a"(value) : "d"(field) : "cc");
 577         return value;
 578 }
 579
 580 static u16 vmcs_read16(unsigned long field)
 581 {
 582         return vmcs_readl(field);
 583 }
 584
 585 static u32 vmcs_read32(unsigned long field)
 586 {
 587         return vmcs_readl(field);
 588 }
 589
 590 static u64 vmcs_read64(unsigned long field)
 591 {
 592 #ifdef CONFIG_X86_64
 593         return vmcs_readl(field);
 594 #else
 595         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 596 #endif
 597 }
 598
 599 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 600 {
 601         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 602                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 603         dump_stack();
 604 }
 605
 606 static void vmcs_writel(unsigned long field, unsigned long value)
 607 {
 608         u8 error;
 609
 610         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 611                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 612         if (unlikely(error))
 613                 vmwrite_error(field, value);
 614 }
 615
 616 static void vmcs_write16(unsigned long field, u16 value)
 617 {
 618         vmcs_writel(field, value);
 619 }
 620
 621 static void vmcs_write32(unsigned long field, u32 value)
 622 {
 623         vmcs_writel(field, value);
 624 }
 625
 626 static void vmcs_write64(unsigned long field, u64 value)
 627 {
 628         vmcs_writel(field, value);
 629 #ifndef CONFIG_X86_64
 630         asm volatile ("");
 631         vmcs_writel(field+1, value >> 32);
 632 #endif
 633 }
 634
 635 static void vmcs_clear_bits(unsigned long field, u32 mask)
 636 {
 637         vmcs_writel(field, vmcs_readl(field) & ~mask);
 638 }
 639
 640 static void vmcs_set_bits(unsigned long field, u32 mask)
 641 {
 642         vmcs_writel(field, vmcs_readl(field) | mask);
 643 }
 644
 645 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 646 {
 647         u32 eb;
 648
 649         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
 650              (1u << NM_VECTOR) | (1u << DB_VECTOR);
 651         if ((vcpu->guest_debug &
 652              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
 653             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
 654                 eb |= 1u << BP_VECTOR;
 655         if (to_vmx(vcpu)->rmode.vm86_active)
 656                 eb = ~0;
 657         if (enable_ept)
 658                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 659         if (vcpu->fpu_active)
 660                 eb &= ~(1u << NM_VECTOR);
 661         vmcs_write32(EXCEPTION_BITMAP, eb);
 662 }
 663
 664 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
 665 {
 666         unsigned i;
 667         struct msr_autoload *m = &vmx->msr_autoload;
 668
 669         if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
 670                 vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
 671                 vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
 672                 return;
 673         }
 674
 675         for (i = 0; i < m->nr; ++i)
 676                 if (m->guest[i].index == msr)
 677                         break;
 678
 679         if (i == m->nr)
 680                 return;
 681         --m->nr;
 682         m->guest[i] = m->guest[m->nr];
 683         m->host[i] = m->host[m->nr];
 684         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
 685         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
 686 }
 687
 688 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
 689                                   u64 guest_val, u64 host_val)
 690 {
 691         unsigned i;
 692         struct msr_autoload *m = &vmx->msr_autoload;
 693
 694         if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
 695                 vmcs_write64(GUEST_IA32_EFER, guest_val);
 696                 vmcs_write64(HOST_IA32_EFER, host_val);
 697                 vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
 698                 vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
 699                 return;
 700         }
 701
 702         for (i = 0; i < m->nr; ++i)
 703                 if (m->guest[i].index == msr)
 704                         break;
 705
 706         if (i == m->nr) {
 707                 ++m->nr;
 708                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
 709                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
 710         }
 711
 712         m->guest[i].index = msr;
 713         m->guest[i].value = guest_val;
 714         m->host[i].index = msr;
 715         m->host[i].value = host_val;
 716 }
 717
 718 static void reload_tss(void)
 719 {
 720         /*
 721          * VT restores TR but not its size.  Useless.
 722          */
 723         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
 724         struct desc_struct *descs;
 725
 726         descs = (void *)gdt->address;
 727         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 728         load_TR_desc();
 729 }
 730
 731 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
 732 {
 733         u64 guest_efer;
 734         u64 ignore_bits;
 735
 736         guest_efer = vmx->vcpu.arch.efer;
 737
 738         /*
 739          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 740          * outside long mode
 741          */
 742         ignore_bits = EFER_NX | EFER_SCE;
 743 #ifdef CONFIG_X86_64
 744         ignore_bits |= EFER_LMA | EFER_LME;
 745         /* SCE is meaningful only in long mode on Intel */
 746         if (guest_efer & EFER_LMA)
 747                 ignore_bits &= ~(u64)EFER_SCE;
 748 #endif
 749         guest_efer &= ~ignore_bits;
 750         guest_efer |= host_efer & ignore_bits;
 751         vmx->guest_msrs[efer_offset].data = guest_efer;
 752         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
 753
 754         clear_atomic_switch_msr(vmx, MSR_EFER);
 755         /* On ept, can't emulate nx, and must switch nx atomically */
 756         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
 757                 guest_efer = vmx->vcpu.arch.efer;
 758                 if (!(guest_efer & EFER_LMA))
 759                         guest_efer &= ~EFER_LME;
 760                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
 761                 return false;
 762         }
 763
 764         return true;
 765 }
 766
 767 static unsigned long segment_base(u16 selector)
 768 {
 769         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
 770         struct desc_struct *d;
 771         unsigned long table_base;
 772         unsigned long v;
 773
 774         if (!(selector & ~3))
 775                 return 0;
 776
 777         table_base = gdt->address;
 778
 779         if (selector & 4) {           /* from ldt */
 780                 u16 ldt_selector = kvm_read_ldt();
 781
 782                 if (!(ldt_selector & ~3))
 783                         return 0;
 784
 785                 table_base = segment_base(ldt_selector);
 786         }
 787         d = (struct desc_struct *)(table_base + (selector & ~7));
 788         v = get_desc_base(d);
 789 #ifdef CONFIG_X86_64
 790        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
 791                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
 792 #endif
 793         return v;
 794 }
 795
 796 static inline unsigned long kvm_read_tr_base(void)
 797 {
 798         u16 tr;
 799         asm("str %0" : "=g"(tr));
 800         return segment_base(tr);
 801 }
 802
 803 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 804 {
 805         struct vcpu_vmx *vmx = to_vmx(vcpu);
 806         int i;
 807
 808         if (vmx->host_state.loaded)
 809                 return;
 810
 811         vmx->host_state.loaded = 1;
 812         /*
 813          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 814          * allow segment selectors with cpl > 0 or ti == 1.
 815          */
 816         vmx->host_state.ldt_sel = kvm_read_ldt();
 817         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 818         savesegment(fs, vmx->host_state.fs_sel);
 819         if (!(vmx->host_state.fs_sel & 7)) {
 820                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 821                 vmx->host_state.fs_reload_needed = 0;
 822         } else {
 823                 vmcs_write16(HOST_FS_SELECTOR, 0);
 824                 vmx->host_state.fs_reload_needed = 1;
 825         }
 826         savesegment(gs, vmx->host_state.gs_sel);
 827         if (!(vmx->host_state.gs_sel & 7))
 828                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 829         else {
 830                 vmcs_write16(HOST_GS_SELECTOR, 0);
 831                 vmx->host_state.gs_ldt_reload_needed = 1;
 832         }
 833
 834 #ifdef CONFIG_X86_64
 835         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 836         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 837 #else
 838         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 839         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 840 #endif
 841
 842 #ifdef CONFIG_X86_64
 843         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 844         if (is_long_mode(&vmx->vcpu))
 845                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 846 #endif
 847         for (i = 0; i < vmx->save_nmsrs; ++i)
 848                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
 849                                    vmx->guest_msrs[i].data,
 850                                    vmx->guest_msrs[i].mask);
 851 }
 852
 853 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 854 {
 855         if (!vmx->host_state.loaded)
 856                 return;
 857
 858         ++vmx->vcpu.stat.host_state_reload;
 859         vmx->host_state.loaded = 0;
 860 #ifdef CONFIG_X86_64
 861         if (is_long_mode(&vmx->vcpu))
 862                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 863 #endif
 864         if (vmx->host_state.gs_ldt_reload_needed) {
 865                 kvm_load_ldt(vmx->host_state.ldt_sel);
 866 #ifdef CONFIG_X86_64
 867                 load_gs_index(vmx->host_state.gs_sel);
 868 #else
 869                 loadsegment(gs, vmx->host_state.gs_sel);
 870 #endif
 871         }
 872         if (vmx->host_state.fs_reload_needed)
 873                 loadsegment(fs, vmx->host_state.fs_sel);
 874         reload_tss();
 875 #ifdef CONFIG_X86_64
 876         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 877 #endif
 878         if (current_thread_info()->status & TS_USEDFPU)
 879                 clts();
 880         load_gdt(&__get_cpu_var(host_gdt));
 881 }
 882
 883 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 884 {
 885         preempt_disable();
 886         __vmx_load_host_state(vmx);
 887         preempt_enable();
 888 }
 889
 890 /*
 891  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 892  * vcpu mutex is already taken.
 893  */
 894 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 895 {
 896         struct vcpu_vmx *vmx = to_vmx(vcpu);
 897         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
 898
 899         if (!vmm_exclusive)
 900                 kvm_cpu_vmxon(phys_addr);
 901         else if (vcpu->cpu != cpu)
 902                 vcpu_clear(vmx);
 903
 904         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 905                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 906                 vmcs_load(vmx->vmcs);
 907         }
 908
 909         if (vcpu->cpu != cpu) {
 910                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
 911                 unsigned long sysenter_esp;
 912
 913                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
 914                 local_irq_disable();
 915                 list_add(&vmx->local_vcpus_link,
 916                          &per_cpu(vcpus_on_cpu, cpu));
 917                 local_irq_enable();
 918
 919                 /*
 920                  * Linux uses per-cpu TSS and GDT, so set these when switching
 921                  * processors.
 922                  */
 923                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
 924                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
 925
 926                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 927                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 928         }
 929 }
 930
 931 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 932 {
 933         __vmx_load_host_state(to_vmx(vcpu));
 934         if (!vmm_exclusive) {
 935                 __vcpu_clear(to_vmx(vcpu));
 936                 kvm_cpu_vmxoff();
 937         }
 938 }
 939
 940 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 941 {
 942         ulong cr0;
 943
 944         if (vcpu->fpu_active)
 945                 return;
 946         vcpu->fpu_active = 1;
 947         cr0 = vmcs_readl(GUEST_CR0);
 948         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
 949         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
 950         vmcs_writel(GUEST_CR0, cr0);
 951         update_exception_bitmap(vcpu);
 952         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
 953         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
 954 }
 955
 956 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
 957
 958 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 959 {
 960         vmx_decache_cr0_guest_bits(vcpu);
 961         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
 962         update_exception_bitmap(vcpu);
 963         vcpu->arch.cr0_guest_owned_bits = 0;
 964         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
 965         vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
 966 }
 967
 968 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 969 {
 970         unsigned long rflags, save_rflags;
 971
 972         rflags = vmcs_readl(GUEST_RFLAGS);
 973         if (to_vmx(vcpu)->rmode.vm86_active) {
 974                 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
 975                 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
 976                 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
 977         }
 978         return rflags;
 979 }
 980
 981 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 982 {
 983         if (to_vmx(vcpu)->rmode.vm86_active) {
 984                 to_vmx(vcpu)->rmode.save_rflags = rflags;
 985                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 986         }
 987         vmcs_writel(GUEST_RFLAGS, rflags);
 988 }
 989
 990 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 991 {
 992         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 993         int ret = 0;
 994
 995         if (interruptibility & GUEST_INTR_STATE_STI)
 996                 ret |= KVM_X86_SHADOW_INT_STI;
 997         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
 998                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
 999
1000         return ret & mask;
1001 }
1002
1003 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1004 {
1005         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1006         u32 interruptibility = interruptibility_old;
1007
1008         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1009
1010         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1011                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1012         else if (mask & KVM_X86_SHADOW_INT_STI)
1013                 interruptibility |= GUEST_INTR_STATE_STI;
1014
1015         if ((interruptibility != interruptibility_old))
1016                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1017 }
1018
1019 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1020 {
1021         unsigned long rip;
1022
1023         rip = kvm_rip_read(vcpu);
1024         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1025         kvm_rip_write(vcpu, rip);
1026
1027         /* skipping an emulated instruction also counts */
1028         vmx_set_interrupt_shadow(vcpu, 0);
1029 }
1030
1031 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1032 {
1033         /* Ensure that we clear the HLT state in the VMCS.  We don't need to
1034          * explicitly skip the instruction because if the HLT state is set, then
1035          * the instruction is already executing and RIP has already been
1036          * advanced. */
1037         if (!yield_on_hlt &&
1038             vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1039                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1040 }
1041
1042 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1043                                 bool has_error_code, u32 error_code,
1044                                 bool reinject)
1045 {
1046         struct vcpu_vmx *vmx = to_vmx(vcpu);
1047         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1048
1049         if (has_error_code) {
1050                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1051                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1052         }
1053
1054         if (vmx->rmode.vm86_active) {
1055                 if (kvm_inject_realmode_interrupt(vcpu, nr) != EMULATE_DONE)
1056                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1057                 return;
1058         }
1059
1060         if (kvm_exception_is_soft(nr)) {
1061                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1062                              vmx->vcpu.arch.event_exit_inst_len);
1063                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1064         } else
1065                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1066
1067         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1068         vmx_clear_hlt(vcpu);
1069 }
1070
1071 static bool vmx_rdtscp_supported(void)
1072 {
1073         return cpu_has_vmx_rdtscp();
1074 }
1075
1076 /*
1077  * Swap MSR entry in host/guest MSR entry array.
1078  */
1079 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1080 {
1081         struct shared_msr_entry tmp;
1082
1083         tmp = vmx->guest_msrs[to];
1084         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1085         vmx->guest_msrs[from] = tmp;
1086 }
1087
1088 /*
1089  * Set up the vmcs to automatically save and restore system
1090  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1091  * mode, as fiddling with msrs is very expensive.
1092  */
1093 static void setup_msrs(struct vcpu_vmx *vmx)
1094 {
1095         int save_nmsrs, index;
1096         unsigned long *msr_bitmap;
1097
1098         vmx_load_host_state(vmx);
1099         save_nmsrs = 0;
1100 #ifdef CONFIG_X86_64
1101         if (is_long_mode(&vmx->vcpu)) {
1102                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1103                 if (index >= 0)
1104                         move_msr_up(vmx, index, save_nmsrs++);
1105                 index = __find_msr_index(vmx, MSR_LSTAR);
1106                 if (index >= 0)
1107                         move_msr_up(vmx, index, save_nmsrs++);
1108                 index = __find_msr_index(vmx, MSR_CSTAR);
1109                 if (index >= 0)
1110                         move_msr_up(vmx, index, save_nmsrs++);
1111                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1112                 if (index >= 0 && vmx->rdtscp_enabled)
1113                         move_msr_up(vmx, index, save_nmsrs++);
1114                 /*
1115                  * MSR_STAR is only needed on long mode guests, and only
1116                  * if efer.sce is enabled.
1117                  */
1118                 index = __find_msr_index(vmx, MSR_STAR);
1119                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1120                         move_msr_up(vmx, index, save_nmsrs++);
1121         }
1122 #endif
1123         index = __find_msr_index(vmx, MSR_EFER);
1124         if (index >= 0 && update_transition_efer(vmx, index))
1125                 move_msr_up(vmx, index, save_nmsrs++);
1126
1127         vmx->save_nmsrs = save_nmsrs;
1128
1129         if (cpu_has_vmx_msr_bitmap()) {
1130                 if (is_long_mode(&vmx->vcpu))
1131                         msr_bitmap = vmx_msr_bitmap_longmode;
1132                 else
1133                         msr_bitmap = vmx_msr_bitmap_legacy;
1134
1135                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1136         }
1137 }
1138
1139 /*
1140  * reads and returns guest's timestamp counter "register"
1141  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1142  */
1143 static u64 guest_read_tsc(void)
1144 {
1145         u64 host_tsc, tsc_offset;
1146
1147         rdtscll(host_tsc);
1148         tsc_offset = vmcs_read64(TSC_OFFSET);
1149         return host_tsc + tsc_offset;
1150 }
1151
1152 /*
1153  * writes 'offset' into guest's timestamp counter offset register
1154  */
1155 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1156 {
1157         vmcs_write64(TSC_OFFSET, offset);
1158 }
1159
1160 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1161 {
1162         u64 offset = vmcs_read64(TSC_OFFSET);
1163         vmcs_write64(TSC_OFFSET, offset + adjustment);
1164 }
1165
1166 /*
1167  * Reads an msr value (of 'msr_index') into 'pdata'.
1168  * Returns 0 on success, non-0 otherwise.
1169  * Assumes vcpu_load() was already called.
1170  */
1171 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1172 {
1173         u64 data;
1174         struct shared_msr_entry *msr;
1175
1176         if (!pdata) {
1177                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1178                 return -EINVAL;
1179         }
1180
1181         switch (msr_index) {
1182 #ifdef CONFIG_X86_64
1183         case MSR_FS_BASE:
1184                 data = vmcs_readl(GUEST_FS_BASE);
1185                 break;
1186         case MSR_GS_BASE:
1187                 data = vmcs_readl(GUEST_GS_BASE);
1188                 break;
1189         case MSR_KERNEL_GS_BASE:
1190                 vmx_load_host_state(to_vmx(vcpu));
1191                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1192                 break;
1193 #endif
1194         case MSR_EFER:
1195                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1196         case MSR_IA32_TSC:
1197                 data = guest_read_tsc();
1198                 break;
1199         case MSR_IA32_SYSENTER_CS:
1200                 data = vmcs_read32(GUEST_SYSENTER_CS);
1201                 break;
1202         case MSR_IA32_SYSENTER_EIP:
1203                 data = vmcs_readl(GUEST_SYSENTER_EIP);
1204                 break;
1205         case MSR_IA32_SYSENTER_ESP:
1206                 data = vmcs_readl(GUEST_SYSENTER_ESP);
1207                 break;
1208         case MSR_TSC_AUX:
1209                 if (!to_vmx(vcpu)->rdtscp_enabled)
1210                         return 1;
1211                 /* Otherwise falls through */
1212         default:
1213                 vmx_load_host_state(to_vmx(vcpu));
1214                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1215                 if (msr) {
1216                         vmx_load_host_state(to_vmx(vcpu));
1217                         data = msr->data;
1218                         break;
1219                 }
1220                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1221         }
1222
1223         *pdata = data;
1224         return 0;
1225 }
1226
1227 /*
1228  * Writes msr value into into the appropriate "register".
1229  * Returns 0 on success, non-0 otherwise.
1230  * Assumes vcpu_load() was already called.
1231  */
1232 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1233 {
1234         struct vcpu_vmx *vmx = to_vmx(vcpu);
1235         struct shared_msr_entry *msr;
1236         int ret = 0;
1237
1238         switch (msr_index) {
1239         case MSR_EFER:
1240                 vmx_load_host_state(vmx);
1241                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1242                 break;
1243 #ifdef CONFIG_X86_64
1244         case MSR_FS_BASE:
1245                 vmcs_writel(GUEST_FS_BASE, data);
1246                 break;
1247         case MSR_GS_BASE:
1248                 vmcs_writel(GUEST_GS_BASE, data);
1249                 break;
1250         case MSR_KERNEL_GS_BASE:
1251                 vmx_load_host_state(vmx);
1252                 vmx->msr_guest_kernel_gs_base = data;
1253                 break;
1254 #endif
1255         case MSR_IA32_SYSENTER_CS:
1256                 vmcs_write32(GUEST_SYSENTER_CS, data);
1257                 break;
1258         case MSR_IA32_SYSENTER_EIP:
1259                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1260                 break;
1261         case MSR_IA32_SYSENTER_ESP:
1262                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1263                 break;
1264         case MSR_IA32_TSC:
1265                 kvm_write_tsc(vcpu, data);
1266                 break;
1267         case MSR_IA32_CR_PAT:
1268                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1269                         vmcs_write64(GUEST_IA32_PAT, data);
1270                         vcpu->arch.pat = data;
1271                         break;
1272                 }
1273                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1274                 break;
1275         case MSR_TSC_AUX:
1276                 if (!vmx->rdtscp_enabled)
1277                         return 1;
1278                 /* Check reserved bit, higher 32 bits should be zero */
1279                 if ((data >> 32) != 0)
1280                         return 1;
1281                 /* Otherwise falls through */
1282         default:
1283                 msr = find_msr_entry(vmx, msr_index);
1284                 if (msr) {
1285                         vmx_load_host_state(vmx);
1286                         msr->data = data;
1287                         break;
1288                 }
1289                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1290         }
1291
1292         return ret;
1293 }
1294
1295 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1296 {
1297         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1298         switch (reg) {
1299         case VCPU_REGS_RSP:
1300                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1301                 break;
1302         case VCPU_REGS_RIP:
1303                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1304                 break;
1305         case VCPU_EXREG_PDPTR:
1306                 if (enable_ept)
1307                         ept_save_pdptrs(vcpu);
1308                 break;
1309         default:
1310                 break;
1311         }
1312 }
1313
1314 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1315 {
1316         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1317                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1318         else
1319                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1320
1321         update_exception_bitmap(vcpu);
1322 }
1323
1324 static __init int cpu_has_kvm_support(void)
1325 {
1326         return cpu_has_vmx();
1327 }
1328
1329 static __init int vmx_disabled_by_bios(void)
1330 {
1331         u64 msr;
1332
1333         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1334         if (msr & FEATURE_CONTROL_LOCKED) {
1335                 /* launched w/ TXT and VMX disabled */
1336                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1337                         && tboot_enabled())
1338                         return 1;
1339                 /* launched w/o TXT and VMX only enabled w/ TXT */
1340                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1341                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1342                         && !tboot_enabled()) {
1343                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
1344                                 "activate TXT before enabling KVM\n");
1345                         return 1;
1346                 }
1347                 /* launched w/o TXT and VMX disabled */
1348                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1349                         && !tboot_enabled())
1350                         return 1;
1351         }
1352
1353         return 0;
1354 }
1355
1356 static void kvm_cpu_vmxon(u64 addr)
1357 {
1358         asm volatile (ASM_VMX_VMXON_RAX
1359                         : : "a"(&addr), "m"(addr)
1360                         : "memory", "cc");
1361 }
1362
1363 static int hardware_enable(void *garbage)
1364 {
1365         int cpu = raw_smp_processor_id();
1366         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1367         u64 old, test_bits;
1368
1369         if (read_cr4() & X86_CR4_VMXE)
1370                 return -EBUSY;
1371
1372         INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1373         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1374
1375         test_bits = FEATURE_CONTROL_LOCKED;
1376         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1377         if (tboot_enabled())
1378                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1379
1380         if ((old & test_bits) != test_bits) {
1381                 /* enable and lock */
1382                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1383         }
1384         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1385
1386         if (vmm_exclusive) {
1387                 kvm_cpu_vmxon(phys_addr);
1388                 ept_sync_global();
1389         }
1390
1391         store_gdt(&__get_cpu_var(host_gdt));
1392
1393         return 0;
1394 }
1395
1396 static void vmclear_local_vcpus(void)
1397 {
1398         int cpu = raw_smp_processor_id();
1399         struct vcpu_vmx *vmx, *n;
1400
1401         list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1402                                  local_vcpus_link)
1403                 __vcpu_clear(vmx);
1404 }
1405
1406
1407 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1408  * tricks.
1409  */
1410 static void kvm_cpu_vmxoff(void)
1411 {
1412         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1413 }
1414
1415 static void hardware_disable(void *garbage)
1416 {
1417         if (vmm_exclusive) {
1418                 vmclear_local_vcpus();
1419                 kvm_cpu_vmxoff();
1420         }
1421         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1422 }
1423
1424 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1425                                       u32 msr, u32 *result)
1426 {
1427         u32 vmx_msr_low, vmx_msr_high;
1428         u32 ctl = ctl_min | ctl_opt;
1429
1430         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1431
1432         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1433         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1434
1435         /* Ensure minimum (required) set of control bits are supported. */
1436         if (ctl_min & ~ctl)
1437                 return -EIO;
1438
1439         *result = ctl;
1440         return 0;
1441 }
1442
1443 static __init bool allow_1_setting(u32 msr, u32 ctl)
1444 {
1445         u32 vmx_msr_low, vmx_msr_high;
1446
1447         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1448         return vmx_msr_high & ctl;
1449 }
1450
1451 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1452 {
1453         u32 vmx_msr_low, vmx_msr_high;
1454         u32 min, opt, min2, opt2;
1455         u32 _pin_based_exec_control = 0;
1456         u32 _cpu_based_exec_control = 0;
1457         u32 _cpu_based_2nd_exec_control = 0;
1458         u32 _vmexit_control = 0;
1459         u32 _vmentry_control = 0;
1460
1461         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1462         opt = PIN_BASED_VIRTUAL_NMIS;
1463         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1464                                 &_pin_based_exec_control) < 0)
1465                 return -EIO;
1466
1467         min =
1468 #ifdef CONFIG_X86_64
1469               CPU_BASED_CR8_LOAD_EXITING |
1470               CPU_BASED_CR8_STORE_EXITING |
1471 #endif
1472               CPU_BASED_CR3_LOAD_EXITING |
1473               CPU_BASED_CR3_STORE_EXITING |
1474               CPU_BASED_USE_IO_BITMAPS |
1475               CPU_BASED_MOV_DR_EXITING |
1476               CPU_BASED_USE_TSC_OFFSETING |
1477               CPU_BASED_MWAIT_EXITING |
1478               CPU_BASED_MONITOR_EXITING |
1479               CPU_BASED_INVLPG_EXITING;
1480
1481         if (yield_on_hlt)
1482                 min |= CPU_BASED_HLT_EXITING;
1483
1484         opt = CPU_BASED_TPR_SHADOW |
1485               CPU_BASED_USE_MSR_BITMAPS |
1486               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1487         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1488                                 &_cpu_based_exec_control) < 0)
1489                 return -EIO;
1490 #ifdef CONFIG_X86_64
1491         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1492                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1493                                            ~CPU_BASED_CR8_STORE_EXITING;
1494 #endif
1495         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1496                 min2 = 0;
1497                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1498                         SECONDARY_EXEC_WBINVD_EXITING |
1499                         SECONDARY_EXEC_ENABLE_VPID |
1500                         SECONDARY_EXEC_ENABLE_EPT |
1501                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
1502                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1503                         SECONDARY_EXEC_RDTSCP;
1504                 if (adjust_vmx_controls(min2, opt2,
1505                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1506                                         &_cpu_based_2nd_exec_control) < 0)
1507                         return -EIO;
1508         }
1509 #ifndef CONFIG_X86_64
1510         if (!(_cpu_based_2nd_exec_control &
1511                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1512                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1513 #endif
1514         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1515                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1516                    enabled */
1517                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1518                                              CPU_BASED_CR3_STORE_EXITING |
1519                                              CPU_BASED_INVLPG_EXITING);
1520                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1521                       vmx_capability.ept, vmx_capability.vpid);
1522         }
1523
1524         min = 0;
1525 #ifdef CONFIG_X86_64
1526         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1527 #endif
1528         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1529         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1530                                 &_vmexit_control) < 0)
1531                 return -EIO;
1532
1533         min = 0;
1534         opt = VM_ENTRY_LOAD_IA32_PAT;
1535         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1536                                 &_vmentry_control) < 0)
1537                 return -EIO;
1538
1539         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1540
1541         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1542         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1543                 return -EIO;
1544
1545 #ifdef CONFIG_X86_64
1546         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1547         if (vmx_msr_high & (1u<<16))
1548                 return -EIO;
1549 #endif
1550
1551         /* Require Write-Back (WB) memory type for VMCS accesses. */
1552         if (((vmx_msr_high >> 18) & 15) != 6)
1553                 return -EIO;
1554
1555         vmcs_conf->size = vmx_msr_high & 0x1fff;
1556         vmcs_conf->order = get_order(vmcs_config.size);
1557         vmcs_conf->revision_id = vmx_msr_low;
1558
1559         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1560         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1561         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1562         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1563         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1564
1565         cpu_has_load_ia32_efer =
1566                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
1567                                 VM_ENTRY_LOAD_IA32_EFER)
1568                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
1569                                    VM_EXIT_LOAD_IA32_EFER);
1570
1571         return 0;
1572 }
1573
1574 static struct vmcs *alloc_vmcs_cpu(int cpu)
1575 {
1576         int node = cpu_to_node(cpu);
1577         struct page *pages;
1578         struct vmcs *vmcs;
1579
1580         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1581         if (!pages)
1582                 return NULL;
1583         vmcs = page_address(pages);
1584         memset(vmcs, 0, vmcs_config.size);
1585         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1586         return vmcs;
1587 }
1588
1589 static struct vmcs *alloc_vmcs(void)
1590 {
1591         return alloc_vmcs_cpu(raw_smp_processor_id());
1592 }
1593
1594 static void free_vmcs(struct vmcs *vmcs)
1595 {
1596         free_pages((unsigned long)vmcs, vmcs_config.order);
1597 }
1598
1599 static void free_kvm_area(void)
1600 {
1601         int cpu;
1602
1603         for_each_possible_cpu(cpu) {
1604                 free_vmcs(per_cpu(vmxarea, cpu));
1605                 per_cpu(vmxarea, cpu) = NULL;
1606         }
1607 }
1608
1609 static __init int alloc_kvm_area(void)
1610 {
1611         int cpu;
1612
1613         for_each_possible_cpu(cpu) {
1614                 struct vmcs *vmcs;
1615
1616                 vmcs = alloc_vmcs_cpu(cpu);
1617                 if (!vmcs) {
1618                         free_kvm_area();
1619                         return -ENOMEM;
1620                 }
1621
1622                 per_cpu(vmxarea, cpu) = vmcs;
1623         }
1624         return 0;
1625 }
1626
1627 static __init int hardware_setup(void)
1628 {
1629         if (setup_vmcs_config(&vmcs_config) < 0)
1630                 return -EIO;
1631
1632         if (boot_cpu_has(X86_FEATURE_NX))
1633                 kvm_enable_efer_bits(EFER_NX);
1634
1635         if (!cpu_has_vmx_vpid())
1636                 enable_vpid = 0;
1637
1638         if (!cpu_has_vmx_ept() ||
1639             !cpu_has_vmx_ept_4levels()) {
1640                 enable_ept = 0;
1641                 enable_unrestricted_guest = 0;
1642         }
1643
1644         if (!cpu_has_vmx_unrestricted_guest())
1645                 enable_unrestricted_guest = 0;
1646
1647         if (!cpu_has_vmx_flexpriority())
1648                 flexpriority_enabled = 0;
1649
1650         if (!cpu_has_vmx_tpr_shadow())
1651                 kvm_x86_ops->update_cr8_intercept = NULL;
1652
1653         if (enable_ept && !cpu_has_vmx_ept_2m_page())
1654                 kvm_disable_largepages();
1655
1656         if (!cpu_has_vmx_ple())
1657                 ple_gap = 0;
1658
1659         return alloc_kvm_area();
1660 }
1661
1662 static __exit void hardware_unsetup(void)
1663 {
1664         free_kvm_area();
1665 }
1666
1667 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1668 {
1669         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1670
1671         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1672                 vmcs_write16(sf->selector, save->selector);
1673                 vmcs_writel(sf->base, save->base);
1674                 vmcs_write32(sf->limit, save->limit);
1675                 vmcs_write32(sf->ar_bytes, save->ar);
1676         } else {
1677                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1678                         << AR_DPL_SHIFT;
1679                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1680         }
1681 }
1682
1683 static void enter_pmode(struct kvm_vcpu *vcpu)
1684 {
1685         unsigned long flags;
1686         struct vcpu_vmx *vmx = to_vmx(vcpu);
1687
1688         vmx->emulation_required = 1;
1689         vmx->rmode.vm86_active = 0;
1690
1691         vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
1692         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1693         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1694         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1695
1696         flags = vmcs_readl(GUEST_RFLAGS);
1697         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1698         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1699         vmcs_writel(GUEST_RFLAGS, flags);
1700
1701         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1702                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1703
1704         update_exception_bitmap(vcpu);
1705
1706         if (emulate_invalid_guest_state)
1707                 return;
1708
1709         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1710         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1711         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1712         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1713
1714         vmcs_write16(GUEST_SS_SELECTOR, 0);
1715         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1716
1717         vmcs_write16(GUEST_CS_SELECTOR,
1718                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1719         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1720 }
1721
1722 static gva_t rmode_tss_base(struct kvm *kvm)
1723 {
1724         if (!kvm->arch.tss_addr) {
1725                 struct kvm_memslots *slots;
1726                 gfn_t base_gfn;
1727
1728                 slots = kvm_memslots(kvm);
1729                 base_gfn = slots->memslots[0].base_gfn +
1730                                  kvm->memslots->memslots[0].npages - 3;
1731                 return base_gfn << PAGE_SHIFT;
1732         }
1733         return kvm->arch.tss_addr;
1734 }
1735
1736 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1737 {
1738         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1739
1740         save->selector = vmcs_read16(sf->selector);
1741         save->base = vmcs_readl(sf->base);
1742         save->limit = vmcs_read32(sf->limit);
1743         save->ar = vmcs_read32(sf->ar_bytes);
1744         vmcs_write16(sf->selector, save->base >> 4);
1745         vmcs_write32(sf->base, save->base & 0xffff0);
1746         vmcs_write32(sf->limit, 0xffff);
1747         vmcs_write32(sf->ar_bytes, 0xf3);
1748         if (save->base & 0xf)
1749                 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
1750                             " aligned when entering protected mode (seg=%d)",
1751                             seg);
1752 }
1753
1754 static void enter_rmode(struct kvm_vcpu *vcpu)
1755 {
1756         unsigned long flags;
1757         struct vcpu_vmx *vmx = to_vmx(vcpu);
1758
1759         if (enable_unrestricted_guest)
1760                 return;
1761
1762         vmx->emulation_required = 1;
1763         vmx->rmode.vm86_active = 1;
1764
1765         vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
1766         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1767         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1768
1769         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1770         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1771
1772         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1773         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1774
1775         flags = vmcs_readl(GUEST_RFLAGS);
1776         vmx->rmode.save_rflags = flags;
1777
1778         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1779
1780         vmcs_writel(GUEST_RFLAGS, flags);
1781         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1782         update_exception_bitmap(vcpu);
1783
1784         if (emulate_invalid_guest_state)
1785                 goto continue_rmode;
1786
1787         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1788         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1789         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1790
1791         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1792         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1793         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1794                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1795         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1796
1797         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1798         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1799         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1800         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1801
1802 continue_rmode:
1803         kvm_mmu_reset_context(vcpu);
1804 }
1805
1806 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1807 {
1808         struct vcpu_vmx *vmx = to_vmx(vcpu);
1809         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1810
1811         if (!msr)
1812                 return;
1813
1814         /*
1815          * Force kernel_gs_base reloading before EFER changes, as control
1816          * of this msr depends on is_long_mode().
1817          */
1818         vmx_load_host_state(to_vmx(vcpu));
1819         vcpu->arch.efer = efer;
1820         if (efer & EFER_LMA) {
1821                 vmcs_write32(VM_ENTRY_CONTROLS,
1822                              vmcs_read32(VM_ENTRY_CONTROLS) |
1823                              VM_ENTRY_IA32E_MODE);
1824                 msr->data = efer;
1825         } else {
1826                 vmcs_write32(VM_ENTRY_CONTROLS,
1827                              vmcs_read32(VM_ENTRY_CONTROLS) &
1828                              ~VM_ENTRY_IA32E_MODE);
1829
1830                 msr->data = efer & ~EFER_LME;
1831         }
1832         setup_msrs(vmx);
1833 }
1834
1835 #ifdef CONFIG_X86_64
1836
1837 static void enter_lmode(struct kvm_vcpu *vcpu)
1838 {
1839         u32 guest_tr_ar;
1840
1841         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1842         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1843                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1844                        __func__);
1845                 vmcs_write32(GUEST_TR_AR_BYTES,
1846                              (guest_tr_ar & ~AR_TYPE_MASK)
1847                              | AR_TYPE_BUSY_64_TSS);
1848         }
1849         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
1850 }
1851
1852 static void exit_lmode(struct kvm_vcpu *vcpu)
1853 {
1854         vmcs_write32(VM_ENTRY_CONTROLS,
1855                      vmcs_read32(VM_ENTRY_CONTROLS)
1856                      & ~VM_ENTRY_IA32E_MODE);
1857         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
1858 }
1859
1860 #endif
1861
1862 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1863 {
1864         vpid_sync_context(to_vmx(vcpu));
1865         if (enable_ept) {
1866                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
1867                         return;
1868                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1869         }
1870 }
1871
1872 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1873 {
1874         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1875
1876         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1877         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1878 }
1879
1880 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
1881 {
1882         if (enable_ept && is_paging(vcpu))
1883                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1884         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
1885 }
1886
1887 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1888 {
1889         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1890
1891         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1892         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
1893 }
1894
1895 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1896 {
1897         if (!test_bit(VCPU_EXREG_PDPTR,
1898                       (unsigned long *)&vcpu->arch.regs_dirty))
1899                 return;
1900
1901         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1902                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
1903                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
1904                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
1905                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1906         }
1907 }
1908
1909 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1910 {
1911         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1912                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1913                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1914                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1915                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1916         }
1917
1918         __set_bit(VCPU_EXREG_PDPTR,
1919                   (unsigned long *)&vcpu->arch.regs_avail);
1920         __set_bit(VCPU_EXREG_PDPTR,
1921                   (unsigned long *)&vcpu->arch.regs_dirty);
1922 }
1923
1924 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1925
1926 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1927                                         unsigned long cr0,
1928                                         struct kvm_vcpu *vcpu)
1929 {
1930         vmx_decache_cr3(vcpu);
1931         if (!(cr0 & X86_CR0_PG)) {
1932                 /* From paging/starting to nonpaging */
1933                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1934                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1935                              (CPU_BASED_CR3_LOAD_EXITING |
1936                               CPU_BASED_CR3_STORE_EXITING));
1937                 vcpu->arch.cr0 = cr0;
1938                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1939         } else if (!is_paging(vcpu)) {
1940                 /* From nonpaging to paging */
1941                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1942                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1943                              ~(CPU_BASED_CR3_LOAD_EXITING |
1944                                CPU_BASED_CR3_STORE_EXITING));
1945                 vcpu->arch.cr0 = cr0;
1946                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1947         }
1948
1949         if (!(cr0 & X86_CR0_WP))
1950                 *hw_cr0 &= ~X86_CR0_WP;
1951 }
1952
1953 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1954 {
1955         struct vcpu_vmx *vmx = to_vmx(vcpu);
1956         unsigned long hw_cr0;
1957
1958         if (enable_unrestricted_guest)
1959                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1960                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1961         else
1962                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1963
1964         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1965                 enter_pmode(vcpu);
1966
1967         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1968                 enter_rmode(vcpu);
1969
1970 #ifdef CONFIG_X86_64
1971         if (vcpu->arch.efer & EFER_LME) {
1972                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1973                         enter_lmode(vcpu);
1974                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1975                         exit_lmode(vcpu);
1976         }
1977 #endif
1978
1979         if (enable_ept)
1980                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1981
1982         if (!vcpu->fpu_active)
1983                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
1984
1985         vmcs_writel(CR0_READ_SHADOW, cr0);
1986         vmcs_writel(GUEST_CR0, hw_cr0);
1987         vcpu->arch.cr0 = cr0;
1988 }
1989
1990 static u64 construct_eptp(unsigned long root_hpa)
1991 {
1992         u64 eptp;
1993
1994         /* TODO write the value reading from MSR */
1995         eptp = VMX_EPT_DEFAULT_MT |
1996                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1997         eptp |= (root_hpa & PAGE_MASK);
1998
1999         return eptp;
2000 }
2001
2002 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2003 {
2004         unsigned long guest_cr3;
2005         u64 eptp;
2006
2007         guest_cr3 = cr3;
2008         if (enable_ept) {
2009                 eptp = construct_eptp(cr3);
2010                 vmcs_write64(EPT_POINTER, eptp);
2011                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
2012                         vcpu->kvm->arch.ept_identity_map_addr;
2013                 ept_load_pdptrs(vcpu);
2014         }
2015
2016         vmx_flush_tlb(vcpu);
2017         vmcs_writel(GUEST_CR3, guest_cr3);
2018 }
2019
2020 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2021 {
2022         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
2023                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
2024
2025         vcpu->arch.cr4 = cr4;
2026         if (enable_ept) {
2027                 if (!is_paging(vcpu)) {
2028                         hw_cr4 &= ~X86_CR4_PAE;
2029                         hw_cr4 |= X86_CR4_PSE;
2030                 } else if (!(cr4 & X86_CR4_PAE)) {
2031                         hw_cr4 &= ~X86_CR4_PAE;
2032                 }
2033         }
2034
2035         vmcs_writel(CR4_READ_SHADOW, cr4);
2036         vmcs_writel(GUEST_CR4, hw_cr4);
2037 }
2038
2039 static void vmx_get_segment(struct kvm_vcpu *vcpu,
2040                             struct kvm_segment *var, int seg)
2041 {
2042         struct vcpu_vmx *vmx = to_vmx(vcpu);
2043         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2044         struct kvm_save_segment *save;
2045         u32 ar;
2046
2047         if (vmx->rmode.vm86_active
2048             && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
2049                 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
2050                 || seg == VCPU_SREG_GS)
2051             && !emulate_invalid_guest_state) {
2052                 switch (seg) {
2053                 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
2054                 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
2055                 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
2056                 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
2057                 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
2058                 default: BUG();
2059                 }
2060                 var->selector = save->selector;
2061                 var->base = save->base;
2062                 var->limit = save->limit;
2063                 ar = save->ar;
2064                 if (seg == VCPU_SREG_TR
2065                     || var->selector == vmcs_read16(sf->selector))
2066                         goto use_saved_rmode_seg;
2067         }
2068         var->base = vmcs_readl(sf->base);
2069         var->limit = vmcs_read32(sf->limit);
2070         var->selector = vmcs_read16(sf->selector);
2071         ar = vmcs_read32(sf->ar_bytes);
2072 use_saved_rmode_seg:
2073         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
2074                 ar = 0;
2075         var->type = ar & 15;
2076         var->s = (ar >> 4) & 1;
2077         var->dpl = (ar >> 5) & 3;
2078         var->present = (ar >> 7) & 1;
2079         var->avl = (ar >> 12) & 1;
2080         var->l = (ar >> 13) & 1;
2081         var->db = (ar >> 14) & 1;
2082         var->g = (ar >> 15) & 1;
2083         var->unusable = (ar >> 16) & 1;
2084 }
2085
2086 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2087 {
2088         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2089         struct kvm_segment s;
2090
2091         if (to_vmx(vcpu)->rmode.vm86_active) {
2092                 vmx_get_segment(vcpu, &s, seg);
2093                 return s.base;
2094         }
2095         return vmcs_readl(sf->base);
2096 }
2097
2098 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2099 {
2100         if (!is_protmode(vcpu))
2101                 return 0;
2102
2103         if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
2104                 return 3;
2105
2106         return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2107 }
2108
2109 static u32 vmx_segment_access_rights(struct kvm_segment *var)
2110 {
2111         u32 ar;
2112
2113         if (var->unusable)
2114                 ar = 1 << 16;
2115         else {
2116                 ar = var->type & 15;
2117                 ar |= (var->s & 1) << 4;
2118                 ar |= (var->dpl & 3) << 5;
2119                 ar |= (var->present & 1) << 7;
2120                 ar |= (var->avl & 1) << 12;
2121                 ar |= (var->l & 1) << 13;
2122                 ar |= (var->db & 1) << 14;
2123                 ar |= (var->g & 1) << 15;
2124         }
2125         if (ar == 0) /* a 0 value means unusable */
2126                 ar = AR_UNUSABLE_MASK;
2127
2128         return ar;
2129 }
2130
2131 static void vmx_set_segment(struct kvm_vcpu *vcpu,
2132                             struct kvm_segment *var, int seg)
2133 {
2134         struct vcpu_vmx *vmx = to_vmx(vcpu);
2135         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2136         u32 ar;
2137
2138         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2139                 vmcs_write16(sf->selector, var->selector);
2140                 vmx->rmode.tr.selector = var->selector;
2141                 vmx->rmode.tr.base = var->base;
2142                 vmx->rmode.tr.limit = var->limit;
2143                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
2144                 return;
2145         }
2146         vmcs_writel(sf->base, var->base);
2147         vmcs_write32(sf->limit, var->limit);
2148         vmcs_write16(sf->selector, var->selector);
2149         if (vmx->rmode.vm86_active && var->s) {
2150                 /*
2151                  * Hack real-mode segments into vm86 compatibility.
2152                  */
2153                 if (var->base == 0xffff0000 && var->selector == 0xf000)
2154                         vmcs_writel(sf->base, 0xf0000);
2155                 ar = 0xf3;
2156         } else
2157                 ar = vmx_segment_access_rights(var);
2158
2159         /*
2160          *   Fix the "Accessed" bit in AR field of segment registers for older
2161          * qemu binaries.
2162          *   IA32 arch specifies that at the time of processor reset the
2163          * "Accessed" bit in the AR field of segment registers is 1. And qemu
2164          * is setting it to 0 in the usedland code. This causes invalid guest
2165          * state vmexit when "unrestricted guest" mode is turned on.
2166          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
2167          * tree. Newer qemu binaries with that qemu fix would not need this
2168          * kvm hack.
2169          */
2170         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2171                 ar |= 0x1; /* Accessed */
2172
2173         vmcs_write32(sf->ar_bytes, ar);
2174 }
2175
2176 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2177 {
2178         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2179
2180         *db = (ar >> 14) & 1;
2181         *l = (ar >> 13) & 1;
2182 }
2183
2184 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2185 {
2186         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2187         dt->address = vmcs_readl(GUEST_IDTR_BASE);
2188 }
2189
2190 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2191 {
2192         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2193         vmcs_writel(GUEST_IDTR_BASE, dt->address);
2194 }
2195
2196 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2197 {
2198         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2199         dt->address = vmcs_readl(GUEST_GDTR_BASE);
2200 }
2201
2202 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2203 {
2204         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2205         vmcs_writel(GUEST_GDTR_BASE, dt->address);
2206 }
2207
2208 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2209 {
2210         struct kvm_segment var;
2211         u32 ar;
2212
2213         vmx_get_segment(vcpu, &var, seg);
2214         ar = vmx_segment_access_rights(&var);
2215
2216         if (var.base != (var.selector << 4))
2217                 return false;
2218         if (var.limit != 0xffff)
2219                 return false;
2220         if (ar != 0xf3)
2221                 return false;
2222
2223         return true;
2224 }
2225
2226 static bool code_segment_valid(struct kvm_vcpu *vcpu)
2227 {
2228         struct kvm_segment cs;
2229         unsigned int cs_rpl;
2230
2231         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2232         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2233
2234         if (cs.unusable)
2235                 return false;
2236         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2237                 return false;
2238         if (!cs.s)
2239                 return false;
2240         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
2241                 if (cs.dpl > cs_rpl)
2242                         return false;
2243         } else {
2244                 if (cs.dpl != cs_rpl)
2245                         return false;
2246         }
2247         if (!cs.present)
2248                 return false;
2249
2250         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2251         return true;
2252 }
2253
2254 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2255 {
2256         struct kvm_segment ss;
2257         unsigned int ss_rpl;
2258
2259         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2260         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2261
2262         if (ss.unusable)
2263                 return true;
2264         if (ss.type != 3 && ss.type != 7)
2265                 return false;
2266         if (!ss.s)
2267                 return false;
2268         if (ss.dpl != ss_rpl) /* DPL != RPL */
2269                 return false;
2270         if (!ss.present)
2271                 return false;
2272
2273         return true;
2274 }
2275
2276 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2277 {
2278         struct kvm_segment var;
2279         unsigned int rpl;
2280
2281         vmx_get_segment(vcpu, &var, seg);
2282         rpl = var.selector & SELECTOR_RPL_MASK;
2283
2284         if (var.unusable)
2285                 return true;
2286         if (!var.s)
2287                 return false;
2288         if (!var.present)
2289                 return false;
2290         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2291                 if (var.dpl < rpl) /* DPL < RPL */
2292                         return false;
2293         }
2294
2295         /* TODO: Add other members to kvm_segment_field to allow checking for other access
2296          * rights flags
2297          */
2298         return true;
2299 }
2300
2301 static bool tr_valid(struct kvm_vcpu *vcpu)
2302 {
2303         struct kvm_segment tr;
2304
2305         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2306
2307         if (tr.unusable)
2308                 return false;
2309         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
2310                 return false;
2311         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2312                 return false;
2313         if (!tr.present)
2314                 return false;
2315
2316         return true;
2317 }
2318
2319 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2320 {
2321         struct kvm_segment ldtr;
2322
2323         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2324
2325         if (ldtr.unusable)
2326                 return true;
2327         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
2328                 return false;
2329         if (ldtr.type != 2)
2330                 return false;
2331         if (!ldtr.present)
2332                 return false;
2333
2334         return true;
2335 }
2336
2337 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2338 {
2339         struct kvm_segment cs, ss;
2340
2341         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2342         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2343
2344         return ((cs.selector & SELECTOR_RPL_MASK) ==
2345                  (ss.selector & SELECTOR_RPL_MASK));
2346 }
2347
2348 /*
2349  * Check if guest state is valid. Returns true if valid, false if
2350  * not.
2351  * We assume that registers are always usable
2352  */
2353 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2354 {
2355         /* real mode guest state checks */
2356         if (!is_protmode(vcpu)) {
2357                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2358                         return false;
2359                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2360                         return false;
2361                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2362                         return false;
2363                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2364                         return false;
2365                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2366                         return false;
2367                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2368                         return false;
2369         } else {
2370         /* protected mode guest state checks */
2371                 if (!cs_ss_rpl_check(vcpu))
2372                         return false;
2373                 if (!code_segment_valid(vcpu))
2374                         return false;
2375                 if (!stack_segment_valid(vcpu))
2376                         return false;
2377                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2378                         return false;
2379                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2380                         return false;
2381                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2382                         return false;
2383                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2384                         return false;
2385                 if (!tr_valid(vcpu))
2386                         return false;
2387                 if (!ldtr_valid(vcpu))
2388                         return false;
2389         }
2390         /* TODO:
2391          * - Add checks on RIP
2392          * - Add checks on RFLAGS
2393          */
2394
2395         return true;
2396 }
2397
2398 static int init_rmode_tss(struct kvm *kvm)
2399 {
2400         gfn_t fn;
2401         u16 data = 0;
2402         int r, idx, ret = 0;
2403
2404         idx = srcu_read_lock(&kvm->srcu);
2405         fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2406         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2407         if (r < 0)
2408                 goto out;
2409         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2410         r = kvm_write_guest_page(kvm, fn++, &data,
2411                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
2412         if (r < 0)
2413                 goto out;
2414         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2415         if (r < 0)
2416                 goto out;
2417         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2418         if (r < 0)
2419                 goto out;
2420         data = ~0;
2421         r = kvm_write_guest_page(kvm, fn, &data,
2422                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2423                                  sizeof(u8));
2424         if (r < 0)
2425                 goto out;
2426
2427         ret = 1;
2428 out:
2429         srcu_read_unlock(&kvm->srcu, idx);
2430         return ret;
2431 }
2432
2433 static int init_rmode_identity_map(struct kvm *kvm)
2434 {
2435         int i, idx, r, ret;
2436         pfn_t identity_map_pfn;
2437         u32 tmp;
2438
2439         if (!enable_ept)
2440                 return 1;
2441         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2442                 printk(KERN_ERR "EPT: identity-mapping pagetable "
2443                         "haven't been allocated!\n");
2444                 return 0;
2445         }
2446         if (likely(kvm->arch.ept_identity_pagetable_done))
2447                 return 1;
2448         ret = 0;
2449         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2450         idx = srcu_read_lock(&kvm->srcu);
2451         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2452         if (r < 0)
2453                 goto out;
2454         /* Set up identity-mapping pagetable for EPT in real mode */
2455         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2456                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2457                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2458                 r = kvm_write_guest_page(kvm, identity_map_pfn,
2459                                 &tmp, i * sizeof(tmp), sizeof(tmp));
2460                 if (r < 0)
2461                         goto out;
2462         }
2463         kvm->arch.ept_identity_pagetable_done = true;
2464         ret = 1;
2465 out:
2466         srcu_read_unlock(&kvm->srcu, idx);
2467         return ret;
2468 }
2469
2470 static void seg_setup(int seg)
2471 {
2472         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2473         unsigned int ar;
2474
2475         vmcs_write16(sf->selector, 0);
2476         vmcs_writel(sf->base, 0);
2477         vmcs_write32(sf->limit, 0xffff);
2478         if (enable_unrestricted_guest) {
2479                 ar = 0x93;
2480                 if (seg == VCPU_SREG_CS)
2481                         ar |= 0x08; /* code segment */
2482         } else
2483                 ar = 0xf3;
2484
2485         vmcs_write32(sf->ar_bytes, ar);
2486 }
2487
2488 static int alloc_apic_access_page(struct kvm *kvm)
2489 {
2490         struct kvm_userspace_memory_region kvm_userspace_mem;
2491         int r = 0;
2492
2493         mutex_lock(&kvm->slots_lock);
2494         if (kvm->arch.apic_access_page)
2495                 goto out;
2496         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2497         kvm_userspace_mem.flags = 0;
2498         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2499         kvm_userspace_mem.memory_size = PAGE_SIZE;
2500         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2501         if (r)
2502                 goto out;
2503
2504         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2505 out:
2506         mutex_unlock(&kvm->slots_lock);
2507         return r;
2508 }
2509
2510 static int alloc_identity_pagetable(struct kvm *kvm)
2511 {
2512         struct kvm_userspace_memory_region kvm_userspace_mem;
2513         int r = 0;
2514
2515         mutex_lock(&kvm->slots_lock);
2516         if (kvm->arch.ept_identity_pagetable)
2517                 goto out;
2518         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2519         kvm_userspace_mem.flags = 0;
2520         kvm_userspace_mem.guest_phys_addr =
2521                 kvm->arch.ept_identity_map_addr;
2522         kvm_userspace_mem.memory_size = PAGE_SIZE;
2523         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2524         if (r)
2525                 goto out;
2526
2527         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2528                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2529 out:
2530         mutex_unlock(&kvm->slots_lock);
2531         return r;
2532 }
2533
2534 static void allocate_vpid(struct vcpu_vmx *vmx)
2535 {
2536         int vpid;
2537
2538         vmx->vpid = 0;
2539         if (!enable_vpid)
2540                 return;
2541         spin_lock(&vmx_vpid_lock);
2542         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2543         if (vpid < VMX_NR_VPIDS) {
2544                 vmx->vpid = vpid;
2545                 __set_bit(vpid, vmx_vpid_bitmap);
2546         }
2547         spin_unlock(&vmx_vpid_lock);
2548 }
2549
2550 static void free_vpid(struct vcpu_vmx *vmx)
2551 {
2552         if (!enable_vpid)
2553                 return;
2554         spin_lock(&vmx_vpid_lock);
2555         if (vmx->vpid != 0)
2556                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2557         spin_unlock(&vmx_vpid_lock);
2558 }
2559
2560 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2561 {
2562         int f = sizeof(unsigned long);
2563
2564         if (!cpu_has_vmx_msr_bitmap())
2565                 return;
2566
2567         /*
2568          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2569          * have the write-low and read-high bitmap offsets the wrong way round.
2570          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2571          */
2572         if (msr <= 0x1fff) {
2573                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2574                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2575         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2576                 msr &= 0x1fff;
2577                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2578                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2579         }
2580 }
2581
2582 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2583 {
2584         if (!longmode_only)
2585                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2586         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2587 }
2588
2589 /*
2590  * Sets up the vmcs for emulated real mode.
2591  */
2592 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2593 {
2594         u32 host_sysenter_cs, msr_low, msr_high;
2595         u32 junk;
2596         u64 host_pat;
2597         unsigned long a;
2598         struct desc_ptr dt;
2599         int i;
2600         unsigned long kvm_vmx_return;
2601         u32 exec_control;
2602
2603         /* I/O */
2604         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2605         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2606
2607         if (cpu_has_vmx_msr_bitmap())
2608                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2609
2610         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2611
2612         /* Control */
2613         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2614                 vmcs_config.pin_based_exec_ctrl);
2615
2616         exec_control = vmcs_config.cpu_based_exec_ctrl;
2617         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2618                 exec_control &= ~CPU_BASED_TPR_SHADOW;
2619 #ifdef CONFIG_X86_64
2620                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2621                                 CPU_BASED_CR8_LOAD_EXITING;
2622 #endif
2623         }
2624         if (!enable_ept)
2625                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2626                                 CPU_BASED_CR3_LOAD_EXITING  |
2627                                 CPU_BASED_INVLPG_EXITING;
2628         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2629
2630         if (cpu_has_secondary_exec_ctrls()) {
2631                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2632                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2633                         exec_control &=
2634                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2635                 if (vmx->vpid == 0)
2636                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2637                 if (!enable_ept) {
2638                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2639                         enable_unrestricted_guest = 0;
2640                 }
2641                 if (!enable_unrestricted_guest)
2642                         exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2643                 if (!ple_gap)
2644                         exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2645                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2646         }
2647
2648         if (ple_gap) {
2649                 vmcs_write32(PLE_GAP, ple_gap);
2650                 vmcs_write32(PLE_WINDOW, ple_window);
2651         }
2652
2653         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2654         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2655         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
2656
2657         vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS);  /* 22.2.3 */
2658         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
2659         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
2660
2661         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
2662         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2663         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2664         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
2665         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
2666         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2667 #ifdef CONFIG_X86_64
2668         rdmsrl(MSR_FS_BASE, a);
2669         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2670         rdmsrl(MSR_GS_BASE, a);
2671         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2672 #else
2673         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2674         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2675 #endif
2676
2677         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
2678
2679         native_store_idt(&dt);
2680         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
2681
2682         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2683         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2684         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2685         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2686         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2687         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2688         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
2689
2690         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2691         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2692         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2693         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
2694         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2695         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
2696
2697         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2698                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2699                 host_pat = msr_low | ((u64) msr_high << 32);
2700                 vmcs_write64(HOST_IA32_PAT, host_pat);
2701         }
2702         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2703                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2704                 host_pat = msr_low | ((u64) msr_high << 32);
2705                 /* Write the default value follow host pat */
2706                 vmcs_write64(GUEST_IA32_PAT, host_pat);
2707                 /* Keep arch.pat sync with GUEST_IA32_PAT */
2708                 vmx->vcpu.arch.pat = host_pat;
2709         }
2710
2711         for (i = 0; i < NR_VMX_MSR; ++i) {
2712                 u32 index = vmx_msr_index[i];
2713                 u32 data_low, data_high;
2714                 int j = vmx->nmsrs;
2715
2716                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2717                         continue;
2718                 if (wrmsr_safe(index, data_low, data_high) < 0)
2719                         continue;
2720                 vmx->guest_msrs[j].index = i;
2721                 vmx->guest_msrs[j].data = 0;
2722                 vmx->guest_msrs[j].mask = -1ull;
2723                 ++vmx->nmsrs;
2724         }
2725
2726         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2727
2728         /* 22.2.1, 20.8.1 */
2729         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2730
2731         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2732         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2733         if (enable_ept)
2734                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
2735         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
2736
2737         kvm_write_tsc(&vmx->vcpu, 0);
2738
2739         return 0;
2740 }
2741
2742 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2743 {
2744         struct vcpu_vmx *vmx = to_vmx(vcpu);
2745         u64 msr;
2746         int ret;
2747
2748         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2749
2750         vmx->rmode.vm86_active = 0;
2751
2752         vmx->soft_vnmi_blocked = 0;
2753
2754         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2755         kvm_set_cr8(&vmx->vcpu, 0);
2756         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2757         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2758                 msr |= MSR_IA32_APICBASE_BSP;
2759         kvm_set_apic_base(&vmx->vcpu, msr);
2760
2761         ret = fx_init(&vmx->vcpu);
2762         if (ret != 0)
2763                 goto out;
2764
2765         seg_setup(VCPU_SREG_CS);
2766         /*
2767          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2768          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2769          */
2770         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2771                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2772                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2773         } else {
2774                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2775                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2776         }
2777
2778         seg_setup(VCPU_SREG_DS);
2779         seg_setup(VCPU_SREG_ES);
2780         seg_setup(VCPU_SREG_FS);
2781         seg_setup(VCPU_SREG_GS);
2782         seg_setup(VCPU_SREG_SS);
2783
2784         vmcs_write16(GUEST_TR_SELECTOR, 0);
2785         vmcs_writel(GUEST_TR_BASE, 0);
2786         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2787         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2788
2789         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2790         vmcs_writel(GUEST_LDTR_BASE, 0);
2791         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2792         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2793
2794         vmcs_write32(GUEST_SYSENTER_CS, 0);
2795         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2796         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2797
2798         vmcs_writel(GUEST_RFLAGS, 0x02);
2799         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2800                 kvm_rip_write(vcpu, 0xfff0);
2801         else
2802                 kvm_rip_write(vcpu, 0);
2803         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2804
2805         vmcs_writel(GUEST_DR7, 0x400);
2806
2807         vmcs_writel(GUEST_GDTR_BASE, 0);
2808         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2809
2810         vmcs_writel(GUEST_IDTR_BASE, 0);
2811         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2812
2813         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
2814         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2815         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2816
2817         /* Special registers */
2818         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2819
2820         setup_msrs(vmx);
2821
2822         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2823
2824         if (cpu_has_vmx_tpr_shadow()) {
2825                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2826                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2827                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2828                                      __pa(vmx->vcpu.arch.apic->regs));
2829                 vmcs_write32(TPR_THRESHOLD, 0);
2830         }
2831
2832         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2833                 vmcs_write64(APIC_ACCESS_ADDR,
2834                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2835
2836         if (vmx->vpid != 0)
2837                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2838
2839         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2840         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
2841         vmx_set_cr4(&vmx->vcpu, 0);
2842         vmx_set_efer(&vmx->vcpu, 0);
2843         vmx_fpu_activate(&vmx->vcpu);
2844         update_exception_bitmap(&vmx->vcpu);
2845
2846         vpid_sync_context(vmx);
2847
2848         ret = 0;
2849
2850         /* HACK: Don't enable emulation on guest boot/reset */
2851         vmx->emulation_required = 0;
2852
2853 out:
2854         return ret;
2855 }
2856
2857 static void enable_irq_window(struct kvm_vcpu *vcpu)
2858 {
2859         u32 cpu_based_vm_exec_control;
2860
2861         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2862         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2863         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2864 }
2865
2866 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2867 {
2868         u32 cpu_based_vm_exec_control;
2869
2870         if (!cpu_has_virtual_nmis()) {
2871                 enable_irq_window(vcpu);
2872                 return;
2873         }
2874
2875         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
2876                 enable_irq_window(vcpu);
2877                 return;
2878         }
2879         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2880         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2881         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2882 }
2883
2884 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2885 {
2886         struct vcpu_vmx *vmx = to_vmx(vcpu);
2887         uint32_t intr;
2888         int irq = vcpu->arch.interrupt.nr;
2889
2890         trace_kvm_inj_virq(irq);
2891
2892         ++vcpu->stat.irq_injections;
2893         if (vmx->rmode.vm86_active) {
2894                 if (kvm_inject_realmode_interrupt(vcpu, irq) != EMULATE_DONE)
2895                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2896                 return;
2897         }
2898         intr = irq | INTR_INFO_VALID_MASK;
2899         if (vcpu->arch.interrupt.soft) {
2900                 intr |= INTR_TYPE_SOFT_INTR;
2901                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2902                              vmx->vcpu.arch.event_exit_inst_len);
2903         } else
2904                 intr |= INTR_TYPE_EXT_INTR;
2905         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2906         vmx_clear_hlt(vcpu);
2907 }
2908
2909 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2910 {
2911         struct vcpu_vmx *vmx = to_vmx(vcpu);
2912
2913         if (!cpu_has_virtual_nmis()) {
2914                 /*
2915                  * Tracking the NMI-blocked state in software is built upon
2916                  * finding the next open IRQ window. This, in turn, depends on
2917                  * well-behaving guests: They have to keep IRQs disabled at
2918                  * least as long as the NMI handler runs. Otherwise we may
2919                  * cause NMI nesting, maybe breaking the guest. But as this is
2920                  * highly unlikely, we can live with the residual risk.
2921                  */
2922                 vmx->soft_vnmi_blocked = 1;
2923                 vmx->vnmi_blocked_time = 0;
2924         }
2925
2926         ++vcpu->stat.nmi_injections;
2927         if (vmx->rmode.vm86_active) {
2928                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR) != EMULATE_DONE)
2929                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2930                 return;
2931         }
2932         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2933                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2934         vmx_clear_hlt(vcpu);
2935 }
2936
2937 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2938 {
2939         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2940                 return 0;
2941
2942         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2943                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
2944                    | GUEST_INTR_STATE_NMI));
2945 }
2946
2947 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2948 {
2949         if (!cpu_has_virtual_nmis())
2950                 return to_vmx(vcpu)->soft_vnmi_blocked;
2951         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
2952 }
2953
2954 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2955 {
2956         struct vcpu_vmx *vmx = to_vmx(vcpu);
2957
2958         if (!cpu_has_virtual_nmis()) {
2959                 if (vmx->soft_vnmi_blocked != masked) {
2960                         vmx->soft_vnmi_blocked = masked;
2961                         vmx->vnmi_blocked_time = 0;
2962                 }
2963         } else {
2964                 if (masked)
2965                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2966                                       GUEST_INTR_STATE_NMI);
2967                 else
2968                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2969                                         GUEST_INTR_STATE_NMI);
2970         }
2971 }
2972
2973 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2974 {
2975         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2976                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2977                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2978 }
2979
2980 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2981 {
2982         int ret;
2983         struct kvm_userspace_memory_region tss_mem = {
2984                 .slot = TSS_PRIVATE_MEMSLOT,
2985                 .guest_phys_addr = addr,
2986                 .memory_size = PAGE_SIZE * 3,
2987                 .flags = 0,
2988         };
2989
2990         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2991         if (ret)
2992                 return ret;
2993         kvm->arch.tss_addr = addr;
2994         if (!init_rmode_tss(kvm))
2995                 return  -ENOMEM;
2996
2997         return 0;
2998 }
2999
3000 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
3001                                   int vec, u32 err_code)
3002 {
3003         /*
3004          * Instruction with address size override prefix opcode 0x67
3005          * Cause the #SS fault with 0 error code in VM86 mode.
3006          */
3007         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
3008                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
3009                         return 1;
3010         /*
3011          * Forward all other exceptions that are valid in real mode.
3012          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
3013          *        the required debugging infrastructure rework.
3014          */
3015         switch (vec) {
3016         case DB_VECTOR:
3017                 if (vcpu->guest_debug &
3018                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
3019                         return 0;
3020                 kvm_queue_exception(vcpu, vec);
3021                 return 1;
3022         case BP_VECTOR:
3023                 /*
3024                  * Update instruction length as we may reinject the exception
3025                  * from user space while in guest debugging mode.
3026                  */
3027                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
3028                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3029                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
3030                         return 0;
3031                 /* fall through */
3032         case DE_VECTOR:
3033         case OF_VECTOR:
3034         case BR_VECTOR:
3035         case UD_VECTOR:
3036         case DF_VECTOR:
3037         case SS_VECTOR:
3038         case GP_VECTOR:
3039         case MF_VECTOR:
3040                 kvm_queue_exception(vcpu, vec);
3041                 return 1;
3042         }
3043         return 0;
3044 }
3045
3046 /*
3047  * Trigger machine check on the host. We assume all the MSRs are already set up
3048  * by the CPU and that we still run on the same CPU as the MCE occurred on.
3049  * We pass a fake environment to the machine check handler because we want
3050  * the guest to be always treated like user space, no matter what context
3051  * it used internally.
3052  */
3053 static void kvm_machine_check(void)
3054 {
3055 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
3056         struct pt_regs regs = {
3057                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
3058                 .flags = X86_EFLAGS_IF,
3059         };
3060
3061         do_machine_check(&regs, 0);
3062 #endif
3063 }
3064
3065 static int handle_machine_check(struct kvm_vcpu *vcpu)
3066 {
3067         /* already handled by vcpu_run */
3068         return 1;
3069 }
3070
3071 static int handle_exception(struct kvm_vcpu *vcpu)
3072 {
3073         struct vcpu_vmx *vmx = to_vmx(vcpu);
3074         struct kvm_run *kvm_run = vcpu->run;
3075         u32 intr_info, ex_no, error_code;
3076         unsigned long cr2, rip, dr6;
3077         u32 vect_info;
3078         enum emulation_result er;
3079
3080         vect_info = vmx->idt_vectoring_info;
3081         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3082
3083         if (is_machine_check(intr_info))
3084                 return handle_machine_check(vcpu);
3085
3086         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
3087             !is_page_fault(intr_info)) {
3088                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3089                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3090                 vcpu->run->internal.ndata = 2;
3091                 vcpu->run->internal.data[0] = vect_info;
3092                 vcpu->run->internal.data[1] = intr_info;
3093                 return 0;
3094         }
3095
3096         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
3097                 return 1;  /* already handled by vmx_vcpu_run() */
3098
3099         if (is_no_device(intr_info)) {
3100                 vmx_fpu_activate(vcpu);
3101                 return 1;
3102         }
3103
3104         if (is_invalid_opcode(intr_info)) {
3105                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
3106                 if (er != EMULATE_DONE)
3107                         kvm_queue_exception(vcpu, UD_VECTOR);
3108                 return 1;
3109         }
3110
3111         error_code = 0;
3112         rip = kvm_rip_read(vcpu);
3113         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
3114                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3115         if (is_page_fault(intr_info)) {
3116                 /* EPT won't cause page fault directly */
3117                 if (enable_ept)
3118                         BUG();
3119                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
3120                 trace_kvm_page_fault(cr2, error_code);
3121
3122                 if (kvm_event_needs_reinjection(vcpu))
3123                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
3124                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
3125         }
3126
3127         if (vmx->rmode.vm86_active &&
3128             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
3129                                                                 error_code)) {
3130                 if (vcpu->arch.halt_request) {
3131                         vcpu->arch.halt_request = 0;
3132                         return kvm_emulate_halt(vcpu);
3133                 }
3134                 return 1;
3135         }
3136
3137         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
3138         switch (ex_no) {
3139         case DB_VECTOR:
3140                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3141                 if (!(vcpu->guest_debug &
3142                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3143                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3144                         kvm_queue_exception(vcpu, DB_VECTOR);
3145                         return 1;
3146                 }
3147                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3148                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3149                 /* fall through */
3150         case BP_VECTOR:
3151                 /*
3152                  * Update instruction length as we may reinject #BP from
3153                  * user space while in guest debugging mode. Reading it for
3154                  * #DB as well causes no harm, it is not used in that case.
3155                  */
3156                 vmx->vcpu.arch.event_exit_inst_len =
3157                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3158                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
3159                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3160                 kvm_run->debug.arch.exception = ex_no;
3161                 break;
3162         default:
3163                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3164                 kvm_run->ex.exception = ex_no;
3165                 kvm_run->ex.error_code = error_code;
3166                 break;
3167         }
3168         return 0;
3169 }
3170
3171 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
3172 {
3173         ++vcpu->stat.irq_exits;
3174         return 1;
3175 }
3176
3177 static int handle_triple_fault(struct kvm_vcpu *vcpu)
3178 {
3179         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
3180         return 0;
3181 }
3182
3183 static int handle_io(struct kvm_vcpu *vcpu)
3184 {
3185         unsigned long exit_qualification;
3186         int size, in, string;
3187         unsigned port;
3188
3189         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3190         string = (exit_qualification & 16) != 0;
3191         in = (exit_qualification & 8) != 0;
3192
3193         ++vcpu->stat.io_exits;
3194
3195         if (string || in)
3196                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
3197
3198         port = exit_qualification >> 16;
3199         size = (exit_qualification & 7) + 1;
3200         skip_emulated_instruction(vcpu);
3201
3202         return kvm_fast_pio_out(vcpu, size, port);
3203 }
3204
3205 static void
3206 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3207 {
3208         /*
3209          * Patch in the VMCALL instruction:
3210          */
3211         hypercall[0] = 0x0f;
3212         hypercall[1] = 0x01;
3213         hypercall[2] = 0xc1;
3214 }
3215
3216 static int handle_cr(struct kvm_vcpu *vcpu)
3217 {
3218         unsigned long exit_qualification, val;
3219         int cr;
3220         int reg;
3221         int err;
3222
3223         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3224         cr = exit_qualification & 15;
3225         reg = (exit_qualification >> 8) & 15;
3226         switch ((exit_qualification >> 4) & 3) {
3227         case 0: /* mov to cr */
3228                 val = kvm_register_read(vcpu, reg);
3229                 trace_kvm_cr_write(cr, val);
3230                 switch (cr) {
3231                 case 0:
3232                         err = kvm_set_cr0(vcpu, val);
3233                         kvm_complete_insn_gp(vcpu, err);
3234                         return 1;
3235                 case 3:
3236                         err = kvm_set_cr3(vcpu, val);
3237                         kvm_complete_insn_gp(vcpu, err);
3238                         return 1;
3239                 case 4:
3240                         err = kvm_set_cr4(vcpu, val);
3241                         kvm_complete_insn_gp(vcpu, err);
3242                         return 1;
3243                 case 8: {
3244                                 u8 cr8_prev = kvm_get_cr8(vcpu);
3245                                 u8 cr8 = kvm_register_read(vcpu, reg);
3246                                 err = kvm_set_cr8(vcpu, cr8);
3247                                 kvm_complete_insn_gp(vcpu, err);
3248                                 if (irqchip_in_kernel(vcpu->kvm))
3249                                         return 1;
3250                                 if (cr8_prev <= cr8)
3251                                         return 1;
3252                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
3253                                 return 0;
3254                         }
3255                 };
3256                 break;
3257         case 2: /* clts */
3258                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
3259                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
3260                 skip_emulated_instruction(vcpu);
3261                 vmx_fpu_activate(vcpu);
3262                 return 1;
3263         case 1: /*mov from cr*/
3264                 switch (cr) {
3265                 case 3:
3266                         val = kvm_read_cr3(vcpu);
3267                         kvm_register_write(vcpu, reg, val);
3268                         trace_kvm_cr_read(cr, val);
3269                         skip_emulated_instruction(vcpu);
3270                         return 1;
3271                 case 8:
3272                         val = kvm_get_cr8(vcpu);
3273                         kvm_register_write(vcpu, reg, val);
3274                         trace_kvm_cr_read(cr, val);
3275                         skip_emulated_instruction(vcpu);
3276                         return 1;
3277                 }
3278                 break;
3279         case 3: /* lmsw */
3280                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
3281                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
3282                 kvm_lmsw(vcpu, val);
3283
3284                 skip_emulated_instruction(vcpu);
3285                 return 1;
3286         default:
3287                 break;
3288         }
3289         vcpu->run->exit_reason = 0;
3290         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
3291                (int)(exit_qualification >> 4) & 3, cr);
3292         return 0;
3293 }
3294
3295 static int handle_dr(struct kvm_vcpu *vcpu)
3296 {
3297         unsigned long exit_qualification;
3298         int dr, reg;
3299
3300         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3301         if (!kvm_require_cpl(vcpu, 0))
3302                 return 1;
3303         dr = vmcs_readl(GUEST_DR7);
3304         if (dr & DR7_GD) {
3305                 /*
3306                  * As the vm-exit takes precedence over the debug trap, we
3307                  * need to emulate the latter, either for the host or the
3308                  * guest debugging itself.
3309                  */
3310                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3311                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3312                         vcpu->run->debug.arch.dr7 = dr;
3313                         vcpu->run->debug.arch.pc =
3314                                 vmcs_readl(GUEST_CS_BASE) +
3315                                 vmcs_readl(GUEST_RIP);
3316                         vcpu->run->debug.arch.exception = DB_VECTOR;
3317                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3318                         return 0;
3319                 } else {
3320                         vcpu->arch.dr7 &= ~DR7_GD;
3321                         vcpu->arch.dr6 |= DR6_BD;
3322                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3323                         kvm_queue_exception(vcpu, DB_VECTOR);
3324                         return 1;
3325                 }
3326         }
3327
3328         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3329         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3330         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3331         if (exit_qualification & TYPE_MOV_FROM_DR) {
3332                 unsigned long val;
3333                 if (!kvm_get_dr(vcpu, dr, &val))
3334                         kvm_register_write(vcpu, reg, val);
3335         } else
3336                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
3337         skip_emulated_instruction(vcpu);
3338         return 1;
3339 }
3340
3341 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3342 {
3343         vmcs_writel(GUEST_DR7, val);
3344 }
3345
3346 static int handle_cpuid(struct kvm_vcpu *vcpu)
3347 {
3348         kvm_emulate_cpuid(vcpu);
3349         return 1;
3350 }
3351
3352 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3353 {
3354         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3355         u64 data;
3356
3357         if (vmx_get_msr(vcpu, ecx, &data)) {
3358                 trace_kvm_msr_read_ex(ecx);
3359                 kvm_inject_gp(vcpu, 0);
3360                 return 1;
3361         }
3362
3363         trace_kvm_msr_read(ecx, data);
3364
3365         /* FIXME: handling of bits 32:63 of rax, rdx */
3366         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3367         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3368         skip_emulated_instruction(vcpu);
3369         return 1;
3370 }
3371
3372 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3373 {
3374         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3375         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3376                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3377
3378         if (vmx_set_msr(vcpu, ecx, data) != 0) {
3379                 trace_kvm_msr_write_ex(ecx, data);
3380                 kvm_inject_gp(vcpu, 0);
3381                 return 1;
3382         }
3383
3384         trace_kvm_msr_write(ecx, data);
3385         skip_emulated_instruction(vcpu);
3386         return 1;
3387 }
3388
3389 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3390 {
3391         kvm_make_request(KVM_REQ_EVENT, vcpu);
3392         return 1;
3393 }
3394
3395 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3396 {
3397         u32 cpu_based_vm_exec_control;
3398
3399         /* clear pending irq */
3400         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3401         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3402         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3403
3404         kvm_make_request(KVM_REQ_EVENT, vcpu);
3405
3406         ++vcpu->stat.irq_window_exits;
3407
3408         /*
3409          * If the user space waits to inject interrupts, exit as soon as
3410          * possible
3411          */
3412         if (!irqchip_in_kernel(vcpu->kvm) &&
3413             vcpu->run->request_interrupt_window &&
3414             !kvm_cpu_has_interrupt(vcpu)) {
3415                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3416                 return 0;
3417         }
3418         return 1;
3419 }
3420
3421 static int handle_halt(struct kvm_vcpu *vcpu)
3422 {
3423         skip_emulated_instruction(vcpu);
3424         return kvm_emulate_halt(vcpu);
3425 }
3426
3427 static int handle_vmcall(struct kvm_vcpu *vcpu)
3428 {
3429         skip_emulated_instruction(vcpu);
3430         kvm_emulate_hypercall(vcpu);
3431         return 1;
3432 }
3433
3434 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3435 {
3436         kvm_queue_exception(vcpu, UD_VECTOR);
3437         return 1;
3438 }
3439
3440 static int handle_invd(struct kvm_vcpu *vcpu)
3441 {
3442         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
3443 }
3444
3445 static int handle_invlpg(struct kvm_vcpu *vcpu)
3446 {
3447         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3448
3449         kvm_mmu_invlpg(vcpu, exit_qualification);
3450         skip_emulated_instruction(vcpu);
3451         return 1;
3452 }
3453
3454 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3455 {
3456         skip_emulated_instruction(vcpu);
3457         kvm_emulate_wbinvd(vcpu);
3458         return 1;
3459 }
3460
3461 static int handle_xsetbv(struct kvm_vcpu *vcpu)
3462 {
3463         u64 new_bv = kvm_read_edx_eax(vcpu);
3464         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3465
3466         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
3467                 skip_emulated_instruction(vcpu);
3468         return 1;
3469 }
3470
3471 static int handle_apic_access(struct kvm_vcpu *vcpu)
3472 {
3473         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
3474 }
3475
3476 static int handle_task_switch(struct kvm_vcpu *vcpu)
3477 {
3478         struct vcpu_vmx *vmx = to_vmx(vcpu);
3479         unsigned long exit_qualification;
3480         bool has_error_code = false;
3481         u32 error_code = 0;
3482         u16 tss_selector;
3483         int reason, type, idt_v;
3484
3485         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3486         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3487
3488         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3489
3490         reason = (u32)exit_qualification >> 30;
3491         if (reason == TASK_SWITCH_GATE && idt_v) {
3492                 switch (type) {
3493                 case INTR_TYPE_NMI_INTR:
3494                         vcpu->arch.nmi_injected = false;
3495                         if (cpu_has_virtual_nmis())
3496                                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3497                                               GUEST_INTR_STATE_NMI);
3498                         break;
3499                 case INTR_TYPE_EXT_INTR:
3500                 case INTR_TYPE_SOFT_INTR:
3501                         kvm_clear_interrupt_queue(vcpu);
3502                         break;
3503                 case INTR_TYPE_HARD_EXCEPTION:
3504                         if (vmx->idt_vectoring_info &
3505                             VECTORING_INFO_DELIVER_CODE_MASK) {
3506                                 has_error_code = true;
3507                                 error_code =
3508                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
3509                         }
3510                         /* fall through */
3511                 case INTR_TYPE_SOFT_EXCEPTION:
3512                         kvm_clear_exception_queue(vcpu);
3513                         break;
3514                 default:
3515                         break;
3516                 }
3517         }
3518         tss_selector = exit_qualification;
3519
3520         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3521                        type != INTR_TYPE_EXT_INTR &&
3522                        type != INTR_TYPE_NMI_INTR))
3523                 skip_emulated_instruction(vcpu);
3524
3525         if (kvm_task_switch(vcpu, tss_selector, reason,
3526                                 has_error_code, error_code) == EMULATE_FAIL) {
3527                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3528                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3529                 vcpu->run->internal.ndata = 0;
3530                 return 0;
3531         }
3532
3533         /* clear all local breakpoint enable flags */
3534         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3535
3536         /*
3537          * TODO: What about debug traps on tss switch?
3538          *       Are we supposed to inject them and update dr6?
3539          */
3540
3541         return 1;
3542 }
3543
3544 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3545 {
3546         unsigned long exit_qualification;
3547         gpa_t gpa;
3548         int gla_validity;
3549
3550         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3551
3552         if (exit_qualification & (1 << 6)) {
3553                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3554                 return -EINVAL;
3555         }
3556
3557         gla_validity = (exit_qualification >> 7) & 0x3;
3558         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3559                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3560                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3561                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3562                         vmcs_readl(GUEST_LINEAR_ADDRESS));
3563                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3564                         (long unsigned int)exit_qualification);
3565                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3566                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3567                 return 0;
3568         }
3569
3570         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3571         trace_kvm_page_fault(gpa, exit_qualification);
3572         return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
3573 }
3574
3575 static u64 ept_rsvd_mask(u64 spte, int level)
3576 {
3577         int i;
3578         u64 mask = 0;
3579
3580         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3581                 mask |= (1ULL << i);
3582
3583         if (level > 2)
3584                 /* bits 7:3 reserved */
3585                 mask |= 0xf8;
3586         else if (level == 2) {
3587                 if (spte & (1ULL << 7))
3588                         /* 2MB ref, bits 20:12 reserved */
3589                         mask |= 0x1ff000;
3590                 else
3591                         /* bits 6:3 reserved */
3592                         mask |= 0x78;
3593         }
3594
3595         return mask;
3596 }
3597
3598 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3599                                        int level)
3600 {
3601         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3602
3603         /* 010b (write-only) */
3604         WARN_ON((spte & 0x7) == 0x2);
3605
3606         /* 110b (write/execute) */
3607         WARN_ON((spte & 0x7) == 0x6);
3608
3609         /* 100b (execute-only) and value not supported by logical processor */
3610         if (!cpu_has_vmx_ept_execute_only())
3611                 WARN_ON((spte & 0x7) == 0x4);
3612
3613         /* not 000b */
3614         if ((spte & 0x7)) {
3615                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3616
3617                 if (rsvd_bits != 0) {
3618                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3619                                          __func__, rsvd_bits);
3620                         WARN_ON(1);
3621                 }
3622
3623                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3624                         u64 ept_mem_type = (spte & 0x38) >> 3;
3625
3626                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
3627                             ept_mem_type == 7) {
3628                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3629                                                 __func__, ept_mem_type);
3630                                 WARN_ON(1);
3631                         }
3632                 }
3633         }
3634 }
3635
3636 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3637 {
3638         u64 sptes[4];
3639         int nr_sptes, i;
3640         gpa_t gpa;
3641
3642         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3643
3644         printk(KERN_ERR "EPT: Misconfiguration.\n");
3645         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3646
3647         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3648
3649         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3650                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3651
3652         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3653         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3654
3655         return 0;
3656 }
3657
3658 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3659 {
3660         u32 cpu_based_vm_exec_control;
3661
3662         /* clear pending NMI */
3663         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3664         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3665         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3666         ++vcpu->stat.nmi_window_exits;
3667         kvm_make_request(KVM_REQ_EVENT, vcpu);
3668
3669         return 1;
3670 }
3671
3672 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3673 {
3674         struct vcpu_vmx *vmx = to_vmx(vcpu);
3675         enum emulation_result err = EMULATE_DONE;
3676         int ret = 1;
3677         u32 cpu_exec_ctrl;
3678         bool intr_window_requested;
3679
3680         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3681         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
3682
3683         while (!guest_state_valid(vcpu)) {
3684                 if (intr_window_requested
3685                     && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
3686                         return handle_interrupt_window(&vmx->vcpu);
3687
3688                 err = emulate_instruction(vcpu, 0);
3689
3690                 if (err == EMULATE_DO_MMIO) {
3691                         ret = 0;
3692                         goto out;
3693                 }
3694
3695                 if (err != EMULATE_DONE)
3696                         return 0;
3697
3698                 if (signal_pending(current))
3699                         goto out;
3700                 if (need_resched())
3701                         schedule();
3702         }
3703
3704         vmx->emulation_required = 0;
3705 out:
3706         return ret;
3707 }
3708
3709 /*
3710  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3711  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3712  */
3713 static int handle_pause(struct kvm_vcpu *vcpu)
3714 {
3715         skip_emulated_instruction(vcpu);
3716         kvm_vcpu_on_spin(vcpu);
3717
3718         return 1;
3719 }
3720
3721 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3722 {
3723         kvm_queue_exception(vcpu, UD_VECTOR);
3724         return 1;
3725 }
3726
3727 /*
3728  * The exit handlers return 1 if the exit was handled fully and guest execution
3729  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
3730  * to be done to userspace and return 0.
3731  */
3732 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3733         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
3734         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
3735         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
3736         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
3737         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
3738         [EXIT_REASON_CR_ACCESS]               = handle_cr,
3739         [EXIT_REASON_DR_ACCESS]               = handle_dr,
3740         [EXIT_REASON_CPUID]                   = handle_cpuid,
3741         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
3742         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
3743         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
3744         [EXIT_REASON_HLT]                     = handle_halt,
3745         [EXIT_REASON_INVD]                    = handle_invd,
3746         [EXIT_REASON_INVLPG]                  = handle_invlpg,
3747         [EXIT_REASON_VMCALL]                  = handle_vmcall,
3748         [EXIT_REASON_VMCLEAR]                 = handle_vmx_insn,
3749         [EXIT_REASON_VMLAUNCH]                = handle_vmx_insn,
3750         [EXIT_REASON_VMPTRLD]                 = handle_vmx_insn,
3751         [EXIT_REASON_VMPTRST]                 = handle_vmx_insn,
3752         [EXIT_REASON_VMREAD]                  = handle_vmx_insn,
3753         [EXIT_REASON_VMRESUME]                = handle_vmx_insn,
3754         [EXIT_REASON_VMWRITE]                 = handle_vmx_insn,
3755         [EXIT_REASON_VMOFF]                   = handle_vmx_insn,
3756         [EXIT_REASON_VMON]                    = handle_vmx_insn,
3757         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
3758         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
3759         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
3760         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
3761         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
3762         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
3763         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
3764         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
3765         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
3766         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
3767         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
3768 };
3769
3770 static const int kvm_vmx_max_exit_handlers =
3771         ARRAY_SIZE(kvm_vmx_exit_handlers);
3772
3773 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3774 {
3775         *info1 = vmcs_readl(EXIT_QUALIFICATION);
3776         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
3777 }
3778
3779 /*
3780  * The guest has exited.  See if we can fix it or if we need userspace
3781  * assistance.
3782  */
3783 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3784 {
3785         struct vcpu_vmx *vmx = to_vmx(vcpu);
3786         u32 exit_reason = vmx->exit_reason;
3787         u32 vectoring_info = vmx->idt_vectoring_info;
3788
3789         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
3790
3791         /* If guest state is invalid, start emulating */
3792         if (vmx->emulation_required && emulate_invalid_guest_state)
3793                 return handle_invalid_guest_state(vcpu);
3794
3795         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
3796                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3797                 vcpu->run->fail_entry.hardware_entry_failure_reason
3798                         = exit_reason;
3799                 return 0;
3800         }
3801
3802         if (unlikely(vmx->fail)) {
3803                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3804                 vcpu->run->fail_entry.hardware_entry_failure_reason
3805                         = vmcs_read32(VM_INSTRUCTION_ERROR);
3806                 return 0;
3807         }
3808
3809         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3810                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3811                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
3812                         exit_reason != EXIT_REASON_TASK_SWITCH))
3813                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3814                        "(0x%x) and exit reason is 0x%x\n",
3815                        __func__, vectoring_info, exit_reason);
3816
3817         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3818                 if (vmx_interrupt_allowed(vcpu)) {
3819                         vmx->soft_vnmi_blocked = 0;
3820                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3821                            vcpu->arch.nmi_pending) {
3822                         /*
3823                          * This CPU don't support us in finding the end of an
3824                          * NMI-blocked window if the guest runs with IRQs
3825                          * disabled. So we pull the trigger after 1 s of
3826                          * futile waiting, but inform the user about this.
3827                          */
3828                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3829                                "state on VCPU %d after 1 s timeout\n",
3830                                __func__, vcpu->vcpu_id);
3831                         vmx->soft_vnmi_blocked = 0;
3832                 }
3833         }
3834
3835         if (exit_reason < kvm_vmx_max_exit_handlers
3836             && kvm_vmx_exit_handlers[exit_reason])
3837                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3838         else {
3839                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3840                 vcpu->run->hw.hardware_exit_reason = exit_reason;
3841         }
3842         return 0;
3843 }
3844
3845 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3846 {
3847         if (irr == -1 || tpr < irr) {
3848                 vmcs_write32(TPR_THRESHOLD, 0);
3849                 return;
3850         }
3851
3852         vmcs_write32(TPR_THRESHOLD, irr);
3853 }
3854
3855 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
3856 {
3857         u32 exit_intr_info = vmx->exit_intr_info;
3858
3859         /* Handle machine checks before interrupts are enabled */
3860         if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3861             || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3862                 && is_machine_check(exit_intr_info)))
3863                 kvm_machine_check();
3864
3865         /* We need to handle NMIs before interrupts are enabled */
3866         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3867             (exit_intr_info & INTR_INFO_VALID_MASK)) {
3868                 kvm_before_handle_nmi(&vmx->vcpu);
3869                 asm("int $2");
3870                 kvm_after_handle_nmi(&vmx->vcpu);
3871         }
3872 }
3873
3874 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
3875 {
3876         u32 exit_intr_info = vmx->exit_intr_info;
3877         bool unblock_nmi;
3878         u8 vector;
3879         bool idtv_info_valid;
3880
3881         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3882
3883         if (cpu_has_virtual_nmis()) {
3884                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3885                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3886                 /*
3887                  * SDM 3: 27.7.1.2 (September 2008)
3888                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
3889                  * a guest IRET fault.
3890                  * SDM 3: 23.2.2 (September 2008)
3891                  * Bit 12 is undefined in any of the following cases:
3892                  *  If the VM exit sets the valid bit in the IDT-vectoring
3893                  *   information field.
3894                  *  If the VM exit is due to a double fault.
3895                  */
3896                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3897                     vector != DF_VECTOR && !idtv_info_valid)
3898                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3899                                       GUEST_INTR_STATE_NMI);
3900         } else if (unlikely(vmx->soft_vnmi_blocked))
3901                 vmx->vnmi_blocked_time +=
3902                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3903 }
3904
3905 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
3906                                       u32 idt_vectoring_info,
3907                                       int instr_len_field,
3908                                       int error_code_field)
3909 {
3910         u8 vector;
3911         int type;
3912         bool idtv_info_valid;
3913
3914         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3915
3916         vmx->vcpu.arch.nmi_injected = false;
3917         kvm_clear_exception_queue(&vmx->vcpu);
3918         kvm_clear_interrupt_queue(&vmx->vcpu);
3919
3920         if (!idtv_info_valid)
3921                 return;
3922
3923         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
3924
3925         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3926         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3927
3928         switch (type) {
3929         case INTR_TYPE_NMI_INTR:
3930                 vmx->vcpu.arch.nmi_injected = true;
3931                 /*
3932                  * SDM 3: 27.7.1.2 (September 2008)
3933                  * Clear bit "block by NMI" before VM entry if a NMI
3934                  * delivery faulted.
3935                  */
3936                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3937                                 GUEST_INTR_STATE_NMI);
3938                 break;
3939         case INTR_TYPE_SOFT_EXCEPTION:
3940                 vmx->vcpu.arch.event_exit_inst_len =
3941                         vmcs_read32(instr_len_field);
3942                 /* fall through */
3943         case INTR_TYPE_HARD_EXCEPTION:
3944                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3945                         u32 err = vmcs_read32(error_code_field);
3946                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
3947                 } else
3948                         kvm_queue_exception(&vmx->vcpu, vector);
3949                 break;
3950         case INTR_TYPE_SOFT_INTR:
3951                 vmx->vcpu.arch.event_exit_inst_len =
3952                         vmcs_read32(instr_len_field);
3953                 /* fall through */
3954         case INTR_TYPE_EXT_INTR:
3955                 kvm_queue_interrupt(&vmx->vcpu, vector,
3956                         type == INTR_TYPE_SOFT_INTR);
3957                 break;
3958         default:
3959                 break;
3960         }
3961 }
3962
3963 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3964 {
3965         __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
3966                                   VM_EXIT_INSTRUCTION_LEN,
3967                                   IDT_VECTORING_ERROR_CODE);
3968 }
3969
3970 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
3971 {
3972         __vmx_complete_interrupts(to_vmx(vcpu),
3973                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
3974                                   VM_ENTRY_INSTRUCTION_LEN,
3975                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
3976
3977         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
3978 }
3979
3980 #ifdef CONFIG_X86_64
3981 #define R "r"
3982 #define Q "q"
3983 #else
3984 #define R "e"
3985 #define Q "l"
3986 #endif
3987
3988 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
3989 {
3990         struct vcpu_vmx *vmx = to_vmx(vcpu);
3991
3992         /* Record the guest's net vcpu time for enforced NMI injections. */
3993         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3994                 vmx->entry_time = ktime_get();
3995
3996         /* Don't enter VMX if guest state is invalid, let the exit handler
3997            start emulation until we arrive back to a valid state */
3998         if (vmx->emulation_required && emulate_invalid_guest_state)
3999                 return;
4000
4001         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
4002                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
4003         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
4004                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
4005
4006         /* When single-stepping over STI and MOV SS, we must clear the
4007          * corresponding interruptibility bits in the guest state. Otherwise
4008          * vmentry fails as it then expects bit 14 (BS) in pending debug
4009          * exceptions being set, but that's not correct for the guest debugging
4010          * case. */
4011         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
4012                 vmx_set_interrupt_shadow(vcpu, 0);
4013
4014         asm(
4015                 /* Store host registers */
4016                 "push %%"R"dx; push %%"R"bp;"
4017                 "push %%"R"cx \n\t" /* placeholder for guest rcx */
4018                 "push %%"R"cx \n\t"
4019                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
4020                 "je 1f \n\t"
4021                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4022                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
4023                 "1: \n\t"
4024                 /* Reload cr2 if changed */
4025                 "mov %c[cr2](%0), %%"R"ax \n\t"
4026                 "mov %%cr2, %%"R"dx \n\t"
4027                 "cmp %%"R"ax, %%"R"dx \n\t"
4028                 "je 2f \n\t"
4029                 "mov %%"R"ax, %%cr2 \n\t"
4030                 "2: \n\t"
4031                 /* Check if vmlaunch of vmresume is needed */
4032                 "cmpl $0, %c[launched](%0) \n\t"
4033                 /* Load guest registers.  Don't clobber flags. */
4034                 "mov %c[rax](%0), %%"R"ax \n\t"
4035                 "mov %c[rbx](%0), %%"R"bx \n\t"
4036                 "mov %c[rdx](%0), %%"R"dx \n\t"
4037                 "mov %c[rsi](%0), %%"R"si \n\t"
4038                 "mov %c[rdi](%0), %%"R"di \n\t"
4039                 "mov %c[rbp](%0), %%"R"bp \n\t"
4040 #ifdef CONFIG_X86_64
4041                 "mov %c[r8](%0),  %%r8  \n\t"
4042                 "mov %c[r9](%0),  %%r9  \n\t"
4043                 "mov %c[r10](%0), %%r10 \n\t"
4044                 "mov %c[r11](%0), %%r11 \n\t"
4045                 "mov %c[r12](%0), %%r12 \n\t"
4046                 "mov %c[r13](%0), %%r13 \n\t"
4047                 "mov %c[r14](%0), %%r14 \n\t"
4048                 "mov %c[r15](%0), %%r15 \n\t"
4049 #endif
4050                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
4051
4052                 /* Enter guest mode */
4053                 "jne .Llaunched \n\t"
4054                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
4055                 "jmp .Lkvm_vmx_return \n\t"
4056                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
4057                 ".Lkvm_vmx_return: "
4058                 /* Save guest registers, load host registers, keep flags */
4059                 "mov %0, %c[wordsize](%%"R"sp) \n\t"
4060                 "pop %0 \n\t"
4061                 "mov %%"R"ax, %c[rax](%0) \n\t"
4062                 "mov %%"R"bx, %c[rbx](%0) \n\t"
4063                 "pop"Q" %c[rcx](%0) \n\t"
4064                 "mov %%"R"dx, %c[rdx](%0) \n\t"
4065                 "mov %%"R"si, %c[rsi](%0) \n\t"
4066                 "mov %%"R"di, %c[rdi](%0) \n\t"
4067                 "mov %%"R"bp, %c[rbp](%0) \n\t"
4068 #ifdef CONFIG_X86_64
4069                 "mov %%r8,  %c[r8](%0) \n\t"
4070                 "mov %%r9,  %c[r9](%0) \n\t"
4071                 "mov %%r10, %c[r10](%0) \n\t"
4072                 "mov %%r11, %c[r11](%0) \n\t"
4073                 "mov %%r12, %c[r12](%0) \n\t"
4074                 "mov %%r13, %c[r13](%0) \n\t"
4075                 "mov %%r14, %c[r14](%0) \n\t"
4076                 "mov %%r15, %c[r15](%0) \n\t"
4077 #endif
4078                 "mov %%cr2, %%"R"ax   \n\t"
4079                 "mov %%"R"ax, %c[cr2](%0) \n\t"
4080
4081                 "pop  %%"R"bp; pop  %%"R"dx \n\t"
4082                 "setbe %c[fail](%0) \n\t"
4083               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
4084                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
4085                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
4086                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
4087                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
4088                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
4089                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
4090                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
4091                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
4092                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
4093                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
4094 #ifdef CONFIG_X86_64
4095                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
4096                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
4097                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
4098                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
4099                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4100                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4101                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4102                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
4103 #endif
4104                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
4105                 [wordsize]"i"(sizeof(ulong))
4106               : "cc", "memory"
4107                 , R"ax", R"bx", R"di", R"si"
4108 #ifdef CONFIG_X86_64
4109                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4110 #endif
4111               );
4112
4113         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
4114                                   | (1 << VCPU_EXREG_PDPTR)
4115                                   | (1 << VCPU_EXREG_CR3));
4116         vcpu->arch.regs_dirty = 0;
4117
4118         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
4119
4120         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
4121         vmx->launched = 1;
4122
4123         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
4124         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
4125
4126         vmx_complete_atomic_exit(vmx);
4127         vmx_recover_nmi_blocking(vmx);
4128         vmx_complete_interrupts(vmx);
4129 }
4130
4131 #undef R
4132 #undef Q
4133
4134 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
4135 {
4136         struct vcpu_vmx *vmx = to_vmx(vcpu);
4137
4138         if (vmx->vmcs) {
4139                 vcpu_clear(vmx);
4140                 free_vmcs(vmx->vmcs);
4141                 vmx->vmcs = NULL;
4142         }
4143 }
4144
4145 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4146 {
4147         struct vcpu_vmx *vmx = to_vmx(vcpu);
4148
4149         free_vpid(vmx);
4150         vmx_free_vmcs(vcpu);
4151         kfree(vmx->guest_msrs);
4152         kvm_vcpu_uninit(vcpu);
4153         kmem_cache_free(kvm_vcpu_cache, vmx);
4154 }
4155
4156 static inline void vmcs_init(struct vmcs *vmcs)
4157 {
4158         u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id()));
4159
4160         if (!vmm_exclusive)
4161                 kvm_cpu_vmxon(phys_addr);
4162
4163         vmcs_clear(vmcs);
4164
4165         if (!vmm_exclusive)
4166                 kvm_cpu_vmxoff();
4167 }
4168
4169 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
4170 {
4171         int err;
4172         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
4173         int cpu;
4174
4175         if (!vmx)
4176                 return ERR_PTR(-ENOMEM);
4177
4178         allocate_vpid(vmx);
4179
4180         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4181         if (err)
4182                 goto free_vcpu;
4183
4184         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
4185         if (!vmx->guest_msrs) {
4186                 err = -ENOMEM;
4187                 goto uninit_vcpu;
4188         }
4189
4190         vmx->vmcs = alloc_vmcs();
4191         if (!vmx->vmcs)
4192                 goto free_msrs;
4193
4194         vmcs_init(vmx->vmcs);
4195
4196         cpu = get_cpu();
4197         vmx_vcpu_load(&vmx->vcpu, cpu);
4198         vmx->vcpu.cpu = cpu;
4199         err = vmx_vcpu_setup(vmx);
4200         vmx_vcpu_put(&vmx->vcpu);
4201         put_cpu();
4202         if (err)
4203                 goto free_vmcs;
4204         if (vm_need_virtualize_apic_accesses(kvm))
4205                 if (alloc_apic_access_page(kvm) != 0)
4206                         goto free_vmcs;
4207
4208         if (enable_ept) {
4209                 if (!kvm->arch.ept_identity_map_addr)
4210                         kvm->arch.ept_identity_map_addr =
4211                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
4212                 err = -ENOMEM;
4213                 if (alloc_identity_pagetable(kvm) != 0)
4214                         goto free_vmcs;
4215                 if (!init_rmode_identity_map(kvm))
4216                         goto free_vmcs;
4217         }
4218
4219         return &vmx->vcpu;
4220
4221 free_vmcs:
4222         free_vmcs(vmx->vmcs);
4223 free_msrs:
4224         kfree(vmx->guest_msrs);
4225 uninit_vcpu:
4226         kvm_vcpu_uninit(&vmx->vcpu);
4227 free_vcpu:
4228         free_vpid(vmx);
4229         kmem_cache_free(kvm_vcpu_cache, vmx);
4230         return ERR_PTR(err);
4231 }
4232
4233 static void __init vmx_check_processor_compat(void *rtn)
4234 {
4235         struct vmcs_config vmcs_conf;
4236
4237         *(int *)rtn = 0;
4238         if (setup_vmcs_config(&vmcs_conf) < 0)
4239                 *(int *)rtn = -EIO;
4240         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4241                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4242                                 smp_processor_id());
4243                 *(int *)rtn = -EIO;
4244         }
4245 }
4246
4247 static int get_ept_level(void)
4248 {
4249         return VMX_EPT_DEFAULT_GAW + 1;
4250 }
4251
4252 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4253 {
4254         u64 ret;
4255
4256         /* For VT-d and EPT combination
4257          * 1. MMIO: always map as UC
4258          * 2. EPT with VT-d:
4259          *   a. VT-d without snooping control feature: can't guarantee the
4260          *      result, try to trust guest.
4261          *   b. VT-d with snooping control feature: snooping control feature of
4262          *      VT-d engine can guarantee the cache correctness. Just set it
4263          *      to WB to keep consistent with host. So the same as item 3.
4264          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
4265          *    consistent with host MTRR
4266          */
4267         if (is_mmio)
4268                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
4269         else if (vcpu->kvm->arch.iommu_domain &&
4270                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4271                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4272                       VMX_EPT_MT_EPTE_SHIFT;
4273         else
4274                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
4275                         | VMX_EPT_IPAT_BIT;
4276
4277         return ret;
4278 }
4279
4280 #define _ER(x) { EXIT_REASON_##x, #x }
4281
4282 static const struct trace_print_flags vmx_exit_reasons_str[] = {
4283         _ER(EXCEPTION_NMI),
4284         _ER(EXTERNAL_INTERRUPT),
4285         _ER(TRIPLE_FAULT),
4286         _ER(PENDING_INTERRUPT),
4287         _ER(NMI_WINDOW),
4288         _ER(TASK_SWITCH),
4289         _ER(CPUID),
4290         _ER(HLT),
4291         _ER(INVLPG),
4292         _ER(RDPMC),
4293         _ER(RDTSC),
4294         _ER(VMCALL),
4295         _ER(VMCLEAR),
4296         _ER(VMLAUNCH),
4297         _ER(VMPTRLD),
4298         _ER(VMPTRST),
4299         _ER(VMREAD),
4300         _ER(VMRESUME),
4301         _ER(VMWRITE),
4302         _ER(VMOFF),
4303         _ER(VMON),
4304         _ER(CR_ACCESS),
4305         _ER(DR_ACCESS),
4306         _ER(IO_INSTRUCTION),
4307         _ER(MSR_READ),
4308         _ER(MSR_WRITE),
4309         _ER(MWAIT_INSTRUCTION),
4310         _ER(MONITOR_INSTRUCTION),
4311         _ER(PAUSE_INSTRUCTION),
4312         _ER(MCE_DURING_VMENTRY),
4313         _ER(TPR_BELOW_THRESHOLD),
4314         _ER(APIC_ACCESS),
4315         _ER(EPT_VIOLATION),
4316         _ER(EPT_MISCONFIG),
4317         _ER(WBINVD),
4318         { -1, NULL }
4319 };
4320
4321 #undef _ER
4322
4323 static int vmx_get_lpage_level(void)
4324 {
4325         if (enable_ept && !cpu_has_vmx_ept_1g_page())
4326                 return PT_DIRECTORY_LEVEL;
4327         else
4328                 /* For shadow and EPT supported 1GB page */
4329                 return PT_PDPE_LEVEL;
4330 }
4331
4332 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4333 {
4334         struct kvm_cpuid_entry2 *best;
4335         struct vcpu_vmx *vmx = to_vmx(vcpu);
4336         u32 exec_control;
4337
4338         vmx->rdtscp_enabled = false;
4339         if (vmx_rdtscp_supported()) {
4340                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4341                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4342                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4343                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4344                                 vmx->rdtscp_enabled = true;
4345                         else {
4346                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4347                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4348                                                 exec_control);
4349                         }
4350                 }
4351         }
4352 }
4353
4354 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4355 {
4356 }
4357
4358 static struct kvm_x86_ops vmx_x86_ops = {
4359         .cpu_has_kvm_support = cpu_has_kvm_support,
4360         .disabled_by_bios = vmx_disabled_by_bios,
4361         .hardware_setup = hardware_setup,
4362         .hardware_unsetup = hardware_unsetup,
4363         .check_processor_compatibility = vmx_check_processor_compat,
4364         .hardware_enable = hardware_enable,
4365         .hardware_disable = hardware_disable,
4366         .cpu_has_accelerated_tpr = report_flexpriority,
4367
4368         .vcpu_create = vmx_create_vcpu,
4369         .vcpu_free = vmx_free_vcpu,
4370         .vcpu_reset = vmx_vcpu_reset,
4371
4372         .prepare_guest_switch = vmx_save_host_state,
4373         .vcpu_load = vmx_vcpu_load,
4374         .vcpu_put = vmx_vcpu_put,
4375
4376         .set_guest_debug = set_guest_debug,
4377         .get_msr = vmx_get_msr,
4378         .set_msr = vmx_set_msr,
4379         .get_segment_base = vmx_get_segment_base,
4380         .get_segment = vmx_get_segment,
4381         .set_segment = vmx_set_segment,
4382         .get_cpl = vmx_get_cpl,
4383         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4384         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
4385         .decache_cr3 = vmx_decache_cr3,
4386         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4387         .set_cr0 = vmx_set_cr0,
4388         .set_cr3 = vmx_set_cr3,
4389         .set_cr4 = vmx_set_cr4,
4390         .set_efer = vmx_set_efer,
4391         .get_idt = vmx_get_idt,
4392         .set_idt = vmx_set_idt,
4393         .get_gdt = vmx_get_gdt,
4394         .set_gdt = vmx_set_gdt,
4395         .set_dr7 = vmx_set_dr7,
4396         .cache_reg = vmx_cache_reg,
4397         .get_rflags = vmx_get_rflags,
4398         .set_rflags = vmx_set_rflags,
4399         .fpu_activate = vmx_fpu_activate,
4400         .fpu_deactivate = vmx_fpu_deactivate,
4401
4402         .tlb_flush = vmx_flush_tlb,
4403
4404         .run = vmx_vcpu_run,
4405         .handle_exit = vmx_handle_exit,
4406         .skip_emulated_instruction = skip_emulated_instruction,
4407         .set_interrupt_shadow = vmx_set_interrupt_shadow,
4408         .get_interrupt_shadow = vmx_get_interrupt_shadow,
4409         .patch_hypercall = vmx_patch_hypercall,
4410         .set_irq = vmx_inject_irq,
4411         .set_nmi = vmx_inject_nmi,
4412         .queue_exception = vmx_queue_exception,
4413         .cancel_injection = vmx_cancel_injection,
4414         .interrupt_allowed = vmx_interrupt_allowed,
4415         .nmi_allowed = vmx_nmi_allowed,
4416         .get_nmi_mask = vmx_get_nmi_mask,
4417         .set_nmi_mask = vmx_set_nmi_mask,
4418         .enable_nmi_window = enable_nmi_window,
4419         .enable_irq_window = enable_irq_window,
4420         .update_cr8_intercept = update_cr8_intercept,
4421
4422         .set_tss_addr = vmx_set_tss_addr,
4423         .get_tdp_level = get_ept_level,
4424         .get_mt_mask = vmx_get_mt_mask,
4425
4426         .get_exit_info = vmx_get_exit_info,
4427         .exit_reasons_str = vmx_exit_reasons_str,
4428
4429         .get_lpage_level = vmx_get_lpage_level,
4430
4431         .cpuid_update = vmx_cpuid_update,
4432
4433         .rdtscp_supported = vmx_rdtscp_supported,
4434
4435         .set_supported_cpuid = vmx_set_supported_cpuid,
4436
4437         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
4438
4439         .write_tsc_offset = vmx_write_tsc_offset,
4440         .adjust_tsc_offset = vmx_adjust_tsc_offset,
4441
4442         .set_tdp_cr3 = vmx_set_cr3,
4443 };
4444
4445 static int __init vmx_init(void)
4446 {
4447         int r, i;
4448
4449         rdmsrl_safe(MSR_EFER, &host_efer);
4450
4451         for (i = 0; i < NR_VMX_MSR; ++i)
4452                 kvm_define_shared_msr(i, vmx_msr_index[i]);
4453
4454         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4455         if (!vmx_io_bitmap_a)
4456                 return -ENOMEM;
4457
4458         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4459         if (!vmx_io_bitmap_b) {
4460                 r = -ENOMEM;
4461                 goto out;
4462         }
4463
4464         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4465         if (!vmx_msr_bitmap_legacy) {
4466                 r = -ENOMEM;
4467                 goto out1;
4468         }
4469
4470         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4471         if (!vmx_msr_bitmap_longmode) {
4472                 r = -ENOMEM;
4473                 goto out2;
4474         }
4475
4476         /*
4477          * Allow direct access to the PC debug port (it is often used for I/O
4478          * delays, but the vmexits simply slow things down).
4479          */
4480         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4481         clear_bit(0x80, vmx_io_bitmap_a);
4482
4483         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4484
4485         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4486         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4487
4488         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4489
4490         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4491                      __alignof__(struct vcpu_vmx), THIS_MODULE);
4492         if (r)
4493                 goto out3;
4494
4495         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4496         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4497         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4498         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4499         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4500         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4501
4502         if (enable_ept) {
4503                 bypass_guest_pf = 0;
4504                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4505                                 VMX_EPT_EXECUTABLE_MASK);
4506                 kvm_enable_tdp();
4507         } else
4508                 kvm_disable_tdp();
4509
4510         if (bypass_guest_pf)
4511                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4512
4513         return 0;
4514
4515 out3:
4516         free_page((unsigned long)vmx_msr_bitmap_longmode);
4517 out2:
4518         free_page((unsigned long)vmx_msr_bitmap_legacy);
4519 out1:
4520         free_page((unsigned long)vmx_io_bitmap_b);
4521 out:
4522         free_page((unsigned long)vmx_io_bitmap_a);
4523         return r;
4524 }
4525
4526 static void __exit vmx_exit(void)
4527 {
4528         free_page((unsigned long)vmx_msr_bitmap_legacy);
4529         free_page((unsigned long)vmx_msr_bitmap_longmode);
4530         free_page((unsigned long)vmx_io_bitmap_b);
4531         free_page((unsigned long)vmx_io_bitmap_a);
4532
4533         kvm_exit();
4534 }
4535
4536 module_init(vmx_init)
4537 module_exit(vmx_exit)