arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/ftrace_event.h>
  31 #include <linux/slab.h>
  32 #include <linux/tboot.h>
  33 #include "kvm_cache_regs.h"
  34 #include "x86.h"
  35
  36 #include <asm/io.h>
  37 #include <asm/desc.h>
  38 #include <asm/vmx.h>
  39 #include <asm/virtext.h>
  40 #include <asm/mce.h>
  41 #include <asm/i387.h>
  42 #include <asm/xcr.h>
  43 #include <asm/perf_event.h>
  44
  45 #include "trace.h"
  46
  47 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  48 #define __ex_clear(x, reg) \
  49         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  50
  51 MODULE_AUTHOR("Qumranet");
  52 MODULE_LICENSE("GPL");
  53
  54 static bool __read_mostly enable_vpid = 1;
  55 module_param_named(vpid, enable_vpid, bool, 0444);
  56
  57 static bool __read_mostly flexpriority_enabled = 1;
  58 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  59
  60 static bool __read_mostly enable_ept = 1;
  61 module_param_named(ept, enable_ept, bool, S_IRUGO);
  62
  63 static bool __read_mostly enable_unrestricted_guest = 1;
  64 module_param_named(unrestricted_guest,
  65                         enable_unrestricted_guest, bool, S_IRUGO);
  66
  67 static bool __read_mostly emulate_invalid_guest_state = 0;
  68 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  69
  70 static bool __read_mostly vmm_exclusive = 1;
  71 module_param(vmm_exclusive, bool, S_IRUGO);
  72
  73 static bool __read_mostly fasteoi = 1;
  74 module_param(fasteoi, bool, S_IRUGO);
  75
  76 /*
  77  * If nested=1, nested virtualization is supported, i.e., guests may use
  78  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  79  * use VMX instructions.
  80  */
  81 static bool __read_mostly nested = 0;
  82 module_param(nested, bool, S_IRUGO);
  83
  84 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  85         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
  86 #define KVM_GUEST_CR0_MASK                                              \
  87         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  88 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
  89         (X86_CR0_WP | X86_CR0_NE)
  90 #define KVM_VM_CR0_ALWAYS_ON                                            \
  91         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  92 #define KVM_CR4_GUEST_OWNED_BITS                                      \
  93         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
  94          | X86_CR4_OSXMMEXCPT)
  95
  96 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
  97 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
  98
  99 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 100
 101 /*
 102  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 103  * ple_gap:    upper bound on the amount of time between two successive
 104  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 105  *             According to test, this time is usually smaller than 128 cycles.
 106  * ple_window: upper bound on the amount of time a guest is allowed to execute
 107  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 108  *             less than 2^12 cycles
 109  * Time is measured based on a counter that runs at the same rate as the TSC,
 110  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 111  */
 112 #define KVM_VMX_DEFAULT_PLE_GAP    128
 113 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 114 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 115 module_param(ple_gap, int, S_IRUGO);
 116
 117 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 118 module_param(ple_window, int, S_IRUGO);
 119
 120 #define NR_AUTOLOAD_MSRS 8
 121 #define VMCS02_POOL_SIZE 1
 122
 123 struct vmcs {
 124         u32 revision_id;
 125         u32 abort;
 126         char data[0];
 127 };
 128
 129 /*
 130  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 131  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 132  * loaded on this CPU (so we can clear them if the CPU goes down).
 133  */
 134 struct loaded_vmcs {
 135         struct vmcs *vmcs;
 136         int cpu;
 137         int launched;
 138         struct list_head loaded_vmcss_on_cpu_link;
 139 };
 140
 141 struct shared_msr_entry {
 142         unsigned index;
 143         u64 data;
 144         u64 mask;
 145 };
 146
 147 /*
 148  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 149  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 150  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 151  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 152  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 153  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 154  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 155  * underlying hardware which will be used to run L2.
 156  * This structure is packed to ensure that its layout is identical across
 157  * machines (necessary for live migration).
 158  * If there are changes in this struct, VMCS12_REVISION must be changed.
 159  */
 160 typedef u64 natural_width;
 161 struct __packed vmcs12 {
 162         /* According to the Intel spec, a VMCS region must start with the
 163          * following two fields. Then follow implementation-specific data.
 164          */
 165         u32 revision_id;
 166         u32 abort;
 167
 168         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 169         u32 padding[7]; /* room for future expansion */
 170
 171         u64 io_bitmap_a;
 172         u64 io_bitmap_b;
 173         u64 msr_bitmap;
 174         u64 vm_exit_msr_store_addr;
 175         u64 vm_exit_msr_load_addr;
 176         u64 vm_entry_msr_load_addr;
 177         u64 tsc_offset;
 178         u64 virtual_apic_page_addr;
 179         u64 apic_access_addr;
 180         u64 ept_pointer;
 181         u64 guest_physical_address;
 182         u64 vmcs_link_pointer;
 183         u64 guest_ia32_debugctl;
 184         u64 guest_ia32_pat;
 185         u64 guest_ia32_efer;
 186         u64 guest_ia32_perf_global_ctrl;
 187         u64 guest_pdptr0;
 188         u64 guest_pdptr1;
 189         u64 guest_pdptr2;
 190         u64 guest_pdptr3;
 191         u64 host_ia32_pat;
 192         u64 host_ia32_efer;
 193         u64 host_ia32_perf_global_ctrl;
 194         u64 padding64[8]; /* room for future expansion */
 195         /*
 196          * To allow migration of L1 (complete with its L2 guests) between
 197          * machines of different natural widths (32 or 64 bit), we cannot have
 198          * unsigned long fields with no explict size. We use u64 (aliased
 199          * natural_width) instead. Luckily, x86 is little-endian.
 200          */
 201         natural_width cr0_guest_host_mask;
 202         natural_width cr4_guest_host_mask;
 203         natural_width cr0_read_shadow;
 204         natural_width cr4_read_shadow;
 205         natural_width cr3_target_value0;
 206         natural_width cr3_target_value1;
 207         natural_width cr3_target_value2;
 208         natural_width cr3_target_value3;
 209         natural_width exit_qualification;
 210         natural_width guest_linear_address;
 211         natural_width guest_cr0;
 212         natural_width guest_cr3;
 213         natural_width guest_cr4;
 214         natural_width guest_es_base;
 215         natural_width guest_cs_base;
 216         natural_width guest_ss_base;
 217         natural_width guest_ds_base;
 218         natural_width guest_fs_base;
 219         natural_width guest_gs_base;
 220         natural_width guest_ldtr_base;
 221         natural_width guest_tr_base;
 222         natural_width guest_gdtr_base;
 223         natural_width guest_idtr_base;
 224         natural_width guest_dr7;
 225         natural_width guest_rsp;
 226         natural_width guest_rip;
 227         natural_width guest_rflags;
 228         natural_width guest_pending_dbg_exceptions;
 229         natural_width guest_sysenter_esp;
 230         natural_width guest_sysenter_eip;
 231         natural_width host_cr0;
 232         natural_width host_cr3;
 233         natural_width host_cr4;
 234         natural_width host_fs_base;
 235         natural_width host_gs_base;
 236         natural_width host_tr_base;
 237         natural_width host_gdtr_base;
 238         natural_width host_idtr_base;
 239         natural_width host_ia32_sysenter_esp;
 240         natural_width host_ia32_sysenter_eip;
 241         natural_width host_rsp;
 242         natural_width host_rip;
 243         natural_width paddingl[8]; /* room for future expansion */
 244         u32 pin_based_vm_exec_control;
 245         u32 cpu_based_vm_exec_control;
 246         u32 exception_bitmap;
 247         u32 page_fault_error_code_mask;
 248         u32 page_fault_error_code_match;
 249         u32 cr3_target_count;
 250         u32 vm_exit_controls;
 251         u32 vm_exit_msr_store_count;
 252         u32 vm_exit_msr_load_count;
 253         u32 vm_entry_controls;
 254         u32 vm_entry_msr_load_count;
 255         u32 vm_entry_intr_info_field;
 256         u32 vm_entry_exception_error_code;
 257         u32 vm_entry_instruction_len;
 258         u32 tpr_threshold;
 259         u32 secondary_vm_exec_control;
 260         u32 vm_instruction_error;
 261         u32 vm_exit_reason;
 262         u32 vm_exit_intr_info;
 263         u32 vm_exit_intr_error_code;
 264         u32 idt_vectoring_info_field;
 265         u32 idt_vectoring_error_code;
 266         u32 vm_exit_instruction_len;
 267         u32 vmx_instruction_info;
 268         u32 guest_es_limit;
 269         u32 guest_cs_limit;
 270         u32 guest_ss_limit;
 271         u32 guest_ds_limit;
 272         u32 guest_fs_limit;
 273         u32 guest_gs_limit;
 274         u32 guest_ldtr_limit;
 275         u32 guest_tr_limit;
 276         u32 guest_gdtr_limit;
 277         u32 guest_idtr_limit;
 278         u32 guest_es_ar_bytes;
 279         u32 guest_cs_ar_bytes;
 280         u32 guest_ss_ar_bytes;
 281         u32 guest_ds_ar_bytes;
 282         u32 guest_fs_ar_bytes;
 283         u32 guest_gs_ar_bytes;
 284         u32 guest_ldtr_ar_bytes;
 285         u32 guest_tr_ar_bytes;
 286         u32 guest_interruptibility_info;
 287         u32 guest_activity_state;
 288         u32 guest_sysenter_cs;
 289         u32 host_ia32_sysenter_cs;
 290         u32 padding32[8]; /* room for future expansion */
 291         u16 virtual_processor_id;
 292         u16 guest_es_selector;
 293         u16 guest_cs_selector;
 294         u16 guest_ss_selector;
 295         u16 guest_ds_selector;
 296         u16 guest_fs_selector;
 297         u16 guest_gs_selector;
 298         u16 guest_ldtr_selector;
 299         u16 guest_tr_selector;
 300         u16 host_es_selector;
 301         u16 host_cs_selector;
 302         u16 host_ss_selector;
 303         u16 host_ds_selector;
 304         u16 host_fs_selector;
 305         u16 host_gs_selector;
 306         u16 host_tr_selector;
 307 };
 308
 309 /*
 310  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 311  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 312  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 313  */
 314 #define VMCS12_REVISION 0x11e57ed0
 315
 316 /*
 317  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 318  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 319  * current implementation, 4K are reserved to avoid future complications.
 320  */
 321 #define VMCS12_SIZE 0x1000
 322
 323 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 324 struct vmcs02_list {
 325         struct list_head list;
 326         gpa_t vmptr;
 327         struct loaded_vmcs vmcs02;
 328 };
 329
 330 /*
 331  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 332  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 333  */
 334 struct nested_vmx {
 335         /* Has the level1 guest done vmxon? */
 336         bool vmxon;
 337
 338         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 339         gpa_t current_vmptr;
 340         /* The host-usable pointer to the above */
 341         struct page *current_vmcs12_page;
 342         struct vmcs12 *current_vmcs12;
 343
 344         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 345         struct list_head vmcs02_pool;
 346         int vmcs02_num;
 347         u64 vmcs01_tsc_offset;
 348         /* L2 must run next, and mustn't decide to exit to L1. */
 349         bool nested_run_pending;
 350         /*
 351          * Guest pages referred to in vmcs02 with host-physical pointers, so
 352          * we must keep them pinned while L2 runs.
 353          */
 354         struct page *apic_access_page;
 355 };
 356
 357 struct vcpu_vmx {
 358         struct kvm_vcpu       vcpu;
 359         unsigned long         host_rsp;
 360         u8                    fail;
 361         u8                    cpl;
 362         bool                  nmi_known_unmasked;
 363         u32                   exit_intr_info;
 364         u32                   idt_vectoring_info;
 365         ulong                 rflags;
 366         struct shared_msr_entry *guest_msrs;
 367         int                   nmsrs;
 368         int                   save_nmsrs;
 369 #ifdef CONFIG_X86_64
 370         u64                   msr_host_kernel_gs_base;
 371         u64                   msr_guest_kernel_gs_base;
 372 #endif
 373         /*
 374          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 375          * non-nested (L1) guest, it always points to vmcs01. For a nested
 376          * guest (L2), it points to a different VMCS.
 377          */
 378         struct loaded_vmcs    vmcs01;
 379         struct loaded_vmcs   *loaded_vmcs;
 380         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 381         struct msr_autoload {
 382                 unsigned nr;
 383                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 384                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 385         } msr_autoload;
 386         struct {
 387                 int           loaded;
 388                 u16           fs_sel, gs_sel, ldt_sel;
 389                 int           gs_ldt_reload_needed;
 390                 int           fs_reload_needed;
 391         } host_state;
 392         struct {
 393                 int vm86_active;
 394                 ulong save_rflags;
 395                 struct kvm_save_segment {
 396                         u16 selector;
 397                         unsigned long base;
 398                         u32 limit;
 399                         u32 ar;
 400                 } tr, es, ds, fs, gs;
 401         } rmode;
 402         struct {
 403                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 404                 struct kvm_save_segment seg[8];
 405         } segment_cache;
 406         int vpid;
 407         bool emulation_required;
 408
 409         /* Support for vnmi-less CPUs */
 410         int soft_vnmi_blocked;
 411         ktime_t entry_time;
 412         s64 vnmi_blocked_time;
 413         u32 exit_reason;
 414
 415         bool rdtscp_enabled;
 416
 417         /* Support for a guest hypervisor (nested VMX) */
 418         struct nested_vmx nested;
 419 };
 420
 421 enum segment_cache_field {
 422         SEG_FIELD_SEL = 0,
 423         SEG_FIELD_BASE = 1,
 424         SEG_FIELD_LIMIT = 2,
 425         SEG_FIELD_AR = 3,
 426
 427         SEG_FIELD_NR = 4
 428 };
 429
 430 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 431 {
 432         return container_of(vcpu, struct vcpu_vmx, vcpu);
 433 }
 434
 435 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 436 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 437 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 438                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 439
 440 static unsigned short vmcs_field_to_offset_table[] = {
 441         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 442         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 443         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 444         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 445         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 446         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 447         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 448         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 449         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 450         FIELD(HOST_ES_SELECTOR, host_es_selector),
 451         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 452         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 453         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 454         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 455         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 456         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 457         FIELD64(IO_BITMAP_A, io_bitmap_a),
 458         FIELD64(IO_BITMAP_B, io_bitmap_b),
 459         FIELD64(MSR_BITMAP, msr_bitmap),
 460         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 461         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 462         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 463         FIELD64(TSC_OFFSET, tsc_offset),
 464         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 465         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 466         FIELD64(EPT_POINTER, ept_pointer),
 467         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 468         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 469         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 470         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 471         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 472         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 473         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 474         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 475         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 476         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 477         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 478         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 479         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 480         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 481         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 482         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 483         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 484         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 485         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 486         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 487         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 488         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 489         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 490         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 491         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 492         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 493         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 494         FIELD(TPR_THRESHOLD, tpr_threshold),
 495         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 496         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 497         FIELD(VM_EXIT_REASON, vm_exit_reason),
 498         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 499         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 500         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 501         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 502         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 503         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 504         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 505         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 506         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 507         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 508         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 509         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 510         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 511         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 512         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 513         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 514         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 515         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 516         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 517         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 518         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 519         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 520         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 521         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 522         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 523         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 524         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 525         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 526         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 527         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 528         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 529         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 530         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 531         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 532         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 533         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 534         FIELD(EXIT_QUALIFICATION, exit_qualification),
 535         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 536         FIELD(GUEST_CR0, guest_cr0),
 537         FIELD(GUEST_CR3, guest_cr3),
 538         FIELD(GUEST_CR4, guest_cr4),
 539         FIELD(GUEST_ES_BASE, guest_es_base),
 540         FIELD(GUEST_CS_BASE, guest_cs_base),
 541         FIELD(GUEST_SS_BASE, guest_ss_base),
 542         FIELD(GUEST_DS_BASE, guest_ds_base),
 543         FIELD(GUEST_FS_BASE, guest_fs_base),
 544         FIELD(GUEST_GS_BASE, guest_gs_base),
 545         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 546         FIELD(GUEST_TR_BASE, guest_tr_base),
 547         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 548         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 549         FIELD(GUEST_DR7, guest_dr7),
 550         FIELD(GUEST_RSP, guest_rsp),
 551         FIELD(GUEST_RIP, guest_rip),
 552         FIELD(GUEST_RFLAGS, guest_rflags),
 553         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 554         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 555         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 556         FIELD(HOST_CR0, host_cr0),
 557         FIELD(HOST_CR3, host_cr3),
 558         FIELD(HOST_CR4, host_cr4),
 559         FIELD(HOST_FS_BASE, host_fs_base),
 560         FIELD(HOST_GS_BASE, host_gs_base),
 561         FIELD(HOST_TR_BASE, host_tr_base),
 562         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 563         FIELD(HOST_IDTR_BASE, host_idtr_base),
 564         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 565         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 566         FIELD(HOST_RSP, host_rsp),
 567         FIELD(HOST_RIP, host_rip),
 568 };
 569 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 570
 571 static inline short vmcs_field_to_offset(unsigned long field)
 572 {
 573         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 574                 return -1;
 575         return vmcs_field_to_offset_table[field];
 576 }
 577
 578 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 579 {
 580         return to_vmx(vcpu)->nested.current_vmcs12;
 581 }
 582
 583 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 584 {
 585         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 586         if (is_error_page(page)) {
 587                 kvm_release_page_clean(page);
 588                 return NULL;
 589         }
 590         return page;
 591 }
 592
 593 static void nested_release_page(struct page *page)
 594 {
 595         kvm_release_page_dirty(page);
 596 }
 597
 598 static void nested_release_page_clean(struct page *page)
 599 {
 600         kvm_release_page_clean(page);
 601 }
 602
 603 static u64 construct_eptp(unsigned long root_hpa);
 604 static void kvm_cpu_vmxon(u64 addr);
 605 static void kvm_cpu_vmxoff(void);
 606 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
 607 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 608
 609 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 610 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 611 /*
 612  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 613  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 614  */
 615 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 616 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 617
 618 static unsigned long *vmx_io_bitmap_a;
 619 static unsigned long *vmx_io_bitmap_b;
 620 static unsigned long *vmx_msr_bitmap_legacy;
 621 static unsigned long *vmx_msr_bitmap_longmode;
 622
 623 static bool cpu_has_load_ia32_efer;
 624 static bool cpu_has_load_perf_global_ctrl;
 625
 626 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 627 static DEFINE_SPINLOCK(vmx_vpid_lock);
 628
 629 static struct vmcs_config {
 630         int size;
 631         int order;
 632         u32 revision_id;
 633         u32 pin_based_exec_ctrl;
 634         u32 cpu_based_exec_ctrl;
 635         u32 cpu_based_2nd_exec_ctrl;
 636         u32 vmexit_ctrl;
 637         u32 vmentry_ctrl;
 638 } vmcs_config;
 639
 640 static struct vmx_capability {
 641         u32 ept;
 642         u32 vpid;
 643 } vmx_capability;
 644
 645 #define VMX_SEGMENT_FIELD(seg)                                  \
 646         [VCPU_SREG_##seg] = {                                   \
 647                 .selector = GUEST_##seg##_SELECTOR,             \
 648                 .base = GUEST_##seg##_BASE,                     \
 649                 .limit = GUEST_##seg##_LIMIT,                   \
 650                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 651         }
 652
 653 static struct kvm_vmx_segment_field {
 654         unsigned selector;
 655         unsigned base;
 656         unsigned limit;
 657         unsigned ar_bytes;
 658 } kvm_vmx_segment_fields[] = {
 659         VMX_SEGMENT_FIELD(CS),
 660         VMX_SEGMENT_FIELD(DS),
 661         VMX_SEGMENT_FIELD(ES),
 662         VMX_SEGMENT_FIELD(FS),
 663         VMX_SEGMENT_FIELD(GS),
 664         VMX_SEGMENT_FIELD(SS),
 665         VMX_SEGMENT_FIELD(TR),
 666         VMX_SEGMENT_FIELD(LDTR),
 667 };
 668
 669 static u64 host_efer;
 670
 671 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 672
 673 /*
 674  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 675  * away by decrementing the array size.
 676  */
 677 static const u32 vmx_msr_index[] = {
 678 #ifdef CONFIG_X86_64
 679         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 680 #endif
 681         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 682 };
 683 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 684
 685 static inline bool is_page_fault(u32 intr_info)
 686 {
 687         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 688                              INTR_INFO_VALID_MASK)) ==
 689                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 690 }
 691
 692 static inline bool is_no_device(u32 intr_info)
 693 {
 694         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 695                              INTR_INFO_VALID_MASK)) ==
 696                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 697 }
 698
 699 static inline bool is_invalid_opcode(u32 intr_info)
 700 {
 701         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 702                              INTR_INFO_VALID_MASK)) ==
 703                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 704 }
 705
 706 static inline bool is_external_interrupt(u32 intr_info)
 707 {
 708         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 709                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 710 }
 711
 712 static inline bool is_machine_check(u32 intr_info)
 713 {
 714         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 715                              INTR_INFO_VALID_MASK)) ==
 716                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 717 }
 718
 719 static inline bool cpu_has_vmx_msr_bitmap(void)
 720 {
 721         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 722 }
 723
 724 static inline bool cpu_has_vmx_tpr_shadow(void)
 725 {
 726         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 727 }
 728
 729 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 730 {
 731         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 732 }
 733
 734 static inline bool cpu_has_secondary_exec_ctrls(void)
 735 {
 736         return vmcs_config.cpu_based_exec_ctrl &
 737                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 738 }
 739
 740 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 741 {
 742         return vmcs_config.cpu_based_2nd_exec_ctrl &
 743                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 744 }
 745
 746 static inline bool cpu_has_vmx_flexpriority(void)
 747 {
 748         return cpu_has_vmx_tpr_shadow() &&
 749                 cpu_has_vmx_virtualize_apic_accesses();
 750 }
 751
 752 static inline bool cpu_has_vmx_ept_execute_only(void)
 753 {
 754         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 755 }
 756
 757 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 758 {
 759         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 760 }
 761
 762 static inline bool cpu_has_vmx_eptp_writeback(void)
 763 {
 764         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 765 }
 766
 767 static inline bool cpu_has_vmx_ept_2m_page(void)
 768 {
 769         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 770 }
 771
 772 static inline bool cpu_has_vmx_ept_1g_page(void)
 773 {
 774         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 775 }
 776
 777 static inline bool cpu_has_vmx_ept_4levels(void)
 778 {
 779         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 780 }
 781
 782 static inline bool cpu_has_vmx_invept_individual_addr(void)
 783 {
 784         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
 785 }
 786
 787 static inline bool cpu_has_vmx_invept_context(void)
 788 {
 789         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 790 }
 791
 792 static inline bool cpu_has_vmx_invept_global(void)
 793 {
 794         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 795 }
 796
 797 static inline bool cpu_has_vmx_invvpid_single(void)
 798 {
 799         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 800 }
 801
 802 static inline bool cpu_has_vmx_invvpid_global(void)
 803 {
 804         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 805 }
 806
 807 static inline bool cpu_has_vmx_ept(void)
 808 {
 809         return vmcs_config.cpu_based_2nd_exec_ctrl &
 810                 SECONDARY_EXEC_ENABLE_EPT;
 811 }
 812
 813 static inline bool cpu_has_vmx_unrestricted_guest(void)
 814 {
 815         return vmcs_config.cpu_based_2nd_exec_ctrl &
 816                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 817 }
 818
 819 static inline bool cpu_has_vmx_ple(void)
 820 {
 821         return vmcs_config.cpu_based_2nd_exec_ctrl &
 822                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 823 }
 824
 825 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 826 {
 827         return flexpriority_enabled && irqchip_in_kernel(kvm);
 828 }
 829
 830 static inline bool cpu_has_vmx_vpid(void)
 831 {
 832         return vmcs_config.cpu_based_2nd_exec_ctrl &
 833                 SECONDARY_EXEC_ENABLE_VPID;
 834 }
 835
 836 static inline bool cpu_has_vmx_rdtscp(void)
 837 {
 838         return vmcs_config.cpu_based_2nd_exec_ctrl &
 839                 SECONDARY_EXEC_RDTSCP;
 840 }
 841
 842 static inline bool cpu_has_virtual_nmis(void)
 843 {
 844         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 845 }
 846
 847 static inline bool cpu_has_vmx_wbinvd_exit(void)
 848 {
 849         return vmcs_config.cpu_based_2nd_exec_ctrl &
 850                 SECONDARY_EXEC_WBINVD_EXITING;
 851 }
 852
 853 static inline bool report_flexpriority(void)
 854 {
 855         return flexpriority_enabled;
 856 }
 857
 858 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
 859 {
 860         return vmcs12->cpu_based_vm_exec_control & bit;
 861 }
 862
 863 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
 864 {
 865         return (vmcs12->cpu_based_vm_exec_control &
 866                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
 867                 (vmcs12->secondary_vm_exec_control & bit);
 868 }
 869
 870 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
 871         struct kvm_vcpu *vcpu)
 872 {
 873         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
 874 }
 875
 876 static inline bool is_exception(u32 intr_info)
 877 {
 878         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 879                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
 880 }
 881
 882 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
 883 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
 884                         struct vmcs12 *vmcs12,
 885                         u32 reason, unsigned long qualification);
 886
 887 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 888 {
 889         int i;
 890
 891         for (i = 0; i < vmx->nmsrs; ++i)
 892                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 893                         return i;
 894         return -1;
 895 }
 896
 897 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 898 {
 899     struct {
 900         u64 vpid : 16;
 901         u64 rsvd : 48;
 902         u64 gva;
 903     } operand = { vpid, 0, gva };
 904
 905     asm volatile (__ex(ASM_VMX_INVVPID)
 906                   /* CF==1 or ZF==1 --> rc = -1 */
 907                   "; ja 1f ; ud2 ; 1:"
 908                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 909 }
 910
 911 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 912 {
 913         struct {
 914                 u64 eptp, gpa;
 915         } operand = {eptp, gpa};
 916
 917         asm volatile (__ex(ASM_VMX_INVEPT)
 918                         /* CF==1 or ZF==1 --> rc = -1 */
 919                         "; ja 1f ; ud2 ; 1:\n"
 920                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 921 }
 922
 923 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 924 {
 925         int i;
 926
 927         i = __find_msr_index(vmx, msr);
 928         if (i >= 0)
 929                 return &vmx->guest_msrs[i];
 930         return NULL;
 931 }
 932
 933 static void vmcs_clear(struct vmcs *vmcs)
 934 {
 935         u64 phys_addr = __pa(vmcs);
 936         u8 error;
 937
 938         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 939                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 940                       : "cc", "memory");
 941         if (error)
 942                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 943                        vmcs, phys_addr);
 944 }
 945
 946 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
 947 {
 948         vmcs_clear(loaded_vmcs->vmcs);
 949         loaded_vmcs->cpu = -1;
 950         loaded_vmcs->launched = 0;
 951 }
 952
 953 static void vmcs_load(struct vmcs *vmcs)
 954 {
 955         u64 phys_addr = __pa(vmcs);
 956         u8 error;
 957
 958         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 959                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 960                         : "cc", "memory");
 961         if (error)
 962                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
 963                        vmcs, phys_addr);
 964 }
 965
 966 static void __loaded_vmcs_clear(void *arg)
 967 {
 968         struct loaded_vmcs *loaded_vmcs = arg;
 969         int cpu = raw_smp_processor_id();
 970
 971         if (loaded_vmcs->cpu != cpu)
 972                 return; /* vcpu migration can race with cpu offline */
 973         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
 974                 per_cpu(current_vmcs, cpu) = NULL;
 975         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
 976         loaded_vmcs_init(loaded_vmcs);
 977 }
 978
 979 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
 980 {
 981         if (loaded_vmcs->cpu != -1)
 982                 smp_call_function_single(
 983                         loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
 984 }
 985
 986 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
 987 {
 988         if (vmx->vpid == 0)
 989                 return;
 990
 991         if (cpu_has_vmx_invvpid_single())
 992                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 993 }
 994
 995 static inline void vpid_sync_vcpu_global(void)
 996 {
 997         if (cpu_has_vmx_invvpid_global())
 998                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
 999 }
1000
1001 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1002 {
1003         if (cpu_has_vmx_invvpid_single())
1004                 vpid_sync_vcpu_single(vmx);
1005         else
1006                 vpid_sync_vcpu_global();
1007 }
1008
1009 static inline void ept_sync_global(void)
1010 {
1011         if (cpu_has_vmx_invept_global())
1012                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1013 }
1014
1015 static inline void ept_sync_context(u64 eptp)
1016 {
1017         if (enable_ept) {
1018                 if (cpu_has_vmx_invept_context())
1019                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1020                 else
1021                         ept_sync_global();
1022         }
1023 }
1024
1025 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1026 {
1027         if (enable_ept) {
1028                 if (cpu_has_vmx_invept_individual_addr())
1029                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1030                                         eptp, gpa);
1031                 else
1032                         ept_sync_context(eptp);
1033         }
1034 }
1035
1036 static __always_inline unsigned long vmcs_readl(unsigned long field)
1037 {
1038         unsigned long value;
1039
1040         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1041                       : "=a"(value) : "d"(field) : "cc");
1042         return value;
1043 }
1044
1045 static __always_inline u16 vmcs_read16(unsigned long field)
1046 {
1047         return vmcs_readl(field);
1048 }
1049
1050 static __always_inline u32 vmcs_read32(unsigned long field)
1051 {
1052         return vmcs_readl(field);
1053 }
1054
1055 static __always_inline u64 vmcs_read64(unsigned long field)
1056 {
1057 #ifdef CONFIG_X86_64
1058         return vmcs_readl(field);
1059 #else
1060         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1061 #endif
1062 }
1063
1064 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1065 {
1066         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1067                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1068         dump_stack();
1069 }
1070
1071 static void vmcs_writel(unsigned long field, unsigned long value)
1072 {
1073         u8 error;
1074
1075         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1076                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1077         if (unlikely(error))
1078                 vmwrite_error(field, value);
1079 }
1080
1081 static void vmcs_write16(unsigned long field, u16 value)
1082 {
1083         vmcs_writel(field, value);
1084 }
1085
1086 static void vmcs_write32(unsigned long field, u32 value)
1087 {
1088         vmcs_writel(field, value);
1089 }
1090
1091 static void vmcs_write64(unsigned long field, u64 value)
1092 {
1093         vmcs_writel(field, value);
1094 #ifndef CONFIG_X86_64
1095         asm volatile ("");
1096         vmcs_writel(field+1, value >> 32);
1097 #endif
1098 }
1099
1100 static void vmcs_clear_bits(unsigned long field, u32 mask)
1101 {
1102         vmcs_writel(field, vmcs_readl(field) & ~mask);
1103 }
1104
1105 static void vmcs_set_bits(unsigned long field, u32 mask)
1106 {
1107         vmcs_writel(field, vmcs_readl(field) | mask);
1108 }
1109
1110 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1111 {
1112         vmx->segment_cache.bitmask = 0;
1113 }
1114
1115 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1116                                        unsigned field)
1117 {
1118         bool ret;
1119         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1120
1121         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1122                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1123                 vmx->segment_cache.bitmask = 0;
1124         }
1125         ret = vmx->segment_cache.bitmask & mask;
1126         vmx->segment_cache.bitmask |= mask;
1127         return ret;
1128 }
1129
1130 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1131 {
1132         u16 *p = &vmx->segment_cache.seg[seg].selector;
1133
1134         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1135                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1136         return *p;
1137 }
1138
1139 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1140 {
1141         ulong *p = &vmx->segment_cache.seg[seg].base;
1142
1143         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1144                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1145         return *p;
1146 }
1147
1148 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1149 {
1150         u32 *p = &vmx->segment_cache.seg[seg].limit;
1151
1152         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1153                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1154         return *p;
1155 }
1156
1157 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1158 {
1159         u32 *p = &vmx->segment_cache.seg[seg].ar;
1160
1161         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1162                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1163         return *p;
1164 }
1165
1166 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1167 {
1168         u32 eb;
1169
1170         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1171              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1172         if ((vcpu->guest_debug &
1173              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1174             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1175                 eb |= 1u << BP_VECTOR;
1176         if (to_vmx(vcpu)->rmode.vm86_active)
1177                 eb = ~0;
1178         if (enable_ept)
1179                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1180         if (vcpu->fpu_active)
1181                 eb &= ~(1u << NM_VECTOR);
1182
1183         /* When we are running a nested L2 guest and L1 specified for it a
1184          * certain exception bitmap, we must trap the same exceptions and pass
1185          * them to L1. When running L2, we will only handle the exceptions
1186          * specified above if L1 did not want them.
1187          */
1188         if (is_guest_mode(vcpu))
1189                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1190
1191         vmcs_write32(EXCEPTION_BITMAP, eb);
1192 }
1193
1194 static void clear_atomic_switch_msr_special(unsigned long entry,
1195                 unsigned long exit)
1196 {
1197         vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1198         vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1199 }
1200
1201 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1202 {
1203         unsigned i;
1204         struct msr_autoload *m = &vmx->msr_autoload;
1205
1206         switch (msr) {
1207         case MSR_EFER:
1208                 if (cpu_has_load_ia32_efer) {
1209                         clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1210                                         VM_EXIT_LOAD_IA32_EFER);
1211                         return;
1212                 }
1213                 break;
1214         case MSR_CORE_PERF_GLOBAL_CTRL:
1215                 if (cpu_has_load_perf_global_ctrl) {
1216                         clear_atomic_switch_msr_special(
1217                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1218                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1219                         return;
1220                 }
1221                 break;
1222         }
1223
1224         for (i = 0; i < m->nr; ++i)
1225                 if (m->guest[i].index == msr)
1226                         break;
1227
1228         if (i == m->nr)
1229                 return;
1230         --m->nr;
1231         m->guest[i] = m->guest[m->nr];
1232         m->host[i] = m->host[m->nr];
1233         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1234         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1235 }
1236
1237 static void add_atomic_switch_msr_special(unsigned long entry,
1238                 unsigned long exit, unsigned long guest_val_vmcs,
1239                 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1240 {
1241         vmcs_write64(guest_val_vmcs, guest_val);
1242         vmcs_write64(host_val_vmcs, host_val);
1243         vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1244         vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1245 }
1246
1247 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1248                                   u64 guest_val, u64 host_val)
1249 {
1250         unsigned i;
1251         struct msr_autoload *m = &vmx->msr_autoload;
1252
1253         switch (msr) {
1254         case MSR_EFER:
1255                 if (cpu_has_load_ia32_efer) {
1256                         add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1257                                         VM_EXIT_LOAD_IA32_EFER,
1258                                         GUEST_IA32_EFER,
1259                                         HOST_IA32_EFER,
1260                                         guest_val, host_val);
1261                         return;
1262                 }
1263                 break;
1264         case MSR_CORE_PERF_GLOBAL_CTRL:
1265                 if (cpu_has_load_perf_global_ctrl) {
1266                         add_atomic_switch_msr_special(
1267                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1268                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1269                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1270                                         HOST_IA32_PERF_GLOBAL_CTRL,
1271                                         guest_val, host_val);
1272                         return;
1273                 }
1274                 break;
1275         }
1276
1277         for (i = 0; i < m->nr; ++i)
1278                 if (m->guest[i].index == msr)
1279                         break;
1280
1281         if (i == NR_AUTOLOAD_MSRS) {
1282                 printk_once(KERN_WARNING"Not enough mst switch entries. "
1283                                 "Can't add msr %x\n", msr);
1284                 return;
1285         } else if (i == m->nr) {
1286                 ++m->nr;
1287                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1288                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1289         }
1290
1291         m->guest[i].index = msr;
1292         m->guest[i].value = guest_val;
1293         m->host[i].index = msr;
1294         m->host[i].value = host_val;
1295 }
1296
1297 static void reload_tss(void)
1298 {
1299         /*
1300          * VT restores TR but not its size.  Useless.
1301          */
1302         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1303         struct desc_struct *descs;
1304
1305         descs = (void *)gdt->address;
1306         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1307         load_TR_desc();
1308 }
1309
1310 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1311 {
1312         u64 guest_efer;
1313         u64 ignore_bits;
1314
1315         guest_efer = vmx->vcpu.arch.efer;
1316
1317         /*
1318          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1319          * outside long mode
1320          */
1321         ignore_bits = EFER_NX | EFER_SCE;
1322 #ifdef CONFIG_X86_64
1323         ignore_bits |= EFER_LMA | EFER_LME;
1324         /* SCE is meaningful only in long mode on Intel */
1325         if (guest_efer & EFER_LMA)
1326                 ignore_bits &= ~(u64)EFER_SCE;
1327 #endif
1328         guest_efer &= ~ignore_bits;
1329         guest_efer |= host_efer & ignore_bits;
1330         vmx->guest_msrs[efer_offset].data = guest_efer;
1331         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1332
1333         clear_atomic_switch_msr(vmx, MSR_EFER);
1334         /* On ept, can't emulate nx, and must switch nx atomically */
1335         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1336                 guest_efer = vmx->vcpu.arch.efer;
1337                 if (!(guest_efer & EFER_LMA))
1338                         guest_efer &= ~EFER_LME;
1339                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1340                 return false;
1341         }
1342
1343         return true;
1344 }
1345
1346 static unsigned long segment_base(u16 selector)
1347 {
1348         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1349         struct desc_struct *d;
1350         unsigned long table_base;
1351         unsigned long v;
1352
1353         if (!(selector & ~3))
1354                 return 0;
1355
1356         table_base = gdt->address;
1357
1358         if (selector & 4) {           /* from ldt */
1359                 u16 ldt_selector = kvm_read_ldt();
1360
1361                 if (!(ldt_selector & ~3))
1362                         return 0;
1363
1364                 table_base = segment_base(ldt_selector);
1365         }
1366         d = (struct desc_struct *)(table_base + (selector & ~7));
1367         v = get_desc_base(d);
1368 #ifdef CONFIG_X86_64
1369        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1370                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1371 #endif
1372         return v;
1373 }
1374
1375 static inline unsigned long kvm_read_tr_base(void)
1376 {
1377         u16 tr;
1378         asm("str %0" : "=g"(tr));
1379         return segment_base(tr);
1380 }
1381
1382 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1383 {
1384         struct vcpu_vmx *vmx = to_vmx(vcpu);
1385         int i;
1386
1387         if (vmx->host_state.loaded)
1388                 return;
1389
1390         vmx->host_state.loaded = 1;
1391         /*
1392          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1393          * allow segment selectors with cpl > 0 or ti == 1.
1394          */
1395         vmx->host_state.ldt_sel = kvm_read_ldt();
1396         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1397         savesegment(fs, vmx->host_state.fs_sel);
1398         if (!(vmx->host_state.fs_sel & 7)) {
1399                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1400                 vmx->host_state.fs_reload_needed = 0;
1401         } else {
1402                 vmcs_write16(HOST_FS_SELECTOR, 0);
1403                 vmx->host_state.fs_reload_needed = 1;
1404         }
1405         savesegment(gs, vmx->host_state.gs_sel);
1406         if (!(vmx->host_state.gs_sel & 7))
1407                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1408         else {
1409                 vmcs_write16(HOST_GS_SELECTOR, 0);
1410                 vmx->host_state.gs_ldt_reload_needed = 1;
1411         }
1412
1413 #ifdef CONFIG_X86_64
1414         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1415         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1416 #else
1417         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1418         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1419 #endif
1420
1421 #ifdef CONFIG_X86_64
1422         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1423         if (is_long_mode(&vmx->vcpu))
1424                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1425 #endif
1426         for (i = 0; i < vmx->save_nmsrs; ++i)
1427                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1428                                    vmx->guest_msrs[i].data,
1429                                    vmx->guest_msrs[i].mask);
1430 }
1431
1432 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1433 {
1434         if (!vmx->host_state.loaded)
1435                 return;
1436
1437         ++vmx->vcpu.stat.host_state_reload;
1438         vmx->host_state.loaded = 0;
1439 #ifdef CONFIG_X86_64
1440         if (is_long_mode(&vmx->vcpu))
1441                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1442 #endif
1443         if (vmx->host_state.gs_ldt_reload_needed) {
1444                 kvm_load_ldt(vmx->host_state.ldt_sel);
1445 #ifdef CONFIG_X86_64
1446                 load_gs_index(vmx->host_state.gs_sel);
1447 #else
1448                 loadsegment(gs, vmx->host_state.gs_sel);
1449 #endif
1450         }
1451         if (vmx->host_state.fs_reload_needed)
1452                 loadsegment(fs, vmx->host_state.fs_sel);
1453         reload_tss();
1454 #ifdef CONFIG_X86_64
1455         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1456 #endif
1457         if (__thread_has_fpu(current))
1458                 clts();
1459         load_gdt(&__get_cpu_var(host_gdt));
1460 }
1461
1462 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1463 {
1464         preempt_disable();
1465         __vmx_load_host_state(vmx);
1466         preempt_enable();
1467 }
1468
1469 /*
1470  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1471  * vcpu mutex is already taken.
1472  */
1473 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1474 {
1475         struct vcpu_vmx *vmx = to_vmx(vcpu);
1476         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1477
1478         if (!vmm_exclusive)
1479                 kvm_cpu_vmxon(phys_addr);
1480         else if (vmx->loaded_vmcs->cpu != cpu)
1481                 loaded_vmcs_clear(vmx->loaded_vmcs);
1482
1483         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1484                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1485                 vmcs_load(vmx->loaded_vmcs->vmcs);
1486         }
1487
1488         if (vmx->loaded_vmcs->cpu != cpu) {
1489                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1490                 unsigned long sysenter_esp;
1491
1492                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1493                 local_irq_disable();
1494                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1495                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1496                 local_irq_enable();
1497
1498                 /*
1499                  * Linux uses per-cpu TSS and GDT, so set these when switching
1500                  * processors.
1501                  */
1502                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1503                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1504
1505                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1506                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1507                 vmx->loaded_vmcs->cpu = cpu;
1508         }
1509 }
1510
1511 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1512 {
1513         __vmx_load_host_state(to_vmx(vcpu));
1514         if (!vmm_exclusive) {
1515                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1516                 vcpu->cpu = -1;
1517                 kvm_cpu_vmxoff();
1518         }
1519 }
1520
1521 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1522 {
1523         ulong cr0;
1524
1525         if (vcpu->fpu_active)
1526                 return;
1527         vcpu->fpu_active = 1;
1528         cr0 = vmcs_readl(GUEST_CR0);
1529         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1530         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1531         vmcs_writel(GUEST_CR0, cr0);
1532         update_exception_bitmap(vcpu);
1533         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1534         if (is_guest_mode(vcpu))
1535                 vcpu->arch.cr0_guest_owned_bits &=
1536                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1537         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1538 }
1539
1540 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1541
1542 /*
1543  * Return the cr0 value that a nested guest would read. This is a combination
1544  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1545  * its hypervisor (cr0_read_shadow).
1546  */
1547 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1548 {
1549         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1550                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1551 }
1552 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1553 {
1554         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1555                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1556 }
1557
1558 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1559 {
1560         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1561          * set this *before* calling this function.
1562          */
1563         vmx_decache_cr0_guest_bits(vcpu);
1564         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1565         update_exception_bitmap(vcpu);
1566         vcpu->arch.cr0_guest_owned_bits = 0;
1567         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1568         if (is_guest_mode(vcpu)) {
1569                 /*
1570                  * L1's specified read shadow might not contain the TS bit,
1571                  * so now that we turned on shadowing of this bit, we need to
1572                  * set this bit of the shadow. Like in nested_vmx_run we need
1573                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1574                  * up-to-date here because we just decached cr0.TS (and we'll
1575                  * only update vmcs12->guest_cr0 on nested exit).
1576                  */
1577                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1578                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1579                         (vcpu->arch.cr0 & X86_CR0_TS);
1580                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1581         } else
1582                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1583 }
1584
1585 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1586 {
1587         unsigned long rflags, save_rflags;
1588
1589         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1590                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1591                 rflags = vmcs_readl(GUEST_RFLAGS);
1592                 if (to_vmx(vcpu)->rmode.vm86_active) {
1593                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1594                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1595                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1596                 }
1597                 to_vmx(vcpu)->rflags = rflags;
1598         }
1599         return to_vmx(vcpu)->rflags;
1600 }
1601
1602 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1603 {
1604         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1605         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1606         to_vmx(vcpu)->rflags = rflags;
1607         if (to_vmx(vcpu)->rmode.vm86_active) {
1608                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1609                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1610         }
1611         vmcs_writel(GUEST_RFLAGS, rflags);
1612 }
1613
1614 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1615 {
1616         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1617         int ret = 0;
1618
1619         if (interruptibility & GUEST_INTR_STATE_STI)
1620                 ret |= KVM_X86_SHADOW_INT_STI;
1621         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1622                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1623
1624         return ret & mask;
1625 }
1626
1627 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1628 {
1629         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1630         u32 interruptibility = interruptibility_old;
1631
1632         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1633
1634         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1635                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1636         else if (mask & KVM_X86_SHADOW_INT_STI)
1637                 interruptibility |= GUEST_INTR_STATE_STI;
1638
1639         if ((interruptibility != interruptibility_old))
1640                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1641 }
1642
1643 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1644 {
1645         unsigned long rip;
1646
1647         rip = kvm_rip_read(vcpu);
1648         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1649         kvm_rip_write(vcpu, rip);
1650
1651         /* skipping an emulated instruction also counts */
1652         vmx_set_interrupt_shadow(vcpu, 0);
1653 }
1654
1655 /*
1656  * KVM wants to inject page-faults which it got to the guest. This function
1657  * checks whether in a nested guest, we need to inject them to L1 or L2.
1658  * This function assumes it is called with the exit reason in vmcs02 being
1659  * a #PF exception (this is the only case in which KVM injects a #PF when L2
1660  * is running).
1661  */
1662 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1663 {
1664         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1665
1666         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1667         if (!(vmcs12->exception_bitmap & PF_VECTOR))
1668                 return 0;
1669
1670         nested_vmx_vmexit(vcpu);
1671         return 1;
1672 }
1673
1674 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1675                                 bool has_error_code, u32 error_code,
1676                                 bool reinject)
1677 {
1678         struct vcpu_vmx *vmx = to_vmx(vcpu);
1679         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1680
1681         if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1682                 nested_pf_handled(vcpu))
1683                 return;
1684
1685         if (has_error_code) {
1686                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1687                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1688         }
1689
1690         if (vmx->rmode.vm86_active) {
1691                 int inc_eip = 0;
1692                 if (kvm_exception_is_soft(nr))
1693                         inc_eip = vcpu->arch.event_exit_inst_len;
1694                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1695                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1696                 return;
1697         }
1698
1699         if (kvm_exception_is_soft(nr)) {
1700                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1701                              vmx->vcpu.arch.event_exit_inst_len);
1702                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1703         } else
1704                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1705
1706         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1707 }
1708
1709 static bool vmx_rdtscp_supported(void)
1710 {
1711         return cpu_has_vmx_rdtscp();
1712 }
1713
1714 /*
1715  * Swap MSR entry in host/guest MSR entry array.
1716  */
1717 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1718 {
1719         struct shared_msr_entry tmp;
1720
1721         tmp = vmx->guest_msrs[to];
1722         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1723         vmx->guest_msrs[from] = tmp;
1724 }
1725
1726 /*
1727  * Set up the vmcs to automatically save and restore system
1728  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1729  * mode, as fiddling with msrs is very expensive.
1730  */
1731 static void setup_msrs(struct vcpu_vmx *vmx)
1732 {
1733         int save_nmsrs, index;
1734         unsigned long *msr_bitmap;
1735
1736         save_nmsrs = 0;
1737 #ifdef CONFIG_X86_64
1738         if (is_long_mode(&vmx->vcpu)) {
1739                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1740                 if (index >= 0)
1741                         move_msr_up(vmx, index, save_nmsrs++);
1742                 index = __find_msr_index(vmx, MSR_LSTAR);
1743                 if (index >= 0)
1744                         move_msr_up(vmx, index, save_nmsrs++);
1745                 index = __find_msr_index(vmx, MSR_CSTAR);
1746                 if (index >= 0)
1747                         move_msr_up(vmx, index, save_nmsrs++);
1748                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1749                 if (index >= 0 && vmx->rdtscp_enabled)
1750                         move_msr_up(vmx, index, save_nmsrs++);
1751                 /*
1752                  * MSR_STAR is only needed on long mode guests, and only
1753                  * if efer.sce is enabled.
1754                  */
1755                 index = __find_msr_index(vmx, MSR_STAR);
1756                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1757                         move_msr_up(vmx, index, save_nmsrs++);
1758         }
1759 #endif
1760         index = __find_msr_index(vmx, MSR_EFER);
1761         if (index >= 0 && update_transition_efer(vmx, index))
1762                 move_msr_up(vmx, index, save_nmsrs++);
1763
1764         vmx->save_nmsrs = save_nmsrs;
1765
1766         if (cpu_has_vmx_msr_bitmap()) {
1767                 if (is_long_mode(&vmx->vcpu))
1768                         msr_bitmap = vmx_msr_bitmap_longmode;
1769                 else
1770                         msr_bitmap = vmx_msr_bitmap_legacy;
1771
1772                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1773         }
1774 }
1775
1776 /*
1777  * reads and returns guest's timestamp counter "register"
1778  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1779  */
1780 static u64 guest_read_tsc(void)
1781 {
1782         u64 host_tsc, tsc_offset;
1783
1784         rdtscll(host_tsc);
1785         tsc_offset = vmcs_read64(TSC_OFFSET);
1786         return host_tsc + tsc_offset;
1787 }
1788
1789 /*
1790  * Like guest_read_tsc, but always returns L1's notion of the timestamp
1791  * counter, even if a nested guest (L2) is currently running.
1792  */
1793 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu)
1794 {
1795         u64 host_tsc, tsc_offset;
1796
1797         rdtscll(host_tsc);
1798         tsc_offset = is_guest_mode(vcpu) ?
1799                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1800                 vmcs_read64(TSC_OFFSET);
1801         return host_tsc + tsc_offset;
1802 }
1803
1804 /*
1805  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
1806  * software catchup for faster rates on slower CPUs.
1807  */
1808 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1809 {
1810         if (!scale)
1811                 return;
1812
1813         if (user_tsc_khz > tsc_khz) {
1814                 vcpu->arch.tsc_catchup = 1;
1815                 vcpu->arch.tsc_always_catchup = 1;
1816         } else
1817                 WARN(1, "user requested TSC rate below hardware speed\n");
1818 }
1819
1820 /*
1821  * writes 'offset' into guest's timestamp counter offset register
1822  */
1823 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1824 {
1825         if (is_guest_mode(vcpu)) {
1826                 /*
1827                  * We're here if L1 chose not to trap WRMSR to TSC. According
1828                  * to the spec, this should set L1's TSC; The offset that L1
1829                  * set for L2 remains unchanged, and still needs to be added
1830                  * to the newly set TSC to get L2's TSC.
1831                  */
1832                 struct vmcs12 *vmcs12;
1833                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1834                 /* recalculate vmcs02.TSC_OFFSET: */
1835                 vmcs12 = get_vmcs12(vcpu);
1836                 vmcs_write64(TSC_OFFSET, offset +
1837                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1838                          vmcs12->tsc_offset : 0));
1839         } else {
1840                 vmcs_write64(TSC_OFFSET, offset);
1841         }
1842 }
1843
1844 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1845 {
1846         u64 offset = vmcs_read64(TSC_OFFSET);
1847         vmcs_write64(TSC_OFFSET, offset + adjustment);
1848         if (is_guest_mode(vcpu)) {
1849                 /* Even when running L2, the adjustment needs to apply to L1 */
1850                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1851         }
1852 }
1853
1854 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1855 {
1856         return target_tsc - native_read_tsc();
1857 }
1858
1859 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1860 {
1861         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1862         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1863 }
1864
1865 /*
1866  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1867  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1868  * all guests if the "nested" module option is off, and can also be disabled
1869  * for a single guest by disabling its VMX cpuid bit.
1870  */
1871 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1872 {
1873         return nested && guest_cpuid_has_vmx(vcpu);
1874 }
1875
1876 /*
1877  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1878  * returned for the various VMX controls MSRs when nested VMX is enabled.
1879  * The same values should also be used to verify that vmcs12 control fields are
1880  * valid during nested entry from L1 to L2.
1881  * Each of these control msrs has a low and high 32-bit half: A low bit is on
1882  * if the corresponding bit in the (32-bit) control field *must* be on, and a
1883  * bit in the high half is on if the corresponding bit in the control field
1884  * may be on. See also vmx_control_verify().
1885  * TODO: allow these variables to be modified (downgraded) by module options
1886  * or other means.
1887  */
1888 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1889 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1890 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1891 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1892 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1893 static __init void nested_vmx_setup_ctls_msrs(void)
1894 {
1895         /*
1896          * Note that as a general rule, the high half of the MSRs (bits in
1897          * the control fields which may be 1) should be initialized by the
1898          * intersection of the underlying hardware's MSR (i.e., features which
1899          * can be supported) and the list of features we want to expose -
1900          * because they are known to be properly supported in our code.
1901          * Also, usually, the low half of the MSRs (bits which must be 1) can
1902          * be set to 0, meaning that L1 may turn off any of these bits. The
1903          * reason is that if one of these bits is necessary, it will appear
1904          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1905          * fields of vmcs01 and vmcs02, will turn these bits off - and
1906          * nested_vmx_exit_handled() will not pass related exits to L1.
1907          * These rules have exceptions below.
1908          */
1909
1910         /* pin-based controls */
1911         /*
1912          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1913          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1914          */
1915         nested_vmx_pinbased_ctls_low = 0x16 ;
1916         nested_vmx_pinbased_ctls_high = 0x16 |
1917                 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1918                 PIN_BASED_VIRTUAL_NMIS;
1919
1920         /* exit controls */
1921         nested_vmx_exit_ctls_low = 0;
1922         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
1923 #ifdef CONFIG_X86_64
1924         nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1925 #else
1926         nested_vmx_exit_ctls_high = 0;
1927 #endif
1928
1929         /* entry controls */
1930         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1931                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1932         nested_vmx_entry_ctls_low = 0;
1933         nested_vmx_entry_ctls_high &=
1934                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1935
1936         /* cpu-based controls */
1937         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1938                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1939         nested_vmx_procbased_ctls_low = 0;
1940         nested_vmx_procbased_ctls_high &=
1941                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1942                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1943                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1944                 CPU_BASED_CR3_STORE_EXITING |
1945 #ifdef CONFIG_X86_64
1946                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1947 #endif
1948                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1949                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1950                 CPU_BASED_RDPMC_EXITING |
1951                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1952         /*
1953          * We can allow some features even when not supported by the
1954          * hardware. For example, L1 can specify an MSR bitmap - and we
1955          * can use it to avoid exits to L1 - even when L0 runs L2
1956          * without MSR bitmaps.
1957          */
1958         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1959
1960         /* secondary cpu-based controls */
1961         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
1962                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
1963         nested_vmx_secondary_ctls_low = 0;
1964         nested_vmx_secondary_ctls_high &=
1965                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1966 }
1967
1968 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
1969 {
1970         /*
1971          * Bits 0 in high must be 0, and bits 1 in low must be 1.
1972          */
1973         return ((control & high) | low) == control;
1974 }
1975
1976 static inline u64 vmx_control_msr(u32 low, u32 high)
1977 {
1978         return low | ((u64)high << 32);
1979 }
1980
1981 /*
1982  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
1983  * also let it use VMX-specific MSRs.
1984  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
1985  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
1986  * like all other MSRs).
1987  */
1988 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1989 {
1990         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
1991                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
1992                 /*
1993                  * According to the spec, processors which do not support VMX
1994                  * should throw a #GP(0) when VMX capability MSRs are read.
1995                  */
1996                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
1997                 return 1;
1998         }
1999
2000         switch (msr_index) {
2001         case MSR_IA32_FEATURE_CONTROL:
2002                 *pdata = 0;
2003                 break;
2004         case MSR_IA32_VMX_BASIC:
2005                 /*
2006                  * This MSR reports some information about VMX support. We
2007                  * should return information about the VMX we emulate for the
2008                  * guest, and the VMCS structure we give it - not about the
2009                  * VMX support of the underlying hardware.
2010                  */
2011                 *pdata = VMCS12_REVISION |
2012                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2013                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2014                 break;
2015         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2016         case MSR_IA32_VMX_PINBASED_CTLS:
2017                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2018                                         nested_vmx_pinbased_ctls_high);
2019                 break;
2020         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2021         case MSR_IA32_VMX_PROCBASED_CTLS:
2022                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2023                                         nested_vmx_procbased_ctls_high);
2024                 break;
2025         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2026         case MSR_IA32_VMX_EXIT_CTLS:
2027                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2028                                         nested_vmx_exit_ctls_high);
2029                 break;
2030         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2031         case MSR_IA32_VMX_ENTRY_CTLS:
2032                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2033                                         nested_vmx_entry_ctls_high);
2034                 break;
2035         case MSR_IA32_VMX_MISC:
2036                 *pdata = 0;
2037                 break;
2038         /*
2039          * These MSRs specify bits which the guest must keep fixed (on or off)
2040          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2041          * We picked the standard core2 setting.
2042          */
2043 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2044 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2045         case MSR_IA32_VMX_CR0_FIXED0:
2046                 *pdata = VMXON_CR0_ALWAYSON;
2047                 break;
2048         case MSR_IA32_VMX_CR0_FIXED1:
2049                 *pdata = -1ULL;
2050                 break;
2051         case MSR_IA32_VMX_CR4_FIXED0:
2052                 *pdata = VMXON_CR4_ALWAYSON;
2053                 break;
2054         case MSR_IA32_VMX_CR4_FIXED1:
2055                 *pdata = -1ULL;
2056                 break;
2057         case MSR_IA32_VMX_VMCS_ENUM:
2058                 *pdata = 0x1f;
2059                 break;
2060         case MSR_IA32_VMX_PROCBASED_CTLS2:
2061                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2062                                         nested_vmx_secondary_ctls_high);
2063                 break;
2064         case MSR_IA32_VMX_EPT_VPID_CAP:
2065                 /* Currently, no nested ept or nested vpid */
2066                 *pdata = 0;
2067                 break;
2068         default:
2069                 return 0;
2070         }
2071
2072         return 1;
2073 }
2074
2075 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2076 {
2077         if (!nested_vmx_allowed(vcpu))
2078                 return 0;
2079
2080         if (msr_index == MSR_IA32_FEATURE_CONTROL)
2081                 /* TODO: the right thing. */
2082                 return 1;
2083         /*
2084          * No need to treat VMX capability MSRs specially: If we don't handle
2085          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2086          */
2087         return 0;
2088 }
2089
2090 /*
2091  * Reads an msr value (of 'msr_index') into 'pdata'.
2092  * Returns 0 on success, non-0 otherwise.
2093  * Assumes vcpu_load() was already called.
2094  */
2095 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2096 {
2097         u64 data;
2098         struct shared_msr_entry *msr;
2099
2100         if (!pdata) {
2101                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2102                 return -EINVAL;
2103         }
2104
2105         switch (msr_index) {
2106 #ifdef CONFIG_X86_64
2107         case MSR_FS_BASE:
2108                 data = vmcs_readl(GUEST_FS_BASE);
2109                 break;
2110         case MSR_GS_BASE:
2111                 data = vmcs_readl(GUEST_GS_BASE);
2112                 break;
2113         case MSR_KERNEL_GS_BASE:
2114                 vmx_load_host_state(to_vmx(vcpu));
2115                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2116                 break;
2117 #endif
2118         case MSR_EFER:
2119                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2120         case MSR_IA32_TSC:
2121                 data = guest_read_tsc();
2122                 break;
2123         case MSR_IA32_SYSENTER_CS:
2124                 data = vmcs_read32(GUEST_SYSENTER_CS);
2125                 break;
2126         case MSR_IA32_SYSENTER_EIP:
2127                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2128                 break;
2129         case MSR_IA32_SYSENTER_ESP:
2130                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2131                 break;
2132         case MSR_TSC_AUX:
2133                 if (!to_vmx(vcpu)->rdtscp_enabled)
2134                         return 1;
2135                 /* Otherwise falls through */
2136         default:
2137                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2138                         return 0;
2139                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2140                 if (msr) {
2141                         data = msr->data;
2142                         break;
2143                 }
2144                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2145         }
2146
2147         *pdata = data;
2148         return 0;
2149 }
2150
2151 /*
2152  * Writes msr value into into the appropriate "register".
2153  * Returns 0 on success, non-0 otherwise.
2154  * Assumes vcpu_load() was already called.
2155  */
2156 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2157 {
2158         struct vcpu_vmx *vmx = to_vmx(vcpu);
2159         struct shared_msr_entry *msr;
2160         int ret = 0;
2161
2162         switch (msr_index) {
2163         case MSR_EFER:
2164                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2165                 break;
2166 #ifdef CONFIG_X86_64
2167         case MSR_FS_BASE:
2168                 vmx_segment_cache_clear(vmx);
2169                 vmcs_writel(GUEST_FS_BASE, data);
2170                 break;
2171         case MSR_GS_BASE:
2172                 vmx_segment_cache_clear(vmx);
2173                 vmcs_writel(GUEST_GS_BASE, data);
2174                 break;
2175         case MSR_KERNEL_GS_BASE:
2176                 vmx_load_host_state(vmx);
2177                 vmx->msr_guest_kernel_gs_base = data;
2178                 break;
2179 #endif
2180         case MSR_IA32_SYSENTER_CS:
2181                 vmcs_write32(GUEST_SYSENTER_CS, data);
2182                 break;
2183         case MSR_IA32_SYSENTER_EIP:
2184                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2185                 break;
2186         case MSR_IA32_SYSENTER_ESP:
2187                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2188                 break;
2189         case MSR_IA32_TSC:
2190                 kvm_write_tsc(vcpu, data);
2191                 break;
2192         case MSR_IA32_CR_PAT:
2193                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2194                         vmcs_write64(GUEST_IA32_PAT, data);
2195                         vcpu->arch.pat = data;
2196                         break;
2197                 }
2198                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2199                 break;
2200         case MSR_TSC_AUX:
2201                 if (!vmx->rdtscp_enabled)
2202                         return 1;
2203                 /* Check reserved bit, higher 32 bits should be zero */
2204                 if ((data >> 32) != 0)
2205                         return 1;
2206                 /* Otherwise falls through */
2207         default:
2208                 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2209                         break;
2210                 msr = find_msr_entry(vmx, msr_index);
2211                 if (msr) {
2212                         msr->data = data;
2213                         break;
2214                 }
2215                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2216         }
2217
2218         return ret;
2219 }
2220
2221 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2222 {
2223         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2224         switch (reg) {
2225         case VCPU_REGS_RSP:
2226                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2227                 break;
2228         case VCPU_REGS_RIP:
2229                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2230                 break;
2231         case VCPU_EXREG_PDPTR:
2232                 if (enable_ept)
2233                         ept_save_pdptrs(vcpu);
2234                 break;
2235         default:
2236                 break;
2237         }
2238 }
2239
2240 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
2241 {
2242         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2243                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2244         else
2245                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2246
2247         update_exception_bitmap(vcpu);
2248 }
2249
2250 static __init int cpu_has_kvm_support(void)
2251 {
2252         return cpu_has_vmx();
2253 }
2254
2255 static __init int vmx_disabled_by_bios(void)
2256 {
2257         u64 msr;
2258
2259         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2260         if (msr & FEATURE_CONTROL_LOCKED) {
2261                 /* launched w/ TXT and VMX disabled */
2262                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2263                         && tboot_enabled())
2264                         return 1;
2265                 /* launched w/o TXT and VMX only enabled w/ TXT */
2266                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2267                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2268                         && !tboot_enabled()) {
2269                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2270                                 "activate TXT before enabling KVM\n");
2271                         return 1;
2272                 }
2273                 /* launched w/o TXT and VMX disabled */
2274                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2275                         && !tboot_enabled())
2276                         return 1;
2277         }
2278
2279         return 0;
2280 }
2281
2282 static void kvm_cpu_vmxon(u64 addr)
2283 {
2284         asm volatile (ASM_VMX_VMXON_RAX
2285                         : : "a"(&addr), "m"(addr)
2286                         : "memory", "cc");
2287 }
2288
2289 static int hardware_enable(void *garbage)
2290 {
2291         int cpu = raw_smp_processor_id();
2292         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2293         u64 old, test_bits;
2294
2295         if (read_cr4() & X86_CR4_VMXE)
2296                 return -EBUSY;
2297
2298         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2299         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2300
2301         test_bits = FEATURE_CONTROL_LOCKED;
2302         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2303         if (tboot_enabled())
2304                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2305
2306         if ((old & test_bits) != test_bits) {
2307                 /* enable and lock */
2308                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2309         }
2310         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2311
2312         if (vmm_exclusive) {
2313                 kvm_cpu_vmxon(phys_addr);
2314                 ept_sync_global();
2315         }
2316
2317         store_gdt(&__get_cpu_var(host_gdt));
2318
2319         return 0;
2320 }
2321
2322 static void vmclear_local_loaded_vmcss(void)
2323 {
2324         int cpu = raw_smp_processor_id();
2325         struct loaded_vmcs *v, *n;
2326
2327         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2328                                  loaded_vmcss_on_cpu_link)
2329                 __loaded_vmcs_clear(v);
2330 }
2331
2332
2333 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2334  * tricks.
2335  */
2336 static void kvm_cpu_vmxoff(void)
2337 {
2338         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2339 }
2340
2341 static void hardware_disable(void *garbage)
2342 {
2343         if (vmm_exclusive) {
2344                 vmclear_local_loaded_vmcss();
2345                 kvm_cpu_vmxoff();
2346         }
2347         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2348 }
2349
2350 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2351                                       u32 msr, u32 *result)
2352 {
2353         u32 vmx_msr_low, vmx_msr_high;
2354         u32 ctl = ctl_min | ctl_opt;
2355
2356         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2357
2358         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2359         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2360
2361         /* Ensure minimum (required) set of control bits are supported. */
2362         if (ctl_min & ~ctl)
2363                 return -EIO;
2364
2365         *result = ctl;
2366         return 0;
2367 }
2368
2369 static __init bool allow_1_setting(u32 msr, u32 ctl)
2370 {
2371         u32 vmx_msr_low, vmx_msr_high;
2372
2373         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2374         return vmx_msr_high & ctl;
2375 }
2376
2377 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2378 {
2379         u32 vmx_msr_low, vmx_msr_high;
2380         u32 min, opt, min2, opt2;
2381         u32 _pin_based_exec_control = 0;
2382         u32 _cpu_based_exec_control = 0;
2383         u32 _cpu_based_2nd_exec_control = 0;
2384         u32 _vmexit_control = 0;
2385         u32 _vmentry_control = 0;
2386
2387         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2388         opt = PIN_BASED_VIRTUAL_NMIS;
2389         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2390                                 &_pin_based_exec_control) < 0)
2391                 return -EIO;
2392
2393         min = CPU_BASED_HLT_EXITING |
2394 #ifdef CONFIG_X86_64
2395               CPU_BASED_CR8_LOAD_EXITING |
2396               CPU_BASED_CR8_STORE_EXITING |
2397 #endif
2398               CPU_BASED_CR3_LOAD_EXITING |
2399               CPU_BASED_CR3_STORE_EXITING |
2400               CPU_BASED_USE_IO_BITMAPS |
2401               CPU_BASED_MOV_DR_EXITING |
2402               CPU_BASED_USE_TSC_OFFSETING |
2403               CPU_BASED_MWAIT_EXITING |
2404               CPU_BASED_MONITOR_EXITING |
2405               CPU_BASED_INVLPG_EXITING |
2406               CPU_BASED_RDPMC_EXITING;
2407
2408         opt = CPU_BASED_TPR_SHADOW |
2409               CPU_BASED_USE_MSR_BITMAPS |
2410               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2411         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2412                                 &_cpu_based_exec_control) < 0)
2413                 return -EIO;
2414 #ifdef CONFIG_X86_64
2415         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2416                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2417                                            ~CPU_BASED_CR8_STORE_EXITING;
2418 #endif
2419         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2420                 min2 = 0;
2421                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2422                         SECONDARY_EXEC_WBINVD_EXITING |
2423                         SECONDARY_EXEC_ENABLE_VPID |
2424                         SECONDARY_EXEC_ENABLE_EPT |
2425                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2426                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2427                         SECONDARY_EXEC_RDTSCP;
2428                 if (adjust_vmx_controls(min2, opt2,
2429                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2430                                         &_cpu_based_2nd_exec_control) < 0)
2431                         return -EIO;
2432         }
2433 #ifndef CONFIG_X86_64
2434         if (!(_cpu_based_2nd_exec_control &
2435                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2436                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2437 #endif
2438         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2439                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2440                    enabled */
2441                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2442                                              CPU_BASED_CR3_STORE_EXITING |
2443                                              CPU_BASED_INVLPG_EXITING);
2444                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2445                       vmx_capability.ept, vmx_capability.vpid);
2446         }
2447
2448         min = 0;
2449 #ifdef CONFIG_X86_64
2450         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2451 #endif
2452         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2453         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2454                                 &_vmexit_control) < 0)
2455                 return -EIO;
2456
2457         min = 0;
2458         opt = VM_ENTRY_LOAD_IA32_PAT;
2459         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2460                                 &_vmentry_control) < 0)
2461                 return -EIO;
2462
2463         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2464
2465         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2466         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2467                 return -EIO;
2468
2469 #ifdef CONFIG_X86_64
2470         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2471         if (vmx_msr_high & (1u<<16))
2472                 return -EIO;
2473 #endif
2474
2475         /* Require Write-Back (WB) memory type for VMCS accesses. */
2476         if (((vmx_msr_high >> 18) & 15) != 6)
2477                 return -EIO;
2478
2479         vmcs_conf->size = vmx_msr_high & 0x1fff;
2480         vmcs_conf->order = get_order(vmcs_config.size);
2481         vmcs_conf->revision_id = vmx_msr_low;
2482
2483         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2484         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2485         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2486         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2487         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2488
2489         cpu_has_load_ia32_efer =
2490                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2491                                 VM_ENTRY_LOAD_IA32_EFER)
2492                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2493                                    VM_EXIT_LOAD_IA32_EFER);
2494
2495         cpu_has_load_perf_global_ctrl =
2496                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2497                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2498                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2499                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2500
2501         /*
2502          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2503          * but due to arrata below it can't be used. Workaround is to use
2504          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2505          *
2506          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2507          *
2508          * AAK155             (model 26)
2509          * AAP115             (model 30)
2510          * AAT100             (model 37)
2511          * BC86,AAY89,BD102   (model 44)
2512          * BA97               (model 46)
2513          *
2514          */
2515         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2516                 switch (boot_cpu_data.x86_model) {
2517                 case 26:
2518                 case 30:
2519                 case 37:
2520                 case 44:
2521                 case 46:
2522                         cpu_has_load_perf_global_ctrl = false;
2523                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2524                                         "does not work properly. Using workaround\n");
2525                         break;
2526                 default:
2527                         break;
2528                 }
2529         }
2530
2531         return 0;
2532 }
2533
2534 static struct vmcs *alloc_vmcs_cpu(int cpu)
2535 {
2536         int node = cpu_to_node(cpu);
2537         struct page *pages;
2538         struct vmcs *vmcs;
2539
2540         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2541         if (!pages)
2542                 return NULL;
2543         vmcs = page_address(pages);
2544         memset(vmcs, 0, vmcs_config.size);
2545         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2546         return vmcs;
2547 }
2548
2549 static struct vmcs *alloc_vmcs(void)
2550 {
2551         return alloc_vmcs_cpu(raw_smp_processor_id());
2552 }
2553
2554 static void free_vmcs(struct vmcs *vmcs)
2555 {
2556         free_pages((unsigned long)vmcs, vmcs_config.order);
2557 }
2558
2559 /*
2560  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2561  */
2562 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2563 {
2564         if (!loaded_vmcs->vmcs)
2565                 return;
2566         loaded_vmcs_clear(loaded_vmcs);
2567         free_vmcs(loaded_vmcs->vmcs);
2568         loaded_vmcs->vmcs = NULL;
2569 }
2570
2571 static void free_kvm_area(void)
2572 {
2573         int cpu;
2574
2575         for_each_possible_cpu(cpu) {
2576                 free_vmcs(per_cpu(vmxarea, cpu));
2577                 per_cpu(vmxarea, cpu) = NULL;
2578         }
2579 }
2580
2581 static __init int alloc_kvm_area(void)
2582 {
2583         int cpu;
2584
2585         for_each_possible_cpu(cpu) {
2586                 struct vmcs *vmcs;
2587
2588                 vmcs = alloc_vmcs_cpu(cpu);
2589                 if (!vmcs) {
2590                         free_kvm_area();
2591                         return -ENOMEM;
2592                 }
2593
2594                 per_cpu(vmxarea, cpu) = vmcs;
2595         }
2596         return 0;
2597 }
2598
2599 static __init int hardware_setup(void)
2600 {
2601         if (setup_vmcs_config(&vmcs_config) < 0)
2602                 return -EIO;
2603
2604         if (boot_cpu_has(X86_FEATURE_NX))
2605                 kvm_enable_efer_bits(EFER_NX);
2606
2607         if (!cpu_has_vmx_vpid())
2608                 enable_vpid = 0;
2609
2610         if (!cpu_has_vmx_ept() ||
2611             !cpu_has_vmx_ept_4levels()) {
2612                 enable_ept = 0;
2613                 enable_unrestricted_guest = 0;
2614         }
2615
2616         if (!cpu_has_vmx_unrestricted_guest())
2617                 enable_unrestricted_guest = 0;
2618
2619         if (!cpu_has_vmx_flexpriority())
2620                 flexpriority_enabled = 0;
2621
2622         if (!cpu_has_vmx_tpr_shadow())
2623                 kvm_x86_ops->update_cr8_intercept = NULL;
2624
2625         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2626                 kvm_disable_largepages();
2627
2628         if (!cpu_has_vmx_ple())
2629                 ple_gap = 0;
2630
2631         if (nested)
2632                 nested_vmx_setup_ctls_msrs();
2633
2634         return alloc_kvm_area();
2635 }
2636
2637 static __exit void hardware_unsetup(void)
2638 {
2639         free_kvm_area();
2640 }
2641
2642 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2643 {
2644         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2645
2646         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
2647                 vmcs_write16(sf->selector, save->selector);
2648                 vmcs_writel(sf->base, save->base);
2649                 vmcs_write32(sf->limit, save->limit);
2650                 vmcs_write32(sf->ar_bytes, save->ar);
2651         } else {
2652                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2653                         << AR_DPL_SHIFT;
2654                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2655         }
2656 }
2657
2658 static void enter_pmode(struct kvm_vcpu *vcpu)
2659 {
2660         unsigned long flags;
2661         struct vcpu_vmx *vmx = to_vmx(vcpu);
2662
2663         vmx->emulation_required = 1;
2664         vmx->rmode.vm86_active = 0;
2665
2666         vmx_segment_cache_clear(vmx);
2667
2668         vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
2669         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2670         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2671         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
2672
2673         flags = vmcs_readl(GUEST_RFLAGS);
2674         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2675         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2676         vmcs_writel(GUEST_RFLAGS, flags);
2677
2678         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2679                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2680
2681         update_exception_bitmap(vcpu);
2682
2683         if (emulate_invalid_guest_state)
2684                 return;
2685
2686         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2687         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2688         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2689         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
2690
2691         vmx_segment_cache_clear(vmx);
2692
2693         vmcs_write16(GUEST_SS_SELECTOR, 0);
2694         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2695
2696         vmcs_write16(GUEST_CS_SELECTOR,
2697                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2698         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2699 }
2700
2701 static gva_t rmode_tss_base(struct kvm *kvm)
2702 {
2703         if (!kvm->arch.tss_addr) {
2704                 struct kvm_memslots *slots;
2705                 struct kvm_memory_slot *slot;
2706                 gfn_t base_gfn;
2707
2708                 slots = kvm_memslots(kvm);
2709                 slot = id_to_memslot(slots, 0);
2710                 base_gfn = slot->base_gfn + slot->npages - 3;
2711
2712                 return base_gfn << PAGE_SHIFT;
2713         }
2714         return kvm->arch.tss_addr;
2715 }
2716
2717 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2718 {
2719         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2720
2721         save->selector = vmcs_read16(sf->selector);
2722         save->base = vmcs_readl(sf->base);
2723         save->limit = vmcs_read32(sf->limit);
2724         save->ar = vmcs_read32(sf->ar_bytes);
2725         vmcs_write16(sf->selector, save->base >> 4);
2726         vmcs_write32(sf->base, save->base & 0xffff0);
2727         vmcs_write32(sf->limit, 0xffff);
2728         vmcs_write32(sf->ar_bytes, 0xf3);
2729         if (save->base & 0xf)
2730                 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2731                             " aligned when entering protected mode (seg=%d)",
2732                             seg);
2733 }
2734
2735 static void enter_rmode(struct kvm_vcpu *vcpu)
2736 {
2737         unsigned long flags;
2738         struct vcpu_vmx *vmx = to_vmx(vcpu);
2739
2740         if (enable_unrestricted_guest)
2741                 return;
2742
2743         vmx->emulation_required = 1;
2744         vmx->rmode.vm86_active = 1;
2745
2746         /*
2747          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2748          * vcpu. Call it here with phys address pointing 16M below 4G.
2749          */
2750         if (!vcpu->kvm->arch.tss_addr) {
2751                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2752                              "called before entering vcpu\n");
2753                 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2754                 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2755                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2756         }
2757
2758         vmx_segment_cache_clear(vmx);
2759
2760         vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
2761         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
2762         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2763
2764         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
2765         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2766
2767         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
2768         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2769
2770         flags = vmcs_readl(GUEST_RFLAGS);
2771         vmx->rmode.save_rflags = flags;
2772
2773         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2774
2775         vmcs_writel(GUEST_RFLAGS, flags);
2776         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2777         update_exception_bitmap(vcpu);
2778
2779         if (emulate_invalid_guest_state)
2780                 goto continue_rmode;
2781
2782         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
2783         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
2784         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
2785
2786         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
2787         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
2788         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
2789                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
2790         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
2791
2792         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
2793         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
2794         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
2795         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
2796
2797 continue_rmode:
2798         kvm_mmu_reset_context(vcpu);
2799 }
2800
2801 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2802 {
2803         struct vcpu_vmx *vmx = to_vmx(vcpu);
2804         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2805
2806         if (!msr)
2807                 return;
2808
2809         /*
2810          * Force kernel_gs_base reloading before EFER changes, as control
2811          * of this msr depends on is_long_mode().
2812          */
2813         vmx_load_host_state(to_vmx(vcpu));
2814         vcpu->arch.efer = efer;
2815         if (efer & EFER_LMA) {
2816                 vmcs_write32(VM_ENTRY_CONTROLS,
2817                              vmcs_read32(VM_ENTRY_CONTROLS) |
2818                              VM_ENTRY_IA32E_MODE);
2819                 msr->data = efer;
2820         } else {
2821                 vmcs_write32(VM_ENTRY_CONTROLS,
2822                              vmcs_read32(VM_ENTRY_CONTROLS) &
2823                              ~VM_ENTRY_IA32E_MODE);
2824
2825                 msr->data = efer & ~EFER_LME;
2826         }
2827         setup_msrs(vmx);
2828 }
2829
2830 #ifdef CONFIG_X86_64
2831
2832 static void enter_lmode(struct kvm_vcpu *vcpu)
2833 {
2834         u32 guest_tr_ar;
2835
2836         vmx_segment_cache_clear(to_vmx(vcpu));
2837
2838         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2839         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2840                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2841                                      __func__);
2842                 vmcs_write32(GUEST_TR_AR_BYTES,
2843                              (guest_tr_ar & ~AR_TYPE_MASK)
2844                              | AR_TYPE_BUSY_64_TSS);
2845         }
2846         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2847 }
2848
2849 static void exit_lmode(struct kvm_vcpu *vcpu)
2850 {
2851         vmcs_write32(VM_ENTRY_CONTROLS,
2852                      vmcs_read32(VM_ENTRY_CONTROLS)
2853                      & ~VM_ENTRY_IA32E_MODE);
2854         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2855 }
2856
2857 #endif
2858
2859 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2860 {
2861         vpid_sync_context(to_vmx(vcpu));
2862         if (enable_ept) {
2863                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2864                         return;
2865                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2866         }
2867 }
2868
2869 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2870 {
2871         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2872
2873         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2874         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2875 }
2876
2877 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2878 {
2879         if (enable_ept && is_paging(vcpu))
2880                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2881         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2882 }
2883
2884 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2885 {
2886         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2887
2888         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2889         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2890 }
2891
2892 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2893 {
2894         if (!test_bit(VCPU_EXREG_PDPTR,
2895                       (unsigned long *)&vcpu->arch.regs_dirty))
2896                 return;
2897
2898         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2899                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2900                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2901                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2902                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
2903         }
2904 }
2905
2906 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2907 {
2908         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2909                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2910                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2911                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2912                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2913         }
2914
2915         __set_bit(VCPU_EXREG_PDPTR,
2916                   (unsigned long *)&vcpu->arch.regs_avail);
2917         __set_bit(VCPU_EXREG_PDPTR,
2918                   (unsigned long *)&vcpu->arch.regs_dirty);
2919 }
2920
2921 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2922
2923 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2924                                         unsigned long cr0,
2925                                         struct kvm_vcpu *vcpu)
2926 {
2927         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2928                 vmx_decache_cr3(vcpu);
2929         if (!(cr0 & X86_CR0_PG)) {
2930                 /* From paging/starting to nonpaging */
2931                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2932                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
2933                              (CPU_BASED_CR3_LOAD_EXITING |
2934                               CPU_BASED_CR3_STORE_EXITING));
2935                 vcpu->arch.cr0 = cr0;
2936                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2937         } else if (!is_paging(vcpu)) {
2938                 /* From nonpaging to paging */
2939                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2940                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
2941                              ~(CPU_BASED_CR3_LOAD_EXITING |
2942                                CPU_BASED_CR3_STORE_EXITING));
2943                 vcpu->arch.cr0 = cr0;
2944                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2945         }
2946
2947         if (!(cr0 & X86_CR0_WP))
2948                 *hw_cr0 &= ~X86_CR0_WP;
2949 }
2950
2951 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2952 {
2953         struct vcpu_vmx *vmx = to_vmx(vcpu);
2954         unsigned long hw_cr0;
2955
2956         if (enable_unrestricted_guest)
2957                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2958                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2959         else
2960                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
2961
2962         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2963                 enter_pmode(vcpu);
2964
2965         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2966                 enter_rmode(vcpu);
2967
2968 #ifdef CONFIG_X86_64
2969         if (vcpu->arch.efer & EFER_LME) {
2970                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2971                         enter_lmode(vcpu);
2972                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2973                         exit_lmode(vcpu);
2974         }
2975 #endif
2976
2977         if (enable_ept)
2978                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2979
2980         if (!vcpu->fpu_active)
2981                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
2982
2983         vmcs_writel(CR0_READ_SHADOW, cr0);
2984         vmcs_writel(GUEST_CR0, hw_cr0);
2985         vcpu->arch.cr0 = cr0;
2986         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2987 }
2988
2989 static u64 construct_eptp(unsigned long root_hpa)
2990 {
2991         u64 eptp;
2992
2993         /* TODO write the value reading from MSR */
2994         eptp = VMX_EPT_DEFAULT_MT |
2995                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
2996         eptp |= (root_hpa & PAGE_MASK);
2997
2998         return eptp;
2999 }
3000
3001 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3002 {
3003         unsigned long guest_cr3;
3004         u64 eptp;
3005
3006         guest_cr3 = cr3;
3007         if (enable_ept) {
3008                 eptp = construct_eptp(cr3);
3009                 vmcs_write64(EPT_POINTER, eptp);
3010                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3011                         vcpu->kvm->arch.ept_identity_map_addr;
3012                 ept_load_pdptrs(vcpu);
3013         }
3014
3015         vmx_flush_tlb(vcpu);
3016         vmcs_writel(GUEST_CR3, guest_cr3);
3017 }
3018
3019 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3020 {
3021         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3022                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3023
3024         if (cr4 & X86_CR4_VMXE) {
3025                 /*
3026                  * To use VMXON (and later other VMX instructions), a guest
3027                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3028                  * So basically the check on whether to allow nested VMX
3029                  * is here.
3030                  */
3031                 if (!nested_vmx_allowed(vcpu))
3032                         return 1;
3033         } else if (to_vmx(vcpu)->nested.vmxon)
3034                 return 1;
3035
3036         vcpu->arch.cr4 = cr4;
3037         if (enable_ept) {
3038                 if (!is_paging(vcpu)) {
3039                         hw_cr4 &= ~X86_CR4_PAE;
3040                         hw_cr4 |= X86_CR4_PSE;
3041                 } else if (!(cr4 & X86_CR4_PAE)) {
3042                         hw_cr4 &= ~X86_CR4_PAE;
3043                 }
3044         }
3045
3046         vmcs_writel(CR4_READ_SHADOW, cr4);
3047         vmcs_writel(GUEST_CR4, hw_cr4);
3048         return 0;
3049 }
3050
3051 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3052                             struct kvm_segment *var, int seg)
3053 {
3054         struct vcpu_vmx *vmx = to_vmx(vcpu);
3055         struct kvm_save_segment *save;
3056         u32 ar;
3057
3058         if (vmx->rmode.vm86_active
3059             && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
3060                 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
3061                 || seg == VCPU_SREG_GS)
3062             && !emulate_invalid_guest_state) {
3063                 switch (seg) {
3064                 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
3065                 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
3066                 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
3067                 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
3068                 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
3069                 default: BUG();
3070                 }
3071                 var->selector = save->selector;
3072                 var->base = save->base;
3073                 var->limit = save->limit;
3074                 ar = save->ar;
3075                 if (seg == VCPU_SREG_TR
3076                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3077                         goto use_saved_rmode_seg;
3078         }
3079         var->base = vmx_read_guest_seg_base(vmx, seg);
3080         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3081         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3082         ar = vmx_read_guest_seg_ar(vmx, seg);
3083 use_saved_rmode_seg:
3084         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
3085                 ar = 0;
3086         var->type = ar & 15;
3087         var->s = (ar >> 4) & 1;
3088         var->dpl = (ar >> 5) & 3;
3089         var->present = (ar >> 7) & 1;
3090         var->avl = (ar >> 12) & 1;
3091         var->l = (ar >> 13) & 1;
3092         var->db = (ar >> 14) & 1;
3093         var->g = (ar >> 15) & 1;
3094         var->unusable = (ar >> 16) & 1;
3095 }
3096
3097 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3098 {
3099         struct kvm_segment s;
3100
3101         if (to_vmx(vcpu)->rmode.vm86_active) {
3102                 vmx_get_segment(vcpu, &s, seg);
3103                 return s.base;
3104         }
3105         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3106 }
3107
3108 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
3109 {
3110         if (!is_protmode(vcpu))
3111                 return 0;
3112
3113         if (!is_long_mode(vcpu)
3114             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3115                 return 3;
3116
3117         return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
3118 }
3119
3120 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3121 {
3122         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3123                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3124                 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
3125         }
3126         return to_vmx(vcpu)->cpl;
3127 }
3128
3129
3130 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3131 {
3132         u32 ar;
3133
3134         if (var->unusable)
3135                 ar = 1 << 16;
3136         else {
3137                 ar = var->type & 15;
3138                 ar |= (var->s & 1) << 4;
3139                 ar |= (var->dpl & 3) << 5;
3140                 ar |= (var->present & 1) << 7;
3141                 ar |= (var->avl & 1) << 12;
3142                 ar |= (var->l & 1) << 13;
3143                 ar |= (var->db & 1) << 14;
3144                 ar |= (var->g & 1) << 15;
3145         }
3146         if (ar == 0) /* a 0 value means unusable */
3147                 ar = AR_UNUSABLE_MASK;
3148
3149         return ar;
3150 }
3151
3152 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3153                             struct kvm_segment *var, int seg)
3154 {
3155         struct vcpu_vmx *vmx = to_vmx(vcpu);
3156         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3157         u32 ar;
3158
3159         vmx_segment_cache_clear(vmx);
3160
3161         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
3162                 vmcs_write16(sf->selector, var->selector);
3163                 vmx->rmode.tr.selector = var->selector;
3164                 vmx->rmode.tr.base = var->base;
3165                 vmx->rmode.tr.limit = var->limit;
3166                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
3167                 return;
3168         }
3169         vmcs_writel(sf->base, var->base);
3170         vmcs_write32(sf->limit, var->limit);
3171         vmcs_write16(sf->selector, var->selector);
3172         if (vmx->rmode.vm86_active && var->s) {
3173                 /*
3174                  * Hack real-mode segments into vm86 compatibility.
3175                  */
3176                 if (var->base == 0xffff0000 && var->selector == 0xf000)
3177                         vmcs_writel(sf->base, 0xf0000);
3178                 ar = 0xf3;
3179         } else
3180                 ar = vmx_segment_access_rights(var);
3181
3182         /*
3183          *   Fix the "Accessed" bit in AR field of segment registers for older
3184          * qemu binaries.
3185          *   IA32 arch specifies that at the time of processor reset the
3186          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3187          * is setting it to 0 in the usedland code. This causes invalid guest
3188          * state vmexit when "unrestricted guest" mode is turned on.
3189          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3190          * tree. Newer qemu binaries with that qemu fix would not need this
3191          * kvm hack.
3192          */
3193         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3194                 ar |= 0x1; /* Accessed */
3195
3196         vmcs_write32(sf->ar_bytes, ar);
3197         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3198 }
3199
3200 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3201 {
3202         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3203
3204         *db = (ar >> 14) & 1;
3205         *l = (ar >> 13) & 1;
3206 }
3207
3208 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3209 {
3210         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3211         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3212 }
3213
3214 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3215 {
3216         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3217         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3218 }
3219
3220 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3221 {
3222         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3223         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3224 }
3225
3226 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3227 {
3228         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3229         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3230 }
3231
3232 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3233 {
3234         struct kvm_segment var;
3235         u32 ar;
3236
3237         vmx_get_segment(vcpu, &var, seg);
3238         ar = vmx_segment_access_rights(&var);
3239
3240         if (var.base != (var.selector << 4))
3241                 return false;
3242         if (var.limit != 0xffff)
3243                 return false;
3244         if (ar != 0xf3)
3245                 return false;
3246
3247         return true;
3248 }
3249
3250 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3251 {
3252         struct kvm_segment cs;
3253         unsigned int cs_rpl;
3254
3255         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3256         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3257
3258         if (cs.unusable)
3259                 return false;
3260         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3261                 return false;
3262         if (!cs.s)
3263                 return false;
3264         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3265                 if (cs.dpl > cs_rpl)
3266                         return false;
3267         } else {
3268                 if (cs.dpl != cs_rpl)
3269                         return false;
3270         }
3271         if (!cs.present)
3272                 return false;
3273
3274         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3275         return true;
3276 }
3277
3278 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3279 {
3280         struct kvm_segment ss;
3281         unsigned int ss_rpl;
3282
3283         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3284         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3285
3286         if (ss.unusable)
3287                 return true;
3288         if (ss.type != 3 && ss.type != 7)
3289                 return false;
3290         if (!ss.s)
3291                 return false;
3292         if (ss.dpl != ss_rpl) /* DPL != RPL */
3293                 return false;
3294         if (!ss.present)
3295                 return false;
3296
3297         return true;
3298 }
3299
3300 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3301 {
3302         struct kvm_segment var;
3303         unsigned int rpl;
3304
3305         vmx_get_segment(vcpu, &var, seg);
3306         rpl = var.selector & SELECTOR_RPL_MASK;
3307
3308         if (var.unusable)
3309                 return true;
3310         if (!var.s)
3311                 return false;
3312         if (!var.present)
3313                 return false;
3314         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3315                 if (var.dpl < rpl) /* DPL < RPL */
3316                         return false;
3317         }
3318
3319         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3320          * rights flags
3321          */
3322         return true;
3323 }
3324
3325 static bool tr_valid(struct kvm_vcpu *vcpu)
3326 {
3327         struct kvm_segment tr;
3328
3329         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3330
3331         if (tr.unusable)
3332                 return false;
3333         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3334                 return false;
3335         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3336                 return false;
3337         if (!tr.present)
3338                 return false;
3339
3340         return true;
3341 }
3342
3343 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3344 {
3345         struct kvm_segment ldtr;
3346
3347         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3348
3349         if (ldtr.unusable)
3350                 return true;
3351         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3352                 return false;
3353         if (ldtr.type != 2)
3354                 return false;
3355         if (!ldtr.present)
3356                 return false;
3357
3358         return true;
3359 }
3360
3361 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3362 {
3363         struct kvm_segment cs, ss;
3364
3365         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3366         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3367
3368         return ((cs.selector & SELECTOR_RPL_MASK) ==
3369                  (ss.selector & SELECTOR_RPL_MASK));
3370 }
3371
3372 /*
3373  * Check if guest state is valid. Returns true if valid, false if
3374  * not.
3375  * We assume that registers are always usable
3376  */
3377 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3378 {
3379         /* real mode guest state checks */
3380         if (!is_protmode(vcpu)) {
3381                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3382                         return false;
3383                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3384                         return false;
3385                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3386                         return false;
3387                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3388                         return false;
3389                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3390                         return false;
3391                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3392                         return false;
3393         } else {
3394         /* protected mode guest state checks */
3395                 if (!cs_ss_rpl_check(vcpu))
3396                         return false;
3397                 if (!code_segment_valid(vcpu))
3398                         return false;
3399                 if (!stack_segment_valid(vcpu))
3400                         return false;
3401                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3402                         return false;
3403                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3404                         return false;
3405                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3406                         return false;
3407                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3408                         return false;
3409                 if (!tr_valid(vcpu))
3410                         return false;
3411                 if (!ldtr_valid(vcpu))
3412                         return false;
3413         }
3414         /* TODO:
3415          * - Add checks on RIP
3416          * - Add checks on RFLAGS
3417          */
3418
3419         return true;
3420 }
3421
3422 static int init_rmode_tss(struct kvm *kvm)
3423 {
3424         gfn_t fn;
3425         u16 data = 0;
3426         int r, idx, ret = 0;
3427
3428         idx = srcu_read_lock(&kvm->srcu);
3429         fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3430         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3431         if (r < 0)
3432                 goto out;
3433         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3434         r = kvm_write_guest_page(kvm, fn++, &data,
3435                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3436         if (r < 0)
3437                 goto out;
3438         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3439         if (r < 0)
3440                 goto out;
3441         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3442         if (r < 0)
3443                 goto out;
3444         data = ~0;
3445         r = kvm_write_guest_page(kvm, fn, &data,
3446                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3447                                  sizeof(u8));
3448         if (r < 0)
3449                 goto out;
3450
3451         ret = 1;
3452 out:
3453         srcu_read_unlock(&kvm->srcu, idx);
3454         return ret;
3455 }
3456
3457 static int init_rmode_identity_map(struct kvm *kvm)
3458 {
3459         int i, idx, r, ret;
3460         pfn_t identity_map_pfn;
3461         u32 tmp;
3462
3463         if (!enable_ept)
3464                 return 1;
3465         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3466                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3467                         "haven't been allocated!\n");
3468                 return 0;
3469         }
3470         if (likely(kvm->arch.ept_identity_pagetable_done))
3471                 return 1;
3472         ret = 0;
3473         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3474         idx = srcu_read_lock(&kvm->srcu);
3475         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3476         if (r < 0)
3477                 goto out;
3478         /* Set up identity-mapping pagetable for EPT in real mode */
3479         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3480                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3481                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3482                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3483                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3484                 if (r < 0)
3485                         goto out;
3486         }
3487         kvm->arch.ept_identity_pagetable_done = true;
3488         ret = 1;
3489 out:
3490         srcu_read_unlock(&kvm->srcu, idx);
3491         return ret;
3492 }
3493
3494 static void seg_setup(int seg)
3495 {
3496         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3497         unsigned int ar;
3498
3499         vmcs_write16(sf->selector, 0);
3500         vmcs_writel(sf->base, 0);
3501         vmcs_write32(sf->limit, 0xffff);
3502         if (enable_unrestricted_guest) {
3503                 ar = 0x93;
3504                 if (seg == VCPU_SREG_CS)
3505                         ar |= 0x08; /* code segment */
3506         } else
3507                 ar = 0xf3;
3508
3509         vmcs_write32(sf->ar_bytes, ar);
3510 }
3511
3512 static int alloc_apic_access_page(struct kvm *kvm)
3513 {
3514         struct kvm_userspace_memory_region kvm_userspace_mem;
3515         int r = 0;
3516
3517         mutex_lock(&kvm->slots_lock);
3518         if (kvm->arch.apic_access_page)
3519                 goto out;
3520         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3521         kvm_userspace_mem.flags = 0;
3522         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3523         kvm_userspace_mem.memory_size = PAGE_SIZE;
3524         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3525         if (r)
3526                 goto out;
3527
3528         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
3529 out:
3530         mutex_unlock(&kvm->slots_lock);
3531         return r;
3532 }
3533
3534 static int alloc_identity_pagetable(struct kvm *kvm)
3535 {
3536         struct kvm_userspace_memory_region kvm_userspace_mem;
3537         int r = 0;
3538
3539         mutex_lock(&kvm->slots_lock);
3540         if (kvm->arch.ept_identity_pagetable)
3541                 goto out;
3542         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3543         kvm_userspace_mem.flags = 0;
3544         kvm_userspace_mem.guest_phys_addr =
3545                 kvm->arch.ept_identity_map_addr;
3546         kvm_userspace_mem.memory_size = PAGE_SIZE;
3547         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3548         if (r)
3549                 goto out;
3550
3551         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
3552                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3553 out:
3554         mutex_unlock(&kvm->slots_lock);
3555         return r;
3556 }
3557
3558 static void allocate_vpid(struct vcpu_vmx *vmx)
3559 {
3560         int vpid;
3561
3562         vmx->vpid = 0;
3563         if (!enable_vpid)
3564                 return;
3565         spin_lock(&vmx_vpid_lock);
3566         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3567         if (vpid < VMX_NR_VPIDS) {
3568                 vmx->vpid = vpid;
3569                 __set_bit(vpid, vmx_vpid_bitmap);
3570         }
3571         spin_unlock(&vmx_vpid_lock);
3572 }
3573
3574 static void free_vpid(struct vcpu_vmx *vmx)
3575 {
3576         if (!enable_vpid)
3577                 return;
3578         spin_lock(&vmx_vpid_lock);
3579         if (vmx->vpid != 0)
3580                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3581         spin_unlock(&vmx_vpid_lock);
3582 }
3583
3584 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
3585 {
3586         int f = sizeof(unsigned long);
3587
3588         if (!cpu_has_vmx_msr_bitmap())
3589                 return;
3590
3591         /*
3592          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3593          * have the write-low and read-high bitmap offsets the wrong way round.
3594          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3595          */
3596         if (msr <= 0x1fff) {
3597                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3598                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
3599         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3600                 msr &= 0x1fff;
3601                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3602                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
3603         }
3604 }
3605
3606 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3607 {
3608         if (!longmode_only)
3609                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3610         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3611 }
3612
3613 /*
3614  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3615  * will not change in the lifetime of the guest.
3616  * Note that host-state that does change is set elsewhere. E.g., host-state
3617  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3618  */
3619 static void vmx_set_constant_host_state(void)
3620 {
3621         u32 low32, high32;
3622         unsigned long tmpl;
3623         struct desc_ptr dt;
3624
3625         vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS);  /* 22.2.3 */
3626         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
3627         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
3628
3629         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
3630         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3631         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3632         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3633         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
3634
3635         native_store_idt(&dt);
3636         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
3637
3638         asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3639         vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3640
3641         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3642         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3643         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3644         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
3645
3646         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3647                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3648                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3649         }
3650 }
3651
3652 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3653 {
3654         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3655         if (enable_ept)
3656                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3657         if (is_guest_mode(&vmx->vcpu))
3658                 vmx->vcpu.arch.cr4_guest_owned_bits &=
3659                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3660         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3661 }
3662
3663 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3664 {
3665         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3666         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3667                 exec_control &= ~CPU_BASED_TPR_SHADOW;
3668 #ifdef CONFIG_X86_64
3669                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3670                                 CPU_BASED_CR8_LOAD_EXITING;
3671 #endif
3672         }
3673         if (!enable_ept)
3674                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3675                                 CPU_BASED_CR3_LOAD_EXITING  |
3676                                 CPU_BASED_INVLPG_EXITING;
3677         return exec_control;
3678 }
3679
3680 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3681 {
3682         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3683         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3684                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3685         if (vmx->vpid == 0)
3686                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3687         if (!enable_ept) {
3688                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3689                 enable_unrestricted_guest = 0;
3690         }
3691         if (!enable_unrestricted_guest)
3692                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3693         if (!ple_gap)
3694                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3695         return exec_control;
3696 }
3697
3698 static void ept_set_mmio_spte_mask(void)
3699 {
3700         /*
3701          * EPT Misconfigurations can be generated if the value of bits 2:0
3702          * of an EPT paging-structure entry is 110b (write/execute).
3703          * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3704          * spte.
3705          */
3706         kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3707 }
3708
3709 /*
3710  * Sets up the vmcs for emulated real mode.
3711  */
3712 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
3713 {
3714 #ifdef CONFIG_X86_64
3715         unsigned long a;
3716 #endif
3717         int i;
3718
3719         /* I/O */
3720         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3721         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
3722
3723         if (cpu_has_vmx_msr_bitmap())
3724                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
3725
3726         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3727
3728         /* Control */
3729         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3730                 vmcs_config.pin_based_exec_ctrl);
3731
3732         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
3733
3734         if (cpu_has_secondary_exec_ctrls()) {
3735                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3736                                 vmx_secondary_exec_control(vmx));
3737         }
3738
3739         if (ple_gap) {
3740                 vmcs_write32(PLE_GAP, ple_gap);
3741                 vmcs_write32(PLE_WINDOW, ple_window);
3742         }
3743
3744         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3745         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
3746         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
3747
3748         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
3749         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
3750         vmx_set_constant_host_state();
3751 #ifdef CONFIG_X86_64
3752         rdmsrl(MSR_FS_BASE, a);
3753         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3754         rdmsrl(MSR_GS_BASE, a);
3755         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3756 #else
3757         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3758         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3759 #endif
3760
3761         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3762         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
3763         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
3764         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
3765         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
3766
3767         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3768                 u32 msr_low, msr_high;
3769                 u64 host_pat;
3770                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3771                 host_pat = msr_low | ((u64) msr_high << 32);
3772                 /* Write the default value follow host pat */
3773                 vmcs_write64(GUEST_IA32_PAT, host_pat);
3774                 /* Keep arch.pat sync with GUEST_IA32_PAT */
3775                 vmx->vcpu.arch.pat = host_pat;
3776         }
3777
3778         for (i = 0; i < NR_VMX_MSR; ++i) {
3779                 u32 index = vmx_msr_index[i];
3780                 u32 data_low, data_high;
3781                 int j = vmx->nmsrs;
3782
3783                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3784                         continue;
3785                 if (wrmsr_safe(index, data_low, data_high) < 0)
3786                         continue;
3787                 vmx->guest_msrs[j].index = i;
3788                 vmx->guest_msrs[j].data = 0;
3789                 vmx->guest_msrs[j].mask = -1ull;
3790                 ++vmx->nmsrs;
3791         }
3792
3793         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
3794
3795         /* 22.2.1, 20.8.1 */
3796         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3797
3798         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
3799         set_cr4_guest_host_mask(vmx);
3800
3801         kvm_write_tsc(&vmx->vcpu, 0);
3802
3803         return 0;
3804 }
3805
3806 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3807 {
3808         struct vcpu_vmx *vmx = to_vmx(vcpu);
3809         u64 msr;
3810         int ret;
3811
3812         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3813
3814         vmx->rmode.vm86_active = 0;
3815
3816         vmx->soft_vnmi_blocked = 0;
3817
3818         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
3819         kvm_set_cr8(&vmx->vcpu, 0);
3820         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
3821         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3822                 msr |= MSR_IA32_APICBASE_BSP;
3823         kvm_set_apic_base(&vmx->vcpu, msr);
3824
3825         ret = fx_init(&vmx->vcpu);
3826         if (ret != 0)
3827                 goto out;
3828
3829         vmx_segment_cache_clear(vmx);
3830
3831         seg_setup(VCPU_SREG_CS);
3832         /*
3833          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3834          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
3835          */
3836         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
3837                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3838                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3839         } else {
3840                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3841                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
3842         }
3843
3844         seg_setup(VCPU_SREG_DS);
3845         seg_setup(VCPU_SREG_ES);
3846         seg_setup(VCPU_SREG_FS);
3847         seg_setup(VCPU_SREG_GS);
3848         seg_setup(VCPU_SREG_SS);
3849
3850         vmcs_write16(GUEST_TR_SELECTOR, 0);
3851         vmcs_writel(GUEST_TR_BASE, 0);
3852         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3853         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3854
3855         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3856         vmcs_writel(GUEST_LDTR_BASE, 0);
3857         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3858         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3859
3860         vmcs_write32(GUEST_SYSENTER_CS, 0);
3861         vmcs_writel(GUEST_SYSENTER_ESP, 0);
3862         vmcs_writel(GUEST_SYSENTER_EIP, 0);
3863
3864         vmcs_writel(GUEST_RFLAGS, 0x02);
3865         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3866                 kvm_rip_write(vcpu, 0xfff0);
3867         else
3868                 kvm_rip_write(vcpu, 0);
3869         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
3870
3871         vmcs_writel(GUEST_DR7, 0x400);
3872
3873         vmcs_writel(GUEST_GDTR_BASE, 0);
3874         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3875
3876         vmcs_writel(GUEST_IDTR_BASE, 0);
3877         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3878
3879         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3880         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3881         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3882
3883         /* Special registers */
3884         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3885
3886         setup_msrs(vmx);
3887
3888         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
3889
3890         if (cpu_has_vmx_tpr_shadow()) {
3891                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3892                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3893                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
3894                                      __pa(vmx->vcpu.arch.apic->regs));
3895                 vmcs_write32(TPR_THRESHOLD, 0);
3896         }
3897
3898         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3899                 vmcs_write64(APIC_ACCESS_ADDR,
3900                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
3901
3902         if (vmx->vpid != 0)
3903                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3904
3905         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
3906         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
3907         vmx_set_cr4(&vmx->vcpu, 0);
3908         vmx_set_efer(&vmx->vcpu, 0);
3909         vmx_fpu_activate(&vmx->vcpu);
3910         update_exception_bitmap(&vmx->vcpu);
3911
3912         vpid_sync_context(vmx);
3913
3914         ret = 0;
3915
3916         /* HACK: Don't enable emulation on guest boot/reset */
3917         vmx->emulation_required = 0;
3918
3919 out:
3920         return ret;
3921 }
3922
3923 /*
3924  * In nested virtualization, check if L1 asked to exit on external interrupts.
3925  * For most existing hypervisors, this will always return true.
3926  */
3927 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
3928 {
3929         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
3930                 PIN_BASED_EXT_INTR_MASK;
3931 }
3932
3933 static void enable_irq_window(struct kvm_vcpu *vcpu)
3934 {
3935         u32 cpu_based_vm_exec_control;
3936         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
3937                 /*
3938                  * We get here if vmx_interrupt_allowed() said we can't
3939                  * inject to L1 now because L2 must run. Ask L2 to exit
3940                  * right after entry, so we can inject to L1 more promptly.
3941                  */
3942                 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
3943                 return;
3944         }
3945
3946         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3947         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
3948         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3949 }
3950
3951 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3952 {
3953         u32 cpu_based_vm_exec_control;
3954
3955         if (!cpu_has_virtual_nmis()) {
3956                 enable_irq_window(vcpu);
3957                 return;
3958         }
3959
3960         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
3961                 enable_irq_window(vcpu);
3962                 return;
3963         }
3964         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3965         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3966         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3967 }
3968
3969 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
3970 {
3971         struct vcpu_vmx *vmx = to_vmx(vcpu);
3972         uint32_t intr;
3973         int irq = vcpu->arch.interrupt.nr;
3974
3975         trace_kvm_inj_virq(irq);
3976
3977         ++vcpu->stat.irq_injections;
3978         if (vmx->rmode.vm86_active) {
3979                 int inc_eip = 0;
3980                 if (vcpu->arch.interrupt.soft)
3981                         inc_eip = vcpu->arch.event_exit_inst_len;
3982                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
3983                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3984                 return;
3985         }
3986         intr = irq | INTR_INFO_VALID_MASK;
3987         if (vcpu->arch.interrupt.soft) {
3988                 intr |= INTR_TYPE_SOFT_INTR;
3989                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3990                              vmx->vcpu.arch.event_exit_inst_len);
3991         } else
3992                 intr |= INTR_TYPE_EXT_INTR;
3993         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
3994 }
3995
3996 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
3997 {
3998         struct vcpu_vmx *vmx = to_vmx(vcpu);
3999
4000         if (is_guest_mode(vcpu))
4001                 return;
4002
4003         if (!cpu_has_virtual_nmis()) {
4004                 /*
4005                  * Tracking the NMI-blocked state in software is built upon
4006                  * finding the next open IRQ window. This, in turn, depends on
4007                  * well-behaving guests: They have to keep IRQs disabled at
4008                  * least as long as the NMI handler runs. Otherwise we may
4009                  * cause NMI nesting, maybe breaking the guest. But as this is
4010                  * highly unlikely, we can live with the residual risk.
4011                  */
4012                 vmx->soft_vnmi_blocked = 1;
4013                 vmx->vnmi_blocked_time = 0;
4014         }
4015
4016         ++vcpu->stat.nmi_injections;
4017         vmx->nmi_known_unmasked = false;
4018         if (vmx->rmode.vm86_active) {
4019                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4020                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4021                 return;
4022         }
4023         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4024                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4025 }
4026
4027 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4028 {
4029         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4030                 return 0;
4031
4032         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4033                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4034                    | GUEST_INTR_STATE_NMI));
4035 }
4036
4037 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4038 {
4039         if (!cpu_has_virtual_nmis())
4040                 return to_vmx(vcpu)->soft_vnmi_blocked;
4041         if (to_vmx(vcpu)->nmi_known_unmasked)
4042                 return false;
4043         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4044 }
4045
4046 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4047 {
4048         struct vcpu_vmx *vmx = to_vmx(vcpu);
4049
4050         if (!cpu_has_virtual_nmis()) {
4051                 if (vmx->soft_vnmi_blocked != masked) {
4052                         vmx->soft_vnmi_blocked = masked;
4053                         vmx->vnmi_blocked_time = 0;
4054                 }
4055         } else {
4056                 vmx->nmi_known_unmasked = !masked;
4057                 if (masked)
4058                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4059                                       GUEST_INTR_STATE_NMI);
4060                 else
4061                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4062                                         GUEST_INTR_STATE_NMI);
4063         }
4064 }
4065
4066 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4067 {
4068         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4069                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4070                 if (to_vmx(vcpu)->nested.nested_run_pending ||
4071                     (vmcs12->idt_vectoring_info_field &
4072                      VECTORING_INFO_VALID_MASK))
4073                         return 0;
4074                 nested_vmx_vmexit(vcpu);
4075                 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4076                 vmcs12->vm_exit_intr_info = 0;
4077                 /* fall through to normal code, but now in L1, not L2 */
4078         }
4079
4080         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4081                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4082                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4083 }
4084
4085 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4086 {
4087         int ret;
4088         struct kvm_userspace_memory_region tss_mem = {
4089                 .slot = TSS_PRIVATE_MEMSLOT,
4090                 .guest_phys_addr = addr,
4091                 .memory_size = PAGE_SIZE * 3,
4092                 .flags = 0,
4093         };
4094
4095         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
4096         if (ret)
4097                 return ret;
4098         kvm->arch.tss_addr = addr;
4099         if (!init_rmode_tss(kvm))
4100                 return  -ENOMEM;
4101
4102         return 0;
4103 }
4104
4105 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4106                                   int vec, u32 err_code)
4107 {
4108         /*
4109          * Instruction with address size override prefix opcode 0x67
4110          * Cause the #SS fault with 0 error code in VM86 mode.
4111          */
4112         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
4113                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
4114                         return 1;
4115         /*
4116          * Forward all other exceptions that are valid in real mode.
4117          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4118          *        the required debugging infrastructure rework.
4119          */
4120         switch (vec) {
4121         case DB_VECTOR:
4122                 if (vcpu->guest_debug &
4123                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4124                         return 0;
4125                 kvm_queue_exception(vcpu, vec);
4126                 return 1;
4127         case BP_VECTOR:
4128                 /*
4129                  * Update instruction length as we may reinject the exception
4130                  * from user space while in guest debugging mode.
4131                  */
4132                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4133                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4134                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4135                         return 0;
4136                 /* fall through */
4137         case DE_VECTOR:
4138         case OF_VECTOR:
4139         case BR_VECTOR:
4140         case UD_VECTOR:
4141         case DF_VECTOR:
4142         case SS_VECTOR:
4143         case GP_VECTOR:
4144         case MF_VECTOR:
4145                 kvm_queue_exception(vcpu, vec);
4146                 return 1;
4147         }
4148         return 0;
4149 }
4150
4151 /*
4152  * Trigger machine check on the host. We assume all the MSRs are already set up
4153  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4154  * We pass a fake environment to the machine check handler because we want
4155  * the guest to be always treated like user space, no matter what context
4156  * it used internally.
4157  */
4158 static void kvm_machine_check(void)
4159 {
4160 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4161         struct pt_regs regs = {
4162                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4163                 .flags = X86_EFLAGS_IF,
4164         };
4165
4166         do_machine_check(&regs, 0);
4167 #endif
4168 }
4169
4170 static int handle_machine_check(struct kvm_vcpu *vcpu)
4171 {
4172         /* already handled by vcpu_run */
4173         return 1;
4174 }
4175
4176 static int handle_exception(struct kvm_vcpu *vcpu)
4177 {
4178         struct vcpu_vmx *vmx = to_vmx(vcpu);
4179         struct kvm_run *kvm_run = vcpu->run;
4180         u32 intr_info, ex_no, error_code;
4181         unsigned long cr2, rip, dr6;
4182         u32 vect_info;
4183         enum emulation_result er;
4184
4185         vect_info = vmx->idt_vectoring_info;
4186         intr_info = vmx->exit_intr_info;
4187
4188         if (is_machine_check(intr_info))
4189                 return handle_machine_check(vcpu);
4190
4191         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4192             !is_page_fault(intr_info)) {
4193                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4194                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4195                 vcpu->run->internal.ndata = 2;
4196                 vcpu->run->internal.data[0] = vect_info;
4197                 vcpu->run->internal.data[1] = intr_info;
4198                 return 0;
4199         }
4200
4201         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4202                 return 1;  /* already handled by vmx_vcpu_run() */
4203
4204         if (is_no_device(intr_info)) {
4205                 vmx_fpu_activate(vcpu);
4206                 return 1;
4207         }
4208
4209         if (is_invalid_opcode(intr_info)) {
4210                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4211                 if (er != EMULATE_DONE)
4212                         kvm_queue_exception(vcpu, UD_VECTOR);
4213                 return 1;
4214         }
4215
4216         error_code = 0;
4217         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4218                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4219         if (is_page_fault(intr_info)) {
4220                 /* EPT won't cause page fault directly */
4221                 BUG_ON(enable_ept);
4222                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4223                 trace_kvm_page_fault(cr2, error_code);
4224
4225                 if (kvm_event_needs_reinjection(vcpu))
4226                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4227                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4228         }
4229
4230         if (vmx->rmode.vm86_active &&
4231             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
4232                                                                 error_code)) {
4233                 if (vcpu->arch.halt_request) {
4234                         vcpu->arch.halt_request = 0;
4235                         return kvm_emulate_halt(vcpu);
4236                 }
4237                 return 1;
4238         }
4239
4240         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4241         switch (ex_no) {
4242         case DB_VECTOR:
4243                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4244                 if (!(vcpu->guest_debug &
4245                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4246                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4247                         kvm_queue_exception(vcpu, DB_VECTOR);
4248                         return 1;
4249                 }
4250                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4251                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4252                 /* fall through */
4253         case BP_VECTOR:
4254                 /*
4255                  * Update instruction length as we may reinject #BP from
4256                  * user space while in guest debugging mode. Reading it for
4257                  * #DB as well causes no harm, it is not used in that case.
4258                  */
4259                 vmx->vcpu.arch.event_exit_inst_len =
4260                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4261                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4262                 rip = kvm_rip_read(vcpu);
4263                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4264                 kvm_run->debug.arch.exception = ex_no;
4265                 break;
4266         default:
4267                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4268                 kvm_run->ex.exception = ex_no;
4269                 kvm_run->ex.error_code = error_code;
4270                 break;
4271         }
4272         return 0;
4273 }
4274
4275 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4276 {
4277         ++vcpu->stat.irq_exits;
4278         return 1;
4279 }
4280
4281 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4282 {
4283         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4284         return 0;
4285 }
4286
4287 static int handle_io(struct kvm_vcpu *vcpu)
4288 {
4289         unsigned long exit_qualification;
4290         int size, in, string;
4291         unsigned port;
4292
4293         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4294         string = (exit_qualification & 16) != 0;
4295         in = (exit_qualification & 8) != 0;
4296
4297         ++vcpu->stat.io_exits;
4298
4299         if (string || in)
4300                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4301
4302         port = exit_qualification >> 16;
4303         size = (exit_qualification & 7) + 1;
4304         skip_emulated_instruction(vcpu);
4305
4306         return kvm_fast_pio_out(vcpu, size, port);
4307 }
4308
4309 static void
4310 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4311 {
4312         /*
4313          * Patch in the VMCALL instruction:
4314          */
4315         hypercall[0] = 0x0f;
4316         hypercall[1] = 0x01;
4317         hypercall[2] = 0xc1;
4318 }
4319
4320 /* called to set cr0 as approriate for a mov-to-cr0 exit. */
4321 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4322 {
4323         if (to_vmx(vcpu)->nested.vmxon &&
4324             ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4325                 return 1;
4326
4327         if (is_guest_mode(vcpu)) {
4328                 /*
4329                  * We get here when L2 changed cr0 in a way that did not change
4330                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4331                  * but did change L0 shadowed bits. This can currently happen
4332                  * with the TS bit: L0 may want to leave TS on (for lazy fpu
4333                  * loading) while pretending to allow the guest to change it.
4334                  */
4335                 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4336                          (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4337                         return 1;
4338                 vmcs_writel(CR0_READ_SHADOW, val);
4339                 return 0;
4340         } else
4341                 return kvm_set_cr0(vcpu, val);
4342 }
4343
4344 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4345 {
4346         if (is_guest_mode(vcpu)) {
4347                 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4348                          (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4349                         return 1;
4350                 vmcs_writel(CR4_READ_SHADOW, val);
4351                 return 0;
4352         } else
4353                 return kvm_set_cr4(vcpu, val);
4354 }
4355
4356 /* called to set cr0 as approriate for clts instruction exit. */
4357 static void handle_clts(struct kvm_vcpu *vcpu)
4358 {
4359         if (is_guest_mode(vcpu)) {
4360                 /*
4361                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4362                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4363                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4364                  */
4365                 vmcs_writel(CR0_READ_SHADOW,
4366                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4367                 vcpu->arch.cr0 &= ~X86_CR0_TS;
4368         } else
4369                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4370 }
4371
4372 static int handle_cr(struct kvm_vcpu *vcpu)
4373 {
4374         unsigned long exit_qualification, val;
4375         int cr;
4376         int reg;
4377         int err;
4378
4379         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4380         cr = exit_qualification & 15;
4381         reg = (exit_qualification >> 8) & 15;
4382         switch ((exit_qualification >> 4) & 3) {
4383         case 0: /* mov to cr */
4384                 val = kvm_register_read(vcpu, reg);
4385                 trace_kvm_cr_write(cr, val);
4386                 switch (cr) {
4387                 case 0:
4388                         err = handle_set_cr0(vcpu, val);
4389                         kvm_complete_insn_gp(vcpu, err);
4390                         return 1;
4391                 case 3:
4392                         err = kvm_set_cr3(vcpu, val);
4393                         kvm_complete_insn_gp(vcpu, err);
4394                         return 1;
4395                 case 4:
4396                         err = handle_set_cr4(vcpu, val);
4397                         kvm_complete_insn_gp(vcpu, err);
4398                         return 1;
4399                 case 8: {
4400                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4401                                 u8 cr8 = kvm_register_read(vcpu, reg);
4402                                 err = kvm_set_cr8(vcpu, cr8);
4403                                 kvm_complete_insn_gp(vcpu, err);
4404                                 if (irqchip_in_kernel(vcpu->kvm))
4405                                         return 1;
4406                                 if (cr8_prev <= cr8)
4407                                         return 1;
4408                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4409                                 return 0;
4410                         }
4411                 };
4412                 break;
4413         case 2: /* clts */
4414                 handle_clts(vcpu);
4415                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4416                 skip_emulated_instruction(vcpu);
4417                 vmx_fpu_activate(vcpu);
4418                 return 1;
4419         case 1: /*mov from cr*/
4420                 switch (cr) {
4421                 case 3:
4422                         val = kvm_read_cr3(vcpu);
4423                         kvm_register_write(vcpu, reg, val);
4424                         trace_kvm_cr_read(cr, val);
4425                         skip_emulated_instruction(vcpu);
4426                         return 1;
4427                 case 8:
4428                         val = kvm_get_cr8(vcpu);
4429                         kvm_register_write(vcpu, reg, val);
4430                         trace_kvm_cr_read(cr, val);
4431                         skip_emulated_instruction(vcpu);
4432                         return 1;
4433                 }
4434                 break;
4435         case 3: /* lmsw */
4436                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4437                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4438                 kvm_lmsw(vcpu, val);
4439
4440                 skip_emulated_instruction(vcpu);
4441                 return 1;
4442         default:
4443                 break;
4444         }
4445         vcpu->run->exit_reason = 0;
4446         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4447                (int)(exit_qualification >> 4) & 3, cr);
4448         return 0;
4449 }
4450
4451 static int handle_dr(struct kvm_vcpu *vcpu)
4452 {
4453         unsigned long exit_qualification;
4454         int dr, reg;
4455
4456         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4457         if (!kvm_require_cpl(vcpu, 0))
4458                 return 1;
4459         dr = vmcs_readl(GUEST_DR7);
4460         if (dr & DR7_GD) {
4461                 /*
4462                  * As the vm-exit takes precedence over the debug trap, we
4463                  * need to emulate the latter, either for the host or the
4464                  * guest debugging itself.
4465                  */
4466                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4467                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4468                         vcpu->run->debug.arch.dr7 = dr;
4469                         vcpu->run->debug.arch.pc =
4470                                 vmcs_readl(GUEST_CS_BASE) +
4471                                 vmcs_readl(GUEST_RIP);
4472                         vcpu->run->debug.arch.exception = DB_VECTOR;
4473                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4474                         return 0;
4475                 } else {
4476                         vcpu->arch.dr7 &= ~DR7_GD;
4477                         vcpu->arch.dr6 |= DR6_BD;
4478                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4479                         kvm_queue_exception(vcpu, DB_VECTOR);
4480                         return 1;
4481                 }
4482         }
4483
4484         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4485         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4486         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4487         if (exit_qualification & TYPE_MOV_FROM_DR) {
4488                 unsigned long val;
4489                 if (!kvm_get_dr(vcpu, dr, &val))
4490                         kvm_register_write(vcpu, reg, val);
4491         } else
4492                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4493         skip_emulated_instruction(vcpu);
4494         return 1;
4495 }
4496
4497 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4498 {
4499         vmcs_writel(GUEST_DR7, val);
4500 }
4501
4502 static int handle_cpuid(struct kvm_vcpu *vcpu)
4503 {
4504         kvm_emulate_cpuid(vcpu);
4505         return 1;
4506 }
4507
4508 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4509 {
4510         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4511         u64 data;
4512
4513         if (vmx_get_msr(vcpu, ecx, &data)) {
4514                 trace_kvm_msr_read_ex(ecx);
4515                 kvm_inject_gp(vcpu, 0);
4516                 return 1;
4517         }
4518
4519         trace_kvm_msr_read(ecx, data);
4520
4521         /* FIXME: handling of bits 32:63 of rax, rdx */
4522         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4523         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4524         skip_emulated_instruction(vcpu);
4525         return 1;
4526 }
4527
4528 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4529 {
4530         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4531         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4532                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4533
4534         if (vmx_set_msr(vcpu, ecx, data) != 0) {
4535                 trace_kvm_msr_write_ex(ecx, data);
4536                 kvm_inject_gp(vcpu, 0);
4537                 return 1;
4538         }
4539
4540         trace_kvm_msr_write(ecx, data);
4541         skip_emulated_instruction(vcpu);
4542         return 1;
4543 }
4544
4545 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4546 {
4547         kvm_make_request(KVM_REQ_EVENT, vcpu);
4548         return 1;
4549 }
4550
4551 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4552 {
4553         u32 cpu_based_vm_exec_control;
4554
4555         /* clear pending irq */
4556         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4557         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4558         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4559
4560         kvm_make_request(KVM_REQ_EVENT, vcpu);
4561
4562         ++vcpu->stat.irq_window_exits;
4563
4564         /*
4565          * If the user space waits to inject interrupts, exit as soon as
4566          * possible
4567          */
4568         if (!irqchip_in_kernel(vcpu->kvm) &&
4569             vcpu->run->request_interrupt_window &&
4570             !kvm_cpu_has_interrupt(vcpu)) {
4571                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4572                 return 0;
4573         }
4574         return 1;
4575 }
4576
4577 static int handle_halt(struct kvm_vcpu *vcpu)
4578 {
4579         skip_emulated_instruction(vcpu);
4580         return kvm_emulate_halt(vcpu);
4581 }
4582
4583 static int handle_vmcall(struct kvm_vcpu *vcpu)
4584 {
4585         skip_emulated_instruction(vcpu);
4586         kvm_emulate_hypercall(vcpu);
4587         return 1;
4588 }
4589
4590 static int handle_invd(struct kvm_vcpu *vcpu)
4591 {
4592         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4593 }
4594
4595 static int handle_invlpg(struct kvm_vcpu *vcpu)
4596 {
4597         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4598
4599         kvm_mmu_invlpg(vcpu, exit_qualification);
4600         skip_emulated_instruction(vcpu);
4601         return 1;
4602 }
4603
4604 static int handle_rdpmc(struct kvm_vcpu *vcpu)
4605 {
4606         int err;
4607
4608         err = kvm_rdpmc(vcpu);
4609         kvm_complete_insn_gp(vcpu, err);
4610
4611         return 1;
4612 }
4613
4614 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4615 {
4616         skip_emulated_instruction(vcpu);
4617         kvm_emulate_wbinvd(vcpu);
4618         return 1;
4619 }
4620
4621 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4622 {
4623         u64 new_bv = kvm_read_edx_eax(vcpu);
4624         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4625
4626         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4627                 skip_emulated_instruction(vcpu);
4628         return 1;
4629 }
4630
4631 static int handle_apic_access(struct kvm_vcpu *vcpu)
4632 {
4633         if (likely(fasteoi)) {
4634                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4635                 int access_type, offset;
4636
4637                 access_type = exit_qualification & APIC_ACCESS_TYPE;
4638                 offset = exit_qualification & APIC_ACCESS_OFFSET;
4639                 /*
4640                  * Sane guest uses MOV to write EOI, with written value
4641                  * not cared. So make a short-circuit here by avoiding
4642                  * heavy instruction emulation.
4643                  */
4644                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4645                     (offset == APIC_EOI)) {
4646                         kvm_lapic_set_eoi(vcpu);
4647                         skip_emulated_instruction(vcpu);
4648                         return 1;
4649                 }
4650         }
4651         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4652 }
4653
4654 static int handle_task_switch(struct kvm_vcpu *vcpu)
4655 {
4656         struct vcpu_vmx *vmx = to_vmx(vcpu);
4657         unsigned long exit_qualification;
4658         bool has_error_code = false;
4659         u32 error_code = 0;
4660         u16 tss_selector;
4661         int reason, type, idt_v;
4662
4663         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4664         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
4665
4666         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4667
4668         reason = (u32)exit_qualification >> 30;
4669         if (reason == TASK_SWITCH_GATE && idt_v) {
4670                 switch (type) {
4671                 case INTR_TYPE_NMI_INTR:
4672                         vcpu->arch.nmi_injected = false;
4673                         vmx_set_nmi_mask(vcpu, true);
4674                         break;
4675                 case INTR_TYPE_EXT_INTR:
4676                 case INTR_TYPE_SOFT_INTR:
4677                         kvm_clear_interrupt_queue(vcpu);
4678                         break;
4679                 case INTR_TYPE_HARD_EXCEPTION:
4680                         if (vmx->idt_vectoring_info &
4681                             VECTORING_INFO_DELIVER_CODE_MASK) {
4682                                 has_error_code = true;
4683                                 error_code =
4684                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
4685                         }
4686                         /* fall through */
4687                 case INTR_TYPE_SOFT_EXCEPTION:
4688                         kvm_clear_exception_queue(vcpu);
4689                         break;
4690                 default:
4691                         break;
4692                 }
4693         }
4694         tss_selector = exit_qualification;
4695
4696         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4697                        type != INTR_TYPE_EXT_INTR &&
4698                        type != INTR_TYPE_NMI_INTR))
4699                 skip_emulated_instruction(vcpu);
4700
4701         if (kvm_task_switch(vcpu, tss_selector, reason,
4702                                 has_error_code, error_code) == EMULATE_FAIL) {
4703                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4704                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4705                 vcpu->run->internal.ndata = 0;
4706                 return 0;
4707         }
4708
4709         /* clear all local breakpoint enable flags */
4710         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4711
4712         /*
4713          * TODO: What about debug traps on tss switch?
4714          *       Are we supposed to inject them and update dr6?
4715          */
4716
4717         return 1;
4718 }
4719
4720 static int handle_ept_violation(struct kvm_vcpu *vcpu)
4721 {
4722         unsigned long exit_qualification;
4723         gpa_t gpa;
4724         int gla_validity;
4725
4726         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4727
4728         if (exit_qualification & (1 << 6)) {
4729                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
4730                 return -EINVAL;
4731         }
4732
4733         gla_validity = (exit_qualification >> 7) & 0x3;
4734         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4735                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4736                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4737                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
4738                         vmcs_readl(GUEST_LINEAR_ADDRESS));
4739                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4740                         (long unsigned int)exit_qualification);
4741                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4742                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
4743                 return 0;
4744         }
4745
4746         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4747         trace_kvm_page_fault(gpa, exit_qualification);
4748         return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
4749 }
4750
4751 static u64 ept_rsvd_mask(u64 spte, int level)
4752 {
4753         int i;
4754         u64 mask = 0;
4755
4756         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4757                 mask |= (1ULL << i);
4758
4759         if (level > 2)
4760                 /* bits 7:3 reserved */
4761                 mask |= 0xf8;
4762         else if (level == 2) {
4763                 if (spte & (1ULL << 7))
4764                         /* 2MB ref, bits 20:12 reserved */
4765                         mask |= 0x1ff000;
4766                 else
4767                         /* bits 6:3 reserved */
4768                         mask |= 0x78;
4769         }
4770
4771         return mask;
4772 }
4773
4774 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4775                                        int level)
4776 {
4777         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4778
4779         /* 010b (write-only) */
4780         WARN_ON((spte & 0x7) == 0x2);
4781
4782         /* 110b (write/execute) */
4783         WARN_ON((spte & 0x7) == 0x6);
4784
4785         /* 100b (execute-only) and value not supported by logical processor */
4786         if (!cpu_has_vmx_ept_execute_only())
4787                 WARN_ON((spte & 0x7) == 0x4);
4788
4789         /* not 000b */
4790         if ((spte & 0x7)) {
4791                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4792
4793                 if (rsvd_bits != 0) {
4794                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4795                                          __func__, rsvd_bits);
4796                         WARN_ON(1);
4797                 }
4798
4799                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4800                         u64 ept_mem_type = (spte & 0x38) >> 3;
4801
4802                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
4803                             ept_mem_type == 7) {
4804                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4805                                                 __func__, ept_mem_type);
4806                                 WARN_ON(1);
4807                         }
4808                 }
4809         }
4810 }
4811
4812 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
4813 {
4814         u64 sptes[4];
4815         int nr_sptes, i, ret;
4816         gpa_t gpa;
4817
4818         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4819
4820         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4821         if (likely(ret == 1))
4822                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4823                                               EMULATE_DONE;
4824         if (unlikely(!ret))
4825                 return 1;
4826
4827         /* It is the real ept misconfig */
4828         printk(KERN_ERR "EPT: Misconfiguration.\n");
4829         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4830
4831         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4832
4833         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4834                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4835
4836         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4837         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
4838
4839         return 0;
4840 }
4841
4842 static int handle_nmi_window(struct kvm_vcpu *vcpu)
4843 {
4844         u32 cpu_based_vm_exec_control;
4845
4846         /* clear pending NMI */
4847         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4848         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4849         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4850         ++vcpu->stat.nmi_window_exits;
4851         kvm_make_request(KVM_REQ_EVENT, vcpu);
4852
4853         return 1;
4854 }
4855
4856 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
4857 {
4858         struct vcpu_vmx *vmx = to_vmx(vcpu);
4859         enum emulation_result err = EMULATE_DONE;
4860         int ret = 1;
4861         u32 cpu_exec_ctrl;
4862         bool intr_window_requested;
4863
4864         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4865         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
4866
4867         while (!guest_state_valid(vcpu)) {
4868                 if (intr_window_requested
4869                     && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
4870                         return handle_interrupt_window(&vmx->vcpu);
4871
4872                 err = emulate_instruction(vcpu, 0);
4873
4874                 if (err == EMULATE_DO_MMIO) {
4875                         ret = 0;
4876                         goto out;
4877                 }
4878
4879                 if (err != EMULATE_DONE)
4880                         return 0;
4881
4882                 if (signal_pending(current))
4883                         goto out;
4884                 if (need_resched())
4885                         schedule();
4886         }
4887
4888         vmx->emulation_required = 0;
4889 out:
4890         return ret;
4891 }
4892
4893 /*
4894  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4895  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4896  */
4897 static int handle_pause(struct kvm_vcpu *vcpu)
4898 {
4899         skip_emulated_instruction(vcpu);
4900         kvm_vcpu_on_spin(vcpu);
4901
4902         return 1;
4903 }
4904
4905 static int handle_invalid_op(struct kvm_vcpu *vcpu)
4906 {
4907         kvm_queue_exception(vcpu, UD_VECTOR);
4908         return 1;
4909 }
4910
4911 /*
4912  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
4913  * We could reuse a single VMCS for all the L2 guests, but we also want the
4914  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
4915  * allows keeping them loaded on the processor, and in the future will allow
4916  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
4917  * every entry if they never change.
4918  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
4919  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
4920  *
4921  * The following functions allocate and free a vmcs02 in this pool.
4922  */
4923
4924 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
4925 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
4926 {
4927         struct vmcs02_list *item;
4928         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4929                 if (item->vmptr == vmx->nested.current_vmptr) {
4930                         list_move(&item->list, &vmx->nested.vmcs02_pool);
4931                         return &item->vmcs02;
4932                 }
4933
4934         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
4935                 /* Recycle the least recently used VMCS. */
4936                 item = list_entry(vmx->nested.vmcs02_pool.prev,
4937                         struct vmcs02_list, list);
4938                 item->vmptr = vmx->nested.current_vmptr;
4939                 list_move(&item->list, &vmx->nested.vmcs02_pool);
4940                 return &item->vmcs02;
4941         }
4942
4943         /* Create a new VMCS */
4944         item = (struct vmcs02_list *)
4945                 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
4946         if (!item)
4947                 return NULL;
4948         item->vmcs02.vmcs = alloc_vmcs();
4949         if (!item->vmcs02.vmcs) {
4950                 kfree(item);
4951                 return NULL;
4952         }
4953         loaded_vmcs_init(&item->vmcs02);
4954         item->vmptr = vmx->nested.current_vmptr;
4955         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
4956         vmx->nested.vmcs02_num++;
4957         return &item->vmcs02;
4958 }
4959
4960 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
4961 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
4962 {
4963         struct vmcs02_list *item;
4964         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4965                 if (item->vmptr == vmptr) {
4966                         free_loaded_vmcs(&item->vmcs02);
4967                         list_del(&item->list);
4968                         kfree(item);
4969                         vmx->nested.vmcs02_num--;
4970                         return;
4971                 }
4972 }
4973
4974 /*
4975  * Free all VMCSs saved for this vcpu, except the one pointed by
4976  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
4977  * currently used, if running L2), and vmcs01 when running L2.
4978  */
4979 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
4980 {
4981         struct vmcs02_list *item, *n;
4982         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4983                 if (vmx->loaded_vmcs != &item->vmcs02)
4984                         free_loaded_vmcs(&item->vmcs02);
4985                 list_del(&item->list);
4986                 kfree(item);
4987         }
4988         vmx->nested.vmcs02_num = 0;
4989
4990         if (vmx->loaded_vmcs != &vmx->vmcs01)
4991                 free_loaded_vmcs(&vmx->vmcs01);
4992 }
4993
4994 /*
4995  * Emulate the VMXON instruction.
4996  * Currently, we just remember that VMX is active, and do not save or even
4997  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
4998  * do not currently need to store anything in that guest-allocated memory
4999  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5000  * argument is different from the VMXON pointer (which the spec says they do).
5001  */
5002 static int handle_vmon(struct kvm_vcpu *vcpu)
5003 {
5004         struct kvm_segment cs;
5005         struct vcpu_vmx *vmx = to_vmx(vcpu);
5006
5007         /* The Intel VMX Instruction Reference lists a bunch of bits that
5008          * are prerequisite to running VMXON, most notably cr4.VMXE must be
5009          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5010          * Otherwise, we should fail with #UD. We test these now:
5011          */
5012         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5013             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5014             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5015                 kvm_queue_exception(vcpu, UD_VECTOR);
5016                 return 1;
5017         }
5018
5019         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5020         if (is_long_mode(vcpu) && !cs.l) {
5021                 kvm_queue_exception(vcpu, UD_VECTOR);
5022                 return 1;
5023         }
5024
5025         if (vmx_get_cpl(vcpu)) {
5026                 kvm_inject_gp(vcpu, 0);
5027                 return 1;
5028         }
5029
5030         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5031         vmx->nested.vmcs02_num = 0;
5032
5033         vmx->nested.vmxon = true;
5034
5035         skip_emulated_instruction(vcpu);
5036         return 1;
5037 }
5038
5039 /*
5040  * Intel's VMX Instruction Reference specifies a common set of prerequisites
5041  * for running VMX instructions (except VMXON, whose prerequisites are
5042  * slightly different). It also specifies what exception to inject otherwise.
5043  */
5044 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5045 {
5046         struct kvm_segment cs;
5047         struct vcpu_vmx *vmx = to_vmx(vcpu);
5048
5049         if (!vmx->nested.vmxon) {
5050                 kvm_queue_exception(vcpu, UD_VECTOR);
5051                 return 0;
5052         }
5053
5054         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5055         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5056             (is_long_mode(vcpu) && !cs.l)) {
5057                 kvm_queue_exception(vcpu, UD_VECTOR);
5058                 return 0;
5059         }
5060
5061         if (vmx_get_cpl(vcpu)) {
5062                 kvm_inject_gp(vcpu, 0);
5063                 return 0;
5064         }
5065
5066         return 1;
5067 }
5068
5069 /*
5070  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5071  * just stops using VMX.
5072  */
5073 static void free_nested(struct vcpu_vmx *vmx)
5074 {
5075         if (!vmx->nested.vmxon)
5076                 return;
5077         vmx->nested.vmxon = false;
5078         if (vmx->nested.current_vmptr != -1ull) {
5079                 kunmap(vmx->nested.current_vmcs12_page);
5080                 nested_release_page(vmx->nested.current_vmcs12_page);
5081                 vmx->nested.current_vmptr = -1ull;
5082                 vmx->nested.current_vmcs12 = NULL;
5083         }
5084         /* Unpin physical memory we referred to in current vmcs02 */
5085         if (vmx->nested.apic_access_page) {
5086                 nested_release_page(vmx->nested.apic_access_page);
5087                 vmx->nested.apic_access_page = 0;
5088         }
5089
5090         nested_free_all_saved_vmcss(vmx);
5091 }
5092
5093 /* Emulate the VMXOFF instruction */
5094 static int handle_vmoff(struct kvm_vcpu *vcpu)
5095 {
5096         if (!nested_vmx_check_permission(vcpu))
5097                 return 1;
5098         free_nested(to_vmx(vcpu));
5099         skip_emulated_instruction(vcpu);
5100         return 1;
5101 }
5102
5103 /*
5104  * Decode the memory-address operand of a vmx instruction, as recorded on an
5105  * exit caused by such an instruction (run by a guest hypervisor).
5106  * On success, returns 0. When the operand is invalid, returns 1 and throws
5107  * #UD or #GP.
5108  */
5109 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5110                                  unsigned long exit_qualification,
5111                                  u32 vmx_instruction_info, gva_t *ret)
5112 {
5113         /*
5114          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5115          * Execution", on an exit, vmx_instruction_info holds most of the
5116          * addressing components of the operand. Only the displacement part
5117          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5118          * For how an actual address is calculated from all these components,
5119          * refer to Vol. 1, "Operand Addressing".
5120          */
5121         int  scaling = vmx_instruction_info & 3;
5122         int  addr_size = (vmx_instruction_info >> 7) & 7;
5123         bool is_reg = vmx_instruction_info & (1u << 10);
5124         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5125         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5126         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5127         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5128         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5129
5130         if (is_reg) {
5131                 kvm_queue_exception(vcpu, UD_VECTOR);
5132                 return 1;
5133         }
5134
5135         /* Addr = segment_base + offset */
5136         /* offset = base + [index * scale] + displacement */
5137         *ret = vmx_get_segment_base(vcpu, seg_reg);
5138         if (base_is_valid)
5139                 *ret += kvm_register_read(vcpu, base_reg);
5140         if (index_is_valid)
5141                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5142         *ret += exit_qualification; /* holds the displacement */
5143
5144         if (addr_size == 1) /* 32 bit */
5145                 *ret &= 0xffffffff;
5146
5147         /*
5148          * TODO: throw #GP (and return 1) in various cases that the VM*
5149          * instructions require it - e.g., offset beyond segment limit,
5150          * unusable or unreadable/unwritable segment, non-canonical 64-bit
5151          * address, and so on. Currently these are not checked.
5152          */
5153         return 0;
5154 }
5155
5156 /*
5157  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5158  * set the success or error code of an emulated VMX instruction, as specified
5159  * by Vol 2B, VMX Instruction Reference, "Conventions".
5160  */
5161 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5162 {
5163         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5164                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5165                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5166 }
5167
5168 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5169 {
5170         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5171                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5172                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5173                         | X86_EFLAGS_CF);
5174 }
5175
5176 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5177                                         u32 vm_instruction_error)
5178 {
5179         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5180                 /*
5181                  * failValid writes the error number to the current VMCS, which
5182                  * can't be done there isn't a current VMCS.
5183                  */
5184                 nested_vmx_failInvalid(vcpu);
5185                 return;
5186         }
5187         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5188                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5189                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5190                         | X86_EFLAGS_ZF);
5191         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5192 }
5193
5194 /* Emulate the VMCLEAR instruction */
5195 static int handle_vmclear(struct kvm_vcpu *vcpu)
5196 {
5197         struct vcpu_vmx *vmx = to_vmx(vcpu);
5198         gva_t gva;
5199         gpa_t vmptr;
5200         struct vmcs12 *vmcs12;
5201         struct page *page;
5202         struct x86_exception e;
5203
5204         if (!nested_vmx_check_permission(vcpu))
5205                 return 1;
5206
5207         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5208                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5209                 return 1;
5210
5211         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5212                                 sizeof(vmptr), &e)) {
5213                 kvm_inject_page_fault(vcpu, &e);
5214                 return 1;
5215         }
5216
5217         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5218                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5219                 skip_emulated_instruction(vcpu);
5220                 return 1;
5221         }
5222
5223         if (vmptr == vmx->nested.current_vmptr) {
5224                 kunmap(vmx->nested.current_vmcs12_page);
5225                 nested_release_page(vmx->nested.current_vmcs12_page);
5226                 vmx->nested.current_vmptr = -1ull;
5227                 vmx->nested.current_vmcs12 = NULL;
5228         }
5229
5230         page = nested_get_page(vcpu, vmptr);
5231         if (page == NULL) {
5232                 /*
5233                  * For accurate processor emulation, VMCLEAR beyond available
5234                  * physical memory should do nothing at all. However, it is
5235                  * possible that a nested vmx bug, not a guest hypervisor bug,
5236                  * resulted in this case, so let's shut down before doing any
5237                  * more damage:
5238                  */
5239                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5240                 return 1;
5241         }
5242         vmcs12 = kmap(page);
5243         vmcs12->launch_state = 0;
5244         kunmap(page);
5245         nested_release_page(page);
5246
5247         nested_free_vmcs02(vmx, vmptr);
5248
5249         skip_emulated_instruction(vcpu);
5250         nested_vmx_succeed(vcpu);
5251         return 1;
5252 }
5253
5254 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5255
5256 /* Emulate the VMLAUNCH instruction */
5257 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5258 {
5259         return nested_vmx_run(vcpu, true);
5260 }
5261
5262 /* Emulate the VMRESUME instruction */
5263 static int handle_vmresume(struct kvm_vcpu *vcpu)
5264 {
5265
5266         return nested_vmx_run(vcpu, false);
5267 }
5268
5269 enum vmcs_field_type {
5270         VMCS_FIELD_TYPE_U16 = 0,
5271         VMCS_FIELD_TYPE_U64 = 1,
5272         VMCS_FIELD_TYPE_U32 = 2,
5273         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5274 };
5275
5276 static inline int vmcs_field_type(unsigned long field)
5277 {
5278         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
5279                 return VMCS_FIELD_TYPE_U32;
5280         return (field >> 13) & 0x3 ;
5281 }
5282
5283 static inline int vmcs_field_readonly(unsigned long field)
5284 {
5285         return (((field >> 10) & 0x3) == 1);
5286 }
5287
5288 /*
5289  * Read a vmcs12 field. Since these can have varying lengths and we return
5290  * one type, we chose the biggest type (u64) and zero-extend the return value
5291  * to that size. Note that the caller, handle_vmread, might need to use only
5292  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5293  * 64-bit fields are to be returned).
5294  */
5295 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5296                                         unsigned long field, u64 *ret)
5297 {
5298         short offset = vmcs_field_to_offset(field);
5299         char *p;
5300
5301         if (offset < 0)
5302                 return 0;
5303
5304         p = ((char *)(get_vmcs12(vcpu))) + offset;
5305
5306         switch (vmcs_field_type(field)) {
5307         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5308                 *ret = *((natural_width *)p);
5309                 return 1;
5310         case VMCS_FIELD_TYPE_U16:
5311                 *ret = *((u16 *)p);
5312                 return 1;
5313         case VMCS_FIELD_TYPE_U32:
5314                 *ret = *((u32 *)p);
5315                 return 1;
5316         case VMCS_FIELD_TYPE_U64:
5317                 *ret = *((u64 *)p);
5318                 return 1;
5319         default:
5320                 return 0; /* can never happen. */
5321         }
5322 }
5323
5324 /*
5325  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5326  * used before) all generate the same failure when it is missing.
5327  */
5328 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5329 {
5330         struct vcpu_vmx *vmx = to_vmx(vcpu);
5331         if (vmx->nested.current_vmptr == -1ull) {
5332                 nested_vmx_failInvalid(vcpu);
5333                 skip_emulated_instruction(vcpu);
5334                 return 0;
5335         }
5336         return 1;
5337 }
5338
5339 static int handle_vmread(struct kvm_vcpu *vcpu)
5340 {
5341         unsigned long field;
5342         u64 field_value;
5343         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5344         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5345         gva_t gva = 0;
5346
5347         if (!nested_vmx_check_permission(vcpu) ||
5348             !nested_vmx_check_vmcs12(vcpu))
5349                 return 1;
5350
5351         /* Decode instruction info and find the field to read */
5352         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5353         /* Read the field, zero-extended to a u64 field_value */
5354         if (!vmcs12_read_any(vcpu, field, &field_value)) {
5355                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5356                 skip_emulated_instruction(vcpu);
5357                 return 1;
5358         }
5359         /*
5360          * Now copy part of this value to register or memory, as requested.
5361          * Note that the number of bits actually copied is 32 or 64 depending
5362          * on the guest's mode (32 or 64 bit), not on the given field's length.
5363          */
5364         if (vmx_instruction_info & (1u << 10)) {
5365                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5366                         field_value);
5367         } else {
5368                 if (get_vmx_mem_address(vcpu, exit_qualification,
5369                                 vmx_instruction_info, &gva))
5370                         return 1;
5371                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5372                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5373                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5374         }
5375
5376         nested_vmx_succeed(vcpu);
5377         skip_emulated_instruction(vcpu);
5378         return 1;
5379 }
5380
5381
5382 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5383 {
5384         unsigned long field;
5385         gva_t gva;
5386         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5387         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5388         char *p;
5389         short offset;
5390         /* The value to write might be 32 or 64 bits, depending on L1's long
5391          * mode, and eventually we need to write that into a field of several
5392          * possible lengths. The code below first zero-extends the value to 64
5393          * bit (field_value), and then copies only the approriate number of
5394          * bits into the vmcs12 field.
5395          */
5396         u64 field_value = 0;
5397         struct x86_exception e;
5398
5399         if (!nested_vmx_check_permission(vcpu) ||
5400             !nested_vmx_check_vmcs12(vcpu))
5401                 return 1;
5402
5403         if (vmx_instruction_info & (1u << 10))
5404                 field_value = kvm_register_read(vcpu,
5405                         (((vmx_instruction_info) >> 3) & 0xf));
5406         else {
5407                 if (get_vmx_mem_address(vcpu, exit_qualification,
5408                                 vmx_instruction_info, &gva))
5409                         return 1;
5410                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5411                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5412                         kvm_inject_page_fault(vcpu, &e);
5413                         return 1;
5414                 }
5415         }
5416
5417
5418         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5419         if (vmcs_field_readonly(field)) {
5420                 nested_vmx_failValid(vcpu,
5421                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5422                 skip_emulated_instruction(vcpu);
5423                 return 1;
5424         }
5425
5426         offset = vmcs_field_to_offset(field);
5427         if (offset < 0) {
5428                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5429                 skip_emulated_instruction(vcpu);
5430                 return 1;
5431         }
5432         p = ((char *) get_vmcs12(vcpu)) + offset;
5433
5434         switch (vmcs_field_type(field)) {
5435         case VMCS_FIELD_TYPE_U16:
5436                 *(u16 *)p = field_value;
5437                 break;
5438         case VMCS_FIELD_TYPE_U32:
5439                 *(u32 *)p = field_value;
5440                 break;
5441         case VMCS_FIELD_TYPE_U64:
5442                 *(u64 *)p = field_value;
5443                 break;
5444         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5445                 *(natural_width *)p = field_value;
5446                 break;
5447         default:
5448                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5449                 skip_emulated_instruction(vcpu);
5450                 return 1;
5451         }
5452
5453         nested_vmx_succeed(vcpu);
5454         skip_emulated_instruction(vcpu);
5455         return 1;
5456 }
5457
5458 /* Emulate the VMPTRLD instruction */
5459 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5460 {
5461         struct vcpu_vmx *vmx = to_vmx(vcpu);
5462         gva_t gva;
5463         gpa_t vmptr;
5464         struct x86_exception e;
5465
5466         if (!nested_vmx_check_permission(vcpu))
5467                 return 1;
5468
5469         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5470                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5471                 return 1;
5472
5473         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5474                                 sizeof(vmptr), &e)) {
5475                 kvm_inject_page_fault(vcpu, &e);
5476                 return 1;
5477         }
5478
5479         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5480                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5481                 skip_emulated_instruction(vcpu);
5482                 return 1;
5483         }
5484
5485         if (vmx->nested.current_vmptr != vmptr) {
5486                 struct vmcs12 *new_vmcs12;
5487                 struct page *page;
5488                 page = nested_get_page(vcpu, vmptr);
5489                 if (page == NULL) {
5490                         nested_vmx_failInvalid(vcpu);
5491                         skip_emulated_instruction(vcpu);
5492                         return 1;
5493                 }
5494                 new_vmcs12 = kmap(page);
5495                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5496                         kunmap(page);
5497                         nested_release_page_clean(page);
5498                         nested_vmx_failValid(vcpu,
5499                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5500                         skip_emulated_instruction(vcpu);
5501                         return 1;
5502                 }
5503                 if (vmx->nested.current_vmptr != -1ull) {
5504                         kunmap(vmx->nested.current_vmcs12_page);
5505                         nested_release_page(vmx->nested.current_vmcs12_page);
5506                 }
5507
5508                 vmx->nested.current_vmptr = vmptr;
5509                 vmx->nested.current_vmcs12 = new_vmcs12;
5510                 vmx->nested.current_vmcs12_page = page;
5511         }
5512
5513         nested_vmx_succeed(vcpu);
5514         skip_emulated_instruction(vcpu);
5515         return 1;
5516 }
5517
5518 /* Emulate the VMPTRST instruction */
5519 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5520 {
5521         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5522         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5523         gva_t vmcs_gva;
5524         struct x86_exception e;
5525
5526         if (!nested_vmx_check_permission(vcpu))
5527                 return 1;
5528
5529         if (get_vmx_mem_address(vcpu, exit_qualification,
5530                         vmx_instruction_info, &vmcs_gva))
5531                 return 1;
5532         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5533         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5534                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
5535                                  sizeof(u64), &e)) {
5536                 kvm_inject_page_fault(vcpu, &e);
5537                 return 1;
5538         }
5539         nested_vmx_succeed(vcpu);
5540         skip_emulated_instruction(vcpu);
5541         return 1;
5542 }
5543
5544 /*
5545  * The exit handlers return 1 if the exit was handled fully and guest execution
5546  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5547  * to be done to userspace and return 0.
5548  */
5549 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5550         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
5551         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5552         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5553         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5554         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5555         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5556         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5557         [EXIT_REASON_CPUID]                   = handle_cpuid,
5558         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
5559         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
5560         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
5561         [EXIT_REASON_HLT]                     = handle_halt,
5562         [EXIT_REASON_INVD]                    = handle_invd,
5563         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5564         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
5565         [EXIT_REASON_VMCALL]                  = handle_vmcall,
5566         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
5567         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
5568         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
5569         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
5570         [EXIT_REASON_VMREAD]                  = handle_vmread,
5571         [EXIT_REASON_VMRESUME]                = handle_vmresume,
5572         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
5573         [EXIT_REASON_VMOFF]                   = handle_vmoff,
5574         [EXIT_REASON_VMON]                    = handle_vmon,
5575         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5576         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5577         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
5578         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
5579         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5580         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5581         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5582         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5583         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5584         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
5585         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
5586 };
5587
5588 static const int kvm_vmx_max_exit_handlers =
5589         ARRAY_SIZE(kvm_vmx_exit_handlers);
5590
5591 /*
5592  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5593  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5594  * disinterest in the current event (read or write a specific MSR) by using an
5595  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5596  */
5597 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5598         struct vmcs12 *vmcs12, u32 exit_reason)
5599 {
5600         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5601         gpa_t bitmap;
5602
5603         if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5604                 return 1;
5605
5606         /*
5607          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5608          * for the four combinations of read/write and low/high MSR numbers.
5609          * First we need to figure out which of the four to use:
5610          */
5611         bitmap = vmcs12->msr_bitmap;
5612         if (exit_reason == EXIT_REASON_MSR_WRITE)
5613                 bitmap += 2048;
5614         if (msr_index >= 0xc0000000) {
5615                 msr_index -= 0xc0000000;
5616                 bitmap += 1024;
5617         }
5618
5619         /* Then read the msr_index'th bit from this bitmap: */
5620         if (msr_index < 1024*8) {
5621                 unsigned char b;
5622                 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5623                 return 1 & (b >> (msr_index & 7));
5624         } else
5625                 return 1; /* let L1 handle the wrong parameter */
5626 }
5627
5628 /*
5629  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5630  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5631  * intercept (via guest_host_mask etc.) the current event.
5632  */
5633 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5634         struct vmcs12 *vmcs12)
5635 {
5636         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5637         int cr = exit_qualification & 15;
5638         int reg = (exit_qualification >> 8) & 15;
5639         unsigned long val = kvm_register_read(vcpu, reg);
5640
5641         switch ((exit_qualification >> 4) & 3) {
5642         case 0: /* mov to cr */
5643                 switch (cr) {
5644                 case 0:
5645                         if (vmcs12->cr0_guest_host_mask &
5646                             (val ^ vmcs12->cr0_read_shadow))
5647                                 return 1;
5648                         break;
5649                 case 3:
5650                         if ((vmcs12->cr3_target_count >= 1 &&
5651                                         vmcs12->cr3_target_value0 == val) ||
5652                                 (vmcs12->cr3_target_count >= 2 &&
5653                                         vmcs12->cr3_target_value1 == val) ||
5654                                 (vmcs12->cr3_target_count >= 3 &&
5655                                         vmcs12->cr3_target_value2 == val) ||
5656                                 (vmcs12->cr3_target_count >= 4 &&
5657                                         vmcs12->cr3_target_value3 == val))
5658                                 return 0;
5659                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5660                                 return 1;
5661                         break;
5662                 case 4:
5663                         if (vmcs12->cr4_guest_host_mask &
5664                             (vmcs12->cr4_read_shadow ^ val))
5665                                 return 1;
5666                         break;
5667                 case 8:
5668                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5669                                 return 1;
5670                         break;
5671                 }
5672                 break;
5673         case 2: /* clts */
5674                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5675                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
5676                         return 1;
5677                 break;
5678         case 1: /* mov from cr */
5679                 switch (cr) {
5680                 case 3:
5681                         if (vmcs12->cpu_based_vm_exec_control &
5682                             CPU_BASED_CR3_STORE_EXITING)
5683                                 return 1;
5684                         break;
5685                 case 8:
5686                         if (vmcs12->cpu_based_vm_exec_control &
5687                             CPU_BASED_CR8_STORE_EXITING)
5688                                 return 1;
5689                         break;
5690                 }
5691                 break;
5692         case 3: /* lmsw */
5693                 /*
5694                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5695                  * cr0. Other attempted changes are ignored, with no exit.
5696                  */
5697                 if (vmcs12->cr0_guest_host_mask & 0xe &
5698                     (val ^ vmcs12->cr0_read_shadow))
5699                         return 1;
5700                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5701                     !(vmcs12->cr0_read_shadow & 0x1) &&
5702                     (val & 0x1))
5703                         return 1;
5704                 break;
5705         }
5706         return 0;
5707 }
5708
5709 /*
5710  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5711  * should handle it ourselves in L0 (and then continue L2). Only call this
5712  * when in is_guest_mode (L2).
5713  */
5714 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5715 {
5716         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5717         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5718         struct vcpu_vmx *vmx = to_vmx(vcpu);
5719         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5720
5721         if (vmx->nested.nested_run_pending)
5722                 return 0;
5723
5724         if (unlikely(vmx->fail)) {
5725                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5726                                     vmcs_read32(VM_INSTRUCTION_ERROR));
5727                 return 1;
5728         }
5729
5730         switch (exit_reason) {
5731         case EXIT_REASON_EXCEPTION_NMI:
5732                 if (!is_exception(intr_info))
5733                         return 0;
5734                 else if (is_page_fault(intr_info))
5735                         return enable_ept;
5736                 return vmcs12->exception_bitmap &
5737                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5738         case EXIT_REASON_EXTERNAL_INTERRUPT:
5739                 return 0;
5740         case EXIT_REASON_TRIPLE_FAULT:
5741                 return 1;
5742         case EXIT_REASON_PENDING_INTERRUPT:
5743         case EXIT_REASON_NMI_WINDOW:
5744                 /*
5745                  * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5746                  * (aka Interrupt Window Exiting) only when L1 turned it on,
5747                  * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5748                  * Same for NMI Window Exiting.
5749                  */
5750                 return 1;
5751         case EXIT_REASON_TASK_SWITCH:
5752                 return 1;
5753         case EXIT_REASON_CPUID:
5754                 return 1;
5755         case EXIT_REASON_HLT:
5756                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5757         case EXIT_REASON_INVD:
5758                 return 1;
5759         case EXIT_REASON_INVLPG:
5760                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5761         case EXIT_REASON_RDPMC:
5762                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5763         case EXIT_REASON_RDTSC:
5764                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5765         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5766         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5767         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5768         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5769         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5770                 /*
5771                  * VMX instructions trap unconditionally. This allows L1 to
5772                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
5773                  */
5774                 return 1;
5775         case EXIT_REASON_CR_ACCESS:
5776                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5777         case EXIT_REASON_DR_ACCESS:
5778                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5779         case EXIT_REASON_IO_INSTRUCTION:
5780                 /* TODO: support IO bitmaps */
5781                 return 1;
5782         case EXIT_REASON_MSR_READ:
5783         case EXIT_REASON_MSR_WRITE:
5784                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5785         case EXIT_REASON_INVALID_STATE:
5786                 return 1;
5787         case EXIT_REASON_MWAIT_INSTRUCTION:
5788                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5789         case EXIT_REASON_MONITOR_INSTRUCTION:
5790                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5791         case EXIT_REASON_PAUSE_INSTRUCTION:
5792                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5793                         nested_cpu_has2(vmcs12,
5794                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5795         case EXIT_REASON_MCE_DURING_VMENTRY:
5796                 return 0;
5797         case EXIT_REASON_TPR_BELOW_THRESHOLD:
5798                 return 1;
5799         case EXIT_REASON_APIC_ACCESS:
5800                 return nested_cpu_has2(vmcs12,
5801                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5802         case EXIT_REASON_EPT_VIOLATION:
5803         case EXIT_REASON_EPT_MISCONFIG:
5804                 return 0;
5805         case EXIT_REASON_WBINVD:
5806                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5807         case EXIT_REASON_XSETBV:
5808                 return 1;
5809         default:
5810                 return 1;
5811         }
5812 }
5813
5814 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5815 {
5816         *info1 = vmcs_readl(EXIT_QUALIFICATION);
5817         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5818 }
5819
5820 /*
5821  * The guest has exited.  See if we can fix it or if we need userspace
5822  * assistance.
5823  */
5824 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5825 {
5826         struct vcpu_vmx *vmx = to_vmx(vcpu);
5827         u32 exit_reason = vmx->exit_reason;
5828         u32 vectoring_info = vmx->idt_vectoring_info;
5829
5830         /* If guest state is invalid, start emulating */
5831         if (vmx->emulation_required && emulate_invalid_guest_state)
5832                 return handle_invalid_guest_state(vcpu);
5833
5834         /*
5835          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5836          * we did not inject a still-pending event to L1 now because of
5837          * nested_run_pending, we need to re-enable this bit.
5838          */
5839         if (vmx->nested.nested_run_pending)
5840                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5841
5842         if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5843             exit_reason == EXIT_REASON_VMRESUME))
5844                 vmx->nested.nested_run_pending = 1;
5845         else
5846                 vmx->nested.nested_run_pending = 0;
5847
5848         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5849                 nested_vmx_vmexit(vcpu);
5850                 return 1;
5851         }
5852
5853         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5854                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5855                 vcpu->run->fail_entry.hardware_entry_failure_reason
5856                         = exit_reason;
5857                 return 0;
5858         }
5859
5860         if (unlikely(vmx->fail)) {
5861                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5862                 vcpu->run->fail_entry.hardware_entry_failure_reason
5863                         = vmcs_read32(VM_INSTRUCTION_ERROR);
5864                 return 0;
5865         }
5866
5867         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5868                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5869                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
5870                         exit_reason != EXIT_REASON_TASK_SWITCH))
5871                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
5872                        "(0x%x) and exit reason is 0x%x\n",
5873                        __func__, vectoring_info, exit_reason);
5874
5875         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
5876             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
5877                                         get_vmcs12(vcpu), vcpu)))) {
5878                 if (vmx_interrupt_allowed(vcpu)) {
5879                         vmx->soft_vnmi_blocked = 0;
5880                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
5881                            vcpu->arch.nmi_pending) {
5882                         /*
5883                          * This CPU don't support us in finding the end of an
5884                          * NMI-blocked window if the guest runs with IRQs
5885                          * disabled. So we pull the trigger after 1 s of
5886                          * futile waiting, but inform the user about this.
5887                          */
5888                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5889                                "state on VCPU %d after 1 s timeout\n",
5890                                __func__, vcpu->vcpu_id);
5891                         vmx->soft_vnmi_blocked = 0;
5892                 }
5893         }
5894
5895         if (exit_reason < kvm_vmx_max_exit_handlers
5896             && kvm_vmx_exit_handlers[exit_reason])
5897                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5898         else {
5899                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5900                 vcpu->run->hw.hardware_exit_reason = exit_reason;
5901         }
5902         return 0;
5903 }
5904
5905 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5906 {
5907         if (irr == -1 || tpr < irr) {
5908                 vmcs_write32(TPR_THRESHOLD, 0);
5909                 return;
5910         }
5911
5912         vmcs_write32(TPR_THRESHOLD, irr);
5913 }
5914
5915 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
5916 {
5917         u32 exit_intr_info;
5918
5919         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
5920               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
5921                 return;
5922
5923         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5924         exit_intr_info = vmx->exit_intr_info;
5925
5926         /* Handle machine checks before interrupts are enabled */
5927         if (is_machine_check(exit_intr_info))
5928                 kvm_machine_check();
5929
5930         /* We need to handle NMIs before interrupts are enabled */
5931         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
5932             (exit_intr_info & INTR_INFO_VALID_MASK)) {
5933                 kvm_before_handle_nmi(&vmx->vcpu);
5934                 asm("int $2");
5935                 kvm_after_handle_nmi(&vmx->vcpu);
5936         }
5937 }
5938
5939 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
5940 {
5941         u32 exit_intr_info;
5942         bool unblock_nmi;
5943         u8 vector;
5944         bool idtv_info_valid;
5945
5946         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
5947
5948         if (cpu_has_virtual_nmis()) {
5949                 if (vmx->nmi_known_unmasked)
5950                         return;
5951                 /*
5952                  * Can't use vmx->exit_intr_info since we're not sure what
5953                  * the exit reason is.
5954                  */
5955                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5956                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
5957                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
5958                 /*
5959                  * SDM 3: 27.7.1.2 (September 2008)
5960                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
5961                  * a guest IRET fault.
5962                  * SDM 3: 23.2.2 (September 2008)
5963                  * Bit 12 is undefined in any of the following cases:
5964                  *  If the VM exit sets the valid bit in the IDT-vectoring
5965                  *   information field.
5966                  *  If the VM exit is due to a double fault.
5967                  */
5968                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
5969                     vector != DF_VECTOR && !idtv_info_valid)
5970                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5971                                       GUEST_INTR_STATE_NMI);
5972                 else
5973                         vmx->nmi_known_unmasked =
5974                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
5975                                   & GUEST_INTR_STATE_NMI);
5976         } else if (unlikely(vmx->soft_vnmi_blocked))
5977                 vmx->vnmi_blocked_time +=
5978                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
5979 }
5980
5981 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
5982                                       u32 idt_vectoring_info,
5983                                       int instr_len_field,
5984                                       int error_code_field)
5985 {
5986         u8 vector;
5987         int type;
5988         bool idtv_info_valid;
5989
5990         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
5991
5992         vmx->vcpu.arch.nmi_injected = false;
5993         kvm_clear_exception_queue(&vmx->vcpu);
5994         kvm_clear_interrupt_queue(&vmx->vcpu);
5995
5996         if (!idtv_info_valid)
5997                 return;
5998
5999         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6000
6001         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6002         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6003
6004         switch (type) {
6005         case INTR_TYPE_NMI_INTR:
6006                 vmx->vcpu.arch.nmi_injected = true;
6007                 /*
6008                  * SDM 3: 27.7.1.2 (September 2008)
6009                  * Clear bit "block by NMI" before VM entry if a NMI
6010                  * delivery faulted.
6011                  */
6012                 vmx_set_nmi_mask(&vmx->vcpu, false);
6013                 break;
6014         case INTR_TYPE_SOFT_EXCEPTION:
6015                 vmx->vcpu.arch.event_exit_inst_len =
6016                         vmcs_read32(instr_len_field);
6017                 /* fall through */
6018         case INTR_TYPE_HARD_EXCEPTION:
6019                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6020                         u32 err = vmcs_read32(error_code_field);
6021                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
6022                 } else
6023                         kvm_queue_exception(&vmx->vcpu, vector);
6024                 break;
6025         case INTR_TYPE_SOFT_INTR:
6026                 vmx->vcpu.arch.event_exit_inst_len =
6027                         vmcs_read32(instr_len_field);
6028                 /* fall through */
6029         case INTR_TYPE_EXT_INTR:
6030                 kvm_queue_interrupt(&vmx->vcpu, vector,
6031                         type == INTR_TYPE_SOFT_INTR);
6032                 break;
6033         default:
6034                 break;
6035         }
6036 }
6037
6038 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6039 {
6040         if (is_guest_mode(&vmx->vcpu))
6041                 return;
6042         __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6043                                   VM_EXIT_INSTRUCTION_LEN,
6044                                   IDT_VECTORING_ERROR_CODE);
6045 }
6046
6047 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6048 {
6049         if (is_guest_mode(vcpu))
6050                 return;
6051         __vmx_complete_interrupts(to_vmx(vcpu),
6052                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6053                                   VM_ENTRY_INSTRUCTION_LEN,
6054                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6055
6056         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6057 }
6058
6059 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6060 {
6061         int i, nr_msrs;
6062         struct perf_guest_switch_msr *msrs;
6063
6064         msrs = perf_guest_get_msrs(&nr_msrs);
6065
6066         if (!msrs)
6067                 return;
6068
6069         for (i = 0; i < nr_msrs; i++)
6070                 if (msrs[i].host == msrs[i].guest)
6071                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6072                 else
6073                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6074                                         msrs[i].host);
6075 }
6076
6077 #ifdef CONFIG_X86_64
6078 #define R "r"
6079 #define Q "q"
6080 #else
6081 #define R "e"
6082 #define Q "l"
6083 #endif
6084
6085 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6086 {
6087         struct vcpu_vmx *vmx = to_vmx(vcpu);
6088
6089         if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6090                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6091                 if (vmcs12->idt_vectoring_info_field &
6092                                 VECTORING_INFO_VALID_MASK) {
6093                         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6094                                 vmcs12->idt_vectoring_info_field);
6095                         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6096                                 vmcs12->vm_exit_instruction_len);
6097                         if (vmcs12->idt_vectoring_info_field &
6098                                         VECTORING_INFO_DELIVER_CODE_MASK)
6099                                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6100                                         vmcs12->idt_vectoring_error_code);
6101                 }
6102         }
6103
6104         /* Record the guest's net vcpu time for enforced NMI injections. */
6105         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6106                 vmx->entry_time = ktime_get();
6107
6108         /* Don't enter VMX if guest state is invalid, let the exit handler
6109            start emulation until we arrive back to a valid state */
6110         if (vmx->emulation_required && emulate_invalid_guest_state)
6111                 return;
6112
6113         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6114                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6115         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6116                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6117
6118         /* When single-stepping over STI and MOV SS, we must clear the
6119          * corresponding interruptibility bits in the guest state. Otherwise
6120          * vmentry fails as it then expects bit 14 (BS) in pending debug
6121          * exceptions being set, but that's not correct for the guest debugging
6122          * case. */
6123         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6124                 vmx_set_interrupt_shadow(vcpu, 0);
6125
6126         atomic_switch_perf_msrs(vmx);
6127
6128         vmx->__launched = vmx->loaded_vmcs->launched;
6129         asm(
6130                 /* Store host registers */
6131                 "push %%"R"dx; push %%"R"bp;"
6132                 "push %%"R"cx \n\t" /* placeholder for guest rcx */
6133                 "push %%"R"cx \n\t"
6134                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
6135                 "je 1f \n\t"
6136                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
6137                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
6138                 "1: \n\t"
6139                 /* Reload cr2 if changed */
6140                 "mov %c[cr2](%0), %%"R"ax \n\t"
6141                 "mov %%cr2, %%"R"dx \n\t"
6142                 "cmp %%"R"ax, %%"R"dx \n\t"
6143                 "je 2f \n\t"
6144                 "mov %%"R"ax, %%cr2 \n\t"
6145                 "2: \n\t"
6146                 /* Check if vmlaunch of vmresume is needed */
6147                 "cmpl $0, %c[launched](%0) \n\t"
6148                 /* Load guest registers.  Don't clobber flags. */
6149                 "mov %c[rax](%0), %%"R"ax \n\t"
6150                 "mov %c[rbx](%0), %%"R"bx \n\t"
6151                 "mov %c[rdx](%0), %%"R"dx \n\t"
6152                 "mov %c[rsi](%0), %%"R"si \n\t"
6153                 "mov %c[rdi](%0), %%"R"di \n\t"
6154                 "mov %c[rbp](%0), %%"R"bp \n\t"
6155 #ifdef CONFIG_X86_64
6156                 "mov %c[r8](%0),  %%r8  \n\t"
6157                 "mov %c[r9](%0),  %%r9  \n\t"
6158                 "mov %c[r10](%0), %%r10 \n\t"
6159                 "mov %c[r11](%0), %%r11 \n\t"
6160                 "mov %c[r12](%0), %%r12 \n\t"
6161                 "mov %c[r13](%0), %%r13 \n\t"
6162                 "mov %c[r14](%0), %%r14 \n\t"
6163                 "mov %c[r15](%0), %%r15 \n\t"
6164 #endif
6165                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
6166
6167                 /* Enter guest mode */
6168                 "jne .Llaunched \n\t"
6169                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
6170                 "jmp .Lkvm_vmx_return \n\t"
6171                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
6172                 ".Lkvm_vmx_return: "
6173                 /* Save guest registers, load host registers, keep flags */
6174                 "mov %0, %c[wordsize](%%"R"sp) \n\t"
6175                 "pop %0 \n\t"
6176                 "mov %%"R"ax, %c[rax](%0) \n\t"
6177                 "mov %%"R"bx, %c[rbx](%0) \n\t"
6178                 "pop"Q" %c[rcx](%0) \n\t"
6179                 "mov %%"R"dx, %c[rdx](%0) \n\t"
6180                 "mov %%"R"si, %c[rsi](%0) \n\t"
6181                 "mov %%"R"di, %c[rdi](%0) \n\t"
6182                 "mov %%"R"bp, %c[rbp](%0) \n\t"
6183 #ifdef CONFIG_X86_64
6184                 "mov %%r8,  %c[r8](%0) \n\t"
6185                 "mov %%r9,  %c[r9](%0) \n\t"
6186                 "mov %%r10, %c[r10](%0) \n\t"
6187                 "mov %%r11, %c[r11](%0) \n\t"
6188                 "mov %%r12, %c[r12](%0) \n\t"
6189                 "mov %%r13, %c[r13](%0) \n\t"
6190                 "mov %%r14, %c[r14](%0) \n\t"
6191                 "mov %%r15, %c[r15](%0) \n\t"
6192 #endif
6193                 "mov %%cr2, %%"R"ax   \n\t"
6194                 "mov %%"R"ax, %c[cr2](%0) \n\t"
6195
6196                 "pop  %%"R"bp; pop  %%"R"dx \n\t"
6197                 "setbe %c[fail](%0) \n\t"
6198               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
6199                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
6200                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
6201                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
6202                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6203                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6204                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6205                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6206                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6207                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6208                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
6209 #ifdef CONFIG_X86_64
6210                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6211                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6212                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6213                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6214                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6215                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6216                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6217                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6218 #endif
6219                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6220                 [wordsize]"i"(sizeof(ulong))
6221               : "cc", "memory"
6222                 , R"ax", R"bx", R"di", R"si"
6223 #ifdef CONFIG_X86_64
6224                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6225 #endif
6226               );
6227
6228         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6229                                   | (1 << VCPU_EXREG_RFLAGS)
6230                                   | (1 << VCPU_EXREG_CPL)
6231                                   | (1 << VCPU_EXREG_PDPTR)
6232                                   | (1 << VCPU_EXREG_SEGMENTS)
6233                                   | (1 << VCPU_EXREG_CR3));
6234         vcpu->arch.regs_dirty = 0;
6235
6236         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6237
6238         if (is_guest_mode(vcpu)) {
6239                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6240                 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6241                 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6242                         vmcs12->idt_vectoring_error_code =
6243                                 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6244                         vmcs12->vm_exit_instruction_len =
6245                                 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6246                 }
6247         }
6248
6249         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
6250         vmx->loaded_vmcs->launched = 1;
6251
6252         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
6253         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
6254
6255         vmx_complete_atomic_exit(vmx);
6256         vmx_recover_nmi_blocking(vmx);
6257         vmx_complete_interrupts(vmx);
6258 }
6259
6260 #undef R
6261 #undef Q
6262
6263 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6264 {
6265         struct vcpu_vmx *vmx = to_vmx(vcpu);
6266
6267         free_vpid(vmx);
6268         free_nested(vmx);
6269         free_loaded_vmcs(vmx->loaded_vmcs);
6270         kfree(vmx->guest_msrs);
6271         kvm_vcpu_uninit(vcpu);
6272         kmem_cache_free(kvm_vcpu_cache, vmx);
6273 }
6274
6275 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6276 {
6277         int err;
6278         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
6279         int cpu;
6280
6281         if (!vmx)
6282                 return ERR_PTR(-ENOMEM);
6283
6284         allocate_vpid(vmx);
6285
6286         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6287         if (err)
6288                 goto free_vcpu;
6289
6290         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
6291         err = -ENOMEM;
6292         if (!vmx->guest_msrs) {
6293                 goto uninit_vcpu;
6294         }
6295
6296         vmx->loaded_vmcs = &vmx->vmcs01;
6297         vmx->loaded_vmcs->vmcs = alloc_vmcs();
6298         if (!vmx->loaded_vmcs->vmcs)
6299                 goto free_msrs;
6300         if (!vmm_exclusive)
6301                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6302         loaded_vmcs_init(vmx->loaded_vmcs);
6303         if (!vmm_exclusive)
6304                 kvm_cpu_vmxoff();
6305
6306         cpu = get_cpu();
6307         vmx_vcpu_load(&vmx->vcpu, cpu);
6308         vmx->vcpu.cpu = cpu;
6309         err = vmx_vcpu_setup(vmx);
6310         vmx_vcpu_put(&vmx->vcpu);
6311         put_cpu();
6312         if (err)
6313                 goto free_vmcs;
6314         if (vm_need_virtualize_apic_accesses(kvm))
6315                 err = alloc_apic_access_page(kvm);
6316                 if (err)
6317                         goto free_vmcs;
6318
6319         if (enable_ept) {
6320                 if (!kvm->arch.ept_identity_map_addr)
6321                         kvm->arch.ept_identity_map_addr =
6322                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
6323                 err = -ENOMEM;
6324                 if (alloc_identity_pagetable(kvm) != 0)
6325                         goto free_vmcs;
6326                 if (!init_rmode_identity_map(kvm))
6327                         goto free_vmcs;
6328         }
6329
6330         vmx->nested.current_vmptr = -1ull;
6331         vmx->nested.current_vmcs12 = NULL;
6332
6333         return &vmx->vcpu;
6334
6335 free_vmcs:
6336         free_vmcs(vmx->loaded_vmcs->vmcs);
6337 free_msrs:
6338         kfree(vmx->guest_msrs);
6339 uninit_vcpu:
6340         kvm_vcpu_uninit(&vmx->vcpu);
6341 free_vcpu:
6342         free_vpid(vmx);
6343         kmem_cache_free(kvm_vcpu_cache, vmx);
6344         return ERR_PTR(err);
6345 }
6346
6347 static void __init vmx_check_processor_compat(void *rtn)
6348 {
6349         struct vmcs_config vmcs_conf;
6350
6351         *(int *)rtn = 0;
6352         if (setup_vmcs_config(&vmcs_conf) < 0)
6353                 *(int *)rtn = -EIO;
6354         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6355                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6356                                 smp_processor_id());
6357                 *(int *)rtn = -EIO;
6358         }
6359 }
6360
6361 static int get_ept_level(void)
6362 {
6363         return VMX_EPT_DEFAULT_GAW + 1;
6364 }
6365
6366 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6367 {
6368         u64 ret;
6369
6370         /* For VT-d and EPT combination
6371          * 1. MMIO: always map as UC
6372          * 2. EPT with VT-d:
6373          *   a. VT-d without snooping control feature: can't guarantee the
6374          *      result, try to trust guest.
6375          *   b. VT-d with snooping control feature: snooping control feature of
6376          *      VT-d engine can guarantee the cache correctness. Just set it
6377          *      to WB to keep consistent with host. So the same as item 3.
6378          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6379          *    consistent with host MTRR
6380          */
6381         if (is_mmio)
6382                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
6383         else if (vcpu->kvm->arch.iommu_domain &&
6384                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6385                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6386                       VMX_EPT_MT_EPTE_SHIFT;
6387         else
6388                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
6389                         | VMX_EPT_IPAT_BIT;
6390
6391         return ret;
6392 }
6393
6394 static int vmx_get_lpage_level(void)
6395 {
6396         if (enable_ept && !cpu_has_vmx_ept_1g_page())
6397                 return PT_DIRECTORY_LEVEL;
6398         else
6399                 /* For shadow and EPT supported 1GB page */
6400                 return PT_PDPE_LEVEL;
6401 }
6402
6403 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6404 {
6405         struct kvm_cpuid_entry2 *best;
6406         struct vcpu_vmx *vmx = to_vmx(vcpu);
6407         u32 exec_control;
6408
6409         vmx->rdtscp_enabled = false;
6410         if (vmx_rdtscp_supported()) {
6411                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6412                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6413                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6414                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6415                                 vmx->rdtscp_enabled = true;
6416                         else {
6417                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6418                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6419                                                 exec_control);
6420                         }
6421                 }
6422         }
6423 }
6424
6425 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6426 {
6427         if (func == 1 && nested)
6428                 entry->ecx |= bit(X86_FEATURE_VMX);
6429 }
6430
6431 /*
6432  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6433  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6434  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6435  * guest in a way that will both be appropriate to L1's requests, and our
6436  * needs. In addition to modifying the active vmcs (which is vmcs02), this
6437  * function also has additional necessary side-effects, like setting various
6438  * vcpu->arch fields.
6439  */
6440 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6441 {
6442         struct vcpu_vmx *vmx = to_vmx(vcpu);
6443         u32 exec_control;
6444
6445         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6446         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6447         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6448         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6449         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6450         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6451         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6452         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6453         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6454         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6455         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6456         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6457         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6458         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6459         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6460         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6461         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6462         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6463         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6464         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6465         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6466         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6467         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6468         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6469         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6470         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6471         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6472         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6473         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6474         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6475         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6476         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6477         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6478         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6479         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6480         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6481
6482         vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6483         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6484                 vmcs12->vm_entry_intr_info_field);
6485         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6486                 vmcs12->vm_entry_exception_error_code);
6487         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6488                 vmcs12->vm_entry_instruction_len);
6489         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6490                 vmcs12->guest_interruptibility_info);
6491         vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6492         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6493         vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6494         vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6495         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6496                 vmcs12->guest_pending_dbg_exceptions);
6497         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6498         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6499
6500         vmcs_write64(VMCS_LINK_POINTER, -1ull);
6501
6502         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6503                 (vmcs_config.pin_based_exec_ctrl |
6504                  vmcs12->pin_based_vm_exec_control));
6505
6506         /*
6507          * Whether page-faults are trapped is determined by a combination of
6508          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6509          * If enable_ept, L0 doesn't care about page faults and we should
6510          * set all of these to L1's desires. However, if !enable_ept, L0 does
6511          * care about (at least some) page faults, and because it is not easy
6512          * (if at all possible?) to merge L0 and L1's desires, we simply ask
6513          * to exit on each and every L2 page fault. This is done by setting
6514          * MASK=MATCH=0 and (see below) EB.PF=1.
6515          * Note that below we don't need special code to set EB.PF beyond the
6516          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6517          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6518          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6519          *
6520          * A problem with this approach (when !enable_ept) is that L1 may be
6521          * injected with more page faults than it asked for. This could have
6522          * caused problems, but in practice existing hypervisors don't care.
6523          * To fix this, we will need to emulate the PFEC checking (on the L1
6524          * page tables), using walk_addr(), when injecting PFs to L1.
6525          */
6526         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6527                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6528         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6529                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6530
6531         if (cpu_has_secondary_exec_ctrls()) {
6532                 u32 exec_control = vmx_secondary_exec_control(vmx);
6533                 if (!vmx->rdtscp_enabled)
6534                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
6535                 /* Take the following fields only from vmcs12 */
6536                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6537                 if (nested_cpu_has(vmcs12,
6538                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6539                         exec_control |= vmcs12->secondary_vm_exec_control;
6540
6541                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6542                         /*
6543                          * Translate L1 physical address to host physical
6544                          * address for vmcs02. Keep the page pinned, so this
6545                          * physical address remains valid. We keep a reference
6546                          * to it so we can release it later.
6547                          */
6548                         if (vmx->nested.apic_access_page) /* shouldn't happen */
6549                                 nested_release_page(vmx->nested.apic_access_page);
6550                         vmx->nested.apic_access_page =
6551                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
6552                         /*
6553                          * If translation failed, no matter: This feature asks
6554                          * to exit when accessing the given address, and if it
6555                          * can never be accessed, this feature won't do
6556                          * anything anyway.
6557                          */
6558                         if (!vmx->nested.apic_access_page)
6559                                 exec_control &=
6560                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6561                         else
6562                                 vmcs_write64(APIC_ACCESS_ADDR,
6563                                   page_to_phys(vmx->nested.apic_access_page));
6564                 }
6565
6566                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6567         }
6568
6569
6570         /*
6571          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6572          * Some constant fields are set here by vmx_set_constant_host_state().
6573          * Other fields are different per CPU, and will be set later when
6574          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6575          */
6576         vmx_set_constant_host_state();
6577
6578         /*
6579          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6580          * entry, but only if the current (host) sp changed from the value
6581          * we wrote last (vmx->host_rsp). This cache is no longer relevant
6582          * if we switch vmcs, and rather than hold a separate cache per vmcs,
6583          * here we just force the write to happen on entry.
6584          */
6585         vmx->host_rsp = 0;
6586
6587         exec_control = vmx_exec_control(vmx); /* L0's desires */
6588         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6589         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6590         exec_control &= ~CPU_BASED_TPR_SHADOW;
6591         exec_control |= vmcs12->cpu_based_vm_exec_control;
6592         /*
6593          * Merging of IO and MSR bitmaps not currently supported.
6594          * Rather, exit every time.
6595          */
6596         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6597         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6598         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6599
6600         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6601
6602         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6603          * bitwise-or of what L1 wants to trap for L2, and what we want to
6604          * trap. Note that CR0.TS also needs updating - we do this later.
6605          */
6606         update_exception_bitmap(vcpu);
6607         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6608         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6609
6610         /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6611         vmcs_write32(VM_EXIT_CONTROLS,
6612                 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6613         vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6614                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6615
6616         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6617                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6618         else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6619                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6620
6621
6622         set_cr4_guest_host_mask(vmx);
6623
6624         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6625                 vmcs_write64(TSC_OFFSET,
6626                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6627         else
6628                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
6629
6630         if (enable_vpid) {
6631                 /*
6632                  * Trivially support vpid by letting L2s share their parent
6633                  * L1's vpid. TODO: move to a more elaborate solution, giving
6634                  * each L2 its own vpid and exposing the vpid feature to L1.
6635                  */
6636                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6637                 vmx_flush_tlb(vcpu);
6638         }
6639
6640         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6641                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6642         if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6643                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6644         else
6645                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6646         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6647         vmx_set_efer(vcpu, vcpu->arch.efer);
6648
6649         /*
6650          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6651          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6652          * The CR0_READ_SHADOW is what L2 should have expected to read given
6653          * the specifications by L1; It's not enough to take
6654          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6655          * have more bits than L1 expected.
6656          */
6657         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6658         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6659
6660         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6661         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6662
6663         /* shadow page tables on either EPT or shadow page tables */
6664         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6665         kvm_mmu_reset_context(vcpu);
6666
6667         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6668         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6669 }
6670
6671 /*
6672  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6673  * for running an L2 nested guest.
6674  */
6675 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6676 {
6677         struct vmcs12 *vmcs12;
6678         struct vcpu_vmx *vmx = to_vmx(vcpu);
6679         int cpu;
6680         struct loaded_vmcs *vmcs02;
6681
6682         if (!nested_vmx_check_permission(vcpu) ||
6683             !nested_vmx_check_vmcs12(vcpu))
6684                 return 1;
6685
6686         skip_emulated_instruction(vcpu);
6687         vmcs12 = get_vmcs12(vcpu);
6688
6689         /*
6690          * The nested entry process starts with enforcing various prerequisites
6691          * on vmcs12 as required by the Intel SDM, and act appropriately when
6692          * they fail: As the SDM explains, some conditions should cause the
6693          * instruction to fail, while others will cause the instruction to seem
6694          * to succeed, but return an EXIT_REASON_INVALID_STATE.
6695          * To speed up the normal (success) code path, we should avoid checking
6696          * for misconfigurations which will anyway be caught by the processor
6697          * when using the merged vmcs02.
6698          */
6699         if (vmcs12->launch_state == launch) {
6700                 nested_vmx_failValid(vcpu,
6701                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6702                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6703                 return 1;
6704         }
6705
6706         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6707                         !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6708                 /*TODO: Also verify bits beyond physical address width are 0*/
6709                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6710                 return 1;
6711         }
6712
6713         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6714                         !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6715                 /*TODO: Also verify bits beyond physical address width are 0*/
6716                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6717                 return 1;
6718         }
6719
6720         if (vmcs12->vm_entry_msr_load_count > 0 ||
6721             vmcs12->vm_exit_msr_load_count > 0 ||
6722             vmcs12->vm_exit_msr_store_count > 0) {
6723                 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6724                                     __func__);
6725                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6726                 return 1;
6727         }
6728
6729         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6730               nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6731             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6732               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6733             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6734               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6735             !vmx_control_verify(vmcs12->vm_exit_controls,
6736               nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6737             !vmx_control_verify(vmcs12->vm_entry_controls,
6738               nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6739         {
6740                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6741                 return 1;
6742         }
6743
6744         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6745             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6746                 nested_vmx_failValid(vcpu,
6747                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6748                 return 1;
6749         }
6750
6751         if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6752             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6753                 nested_vmx_entry_failure(vcpu, vmcs12,
6754                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6755                 return 1;
6756         }
6757         if (vmcs12->vmcs_link_pointer != -1ull) {
6758                 nested_vmx_entry_failure(vcpu, vmcs12,
6759                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6760                 return 1;
6761         }
6762
6763         /*
6764          * We're finally done with prerequisite checking, and can start with
6765          * the nested entry.
6766          */
6767
6768         vmcs02 = nested_get_current_vmcs02(vmx);
6769         if (!vmcs02)
6770                 return -ENOMEM;
6771
6772         enter_guest_mode(vcpu);
6773
6774         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6775
6776         cpu = get_cpu();
6777         vmx->loaded_vmcs = vmcs02;
6778         vmx_vcpu_put(vcpu);
6779         vmx_vcpu_load(vcpu, cpu);
6780         vcpu->cpu = cpu;
6781         put_cpu();
6782
6783         vmcs12->launch_state = 1;
6784
6785         prepare_vmcs02(vcpu, vmcs12);
6786
6787         /*
6788          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6789          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6790          * returned as far as L1 is concerned. It will only return (and set
6791          * the success flag) when L2 exits (see nested_vmx_vmexit()).
6792          */
6793         return 1;
6794 }
6795
6796 /*
6797  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6798  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6799  * This function returns the new value we should put in vmcs12.guest_cr0.
6800  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6801  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6802  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6803  *     didn't trap the bit, because if L1 did, so would L0).
6804  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6805  *     been modified by L2, and L1 knows it. So just leave the old value of
6806  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6807  *     isn't relevant, because if L0 traps this bit it can set it to anything.
6808  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6809  *     changed these bits, and therefore they need to be updated, but L0
6810  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6811  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6812  */
6813 static inline unsigned long
6814 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6815 {
6816         return
6817         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6818         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6819         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6820                         vcpu->arch.cr0_guest_owned_bits));
6821 }
6822
6823 static inline unsigned long
6824 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6825 {
6826         return
6827         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
6828         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
6829         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
6830                         vcpu->arch.cr4_guest_owned_bits));
6831 }
6832
6833 /*
6834  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6835  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6836  * and this function updates it to reflect the changes to the guest state while
6837  * L2 was running (and perhaps made some exits which were handled directly by L0
6838  * without going back to L1), and to reflect the exit reason.
6839  * Note that we do not have to copy here all VMCS fields, just those that
6840  * could have changed by the L2 guest or the exit - i.e., the guest-state and
6841  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
6842  * which already writes to vmcs12 directly.
6843  */
6844 void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6845 {
6846         /* update guest state fields: */
6847         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
6848         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
6849
6850         kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
6851         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6852         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
6853         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
6854
6855         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
6856         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
6857         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
6858         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
6859         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
6860         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
6861         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
6862         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
6863         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
6864         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
6865         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
6866         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
6867         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
6868         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
6869         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
6870         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
6871         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
6872         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
6873         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
6874         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
6875         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
6876         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
6877         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
6878         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
6879         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
6880         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
6881         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
6882         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
6883         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
6884         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
6885         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
6886         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
6887         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
6888         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
6889         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
6890         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
6891
6892         vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
6893         vmcs12->guest_interruptibility_info =
6894                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
6895         vmcs12->guest_pending_dbg_exceptions =
6896                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
6897
6898         /* TODO: These cannot have changed unless we have MSR bitmaps and
6899          * the relevant bit asks not to trap the change */
6900         vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
6901         if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
6902                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
6903         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
6904         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
6905         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
6906
6907         /* update exit information fields: */
6908
6909         vmcs12->vm_exit_reason  = vmcs_read32(VM_EXIT_REASON);
6910         vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6911
6912         vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6913         vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6914         vmcs12->idt_vectoring_info_field =
6915                 vmcs_read32(IDT_VECTORING_INFO_FIELD);
6916         vmcs12->idt_vectoring_error_code =
6917                 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6918         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6919         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6920
6921         /* clear vm-entry fields which are to be cleared on exit */
6922         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6923                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
6924 }
6925
6926 /*
6927  * A part of what we need to when the nested L2 guest exits and we want to
6928  * run its L1 parent, is to reset L1's guest state to the host state specified
6929  * in vmcs12.
6930  * This function is to be called not only on normal nested exit, but also on
6931  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
6932  * Failures During or After Loading Guest State").
6933  * This function should be called when the active VMCS is L1's (vmcs01).
6934  */
6935 void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6936 {
6937         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
6938                 vcpu->arch.efer = vmcs12->host_ia32_efer;
6939         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
6940                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6941         else
6942                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6943         vmx_set_efer(vcpu, vcpu->arch.efer);
6944
6945         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
6946         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
6947         /*
6948          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
6949          * actually changed, because it depends on the current state of
6950          * fpu_active (which may have changed).
6951          * Note that vmx_set_cr0 refers to efer set above.
6952          */
6953         kvm_set_cr0(vcpu, vmcs12->host_cr0);
6954         /*
6955          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
6956          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
6957          * but we also need to update cr0_guest_host_mask and exception_bitmap.
6958          */
6959         update_exception_bitmap(vcpu);
6960         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
6961         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6962
6963         /*
6964          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
6965          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
6966          */
6967         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
6968         kvm_set_cr4(vcpu, vmcs12->host_cr4);
6969
6970         /* shadow page tables on either EPT or shadow page tables */
6971         kvm_set_cr3(vcpu, vmcs12->host_cr3);
6972         kvm_mmu_reset_context(vcpu);
6973
6974         if (enable_vpid) {
6975                 /*
6976                  * Trivially support vpid by letting L2s share their parent
6977                  * L1's vpid. TODO: move to a more elaborate solution, giving
6978                  * each L2 its own vpid and exposing the vpid feature to L1.
6979                  */
6980                 vmx_flush_tlb(vcpu);
6981         }
6982
6983
6984         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
6985         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
6986         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
6987         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
6988         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
6989         vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
6990         vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
6991         vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
6992         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
6993         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
6994         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
6995         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
6996         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
6997         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
6998         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
6999
7000         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7001                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7002         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7003                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7004                         vmcs12->host_ia32_perf_global_ctrl);
7005 }
7006
7007 /*
7008  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7009  * and modify vmcs12 to make it see what it would expect to see there if
7010  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7011  */
7012 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7013 {
7014         struct vcpu_vmx *vmx = to_vmx(vcpu);
7015         int cpu;
7016         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7017
7018         leave_guest_mode(vcpu);
7019         prepare_vmcs12(vcpu, vmcs12);
7020
7021         cpu = get_cpu();
7022         vmx->loaded_vmcs = &vmx->vmcs01;
7023         vmx_vcpu_put(vcpu);
7024         vmx_vcpu_load(vcpu, cpu);
7025         vcpu->cpu = cpu;
7026         put_cpu();
7027
7028         /* if no vmcs02 cache requested, remove the one we used */
7029         if (VMCS02_POOL_SIZE == 0)
7030                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7031
7032         load_vmcs12_host_state(vcpu, vmcs12);
7033
7034         /* Update TSC_OFFSET if TSC was changed while L2 ran */
7035         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7036
7037         /* This is needed for same reason as it was needed in prepare_vmcs02 */
7038         vmx->host_rsp = 0;
7039
7040         /* Unpin physical memory we referred to in vmcs02 */
7041         if (vmx->nested.apic_access_page) {
7042                 nested_release_page(vmx->nested.apic_access_page);
7043                 vmx->nested.apic_access_page = 0;
7044         }
7045
7046         /*
7047          * Exiting from L2 to L1, we're now back to L1 which thinks it just
7048          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7049          * success or failure flag accordingly.
7050          */
7051         if (unlikely(vmx->fail)) {
7052                 vmx->fail = 0;
7053                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7054         } else
7055                 nested_vmx_succeed(vcpu);
7056 }
7057
7058 /*
7059  * L1's failure to enter L2 is a subset of a normal exit, as explained in
7060  * 23.7 "VM-entry failures during or after loading guest state" (this also
7061  * lists the acceptable exit-reason and exit-qualification parameters).
7062  * It should only be called before L2 actually succeeded to run, and when
7063  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7064  */
7065 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7066                         struct vmcs12 *vmcs12,
7067                         u32 reason, unsigned long qualification)
7068 {
7069         load_vmcs12_host_state(vcpu, vmcs12);
7070         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7071         vmcs12->exit_qualification = qualification;
7072         nested_vmx_succeed(vcpu);
7073 }
7074
7075 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7076                                struct x86_instruction_info *info,
7077                                enum x86_intercept_stage stage)
7078 {
7079         return X86EMUL_CONTINUE;
7080 }
7081
7082 static struct kvm_x86_ops vmx_x86_ops = {
7083         .cpu_has_kvm_support = cpu_has_kvm_support,
7084         .disabled_by_bios = vmx_disabled_by_bios,
7085         .hardware_setup = hardware_setup,
7086         .hardware_unsetup = hardware_unsetup,
7087         .check_processor_compatibility = vmx_check_processor_compat,
7088         .hardware_enable = hardware_enable,
7089         .hardware_disable = hardware_disable,
7090         .cpu_has_accelerated_tpr = report_flexpriority,
7091
7092         .vcpu_create = vmx_create_vcpu,
7093         .vcpu_free = vmx_free_vcpu,
7094         .vcpu_reset = vmx_vcpu_reset,
7095
7096         .prepare_guest_switch = vmx_save_host_state,
7097         .vcpu_load = vmx_vcpu_load,
7098         .vcpu_put = vmx_vcpu_put,
7099
7100         .set_guest_debug = set_guest_debug,
7101         .get_msr = vmx_get_msr,
7102         .set_msr = vmx_set_msr,
7103         .get_segment_base = vmx_get_segment_base,
7104         .get_segment = vmx_get_segment,
7105         .set_segment = vmx_set_segment,
7106         .get_cpl = vmx_get_cpl,
7107         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7108         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7109         .decache_cr3 = vmx_decache_cr3,
7110         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7111         .set_cr0 = vmx_set_cr0,
7112         .set_cr3 = vmx_set_cr3,
7113         .set_cr4 = vmx_set_cr4,
7114         .set_efer = vmx_set_efer,
7115         .get_idt = vmx_get_idt,
7116         .set_idt = vmx_set_idt,
7117         .get_gdt = vmx_get_gdt,
7118         .set_gdt = vmx_set_gdt,
7119         .set_dr7 = vmx_set_dr7,
7120         .cache_reg = vmx_cache_reg,
7121         .get_rflags = vmx_get_rflags,
7122         .set_rflags = vmx_set_rflags,
7123         .fpu_activate = vmx_fpu_activate,
7124         .fpu_deactivate = vmx_fpu_deactivate,
7125
7126         .tlb_flush = vmx_flush_tlb,
7127
7128         .run = vmx_vcpu_run,
7129         .handle_exit = vmx_handle_exit,
7130         .skip_emulated_instruction = skip_emulated_instruction,
7131         .set_interrupt_shadow = vmx_set_interrupt_shadow,
7132         .get_interrupt_shadow = vmx_get_interrupt_shadow,
7133         .patch_hypercall = vmx_patch_hypercall,
7134         .set_irq = vmx_inject_irq,
7135         .set_nmi = vmx_inject_nmi,
7136         .queue_exception = vmx_queue_exception,
7137         .cancel_injection = vmx_cancel_injection,
7138         .interrupt_allowed = vmx_interrupt_allowed,
7139         .nmi_allowed = vmx_nmi_allowed,
7140         .get_nmi_mask = vmx_get_nmi_mask,
7141         .set_nmi_mask = vmx_set_nmi_mask,
7142         .enable_nmi_window = enable_nmi_window,
7143         .enable_irq_window = enable_irq_window,
7144         .update_cr8_intercept = update_cr8_intercept,
7145
7146         .set_tss_addr = vmx_set_tss_addr,
7147         .get_tdp_level = get_ept_level,
7148         .get_mt_mask = vmx_get_mt_mask,
7149
7150         .get_exit_info = vmx_get_exit_info,
7151
7152         .get_lpage_level = vmx_get_lpage_level,
7153
7154         .cpuid_update = vmx_cpuid_update,
7155
7156         .rdtscp_supported = vmx_rdtscp_supported,
7157
7158         .set_supported_cpuid = vmx_set_supported_cpuid,
7159
7160         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7161
7162         .set_tsc_khz = vmx_set_tsc_khz,
7163         .write_tsc_offset = vmx_write_tsc_offset,
7164         .adjust_tsc_offset = vmx_adjust_tsc_offset,
7165         .compute_tsc_offset = vmx_compute_tsc_offset,
7166         .read_l1_tsc = vmx_read_l1_tsc,
7167
7168         .set_tdp_cr3 = vmx_set_cr3,
7169
7170         .check_intercept = vmx_check_intercept,
7171 };
7172
7173 static int __init vmx_init(void)
7174 {
7175         int r, i;
7176
7177         rdmsrl_safe(MSR_EFER, &host_efer);
7178
7179         for (i = 0; i < NR_VMX_MSR; ++i)
7180                 kvm_define_shared_msr(i, vmx_msr_index[i]);
7181
7182         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
7183         if (!vmx_io_bitmap_a)
7184                 return -ENOMEM;
7185
7186         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
7187         if (!vmx_io_bitmap_b) {
7188                 r = -ENOMEM;
7189                 goto out;
7190         }
7191
7192         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
7193         if (!vmx_msr_bitmap_legacy) {
7194                 r = -ENOMEM;
7195                 goto out1;
7196         }
7197
7198         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
7199         if (!vmx_msr_bitmap_longmode) {
7200                 r = -ENOMEM;
7201                 goto out2;
7202         }
7203
7204         /*
7205          * Allow direct access to the PC debug port (it is often used for I/O
7206          * delays, but the vmexits simply slow things down).
7207          */
7208         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7209         clear_bit(0x80, vmx_io_bitmap_a);
7210
7211         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
7212
7213         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7214         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
7215
7216         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7217
7218         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7219                      __alignof__(struct vcpu_vmx), THIS_MODULE);
7220         if (r)
7221                 goto out3;
7222
7223         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7224         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7225         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7226         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7227         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7228         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
7229
7230         if (enable_ept) {
7231                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
7232                                 VMX_EPT_EXECUTABLE_MASK);
7233                 ept_set_mmio_spte_mask();
7234                 kvm_enable_tdp();
7235         } else
7236                 kvm_disable_tdp();
7237
7238         return 0;
7239
7240 out3:
7241         free_page((unsigned long)vmx_msr_bitmap_longmode);
7242 out2:
7243         free_page((unsigned long)vmx_msr_bitmap_legacy);
7244 out1:
7245         free_page((unsigned long)vmx_io_bitmap_b);
7246 out:
7247         free_page((unsigned long)vmx_io_bitmap_a);
7248         return r;
7249 }
7250
7251 static void __exit vmx_exit(void)
7252 {
7253         free_page((unsigned long)vmx_msr_bitmap_legacy);
7254         free_page((unsigned long)vmx_msr_bitmap_longmode);
7255         free_page((unsigned long)vmx_io_bitmap_b);
7256         free_page((unsigned long)vmx_io_bitmap_a);
7257
7258         kvm_exit();
7259 }
7260
7261 module_init(vmx_init)
7262 module_exit(vmx_exit)