arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include "kvm_cache_regs.h"
  37 #include "x86.h"
  38
  39 #include <asm/cpu.h>
  40 #include <asm/io.h>
  41 #include <asm/desc.h>
  42 #include <asm/vmx.h>
  43 #include <asm/virtext.h>
  44 #include <asm/mce.h>
  45 #include <asm/fpu/internal.h>
  46 #include <asm/perf_event.h>
  47 #include <asm/debugreg.h>
  48 #include <asm/kexec.h>
  49 #include <asm/apic.h>
  50 #include <asm/irq_remapping.h>
  51
  52 #include "trace.h"
  53 #include "pmu.h"
  54
  55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  56 #define __ex_clear(x, reg) \
  57         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  58
  59 MODULE_AUTHOR("Qumranet");
  60 MODULE_LICENSE("GPL");
  61
  62 static const struct x86_cpu_id vmx_cpu_id[] = {
  63         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  64         {}
  65 };
  66 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  67
  68 static bool __read_mostly enable_vpid = 1;
  69 module_param_named(vpid, enable_vpid, bool, 0444);
  70
  71 static bool __read_mostly flexpriority_enabled = 1;
  72 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  73
  74 static bool __read_mostly enable_ept = 1;
  75 module_param_named(ept, enable_ept, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_unrestricted_guest = 1;
  78 module_param_named(unrestricted_guest,
  79                         enable_unrestricted_guest, bool, S_IRUGO);
  80
  81 static bool __read_mostly enable_ept_ad_bits = 1;
  82 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  83
  84 static bool __read_mostly emulate_invalid_guest_state = true;
  85 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  86
  87 static bool __read_mostly vmm_exclusive = 1;
  88 module_param(vmm_exclusive, bool, S_IRUGO);
  89
  90 static bool __read_mostly fasteoi = 1;
  91 module_param(fasteoi, bool, S_IRUGO);
  92
  93 static bool __read_mostly enable_apicv = 1;
  94 module_param(enable_apicv, bool, S_IRUGO);
  95
  96 static bool __read_mostly enable_shadow_vmcs = 1;
  97 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  98 /*
  99  * If nested=1, nested virtualization is supported, i.e., guests may use
 100  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 101  * use VMX instructions.
 102  */
 103 static bool __read_mostly nested = 0;
 104 module_param(nested, bool, S_IRUGO);
 105
 106 static u64 __read_mostly host_xss;
 107
 108 static bool __read_mostly enable_pml = 1;
 109 module_param_named(pml, enable_pml, bool, S_IRUGO);
 110
 111 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 112
 113 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 114 static int __read_mostly cpu_preemption_timer_multi;
 115 static bool __read_mostly enable_preemption_timer = 1;
 116 #ifdef CONFIG_X86_64
 117 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 118 #endif
 119
 120 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 121 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 122 #define KVM_VM_CR0_ALWAYS_ON                                            \
 123         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 124 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 125         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 126          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 127
 128 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 129 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 130
 131 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 132
 133 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 134
 135 /*
 136  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 137  * ple_gap:    upper bound on the amount of time between two successive
 138  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 139  *             According to test, this time is usually smaller than 128 cycles.
 140  * ple_window: upper bound on the amount of time a guest is allowed to execute
 141  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 142  *             less than 2^12 cycles
 143  * Time is measured based on a counter that runs at the same rate as the TSC,
 144  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 145  */
 146 #define KVM_VMX_DEFAULT_PLE_GAP           128
 147 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 148 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 149 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 150 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 151                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 152
 153 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 154 module_param(ple_gap, int, S_IRUGO);
 155
 156 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 157 module_param(ple_window, int, S_IRUGO);
 158
 159 /* Default doubles per-vcpu window every exit. */
 160 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 161 module_param(ple_window_grow, int, S_IRUGO);
 162
 163 /* Default resets per-vcpu window every exit to ple_window. */
 164 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 165 module_param(ple_window_shrink, int, S_IRUGO);
 166
 167 /* Default is to compute the maximum so we can never overflow. */
 168 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 169 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 170 module_param(ple_window_max, int, S_IRUGO);
 171
 172 extern const ulong vmx_return;
 173
 174 #define NR_AUTOLOAD_MSRS 8
 175 #define VMCS02_POOL_SIZE 1
 176
 177 struct vmcs {
 178         u32 revision_id;
 179         u32 abort;
 180         char data[0];
 181 };
 182
 183 /*
 184  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 185  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 186  * loaded on this CPU (so we can clear them if the CPU goes down).
 187  */
 188 struct loaded_vmcs {
 189         struct vmcs *vmcs;
 190         int cpu;
 191         int launched;
 192         struct list_head loaded_vmcss_on_cpu_link;
 193 };
 194
 195 struct shared_msr_entry {
 196         unsigned index;
 197         u64 data;
 198         u64 mask;
 199 };
 200
 201 /*
 202  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 203  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 204  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 205  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 206  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 207  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 208  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 209  * underlying hardware which will be used to run L2.
 210  * This structure is packed to ensure that its layout is identical across
 211  * machines (necessary for live migration).
 212  * If there are changes in this struct, VMCS12_REVISION must be changed.
 213  */
 214 typedef u64 natural_width;
 215 struct __packed vmcs12 {
 216         /* According to the Intel spec, a VMCS region must start with the
 217          * following two fields. Then follow implementation-specific data.
 218          */
 219         u32 revision_id;
 220         u32 abort;
 221
 222         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 223         u32 padding[7]; /* room for future expansion */
 224
 225         u64 io_bitmap_a;
 226         u64 io_bitmap_b;
 227         u64 msr_bitmap;
 228         u64 vm_exit_msr_store_addr;
 229         u64 vm_exit_msr_load_addr;
 230         u64 vm_entry_msr_load_addr;
 231         u64 tsc_offset;
 232         u64 virtual_apic_page_addr;
 233         u64 apic_access_addr;
 234         u64 posted_intr_desc_addr;
 235         u64 ept_pointer;
 236         u64 eoi_exit_bitmap0;
 237         u64 eoi_exit_bitmap1;
 238         u64 eoi_exit_bitmap2;
 239         u64 eoi_exit_bitmap3;
 240         u64 xss_exit_bitmap;
 241         u64 guest_physical_address;
 242         u64 vmcs_link_pointer;
 243         u64 guest_ia32_debugctl;
 244         u64 guest_ia32_pat;
 245         u64 guest_ia32_efer;
 246         u64 guest_ia32_perf_global_ctrl;
 247         u64 guest_pdptr0;
 248         u64 guest_pdptr1;
 249         u64 guest_pdptr2;
 250         u64 guest_pdptr3;
 251         u64 guest_bndcfgs;
 252         u64 host_ia32_pat;
 253         u64 host_ia32_efer;
 254         u64 host_ia32_perf_global_ctrl;
 255         u64 padding64[8]; /* room for future expansion */
 256         /*
 257          * To allow migration of L1 (complete with its L2 guests) between
 258          * machines of different natural widths (32 or 64 bit), we cannot have
 259          * unsigned long fields with no explict size. We use u64 (aliased
 260          * natural_width) instead. Luckily, x86 is little-endian.
 261          */
 262         natural_width cr0_guest_host_mask;
 263         natural_width cr4_guest_host_mask;
 264         natural_width cr0_read_shadow;
 265         natural_width cr4_read_shadow;
 266         natural_width cr3_target_value0;
 267         natural_width cr3_target_value1;
 268         natural_width cr3_target_value2;
 269         natural_width cr3_target_value3;
 270         natural_width exit_qualification;
 271         natural_width guest_linear_address;
 272         natural_width guest_cr0;
 273         natural_width guest_cr3;
 274         natural_width guest_cr4;
 275         natural_width guest_es_base;
 276         natural_width guest_cs_base;
 277         natural_width guest_ss_base;
 278         natural_width guest_ds_base;
 279         natural_width guest_fs_base;
 280         natural_width guest_gs_base;
 281         natural_width guest_ldtr_base;
 282         natural_width guest_tr_base;
 283         natural_width guest_gdtr_base;
 284         natural_width guest_idtr_base;
 285         natural_width guest_dr7;
 286         natural_width guest_rsp;
 287         natural_width guest_rip;
 288         natural_width guest_rflags;
 289         natural_width guest_pending_dbg_exceptions;
 290         natural_width guest_sysenter_esp;
 291         natural_width guest_sysenter_eip;
 292         natural_width host_cr0;
 293         natural_width host_cr3;
 294         natural_width host_cr4;
 295         natural_width host_fs_base;
 296         natural_width host_gs_base;
 297         natural_width host_tr_base;
 298         natural_width host_gdtr_base;
 299         natural_width host_idtr_base;
 300         natural_width host_ia32_sysenter_esp;
 301         natural_width host_ia32_sysenter_eip;
 302         natural_width host_rsp;
 303         natural_width host_rip;
 304         natural_width paddingl[8]; /* room for future expansion */
 305         u32 pin_based_vm_exec_control;
 306         u32 cpu_based_vm_exec_control;
 307         u32 exception_bitmap;
 308         u32 page_fault_error_code_mask;
 309         u32 page_fault_error_code_match;
 310         u32 cr3_target_count;
 311         u32 vm_exit_controls;
 312         u32 vm_exit_msr_store_count;
 313         u32 vm_exit_msr_load_count;
 314         u32 vm_entry_controls;
 315         u32 vm_entry_msr_load_count;
 316         u32 vm_entry_intr_info_field;
 317         u32 vm_entry_exception_error_code;
 318         u32 vm_entry_instruction_len;
 319         u32 tpr_threshold;
 320         u32 secondary_vm_exec_control;
 321         u32 vm_instruction_error;
 322         u32 vm_exit_reason;
 323         u32 vm_exit_intr_info;
 324         u32 vm_exit_intr_error_code;
 325         u32 idt_vectoring_info_field;
 326         u32 idt_vectoring_error_code;
 327         u32 vm_exit_instruction_len;
 328         u32 vmx_instruction_info;
 329         u32 guest_es_limit;
 330         u32 guest_cs_limit;
 331         u32 guest_ss_limit;
 332         u32 guest_ds_limit;
 333         u32 guest_fs_limit;
 334         u32 guest_gs_limit;
 335         u32 guest_ldtr_limit;
 336         u32 guest_tr_limit;
 337         u32 guest_gdtr_limit;
 338         u32 guest_idtr_limit;
 339         u32 guest_es_ar_bytes;
 340         u32 guest_cs_ar_bytes;
 341         u32 guest_ss_ar_bytes;
 342         u32 guest_ds_ar_bytes;
 343         u32 guest_fs_ar_bytes;
 344         u32 guest_gs_ar_bytes;
 345         u32 guest_ldtr_ar_bytes;
 346         u32 guest_tr_ar_bytes;
 347         u32 guest_interruptibility_info;
 348         u32 guest_activity_state;
 349         u32 guest_sysenter_cs;
 350         u32 host_ia32_sysenter_cs;
 351         u32 vmx_preemption_timer_value;
 352         u32 padding32[7]; /* room for future expansion */
 353         u16 virtual_processor_id;
 354         u16 posted_intr_nv;
 355         u16 guest_es_selector;
 356         u16 guest_cs_selector;
 357         u16 guest_ss_selector;
 358         u16 guest_ds_selector;
 359         u16 guest_fs_selector;
 360         u16 guest_gs_selector;
 361         u16 guest_ldtr_selector;
 362         u16 guest_tr_selector;
 363         u16 guest_intr_status;
 364         u16 host_es_selector;
 365         u16 host_cs_selector;
 366         u16 host_ss_selector;
 367         u16 host_ds_selector;
 368         u16 host_fs_selector;
 369         u16 host_gs_selector;
 370         u16 host_tr_selector;
 371 };
 372
 373 /*
 374  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 375  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 376  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 377  */
 378 #define VMCS12_REVISION 0x11e57ed0
 379
 380 /*
 381  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 382  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 383  * current implementation, 4K are reserved to avoid future complications.
 384  */
 385 #define VMCS12_SIZE 0x1000
 386
 387 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 388 struct vmcs02_list {
 389         struct list_head list;
 390         gpa_t vmptr;
 391         struct loaded_vmcs vmcs02;
 392 };
 393
 394 /*
 395  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 396  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 397  */
 398 struct nested_vmx {
 399         /* Has the level1 guest done vmxon? */
 400         bool vmxon;
 401         gpa_t vmxon_ptr;
 402
 403         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 404         gpa_t current_vmptr;
 405         /* The host-usable pointer to the above */
 406         struct page *current_vmcs12_page;
 407         struct vmcs12 *current_vmcs12;
 408         /*
 409          * Cache of the guest's VMCS, existing outside of guest memory.
 410          * Loaded from guest memory during VMPTRLD. Flushed to guest
 411          * memory during VMXOFF, VMCLEAR, VMPTRLD.
 412          */
 413         struct vmcs12 *cached_vmcs12;
 414         struct vmcs *current_shadow_vmcs;
 415         /*
 416          * Indicates if the shadow vmcs must be updated with the
 417          * data hold by vmcs12
 418          */
 419         bool sync_shadow_vmcs;
 420
 421         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 422         struct list_head vmcs02_pool;
 423         int vmcs02_num;
 424         u64 vmcs01_tsc_offset;
 425         /* L2 must run next, and mustn't decide to exit to L1. */
 426         bool nested_run_pending;
 427         /*
 428          * Guest pages referred to in vmcs02 with host-physical pointers, so
 429          * we must keep them pinned while L2 runs.
 430          */
 431         struct page *apic_access_page;
 432         struct page *virtual_apic_page;
 433         struct page *pi_desc_page;
 434         struct pi_desc *pi_desc;
 435         bool pi_pending;
 436         u16 posted_intr_nv;
 437
 438         struct hrtimer preemption_timer;
 439         bool preemption_timer_expired;
 440
 441         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 442         u64 vmcs01_debugctl;
 443
 444         u16 vpid02;
 445         u16 last_vpid;
 446
 447         u32 nested_vmx_procbased_ctls_low;
 448         u32 nested_vmx_procbased_ctls_high;
 449         u32 nested_vmx_true_procbased_ctls_low;
 450         u32 nested_vmx_secondary_ctls_low;
 451         u32 nested_vmx_secondary_ctls_high;
 452         u32 nested_vmx_pinbased_ctls_low;
 453         u32 nested_vmx_pinbased_ctls_high;
 454         u32 nested_vmx_exit_ctls_low;
 455         u32 nested_vmx_exit_ctls_high;
 456         u32 nested_vmx_true_exit_ctls_low;
 457         u32 nested_vmx_entry_ctls_low;
 458         u32 nested_vmx_entry_ctls_high;
 459         u32 nested_vmx_true_entry_ctls_low;
 460         u32 nested_vmx_misc_low;
 461         u32 nested_vmx_misc_high;
 462         u32 nested_vmx_ept_caps;
 463         u32 nested_vmx_vpid_caps;
 464 };
 465
 466 #define POSTED_INTR_ON  0
 467 #define POSTED_INTR_SN  1
 468
 469 /* Posted-Interrupt Descriptor */
 470 struct pi_desc {
 471         u32 pir[8];     /* Posted interrupt requested */
 472         union {
 473                 struct {
 474                                 /* bit 256 - Outstanding Notification */
 475                         u16     on      : 1,
 476                                 /* bit 257 - Suppress Notification */
 477                                 sn      : 1,
 478                                 /* bit 271:258 - Reserved */
 479                                 rsvd_1  : 14;
 480                                 /* bit 279:272 - Notification Vector */
 481                         u8      nv;
 482                                 /* bit 287:280 - Reserved */
 483                         u8      rsvd_2;
 484                                 /* bit 319:288 - Notification Destination */
 485                         u32     ndst;
 486                 };
 487                 u64 control;
 488         };
 489         u32 rsvd[6];
 490 } __aligned(64);
 491
 492 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 493 {
 494         return test_and_set_bit(POSTED_INTR_ON,
 495                         (unsigned long *)&pi_desc->control);
 496 }
 497
 498 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 499 {
 500         return test_and_clear_bit(POSTED_INTR_ON,
 501                         (unsigned long *)&pi_desc->control);
 502 }
 503
 504 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 505 {
 506         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 507 }
 508
 509 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 510 {
 511         return clear_bit(POSTED_INTR_SN,
 512                         (unsigned long *)&pi_desc->control);
 513 }
 514
 515 static inline void pi_set_sn(struct pi_desc *pi_desc)
 516 {
 517         return set_bit(POSTED_INTR_SN,
 518                         (unsigned long *)&pi_desc->control);
 519 }
 520
 521 static inline int pi_test_on(struct pi_desc *pi_desc)
 522 {
 523         return test_bit(POSTED_INTR_ON,
 524                         (unsigned long *)&pi_desc->control);
 525 }
 526
 527 static inline int pi_test_sn(struct pi_desc *pi_desc)
 528 {
 529         return test_bit(POSTED_INTR_SN,
 530                         (unsigned long *)&pi_desc->control);
 531 }
 532
 533 struct vcpu_vmx {
 534         struct kvm_vcpu       vcpu;
 535         unsigned long         host_rsp;
 536         u8                    fail;
 537         bool                  nmi_known_unmasked;
 538         u32                   exit_intr_info;
 539         u32                   idt_vectoring_info;
 540         ulong                 rflags;
 541         struct shared_msr_entry *guest_msrs;
 542         int                   nmsrs;
 543         int                   save_nmsrs;
 544         unsigned long         host_idt_base;
 545 #ifdef CONFIG_X86_64
 546         u64                   msr_host_kernel_gs_base;
 547         u64                   msr_guest_kernel_gs_base;
 548 #endif
 549         u32 vm_entry_controls_shadow;
 550         u32 vm_exit_controls_shadow;
 551         /*
 552          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 553          * non-nested (L1) guest, it always points to vmcs01. For a nested
 554          * guest (L2), it points to a different VMCS.
 555          */
 556         struct loaded_vmcs    vmcs01;
 557         struct loaded_vmcs   *loaded_vmcs;
 558         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 559         struct msr_autoload {
 560                 unsigned nr;
 561                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 562                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 563         } msr_autoload;
 564         struct {
 565                 int           loaded;
 566                 u16           fs_sel, gs_sel, ldt_sel;
 567 #ifdef CONFIG_X86_64
 568                 u16           ds_sel, es_sel;
 569 #endif
 570                 int           gs_ldt_reload_needed;
 571                 int           fs_reload_needed;
 572                 u64           msr_host_bndcfgs;
 573                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 574         } host_state;
 575         struct {
 576                 int vm86_active;
 577                 ulong save_rflags;
 578                 struct kvm_segment segs[8];
 579         } rmode;
 580         struct {
 581                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 582                 struct kvm_save_segment {
 583                         u16 selector;
 584                         unsigned long base;
 585                         u32 limit;
 586                         u32 ar;
 587                 } seg[8];
 588         } segment_cache;
 589         int vpid;
 590         bool emulation_required;
 591
 592         /* Support for vnmi-less CPUs */
 593         int soft_vnmi_blocked;
 594         ktime_t entry_time;
 595         s64 vnmi_blocked_time;
 596         u32 exit_reason;
 597
 598         /* Posted interrupt descriptor */
 599         struct pi_desc pi_desc;
 600
 601         /* Support for a guest hypervisor (nested VMX) */
 602         struct nested_vmx nested;
 603
 604         /* Dynamic PLE window. */
 605         int ple_window;
 606         bool ple_window_dirty;
 607
 608         /* Support for PML */
 609 #define PML_ENTITY_NUM          512
 610         struct page *pml_pg;
 611
 612         /* apic deadline value in host tsc */
 613         u64 hv_deadline_tsc;
 614
 615         u64 current_tsc_ratio;
 616
 617         bool guest_pkru_valid;
 618         u32 guest_pkru;
 619         u32 host_pkru;
 620
 621         /*
 622          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
 623          * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
 624          * in msr_ia32_feature_control_valid_bits.
 625          */
 626         u64 msr_ia32_feature_control;
 627         u64 msr_ia32_feature_control_valid_bits;
 628 };
 629
 630 enum segment_cache_field {
 631         SEG_FIELD_SEL = 0,
 632         SEG_FIELD_BASE = 1,
 633         SEG_FIELD_LIMIT = 2,
 634         SEG_FIELD_AR = 3,
 635
 636         SEG_FIELD_NR = 4
 637 };
 638
 639 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 640 {
 641         return container_of(vcpu, struct vcpu_vmx, vcpu);
 642 }
 643
 644 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 645 {
 646         return &(to_vmx(vcpu)->pi_desc);
 647 }
 648
 649 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 650 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 651 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 652                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 653
 654
 655 static unsigned long shadow_read_only_fields[] = {
 656         /*
 657          * We do NOT shadow fields that are modified when L0
 658          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 659          * VMXON...) executed by L1.
 660          * For example, VM_INSTRUCTION_ERROR is read
 661          * by L1 if a vmx instruction fails (part of the error path).
 662          * Note the code assumes this logic. If for some reason
 663          * we start shadowing these fields then we need to
 664          * force a shadow sync when L0 emulates vmx instructions
 665          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 666          * by nested_vmx_failValid)
 667          */
 668         VM_EXIT_REASON,
 669         VM_EXIT_INTR_INFO,
 670         VM_EXIT_INSTRUCTION_LEN,
 671         IDT_VECTORING_INFO_FIELD,
 672         IDT_VECTORING_ERROR_CODE,
 673         VM_EXIT_INTR_ERROR_CODE,
 674         EXIT_QUALIFICATION,
 675         GUEST_LINEAR_ADDRESS,
 676         GUEST_PHYSICAL_ADDRESS
 677 };
 678 static int max_shadow_read_only_fields =
 679         ARRAY_SIZE(shadow_read_only_fields);
 680
 681 static unsigned long shadow_read_write_fields[] = {
 682         TPR_THRESHOLD,
 683         GUEST_RIP,
 684         GUEST_RSP,
 685         GUEST_CR0,
 686         GUEST_CR3,
 687         GUEST_CR4,
 688         GUEST_INTERRUPTIBILITY_INFO,
 689         GUEST_RFLAGS,
 690         GUEST_CS_SELECTOR,
 691         GUEST_CS_AR_BYTES,
 692         GUEST_CS_LIMIT,
 693         GUEST_CS_BASE,
 694         GUEST_ES_BASE,
 695         GUEST_BNDCFGS,
 696         CR0_GUEST_HOST_MASK,
 697         CR0_READ_SHADOW,
 698         CR4_READ_SHADOW,
 699         TSC_OFFSET,
 700         EXCEPTION_BITMAP,
 701         CPU_BASED_VM_EXEC_CONTROL,
 702         VM_ENTRY_EXCEPTION_ERROR_CODE,
 703         VM_ENTRY_INTR_INFO_FIELD,
 704         VM_ENTRY_INSTRUCTION_LEN,
 705         VM_ENTRY_EXCEPTION_ERROR_CODE,
 706         HOST_FS_BASE,
 707         HOST_GS_BASE,
 708         HOST_FS_SELECTOR,
 709         HOST_GS_SELECTOR
 710 };
 711 static int max_shadow_read_write_fields =
 712         ARRAY_SIZE(shadow_read_write_fields);
 713
 714 static const unsigned short vmcs_field_to_offset_table[] = {
 715         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 716         FIELD(POSTED_INTR_NV, posted_intr_nv),
 717         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 718         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 719         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 720         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 721         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 722         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 723         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 724         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 725         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 726         FIELD(HOST_ES_SELECTOR, host_es_selector),
 727         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 728         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 729         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 730         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 731         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 732         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 733         FIELD64(IO_BITMAP_A, io_bitmap_a),
 734         FIELD64(IO_BITMAP_B, io_bitmap_b),
 735         FIELD64(MSR_BITMAP, msr_bitmap),
 736         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 737         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 738         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 739         FIELD64(TSC_OFFSET, tsc_offset),
 740         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 741         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 742         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 743         FIELD64(EPT_POINTER, ept_pointer),
 744         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 745         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 746         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 747         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 748         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 749         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 750         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 751         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 752         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 753         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 754         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 755         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 756         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 757         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 758         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 759         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 760         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 761         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 762         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 763         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 764         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 765         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 766         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 767         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 768         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 769         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 770         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 771         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 772         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 773         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 774         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 775         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 776         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 777         FIELD(TPR_THRESHOLD, tpr_threshold),
 778         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 779         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 780         FIELD(VM_EXIT_REASON, vm_exit_reason),
 781         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 782         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 783         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 784         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 785         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 786         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 787         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 788         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 789         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 790         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 791         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 792         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 793         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 794         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 795         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 796         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 797         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 798         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 799         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 800         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 801         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 802         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 803         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 804         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 805         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 806         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 807         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 808         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 809         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 810         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 811         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 812         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 813         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 814         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 815         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 816         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 817         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 818         FIELD(EXIT_QUALIFICATION, exit_qualification),
 819         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 820         FIELD(GUEST_CR0, guest_cr0),
 821         FIELD(GUEST_CR3, guest_cr3),
 822         FIELD(GUEST_CR4, guest_cr4),
 823         FIELD(GUEST_ES_BASE, guest_es_base),
 824         FIELD(GUEST_CS_BASE, guest_cs_base),
 825         FIELD(GUEST_SS_BASE, guest_ss_base),
 826         FIELD(GUEST_DS_BASE, guest_ds_base),
 827         FIELD(GUEST_FS_BASE, guest_fs_base),
 828         FIELD(GUEST_GS_BASE, guest_gs_base),
 829         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 830         FIELD(GUEST_TR_BASE, guest_tr_base),
 831         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 832         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 833         FIELD(GUEST_DR7, guest_dr7),
 834         FIELD(GUEST_RSP, guest_rsp),
 835         FIELD(GUEST_RIP, guest_rip),
 836         FIELD(GUEST_RFLAGS, guest_rflags),
 837         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 838         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 839         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 840         FIELD(HOST_CR0, host_cr0),
 841         FIELD(HOST_CR3, host_cr3),
 842         FIELD(HOST_CR4, host_cr4),
 843         FIELD(HOST_FS_BASE, host_fs_base),
 844         FIELD(HOST_GS_BASE, host_gs_base),
 845         FIELD(HOST_TR_BASE, host_tr_base),
 846         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 847         FIELD(HOST_IDTR_BASE, host_idtr_base),
 848         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 849         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 850         FIELD(HOST_RSP, host_rsp),
 851         FIELD(HOST_RIP, host_rip),
 852 };
 853
 854 static inline short vmcs_field_to_offset(unsigned long field)
 855 {
 856         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 857
 858         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 859             vmcs_field_to_offset_table[field] == 0)
 860                 return -ENOENT;
 861
 862         return vmcs_field_to_offset_table[field];
 863 }
 864
 865 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 866 {
 867         return to_vmx(vcpu)->nested.cached_vmcs12;
 868 }
 869
 870 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 871 {
 872         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 873         if (is_error_page(page))
 874                 return NULL;
 875
 876         return page;
 877 }
 878
 879 static void nested_release_page(struct page *page)
 880 {
 881         kvm_release_page_dirty(page);
 882 }
 883
 884 static void nested_release_page_clean(struct page *page)
 885 {
 886         kvm_release_page_clean(page);
 887 }
 888
 889 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 890 static u64 construct_eptp(unsigned long root_hpa);
 891 static void kvm_cpu_vmxon(u64 addr);
 892 static void kvm_cpu_vmxoff(void);
 893 static bool vmx_xsaves_supported(void);
 894 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 895 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 896                             struct kvm_segment *var, int seg);
 897 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 898                             struct kvm_segment *var, int seg);
 899 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 900 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 901 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 902 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 903 static int alloc_identity_pagetable(struct kvm *kvm);
 904
 905 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 906 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 907 /*
 908  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 909  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 910  */
 911 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 912 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 913
 914 /*
 915  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 916  * can find which vCPU should be waken up.
 917  */
 918 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 919 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 920
 921 static unsigned long *vmx_io_bitmap_a;
 922 static unsigned long *vmx_io_bitmap_b;
 923 static unsigned long *vmx_msr_bitmap_legacy;
 924 static unsigned long *vmx_msr_bitmap_longmode;
 925 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 926 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 927 static unsigned long *vmx_msr_bitmap_nested;
 928 static unsigned long *vmx_vmread_bitmap;
 929 static unsigned long *vmx_vmwrite_bitmap;
 930
 931 static bool cpu_has_load_ia32_efer;
 932 static bool cpu_has_load_perf_global_ctrl;
 933
 934 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 935 static DEFINE_SPINLOCK(vmx_vpid_lock);
 936
 937 static struct vmcs_config {
 938         int size;
 939         int order;
 940         u32 revision_id;
 941         u32 pin_based_exec_ctrl;
 942         u32 cpu_based_exec_ctrl;
 943         u32 cpu_based_2nd_exec_ctrl;
 944         u32 vmexit_ctrl;
 945         u32 vmentry_ctrl;
 946 } vmcs_config;
 947
 948 static struct vmx_capability {
 949         u32 ept;
 950         u32 vpid;
 951 } vmx_capability;
 952
 953 #define VMX_SEGMENT_FIELD(seg)                                  \
 954         [VCPU_SREG_##seg] = {                                   \
 955                 .selector = GUEST_##seg##_SELECTOR,             \
 956                 .base = GUEST_##seg##_BASE,                     \
 957                 .limit = GUEST_##seg##_LIMIT,                   \
 958                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 959         }
 960
 961 static const struct kvm_vmx_segment_field {
 962         unsigned selector;
 963         unsigned base;
 964         unsigned limit;
 965         unsigned ar_bytes;
 966 } kvm_vmx_segment_fields[] = {
 967         VMX_SEGMENT_FIELD(CS),
 968         VMX_SEGMENT_FIELD(DS),
 969         VMX_SEGMENT_FIELD(ES),
 970         VMX_SEGMENT_FIELD(FS),
 971         VMX_SEGMENT_FIELD(GS),
 972         VMX_SEGMENT_FIELD(SS),
 973         VMX_SEGMENT_FIELD(TR),
 974         VMX_SEGMENT_FIELD(LDTR),
 975 };
 976
 977 static u64 host_efer;
 978
 979 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 980
 981 /*
 982  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 983  * away by decrementing the array size.
 984  */
 985 static const u32 vmx_msr_index[] = {
 986 #ifdef CONFIG_X86_64
 987         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 988 #endif
 989         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 990 };
 991
 992 static inline bool is_exception_n(u32 intr_info, u8 vector)
 993 {
 994         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 995                              INTR_INFO_VALID_MASK)) ==
 996                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
 997 }
 998
 999 static inline bool is_debug(u32 intr_info)
1000 {
1001         return is_exception_n(intr_info, DB_VECTOR);
1002 }
1003
1004 static inline bool is_breakpoint(u32 intr_info)
1005 {
1006         return is_exception_n(intr_info, BP_VECTOR);
1007 }
1008
1009 static inline bool is_page_fault(u32 intr_info)
1010 {
1011         return is_exception_n(intr_info, PF_VECTOR);
1012 }
1013
1014 static inline bool is_no_device(u32 intr_info)
1015 {
1016         return is_exception_n(intr_info, NM_VECTOR);
1017 }
1018
1019 static inline bool is_invalid_opcode(u32 intr_info)
1020 {
1021         return is_exception_n(intr_info, UD_VECTOR);
1022 }
1023
1024 static inline bool is_external_interrupt(u32 intr_info)
1025 {
1026         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1027                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1028 }
1029
1030 static inline bool is_machine_check(u32 intr_info)
1031 {
1032         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1033                              INTR_INFO_VALID_MASK)) ==
1034                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1035 }
1036
1037 static inline bool cpu_has_vmx_msr_bitmap(void)
1038 {
1039         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1040 }
1041
1042 static inline bool cpu_has_vmx_tpr_shadow(void)
1043 {
1044         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1045 }
1046
1047 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1048 {
1049         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1050 }
1051
1052 static inline bool cpu_has_secondary_exec_ctrls(void)
1053 {
1054         return vmcs_config.cpu_based_exec_ctrl &
1055                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1056 }
1057
1058 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1059 {
1060         return vmcs_config.cpu_based_2nd_exec_ctrl &
1061                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1062 }
1063
1064 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1065 {
1066         return vmcs_config.cpu_based_2nd_exec_ctrl &
1067                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1068 }
1069
1070 static inline bool cpu_has_vmx_apic_register_virt(void)
1071 {
1072         return vmcs_config.cpu_based_2nd_exec_ctrl &
1073                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1074 }
1075
1076 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1077 {
1078         return vmcs_config.cpu_based_2nd_exec_ctrl &
1079                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1080 }
1081
1082 /*
1083  * Comment's format: document - errata name - stepping - processor name.
1084  * Refer from
1085  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1086  */
1087 static u32 vmx_preemption_cpu_tfms[] = {
1088 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
1089 0x000206E6,
1090 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
1091 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1092 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1093 0x00020652,
1094 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1095 0x00020655,
1096 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
1097 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
1098 /*
1099  * 320767.pdf - AAP86  - B1 -
1100  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1101  */
1102 0x000106E5,
1103 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1104 0x000106A0,
1105 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1106 0x000106A1,
1107 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1108 0x000106A4,
1109  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1110  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1111  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1112 0x000106A5,
1113 };
1114
1115 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1116 {
1117         u32 eax = cpuid_eax(0x00000001), i;
1118
1119         /* Clear the reserved bits */
1120         eax &= ~(0x3U << 14 | 0xfU << 28);
1121         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1122                 if (eax == vmx_preemption_cpu_tfms[i])
1123                         return true;
1124
1125         return false;
1126 }
1127
1128 static inline bool cpu_has_vmx_preemption_timer(void)
1129 {
1130         return vmcs_config.pin_based_exec_ctrl &
1131                 PIN_BASED_VMX_PREEMPTION_TIMER;
1132 }
1133
1134 static inline bool cpu_has_vmx_posted_intr(void)
1135 {
1136         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1137                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1138 }
1139
1140 static inline bool cpu_has_vmx_apicv(void)
1141 {
1142         return cpu_has_vmx_apic_register_virt() &&
1143                 cpu_has_vmx_virtual_intr_delivery() &&
1144                 cpu_has_vmx_posted_intr();
1145 }
1146
1147 static inline bool cpu_has_vmx_flexpriority(void)
1148 {
1149         return cpu_has_vmx_tpr_shadow() &&
1150                 cpu_has_vmx_virtualize_apic_accesses();
1151 }
1152
1153 static inline bool cpu_has_vmx_ept_execute_only(void)
1154 {
1155         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1156 }
1157
1158 static inline bool cpu_has_vmx_ept_2m_page(void)
1159 {
1160         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1161 }
1162
1163 static inline bool cpu_has_vmx_ept_1g_page(void)
1164 {
1165         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1166 }
1167
1168 static inline bool cpu_has_vmx_ept_4levels(void)
1169 {
1170         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1171 }
1172
1173 static inline bool cpu_has_vmx_ept_ad_bits(void)
1174 {
1175         return vmx_capability.ept & VMX_EPT_AD_BIT;
1176 }
1177
1178 static inline bool cpu_has_vmx_invept_context(void)
1179 {
1180         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1181 }
1182
1183 static inline bool cpu_has_vmx_invept_global(void)
1184 {
1185         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1186 }
1187
1188 static inline bool cpu_has_vmx_invvpid_single(void)
1189 {
1190         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1191 }
1192
1193 static inline bool cpu_has_vmx_invvpid_global(void)
1194 {
1195         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1196 }
1197
1198 static inline bool cpu_has_vmx_ept(void)
1199 {
1200         return vmcs_config.cpu_based_2nd_exec_ctrl &
1201                 SECONDARY_EXEC_ENABLE_EPT;
1202 }
1203
1204 static inline bool cpu_has_vmx_unrestricted_guest(void)
1205 {
1206         return vmcs_config.cpu_based_2nd_exec_ctrl &
1207                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1208 }
1209
1210 static inline bool cpu_has_vmx_ple(void)
1211 {
1212         return vmcs_config.cpu_based_2nd_exec_ctrl &
1213                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1214 }
1215
1216 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1217 {
1218         return flexpriority_enabled && lapic_in_kernel(vcpu);
1219 }
1220
1221 static inline bool cpu_has_vmx_vpid(void)
1222 {
1223         return vmcs_config.cpu_based_2nd_exec_ctrl &
1224                 SECONDARY_EXEC_ENABLE_VPID;
1225 }
1226
1227 static inline bool cpu_has_vmx_rdtscp(void)
1228 {
1229         return vmcs_config.cpu_based_2nd_exec_ctrl &
1230                 SECONDARY_EXEC_RDTSCP;
1231 }
1232
1233 static inline bool cpu_has_vmx_invpcid(void)
1234 {
1235         return vmcs_config.cpu_based_2nd_exec_ctrl &
1236                 SECONDARY_EXEC_ENABLE_INVPCID;
1237 }
1238
1239 static inline bool cpu_has_virtual_nmis(void)
1240 {
1241         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1242 }
1243
1244 static inline bool cpu_has_vmx_wbinvd_exit(void)
1245 {
1246         return vmcs_config.cpu_based_2nd_exec_ctrl &
1247                 SECONDARY_EXEC_WBINVD_EXITING;
1248 }
1249
1250 static inline bool cpu_has_vmx_shadow_vmcs(void)
1251 {
1252         u64 vmx_msr;
1253         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1254         /* check if the cpu supports writing r/o exit information fields */
1255         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1256                 return false;
1257
1258         return vmcs_config.cpu_based_2nd_exec_ctrl &
1259                 SECONDARY_EXEC_SHADOW_VMCS;
1260 }
1261
1262 static inline bool cpu_has_vmx_pml(void)
1263 {
1264         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1265 }
1266
1267 static inline bool cpu_has_vmx_tsc_scaling(void)
1268 {
1269         return vmcs_config.cpu_based_2nd_exec_ctrl &
1270                 SECONDARY_EXEC_TSC_SCALING;
1271 }
1272
1273 static inline bool report_flexpriority(void)
1274 {
1275         return flexpriority_enabled;
1276 }
1277
1278 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1279 {
1280         return vmcs12->cpu_based_vm_exec_control & bit;
1281 }
1282
1283 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1284 {
1285         return (vmcs12->cpu_based_vm_exec_control &
1286                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1287                 (vmcs12->secondary_vm_exec_control & bit);
1288 }
1289
1290 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1291 {
1292         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1293 }
1294
1295 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1296 {
1297         return vmcs12->pin_based_vm_exec_control &
1298                 PIN_BASED_VMX_PREEMPTION_TIMER;
1299 }
1300
1301 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1302 {
1303         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1304 }
1305
1306 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1307 {
1308         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1309                 vmx_xsaves_supported();
1310 }
1311
1312 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1313 {
1314         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1315 }
1316
1317 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1318 {
1319         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1320 }
1321
1322 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1323 {
1324         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1325 }
1326
1327 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1328 {
1329         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1330 }
1331
1332 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1333 {
1334         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1335 }
1336
1337 static inline bool is_exception(u32 intr_info)
1338 {
1339         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1340                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1341 }
1342
1343 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1344                               u32 exit_intr_info,
1345                               unsigned long exit_qualification);
1346 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1347                         struct vmcs12 *vmcs12,
1348                         u32 reason, unsigned long qualification);
1349
1350 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1351 {
1352         int i;
1353
1354         for (i = 0; i < vmx->nmsrs; ++i)
1355                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1356                         return i;
1357         return -1;
1358 }
1359
1360 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1361 {
1362     struct {
1363         u64 vpid : 16;
1364         u64 rsvd : 48;
1365         u64 gva;
1366     } operand = { vpid, 0, gva };
1367
1368     asm volatile (__ex(ASM_VMX_INVVPID)
1369                   /* CF==1 or ZF==1 --> rc = -1 */
1370                   "; ja 1f ; ud2 ; 1:"
1371                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1372 }
1373
1374 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1375 {
1376         struct {
1377                 u64 eptp, gpa;
1378         } operand = {eptp, gpa};
1379
1380         asm volatile (__ex(ASM_VMX_INVEPT)
1381                         /* CF==1 or ZF==1 --> rc = -1 */
1382                         "; ja 1f ; ud2 ; 1:\n"
1383                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1384 }
1385
1386 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1387 {
1388         int i;
1389
1390         i = __find_msr_index(vmx, msr);
1391         if (i >= 0)
1392                 return &vmx->guest_msrs[i];
1393         return NULL;
1394 }
1395
1396 static void vmcs_clear(struct vmcs *vmcs)
1397 {
1398         u64 phys_addr = __pa(vmcs);
1399         u8 error;
1400
1401         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1402                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1403                       : "cc", "memory");
1404         if (error)
1405                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1406                        vmcs, phys_addr);
1407 }
1408
1409 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1410 {
1411         vmcs_clear(loaded_vmcs->vmcs);
1412         loaded_vmcs->cpu = -1;
1413         loaded_vmcs->launched = 0;
1414 }
1415
1416 static void vmcs_load(struct vmcs *vmcs)
1417 {
1418         u64 phys_addr = __pa(vmcs);
1419         u8 error;
1420
1421         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1422                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1423                         : "cc", "memory");
1424         if (error)
1425                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1426                        vmcs, phys_addr);
1427 }
1428
1429 #ifdef CONFIG_KEXEC_CORE
1430 /*
1431  * This bitmap is used to indicate whether the vmclear
1432  * operation is enabled on all cpus. All disabled by
1433  * default.
1434  */
1435 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1436
1437 static inline void crash_enable_local_vmclear(int cpu)
1438 {
1439         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1440 }
1441
1442 static inline void crash_disable_local_vmclear(int cpu)
1443 {
1444         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1445 }
1446
1447 static inline int crash_local_vmclear_enabled(int cpu)
1448 {
1449         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1450 }
1451
1452 static void crash_vmclear_local_loaded_vmcss(void)
1453 {
1454         int cpu = raw_smp_processor_id();
1455         struct loaded_vmcs *v;
1456
1457         if (!crash_local_vmclear_enabled(cpu))
1458                 return;
1459
1460         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1461                             loaded_vmcss_on_cpu_link)
1462                 vmcs_clear(v->vmcs);
1463 }
1464 #else
1465 static inline void crash_enable_local_vmclear(int cpu) { }
1466 static inline void crash_disable_local_vmclear(int cpu) { }
1467 #endif /* CONFIG_KEXEC_CORE */
1468
1469 static void __loaded_vmcs_clear(void *arg)
1470 {
1471         struct loaded_vmcs *loaded_vmcs = arg;
1472         int cpu = raw_smp_processor_id();
1473
1474         if (loaded_vmcs->cpu != cpu)
1475                 return; /* vcpu migration can race with cpu offline */
1476         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1477                 per_cpu(current_vmcs, cpu) = NULL;
1478         crash_disable_local_vmclear(cpu);
1479         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1480
1481         /*
1482          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1483          * is before setting loaded_vmcs->vcpu to -1 which is done in
1484          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1485          * then adds the vmcs into percpu list before it is deleted.
1486          */
1487         smp_wmb();
1488
1489         loaded_vmcs_init(loaded_vmcs);
1490         crash_enable_local_vmclear(cpu);
1491 }
1492
1493 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1494 {
1495         int cpu = loaded_vmcs->cpu;
1496
1497         if (cpu != -1)
1498                 smp_call_function_single(cpu,
1499                          __loaded_vmcs_clear, loaded_vmcs, 1);
1500 }
1501
1502 static inline void vpid_sync_vcpu_single(int vpid)
1503 {
1504         if (vpid == 0)
1505                 return;
1506
1507         if (cpu_has_vmx_invvpid_single())
1508                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1509 }
1510
1511 static inline void vpid_sync_vcpu_global(void)
1512 {
1513         if (cpu_has_vmx_invvpid_global())
1514                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1515 }
1516
1517 static inline void vpid_sync_context(int vpid)
1518 {
1519         if (cpu_has_vmx_invvpid_single())
1520                 vpid_sync_vcpu_single(vpid);
1521         else
1522                 vpid_sync_vcpu_global();
1523 }
1524
1525 static inline void ept_sync_global(void)
1526 {
1527         if (cpu_has_vmx_invept_global())
1528                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1529 }
1530
1531 static inline void ept_sync_context(u64 eptp)
1532 {
1533         if (enable_ept) {
1534                 if (cpu_has_vmx_invept_context())
1535                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1536                 else
1537                         ept_sync_global();
1538         }
1539 }
1540
1541 static __always_inline void vmcs_check16(unsigned long field)
1542 {
1543         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1544                          "16-bit accessor invalid for 64-bit field");
1545         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1546                          "16-bit accessor invalid for 64-bit high field");
1547         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1548                          "16-bit accessor invalid for 32-bit high field");
1549         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1550                          "16-bit accessor invalid for natural width field");
1551 }
1552
1553 static __always_inline void vmcs_check32(unsigned long field)
1554 {
1555         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1556                          "32-bit accessor invalid for 16-bit field");
1557         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1558                          "32-bit accessor invalid for natural width field");
1559 }
1560
1561 static __always_inline void vmcs_check64(unsigned long field)
1562 {
1563         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1564                          "64-bit accessor invalid for 16-bit field");
1565         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1566                          "64-bit accessor invalid for 64-bit high field");
1567         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1568                          "64-bit accessor invalid for 32-bit field");
1569         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1570                          "64-bit accessor invalid for natural width field");
1571 }
1572
1573 static __always_inline void vmcs_checkl(unsigned long field)
1574 {
1575         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1576                          "Natural width accessor invalid for 16-bit field");
1577         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1578                          "Natural width accessor invalid for 64-bit field");
1579         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1580                          "Natural width accessor invalid for 64-bit high field");
1581         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1582                          "Natural width accessor invalid for 32-bit field");
1583 }
1584
1585 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1586 {
1587         unsigned long value;
1588
1589         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1590                       : "=a"(value) : "d"(field) : "cc");
1591         return value;
1592 }
1593
1594 static __always_inline u16 vmcs_read16(unsigned long field)
1595 {
1596         vmcs_check16(field);
1597         return __vmcs_readl(field);
1598 }
1599
1600 static __always_inline u32 vmcs_read32(unsigned long field)
1601 {
1602         vmcs_check32(field);
1603         return __vmcs_readl(field);
1604 }
1605
1606 static __always_inline u64 vmcs_read64(unsigned long field)
1607 {
1608         vmcs_check64(field);
1609 #ifdef CONFIG_X86_64
1610         return __vmcs_readl(field);
1611 #else
1612         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1613 #endif
1614 }
1615
1616 static __always_inline unsigned long vmcs_readl(unsigned long field)
1617 {
1618         vmcs_checkl(field);
1619         return __vmcs_readl(field);
1620 }
1621
1622 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1623 {
1624         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1625                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1626         dump_stack();
1627 }
1628
1629 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1630 {
1631         u8 error;
1632
1633         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1634                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1635         if (unlikely(error))
1636                 vmwrite_error(field, value);
1637 }
1638
1639 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1640 {
1641         vmcs_check16(field);
1642         __vmcs_writel(field, value);
1643 }
1644
1645 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1646 {
1647         vmcs_check32(field);
1648         __vmcs_writel(field, value);
1649 }
1650
1651 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1652 {
1653         vmcs_check64(field);
1654         __vmcs_writel(field, value);
1655 #ifndef CONFIG_X86_64
1656         asm volatile ("");
1657         __vmcs_writel(field+1, value >> 32);
1658 #endif
1659 }
1660
1661 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1662 {
1663         vmcs_checkl(field);
1664         __vmcs_writel(field, value);
1665 }
1666
1667 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1668 {
1669         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1670                          "vmcs_clear_bits does not support 64-bit fields");
1671         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1672 }
1673
1674 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1675 {
1676         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1677                          "vmcs_set_bits does not support 64-bit fields");
1678         __vmcs_writel(field, __vmcs_readl(field) | mask);
1679 }
1680
1681 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1682 {
1683         vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1684 }
1685
1686 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1687 {
1688         vmcs_write32(VM_ENTRY_CONTROLS, val);
1689         vmx->vm_entry_controls_shadow = val;
1690 }
1691
1692 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1693 {
1694         if (vmx->vm_entry_controls_shadow != val)
1695                 vm_entry_controls_init(vmx, val);
1696 }
1697
1698 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1699 {
1700         return vmx->vm_entry_controls_shadow;
1701 }
1702
1703
1704 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1705 {
1706         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1707 }
1708
1709 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1710 {
1711         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1712 }
1713
1714 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1715 {
1716         vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1717 }
1718
1719 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1720 {
1721         vmcs_write32(VM_EXIT_CONTROLS, val);
1722         vmx->vm_exit_controls_shadow = val;
1723 }
1724
1725 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1726 {
1727         if (vmx->vm_exit_controls_shadow != val)
1728                 vm_exit_controls_init(vmx, val);
1729 }
1730
1731 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1732 {
1733         return vmx->vm_exit_controls_shadow;
1734 }
1735
1736
1737 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1738 {
1739         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1740 }
1741
1742 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1743 {
1744         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1745 }
1746
1747 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1748 {
1749         vmx->segment_cache.bitmask = 0;
1750 }
1751
1752 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1753                                        unsigned field)
1754 {
1755         bool ret;
1756         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1757
1758         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1759                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1760                 vmx->segment_cache.bitmask = 0;
1761         }
1762         ret = vmx->segment_cache.bitmask & mask;
1763         vmx->segment_cache.bitmask |= mask;
1764         return ret;
1765 }
1766
1767 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1768 {
1769         u16 *p = &vmx->segment_cache.seg[seg].selector;
1770
1771         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1772                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1773         return *p;
1774 }
1775
1776 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1777 {
1778         ulong *p = &vmx->segment_cache.seg[seg].base;
1779
1780         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1781                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1782         return *p;
1783 }
1784
1785 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1786 {
1787         u32 *p = &vmx->segment_cache.seg[seg].limit;
1788
1789         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1790                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1791         return *p;
1792 }
1793
1794 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1795 {
1796         u32 *p = &vmx->segment_cache.seg[seg].ar;
1797
1798         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1799                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1800         return *p;
1801 }
1802
1803 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1804 {
1805         u32 eb;
1806
1807         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1808              (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR);
1809         if ((vcpu->guest_debug &
1810              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1811             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1812                 eb |= 1u << BP_VECTOR;
1813         if (to_vmx(vcpu)->rmode.vm86_active)
1814                 eb = ~0;
1815         if (enable_ept)
1816                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1817         if (vcpu->fpu_active)
1818                 eb &= ~(1u << NM_VECTOR);
1819
1820         /* When we are running a nested L2 guest and L1 specified for it a
1821          * certain exception bitmap, we must trap the same exceptions and pass
1822          * them to L1. When running L2, we will only handle the exceptions
1823          * specified above if L1 did not want them.
1824          */
1825         if (is_guest_mode(vcpu))
1826                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1827
1828         vmcs_write32(EXCEPTION_BITMAP, eb);
1829 }
1830
1831 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1832                 unsigned long entry, unsigned long exit)
1833 {
1834         vm_entry_controls_clearbit(vmx, entry);
1835         vm_exit_controls_clearbit(vmx, exit);
1836 }
1837
1838 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1839 {
1840         unsigned i;
1841         struct msr_autoload *m = &vmx->msr_autoload;
1842
1843         switch (msr) {
1844         case MSR_EFER:
1845                 if (cpu_has_load_ia32_efer) {
1846                         clear_atomic_switch_msr_special(vmx,
1847                                         VM_ENTRY_LOAD_IA32_EFER,
1848                                         VM_EXIT_LOAD_IA32_EFER);
1849                         return;
1850                 }
1851                 break;
1852         case MSR_CORE_PERF_GLOBAL_CTRL:
1853                 if (cpu_has_load_perf_global_ctrl) {
1854                         clear_atomic_switch_msr_special(vmx,
1855                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1856                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1857                         return;
1858                 }
1859                 break;
1860         }
1861
1862         for (i = 0; i < m->nr; ++i)
1863                 if (m->guest[i].index == msr)
1864                         break;
1865
1866         if (i == m->nr)
1867                 return;
1868         --m->nr;
1869         m->guest[i] = m->guest[m->nr];
1870         m->host[i] = m->host[m->nr];
1871         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1872         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1873 }
1874
1875 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1876                 unsigned long entry, unsigned long exit,
1877                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1878                 u64 guest_val, u64 host_val)
1879 {
1880         vmcs_write64(guest_val_vmcs, guest_val);
1881         vmcs_write64(host_val_vmcs, host_val);
1882         vm_entry_controls_setbit(vmx, entry);
1883         vm_exit_controls_setbit(vmx, exit);
1884 }
1885
1886 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1887                                   u64 guest_val, u64 host_val)
1888 {
1889         unsigned i;
1890         struct msr_autoload *m = &vmx->msr_autoload;
1891
1892         switch (msr) {
1893         case MSR_EFER:
1894                 if (cpu_has_load_ia32_efer) {
1895                         add_atomic_switch_msr_special(vmx,
1896                                         VM_ENTRY_LOAD_IA32_EFER,
1897                                         VM_EXIT_LOAD_IA32_EFER,
1898                                         GUEST_IA32_EFER,
1899                                         HOST_IA32_EFER,
1900                                         guest_val, host_val);
1901                         return;
1902                 }
1903                 break;
1904         case MSR_CORE_PERF_GLOBAL_CTRL:
1905                 if (cpu_has_load_perf_global_ctrl) {
1906                         add_atomic_switch_msr_special(vmx,
1907                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1908                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1909                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1910                                         HOST_IA32_PERF_GLOBAL_CTRL,
1911                                         guest_val, host_val);
1912                         return;
1913                 }
1914                 break;
1915         case MSR_IA32_PEBS_ENABLE:
1916                 /* PEBS needs a quiescent period after being disabled (to write
1917                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
1918                  * provide that period, so a CPU could write host's record into
1919                  * guest's memory.
1920                  */
1921                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1922         }
1923
1924         for (i = 0; i < m->nr; ++i)
1925                 if (m->guest[i].index == msr)
1926                         break;
1927
1928         if (i == NR_AUTOLOAD_MSRS) {
1929                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1930                                 "Can't add msr %x\n", msr);
1931                 return;
1932         } else if (i == m->nr) {
1933                 ++m->nr;
1934                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1935                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1936         }
1937
1938         m->guest[i].index = msr;
1939         m->guest[i].value = guest_val;
1940         m->host[i].index = msr;
1941         m->host[i].value = host_val;
1942 }
1943
1944 static void reload_tss(void)
1945 {
1946         /*
1947          * VT restores TR but not its size.  Useless.
1948          */
1949         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1950         struct desc_struct *descs;
1951
1952         descs = (void *)gdt->address;
1953         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1954         load_TR_desc();
1955 }
1956
1957 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1958 {
1959         u64 guest_efer = vmx->vcpu.arch.efer;
1960         u64 ignore_bits = 0;
1961
1962         if (!enable_ept) {
1963                 /*
1964                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
1965                  * host CPUID is more efficient than testing guest CPUID
1966                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
1967                  */
1968                 if (boot_cpu_has(X86_FEATURE_SMEP))
1969                         guest_efer |= EFER_NX;
1970                 else if (!(guest_efer & EFER_NX))
1971                         ignore_bits |= EFER_NX;
1972         }
1973
1974         /*
1975          * LMA and LME handled by hardware; SCE meaningless outside long mode.
1976          */
1977         ignore_bits |= EFER_SCE;
1978 #ifdef CONFIG_X86_64
1979         ignore_bits |= EFER_LMA | EFER_LME;
1980         /* SCE is meaningful only in long mode on Intel */
1981         if (guest_efer & EFER_LMA)
1982                 ignore_bits &= ~(u64)EFER_SCE;
1983 #endif
1984
1985         clear_atomic_switch_msr(vmx, MSR_EFER);
1986
1987         /*
1988          * On EPT, we can't emulate NX, so we must switch EFER atomically.
1989          * On CPUs that support "load IA32_EFER", always switch EFER
1990          * atomically, since it's faster than switching it manually.
1991          */
1992         if (cpu_has_load_ia32_efer ||
1993             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1994                 if (!(guest_efer & EFER_LMA))
1995                         guest_efer &= ~EFER_LME;
1996                 if (guest_efer != host_efer)
1997                         add_atomic_switch_msr(vmx, MSR_EFER,
1998                                               guest_efer, host_efer);
1999                 return false;
2000         } else {
2001                 guest_efer &= ~ignore_bits;
2002                 guest_efer |= host_efer & ignore_bits;
2003
2004                 vmx->guest_msrs[efer_offset].data = guest_efer;
2005                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2006
2007                 return true;
2008         }
2009 }
2010
2011 static unsigned long segment_base(u16 selector)
2012 {
2013         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2014         struct desc_struct *d;
2015         unsigned long table_base;
2016         unsigned long v;
2017
2018         if (!(selector & ~3))
2019                 return 0;
2020
2021         table_base = gdt->address;
2022
2023         if (selector & 4) {           /* from ldt */
2024                 u16 ldt_selector = kvm_read_ldt();
2025
2026                 if (!(ldt_selector & ~3))
2027                         return 0;
2028
2029                 table_base = segment_base(ldt_selector);
2030         }
2031         d = (struct desc_struct *)(table_base + (selector & ~7));
2032         v = get_desc_base(d);
2033 #ifdef CONFIG_X86_64
2034        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
2035                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
2036 #endif
2037         return v;
2038 }
2039
2040 static inline unsigned long kvm_read_tr_base(void)
2041 {
2042         u16 tr;
2043         asm("str %0" : "=g"(tr));
2044         return segment_base(tr);
2045 }
2046
2047 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2048 {
2049         struct vcpu_vmx *vmx = to_vmx(vcpu);
2050         int i;
2051
2052         if (vmx->host_state.loaded)
2053                 return;
2054
2055         vmx->host_state.loaded = 1;
2056         /*
2057          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
2058          * allow segment selectors with cpl > 0 or ti == 1.
2059          */
2060         vmx->host_state.ldt_sel = kvm_read_ldt();
2061         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2062         savesegment(fs, vmx->host_state.fs_sel);
2063         if (!(vmx->host_state.fs_sel & 7)) {
2064                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2065                 vmx->host_state.fs_reload_needed = 0;
2066         } else {
2067                 vmcs_write16(HOST_FS_SELECTOR, 0);
2068                 vmx->host_state.fs_reload_needed = 1;
2069         }
2070         savesegment(gs, vmx->host_state.gs_sel);
2071         if (!(vmx->host_state.gs_sel & 7))
2072                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2073         else {
2074                 vmcs_write16(HOST_GS_SELECTOR, 0);
2075                 vmx->host_state.gs_ldt_reload_needed = 1;
2076         }
2077
2078 #ifdef CONFIG_X86_64
2079         savesegment(ds, vmx->host_state.ds_sel);
2080         savesegment(es, vmx->host_state.es_sel);
2081 #endif
2082
2083 #ifdef CONFIG_X86_64
2084         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2085         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2086 #else
2087         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2088         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2089 #endif
2090
2091 #ifdef CONFIG_X86_64
2092         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2093         if (is_long_mode(&vmx->vcpu))
2094                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2095 #endif
2096         if (boot_cpu_has(X86_FEATURE_MPX))
2097                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2098         for (i = 0; i < vmx->save_nmsrs; ++i)
2099                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2100                                    vmx->guest_msrs[i].data,
2101                                    vmx->guest_msrs[i].mask);
2102 }
2103
2104 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2105 {
2106         if (!vmx->host_state.loaded)
2107                 return;
2108
2109         ++vmx->vcpu.stat.host_state_reload;
2110         vmx->host_state.loaded = 0;
2111 #ifdef CONFIG_X86_64
2112         if (is_long_mode(&vmx->vcpu))
2113                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2114 #endif
2115         if (vmx->host_state.gs_ldt_reload_needed) {
2116                 kvm_load_ldt(vmx->host_state.ldt_sel);
2117 #ifdef CONFIG_X86_64
2118                 load_gs_index(vmx->host_state.gs_sel);
2119 #else
2120                 loadsegment(gs, vmx->host_state.gs_sel);
2121 #endif
2122         }
2123         if (vmx->host_state.fs_reload_needed)
2124                 loadsegment(fs, vmx->host_state.fs_sel);
2125 #ifdef CONFIG_X86_64
2126         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2127                 loadsegment(ds, vmx->host_state.ds_sel);
2128                 loadsegment(es, vmx->host_state.es_sel);
2129         }
2130 #endif
2131         reload_tss();
2132 #ifdef CONFIG_X86_64
2133         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2134 #endif
2135         if (vmx->host_state.msr_host_bndcfgs)
2136                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2137         /*
2138          * If the FPU is not active (through the host task or
2139          * the guest vcpu), then restore the cr0.TS bit.
2140          */
2141         if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
2142                 stts();
2143         load_gdt(this_cpu_ptr(&host_gdt));
2144 }
2145
2146 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2147 {
2148         preempt_disable();
2149         __vmx_load_host_state(vmx);
2150         preempt_enable();
2151 }
2152
2153 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2154 {
2155         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2156         struct pi_desc old, new;
2157         unsigned int dest;
2158
2159         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2160                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2161                 !kvm_vcpu_apicv_active(vcpu))
2162                 return;
2163
2164         do {
2165                 old.control = new.control = pi_desc->control;
2166
2167                 /*
2168                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2169                  * are two possible cases:
2170                  * 1. After running 'pre_block', context switch
2171                  *    happened. For this case, 'sn' was set in
2172                  *    vmx_vcpu_put(), so we need to clear it here.
2173                  * 2. After running 'pre_block', we were blocked,
2174                  *    and woken up by some other guy. For this case,
2175                  *    we don't need to do anything, 'pi_post_block'
2176                  *    will do everything for us. However, we cannot
2177                  *    check whether it is case #1 or case #2 here
2178                  *    (maybe, not needed), so we also clear sn here,
2179                  *    I think it is not a big deal.
2180                  */
2181                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2182                         if (vcpu->cpu != cpu) {
2183                                 dest = cpu_physical_id(cpu);
2184
2185                                 if (x2apic_enabled())
2186                                         new.ndst = dest;
2187                                 else
2188                                         new.ndst = (dest << 8) & 0xFF00;
2189                         }
2190
2191                         /* set 'NV' to 'notification vector' */
2192                         new.nv = POSTED_INTR_VECTOR;
2193                 }
2194
2195                 /* Allow posting non-urgent interrupts */
2196                 new.sn = 0;
2197         } while (cmpxchg(&pi_desc->control, old.control,
2198                         new.control) != old.control);
2199 }
2200
2201 /*
2202  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2203  * vcpu mutex is already taken.
2204  */
2205 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2206 {
2207         struct vcpu_vmx *vmx = to_vmx(vcpu);
2208         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2209         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2210
2211         if (!vmm_exclusive)
2212                 kvm_cpu_vmxon(phys_addr);
2213         else if (!already_loaded)
2214                 loaded_vmcs_clear(vmx->loaded_vmcs);
2215
2216         if (!already_loaded) {
2217                 local_irq_disable();
2218                 crash_disable_local_vmclear(cpu);
2219
2220                 /*
2221                  * Read loaded_vmcs->cpu should be before fetching
2222                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2223                  * See the comments in __loaded_vmcs_clear().
2224                  */
2225                 smp_rmb();
2226
2227                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2228                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2229                 crash_enable_local_vmclear(cpu);
2230                 local_irq_enable();
2231         }
2232
2233         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2234                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2235                 vmcs_load(vmx->loaded_vmcs->vmcs);
2236         }
2237
2238         if (!already_loaded) {
2239                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2240                 unsigned long sysenter_esp;
2241
2242                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2243
2244                 /*
2245                  * Linux uses per-cpu TSS and GDT, so set these when switching
2246                  * processors.
2247                  */
2248                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
2249                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
2250
2251                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2252                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2253
2254                 vmx->loaded_vmcs->cpu = cpu;
2255         }
2256
2257         /* Setup TSC multiplier */
2258         if (kvm_has_tsc_control &&
2259             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) {
2260                 vmx->current_tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2261                 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2262         }
2263
2264         vmx_vcpu_pi_load(vcpu, cpu);
2265         vmx->host_pkru = read_pkru();
2266 }
2267
2268 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2269 {
2270         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2271
2272         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2273                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2274                 !kvm_vcpu_apicv_active(vcpu))
2275                 return;
2276
2277         /* Set SN when the vCPU is preempted */
2278         if (vcpu->preempted)
2279                 pi_set_sn(pi_desc);
2280 }
2281
2282 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2283 {
2284         vmx_vcpu_pi_put(vcpu);
2285
2286         __vmx_load_host_state(to_vmx(vcpu));
2287         if (!vmm_exclusive) {
2288                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2289                 vcpu->cpu = -1;
2290                 kvm_cpu_vmxoff();
2291         }
2292 }
2293
2294 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2295 {
2296         ulong cr0;
2297
2298         if (vcpu->fpu_active)
2299                 return;
2300         vcpu->fpu_active = 1;
2301         cr0 = vmcs_readl(GUEST_CR0);
2302         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2303         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2304         vmcs_writel(GUEST_CR0, cr0);
2305         update_exception_bitmap(vcpu);
2306         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
2307         if (is_guest_mode(vcpu))
2308                 vcpu->arch.cr0_guest_owned_bits &=
2309                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
2310         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2311 }
2312
2313 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2314
2315 /*
2316  * Return the cr0 value that a nested guest would read. This is a combination
2317  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2318  * its hypervisor (cr0_read_shadow).
2319  */
2320 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2321 {
2322         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2323                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2324 }
2325 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2326 {
2327         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2328                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2329 }
2330
2331 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2332 {
2333         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2334          * set this *before* calling this function.
2335          */
2336         vmx_decache_cr0_guest_bits(vcpu);
2337         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2338         update_exception_bitmap(vcpu);
2339         vcpu->arch.cr0_guest_owned_bits = 0;
2340         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2341         if (is_guest_mode(vcpu)) {
2342                 /*
2343                  * L1's specified read shadow might not contain the TS bit,
2344                  * so now that we turned on shadowing of this bit, we need to
2345                  * set this bit of the shadow. Like in nested_vmx_run we need
2346                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2347                  * up-to-date here because we just decached cr0.TS (and we'll
2348                  * only update vmcs12->guest_cr0 on nested exit).
2349                  */
2350                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2351                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2352                         (vcpu->arch.cr0 & X86_CR0_TS);
2353                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2354         } else
2355                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2356 }
2357
2358 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2359 {
2360         unsigned long rflags, save_rflags;
2361
2362         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2363                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2364                 rflags = vmcs_readl(GUEST_RFLAGS);
2365                 if (to_vmx(vcpu)->rmode.vm86_active) {
2366                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2367                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2368                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2369                 }
2370                 to_vmx(vcpu)->rflags = rflags;
2371         }
2372         return to_vmx(vcpu)->rflags;
2373 }
2374
2375 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2376 {
2377         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2378         to_vmx(vcpu)->rflags = rflags;
2379         if (to_vmx(vcpu)->rmode.vm86_active) {
2380                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2381                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2382         }
2383         vmcs_writel(GUEST_RFLAGS, rflags);
2384 }
2385
2386 static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2387 {
2388         return to_vmx(vcpu)->guest_pkru;
2389 }
2390
2391 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2392 {
2393         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2394         int ret = 0;
2395
2396         if (interruptibility & GUEST_INTR_STATE_STI)
2397                 ret |= KVM_X86_SHADOW_INT_STI;
2398         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2399                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2400
2401         return ret;
2402 }
2403
2404 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2405 {
2406         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2407         u32 interruptibility = interruptibility_old;
2408
2409         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2410
2411         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2412                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2413         else if (mask & KVM_X86_SHADOW_INT_STI)
2414                 interruptibility |= GUEST_INTR_STATE_STI;
2415
2416         if ((interruptibility != interruptibility_old))
2417                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2418 }
2419
2420 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2421 {
2422         unsigned long rip;
2423
2424         rip = kvm_rip_read(vcpu);
2425         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2426         kvm_rip_write(vcpu, rip);
2427
2428         /* skipping an emulated instruction also counts */
2429         vmx_set_interrupt_shadow(vcpu, 0);
2430 }
2431
2432 /*
2433  * KVM wants to inject page-faults which it got to the guest. This function
2434  * checks whether in a nested guest, we need to inject them to L1 or L2.
2435  */
2436 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2437 {
2438         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2439
2440         if (!(vmcs12->exception_bitmap & (1u << nr)))
2441                 return 0;
2442
2443         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2444                           vmcs_read32(VM_EXIT_INTR_INFO),
2445                           vmcs_readl(EXIT_QUALIFICATION));
2446         return 1;
2447 }
2448
2449 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2450                                 bool has_error_code, u32 error_code,
2451                                 bool reinject)
2452 {
2453         struct vcpu_vmx *vmx = to_vmx(vcpu);
2454         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2455
2456         if (!reinject && is_guest_mode(vcpu) &&
2457             nested_vmx_check_exception(vcpu, nr))
2458                 return;
2459
2460         if (has_error_code) {
2461                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2462                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2463         }
2464
2465         if (vmx->rmode.vm86_active) {
2466                 int inc_eip = 0;
2467                 if (kvm_exception_is_soft(nr))
2468                         inc_eip = vcpu->arch.event_exit_inst_len;
2469                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2470                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2471                 return;
2472         }
2473
2474         if (kvm_exception_is_soft(nr)) {
2475                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2476                              vmx->vcpu.arch.event_exit_inst_len);
2477                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2478         } else
2479                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2480
2481         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2482 }
2483
2484 static bool vmx_rdtscp_supported(void)
2485 {
2486         return cpu_has_vmx_rdtscp();
2487 }
2488
2489 static bool vmx_invpcid_supported(void)
2490 {
2491         return cpu_has_vmx_invpcid() && enable_ept;
2492 }
2493
2494 /*
2495  * Swap MSR entry in host/guest MSR entry array.
2496  */
2497 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2498 {
2499         struct shared_msr_entry tmp;
2500
2501         tmp = vmx->guest_msrs[to];
2502         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2503         vmx->guest_msrs[from] = tmp;
2504 }
2505
2506 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2507 {
2508         unsigned long *msr_bitmap;
2509
2510         if (is_guest_mode(vcpu))
2511                 msr_bitmap = vmx_msr_bitmap_nested;
2512         else if (cpu_has_secondary_exec_ctrls() &&
2513                  (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2514                   SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
2515                 if (is_long_mode(vcpu))
2516                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2517                 else
2518                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2519         } else {
2520                 if (is_long_mode(vcpu))
2521                         msr_bitmap = vmx_msr_bitmap_longmode;
2522                 else
2523                         msr_bitmap = vmx_msr_bitmap_legacy;
2524         }
2525
2526         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2527 }
2528
2529 /*
2530  * Set up the vmcs to automatically save and restore system
2531  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2532  * mode, as fiddling with msrs is very expensive.
2533  */
2534 static void setup_msrs(struct vcpu_vmx *vmx)
2535 {
2536         int save_nmsrs, index;
2537
2538         save_nmsrs = 0;
2539 #ifdef CONFIG_X86_64
2540         if (is_long_mode(&vmx->vcpu)) {
2541                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2542                 if (index >= 0)
2543                         move_msr_up(vmx, index, save_nmsrs++);
2544                 index = __find_msr_index(vmx, MSR_LSTAR);
2545                 if (index >= 0)
2546                         move_msr_up(vmx, index, save_nmsrs++);
2547                 index = __find_msr_index(vmx, MSR_CSTAR);
2548                 if (index >= 0)
2549                         move_msr_up(vmx, index, save_nmsrs++);
2550                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2551                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2552                         move_msr_up(vmx, index, save_nmsrs++);
2553                 /*
2554                  * MSR_STAR is only needed on long mode guests, and only
2555                  * if efer.sce is enabled.
2556                  */
2557                 index = __find_msr_index(vmx, MSR_STAR);
2558                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2559                         move_msr_up(vmx, index, save_nmsrs++);
2560         }
2561 #endif
2562         index = __find_msr_index(vmx, MSR_EFER);
2563         if (index >= 0 && update_transition_efer(vmx, index))
2564                 move_msr_up(vmx, index, save_nmsrs++);
2565
2566         vmx->save_nmsrs = save_nmsrs;
2567
2568         if (cpu_has_vmx_msr_bitmap())
2569                 vmx_set_msr_bitmap(&vmx->vcpu);
2570 }
2571
2572 /*
2573  * reads and returns guest's timestamp counter "register"
2574  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2575  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2576  */
2577 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2578 {
2579         u64 host_tsc, tsc_offset;
2580
2581         host_tsc = rdtsc();
2582         tsc_offset = vmcs_read64(TSC_OFFSET);
2583         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2584 }
2585
2586 /*
2587  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2588  * counter, even if a nested guest (L2) is currently running.
2589  */
2590 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2591 {
2592         u64 tsc_offset;
2593
2594         tsc_offset = is_guest_mode(vcpu) ?
2595                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2596                 vmcs_read64(TSC_OFFSET);
2597         return host_tsc + tsc_offset;
2598 }
2599
2600 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2601 {
2602         return vmcs_read64(TSC_OFFSET);
2603 }
2604
2605 /*
2606  * writes 'offset' into guest's timestamp counter offset register
2607  */
2608 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2609 {
2610         if (is_guest_mode(vcpu)) {
2611                 /*
2612                  * We're here if L1 chose not to trap WRMSR to TSC. According
2613                  * to the spec, this should set L1's TSC; The offset that L1
2614                  * set for L2 remains unchanged, and still needs to be added
2615                  * to the newly set TSC to get L2's TSC.
2616                  */
2617                 struct vmcs12 *vmcs12;
2618                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2619                 /* recalculate vmcs02.TSC_OFFSET: */
2620                 vmcs12 = get_vmcs12(vcpu);
2621                 vmcs_write64(TSC_OFFSET, offset +
2622                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2623                          vmcs12->tsc_offset : 0));
2624         } else {
2625                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2626                                            vmcs_read64(TSC_OFFSET), offset);
2627                 vmcs_write64(TSC_OFFSET, offset);
2628         }
2629 }
2630
2631 static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment)
2632 {
2633         u64 offset = vmcs_read64(TSC_OFFSET);
2634
2635         vmcs_write64(TSC_OFFSET, offset + adjustment);
2636         if (is_guest_mode(vcpu)) {
2637                 /* Even when running L2, the adjustment needs to apply to L1 */
2638                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2639         } else
2640                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2641                                            offset + adjustment);
2642 }
2643
2644 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2645 {
2646         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2647         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2648 }
2649
2650 /*
2651  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2652  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2653  * all guests if the "nested" module option is off, and can also be disabled
2654  * for a single guest by disabling its VMX cpuid bit.
2655  */
2656 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2657 {
2658         return nested && guest_cpuid_has_vmx(vcpu);
2659 }
2660
2661 /*
2662  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2663  * returned for the various VMX controls MSRs when nested VMX is enabled.
2664  * The same values should also be used to verify that vmcs12 control fields are
2665  * valid during nested entry from L1 to L2.
2666  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2667  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2668  * bit in the high half is on if the corresponding bit in the control field
2669  * may be on. See also vmx_control_verify().
2670  */
2671 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2672 {
2673         /*
2674          * Note that as a general rule, the high half of the MSRs (bits in
2675          * the control fields which may be 1) should be initialized by the
2676          * intersection of the underlying hardware's MSR (i.e., features which
2677          * can be supported) and the list of features we want to expose -
2678          * because they are known to be properly supported in our code.
2679          * Also, usually, the low half of the MSRs (bits which must be 1) can
2680          * be set to 0, meaning that L1 may turn off any of these bits. The
2681          * reason is that if one of these bits is necessary, it will appear
2682          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2683          * fields of vmcs01 and vmcs02, will turn these bits off - and
2684          * nested_vmx_exit_handled() will not pass related exits to L1.
2685          * These rules have exceptions below.
2686          */
2687
2688         /* pin-based controls */
2689         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2690                 vmx->nested.nested_vmx_pinbased_ctls_low,
2691                 vmx->nested.nested_vmx_pinbased_ctls_high);
2692         vmx->nested.nested_vmx_pinbased_ctls_low |=
2693                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2694         vmx->nested.nested_vmx_pinbased_ctls_high &=
2695                 PIN_BASED_EXT_INTR_MASK |
2696                 PIN_BASED_NMI_EXITING |
2697                 PIN_BASED_VIRTUAL_NMIS;
2698         vmx->nested.nested_vmx_pinbased_ctls_high |=
2699                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2700                 PIN_BASED_VMX_PREEMPTION_TIMER;
2701         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2702                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2703                         PIN_BASED_POSTED_INTR;
2704
2705         /* exit controls */
2706         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2707                 vmx->nested.nested_vmx_exit_ctls_low,
2708                 vmx->nested.nested_vmx_exit_ctls_high);
2709         vmx->nested.nested_vmx_exit_ctls_low =
2710                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2711
2712         vmx->nested.nested_vmx_exit_ctls_high &=
2713 #ifdef CONFIG_X86_64
2714                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2715 #endif
2716                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2717         vmx->nested.nested_vmx_exit_ctls_high |=
2718                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2719                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2720                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2721
2722         if (kvm_mpx_supported())
2723                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2724
2725         /* We support free control of debug control saving. */
2726         vmx->nested.nested_vmx_true_exit_ctls_low =
2727                 vmx->nested.nested_vmx_exit_ctls_low &
2728                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2729
2730         /* entry controls */
2731         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2732                 vmx->nested.nested_vmx_entry_ctls_low,
2733                 vmx->nested.nested_vmx_entry_ctls_high);
2734         vmx->nested.nested_vmx_entry_ctls_low =
2735                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2736         vmx->nested.nested_vmx_entry_ctls_high &=
2737 #ifdef CONFIG_X86_64
2738                 VM_ENTRY_IA32E_MODE |
2739 #endif
2740                 VM_ENTRY_LOAD_IA32_PAT;
2741         vmx->nested.nested_vmx_entry_ctls_high |=
2742                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2743         if (kvm_mpx_supported())
2744                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2745
2746         /* We support free control of debug control loading. */
2747         vmx->nested.nested_vmx_true_entry_ctls_low =
2748                 vmx->nested.nested_vmx_entry_ctls_low &
2749                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2750
2751         /* cpu-based controls */
2752         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2753                 vmx->nested.nested_vmx_procbased_ctls_low,
2754                 vmx->nested.nested_vmx_procbased_ctls_high);
2755         vmx->nested.nested_vmx_procbased_ctls_low =
2756                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2757         vmx->nested.nested_vmx_procbased_ctls_high &=
2758                 CPU_BASED_VIRTUAL_INTR_PENDING |
2759                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2760                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2761                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2762                 CPU_BASED_CR3_STORE_EXITING |
2763 #ifdef CONFIG_X86_64
2764                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2765 #endif
2766                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2767                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2768                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2769                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2770                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2771         /*
2772          * We can allow some features even when not supported by the
2773          * hardware. For example, L1 can specify an MSR bitmap - and we
2774          * can use it to avoid exits to L1 - even when L0 runs L2
2775          * without MSR bitmaps.
2776          */
2777         vmx->nested.nested_vmx_procbased_ctls_high |=
2778                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2779                 CPU_BASED_USE_MSR_BITMAPS;
2780
2781         /* We support free control of CR3 access interception. */
2782         vmx->nested.nested_vmx_true_procbased_ctls_low =
2783                 vmx->nested.nested_vmx_procbased_ctls_low &
2784                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2785
2786         /* secondary cpu-based controls */
2787         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2788                 vmx->nested.nested_vmx_secondary_ctls_low,
2789                 vmx->nested.nested_vmx_secondary_ctls_high);
2790         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2791         vmx->nested.nested_vmx_secondary_ctls_high &=
2792                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2793                 SECONDARY_EXEC_RDTSCP |
2794                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2795                 SECONDARY_EXEC_ENABLE_VPID |
2796                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2797                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2798                 SECONDARY_EXEC_WBINVD_EXITING |
2799                 SECONDARY_EXEC_XSAVES;
2800
2801         if (enable_ept) {
2802                 /* nested EPT: emulate EPT also to L1 */
2803                 vmx->nested.nested_vmx_secondary_ctls_high |=
2804                         SECONDARY_EXEC_ENABLE_EPT;
2805                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2806                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2807                          VMX_EPT_INVEPT_BIT;
2808                 if (cpu_has_vmx_ept_execute_only())
2809                         vmx->nested.nested_vmx_ept_caps |=
2810                                 VMX_EPT_EXECUTE_ONLY_BIT;
2811                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2812                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2813                         VMX_EPT_EXTENT_CONTEXT_BIT;
2814         } else
2815                 vmx->nested.nested_vmx_ept_caps = 0;
2816
2817         /*
2818          * Old versions of KVM use the single-context version without
2819          * checking for support, so declare that it is supported even
2820          * though it is treated as global context.  The alternative is
2821          * not failing the single-context invvpid, and it is worse.
2822          */
2823         if (enable_vpid)
2824                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2825                                 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |
2826                                 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
2827         else
2828                 vmx->nested.nested_vmx_vpid_caps = 0;
2829
2830         if (enable_unrestricted_guest)
2831                 vmx->nested.nested_vmx_secondary_ctls_high |=
2832                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2833
2834         /* miscellaneous data */
2835         rdmsr(MSR_IA32_VMX_MISC,
2836                 vmx->nested.nested_vmx_misc_low,
2837                 vmx->nested.nested_vmx_misc_high);
2838         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2839         vmx->nested.nested_vmx_misc_low |=
2840                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2841                 VMX_MISC_ACTIVITY_HLT;
2842         vmx->nested.nested_vmx_misc_high = 0;
2843 }
2844
2845 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2846 {
2847         /*
2848          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2849          */
2850         return ((control & high) | low) == control;
2851 }
2852
2853 static inline u64 vmx_control_msr(u32 low, u32 high)
2854 {
2855         return low | ((u64)high << 32);
2856 }
2857
2858 /* Returns 0 on success, non-0 otherwise. */
2859 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2860 {
2861         struct vcpu_vmx *vmx = to_vmx(vcpu);
2862
2863         switch (msr_index) {
2864         case MSR_IA32_VMX_BASIC:
2865                 /*
2866                  * This MSR reports some information about VMX support. We
2867                  * should return information about the VMX we emulate for the
2868                  * guest, and the VMCS structure we give it - not about the
2869                  * VMX support of the underlying hardware.
2870                  */
2871                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2872                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2873                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2874                 break;
2875         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2876         case MSR_IA32_VMX_PINBASED_CTLS:
2877                 *pdata = vmx_control_msr(
2878                         vmx->nested.nested_vmx_pinbased_ctls_low,
2879                         vmx->nested.nested_vmx_pinbased_ctls_high);
2880                 break;
2881         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2882                 *pdata = vmx_control_msr(
2883                         vmx->nested.nested_vmx_true_procbased_ctls_low,
2884                         vmx->nested.nested_vmx_procbased_ctls_high);
2885                 break;
2886         case MSR_IA32_VMX_PROCBASED_CTLS:
2887                 *pdata = vmx_control_msr(
2888                         vmx->nested.nested_vmx_procbased_ctls_low,
2889                         vmx->nested.nested_vmx_procbased_ctls_high);
2890                 break;
2891         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2892                 *pdata = vmx_control_msr(
2893                         vmx->nested.nested_vmx_true_exit_ctls_low,
2894                         vmx->nested.nested_vmx_exit_ctls_high);
2895                 break;
2896         case MSR_IA32_VMX_EXIT_CTLS:
2897                 *pdata = vmx_control_msr(
2898                         vmx->nested.nested_vmx_exit_ctls_low,
2899                         vmx->nested.nested_vmx_exit_ctls_high);
2900                 break;
2901         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2902                 *pdata = vmx_control_msr(
2903                         vmx->nested.nested_vmx_true_entry_ctls_low,
2904                         vmx->nested.nested_vmx_entry_ctls_high);
2905                 break;
2906         case MSR_IA32_VMX_ENTRY_CTLS:
2907                 *pdata = vmx_control_msr(
2908                         vmx->nested.nested_vmx_entry_ctls_low,
2909                         vmx->nested.nested_vmx_entry_ctls_high);
2910                 break;
2911         case MSR_IA32_VMX_MISC:
2912                 *pdata = vmx_control_msr(
2913                         vmx->nested.nested_vmx_misc_low,
2914                         vmx->nested.nested_vmx_misc_high);
2915                 break;
2916         /*
2917          * These MSRs specify bits which the guest must keep fixed (on or off)
2918          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2919          * We picked the standard core2 setting.
2920          */
2921 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2922 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2923         case MSR_IA32_VMX_CR0_FIXED0:
2924                 *pdata = VMXON_CR0_ALWAYSON;
2925                 break;
2926         case MSR_IA32_VMX_CR0_FIXED1:
2927                 *pdata = -1ULL;
2928                 break;
2929         case MSR_IA32_VMX_CR4_FIXED0:
2930                 *pdata = VMXON_CR4_ALWAYSON;
2931                 break;
2932         case MSR_IA32_VMX_CR4_FIXED1:
2933                 *pdata = -1ULL;
2934                 break;
2935         case MSR_IA32_VMX_VMCS_ENUM:
2936                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2937                 break;
2938         case MSR_IA32_VMX_PROCBASED_CTLS2:
2939                 *pdata = vmx_control_msr(
2940                         vmx->nested.nested_vmx_secondary_ctls_low,
2941                         vmx->nested.nested_vmx_secondary_ctls_high);
2942                 break;
2943         case MSR_IA32_VMX_EPT_VPID_CAP:
2944                 *pdata = vmx->nested.nested_vmx_ept_caps |
2945                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
2946                 break;
2947         default:
2948                 return 1;
2949         }
2950
2951         return 0;
2952 }
2953
2954 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
2955                                                  uint64_t val)
2956 {
2957         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
2958
2959         return !(val & ~valid_bits);
2960 }
2961
2962 /*
2963  * Reads an msr value (of 'msr_index') into 'pdata'.
2964  * Returns 0 on success, non-0 otherwise.
2965  * Assumes vcpu_load() was already called.
2966  */
2967 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2968 {
2969         struct shared_msr_entry *msr;
2970
2971         switch (msr_info->index) {
2972 #ifdef CONFIG_X86_64
2973         case MSR_FS_BASE:
2974                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
2975                 break;
2976         case MSR_GS_BASE:
2977                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
2978                 break;
2979         case MSR_KERNEL_GS_BASE:
2980                 vmx_load_host_state(to_vmx(vcpu));
2981                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2982                 break;
2983 #endif
2984         case MSR_EFER:
2985                 return kvm_get_msr_common(vcpu, msr_info);
2986         case MSR_IA32_TSC:
2987                 msr_info->data = guest_read_tsc(vcpu);
2988                 break;
2989         case MSR_IA32_SYSENTER_CS:
2990                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
2991                 break;
2992         case MSR_IA32_SYSENTER_EIP:
2993                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
2994                 break;
2995         case MSR_IA32_SYSENTER_ESP:
2996                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
2997                 break;
2998         case MSR_IA32_BNDCFGS:
2999                 if (!kvm_mpx_supported())
3000                         return 1;
3001                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3002                 break;
3003         case MSR_IA32_MCG_EXT_CTL:
3004                 if (!msr_info->host_initiated &&
3005                     !(to_vmx(vcpu)->msr_ia32_feature_control &
3006                       FEATURE_CONTROL_LMCE))
3007                         return 1;
3008                 msr_info->data = vcpu->arch.mcg_ext_ctl;
3009                 break;
3010         case MSR_IA32_FEATURE_CONTROL:
3011                 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
3012                 break;
3013         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3014                 if (!nested_vmx_allowed(vcpu))
3015                         return 1;
3016                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
3017         case MSR_IA32_XSS:
3018                 if (!vmx_xsaves_supported())
3019                         return 1;
3020                 msr_info->data = vcpu->arch.ia32_xss;
3021                 break;
3022         case MSR_TSC_AUX:
3023                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3024                         return 1;
3025                 /* Otherwise falls through */
3026         default:
3027                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3028                 if (msr) {
3029                         msr_info->data = msr->data;
3030                         break;
3031                 }
3032                 return kvm_get_msr_common(vcpu, msr_info);
3033         }
3034
3035         return 0;
3036 }
3037
3038 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3039
3040 /*
3041  * Writes msr value into into the appropriate "register".
3042  * Returns 0 on success, non-0 otherwise.
3043  * Assumes vcpu_load() was already called.
3044  */
3045 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3046 {
3047         struct vcpu_vmx *vmx = to_vmx(vcpu);
3048         struct shared_msr_entry *msr;
3049         int ret = 0;
3050         u32 msr_index = msr_info->index;
3051         u64 data = msr_info->data;
3052
3053         switch (msr_index) {
3054         case MSR_EFER:
3055                 ret = kvm_set_msr_common(vcpu, msr_info);
3056                 break;
3057 #ifdef CONFIG_X86_64
3058         case MSR_FS_BASE:
3059                 vmx_segment_cache_clear(vmx);
3060                 vmcs_writel(GUEST_FS_BASE, data);
3061                 break;
3062         case MSR_GS_BASE:
3063                 vmx_segment_cache_clear(vmx);
3064                 vmcs_writel(GUEST_GS_BASE, data);
3065                 break;
3066         case MSR_KERNEL_GS_BASE:
3067                 vmx_load_host_state(vmx);
3068                 vmx->msr_guest_kernel_gs_base = data;
3069                 break;
3070 #endif
3071         case MSR_IA32_SYSENTER_CS:
3072                 vmcs_write32(GUEST_SYSENTER_CS, data);
3073                 break;
3074         case MSR_IA32_SYSENTER_EIP:
3075                 vmcs_writel(GUEST_SYSENTER_EIP, data);
3076                 break;
3077         case MSR_IA32_SYSENTER_ESP:
3078                 vmcs_writel(GUEST_SYSENTER_ESP, data);
3079                 break;
3080         case MSR_IA32_BNDCFGS:
3081                 if (!kvm_mpx_supported())
3082                         return 1;
3083                 vmcs_write64(GUEST_BNDCFGS, data);
3084                 break;
3085         case MSR_IA32_TSC:
3086                 kvm_write_tsc(vcpu, msr_info);
3087                 break;
3088         case MSR_IA32_CR_PAT:
3089                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3090                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3091                                 return 1;
3092                         vmcs_write64(GUEST_IA32_PAT, data);
3093                         vcpu->arch.pat = data;
3094                         break;
3095                 }
3096                 ret = kvm_set_msr_common(vcpu, msr_info);
3097                 break;
3098         case MSR_IA32_TSC_ADJUST:
3099                 ret = kvm_set_msr_common(vcpu, msr_info);
3100                 break;
3101         case MSR_IA32_MCG_EXT_CTL:
3102                 if ((!msr_info->host_initiated &&
3103                      !(to_vmx(vcpu)->msr_ia32_feature_control &
3104                        FEATURE_CONTROL_LMCE)) ||
3105                     (data & ~MCG_EXT_CTL_LMCE_EN))
3106                         return 1;
3107                 vcpu->arch.mcg_ext_ctl = data;
3108                 break;
3109         case MSR_IA32_FEATURE_CONTROL:
3110                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3111                     (to_vmx(vcpu)->msr_ia32_feature_control &
3112                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3113                         return 1;
3114                 vmx->msr_ia32_feature_control = data;
3115                 if (msr_info->host_initiated && data == 0)
3116                         vmx_leave_nested(vcpu);
3117                 break;
3118         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3119                 return 1; /* they are read-only */
3120         case MSR_IA32_XSS:
3121                 if (!vmx_xsaves_supported())
3122                         return 1;
3123                 /*
3124                  * The only supported bit as of Skylake is bit 8, but
3125                  * it is not supported on KVM.
3126                  */
3127                 if (data != 0)
3128                         return 1;
3129                 vcpu->arch.ia32_xss = data;
3130                 if (vcpu->arch.ia32_xss != host_xss)
3131                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3132                                 vcpu->arch.ia32_xss, host_xss);
3133                 else
3134                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3135                 break;
3136         case MSR_TSC_AUX:
3137                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3138                         return 1;
3139                 /* Check reserved bit, higher 32 bits should be zero */
3140                 if ((data >> 32) != 0)
3141                         return 1;
3142                 /* Otherwise falls through */
3143         default:
3144                 msr = find_msr_entry(vmx, msr_index);
3145                 if (msr) {
3146                         u64 old_msr_data = msr->data;
3147                         msr->data = data;
3148                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3149                                 preempt_disable();
3150                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3151                                                          msr->mask);
3152                                 preempt_enable();
3153                                 if (ret)
3154                                         msr->data = old_msr_data;
3155                         }
3156                         break;
3157                 }
3158                 ret = kvm_set_msr_common(vcpu, msr_info);
3159         }
3160
3161         return ret;
3162 }
3163
3164 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3165 {
3166         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3167         switch (reg) {
3168         case VCPU_REGS_RSP:
3169                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3170                 break;
3171         case VCPU_REGS_RIP:
3172                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3173                 break;
3174         case VCPU_EXREG_PDPTR:
3175                 if (enable_ept)
3176                         ept_save_pdptrs(vcpu);
3177                 break;
3178         default:
3179                 break;
3180         }
3181 }
3182
3183 static __init int cpu_has_kvm_support(void)
3184 {
3185         return cpu_has_vmx();
3186 }
3187
3188 static __init int vmx_disabled_by_bios(void)
3189 {
3190         u64 msr;
3191
3192         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3193         if (msr & FEATURE_CONTROL_LOCKED) {
3194                 /* launched w/ TXT and VMX disabled */
3195                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3196                         && tboot_enabled())
3197                         return 1;
3198                 /* launched w/o TXT and VMX only enabled w/ TXT */
3199                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3200                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3201                         && !tboot_enabled()) {
3202                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3203                                 "activate TXT before enabling KVM\n");
3204                         return 1;
3205                 }
3206                 /* launched w/o TXT and VMX disabled */
3207                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3208                         && !tboot_enabled())
3209                         return 1;
3210         }
3211
3212         return 0;
3213 }
3214
3215 static void kvm_cpu_vmxon(u64 addr)
3216 {
3217         intel_pt_handle_vmx(1);
3218
3219         asm volatile (ASM_VMX_VMXON_RAX
3220                         : : "a"(&addr), "m"(addr)
3221                         : "memory", "cc");
3222 }
3223
3224 static int hardware_enable(void)
3225 {
3226         int cpu = raw_smp_processor_id();
3227         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3228         u64 old, test_bits;
3229
3230         if (cr4_read_shadow() & X86_CR4_VMXE)
3231                 return -EBUSY;
3232
3233         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3234         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3235         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3236
3237         /*
3238          * Now we can enable the vmclear operation in kdump
3239          * since the loaded_vmcss_on_cpu list on this cpu
3240          * has been initialized.
3241          *
3242          * Though the cpu is not in VMX operation now, there
3243          * is no problem to enable the vmclear operation
3244          * for the loaded_vmcss_on_cpu list is empty!
3245          */
3246         crash_enable_local_vmclear(cpu);
3247
3248         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3249
3250         test_bits = FEATURE_CONTROL_LOCKED;
3251         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3252         if (tboot_enabled())
3253                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3254
3255         if ((old & test_bits) != test_bits) {
3256                 /* enable and lock */
3257                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3258         }
3259         cr4_set_bits(X86_CR4_VMXE);
3260
3261         if (vmm_exclusive) {
3262                 kvm_cpu_vmxon(phys_addr);
3263                 ept_sync_global();
3264         }
3265
3266         native_store_gdt(this_cpu_ptr(&host_gdt));
3267
3268         return 0;
3269 }
3270
3271 static void vmclear_local_loaded_vmcss(void)
3272 {
3273         int cpu = raw_smp_processor_id();
3274         struct loaded_vmcs *v, *n;
3275
3276         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3277                                  loaded_vmcss_on_cpu_link)
3278                 __loaded_vmcs_clear(v);
3279 }
3280
3281
3282 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3283  * tricks.
3284  */
3285 static void kvm_cpu_vmxoff(void)
3286 {
3287         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3288
3289         intel_pt_handle_vmx(0);
3290 }
3291
3292 static void hardware_disable(void)
3293 {
3294         if (vmm_exclusive) {
3295                 vmclear_local_loaded_vmcss();
3296                 kvm_cpu_vmxoff();
3297         }
3298         cr4_clear_bits(X86_CR4_VMXE);
3299 }
3300
3301 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3302                                       u32 msr, u32 *result)
3303 {
3304         u32 vmx_msr_low, vmx_msr_high;
3305         u32 ctl = ctl_min | ctl_opt;
3306
3307         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3308
3309         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3310         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3311
3312         /* Ensure minimum (required) set of control bits are supported. */
3313         if (ctl_min & ~ctl)
3314                 return -EIO;
3315
3316         *result = ctl;
3317         return 0;
3318 }
3319
3320 static __init bool allow_1_setting(u32 msr, u32 ctl)
3321 {
3322         u32 vmx_msr_low, vmx_msr_high;
3323
3324         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3325         return vmx_msr_high & ctl;
3326 }
3327
3328 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3329 {
3330         u32 vmx_msr_low, vmx_msr_high;
3331         u32 min, opt, min2, opt2;
3332         u32 _pin_based_exec_control = 0;
3333         u32 _cpu_based_exec_control = 0;
3334         u32 _cpu_based_2nd_exec_control = 0;
3335         u32 _vmexit_control = 0;
3336         u32 _vmentry_control = 0;
3337
3338         min = CPU_BASED_HLT_EXITING |
3339 #ifdef CONFIG_X86_64
3340               CPU_BASED_CR8_LOAD_EXITING |
3341               CPU_BASED_CR8_STORE_EXITING |
3342 #endif
3343               CPU_BASED_CR3_LOAD_EXITING |
3344               CPU_BASED_CR3_STORE_EXITING |
3345               CPU_BASED_USE_IO_BITMAPS |
3346               CPU_BASED_MOV_DR_EXITING |
3347               CPU_BASED_USE_TSC_OFFSETING |
3348               CPU_BASED_MWAIT_EXITING |
3349               CPU_BASED_MONITOR_EXITING |
3350               CPU_BASED_INVLPG_EXITING |
3351               CPU_BASED_RDPMC_EXITING;
3352
3353         opt = CPU_BASED_TPR_SHADOW |
3354               CPU_BASED_USE_MSR_BITMAPS |
3355               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3356         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3357                                 &_cpu_based_exec_control) < 0)
3358                 return -EIO;
3359 #ifdef CONFIG_X86_64
3360         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3361                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3362                                            ~CPU_BASED_CR8_STORE_EXITING;
3363 #endif
3364         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3365                 min2 = 0;
3366                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3367                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3368                         SECONDARY_EXEC_WBINVD_EXITING |
3369                         SECONDARY_EXEC_ENABLE_VPID |
3370                         SECONDARY_EXEC_ENABLE_EPT |
3371                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3372                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3373                         SECONDARY_EXEC_RDTSCP |
3374                         SECONDARY_EXEC_ENABLE_INVPCID |
3375                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3376                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3377                         SECONDARY_EXEC_SHADOW_VMCS |
3378                         SECONDARY_EXEC_XSAVES |
3379                         SECONDARY_EXEC_ENABLE_PML |
3380                         SECONDARY_EXEC_TSC_SCALING;
3381                 if (adjust_vmx_controls(min2, opt2,
3382                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3383                                         &_cpu_based_2nd_exec_control) < 0)
3384                         return -EIO;
3385         }
3386 #ifndef CONFIG_X86_64
3387         if (!(_cpu_based_2nd_exec_control &
3388                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3389                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3390 #endif
3391
3392         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3393                 _cpu_based_2nd_exec_control &= ~(
3394                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3395                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3396                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3397
3398         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3399                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3400                    enabled */
3401                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3402                                              CPU_BASED_CR3_STORE_EXITING |
3403                                              CPU_BASED_INVLPG_EXITING);
3404                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3405                       vmx_capability.ept, vmx_capability.vpid);
3406         }
3407
3408         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
3409 #ifdef CONFIG_X86_64
3410         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3411 #endif
3412         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3413                 VM_EXIT_CLEAR_BNDCFGS;
3414         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3415                                 &_vmexit_control) < 0)
3416                 return -EIO;
3417
3418         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3419         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
3420                  PIN_BASED_VMX_PREEMPTION_TIMER;
3421         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3422                                 &_pin_based_exec_control) < 0)
3423                 return -EIO;
3424
3425         if (cpu_has_broken_vmx_preemption_timer())
3426                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3427         if (!(_cpu_based_2nd_exec_control &
3428                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
3429                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3430
3431         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3432         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3433         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3434                                 &_vmentry_control) < 0)
3435                 return -EIO;
3436
3437         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3438
3439         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3440         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3441                 return -EIO;
3442
3443 #ifdef CONFIG_X86_64
3444         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3445         if (vmx_msr_high & (1u<<16))
3446                 return -EIO;
3447 #endif
3448
3449         /* Require Write-Back (WB) memory type for VMCS accesses. */
3450         if (((vmx_msr_high >> 18) & 15) != 6)
3451                 return -EIO;
3452
3453         vmcs_conf->size = vmx_msr_high & 0x1fff;
3454         vmcs_conf->order = get_order(vmcs_config.size);
3455         vmcs_conf->revision_id = vmx_msr_low;
3456
3457         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3458         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3459         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3460         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3461         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3462
3463         cpu_has_load_ia32_efer =
3464                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3465                                 VM_ENTRY_LOAD_IA32_EFER)
3466                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3467                                    VM_EXIT_LOAD_IA32_EFER);
3468
3469         cpu_has_load_perf_global_ctrl =
3470                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3471                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3472                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3473                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3474
3475         /*
3476          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3477          * but due to errata below it can't be used. Workaround is to use
3478          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3479          *
3480          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3481          *
3482          * AAK155             (model 26)
3483          * AAP115             (model 30)
3484          * AAT100             (model 37)
3485          * BC86,AAY89,BD102   (model 44)
3486          * BA97               (model 46)
3487          *
3488          */
3489         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3490                 switch (boot_cpu_data.x86_model) {
3491                 case 26:
3492                 case 30:
3493                 case 37:
3494                 case 44:
3495                 case 46:
3496                         cpu_has_load_perf_global_ctrl = false;
3497                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3498                                         "does not work properly. Using workaround\n");
3499                         break;
3500                 default:
3501                         break;
3502                 }
3503         }
3504
3505         if (boot_cpu_has(X86_FEATURE_XSAVES))
3506                 rdmsrl(MSR_IA32_XSS, host_xss);
3507
3508         return 0;
3509 }
3510
3511 static struct vmcs *alloc_vmcs_cpu(int cpu)
3512 {
3513         int node = cpu_to_node(cpu);
3514         struct page *pages;
3515         struct vmcs *vmcs;
3516
3517         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3518         if (!pages)
3519                 return NULL;
3520         vmcs = page_address(pages);
3521         memset(vmcs, 0, vmcs_config.size);
3522         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3523         return vmcs;
3524 }
3525
3526 static struct vmcs *alloc_vmcs(void)
3527 {
3528         return alloc_vmcs_cpu(raw_smp_processor_id());
3529 }
3530
3531 static void free_vmcs(struct vmcs *vmcs)
3532 {
3533         free_pages((unsigned long)vmcs, vmcs_config.order);
3534 }
3535
3536 /*
3537  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3538  */
3539 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3540 {
3541         if (!loaded_vmcs->vmcs)
3542                 return;
3543         loaded_vmcs_clear(loaded_vmcs);
3544         free_vmcs(loaded_vmcs->vmcs);
3545         loaded_vmcs->vmcs = NULL;
3546 }
3547
3548 static void free_kvm_area(void)
3549 {
3550         int cpu;
3551
3552         for_each_possible_cpu(cpu) {
3553                 free_vmcs(per_cpu(vmxarea, cpu));
3554                 per_cpu(vmxarea, cpu) = NULL;
3555         }
3556 }
3557
3558 static void init_vmcs_shadow_fields(void)
3559 {
3560         int i, j;
3561
3562         /* No checks for read only fields yet */
3563
3564         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3565                 switch (shadow_read_write_fields[i]) {
3566                 case GUEST_BNDCFGS:
3567                         if (!kvm_mpx_supported())
3568                                 continue;
3569                         break;
3570                 default:
3571                         break;
3572                 }
3573
3574                 if (j < i)
3575                         shadow_read_write_fields[j] =
3576                                 shadow_read_write_fields[i];
3577                 j++;
3578         }
3579         max_shadow_read_write_fields = j;
3580
3581         /* shadowed fields guest access without vmexit */
3582         for (i = 0; i < max_shadow_read_write_fields; i++) {
3583                 clear_bit(shadow_read_write_fields[i],
3584                           vmx_vmwrite_bitmap);
3585                 clear_bit(shadow_read_write_fields[i],
3586                           vmx_vmread_bitmap);
3587         }
3588         for (i = 0; i < max_shadow_read_only_fields; i++)
3589                 clear_bit(shadow_read_only_fields[i],
3590                           vmx_vmread_bitmap);
3591 }
3592
3593 static __init int alloc_kvm_area(void)
3594 {
3595         int cpu;
3596
3597         for_each_possible_cpu(cpu) {
3598                 struct vmcs *vmcs;
3599
3600                 vmcs = alloc_vmcs_cpu(cpu);
3601                 if (!vmcs) {
3602                         free_kvm_area();
3603                         return -ENOMEM;
3604                 }
3605
3606                 per_cpu(vmxarea, cpu) = vmcs;
3607         }
3608         return 0;
3609 }
3610
3611 static bool emulation_required(struct kvm_vcpu *vcpu)
3612 {
3613         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3614 }
3615
3616 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3617                 struct kvm_segment *save)
3618 {
3619         if (!emulate_invalid_guest_state) {
3620                 /*
3621                  * CS and SS RPL should be equal during guest entry according
3622                  * to VMX spec, but in reality it is not always so. Since vcpu
3623                  * is in the middle of the transition from real mode to
3624                  * protected mode it is safe to assume that RPL 0 is a good
3625                  * default value.
3626                  */
3627                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3628                         save->selector &= ~SEGMENT_RPL_MASK;
3629                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3630                 save->s = 1;
3631         }
3632         vmx_set_segment(vcpu, save, seg);
3633 }
3634
3635 static void enter_pmode(struct kvm_vcpu *vcpu)
3636 {
3637         unsigned long flags;
3638         struct vcpu_vmx *vmx = to_vmx(vcpu);
3639
3640         /*
3641          * Update real mode segment cache. It may be not up-to-date if sement
3642          * register was written while vcpu was in a guest mode.
3643          */
3644         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3645         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3646         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3647         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3648         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3649         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3650
3651         vmx->rmode.vm86_active = 0;
3652
3653         vmx_segment_cache_clear(vmx);
3654
3655         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3656
3657         flags = vmcs_readl(GUEST_RFLAGS);
3658         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3659         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3660         vmcs_writel(GUEST_RFLAGS, flags);
3661
3662         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3663                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3664
3665         update_exception_bitmap(vcpu);
3666
3667         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3668         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3669         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3670         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3671         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3672         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3673 }
3674
3675 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3676 {
3677         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3678         struct kvm_segment var = *save;
3679
3680         var.dpl = 0x3;
3681         if (seg == VCPU_SREG_CS)
3682                 var.type = 0x3;
3683
3684         if (!emulate_invalid_guest_state) {
3685                 var.selector = var.base >> 4;
3686                 var.base = var.base & 0xffff0;
3687                 var.limit = 0xffff;
3688                 var.g = 0;
3689                 var.db = 0;
3690                 var.present = 1;
3691                 var.s = 1;
3692                 var.l = 0;
3693                 var.unusable = 0;
3694                 var.type = 0x3;
3695                 var.avl = 0;
3696                 if (save->base & 0xf)
3697                         printk_once(KERN_WARNING "kvm: segment base is not "
3698                                         "paragraph aligned when entering "
3699                                         "protected mode (seg=%d)", seg);
3700         }
3701
3702         vmcs_write16(sf->selector, var.selector);
3703         vmcs_write32(sf->base, var.base);
3704         vmcs_write32(sf->limit, var.limit);
3705         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3706 }
3707
3708 static void enter_rmode(struct kvm_vcpu *vcpu)
3709 {
3710         unsigned long flags;
3711         struct vcpu_vmx *vmx = to_vmx(vcpu);
3712
3713         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3714         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3715         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3716         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3717         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3718         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3719         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3720
3721         vmx->rmode.vm86_active = 1;
3722
3723         /*
3724          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3725          * vcpu. Warn the user that an update is overdue.
3726          */
3727         if (!vcpu->kvm->arch.tss_addr)
3728                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3729                              "called before entering vcpu\n");
3730
3731         vmx_segment_cache_clear(vmx);
3732
3733         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3734         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3735         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3736
3737         flags = vmcs_readl(GUEST_RFLAGS);
3738         vmx->rmode.save_rflags = flags;
3739
3740         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3741
3742         vmcs_writel(GUEST_RFLAGS, flags);
3743         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3744         update_exception_bitmap(vcpu);
3745
3746         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3747         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3748         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3749         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3750         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3751         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3752
3753         kvm_mmu_reset_context(vcpu);
3754 }
3755
3756 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3757 {
3758         struct vcpu_vmx *vmx = to_vmx(vcpu);
3759         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3760
3761         if (!msr)
3762                 return;
3763
3764         /*
3765          * Force kernel_gs_base reloading before EFER changes, as control
3766          * of this msr depends on is_long_mode().
3767          */
3768         vmx_load_host_state(to_vmx(vcpu));
3769         vcpu->arch.efer = efer;
3770         if (efer & EFER_LMA) {
3771                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3772                 msr->data = efer;
3773         } else {
3774                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3775
3776                 msr->data = efer & ~EFER_LME;
3777         }
3778         setup_msrs(vmx);
3779 }
3780
3781 #ifdef CONFIG_X86_64
3782
3783 static void enter_lmode(struct kvm_vcpu *vcpu)
3784 {
3785         u32 guest_tr_ar;
3786
3787         vmx_segment_cache_clear(to_vmx(vcpu));
3788
3789         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3790         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3791                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3792                                      __func__);
3793                 vmcs_write32(GUEST_TR_AR_BYTES,
3794                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3795                              | VMX_AR_TYPE_BUSY_64_TSS);
3796         }
3797         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3798 }
3799
3800 static void exit_lmode(struct kvm_vcpu *vcpu)
3801 {
3802         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3803         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3804 }
3805
3806 #endif
3807
3808 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
3809 {
3810         vpid_sync_context(vpid);
3811         if (enable_ept) {
3812                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3813                         return;
3814                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3815         }
3816 }
3817
3818 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3819 {
3820         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
3821 }
3822
3823 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3824 {
3825         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3826
3827         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3828         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3829 }
3830
3831 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3832 {
3833         if (enable_ept && is_paging(vcpu))
3834                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3835         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3836 }
3837
3838 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3839 {
3840         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3841
3842         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3843         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3844 }
3845
3846 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3847 {
3848         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3849
3850         if (!test_bit(VCPU_EXREG_PDPTR,
3851                       (unsigned long *)&vcpu->arch.regs_dirty))
3852                 return;
3853
3854         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3855                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3856                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3857                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3858                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3859         }
3860 }
3861
3862 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3863 {
3864         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3865
3866         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3867                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3868                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3869                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3870                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3871         }
3872
3873         __set_bit(VCPU_EXREG_PDPTR,
3874                   (unsigned long *)&vcpu->arch.regs_avail);
3875         __set_bit(VCPU_EXREG_PDPTR,
3876                   (unsigned long *)&vcpu->arch.regs_dirty);
3877 }
3878
3879 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3880
3881 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3882                                         unsigned long cr0,
3883                                         struct kvm_vcpu *vcpu)
3884 {
3885         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3886                 vmx_decache_cr3(vcpu);
3887         if (!(cr0 & X86_CR0_PG)) {
3888                 /* From paging/starting to nonpaging */
3889                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3890                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3891                              (CPU_BASED_CR3_LOAD_EXITING |
3892                               CPU_BASED_CR3_STORE_EXITING));
3893                 vcpu->arch.cr0 = cr0;
3894                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3895         } else if (!is_paging(vcpu)) {
3896                 /* From nonpaging to paging */
3897                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3898                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3899                              ~(CPU_BASED_CR3_LOAD_EXITING |
3900                                CPU_BASED_CR3_STORE_EXITING));
3901                 vcpu->arch.cr0 = cr0;
3902                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3903         }
3904
3905         if (!(cr0 & X86_CR0_WP))
3906                 *hw_cr0 &= ~X86_CR0_WP;
3907 }
3908
3909 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3910 {
3911         struct vcpu_vmx *vmx = to_vmx(vcpu);
3912         unsigned long hw_cr0;
3913
3914         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3915         if (enable_unrestricted_guest)
3916                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3917         else {
3918                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3919
3920                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3921                         enter_pmode(vcpu);
3922
3923                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3924                         enter_rmode(vcpu);
3925         }
3926
3927 #ifdef CONFIG_X86_64
3928         if (vcpu->arch.efer & EFER_LME) {
3929                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3930                         enter_lmode(vcpu);
3931                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3932                         exit_lmode(vcpu);
3933         }
3934 #endif
3935
3936         if (enable_ept)
3937                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3938
3939         if (!vcpu->fpu_active)
3940                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3941
3942         vmcs_writel(CR0_READ_SHADOW, cr0);
3943         vmcs_writel(GUEST_CR0, hw_cr0);
3944         vcpu->arch.cr0 = cr0;
3945
3946         /* depends on vcpu->arch.cr0 to be set to a new value */
3947         vmx->emulation_required = emulation_required(vcpu);
3948 }
3949
3950 static u64 construct_eptp(unsigned long root_hpa)
3951 {
3952         u64 eptp;
3953
3954         /* TODO write the value reading from MSR */
3955         eptp = VMX_EPT_DEFAULT_MT |
3956                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3957         if (enable_ept_ad_bits)
3958                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3959         eptp |= (root_hpa & PAGE_MASK);
3960
3961         return eptp;
3962 }
3963
3964 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3965 {
3966         unsigned long guest_cr3;
3967         u64 eptp;
3968
3969         guest_cr3 = cr3;
3970         if (enable_ept) {
3971                 eptp = construct_eptp(cr3);
3972                 vmcs_write64(EPT_POINTER, eptp);
3973                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3974                         guest_cr3 = kvm_read_cr3(vcpu);
3975                 else
3976                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3977                 ept_load_pdptrs(vcpu);
3978         }
3979
3980         vmx_flush_tlb(vcpu);
3981         vmcs_writel(GUEST_CR3, guest_cr3);
3982 }
3983
3984 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3985 {
3986         /*
3987          * Pass through host's Machine Check Enable value to hw_cr4, which
3988          * is in force while we are in guest mode.  Do not let guests control
3989          * this bit, even if host CR4.MCE == 0.
3990          */
3991         unsigned long hw_cr4 =
3992                 (cr4_read_shadow() & X86_CR4_MCE) |
3993                 (cr4 & ~X86_CR4_MCE) |
3994                 (to_vmx(vcpu)->rmode.vm86_active ?
3995                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3996
3997         if (cr4 & X86_CR4_VMXE) {
3998                 /*
3999                  * To use VMXON (and later other VMX instructions), a guest
4000                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
4001                  * So basically the check on whether to allow nested VMX
4002                  * is here.
4003                  */
4004                 if (!nested_vmx_allowed(vcpu))
4005                         return 1;
4006         }
4007         if (to_vmx(vcpu)->nested.vmxon &&
4008             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
4009                 return 1;
4010
4011         vcpu->arch.cr4 = cr4;
4012         if (enable_ept) {
4013                 if (!is_paging(vcpu)) {
4014                         hw_cr4 &= ~X86_CR4_PAE;
4015                         hw_cr4 |= X86_CR4_PSE;
4016                 } else if (!(cr4 & X86_CR4_PAE)) {
4017                         hw_cr4 &= ~X86_CR4_PAE;
4018                 }
4019         }
4020
4021         if (!enable_unrestricted_guest && !is_paging(vcpu))
4022                 /*
4023                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4024                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
4025                  * to be manually disabled when guest switches to non-paging
4026                  * mode.
4027                  *
4028                  * If !enable_unrestricted_guest, the CPU is always running
4029                  * with CR0.PG=1 and CR4 needs to be modified.
4030                  * If enable_unrestricted_guest, the CPU automatically
4031                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4032                  */
4033                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4034
4035         vmcs_writel(CR4_READ_SHADOW, cr4);
4036         vmcs_writel(GUEST_CR4, hw_cr4);
4037         return 0;
4038 }
4039
4040 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4041                             struct kvm_segment *var, int seg)
4042 {
4043         struct vcpu_vmx *vmx = to_vmx(vcpu);
4044         u32 ar;
4045
4046         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4047                 *var = vmx->rmode.segs[seg];
4048                 if (seg == VCPU_SREG_TR
4049                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4050                         return;
4051                 var->base = vmx_read_guest_seg_base(vmx, seg);
4052                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4053                 return;
4054         }
4055         var->base = vmx_read_guest_seg_base(vmx, seg);
4056         var->limit = vmx_read_guest_seg_limit(vmx, seg);
4057         var->selector = vmx_read_guest_seg_selector(vmx, seg);
4058         ar = vmx_read_guest_seg_ar(vmx, seg);
4059         var->unusable = (ar >> 16) & 1;
4060         var->type = ar & 15;
4061         var->s = (ar >> 4) & 1;
4062         var->dpl = (ar >> 5) & 3;
4063         /*
4064          * Some userspaces do not preserve unusable property. Since usable
4065          * segment has to be present according to VMX spec we can use present
4066          * property to amend userspace bug by making unusable segment always
4067          * nonpresent. vmx_segment_access_rights() already marks nonpresent
4068          * segment as unusable.
4069          */
4070         var->present = !var->unusable;
4071         var->avl = (ar >> 12) & 1;
4072         var->l = (ar >> 13) & 1;
4073         var->db = (ar >> 14) & 1;
4074         var->g = (ar >> 15) & 1;
4075 }
4076
4077 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4078 {
4079         struct kvm_segment s;
4080
4081         if (to_vmx(vcpu)->rmode.vm86_active) {
4082                 vmx_get_segment(vcpu, &s, seg);
4083                 return s.base;
4084         }
4085         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4086 }
4087
4088 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4089 {
4090         struct vcpu_vmx *vmx = to_vmx(vcpu);
4091
4092         if (unlikely(vmx->rmode.vm86_active))
4093                 return 0;
4094         else {
4095                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4096                 return VMX_AR_DPL(ar);
4097         }
4098 }
4099
4100 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4101 {
4102         u32 ar;
4103
4104         if (var->unusable || !var->present)
4105                 ar = 1 << 16;
4106         else {
4107                 ar = var->type & 15;
4108                 ar |= (var->s & 1) << 4;
4109                 ar |= (var->dpl & 3) << 5;
4110                 ar |= (var->present & 1) << 7;
4111                 ar |= (var->avl & 1) << 12;
4112                 ar |= (var->l & 1) << 13;
4113                 ar |= (var->db & 1) << 14;
4114                 ar |= (var->g & 1) << 15;
4115         }
4116
4117         return ar;
4118 }
4119
4120 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4121                             struct kvm_segment *var, int seg)
4122 {
4123         struct vcpu_vmx *vmx = to_vmx(vcpu);
4124         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4125
4126         vmx_segment_cache_clear(vmx);
4127
4128         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4129                 vmx->rmode.segs[seg] = *var;
4130                 if (seg == VCPU_SREG_TR)
4131                         vmcs_write16(sf->selector, var->selector);
4132                 else if (var->s)
4133                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4134                 goto out;
4135         }
4136
4137         vmcs_writel(sf->base, var->base);
4138         vmcs_write32(sf->limit, var->limit);
4139         vmcs_write16(sf->selector, var->selector);
4140
4141         /*
4142          *   Fix the "Accessed" bit in AR field of segment registers for older
4143          * qemu binaries.
4144          *   IA32 arch specifies that at the time of processor reset the
4145          * "Accessed" bit in the AR field of segment registers is 1. And qemu
4146          * is setting it to 0 in the userland code. This causes invalid guest
4147          * state vmexit when "unrestricted guest" mode is turned on.
4148          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
4149          * tree. Newer qemu binaries with that qemu fix would not need this
4150          * kvm hack.
4151          */
4152         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4153                 var->type |= 0x1; /* Accessed */
4154
4155         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4156
4157 out:
4158         vmx->emulation_required = emulation_required(vcpu);
4159 }
4160
4161 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4162 {
4163         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4164
4165         *db = (ar >> 14) & 1;
4166         *l = (ar >> 13) & 1;
4167 }
4168
4169 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4170 {
4171         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4172         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4173 }
4174
4175 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4176 {
4177         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4178         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4179 }
4180
4181 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4182 {
4183         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4184         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4185 }
4186
4187 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4188 {
4189         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4190         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4191 }
4192
4193 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4194 {
4195         struct kvm_segment var;
4196         u32 ar;
4197
4198         vmx_get_segment(vcpu, &var, seg);
4199         var.dpl = 0x3;
4200         if (seg == VCPU_SREG_CS)
4201                 var.type = 0x3;
4202         ar = vmx_segment_access_rights(&var);
4203
4204         if (var.base != (var.selector << 4))
4205                 return false;
4206         if (var.limit != 0xffff)
4207                 return false;
4208         if (ar != 0xf3)
4209                 return false;
4210
4211         return true;
4212 }
4213
4214 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4215 {
4216         struct kvm_segment cs;
4217         unsigned int cs_rpl;
4218
4219         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4220         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4221
4222         if (cs.unusable)
4223                 return false;
4224         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4225                 return false;
4226         if (!cs.s)
4227                 return false;
4228         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4229                 if (cs.dpl > cs_rpl)
4230                         return false;
4231         } else {
4232                 if (cs.dpl != cs_rpl)
4233                         return false;
4234         }
4235         if (!cs.present)
4236                 return false;
4237
4238         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4239         return true;
4240 }
4241
4242 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4243 {
4244         struct kvm_segment ss;
4245         unsigned int ss_rpl;
4246
4247         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4248         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4249
4250         if (ss.unusable)
4251                 return true;
4252         if (ss.type != 3 && ss.type != 7)
4253                 return false;
4254         if (!ss.s)
4255                 return false;
4256         if (ss.dpl != ss_rpl) /* DPL != RPL */
4257                 return false;
4258         if (!ss.present)
4259                 return false;
4260
4261         return true;
4262 }
4263
4264 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4265 {
4266         struct kvm_segment var;
4267         unsigned int rpl;
4268
4269         vmx_get_segment(vcpu, &var, seg);
4270         rpl = var.selector & SEGMENT_RPL_MASK;
4271
4272         if (var.unusable)
4273                 return true;
4274         if (!var.s)
4275                 return false;
4276         if (!var.present)
4277                 return false;
4278         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4279                 if (var.dpl < rpl) /* DPL < RPL */
4280                         return false;
4281         }
4282
4283         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4284          * rights flags
4285          */
4286         return true;
4287 }
4288
4289 static bool tr_valid(struct kvm_vcpu *vcpu)
4290 {
4291         struct kvm_segment tr;
4292
4293         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4294
4295         if (tr.unusable)
4296                 return false;
4297         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4298                 return false;
4299         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4300                 return false;
4301         if (!tr.present)
4302                 return false;
4303
4304         return true;
4305 }
4306
4307 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4308 {
4309         struct kvm_segment ldtr;
4310
4311         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4312
4313         if (ldtr.unusable)
4314                 return true;
4315         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4316                 return false;
4317         if (ldtr.type != 2)
4318                 return false;
4319         if (!ldtr.present)
4320                 return false;
4321
4322         return true;
4323 }
4324
4325 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4326 {
4327         struct kvm_segment cs, ss;
4328
4329         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4330         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4331
4332         return ((cs.selector & SEGMENT_RPL_MASK) ==
4333                  (ss.selector & SEGMENT_RPL_MASK));
4334 }
4335
4336 /*
4337  * Check if guest state is valid. Returns true if valid, false if
4338  * not.
4339  * We assume that registers are always usable
4340  */
4341 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4342 {
4343         if (enable_unrestricted_guest)
4344                 return true;
4345
4346         /* real mode guest state checks */
4347         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4348                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4349                         return false;
4350                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4351                         return false;
4352                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4353                         return false;
4354                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4355                         return false;
4356                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4357                         return false;
4358                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4359                         return false;
4360         } else {
4361         /* protected mode guest state checks */
4362                 if (!cs_ss_rpl_check(vcpu))
4363                         return false;
4364                 if (!code_segment_valid(vcpu))
4365                         return false;
4366                 if (!stack_segment_valid(vcpu))
4367                         return false;
4368                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4369                         return false;
4370                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4371                         return false;
4372                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4373                         return false;
4374                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4375                         return false;
4376                 if (!tr_valid(vcpu))
4377                         return false;
4378                 if (!ldtr_valid(vcpu))
4379                         return false;
4380         }
4381         /* TODO:
4382          * - Add checks on RIP
4383          * - Add checks on RFLAGS
4384          */
4385
4386         return true;
4387 }
4388
4389 static int init_rmode_tss(struct kvm *kvm)
4390 {
4391         gfn_t fn;
4392         u16 data = 0;
4393         int idx, r;
4394
4395         idx = srcu_read_lock(&kvm->srcu);
4396         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4397         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4398         if (r < 0)
4399                 goto out;
4400         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4401         r = kvm_write_guest_page(kvm, fn++, &data,
4402                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4403         if (r < 0)
4404                 goto out;
4405         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4406         if (r < 0)
4407                 goto out;
4408         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4409         if (r < 0)
4410                 goto out;
4411         data = ~0;
4412         r = kvm_write_guest_page(kvm, fn, &data,
4413                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4414                                  sizeof(u8));
4415 out:
4416         srcu_read_unlock(&kvm->srcu, idx);
4417         return r;
4418 }
4419
4420 static int init_rmode_identity_map(struct kvm *kvm)
4421 {
4422         int i, idx, r = 0;
4423         kvm_pfn_t identity_map_pfn;
4424         u32 tmp;
4425
4426         if (!enable_ept)
4427                 return 0;
4428
4429         /* Protect kvm->arch.ept_identity_pagetable_done. */
4430         mutex_lock(&kvm->slots_lock);
4431
4432         if (likely(kvm->arch.ept_identity_pagetable_done))
4433                 goto out2;
4434
4435         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4436
4437         r = alloc_identity_pagetable(kvm);
4438         if (r < 0)
4439                 goto out2;
4440
4441         idx = srcu_read_lock(&kvm->srcu);
4442         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4443         if (r < 0)
4444                 goto out;
4445         /* Set up identity-mapping pagetable for EPT in real mode */
4446         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4447                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4448                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4449                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4450                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4451                 if (r < 0)
4452                         goto out;
4453         }
4454         kvm->arch.ept_identity_pagetable_done = true;
4455
4456 out:
4457         srcu_read_unlock(&kvm->srcu, idx);
4458
4459 out2:
4460         mutex_unlock(&kvm->slots_lock);
4461         return r;
4462 }
4463
4464 static void seg_setup(int seg)
4465 {
4466         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4467         unsigned int ar;
4468
4469         vmcs_write16(sf->selector, 0);
4470         vmcs_writel(sf->base, 0);
4471         vmcs_write32(sf->limit, 0xffff);
4472         ar = 0x93;
4473         if (seg == VCPU_SREG_CS)
4474                 ar |= 0x08; /* code segment */
4475
4476         vmcs_write32(sf->ar_bytes, ar);
4477 }
4478
4479 static int alloc_apic_access_page(struct kvm *kvm)
4480 {
4481         struct page *page;
4482         int r = 0;
4483
4484         mutex_lock(&kvm->slots_lock);
4485         if (kvm->arch.apic_access_page_done)
4486                 goto out;
4487         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4488                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4489         if (r)
4490                 goto out;
4491
4492         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4493         if (is_error_page(page)) {
4494                 r = -EFAULT;
4495                 goto out;
4496         }
4497
4498         /*
4499          * Do not pin the page in memory, so that memory hot-unplug
4500          * is able to migrate it.
4501          */
4502         put_page(page);
4503         kvm->arch.apic_access_page_done = true;
4504 out:
4505         mutex_unlock(&kvm->slots_lock);
4506         return r;
4507 }
4508
4509 static int alloc_identity_pagetable(struct kvm *kvm)
4510 {
4511         /* Called with kvm->slots_lock held. */
4512
4513         int r = 0;
4514
4515         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4516
4517         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4518                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4519
4520         return r;
4521 }
4522
4523 static int allocate_vpid(void)
4524 {
4525         int vpid;
4526
4527         if (!enable_vpid)
4528                 return 0;
4529         spin_lock(&vmx_vpid_lock);
4530         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4531         if (vpid < VMX_NR_VPIDS)
4532                 __set_bit(vpid, vmx_vpid_bitmap);
4533         else
4534                 vpid = 0;
4535         spin_unlock(&vmx_vpid_lock);
4536         return vpid;
4537 }
4538
4539 static void free_vpid(int vpid)
4540 {
4541         if (!enable_vpid || vpid == 0)
4542                 return;
4543         spin_lock(&vmx_vpid_lock);
4544         __clear_bit(vpid, vmx_vpid_bitmap);
4545         spin_unlock(&vmx_vpid_lock);
4546 }
4547
4548 #define MSR_TYPE_R      1
4549 #define MSR_TYPE_W      2
4550 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4551                                                 u32 msr, int type)
4552 {
4553         int f = sizeof(unsigned long);
4554
4555         if (!cpu_has_vmx_msr_bitmap())
4556                 return;
4557
4558         /*
4559          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4560          * have the write-low and read-high bitmap offsets the wrong way round.
4561          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4562          */
4563         if (msr <= 0x1fff) {
4564                 if (type & MSR_TYPE_R)
4565                         /* read-low */
4566                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4567
4568                 if (type & MSR_TYPE_W)
4569                         /* write-low */
4570                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4571
4572         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4573                 msr &= 0x1fff;
4574                 if (type & MSR_TYPE_R)
4575                         /* read-high */
4576                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4577
4578                 if (type & MSR_TYPE_W)
4579                         /* write-high */
4580                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4581
4582         }
4583 }
4584
4585 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4586                                                 u32 msr, int type)
4587 {
4588         int f = sizeof(unsigned long);
4589
4590         if (!cpu_has_vmx_msr_bitmap())
4591                 return;
4592
4593         /*
4594          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4595          * have the write-low and read-high bitmap offsets the wrong way round.
4596          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4597          */
4598         if (msr <= 0x1fff) {
4599                 if (type & MSR_TYPE_R)
4600                         /* read-low */
4601                         __set_bit(msr, msr_bitmap + 0x000 / f);
4602
4603                 if (type & MSR_TYPE_W)
4604                         /* write-low */
4605                         __set_bit(msr, msr_bitmap + 0x800 / f);
4606
4607         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4608                 msr &= 0x1fff;
4609                 if (type & MSR_TYPE_R)
4610                         /* read-high */
4611                         __set_bit(msr, msr_bitmap + 0x400 / f);
4612
4613                 if (type & MSR_TYPE_W)
4614                         /* write-high */
4615                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4616
4617         }
4618 }
4619
4620 /*
4621  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4622  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4623  */
4624 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4625                                                unsigned long *msr_bitmap_nested,
4626                                                u32 msr, int type)
4627 {
4628         int f = sizeof(unsigned long);
4629
4630         if (!cpu_has_vmx_msr_bitmap()) {
4631                 WARN_ON(1);
4632                 return;
4633         }
4634
4635         /*
4636          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4637          * have the write-low and read-high bitmap offsets the wrong way round.
4638          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4639          */
4640         if (msr <= 0x1fff) {
4641                 if (type & MSR_TYPE_R &&
4642                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4643                         /* read-low */
4644                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4645
4646                 if (type & MSR_TYPE_W &&
4647                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4648                         /* write-low */
4649                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4650
4651         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4652                 msr &= 0x1fff;
4653                 if (type & MSR_TYPE_R &&
4654                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4655                         /* read-high */
4656                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4657
4658                 if (type & MSR_TYPE_W &&
4659                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4660                         /* write-high */
4661                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4662
4663         }
4664 }
4665
4666 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4667 {
4668         if (!longmode_only)
4669                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4670                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4671         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4672                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4673 }
4674
4675 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4676 {
4677         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4678                         msr, MSR_TYPE_R);
4679         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4680                         msr, MSR_TYPE_R);
4681 }
4682
4683 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4684 {
4685         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4686                         msr, MSR_TYPE_R);
4687         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4688                         msr, MSR_TYPE_R);
4689 }
4690
4691 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4692 {
4693         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4694                         msr, MSR_TYPE_W);
4695         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4696                         msr, MSR_TYPE_W);
4697 }
4698
4699 static bool vmx_get_enable_apicv(void)
4700 {
4701         return enable_apicv;
4702 }
4703
4704 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4705 {
4706         struct vcpu_vmx *vmx = to_vmx(vcpu);
4707         int max_irr;
4708         void *vapic_page;
4709         u16 status;
4710
4711         if (vmx->nested.pi_desc &&
4712             vmx->nested.pi_pending) {
4713                 vmx->nested.pi_pending = false;
4714                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4715                         return 0;
4716
4717                 max_irr = find_last_bit(
4718                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4719
4720                 if (max_irr == 256)
4721                         return 0;
4722
4723                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4724                 if (!vapic_page) {
4725                         WARN_ON(1);
4726                         return -ENOMEM;
4727                 }
4728                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4729                 kunmap(vmx->nested.virtual_apic_page);
4730
4731                 status = vmcs_read16(GUEST_INTR_STATUS);
4732                 if ((u8)max_irr > ((u8)status & 0xff)) {
4733                         status &= ~0xff;
4734                         status |= (u8)max_irr;
4735                         vmcs_write16(GUEST_INTR_STATUS, status);
4736                 }
4737         }
4738         return 0;
4739 }
4740
4741 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4742 {
4743 #ifdef CONFIG_SMP
4744         if (vcpu->mode == IN_GUEST_MODE) {
4745                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4746
4747                 /*
4748                  * Currently, we don't support urgent interrupt,
4749                  * all interrupts are recognized as non-urgent
4750                  * interrupt, so we cannot post interrupts when
4751                  * 'SN' is set.
4752                  *
4753                  * If the vcpu is in guest mode, it means it is
4754                  * running instead of being scheduled out and
4755                  * waiting in the run queue, and that's the only
4756                  * case when 'SN' is set currently, warning if
4757                  * 'SN' is set.
4758                  */
4759                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4760
4761                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4762                                 POSTED_INTR_VECTOR);
4763                 return true;
4764         }
4765 #endif
4766         return false;
4767 }
4768
4769 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4770                                                 int vector)
4771 {
4772         struct vcpu_vmx *vmx = to_vmx(vcpu);
4773
4774         if (is_guest_mode(vcpu) &&
4775             vector == vmx->nested.posted_intr_nv) {
4776                 /* the PIR and ON have been set by L1. */
4777                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4778                 /*
4779                  * If a posted intr is not recognized by hardware,
4780                  * we will accomplish it in the next vmentry.
4781                  */
4782                 vmx->nested.pi_pending = true;
4783                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4784                 return 0;
4785         }
4786         return -1;
4787 }
4788 /*
4789  * Send interrupt to vcpu via posted interrupt way.
4790  * 1. If target vcpu is running(non-root mode), send posted interrupt
4791  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4792  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4793  * interrupt from PIR in next vmentry.
4794  */
4795 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4796 {
4797         struct vcpu_vmx *vmx = to_vmx(vcpu);
4798         int r;
4799
4800         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4801         if (!r)
4802                 return;
4803
4804         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4805                 return;
4806
4807         r = pi_test_and_set_on(&vmx->pi_desc);
4808         kvm_make_request(KVM_REQ_EVENT, vcpu);
4809         if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4810                 kvm_vcpu_kick(vcpu);
4811 }
4812
4813 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4814 {
4815         struct vcpu_vmx *vmx = to_vmx(vcpu);
4816
4817         if (!pi_test_and_clear_on(&vmx->pi_desc))
4818                 return;
4819
4820         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4821 }
4822
4823 /*
4824  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4825  * will not change in the lifetime of the guest.
4826  * Note that host-state that does change is set elsewhere. E.g., host-state
4827  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4828  */
4829 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4830 {
4831         u32 low32, high32;
4832         unsigned long tmpl;
4833         struct desc_ptr dt;
4834         unsigned long cr4;
4835
4836         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4837         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4838
4839         /* Save the most likely value for this task's CR4 in the VMCS. */
4840         cr4 = cr4_read_shadow();
4841         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4842         vmx->host_state.vmcs_host_cr4 = cr4;
4843
4844         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4845 #ifdef CONFIG_X86_64
4846         /*
4847          * Load null selectors, so we can avoid reloading them in
4848          * __vmx_load_host_state(), in case userspace uses the null selectors
4849          * too (the expected case).
4850          */
4851         vmcs_write16(HOST_DS_SELECTOR, 0);
4852         vmcs_write16(HOST_ES_SELECTOR, 0);
4853 #else
4854         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4855         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4856 #endif
4857         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4858         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4859
4860         native_store_idt(&dt);
4861         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4862         vmx->host_idt_base = dt.address;
4863
4864         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4865
4866         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4867         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4868         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4869         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4870
4871         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4872                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4873                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4874         }
4875 }
4876
4877 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4878 {
4879         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4880         if (enable_ept)
4881                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4882         if (is_guest_mode(&vmx->vcpu))
4883                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4884                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4885         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4886 }
4887
4888 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4889 {
4890         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4891
4892         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4893                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4894         /* Enable the preemption timer dynamically */
4895         pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4896         return pin_based_exec_ctrl;
4897 }
4898
4899 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4900 {
4901         struct vcpu_vmx *vmx = to_vmx(vcpu);
4902
4903         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4904         if (cpu_has_secondary_exec_ctrls()) {
4905                 if (kvm_vcpu_apicv_active(vcpu))
4906                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
4907                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
4908                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4909                 else
4910                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
4911                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
4912                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4913         }
4914
4915         if (cpu_has_vmx_msr_bitmap())
4916                 vmx_set_msr_bitmap(vcpu);
4917 }
4918
4919 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4920 {
4921         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4922
4923         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4924                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4925
4926         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4927                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4928 #ifdef CONFIG_X86_64
4929                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4930                                 CPU_BASED_CR8_LOAD_EXITING;
4931 #endif
4932         }
4933         if (!enable_ept)
4934                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4935                                 CPU_BASED_CR3_LOAD_EXITING  |
4936                                 CPU_BASED_INVLPG_EXITING;
4937         return exec_control;
4938 }
4939
4940 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4941 {
4942         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4943         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
4944                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4945         if (vmx->vpid == 0)
4946                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4947         if (!enable_ept) {
4948                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4949                 enable_unrestricted_guest = 0;
4950                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4951                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4952         }
4953         if (!enable_unrestricted_guest)
4954                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4955         if (!ple_gap)
4956                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4957         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4958                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4959                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4960         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4961         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4962            (handle_vmptrld).
4963            We can NOT enable shadow_vmcs here because we don't have yet
4964            a current VMCS12
4965         */
4966         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4967
4968         if (!enable_pml)
4969                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4970
4971         return exec_control;
4972 }
4973
4974 static void ept_set_mmio_spte_mask(void)
4975 {
4976         /*
4977          * EPT Misconfigurations can be generated if the value of bits 2:0
4978          * of an EPT paging-structure entry is 110b (write/execute).
4979          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4980          * spte.
4981          */
4982         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4983 }
4984
4985 #define VMX_XSS_EXIT_BITMAP 0
4986 /*
4987  * Sets up the vmcs for emulated real mode.
4988  */
4989 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4990 {
4991 #ifdef CONFIG_X86_64
4992         unsigned long a;
4993 #endif
4994         int i;
4995
4996         /* I/O */
4997         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4998         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4999
5000         if (enable_shadow_vmcs) {
5001                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5002                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5003         }
5004         if (cpu_has_vmx_msr_bitmap())
5005                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
5006
5007         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5008
5009         /* Control */
5010         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5011         vmx->hv_deadline_tsc = -1;
5012
5013         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
5014
5015         if (cpu_has_secondary_exec_ctrls()) {
5016                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5017                                 vmx_secondary_exec_control(vmx));
5018         }
5019
5020         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
5021                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5022                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5023                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5024                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5025
5026                 vmcs_write16(GUEST_INTR_STATUS, 0);
5027
5028                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
5029                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
5030         }
5031
5032         if (ple_gap) {
5033                 vmcs_write32(PLE_GAP, ple_gap);
5034                 vmx->ple_window = ple_window;
5035                 vmx->ple_window_dirty = true;
5036         }
5037
5038         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5039         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5040         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
5041
5042         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
5043         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
5044         vmx_set_constant_host_state(vmx);
5045 #ifdef CONFIG_X86_64
5046         rdmsrl(MSR_FS_BASE, a);
5047         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5048         rdmsrl(MSR_GS_BASE, a);
5049         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5050 #else
5051         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5052         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5053 #endif
5054
5055         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5056         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5057         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
5058         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5059         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
5060
5061         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5062                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5063
5064         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5065                 u32 index = vmx_msr_index[i];
5066                 u32 data_low, data_high;
5067                 int j = vmx->nmsrs;
5068
5069                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5070                         continue;
5071                 if (wrmsr_safe(index, data_low, data_high) < 0)
5072                         continue;
5073                 vmx->guest_msrs[j].index = i;
5074                 vmx->guest_msrs[j].data = 0;
5075                 vmx->guest_msrs[j].mask = -1ull;
5076                 ++vmx->nmsrs;
5077         }
5078
5079
5080         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5081
5082         /* 22.2.1, 20.8.1 */
5083         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5084
5085         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
5086         set_cr4_guest_host_mask(vmx);
5087
5088         if (vmx_xsaves_supported())
5089                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5090
5091         if (enable_pml) {
5092                 ASSERT(vmx->pml_pg);
5093                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5094                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5095         }
5096
5097         return 0;
5098 }
5099
5100 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5101 {
5102         struct vcpu_vmx *vmx = to_vmx(vcpu);
5103         struct msr_data apic_base_msr;
5104         u64 cr0;
5105
5106         vmx->rmode.vm86_active = 0;
5107
5108         vmx->soft_vnmi_blocked = 0;
5109
5110         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5111         kvm_set_cr8(vcpu, 0);
5112
5113         if (!init_event) {
5114                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5115                                      MSR_IA32_APICBASE_ENABLE;
5116                 if (kvm_vcpu_is_reset_bsp(vcpu))
5117                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5118                 apic_base_msr.host_initiated = true;
5119                 kvm_set_apic_base(vcpu, &apic_base_msr);
5120         }
5121
5122         vmx_segment_cache_clear(vmx);
5123
5124         seg_setup(VCPU_SREG_CS);
5125         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5126         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5127
5128         seg_setup(VCPU_SREG_DS);
5129         seg_setup(VCPU_SREG_ES);
5130         seg_setup(VCPU_SREG_FS);
5131         seg_setup(VCPU_SREG_GS);
5132         seg_setup(VCPU_SREG_SS);
5133
5134         vmcs_write16(GUEST_TR_SELECTOR, 0);
5135         vmcs_writel(GUEST_TR_BASE, 0);
5136         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5137         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5138
5139         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5140         vmcs_writel(GUEST_LDTR_BASE, 0);
5141         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5142         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5143
5144         if (!init_event) {
5145                 vmcs_write32(GUEST_SYSENTER_CS, 0);
5146                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5147                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5148                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5149         }
5150
5151         vmcs_writel(GUEST_RFLAGS, 0x02);
5152         kvm_rip_write(vcpu, 0xfff0);
5153
5154         vmcs_writel(GUEST_GDTR_BASE, 0);
5155         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5156
5157         vmcs_writel(GUEST_IDTR_BASE, 0);
5158         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5159
5160         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5161         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5162         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5163
5164         setup_msrs(vmx);
5165
5166         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
5167
5168         if (cpu_has_vmx_tpr_shadow() && !init_event) {
5169                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5170                 if (cpu_need_tpr_shadow(vcpu))
5171                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5172                                      __pa(vcpu->arch.apic->regs));
5173                 vmcs_write32(TPR_THRESHOLD, 0);
5174         }
5175
5176         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5177
5178         if (kvm_vcpu_apicv_active(vcpu))
5179                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5180
5181         if (vmx->vpid != 0)
5182                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5183
5184         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5185         vmx->vcpu.arch.cr0 = cr0;
5186         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5187         vmx_set_cr4(vcpu, 0);
5188         vmx_set_efer(vcpu, 0);
5189         vmx_fpu_activate(vcpu);
5190         update_exception_bitmap(vcpu);
5191
5192         vpid_sync_context(vmx->vpid);
5193 }
5194
5195 /*
5196  * In nested virtualization, check if L1 asked to exit on external interrupts.
5197  * For most existing hypervisors, this will always return true.
5198  */
5199 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5200 {
5201         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5202                 PIN_BASED_EXT_INTR_MASK;
5203 }
5204
5205 /*
5206  * In nested virtualization, check if L1 has set
5207  * VM_EXIT_ACK_INTR_ON_EXIT
5208  */
5209 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5210 {
5211         return get_vmcs12(vcpu)->vm_exit_controls &
5212                 VM_EXIT_ACK_INTR_ON_EXIT;
5213 }
5214
5215 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5216 {
5217         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5218                 PIN_BASED_NMI_EXITING;
5219 }
5220
5221 static void enable_irq_window(struct kvm_vcpu *vcpu)
5222 {
5223         u32 cpu_based_vm_exec_control;
5224
5225         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5226         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
5227         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5228 }
5229
5230 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5231 {
5232         u32 cpu_based_vm_exec_control;
5233
5234         if (!cpu_has_virtual_nmis() ||
5235             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5236                 enable_irq_window(vcpu);
5237                 return;
5238         }
5239
5240         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5241         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
5242         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5243 }
5244
5245 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5246 {
5247         struct vcpu_vmx *vmx = to_vmx(vcpu);
5248         uint32_t intr;
5249         int irq = vcpu->arch.interrupt.nr;
5250
5251         trace_kvm_inj_virq(irq);
5252
5253         ++vcpu->stat.irq_injections;
5254         if (vmx->rmode.vm86_active) {
5255                 int inc_eip = 0;
5256                 if (vcpu->arch.interrupt.soft)
5257                         inc_eip = vcpu->arch.event_exit_inst_len;
5258                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5259                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5260                 return;
5261         }
5262         intr = irq | INTR_INFO_VALID_MASK;
5263         if (vcpu->arch.interrupt.soft) {
5264                 intr |= INTR_TYPE_SOFT_INTR;
5265                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5266                              vmx->vcpu.arch.event_exit_inst_len);
5267         } else
5268                 intr |= INTR_TYPE_EXT_INTR;
5269         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5270 }
5271
5272 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5273 {
5274         struct vcpu_vmx *vmx = to_vmx(vcpu);
5275
5276         if (is_guest_mode(vcpu))
5277                 return;
5278
5279         if (!cpu_has_virtual_nmis()) {
5280                 /*
5281                  * Tracking the NMI-blocked state in software is built upon
5282                  * finding the next open IRQ window. This, in turn, depends on
5283                  * well-behaving guests: They have to keep IRQs disabled at
5284                  * least as long as the NMI handler runs. Otherwise we may
5285                  * cause NMI nesting, maybe breaking the guest. But as this is
5286                  * highly unlikely, we can live with the residual risk.
5287                  */
5288                 vmx->soft_vnmi_blocked = 1;
5289                 vmx->vnmi_blocked_time = 0;
5290         }
5291
5292         ++vcpu->stat.nmi_injections;
5293         vmx->nmi_known_unmasked = false;
5294         if (vmx->rmode.vm86_active) {
5295                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5296                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5297                 return;
5298         }
5299         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5300                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5301 }
5302
5303 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5304 {
5305         if (!cpu_has_virtual_nmis())
5306                 return to_vmx(vcpu)->soft_vnmi_blocked;
5307         if (to_vmx(vcpu)->nmi_known_unmasked)
5308                 return false;
5309         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5310 }
5311
5312 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5313 {
5314         struct vcpu_vmx *vmx = to_vmx(vcpu);
5315
5316         if (!cpu_has_virtual_nmis()) {
5317                 if (vmx->soft_vnmi_blocked != masked) {
5318                         vmx->soft_vnmi_blocked = masked;
5319                         vmx->vnmi_blocked_time = 0;
5320                 }
5321         } else {
5322                 vmx->nmi_known_unmasked = !masked;
5323                 if (masked)
5324                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5325                                       GUEST_INTR_STATE_NMI);
5326                 else
5327                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5328                                         GUEST_INTR_STATE_NMI);
5329         }
5330 }
5331
5332 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5333 {
5334         if (to_vmx(vcpu)->nested.nested_run_pending)
5335                 return 0;
5336
5337         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5338                 return 0;
5339
5340         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5341                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5342                    | GUEST_INTR_STATE_NMI));
5343 }
5344
5345 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5346 {
5347         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5348                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5349                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5350                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5351 }
5352
5353 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5354 {
5355         int ret;
5356
5357         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5358                                     PAGE_SIZE * 3);
5359         if (ret)
5360                 return ret;
5361         kvm->arch.tss_addr = addr;
5362         return init_rmode_tss(kvm);
5363 }
5364
5365 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5366 {
5367         switch (vec) {
5368         case BP_VECTOR:
5369                 /*
5370                  * Update instruction length as we may reinject the exception
5371                  * from user space while in guest debugging mode.
5372                  */
5373                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5374                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5375                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5376                         return false;
5377                 /* fall through */
5378         case DB_VECTOR:
5379                 if (vcpu->guest_debug &
5380                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5381                         return false;
5382                 /* fall through */
5383         case DE_VECTOR:
5384         case OF_VECTOR:
5385         case BR_VECTOR:
5386         case UD_VECTOR:
5387         case DF_VECTOR:
5388         case SS_VECTOR:
5389         case GP_VECTOR:
5390         case MF_VECTOR:
5391                 return true;
5392         break;
5393         }
5394         return false;
5395 }
5396
5397 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5398                                   int vec, u32 err_code)
5399 {
5400         /*
5401          * Instruction with address size override prefix opcode 0x67
5402          * Cause the #SS fault with 0 error code in VM86 mode.
5403          */
5404         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5405                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5406                         if (vcpu->arch.halt_request) {
5407                                 vcpu->arch.halt_request = 0;
5408                                 return kvm_vcpu_halt(vcpu);
5409                         }
5410                         return 1;
5411                 }
5412                 return 0;
5413         }
5414
5415         /*
5416          * Forward all other exceptions that are valid in real mode.
5417          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5418          *        the required debugging infrastructure rework.
5419          */
5420         kvm_queue_exception(vcpu, vec);
5421         return 1;
5422 }
5423
5424 /*
5425  * Trigger machine check on the host. We assume all the MSRs are already set up
5426  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5427  * We pass a fake environment to the machine check handler because we want
5428  * the guest to be always treated like user space, no matter what context
5429  * it used internally.
5430  */
5431 static void kvm_machine_check(void)
5432 {
5433 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5434         struct pt_regs regs = {
5435                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5436                 .flags = X86_EFLAGS_IF,
5437         };
5438
5439         do_machine_check(&regs, 0);
5440 #endif
5441 }
5442
5443 static int handle_machine_check(struct kvm_vcpu *vcpu)
5444 {
5445         /* already handled by vcpu_run */
5446         return 1;
5447 }
5448
5449 static int handle_exception(struct kvm_vcpu *vcpu)
5450 {
5451         struct vcpu_vmx *vmx = to_vmx(vcpu);
5452         struct kvm_run *kvm_run = vcpu->run;
5453         u32 intr_info, ex_no, error_code;
5454         unsigned long cr2, rip, dr6;
5455         u32 vect_info;
5456         enum emulation_result er;
5457
5458         vect_info = vmx->idt_vectoring_info;
5459         intr_info = vmx->exit_intr_info;
5460
5461         if (is_machine_check(intr_info))
5462                 return handle_machine_check(vcpu);
5463
5464         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5465                 return 1;  /* already handled by vmx_vcpu_run() */
5466
5467         if (is_no_device(intr_info)) {
5468                 vmx_fpu_activate(vcpu);
5469                 return 1;
5470         }
5471
5472         if (is_invalid_opcode(intr_info)) {
5473                 if (is_guest_mode(vcpu)) {
5474                         kvm_queue_exception(vcpu, UD_VECTOR);
5475                         return 1;
5476                 }
5477                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5478                 if (er != EMULATE_DONE)
5479                         kvm_queue_exception(vcpu, UD_VECTOR);
5480                 return 1;
5481         }
5482
5483         error_code = 0;
5484         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5485                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5486
5487         /*
5488          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5489          * MMIO, it is better to report an internal error.
5490          * See the comments in vmx_handle_exit.
5491          */
5492         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5493             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5494                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5495                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5496                 vcpu->run->internal.ndata = 3;
5497                 vcpu->run->internal.data[0] = vect_info;
5498                 vcpu->run->internal.data[1] = intr_info;
5499                 vcpu->run->internal.data[2] = error_code;
5500                 return 0;
5501         }
5502
5503         if (is_page_fault(intr_info)) {
5504                 /* EPT won't cause page fault directly */
5505                 BUG_ON(enable_ept);
5506                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5507                 trace_kvm_page_fault(cr2, error_code);
5508
5509                 if (kvm_event_needs_reinjection(vcpu))
5510                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5511                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5512         }
5513
5514         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5515
5516         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5517                 return handle_rmode_exception(vcpu, ex_no, error_code);
5518
5519         switch (ex_no) {
5520         case AC_VECTOR:
5521                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5522                 return 1;
5523         case DB_VECTOR:
5524                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5525                 if (!(vcpu->guest_debug &
5526                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5527                         vcpu->arch.dr6 &= ~15;
5528                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5529                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5530                                 skip_emulated_instruction(vcpu);
5531
5532                         kvm_queue_exception(vcpu, DB_VECTOR);
5533                         return 1;
5534                 }
5535                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5536                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5537                 /* fall through */
5538         case BP_VECTOR:
5539                 /*
5540                  * Update instruction length as we may reinject #BP from
5541                  * user space while in guest debugging mode. Reading it for
5542                  * #DB as well causes no harm, it is not used in that case.
5543                  */
5544                 vmx->vcpu.arch.event_exit_inst_len =
5545                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5546                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5547                 rip = kvm_rip_read(vcpu);
5548                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5549                 kvm_run->debug.arch.exception = ex_no;
5550                 break;
5551         default:
5552                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5553                 kvm_run->ex.exception = ex_no;
5554                 kvm_run->ex.error_code = error_code;
5555                 break;
5556         }
5557         return 0;
5558 }
5559
5560 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5561 {
5562         ++vcpu->stat.irq_exits;
5563         return 1;
5564 }
5565
5566 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5567 {
5568         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5569         return 0;
5570 }
5571
5572 static int handle_io(struct kvm_vcpu *vcpu)
5573 {
5574         unsigned long exit_qualification;
5575         int size, in, string;
5576         unsigned port;
5577
5578         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5579         string = (exit_qualification & 16) != 0;
5580         in = (exit_qualification & 8) != 0;
5581
5582         ++vcpu->stat.io_exits;
5583
5584         if (string || in)
5585                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5586
5587         port = exit_qualification >> 16;
5588         size = (exit_qualification & 7) + 1;
5589         skip_emulated_instruction(vcpu);
5590
5591         return kvm_fast_pio_out(vcpu, size, port);
5592 }
5593
5594 static void
5595 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5596 {
5597         /*
5598          * Patch in the VMCALL instruction:
5599          */
5600         hypercall[0] = 0x0f;
5601         hypercall[1] = 0x01;
5602         hypercall[2] = 0xc1;
5603 }
5604
5605 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5606 {
5607         unsigned long always_on = VMXON_CR0_ALWAYSON;
5608         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5609
5610         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5611                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5612             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5613                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5614         return (val & always_on) == always_on;
5615 }
5616
5617 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5618 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5619 {
5620         if (is_guest_mode(vcpu)) {
5621                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5622                 unsigned long orig_val = val;
5623
5624                 /*
5625                  * We get here when L2 changed cr0 in a way that did not change
5626                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5627                  * but did change L0 shadowed bits. So we first calculate the
5628                  * effective cr0 value that L1 would like to write into the
5629                  * hardware. It consists of the L2-owned bits from the new
5630                  * value combined with the L1-owned bits from L1's guest_cr0.
5631                  */
5632                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5633                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5634
5635                 if (!nested_cr0_valid(vcpu, val))
5636                         return 1;
5637
5638                 if (kvm_set_cr0(vcpu, val))
5639                         return 1;
5640                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5641                 return 0;
5642         } else {
5643                 if (to_vmx(vcpu)->nested.vmxon &&
5644                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5645                         return 1;
5646                 return kvm_set_cr0(vcpu, val);
5647         }
5648 }
5649
5650 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5651 {
5652         if (is_guest_mode(vcpu)) {
5653                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5654                 unsigned long orig_val = val;
5655
5656                 /* analogously to handle_set_cr0 */
5657                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5658                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5659                 if (kvm_set_cr4(vcpu, val))
5660                         return 1;
5661                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5662                 return 0;
5663         } else
5664                 return kvm_set_cr4(vcpu, val);
5665 }
5666
5667 /* called to set cr0 as appropriate for clts instruction exit. */
5668 static void handle_clts(struct kvm_vcpu *vcpu)
5669 {
5670         if (is_guest_mode(vcpu)) {
5671                 /*
5672                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5673                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5674                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5675                  */
5676                 vmcs_writel(CR0_READ_SHADOW,
5677                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5678                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5679         } else
5680                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5681 }
5682
5683 static int handle_cr(struct kvm_vcpu *vcpu)
5684 {
5685         unsigned long exit_qualification, val;
5686         int cr;
5687         int reg;
5688         int err;
5689
5690         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5691         cr = exit_qualification & 15;
5692         reg = (exit_qualification >> 8) & 15;
5693         switch ((exit_qualification >> 4) & 3) {
5694         case 0: /* mov to cr */
5695                 val = kvm_register_readl(vcpu, reg);
5696                 trace_kvm_cr_write(cr, val);
5697                 switch (cr) {
5698                 case 0:
5699                         err = handle_set_cr0(vcpu, val);
5700                         kvm_complete_insn_gp(vcpu, err);
5701                         return 1;
5702                 case 3:
5703                         err = kvm_set_cr3(vcpu, val);
5704                         kvm_complete_insn_gp(vcpu, err);
5705                         return 1;
5706                 case 4:
5707                         err = handle_set_cr4(vcpu, val);
5708                         kvm_complete_insn_gp(vcpu, err);
5709                         return 1;
5710                 case 8: {
5711                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5712                                 u8 cr8 = (u8)val;
5713                                 err = kvm_set_cr8(vcpu, cr8);
5714                                 kvm_complete_insn_gp(vcpu, err);
5715                                 if (lapic_in_kernel(vcpu))
5716                                         return 1;
5717                                 if (cr8_prev <= cr8)
5718                                         return 1;
5719                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5720                                 return 0;
5721                         }
5722                 }
5723                 break;
5724         case 2: /* clts */
5725                 handle_clts(vcpu);
5726                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5727                 skip_emulated_instruction(vcpu);
5728                 vmx_fpu_activate(vcpu);
5729                 return 1;
5730         case 1: /*mov from cr*/
5731                 switch (cr) {
5732                 case 3:
5733                         val = kvm_read_cr3(vcpu);
5734                         kvm_register_write(vcpu, reg, val);
5735                         trace_kvm_cr_read(cr, val);
5736                         skip_emulated_instruction(vcpu);
5737                         return 1;
5738                 case 8:
5739                         val = kvm_get_cr8(vcpu);
5740                         kvm_register_write(vcpu, reg, val);
5741                         trace_kvm_cr_read(cr, val);
5742                         skip_emulated_instruction(vcpu);
5743                         return 1;
5744                 }
5745                 break;
5746         case 3: /* lmsw */
5747                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5748                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5749                 kvm_lmsw(vcpu, val);
5750
5751                 skip_emulated_instruction(vcpu);
5752                 return 1;
5753         default:
5754                 break;
5755         }
5756         vcpu->run->exit_reason = 0;
5757         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5758                (int)(exit_qualification >> 4) & 3, cr);
5759         return 0;
5760 }
5761
5762 static int handle_dr(struct kvm_vcpu *vcpu)
5763 {
5764         unsigned long exit_qualification;
5765         int dr, dr7, reg;
5766
5767         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5768         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5769
5770         /* First, if DR does not exist, trigger UD */
5771         if (!kvm_require_dr(vcpu, dr))
5772                 return 1;
5773
5774         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5775         if (!kvm_require_cpl(vcpu, 0))
5776                 return 1;
5777         dr7 = vmcs_readl(GUEST_DR7);
5778         if (dr7 & DR7_GD) {
5779                 /*
5780                  * As the vm-exit takes precedence over the debug trap, we
5781                  * need to emulate the latter, either for the host or the
5782                  * guest debugging itself.
5783                  */
5784                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5785                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5786                         vcpu->run->debug.arch.dr7 = dr7;
5787                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5788                         vcpu->run->debug.arch.exception = DB_VECTOR;
5789                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5790                         return 0;
5791                 } else {
5792                         vcpu->arch.dr6 &= ~15;
5793                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5794                         kvm_queue_exception(vcpu, DB_VECTOR);
5795                         return 1;
5796                 }
5797         }
5798
5799         if (vcpu->guest_debug == 0) {
5800                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5801                                 CPU_BASED_MOV_DR_EXITING);
5802
5803                 /*
5804                  * No more DR vmexits; force a reload of the debug registers
5805                  * and reenter on this instruction.  The next vmexit will
5806                  * retrieve the full state of the debug registers.
5807                  */
5808                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5809                 return 1;
5810         }
5811
5812         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5813         if (exit_qualification & TYPE_MOV_FROM_DR) {
5814                 unsigned long val;
5815
5816                 if (kvm_get_dr(vcpu, dr, &val))
5817                         return 1;
5818                 kvm_register_write(vcpu, reg, val);
5819         } else
5820                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5821                         return 1;
5822
5823         skip_emulated_instruction(vcpu);
5824         return 1;
5825 }
5826
5827 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5828 {
5829         return vcpu->arch.dr6;
5830 }
5831
5832 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5833 {
5834 }
5835
5836 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5837 {
5838         get_debugreg(vcpu->arch.db[0], 0);
5839         get_debugreg(vcpu->arch.db[1], 1);
5840         get_debugreg(vcpu->arch.db[2], 2);
5841         get_debugreg(vcpu->arch.db[3], 3);
5842         get_debugreg(vcpu->arch.dr6, 6);
5843         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5844
5845         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5846         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
5847 }
5848
5849 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5850 {
5851         vmcs_writel(GUEST_DR7, val);
5852 }
5853
5854 static int handle_cpuid(struct kvm_vcpu *vcpu)
5855 {
5856         kvm_emulate_cpuid(vcpu);
5857         return 1;
5858 }
5859
5860 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5861 {
5862         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5863         struct msr_data msr_info;
5864
5865         msr_info.index = ecx;
5866         msr_info.host_initiated = false;
5867         if (vmx_get_msr(vcpu, &msr_info)) {
5868                 trace_kvm_msr_read_ex(ecx);
5869                 kvm_inject_gp(vcpu, 0);
5870                 return 1;
5871         }
5872
5873         trace_kvm_msr_read(ecx, msr_info.data);
5874
5875         /* FIXME: handling of bits 32:63 of rax, rdx */
5876         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5877         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
5878         skip_emulated_instruction(vcpu);
5879         return 1;
5880 }
5881
5882 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5883 {
5884         struct msr_data msr;
5885         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5886         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5887                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5888
5889         msr.data = data;
5890         msr.index = ecx;
5891         msr.host_initiated = false;
5892         if (kvm_set_msr(vcpu, &msr) != 0) {
5893                 trace_kvm_msr_write_ex(ecx, data);
5894                 kvm_inject_gp(vcpu, 0);
5895                 return 1;
5896         }
5897
5898         trace_kvm_msr_write(ecx, data);
5899         skip_emulated_instruction(vcpu);
5900         return 1;
5901 }
5902
5903 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5904 {
5905         kvm_make_request(KVM_REQ_EVENT, vcpu);
5906         return 1;
5907 }
5908
5909 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5910 {
5911         u32 cpu_based_vm_exec_control;
5912
5913         /* clear pending irq */
5914         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5915         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5916         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5917
5918         kvm_make_request(KVM_REQ_EVENT, vcpu);
5919
5920         ++vcpu->stat.irq_window_exits;
5921         return 1;
5922 }
5923
5924 static int handle_halt(struct kvm_vcpu *vcpu)
5925 {
5926         return kvm_emulate_halt(vcpu);
5927 }
5928
5929 static int handle_vmcall(struct kvm_vcpu *vcpu)
5930 {
5931         return kvm_emulate_hypercall(vcpu);
5932 }
5933
5934 static int handle_invd(struct kvm_vcpu *vcpu)
5935 {
5936         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5937 }
5938
5939 static int handle_invlpg(struct kvm_vcpu *vcpu)
5940 {
5941         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5942
5943         kvm_mmu_invlpg(vcpu, exit_qualification);
5944         skip_emulated_instruction(vcpu);
5945         return 1;
5946 }
5947
5948 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5949 {
5950         int err;
5951
5952         err = kvm_rdpmc(vcpu);
5953         kvm_complete_insn_gp(vcpu, err);
5954
5955         return 1;
5956 }
5957
5958 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5959 {
5960         kvm_emulate_wbinvd(vcpu);
5961         return 1;
5962 }
5963
5964 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5965 {
5966         u64 new_bv = kvm_read_edx_eax(vcpu);
5967         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5968
5969         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5970                 skip_emulated_instruction(vcpu);
5971         return 1;
5972 }
5973
5974 static int handle_xsaves(struct kvm_vcpu *vcpu)
5975 {
5976         skip_emulated_instruction(vcpu);
5977         WARN(1, "this should never happen\n");
5978         return 1;
5979 }
5980
5981 static int handle_xrstors(struct kvm_vcpu *vcpu)
5982 {
5983         skip_emulated_instruction(vcpu);
5984         WARN(1, "this should never happen\n");
5985         return 1;
5986 }
5987
5988 static int handle_apic_access(struct kvm_vcpu *vcpu)
5989 {
5990         if (likely(fasteoi)) {
5991                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5992                 int access_type, offset;
5993
5994                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5995                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5996                 /*
5997                  * Sane guest uses MOV to write EOI, with written value
5998                  * not cared. So make a short-circuit here by avoiding
5999                  * heavy instruction emulation.
6000                  */
6001                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6002                     (offset == APIC_EOI)) {
6003                         kvm_lapic_set_eoi(vcpu);
6004                         skip_emulated_instruction(vcpu);
6005                         return 1;
6006                 }
6007         }
6008         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6009 }
6010
6011 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6012 {
6013         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6014         int vector = exit_qualification & 0xff;
6015
6016         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6017         kvm_apic_set_eoi_accelerated(vcpu, vector);
6018         return 1;
6019 }
6020
6021 static int handle_apic_write(struct kvm_vcpu *vcpu)
6022 {
6023         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6024         u32 offset = exit_qualification & 0xfff;
6025
6026         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6027         kvm_apic_write_nodecode(vcpu, offset);
6028         return 1;
6029 }
6030
6031 static int handle_task_switch(struct kvm_vcpu *vcpu)
6032 {
6033         struct vcpu_vmx *vmx = to_vmx(vcpu);
6034         unsigned long exit_qualification;
6035         bool has_error_code = false;
6036         u32 error_code = 0;
6037         u16 tss_selector;
6038         int reason, type, idt_v, idt_index;
6039
6040         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6041         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6042         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6043
6044         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6045
6046         reason = (u32)exit_qualification >> 30;
6047         if (reason == TASK_SWITCH_GATE && idt_v) {
6048                 switch (type) {
6049                 case INTR_TYPE_NMI_INTR:
6050                         vcpu->arch.nmi_injected = false;
6051                         vmx_set_nmi_mask(vcpu, true);
6052                         break;
6053                 case INTR_TYPE_EXT_INTR:
6054                 case INTR_TYPE_SOFT_INTR:
6055                         kvm_clear_interrupt_queue(vcpu);
6056                         break;
6057                 case INTR_TYPE_HARD_EXCEPTION:
6058                         if (vmx->idt_vectoring_info &
6059                             VECTORING_INFO_DELIVER_CODE_MASK) {
6060                                 has_error_code = true;
6061                                 error_code =
6062                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
6063                         }
6064                         /* fall through */
6065                 case INTR_TYPE_SOFT_EXCEPTION:
6066                         kvm_clear_exception_queue(vcpu);
6067                         break;
6068                 default:
6069                         break;
6070                 }
6071         }
6072         tss_selector = exit_qualification;
6073
6074         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6075                        type != INTR_TYPE_EXT_INTR &&
6076                        type != INTR_TYPE_NMI_INTR))
6077                 skip_emulated_instruction(vcpu);
6078
6079         if (kvm_task_switch(vcpu, tss_selector,
6080                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6081                             has_error_code, error_code) == EMULATE_FAIL) {
6082                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6083                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6084                 vcpu->run->internal.ndata = 0;
6085                 return 0;
6086         }
6087
6088         /*
6089          * TODO: What about debug traps on tss switch?
6090          *       Are we supposed to inject them and update dr6?
6091          */
6092
6093         return 1;
6094 }
6095
6096 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6097 {
6098         unsigned long exit_qualification;
6099         gpa_t gpa;
6100         u32 error_code;
6101         int gla_validity;
6102
6103         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6104
6105         gla_validity = (exit_qualification >> 7) & 0x3;
6106         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
6107                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
6108                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
6109                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
6110                         vmcs_readl(GUEST_LINEAR_ADDRESS));
6111                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
6112                         (long unsigned int)exit_qualification);
6113                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6114                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
6115                 return 0;
6116         }
6117
6118         /*
6119          * EPT violation happened while executing iret from NMI,
6120          * "blocked by NMI" bit has to be set before next VM entry.
6121          * There are errata that may cause this bit to not be set:
6122          * AAK134, BY25.
6123          */
6124         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6125                         cpu_has_virtual_nmis() &&
6126                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6127                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6128
6129         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6130         trace_kvm_page_fault(gpa, exit_qualification);
6131
6132         /* it is a read fault? */
6133         error_code = (exit_qualification << 2) & PFERR_USER_MASK;
6134         /* it is a write fault? */
6135         error_code |= exit_qualification & PFERR_WRITE_MASK;
6136         /* It is a fetch fault? */
6137         error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
6138         /* ept page table is present? */
6139         error_code |= (exit_qualification & 0x38) != 0;
6140
6141         vcpu->arch.exit_qualification = exit_qualification;
6142
6143         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6144 }
6145
6146 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6147 {
6148         int ret;
6149         gpa_t gpa;
6150
6151         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6152         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6153                 skip_emulated_instruction(vcpu);
6154                 trace_kvm_fast_mmio(gpa);
6155                 return 1;
6156         }
6157
6158         ret = handle_mmio_page_fault(vcpu, gpa, true);
6159         if (likely(ret == RET_MMIO_PF_EMULATE))
6160                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6161                                               EMULATE_DONE;
6162
6163         if (unlikely(ret == RET_MMIO_PF_INVALID))
6164                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6165
6166         if (unlikely(ret == RET_MMIO_PF_RETRY))
6167                 return 1;
6168
6169         /* It is the real ept misconfig */
6170         WARN_ON(1);
6171
6172         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6173         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6174
6175         return 0;
6176 }
6177
6178 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6179 {
6180         u32 cpu_based_vm_exec_control;
6181
6182         /* clear pending NMI */
6183         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6184         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6185         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6186         ++vcpu->stat.nmi_window_exits;
6187         kvm_make_request(KVM_REQ_EVENT, vcpu);
6188
6189         return 1;
6190 }
6191
6192 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6193 {
6194         struct vcpu_vmx *vmx = to_vmx(vcpu);
6195         enum emulation_result err = EMULATE_DONE;
6196         int ret = 1;
6197         u32 cpu_exec_ctrl;
6198         bool intr_window_requested;
6199         unsigned count = 130;
6200
6201         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6202         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6203
6204         while (vmx->emulation_required && count-- != 0) {
6205                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6206                         return handle_interrupt_window(&vmx->vcpu);
6207
6208                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
6209                         return 1;
6210
6211                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6212
6213                 if (err == EMULATE_USER_EXIT) {
6214                         ++vcpu->stat.mmio_exits;
6215                         ret = 0;
6216                         goto out;
6217                 }
6218
6219                 if (err != EMULATE_DONE) {
6220                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6221                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6222                         vcpu->run->internal.ndata = 0;
6223                         return 0;
6224                 }
6225
6226                 if (vcpu->arch.halt_request) {
6227                         vcpu->arch.halt_request = 0;
6228                         ret = kvm_vcpu_halt(vcpu);
6229                         goto out;
6230                 }
6231
6232                 if (signal_pending(current))
6233                         goto out;
6234                 if (need_resched())
6235                         schedule();
6236         }
6237
6238 out:
6239         return ret;
6240 }
6241
6242 static int __grow_ple_window(int val)
6243 {
6244         if (ple_window_grow < 1)
6245                 return ple_window;
6246
6247         val = min(val, ple_window_actual_max);
6248
6249         if (ple_window_grow < ple_window)
6250                 val *= ple_window_grow;
6251         else
6252                 val += ple_window_grow;
6253
6254         return val;
6255 }
6256
6257 static int __shrink_ple_window(int val, int modifier, int minimum)
6258 {
6259         if (modifier < 1)
6260                 return ple_window;
6261
6262         if (modifier < ple_window)
6263                 val /= modifier;
6264         else
6265                 val -= modifier;
6266
6267         return max(val, minimum);
6268 }
6269
6270 static void grow_ple_window(struct kvm_vcpu *vcpu)
6271 {
6272         struct vcpu_vmx *vmx = to_vmx(vcpu);
6273         int old = vmx->ple_window;
6274
6275         vmx->ple_window = __grow_ple_window(old);
6276
6277         if (vmx->ple_window != old)
6278                 vmx->ple_window_dirty = true;
6279
6280         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6281 }
6282
6283 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6284 {
6285         struct vcpu_vmx *vmx = to_vmx(vcpu);
6286         int old = vmx->ple_window;
6287
6288         vmx->ple_window = __shrink_ple_window(old,
6289                                               ple_window_shrink, ple_window);
6290
6291         if (vmx->ple_window != old)
6292                 vmx->ple_window_dirty = true;
6293
6294         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6295 }
6296
6297 /*
6298  * ple_window_actual_max is computed to be one grow_ple_window() below
6299  * ple_window_max. (See __grow_ple_window for the reason.)
6300  * This prevents overflows, because ple_window_max is int.
6301  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6302  * this process.
6303  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6304  */
6305 static void update_ple_window_actual_max(void)
6306 {
6307         ple_window_actual_max =
6308                         __shrink_ple_window(max(ple_window_max, ple_window),
6309                                             ple_window_grow, INT_MIN);
6310 }
6311
6312 /*
6313  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6314  */
6315 static void wakeup_handler(void)
6316 {
6317         struct kvm_vcpu *vcpu;
6318         int cpu = smp_processor_id();
6319
6320         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6321         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6322                         blocked_vcpu_list) {
6323                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6324
6325                 if (pi_test_on(pi_desc) == 1)
6326                         kvm_vcpu_kick(vcpu);
6327         }
6328         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6329 }
6330
6331 static __init int hardware_setup(void)
6332 {
6333         int r = -ENOMEM, i, msr;
6334
6335         rdmsrl_safe(MSR_EFER, &host_efer);
6336
6337         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6338                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6339
6340         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6341         if (!vmx_io_bitmap_a)
6342                 return r;
6343
6344         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6345         if (!vmx_io_bitmap_b)
6346                 goto out;
6347
6348         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6349         if (!vmx_msr_bitmap_legacy)
6350                 goto out1;
6351
6352         vmx_msr_bitmap_legacy_x2apic =
6353                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6354         if (!vmx_msr_bitmap_legacy_x2apic)
6355                 goto out2;
6356
6357         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6358         if (!vmx_msr_bitmap_longmode)
6359                 goto out3;
6360
6361         vmx_msr_bitmap_longmode_x2apic =
6362                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6363         if (!vmx_msr_bitmap_longmode_x2apic)
6364                 goto out4;
6365
6366         if (nested) {
6367                 vmx_msr_bitmap_nested =
6368                         (unsigned long *)__get_free_page(GFP_KERNEL);
6369                 if (!vmx_msr_bitmap_nested)
6370                         goto out5;
6371         }
6372
6373         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6374         if (!vmx_vmread_bitmap)
6375                 goto out6;
6376
6377         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6378         if (!vmx_vmwrite_bitmap)
6379                 goto out7;
6380
6381         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6382         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6383
6384         /*
6385          * Allow direct access to the PC debug port (it is often used for I/O
6386          * delays, but the vmexits simply slow things down).
6387          */
6388         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6389         clear_bit(0x80, vmx_io_bitmap_a);
6390
6391         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6392
6393         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6394         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6395         if (nested)
6396                 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6397
6398         if (setup_vmcs_config(&vmcs_config) < 0) {
6399                 r = -EIO;
6400                 goto out8;
6401         }
6402
6403         if (boot_cpu_has(X86_FEATURE_NX))
6404                 kvm_enable_efer_bits(EFER_NX);
6405
6406         if (!cpu_has_vmx_vpid())
6407                 enable_vpid = 0;
6408         if (!cpu_has_vmx_shadow_vmcs())
6409                 enable_shadow_vmcs = 0;
6410         if (enable_shadow_vmcs)
6411                 init_vmcs_shadow_fields();
6412
6413         if (!cpu_has_vmx_ept() ||
6414             !cpu_has_vmx_ept_4levels()) {
6415                 enable_ept = 0;
6416                 enable_unrestricted_guest = 0;
6417                 enable_ept_ad_bits = 0;
6418         }
6419
6420         if (!cpu_has_vmx_ept_ad_bits())
6421                 enable_ept_ad_bits = 0;
6422
6423         if (!cpu_has_vmx_unrestricted_guest())
6424                 enable_unrestricted_guest = 0;
6425
6426         if (!cpu_has_vmx_flexpriority())
6427                 flexpriority_enabled = 0;
6428
6429         /*
6430          * set_apic_access_page_addr() is used to reload apic access
6431          * page upon invalidation.  No need to do anything if not
6432          * using the APIC_ACCESS_ADDR VMCS field.
6433          */
6434         if (!flexpriority_enabled)
6435                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6436
6437         if (!cpu_has_vmx_tpr_shadow())
6438                 kvm_x86_ops->update_cr8_intercept = NULL;
6439
6440         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6441                 kvm_disable_largepages();
6442
6443         if (!cpu_has_vmx_ple())
6444                 ple_gap = 0;
6445
6446         if (!cpu_has_vmx_apicv())
6447                 enable_apicv = 0;
6448
6449         if (cpu_has_vmx_tsc_scaling()) {
6450                 kvm_has_tsc_control = true;
6451                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6452                 kvm_tsc_scaling_ratio_frac_bits = 48;
6453         }
6454
6455         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6456         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6457         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6458         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6459         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6460         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6461         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6462
6463         memcpy(vmx_msr_bitmap_legacy_x2apic,
6464                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6465         memcpy(vmx_msr_bitmap_longmode_x2apic,
6466                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6467
6468         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6469
6470         for (msr = 0x800; msr <= 0x8ff; msr++)
6471                 vmx_disable_intercept_msr_read_x2apic(msr);
6472
6473         /* TMCCT */
6474         vmx_enable_intercept_msr_read_x2apic(0x839);
6475         /* TPR */
6476         vmx_disable_intercept_msr_write_x2apic(0x808);
6477         /* EOI */
6478         vmx_disable_intercept_msr_write_x2apic(0x80b);
6479         /* SELF-IPI */
6480         vmx_disable_intercept_msr_write_x2apic(0x83f);
6481
6482         if (enable_ept) {
6483                 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6484                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6485                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6486                         0ull, VMX_EPT_EXECUTABLE_MASK,
6487                         cpu_has_vmx_ept_execute_only() ?
6488                                       0ull : VMX_EPT_READABLE_MASK);
6489                 ept_set_mmio_spte_mask();
6490                 kvm_enable_tdp();
6491         } else
6492                 kvm_disable_tdp();
6493
6494         update_ple_window_actual_max();
6495
6496         /*
6497          * Only enable PML when hardware supports PML feature, and both EPT
6498          * and EPT A/D bit features are enabled -- PML depends on them to work.
6499          */
6500         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6501                 enable_pml = 0;
6502
6503         if (!enable_pml) {
6504                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6505                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6506                 kvm_x86_ops->flush_log_dirty = NULL;
6507                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6508         }
6509
6510         if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6511                 u64 vmx_msr;
6512
6513                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6514                 cpu_preemption_timer_multi =
6515                          vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6516         } else {
6517                 kvm_x86_ops->set_hv_timer = NULL;
6518                 kvm_x86_ops->cancel_hv_timer = NULL;
6519         }
6520
6521         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6522
6523         kvm_mce_cap_supported |= MCG_LMCE_P;
6524
6525         return alloc_kvm_area();
6526
6527 out8:
6528         free_page((unsigned long)vmx_vmwrite_bitmap);
6529 out7:
6530         free_page((unsigned long)vmx_vmread_bitmap);
6531 out6:
6532         if (nested)
6533                 free_page((unsigned long)vmx_msr_bitmap_nested);
6534 out5:
6535         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6536 out4:
6537         free_page((unsigned long)vmx_msr_bitmap_longmode);
6538 out3:
6539         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6540 out2:
6541         free_page((unsigned long)vmx_msr_bitmap_legacy);
6542 out1:
6543         free_page((unsigned long)vmx_io_bitmap_b);
6544 out:
6545         free_page((unsigned long)vmx_io_bitmap_a);
6546
6547     return r;
6548 }
6549
6550 static __exit void hardware_unsetup(void)
6551 {
6552         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6553         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6554         free_page((unsigned long)vmx_msr_bitmap_legacy);
6555         free_page((unsigned long)vmx_msr_bitmap_longmode);
6556         free_page((unsigned long)vmx_io_bitmap_b);
6557         free_page((unsigned long)vmx_io_bitmap_a);
6558         free_page((unsigned long)vmx_vmwrite_bitmap);
6559         free_page((unsigned long)vmx_vmread_bitmap);
6560         if (nested)
6561                 free_page((unsigned long)vmx_msr_bitmap_nested);
6562
6563         free_kvm_area();
6564 }
6565
6566 /*
6567  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6568  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6569  */
6570 static int handle_pause(struct kvm_vcpu *vcpu)
6571 {
6572         if (ple_gap)
6573                 grow_ple_window(vcpu);
6574
6575         skip_emulated_instruction(vcpu);
6576         kvm_vcpu_on_spin(vcpu);
6577
6578         return 1;
6579 }
6580
6581 static int handle_nop(struct kvm_vcpu *vcpu)
6582 {
6583         skip_emulated_instruction(vcpu);
6584         return 1;
6585 }
6586
6587 static int handle_mwait(struct kvm_vcpu *vcpu)
6588 {
6589         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6590         return handle_nop(vcpu);
6591 }
6592
6593 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6594 {
6595         return 1;
6596 }
6597
6598 static int handle_monitor(struct kvm_vcpu *vcpu)
6599 {
6600         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6601         return handle_nop(vcpu);
6602 }
6603
6604 /*
6605  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6606  * We could reuse a single VMCS for all the L2 guests, but we also want the
6607  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6608  * allows keeping them loaded on the processor, and in the future will allow
6609  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6610  * every entry if they never change.
6611  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6612  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6613  *
6614  * The following functions allocate and free a vmcs02 in this pool.
6615  */
6616
6617 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6618 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6619 {
6620         struct vmcs02_list *item;
6621         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6622                 if (item->vmptr == vmx->nested.current_vmptr) {
6623                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6624                         return &item->vmcs02;
6625                 }
6626
6627         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6628                 /* Recycle the least recently used VMCS. */
6629                 item = list_last_entry(&vmx->nested.vmcs02_pool,
6630                                        struct vmcs02_list, list);
6631                 item->vmptr = vmx->nested.current_vmptr;
6632                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6633                 return &item->vmcs02;
6634         }
6635
6636         /* Create a new VMCS */
6637         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6638         if (!item)
6639                 return NULL;
6640         item->vmcs02.vmcs = alloc_vmcs();
6641         if (!item->vmcs02.vmcs) {
6642                 kfree(item);
6643                 return NULL;
6644         }
6645         loaded_vmcs_init(&item->vmcs02);
6646         item->vmptr = vmx->nested.current_vmptr;
6647         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6648         vmx->nested.vmcs02_num++;
6649         return &item->vmcs02;
6650 }
6651
6652 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6653 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6654 {
6655         struct vmcs02_list *item;
6656         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6657                 if (item->vmptr == vmptr) {
6658                         free_loaded_vmcs(&item->vmcs02);
6659                         list_del(&item->list);
6660                         kfree(item);
6661                         vmx->nested.vmcs02_num--;
6662                         return;
6663                 }
6664 }
6665
6666 /*
6667  * Free all VMCSs saved for this vcpu, except the one pointed by
6668  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6669  * must be &vmx->vmcs01.
6670  */
6671 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6672 {
6673         struct vmcs02_list *item, *n;
6674
6675         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6676         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6677                 /*
6678                  * Something will leak if the above WARN triggers.  Better than
6679                  * a use-after-free.
6680                  */
6681                 if (vmx->loaded_vmcs == &item->vmcs02)
6682                         continue;
6683
6684                 free_loaded_vmcs(&item->vmcs02);
6685                 list_del(&item->list);
6686                 kfree(item);
6687                 vmx->nested.vmcs02_num--;
6688         }
6689 }
6690
6691 /*
6692  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6693  * set the success or error code of an emulated VMX instruction, as specified
6694  * by Vol 2B, VMX Instruction Reference, "Conventions".
6695  */
6696 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6697 {
6698         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6699                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6700                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6701 }
6702
6703 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6704 {
6705         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6706                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6707                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6708                         | X86_EFLAGS_CF);
6709 }
6710
6711 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6712                                         u32 vm_instruction_error)
6713 {
6714         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6715                 /*
6716                  * failValid writes the error number to the current VMCS, which
6717                  * can't be done there isn't a current VMCS.
6718                  */
6719                 nested_vmx_failInvalid(vcpu);
6720                 return;
6721         }
6722         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6723                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6724                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6725                         | X86_EFLAGS_ZF);
6726         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6727         /*
6728          * We don't need to force a shadow sync because
6729          * VM_INSTRUCTION_ERROR is not shadowed
6730          */
6731 }
6732
6733 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6734 {
6735         /* TODO: not to reset guest simply here. */
6736         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6737         pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6738 }
6739
6740 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6741 {
6742         struct vcpu_vmx *vmx =
6743                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6744
6745         vmx->nested.preemption_timer_expired = true;
6746         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6747         kvm_vcpu_kick(&vmx->vcpu);
6748
6749         return HRTIMER_NORESTART;
6750 }
6751
6752 /*
6753  * Decode the memory-address operand of a vmx instruction, as recorded on an
6754  * exit caused by such an instruction (run by a guest hypervisor).
6755  * On success, returns 0. When the operand is invalid, returns 1 and throws
6756  * #UD or #GP.
6757  */
6758 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6759                                  unsigned long exit_qualification,
6760                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6761 {
6762         gva_t off;
6763         bool exn;
6764         struct kvm_segment s;
6765
6766         /*
6767          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6768          * Execution", on an exit, vmx_instruction_info holds most of the
6769          * addressing components of the operand. Only the displacement part
6770          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6771          * For how an actual address is calculated from all these components,
6772          * refer to Vol. 1, "Operand Addressing".
6773          */
6774         int  scaling = vmx_instruction_info & 3;
6775         int  addr_size = (vmx_instruction_info >> 7) & 7;
6776         bool is_reg = vmx_instruction_info & (1u << 10);
6777         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6778         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6779         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6780         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6781         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6782
6783         if (is_reg) {
6784                 kvm_queue_exception(vcpu, UD_VECTOR);
6785                 return 1;
6786         }
6787
6788         /* Addr = segment_base + offset */
6789         /* offset = base + [index * scale] + displacement */
6790         off = exit_qualification; /* holds the displacement */
6791         if (base_is_valid)
6792                 off += kvm_register_read(vcpu, base_reg);
6793         if (index_is_valid)
6794                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6795         vmx_get_segment(vcpu, &s, seg_reg);
6796         *ret = s.base + off;
6797
6798         if (addr_size == 1) /* 32 bit */
6799                 *ret &= 0xffffffff;
6800
6801         /* Checks for #GP/#SS exceptions. */
6802         exn = false;
6803         if (is_long_mode(vcpu)) {
6804                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6805                  * non-canonical form. This is the only check on the memory
6806                  * destination for long mode!
6807                  */
6808                 exn = is_noncanonical_address(*ret);
6809         } else if (is_protmode(vcpu)) {
6810                 /* Protected mode: apply checks for segment validity in the
6811                  * following order:
6812                  * - segment type check (#GP(0) may be thrown)
6813                  * - usability check (#GP(0)/#SS(0))
6814                  * - limit check (#GP(0)/#SS(0))
6815                  */
6816                 if (wr)
6817                         /* #GP(0) if the destination operand is located in a
6818                          * read-only data segment or any code segment.
6819                          */
6820                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6821                 else
6822                         /* #GP(0) if the source operand is located in an
6823                          * execute-only code segment
6824                          */
6825                         exn = ((s.type & 0xa) == 8);
6826                 if (exn) {
6827                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6828                         return 1;
6829                 }
6830                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6831                  */
6832                 exn = (s.unusable != 0);
6833                 /* Protected mode: #GP(0)/#SS(0) if the memory
6834                  * operand is outside the segment limit.
6835                  */
6836                 exn = exn || (off + sizeof(u64) > s.limit);
6837         }
6838         if (exn) {
6839                 kvm_queue_exception_e(vcpu,
6840                                       seg_reg == VCPU_SREG_SS ?
6841                                                 SS_VECTOR : GP_VECTOR,
6842                                       0);
6843                 return 1;
6844         }
6845
6846         return 0;
6847 }
6848
6849 /*
6850  * This function performs the various checks including
6851  * - if it's 4KB aligned
6852  * - No bits beyond the physical address width are set
6853  * - Returns 0 on success or else 1
6854  * (Intel SDM Section 30.3)
6855  */
6856 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6857                                   gpa_t *vmpointer)
6858 {
6859         gva_t gva;
6860         gpa_t vmptr;
6861         struct x86_exception e;
6862         struct page *page;
6863         struct vcpu_vmx *vmx = to_vmx(vcpu);
6864         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6865
6866         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6867                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6868                 return 1;
6869
6870         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6871                                 sizeof(vmptr), &e)) {
6872                 kvm_inject_page_fault(vcpu, &e);
6873                 return 1;
6874         }
6875
6876         switch (exit_reason) {
6877         case EXIT_REASON_VMON:
6878                 /*
6879                  * SDM 3: 24.11.5
6880                  * The first 4 bytes of VMXON region contain the supported
6881                  * VMCS revision identifier
6882                  *
6883                  * Note - IA32_VMX_BASIC[48] will never be 1
6884                  * for the nested case;
6885                  * which replaces physical address width with 32
6886                  *
6887                  */
6888                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6889                         nested_vmx_failInvalid(vcpu);
6890                         skip_emulated_instruction(vcpu);
6891                         return 1;
6892                 }
6893
6894                 page = nested_get_page(vcpu, vmptr);
6895                 if (page == NULL ||
6896                     *(u32 *)kmap(page) != VMCS12_REVISION) {
6897                         nested_vmx_failInvalid(vcpu);
6898                         kunmap(page);
6899                         skip_emulated_instruction(vcpu);
6900                         return 1;
6901                 }
6902                 kunmap(page);
6903                 vmx->nested.vmxon_ptr = vmptr;
6904                 break;
6905         case EXIT_REASON_VMCLEAR:
6906                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6907                         nested_vmx_failValid(vcpu,
6908                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6909                         skip_emulated_instruction(vcpu);
6910                         return 1;
6911                 }
6912
6913                 if (vmptr == vmx->nested.vmxon_ptr) {
6914                         nested_vmx_failValid(vcpu,
6915                                              VMXERR_VMCLEAR_VMXON_POINTER);
6916                         skip_emulated_instruction(vcpu);
6917                         return 1;
6918                 }
6919                 break;
6920         case EXIT_REASON_VMPTRLD:
6921                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6922                         nested_vmx_failValid(vcpu,
6923                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6924                         skip_emulated_instruction(vcpu);
6925                         return 1;
6926                 }
6927
6928                 if (vmptr == vmx->nested.vmxon_ptr) {
6929                         nested_vmx_failValid(vcpu,
6930                                              VMXERR_VMCLEAR_VMXON_POINTER);
6931                         skip_emulated_instruction(vcpu);
6932                         return 1;
6933                 }
6934                 break;
6935         default:
6936                 return 1; /* shouldn't happen */
6937         }
6938
6939         if (vmpointer)
6940                 *vmpointer = vmptr;
6941         return 0;
6942 }
6943
6944 /*
6945  * Emulate the VMXON instruction.
6946  * Currently, we just remember that VMX is active, and do not save or even
6947  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6948  * do not currently need to store anything in that guest-allocated memory
6949  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6950  * argument is different from the VMXON pointer (which the spec says they do).
6951  */
6952 static int handle_vmon(struct kvm_vcpu *vcpu)
6953 {
6954         struct kvm_segment cs;
6955         struct vcpu_vmx *vmx = to_vmx(vcpu);
6956         struct vmcs *shadow_vmcs;
6957         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6958                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6959
6960         /* The Intel VMX Instruction Reference lists a bunch of bits that
6961          * are prerequisite to running VMXON, most notably cr4.VMXE must be
6962          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6963          * Otherwise, we should fail with #UD. We test these now:
6964          */
6965         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6966             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6967             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6968                 kvm_queue_exception(vcpu, UD_VECTOR);
6969                 return 1;
6970         }
6971
6972         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6973         if (is_long_mode(vcpu) && !cs.l) {
6974                 kvm_queue_exception(vcpu, UD_VECTOR);
6975                 return 1;
6976         }
6977
6978         if (vmx_get_cpl(vcpu)) {
6979                 kvm_inject_gp(vcpu, 0);
6980                 return 1;
6981         }
6982
6983         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6984                 return 1;
6985
6986         if (vmx->nested.vmxon) {
6987                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6988                 skip_emulated_instruction(vcpu);
6989                 return 1;
6990         }
6991
6992         if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6993                         != VMXON_NEEDED_FEATURES) {
6994                 kvm_inject_gp(vcpu, 0);
6995                 return 1;
6996         }
6997
6998         vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
6999         if (!vmx->nested.cached_vmcs12)
7000                 return -ENOMEM;
7001
7002         if (enable_shadow_vmcs) {
7003                 shadow_vmcs = alloc_vmcs();
7004                 if (!shadow_vmcs) {
7005                         kfree(vmx->nested.cached_vmcs12);
7006                         return -ENOMEM;
7007                 }
7008                 /* mark vmcs as shadow */
7009                 shadow_vmcs->revision_id |= (1u << 31);
7010                 /* init shadow vmcs */
7011                 vmcs_clear(shadow_vmcs);
7012                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
7013         }
7014
7015         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
7016         vmx->nested.vmcs02_num = 0;
7017
7018         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7019                      HRTIMER_MODE_REL);
7020         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7021
7022         vmx->nested.vmxon = true;
7023
7024         skip_emulated_instruction(vcpu);
7025         nested_vmx_succeed(vcpu);
7026         return 1;
7027 }
7028
7029 /*
7030  * Intel's VMX Instruction Reference specifies a common set of prerequisites
7031  * for running VMX instructions (except VMXON, whose prerequisites are
7032  * slightly different). It also specifies what exception to inject otherwise.
7033  */
7034 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7035 {
7036         struct kvm_segment cs;
7037         struct vcpu_vmx *vmx = to_vmx(vcpu);
7038
7039         if (!vmx->nested.vmxon) {
7040                 kvm_queue_exception(vcpu, UD_VECTOR);
7041                 return 0;
7042         }
7043
7044         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
7045         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
7046             (is_long_mode(vcpu) && !cs.l)) {
7047                 kvm_queue_exception(vcpu, UD_VECTOR);
7048                 return 0;
7049         }
7050
7051         if (vmx_get_cpl(vcpu)) {
7052                 kvm_inject_gp(vcpu, 0);
7053                 return 0;
7054         }
7055
7056         return 1;
7057 }
7058
7059 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7060 {
7061         if (vmx->nested.current_vmptr == -1ull)
7062                 return;
7063
7064         /* current_vmptr and current_vmcs12 are always set/reset together */
7065         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
7066                 return;
7067
7068         if (enable_shadow_vmcs) {
7069                 /* copy to memory all shadowed fields in case
7070                    they were modified */
7071                 copy_shadow_to_vmcs12(vmx);
7072                 vmx->nested.sync_shadow_vmcs = false;
7073                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
7074                                 SECONDARY_EXEC_SHADOW_VMCS);
7075                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7076         }
7077         vmx->nested.posted_intr_nv = -1;
7078
7079         /* Flush VMCS12 to guest memory */
7080         memcpy(vmx->nested.current_vmcs12, vmx->nested.cached_vmcs12,
7081                VMCS12_SIZE);
7082
7083         kunmap(vmx->nested.current_vmcs12_page);
7084         nested_release_page(vmx->nested.current_vmcs12_page);
7085         vmx->nested.current_vmptr = -1ull;
7086         vmx->nested.current_vmcs12 = NULL;
7087 }
7088
7089 /*
7090  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7091  * just stops using VMX.
7092  */
7093 static void free_nested(struct vcpu_vmx *vmx)
7094 {
7095         if (!vmx->nested.vmxon)
7096                 return;
7097
7098         vmx->nested.vmxon = false;
7099         free_vpid(vmx->nested.vpid02);
7100         nested_release_vmcs12(vmx);
7101         if (enable_shadow_vmcs)
7102                 free_vmcs(vmx->nested.current_shadow_vmcs);
7103         kfree(vmx->nested.cached_vmcs12);
7104         /* Unpin physical memory we referred to in current vmcs02 */
7105         if (vmx->nested.apic_access_page) {
7106                 nested_release_page(vmx->nested.apic_access_page);
7107                 vmx->nested.apic_access_page = NULL;
7108         }
7109         if (vmx->nested.virtual_apic_page) {
7110                 nested_release_page(vmx->nested.virtual_apic_page);
7111                 vmx->nested.virtual_apic_page = NULL;
7112         }
7113         if (vmx->nested.pi_desc_page) {
7114                 kunmap(vmx->nested.pi_desc_page);
7115                 nested_release_page(vmx->nested.pi_desc_page);
7116                 vmx->nested.pi_desc_page = NULL;
7117                 vmx->nested.pi_desc = NULL;
7118         }
7119
7120         nested_free_all_saved_vmcss(vmx);
7121 }
7122
7123 /* Emulate the VMXOFF instruction */
7124 static int handle_vmoff(struct kvm_vcpu *vcpu)
7125 {
7126         if (!nested_vmx_check_permission(vcpu))
7127                 return 1;
7128         free_nested(to_vmx(vcpu));
7129         skip_emulated_instruction(vcpu);
7130         nested_vmx_succeed(vcpu);
7131         return 1;
7132 }
7133
7134 /* Emulate the VMCLEAR instruction */
7135 static int handle_vmclear(struct kvm_vcpu *vcpu)
7136 {
7137         struct vcpu_vmx *vmx = to_vmx(vcpu);
7138         gpa_t vmptr;
7139         struct vmcs12 *vmcs12;
7140         struct page *page;
7141
7142         if (!nested_vmx_check_permission(vcpu))
7143                 return 1;
7144
7145         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
7146                 return 1;
7147
7148         if (vmptr == vmx->nested.current_vmptr)
7149                 nested_release_vmcs12(vmx);
7150
7151         page = nested_get_page(vcpu, vmptr);
7152         if (page == NULL) {
7153                 /*
7154                  * For accurate processor emulation, VMCLEAR beyond available
7155                  * physical memory should do nothing at all. However, it is
7156                  * possible that a nested vmx bug, not a guest hypervisor bug,
7157                  * resulted in this case, so let's shut down before doing any
7158                  * more damage:
7159                  */
7160                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7161                 return 1;
7162         }
7163         vmcs12 = kmap(page);
7164         vmcs12->launch_state = 0;
7165         kunmap(page);
7166         nested_release_page(page);
7167
7168         nested_free_vmcs02(vmx, vmptr);
7169
7170         skip_emulated_instruction(vcpu);
7171         nested_vmx_succeed(vcpu);
7172         return 1;
7173 }
7174
7175 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7176
7177 /* Emulate the VMLAUNCH instruction */
7178 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7179 {
7180         return nested_vmx_run(vcpu, true);
7181 }
7182
7183 /* Emulate the VMRESUME instruction */
7184 static int handle_vmresume(struct kvm_vcpu *vcpu)
7185 {
7186
7187         return nested_vmx_run(vcpu, false);
7188 }
7189
7190 enum vmcs_field_type {
7191         VMCS_FIELD_TYPE_U16 = 0,
7192         VMCS_FIELD_TYPE_U64 = 1,
7193         VMCS_FIELD_TYPE_U32 = 2,
7194         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
7195 };
7196
7197 static inline int vmcs_field_type(unsigned long field)
7198 {
7199         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
7200                 return VMCS_FIELD_TYPE_U32;
7201         return (field >> 13) & 0x3 ;
7202 }
7203
7204 static inline int vmcs_field_readonly(unsigned long field)
7205 {
7206         return (((field >> 10) & 0x3) == 1);
7207 }
7208
7209 /*
7210  * Read a vmcs12 field. Since these can have varying lengths and we return
7211  * one type, we chose the biggest type (u64) and zero-extend the return value
7212  * to that size. Note that the caller, handle_vmread, might need to use only
7213  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7214  * 64-bit fields are to be returned).
7215  */
7216 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7217                                   unsigned long field, u64 *ret)
7218 {
7219         short offset = vmcs_field_to_offset(field);
7220         char *p;
7221
7222         if (offset < 0)
7223                 return offset;
7224
7225         p = ((char *)(get_vmcs12(vcpu))) + offset;
7226
7227         switch (vmcs_field_type(field)) {
7228         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7229                 *ret = *((natural_width *)p);
7230                 return 0;
7231         case VMCS_FIELD_TYPE_U16:
7232                 *ret = *((u16 *)p);
7233                 return 0;
7234         case VMCS_FIELD_TYPE_U32:
7235                 *ret = *((u32 *)p);
7236                 return 0;
7237         case VMCS_FIELD_TYPE_U64:
7238                 *ret = *((u64 *)p);
7239                 return 0;
7240         default:
7241                 WARN_ON(1);
7242                 return -ENOENT;
7243         }
7244 }
7245
7246
7247 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7248                                    unsigned long field, u64 field_value){
7249         short offset = vmcs_field_to_offset(field);
7250         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7251         if (offset < 0)
7252                 return offset;
7253
7254         switch (vmcs_field_type(field)) {
7255         case VMCS_FIELD_TYPE_U16:
7256                 *(u16 *)p = field_value;
7257                 return 0;
7258         case VMCS_FIELD_TYPE_U32:
7259                 *(u32 *)p = field_value;
7260                 return 0;
7261         case VMCS_FIELD_TYPE_U64:
7262                 *(u64 *)p = field_value;
7263                 return 0;
7264         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7265                 *(natural_width *)p = field_value;
7266                 return 0;
7267         default:
7268                 WARN_ON(1);
7269                 return -ENOENT;
7270         }
7271
7272 }
7273
7274 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7275 {
7276         int i;
7277         unsigned long field;
7278         u64 field_value;
7279         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7280         const unsigned long *fields = shadow_read_write_fields;
7281         const int num_fields = max_shadow_read_write_fields;
7282
7283         preempt_disable();
7284
7285         vmcs_load(shadow_vmcs);
7286
7287         for (i = 0; i < num_fields; i++) {
7288                 field = fields[i];
7289                 switch (vmcs_field_type(field)) {
7290                 case VMCS_FIELD_TYPE_U16:
7291                         field_value = vmcs_read16(field);
7292                         break;
7293                 case VMCS_FIELD_TYPE_U32:
7294                         field_value = vmcs_read32(field);
7295                         break;
7296                 case VMCS_FIELD_TYPE_U64:
7297                         field_value = vmcs_read64(field);
7298                         break;
7299                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7300                         field_value = vmcs_readl(field);
7301                         break;
7302                 default:
7303                         WARN_ON(1);
7304                         continue;
7305                 }
7306                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7307         }
7308
7309         vmcs_clear(shadow_vmcs);
7310         vmcs_load(vmx->loaded_vmcs->vmcs);
7311
7312         preempt_enable();
7313 }
7314
7315 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7316 {
7317         const unsigned long *fields[] = {
7318                 shadow_read_write_fields,
7319                 shadow_read_only_fields
7320         };
7321         const int max_fields[] = {
7322                 max_shadow_read_write_fields,
7323                 max_shadow_read_only_fields
7324         };
7325         int i, q;
7326         unsigned long field;
7327         u64 field_value = 0;
7328         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7329
7330         vmcs_load(shadow_vmcs);
7331
7332         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7333                 for (i = 0; i < max_fields[q]; i++) {
7334                         field = fields[q][i];
7335                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7336
7337                         switch (vmcs_field_type(field)) {
7338                         case VMCS_FIELD_TYPE_U16:
7339                                 vmcs_write16(field, (u16)field_value);
7340                                 break;
7341                         case VMCS_FIELD_TYPE_U32:
7342                                 vmcs_write32(field, (u32)field_value);
7343                                 break;
7344                         case VMCS_FIELD_TYPE_U64:
7345                                 vmcs_write64(field, (u64)field_value);
7346                                 break;
7347                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7348                                 vmcs_writel(field, (long)field_value);
7349                                 break;
7350                         default:
7351                                 WARN_ON(1);
7352                                 break;
7353                         }
7354                 }
7355         }
7356
7357         vmcs_clear(shadow_vmcs);
7358         vmcs_load(vmx->loaded_vmcs->vmcs);
7359 }
7360
7361 /*
7362  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7363  * used before) all generate the same failure when it is missing.
7364  */
7365 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7366 {
7367         struct vcpu_vmx *vmx = to_vmx(vcpu);
7368         if (vmx->nested.current_vmptr == -1ull) {
7369                 nested_vmx_failInvalid(vcpu);
7370                 skip_emulated_instruction(vcpu);
7371                 return 0;
7372         }
7373         return 1;
7374 }
7375
7376 static int handle_vmread(struct kvm_vcpu *vcpu)
7377 {
7378         unsigned long field;
7379         u64 field_value;
7380         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7381         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7382         gva_t gva = 0;
7383
7384         if (!nested_vmx_check_permission(vcpu) ||
7385             !nested_vmx_check_vmcs12(vcpu))
7386                 return 1;
7387
7388         /* Decode instruction info and find the field to read */
7389         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7390         /* Read the field, zero-extended to a u64 field_value */
7391         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7392                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7393                 skip_emulated_instruction(vcpu);
7394                 return 1;
7395         }
7396         /*
7397          * Now copy part of this value to register or memory, as requested.
7398          * Note that the number of bits actually copied is 32 or 64 depending
7399          * on the guest's mode (32 or 64 bit), not on the given field's length.
7400          */
7401         if (vmx_instruction_info & (1u << 10)) {
7402                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7403                         field_value);
7404         } else {
7405                 if (get_vmx_mem_address(vcpu, exit_qualification,
7406                                 vmx_instruction_info, true, &gva))
7407                         return 1;
7408                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7409                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7410                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7411         }
7412
7413         nested_vmx_succeed(vcpu);
7414         skip_emulated_instruction(vcpu);
7415         return 1;
7416 }
7417
7418
7419 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7420 {
7421         unsigned long field;
7422         gva_t gva;
7423         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7424         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7425         /* The value to write might be 32 or 64 bits, depending on L1's long
7426          * mode, and eventually we need to write that into a field of several
7427          * possible lengths. The code below first zero-extends the value to 64
7428          * bit (field_value), and then copies only the appropriate number of
7429          * bits into the vmcs12 field.
7430          */
7431         u64 field_value = 0;
7432         struct x86_exception e;
7433
7434         if (!nested_vmx_check_permission(vcpu) ||
7435             !nested_vmx_check_vmcs12(vcpu))
7436                 return 1;
7437
7438         if (vmx_instruction_info & (1u << 10))
7439                 field_value = kvm_register_readl(vcpu,
7440                         (((vmx_instruction_info) >> 3) & 0xf));
7441         else {
7442                 if (get_vmx_mem_address(vcpu, exit_qualification,
7443                                 vmx_instruction_info, false, &gva))
7444                         return 1;
7445                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7446                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7447                         kvm_inject_page_fault(vcpu, &e);
7448                         return 1;
7449                 }
7450         }
7451
7452
7453         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7454         if (vmcs_field_readonly(field)) {
7455                 nested_vmx_failValid(vcpu,
7456                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7457                 skip_emulated_instruction(vcpu);
7458                 return 1;
7459         }
7460
7461         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7462                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7463                 skip_emulated_instruction(vcpu);
7464                 return 1;
7465         }
7466
7467         nested_vmx_succeed(vcpu);
7468         skip_emulated_instruction(vcpu);
7469         return 1;
7470 }
7471
7472 /* Emulate the VMPTRLD instruction */
7473 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7474 {
7475         struct vcpu_vmx *vmx = to_vmx(vcpu);
7476         gpa_t vmptr;
7477
7478         if (!nested_vmx_check_permission(vcpu))
7479                 return 1;
7480
7481         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7482                 return 1;
7483
7484         if (vmx->nested.current_vmptr != vmptr) {
7485                 struct vmcs12 *new_vmcs12;
7486                 struct page *page;
7487                 page = nested_get_page(vcpu, vmptr);
7488                 if (page == NULL) {
7489                         nested_vmx_failInvalid(vcpu);
7490                         skip_emulated_instruction(vcpu);
7491                         return 1;
7492                 }
7493                 new_vmcs12 = kmap(page);
7494                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7495                         kunmap(page);
7496                         nested_release_page_clean(page);
7497                         nested_vmx_failValid(vcpu,
7498                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7499                         skip_emulated_instruction(vcpu);
7500                         return 1;
7501                 }
7502
7503                 nested_release_vmcs12(vmx);
7504                 vmx->nested.current_vmptr = vmptr;
7505                 vmx->nested.current_vmcs12 = new_vmcs12;
7506                 vmx->nested.current_vmcs12_page = page;
7507                 /*
7508                  * Load VMCS12 from guest memory since it is not already
7509                  * cached.
7510                  */
7511                 memcpy(vmx->nested.cached_vmcs12,
7512                        vmx->nested.current_vmcs12, VMCS12_SIZE);
7513
7514                 if (enable_shadow_vmcs) {
7515                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7516                                       SECONDARY_EXEC_SHADOW_VMCS);
7517                         vmcs_write64(VMCS_LINK_POINTER,
7518                                      __pa(vmx->nested.current_shadow_vmcs));
7519                         vmx->nested.sync_shadow_vmcs = true;
7520                 }
7521         }
7522
7523         nested_vmx_succeed(vcpu);
7524         skip_emulated_instruction(vcpu);
7525         return 1;
7526 }
7527
7528 /* Emulate the VMPTRST instruction */
7529 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7530 {
7531         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7532         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7533         gva_t vmcs_gva;
7534         struct x86_exception e;
7535
7536         if (!nested_vmx_check_permission(vcpu))
7537                 return 1;
7538
7539         if (get_vmx_mem_address(vcpu, exit_qualification,
7540                         vmx_instruction_info, true, &vmcs_gva))
7541                 return 1;
7542         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7543         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7544                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7545                                  sizeof(u64), &e)) {
7546                 kvm_inject_page_fault(vcpu, &e);
7547                 return 1;
7548         }
7549         nested_vmx_succeed(vcpu);
7550         skip_emulated_instruction(vcpu);
7551         return 1;
7552 }
7553
7554 /* Emulate the INVEPT instruction */
7555 static int handle_invept(struct kvm_vcpu *vcpu)
7556 {
7557         struct vcpu_vmx *vmx = to_vmx(vcpu);
7558         u32 vmx_instruction_info, types;
7559         unsigned long type;
7560         gva_t gva;
7561         struct x86_exception e;
7562         struct {
7563                 u64 eptp, gpa;
7564         } operand;
7565
7566         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7567               SECONDARY_EXEC_ENABLE_EPT) ||
7568             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7569                 kvm_queue_exception(vcpu, UD_VECTOR);
7570                 return 1;
7571         }
7572
7573         if (!nested_vmx_check_permission(vcpu))
7574                 return 1;
7575
7576         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7577                 kvm_queue_exception(vcpu, UD_VECTOR);
7578                 return 1;
7579         }
7580
7581         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7582         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7583
7584         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7585
7586         if (!(types & (1UL << type))) {
7587                 nested_vmx_failValid(vcpu,
7588                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7589                 skip_emulated_instruction(vcpu);
7590                 return 1;
7591         }
7592
7593         /* According to the Intel VMX instruction reference, the memory
7594          * operand is read even if it isn't needed (e.g., for type==global)
7595          */
7596         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7597                         vmx_instruction_info, false, &gva))
7598                 return 1;
7599         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7600                                 sizeof(operand), &e)) {
7601                 kvm_inject_page_fault(vcpu, &e);
7602                 return 1;
7603         }
7604
7605         switch (type) {
7606         case VMX_EPT_EXTENT_GLOBAL:
7607         /*
7608          * TODO: track mappings and invalidate
7609          * single context requests appropriately
7610          */
7611         case VMX_EPT_EXTENT_CONTEXT:
7612                 kvm_mmu_sync_roots(vcpu);
7613                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7614                 nested_vmx_succeed(vcpu);
7615                 break;
7616         default:
7617                 BUG_ON(1);
7618                 break;
7619         }
7620
7621         skip_emulated_instruction(vcpu);
7622         return 1;
7623 }
7624
7625 static int handle_invvpid(struct kvm_vcpu *vcpu)
7626 {
7627         struct vcpu_vmx *vmx = to_vmx(vcpu);
7628         u32 vmx_instruction_info;
7629         unsigned long type, types;
7630         gva_t gva;
7631         struct x86_exception e;
7632         int vpid;
7633
7634         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7635               SECONDARY_EXEC_ENABLE_VPID) ||
7636                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7637                 kvm_queue_exception(vcpu, UD_VECTOR);
7638                 return 1;
7639         }
7640
7641         if (!nested_vmx_check_permission(vcpu))
7642                 return 1;
7643
7644         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7645         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7646
7647         types = (vmx->nested.nested_vmx_vpid_caps >> 8) & 0x7;
7648
7649         if (!(types & (1UL << type))) {
7650                 nested_vmx_failValid(vcpu,
7651                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7652                 skip_emulated_instruction(vcpu);
7653                 return 1;
7654         }
7655
7656         /* according to the intel vmx instruction reference, the memory
7657          * operand is read even if it isn't needed (e.g., for type==global)
7658          */
7659         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7660                         vmx_instruction_info, false, &gva))
7661                 return 1;
7662         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7663                                 sizeof(u32), &e)) {
7664                 kvm_inject_page_fault(vcpu, &e);
7665                 return 1;
7666         }
7667
7668         switch (type) {
7669         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7670                 /*
7671                  * Old versions of KVM use the single-context version so we
7672                  * have to support it; just treat it the same as all-context.
7673                  */
7674         case VMX_VPID_EXTENT_ALL_CONTEXT:
7675                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
7676                 nested_vmx_succeed(vcpu);
7677                 break;
7678         default:
7679                 /* Trap individual address invalidation invvpid calls */
7680                 BUG_ON(1);
7681                 break;
7682         }
7683
7684         skip_emulated_instruction(vcpu);
7685         return 1;
7686 }
7687
7688 static int handle_pml_full(struct kvm_vcpu *vcpu)
7689 {
7690         unsigned long exit_qualification;
7691
7692         trace_kvm_pml_full(vcpu->vcpu_id);
7693
7694         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7695
7696         /*
7697          * PML buffer FULL happened while executing iret from NMI,
7698          * "blocked by NMI" bit has to be set before next VM entry.
7699          */
7700         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7701                         cpu_has_virtual_nmis() &&
7702                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7703                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7704                                 GUEST_INTR_STATE_NMI);
7705
7706         /*
7707          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7708          * here.., and there's no userspace involvement needed for PML.
7709          */
7710         return 1;
7711 }
7712
7713 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7714 {
7715         kvm_lapic_expired_hv_timer(vcpu);
7716         return 1;
7717 }
7718
7719 /*
7720  * The exit handlers return 1 if the exit was handled fully and guest execution
7721  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7722  * to be done to userspace and return 0.
7723  */
7724 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7725         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7726         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7727         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7728         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7729         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7730         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7731         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7732         [EXIT_REASON_CPUID]                   = handle_cpuid,
7733         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7734         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7735         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7736         [EXIT_REASON_HLT]                     = handle_halt,
7737         [EXIT_REASON_INVD]                    = handle_invd,
7738         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7739         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7740         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7741         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7742         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7743         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7744         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7745         [EXIT_REASON_VMREAD]                  = handle_vmread,
7746         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7747         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7748         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7749         [EXIT_REASON_VMON]                    = handle_vmon,
7750         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7751         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7752         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7753         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7754         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7755         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7756         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7757         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7758         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7759         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7760         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7761         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7762         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7763         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7764         [EXIT_REASON_INVEPT]                  = handle_invept,
7765         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7766         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7767         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7768         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7769         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
7770 };
7771
7772 static const int kvm_vmx_max_exit_handlers =
7773         ARRAY_SIZE(kvm_vmx_exit_handlers);
7774
7775 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7776                                        struct vmcs12 *vmcs12)
7777 {
7778         unsigned long exit_qualification;
7779         gpa_t bitmap, last_bitmap;
7780         unsigned int port;
7781         int size;
7782         u8 b;
7783
7784         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7785                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7786
7787         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7788
7789         port = exit_qualification >> 16;
7790         size = (exit_qualification & 7) + 1;
7791
7792         last_bitmap = (gpa_t)-1;
7793         b = -1;
7794
7795         while (size > 0) {
7796                 if (port < 0x8000)
7797                         bitmap = vmcs12->io_bitmap_a;
7798                 else if (port < 0x10000)
7799                         bitmap = vmcs12->io_bitmap_b;
7800                 else
7801                         return true;
7802                 bitmap += (port & 0x7fff) / 8;
7803
7804                 if (last_bitmap != bitmap)
7805                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7806                                 return true;
7807                 if (b & (1 << (port & 7)))
7808                         return true;
7809
7810                 port++;
7811                 size--;
7812                 last_bitmap = bitmap;
7813         }
7814
7815         return false;
7816 }
7817
7818 /*
7819  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7820  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7821  * disinterest in the current event (read or write a specific MSR) by using an
7822  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7823  */
7824 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7825         struct vmcs12 *vmcs12, u32 exit_reason)
7826 {
7827         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7828         gpa_t bitmap;
7829
7830         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7831                 return true;
7832
7833         /*
7834          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7835          * for the four combinations of read/write and low/high MSR numbers.
7836          * First we need to figure out which of the four to use:
7837          */
7838         bitmap = vmcs12->msr_bitmap;
7839         if (exit_reason == EXIT_REASON_MSR_WRITE)
7840                 bitmap += 2048;
7841         if (msr_index >= 0xc0000000) {
7842                 msr_index -= 0xc0000000;
7843                 bitmap += 1024;
7844         }
7845
7846         /* Then read the msr_index'th bit from this bitmap: */
7847         if (msr_index < 1024*8) {
7848                 unsigned char b;
7849                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7850                         return true;
7851                 return 1 & (b >> (msr_index & 7));
7852         } else
7853                 return true; /* let L1 handle the wrong parameter */
7854 }
7855
7856 /*
7857  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7858  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7859  * intercept (via guest_host_mask etc.) the current event.
7860  */
7861 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7862         struct vmcs12 *vmcs12)
7863 {
7864         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7865         int cr = exit_qualification & 15;
7866         int reg = (exit_qualification >> 8) & 15;
7867         unsigned long val = kvm_register_readl(vcpu, reg);
7868
7869         switch ((exit_qualification >> 4) & 3) {
7870         case 0: /* mov to cr */
7871                 switch (cr) {
7872                 case 0:
7873                         if (vmcs12->cr0_guest_host_mask &
7874                             (val ^ vmcs12->cr0_read_shadow))
7875                                 return true;
7876                         break;
7877                 case 3:
7878                         if ((vmcs12->cr3_target_count >= 1 &&
7879                                         vmcs12->cr3_target_value0 == val) ||
7880                                 (vmcs12->cr3_target_count >= 2 &&
7881                                         vmcs12->cr3_target_value1 == val) ||
7882                                 (vmcs12->cr3_target_count >= 3 &&
7883                                         vmcs12->cr3_target_value2 == val) ||
7884                                 (vmcs12->cr3_target_count >= 4 &&
7885                                         vmcs12->cr3_target_value3 == val))
7886                                 return false;
7887                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7888                                 return true;
7889                         break;
7890                 case 4:
7891                         if (vmcs12->cr4_guest_host_mask &
7892                             (vmcs12->cr4_read_shadow ^ val))
7893                                 return true;
7894                         break;
7895                 case 8:
7896                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7897                                 return true;
7898                         break;
7899                 }
7900                 break;
7901         case 2: /* clts */
7902                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7903                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7904                         return true;
7905                 break;
7906         case 1: /* mov from cr */
7907                 switch (cr) {
7908                 case 3:
7909                         if (vmcs12->cpu_based_vm_exec_control &
7910                             CPU_BASED_CR3_STORE_EXITING)
7911                                 return true;
7912                         break;
7913                 case 8:
7914                         if (vmcs12->cpu_based_vm_exec_control &
7915                             CPU_BASED_CR8_STORE_EXITING)
7916                                 return true;
7917                         break;
7918                 }
7919                 break;
7920         case 3: /* lmsw */
7921                 /*
7922                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7923                  * cr0. Other attempted changes are ignored, with no exit.
7924                  */
7925                 if (vmcs12->cr0_guest_host_mask & 0xe &
7926                     (val ^ vmcs12->cr0_read_shadow))
7927                         return true;
7928                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7929                     !(vmcs12->cr0_read_shadow & 0x1) &&
7930                     (val & 0x1))
7931                         return true;
7932                 break;
7933         }
7934         return false;
7935 }
7936
7937 /*
7938  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7939  * should handle it ourselves in L0 (and then continue L2). Only call this
7940  * when in is_guest_mode (L2).
7941  */
7942 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7943 {
7944         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7945         struct vcpu_vmx *vmx = to_vmx(vcpu);
7946         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7947         u32 exit_reason = vmx->exit_reason;
7948
7949         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7950                                 vmcs_readl(EXIT_QUALIFICATION),
7951                                 vmx->idt_vectoring_info,
7952                                 intr_info,
7953                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7954                                 KVM_ISA_VMX);
7955
7956         if (vmx->nested.nested_run_pending)
7957                 return false;
7958
7959         if (unlikely(vmx->fail)) {
7960                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7961                                     vmcs_read32(VM_INSTRUCTION_ERROR));
7962                 return true;
7963         }
7964
7965         switch (exit_reason) {
7966         case EXIT_REASON_EXCEPTION_NMI:
7967                 if (!is_exception(intr_info))
7968                         return false;
7969                 else if (is_page_fault(intr_info))
7970                         return enable_ept;
7971                 else if (is_no_device(intr_info) &&
7972                          !(vmcs12->guest_cr0 & X86_CR0_TS))
7973                         return false;
7974                 else if (is_debug(intr_info) &&
7975                          vcpu->guest_debug &
7976                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
7977                         return false;
7978                 else if (is_breakpoint(intr_info) &&
7979                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
7980                         return false;
7981                 return vmcs12->exception_bitmap &
7982                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7983         case EXIT_REASON_EXTERNAL_INTERRUPT:
7984                 return false;
7985         case EXIT_REASON_TRIPLE_FAULT:
7986                 return true;
7987         case EXIT_REASON_PENDING_INTERRUPT:
7988                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7989         case EXIT_REASON_NMI_WINDOW:
7990                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7991         case EXIT_REASON_TASK_SWITCH:
7992                 return true;
7993         case EXIT_REASON_CPUID:
7994                 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7995                         return false;
7996                 return true;
7997         case EXIT_REASON_HLT:
7998                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7999         case EXIT_REASON_INVD:
8000                 return true;
8001         case EXIT_REASON_INVLPG:
8002                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8003         case EXIT_REASON_RDPMC:
8004                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8005         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8006                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8007         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8008         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8009         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8010         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8011         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8012         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8013                 /*
8014                  * VMX instructions trap unconditionally. This allows L1 to
8015                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
8016                  */
8017                 return true;
8018         case EXIT_REASON_CR_ACCESS:
8019                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8020         case EXIT_REASON_DR_ACCESS:
8021                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8022         case EXIT_REASON_IO_INSTRUCTION:
8023                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8024         case EXIT_REASON_MSR_READ:
8025         case EXIT_REASON_MSR_WRITE:
8026                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8027         case EXIT_REASON_INVALID_STATE:
8028                 return true;
8029         case EXIT_REASON_MWAIT_INSTRUCTION:
8030                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8031         case EXIT_REASON_MONITOR_TRAP_FLAG:
8032                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8033         case EXIT_REASON_MONITOR_INSTRUCTION:
8034                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8035         case EXIT_REASON_PAUSE_INSTRUCTION:
8036                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8037                         nested_cpu_has2(vmcs12,
8038                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8039         case EXIT_REASON_MCE_DURING_VMENTRY:
8040                 return false;
8041         case EXIT_REASON_TPR_BELOW_THRESHOLD:
8042                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8043         case EXIT_REASON_APIC_ACCESS:
8044                 return nested_cpu_has2(vmcs12,
8045                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8046         case EXIT_REASON_APIC_WRITE:
8047         case EXIT_REASON_EOI_INDUCED:
8048                 /* apic_write and eoi_induced should exit unconditionally. */
8049                 return true;
8050         case EXIT_REASON_EPT_VIOLATION:
8051                 /*
8052                  * L0 always deals with the EPT violation. If nested EPT is
8053                  * used, and the nested mmu code discovers that the address is
8054                  * missing in the guest EPT table (EPT12), the EPT violation
8055                  * will be injected with nested_ept_inject_page_fault()
8056                  */
8057                 return false;
8058         case EXIT_REASON_EPT_MISCONFIG:
8059                 /*
8060                  * L2 never uses directly L1's EPT, but rather L0's own EPT
8061                  * table (shadow on EPT) or a merged EPT table that L0 built
8062                  * (EPT on EPT). So any problems with the structure of the
8063                  * table is L0's fault.
8064                  */
8065                 return false;
8066         case EXIT_REASON_WBINVD:
8067                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8068         case EXIT_REASON_XSETBV:
8069                 return true;
8070         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8071                 /*
8072                  * This should never happen, since it is not possible to
8073                  * set XSS to a non-zero value---neither in L1 nor in L2.
8074                  * If if it were, XSS would have to be checked against
8075                  * the XSS exit bitmap in vmcs12.
8076                  */
8077                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8078         case EXIT_REASON_PREEMPTION_TIMER:
8079                 return false;
8080         default:
8081                 return true;
8082         }
8083 }
8084
8085 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8086 {
8087         *info1 = vmcs_readl(EXIT_QUALIFICATION);
8088         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8089 }
8090
8091 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8092 {
8093         if (vmx->pml_pg) {
8094                 __free_page(vmx->pml_pg);
8095                 vmx->pml_pg = NULL;
8096         }
8097 }
8098
8099 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8100 {
8101         struct vcpu_vmx *vmx = to_vmx(vcpu);
8102         u64 *pml_buf;
8103         u16 pml_idx;
8104
8105         pml_idx = vmcs_read16(GUEST_PML_INDEX);
8106
8107         /* Do nothing if PML buffer is empty */
8108         if (pml_idx == (PML_ENTITY_NUM - 1))
8109                 return;
8110
8111         /* PML index always points to next available PML buffer entity */
8112         if (pml_idx >= PML_ENTITY_NUM)
8113                 pml_idx = 0;
8114         else
8115                 pml_idx++;
8116
8117         pml_buf = page_address(vmx->pml_pg);
8118         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8119                 u64 gpa;
8120
8121                 gpa = pml_buf[pml_idx];
8122                 WARN_ON(gpa & (PAGE_SIZE - 1));
8123                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8124         }
8125
8126         /* reset PML index */
8127         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8128 }
8129
8130 /*
8131  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8132  * Called before reporting dirty_bitmap to userspace.
8133  */
8134 static void kvm_flush_pml_buffers(struct kvm *kvm)
8135 {
8136         int i;
8137         struct kvm_vcpu *vcpu;
8138         /*
8139          * We only need to kick vcpu out of guest mode here, as PML buffer
8140          * is flushed at beginning of all VMEXITs, and it's obvious that only
8141          * vcpus running in guest are possible to have unflushed GPAs in PML
8142          * buffer.
8143          */
8144         kvm_for_each_vcpu(i, vcpu, kvm)
8145                 kvm_vcpu_kick(vcpu);
8146 }
8147
8148 static void vmx_dump_sel(char *name, uint32_t sel)
8149 {
8150         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8151                name, vmcs_read32(sel),
8152                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8153                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8154                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8155 }
8156
8157 static void vmx_dump_dtsel(char *name, uint32_t limit)
8158 {
8159         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
8160                name, vmcs_read32(limit),
8161                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8162 }
8163
8164 static void dump_vmcs(void)
8165 {
8166         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8167         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8168         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8169         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8170         u32 secondary_exec_control = 0;
8171         unsigned long cr4 = vmcs_readl(GUEST_CR4);
8172         u64 efer = vmcs_read64(GUEST_IA32_EFER);
8173         int i, n;
8174
8175         if (cpu_has_secondary_exec_ctrls())
8176                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8177
8178         pr_err("*** Guest State ***\n");
8179         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8180                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8181                vmcs_readl(CR0_GUEST_HOST_MASK));
8182         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8183                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8184         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8185         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8186             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8187         {
8188                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
8189                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8190                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
8191                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8192         }
8193         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
8194                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8195         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
8196                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8197         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8198                vmcs_readl(GUEST_SYSENTER_ESP),
8199                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8200         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
8201         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
8202         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
8203         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
8204         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
8205         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
8206         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8207         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8208         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8209         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
8210         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8211             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8212                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
8213                        efer, vmcs_read64(GUEST_IA32_PAT));
8214         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
8215                vmcs_read64(GUEST_IA32_DEBUGCTL),
8216                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8217         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8218                 pr_err("PerfGlobCtl = 0x%016llx\n",
8219                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8220         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8221                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8222         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
8223                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8224                vmcs_read32(GUEST_ACTIVITY_STATE));
8225         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8226                 pr_err("InterruptStatus = %04x\n",
8227                        vmcs_read16(GUEST_INTR_STATUS));
8228
8229         pr_err("*** Host State ***\n");
8230         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8231                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8232         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8233                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8234                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8235                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8236                vmcs_read16(HOST_TR_SELECTOR));
8237         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8238                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8239                vmcs_readl(HOST_TR_BASE));
8240         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8241                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8242         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8243                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8244                vmcs_readl(HOST_CR4));
8245         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8246                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8247                vmcs_read32(HOST_IA32_SYSENTER_CS),
8248                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8249         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8250                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
8251                        vmcs_read64(HOST_IA32_EFER),
8252                        vmcs_read64(HOST_IA32_PAT));
8253         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8254                 pr_err("PerfGlobCtl = 0x%016llx\n",
8255                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8256
8257         pr_err("*** Control State ***\n");
8258         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8259                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8260         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8261         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8262                vmcs_read32(EXCEPTION_BITMAP),
8263                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8264                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8265         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8266                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8267                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8268                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8269         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8270                vmcs_read32(VM_EXIT_INTR_INFO),
8271                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8272                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8273         pr_err("        reason=%08x qualification=%016lx\n",
8274                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8275         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8276                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8277                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8278         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8279         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8280                 pr_err("TSC Multiplier = 0x%016llx\n",
8281                        vmcs_read64(TSC_MULTIPLIER));
8282         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8283                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8284         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8285                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8286         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8287                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8288         n = vmcs_read32(CR3_TARGET_COUNT);
8289         for (i = 0; i + 1 < n; i += 4)
8290                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8291                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8292                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8293         if (i < n)
8294                 pr_err("CR3 target%u=%016lx\n",
8295                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8296         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8297                 pr_err("PLE Gap=%08x Window=%08x\n",
8298                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8299         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8300                 pr_err("Virtual processor ID = 0x%04x\n",
8301                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8302 }
8303
8304 /*
8305  * The guest has exited.  See if we can fix it or if we need userspace
8306  * assistance.
8307  */
8308 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8309 {
8310         struct vcpu_vmx *vmx = to_vmx(vcpu);
8311         u32 exit_reason = vmx->exit_reason;
8312         u32 vectoring_info = vmx->idt_vectoring_info;
8313
8314         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8315
8316         /*
8317          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8318          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8319          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8320          * mode as if vcpus is in root mode, the PML buffer must has been
8321          * flushed already.
8322          */
8323         if (enable_pml)
8324                 vmx_flush_pml_buffer(vcpu);
8325
8326         /* If guest state is invalid, start emulating */
8327         if (vmx->emulation_required)
8328                 return handle_invalid_guest_state(vcpu);
8329
8330         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8331                 nested_vmx_vmexit(vcpu, exit_reason,
8332                                   vmcs_read32(VM_EXIT_INTR_INFO),
8333                                   vmcs_readl(EXIT_QUALIFICATION));
8334                 return 1;
8335         }
8336
8337         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8338                 dump_vmcs();
8339                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8340                 vcpu->run->fail_entry.hardware_entry_failure_reason
8341                         = exit_reason;
8342                 return 0;
8343         }
8344
8345         if (unlikely(vmx->fail)) {
8346                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8347                 vcpu->run->fail_entry.hardware_entry_failure_reason
8348                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8349                 return 0;
8350         }
8351
8352         /*
8353          * Note:
8354          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8355          * delivery event since it indicates guest is accessing MMIO.
8356          * The vm-exit can be triggered again after return to guest that
8357          * will cause infinite loop.
8358          */
8359         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8360                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8361                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8362                         exit_reason != EXIT_REASON_PML_FULL &&
8363                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8364                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8365                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8366                 vcpu->run->internal.ndata = 2;
8367                 vcpu->run->internal.data[0] = vectoring_info;
8368                 vcpu->run->internal.data[1] = exit_reason;
8369                 return 0;
8370         }
8371
8372         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8373             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8374                                         get_vmcs12(vcpu))))) {
8375                 if (vmx_interrupt_allowed(vcpu)) {
8376                         vmx->soft_vnmi_blocked = 0;
8377                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8378                            vcpu->arch.nmi_pending) {
8379                         /*
8380                          * This CPU don't support us in finding the end of an
8381                          * NMI-blocked window if the guest runs with IRQs
8382                          * disabled. So we pull the trigger after 1 s of
8383                          * futile waiting, but inform the user about this.
8384                          */
8385                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8386                                "state on VCPU %d after 1 s timeout\n",
8387                                __func__, vcpu->vcpu_id);
8388                         vmx->soft_vnmi_blocked = 0;
8389                 }
8390         }
8391
8392         if (exit_reason < kvm_vmx_max_exit_handlers
8393             && kvm_vmx_exit_handlers[exit_reason])
8394                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8395         else {
8396                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8397                 kvm_queue_exception(vcpu, UD_VECTOR);
8398                 return 1;
8399         }
8400 }
8401
8402 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8403 {
8404         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8405
8406         if (is_guest_mode(vcpu) &&
8407                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8408                 return;
8409
8410         if (irr == -1 || tpr < irr) {
8411                 vmcs_write32(TPR_THRESHOLD, 0);
8412                 return;
8413         }
8414
8415         vmcs_write32(TPR_THRESHOLD, irr);
8416 }
8417
8418 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8419 {
8420         u32 sec_exec_control;
8421
8422         /*
8423          * There is not point to enable virtualize x2apic without enable
8424          * apicv
8425          */
8426         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8427                                 !kvm_vcpu_apicv_active(vcpu))
8428                 return;
8429
8430         if (!cpu_need_tpr_shadow(vcpu))
8431                 return;
8432
8433         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8434
8435         if (set) {
8436                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8437                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8438         } else {
8439                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8440                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8441         }
8442         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8443
8444         vmx_set_msr_bitmap(vcpu);
8445 }
8446
8447 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8448 {
8449         struct vcpu_vmx *vmx = to_vmx(vcpu);
8450
8451         /*
8452          * Currently we do not handle the nested case where L2 has an
8453          * APIC access page of its own; that page is still pinned.
8454          * Hence, we skip the case where the VCPU is in guest mode _and_
8455          * L1 prepared an APIC access page for L2.
8456          *
8457          * For the case where L1 and L2 share the same APIC access page
8458          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8459          * in the vmcs12), this function will only update either the vmcs01
8460          * or the vmcs02.  If the former, the vmcs02 will be updated by
8461          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8462          * the next L2->L1 exit.
8463          */
8464         if (!is_guest_mode(vcpu) ||
8465             !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
8466                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8467                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8468 }
8469
8470 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
8471 {
8472         u16 status;
8473         u8 old;
8474
8475         if (max_isr == -1)
8476                 max_isr = 0;
8477
8478         status = vmcs_read16(GUEST_INTR_STATUS);
8479         old = status >> 8;
8480         if (max_isr != old) {
8481                 status &= 0xff;
8482                 status |= max_isr << 8;
8483                 vmcs_write16(GUEST_INTR_STATUS, status);
8484         }
8485 }
8486
8487 static void vmx_set_rvi(int vector)
8488 {
8489         u16 status;
8490         u8 old;
8491
8492         if (vector == -1)
8493                 vector = 0;
8494
8495         status = vmcs_read16(GUEST_INTR_STATUS);
8496         old = (u8)status & 0xff;
8497         if ((u8)vector != old) {
8498                 status &= ~0xff;
8499                 status |= (u8)vector;
8500                 vmcs_write16(GUEST_INTR_STATUS, status);
8501         }
8502 }
8503
8504 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8505 {
8506         if (!is_guest_mode(vcpu)) {
8507                 vmx_set_rvi(max_irr);
8508                 return;
8509         }
8510
8511         if (max_irr == -1)
8512                 return;
8513
8514         /*
8515          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8516          * handles it.
8517          */
8518         if (nested_exit_on_intr(vcpu))
8519                 return;
8520
8521         /*
8522          * Else, fall back to pre-APICv interrupt injection since L2
8523          * is run without virtual interrupt delivery.
8524          */
8525         if (!kvm_event_needs_reinjection(vcpu) &&
8526             vmx_interrupt_allowed(vcpu)) {
8527                 kvm_queue_interrupt(vcpu, max_irr, false);
8528                 vmx_inject_irq(vcpu);
8529         }
8530 }
8531
8532 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8533 {
8534         if (!kvm_vcpu_apicv_active(vcpu))
8535                 return;
8536
8537         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8538         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8539         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8540         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8541 }
8542
8543 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8544 {
8545         u32 exit_intr_info;
8546
8547         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8548               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8549                 return;
8550
8551         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8552         exit_intr_info = vmx->exit_intr_info;
8553
8554         /* Handle machine checks before interrupts are enabled */
8555         if (is_machine_check(exit_intr_info))
8556                 kvm_machine_check();
8557
8558         /* We need to handle NMIs before interrupts are enabled */
8559         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
8560             (exit_intr_info & INTR_INFO_VALID_MASK)) {
8561                 kvm_before_handle_nmi(&vmx->vcpu);
8562                 asm("int $2");
8563                 kvm_after_handle_nmi(&vmx->vcpu);
8564         }
8565 }
8566
8567 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8568 {
8569         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8570         register void *__sp asm(_ASM_SP);
8571
8572         /*
8573          * If external interrupt exists, IF bit is set in rflags/eflags on the
8574          * interrupt stack frame, and interrupt will be enabled on a return
8575          * from interrupt handler.
8576          */
8577         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8578                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8579                 unsigned int vector;
8580                 unsigned long entry;
8581                 gate_desc *desc;
8582                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8583 #ifdef CONFIG_X86_64
8584                 unsigned long tmp;
8585 #endif
8586
8587                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8588                 desc = (gate_desc *)vmx->host_idt_base + vector;
8589                 entry = gate_offset(*desc);
8590                 asm volatile(
8591 #ifdef CONFIG_X86_64
8592                         "mov %%" _ASM_SP ", %[sp]\n\t"
8593                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8594                         "push $%c[ss]\n\t"
8595                         "push %[sp]\n\t"
8596 #endif
8597                         "pushf\n\t"
8598                         __ASM_SIZE(push) " $%c[cs]\n\t"
8599                         "call *%[entry]\n\t"
8600                         :
8601 #ifdef CONFIG_X86_64
8602                         [sp]"=&r"(tmp),
8603 #endif
8604                         "+r"(__sp)
8605                         :
8606                         [entry]"r"(entry),
8607                         [ss]"i"(__KERNEL_DS),
8608                         [cs]"i"(__KERNEL_CS)
8609                         );
8610         }
8611 }
8612
8613 static bool vmx_has_high_real_mode_segbase(void)
8614 {
8615         return enable_unrestricted_guest || emulate_invalid_guest_state;
8616 }
8617
8618 static bool vmx_mpx_supported(void)
8619 {
8620         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8621                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8622 }
8623
8624 static bool vmx_xsaves_supported(void)
8625 {
8626         return vmcs_config.cpu_based_2nd_exec_ctrl &
8627                 SECONDARY_EXEC_XSAVES;
8628 }
8629
8630 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8631 {
8632         u32 exit_intr_info;
8633         bool unblock_nmi;
8634         u8 vector;
8635         bool idtv_info_valid;
8636
8637         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8638
8639         if (cpu_has_virtual_nmis()) {
8640                 if (vmx->nmi_known_unmasked)
8641                         return;
8642                 /*
8643                  * Can't use vmx->exit_intr_info since we're not sure what
8644                  * the exit reason is.
8645                  */
8646                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8647                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8648                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8649                 /*
8650                  * SDM 3: 27.7.1.2 (September 2008)
8651                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8652                  * a guest IRET fault.
8653                  * SDM 3: 23.2.2 (September 2008)
8654                  * Bit 12 is undefined in any of the following cases:
8655                  *  If the VM exit sets the valid bit in the IDT-vectoring
8656                  *   information field.
8657                  *  If the VM exit is due to a double fault.
8658                  */
8659                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8660                     vector != DF_VECTOR && !idtv_info_valid)
8661                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8662                                       GUEST_INTR_STATE_NMI);
8663                 else
8664                         vmx->nmi_known_unmasked =
8665                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8666                                   & GUEST_INTR_STATE_NMI);
8667         } else if (unlikely(vmx->soft_vnmi_blocked))
8668                 vmx->vnmi_blocked_time +=
8669                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8670 }
8671
8672 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8673                                       u32 idt_vectoring_info,
8674                                       int instr_len_field,
8675                                       int error_code_field)
8676 {
8677         u8 vector;
8678         int type;
8679         bool idtv_info_valid;
8680
8681         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8682
8683         vcpu->arch.nmi_injected = false;
8684         kvm_clear_exception_queue(vcpu);
8685         kvm_clear_interrupt_queue(vcpu);
8686
8687         if (!idtv_info_valid)
8688                 return;
8689
8690         kvm_make_request(KVM_REQ_EVENT, vcpu);
8691
8692         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8693         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8694
8695         switch (type) {
8696         case INTR_TYPE_NMI_INTR:
8697                 vcpu->arch.nmi_injected = true;
8698                 /*
8699                  * SDM 3: 27.7.1.2 (September 2008)
8700                  * Clear bit "block by NMI" before VM entry if a NMI
8701                  * delivery faulted.
8702                  */
8703                 vmx_set_nmi_mask(vcpu, false);
8704                 break;
8705         case INTR_TYPE_SOFT_EXCEPTION:
8706                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8707                 /* fall through */
8708         case INTR_TYPE_HARD_EXCEPTION:
8709                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8710                         u32 err = vmcs_read32(error_code_field);
8711                         kvm_requeue_exception_e(vcpu, vector, err);
8712                 } else
8713                         kvm_requeue_exception(vcpu, vector);
8714                 break;
8715         case INTR_TYPE_SOFT_INTR:
8716                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8717                 /* fall through */
8718         case INTR_TYPE_EXT_INTR:
8719                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8720                 break;
8721         default:
8722                 break;
8723         }
8724 }
8725
8726 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8727 {
8728         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8729                                   VM_EXIT_INSTRUCTION_LEN,
8730                                   IDT_VECTORING_ERROR_CODE);
8731 }
8732
8733 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8734 {
8735         __vmx_complete_interrupts(vcpu,
8736                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8737                                   VM_ENTRY_INSTRUCTION_LEN,
8738                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8739
8740         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8741 }
8742
8743 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8744 {
8745         int i, nr_msrs;
8746         struct perf_guest_switch_msr *msrs;
8747
8748         msrs = perf_guest_get_msrs(&nr_msrs);
8749
8750         if (!msrs)
8751                 return;
8752
8753         for (i = 0; i < nr_msrs; i++)
8754                 if (msrs[i].host == msrs[i].guest)
8755                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8756                 else
8757                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8758                                         msrs[i].host);
8759 }
8760
8761 void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
8762 {
8763         struct vcpu_vmx *vmx = to_vmx(vcpu);
8764         u64 tscl;
8765         u32 delta_tsc;
8766
8767         if (vmx->hv_deadline_tsc == -1)
8768                 return;
8769
8770         tscl = rdtsc();
8771         if (vmx->hv_deadline_tsc > tscl)
8772                 /* sure to be 32 bit only because checked on set_hv_timer */
8773                 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
8774                         cpu_preemption_timer_multi);
8775         else
8776                 delta_tsc = 0;
8777
8778         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
8779 }
8780
8781 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8782 {
8783         struct vcpu_vmx *vmx = to_vmx(vcpu);
8784         unsigned long debugctlmsr, cr4;
8785
8786         /* Record the guest's net vcpu time for enforced NMI injections. */
8787         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8788                 vmx->entry_time = ktime_get();
8789
8790         /* Don't enter VMX if guest state is invalid, let the exit handler
8791            start emulation until we arrive back to a valid state */
8792         if (vmx->emulation_required)
8793                 return;
8794
8795         if (vmx->ple_window_dirty) {
8796                 vmx->ple_window_dirty = false;
8797                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8798         }
8799
8800         if (vmx->nested.sync_shadow_vmcs) {
8801                 copy_vmcs12_to_shadow(vmx);
8802                 vmx->nested.sync_shadow_vmcs = false;
8803         }
8804
8805         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8806                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8807         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8808                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8809
8810         cr4 = cr4_read_shadow();
8811         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8812                 vmcs_writel(HOST_CR4, cr4);
8813                 vmx->host_state.vmcs_host_cr4 = cr4;
8814         }
8815
8816         /* When single-stepping over STI and MOV SS, we must clear the
8817          * corresponding interruptibility bits in the guest state. Otherwise
8818          * vmentry fails as it then expects bit 14 (BS) in pending debug
8819          * exceptions being set, but that's not correct for the guest debugging
8820          * case. */
8821         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8822                 vmx_set_interrupt_shadow(vcpu, 0);
8823
8824         if (vmx->guest_pkru_valid)
8825                 __write_pkru(vmx->guest_pkru);
8826
8827         atomic_switch_perf_msrs(vmx);
8828         debugctlmsr = get_debugctlmsr();
8829
8830         vmx_arm_hv_timer(vcpu);
8831
8832         vmx->__launched = vmx->loaded_vmcs->launched;
8833         asm(
8834                 /* Store host registers */
8835                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8836                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8837                 "push %%" _ASM_CX " \n\t"
8838                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8839                 "je 1f \n\t"
8840                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8841                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8842                 "1: \n\t"
8843                 /* Reload cr2 if changed */
8844                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8845                 "mov %%cr2, %%" _ASM_DX " \n\t"
8846                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8847                 "je 2f \n\t"
8848                 "mov %%" _ASM_AX", %%cr2 \n\t"
8849                 "2: \n\t"
8850                 /* Check if vmlaunch of vmresume is needed */
8851                 "cmpl $0, %c[launched](%0) \n\t"
8852                 /* Load guest registers.  Don't clobber flags. */
8853                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8854                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8855                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8856                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8857                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8858                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8859 #ifdef CONFIG_X86_64
8860                 "mov %c[r8](%0),  %%r8  \n\t"
8861                 "mov %c[r9](%0),  %%r9  \n\t"
8862                 "mov %c[r10](%0), %%r10 \n\t"
8863                 "mov %c[r11](%0), %%r11 \n\t"
8864                 "mov %c[r12](%0), %%r12 \n\t"
8865                 "mov %c[r13](%0), %%r13 \n\t"
8866                 "mov %c[r14](%0), %%r14 \n\t"
8867                 "mov %c[r15](%0), %%r15 \n\t"
8868 #endif
8869                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8870
8871                 /* Enter guest mode */
8872                 "jne 1f \n\t"
8873                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8874                 "jmp 2f \n\t"
8875                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8876                 "2: "
8877                 /* Save guest registers, load host registers, keep flags */
8878                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8879                 "pop %0 \n\t"
8880                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8881                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8882                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8883                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8884                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8885                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8886                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8887 #ifdef CONFIG_X86_64
8888                 "mov %%r8,  %c[r8](%0) \n\t"
8889                 "mov %%r9,  %c[r9](%0) \n\t"
8890                 "mov %%r10, %c[r10](%0) \n\t"
8891                 "mov %%r11, %c[r11](%0) \n\t"
8892                 "mov %%r12, %c[r12](%0) \n\t"
8893                 "mov %%r13, %c[r13](%0) \n\t"
8894                 "mov %%r14, %c[r14](%0) \n\t"
8895                 "mov %%r15, %c[r15](%0) \n\t"
8896 #endif
8897                 "mov %%cr2, %%" _ASM_AX "   \n\t"
8898                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8899
8900                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
8901                 "setbe %c[fail](%0) \n\t"
8902                 ".pushsection .rodata \n\t"
8903                 ".global vmx_return \n\t"
8904                 "vmx_return: " _ASM_PTR " 2b \n\t"
8905                 ".popsection"
8906               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8907                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8908                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8909                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8910                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8911                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8912                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8913                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8914                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8915                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8916                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8917 #ifdef CONFIG_X86_64
8918                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8919                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8920                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8921                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8922                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8923                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8924                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8925                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8926 #endif
8927                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8928                 [wordsize]"i"(sizeof(ulong))
8929               : "cc", "memory"
8930 #ifdef CONFIG_X86_64
8931                 , "rax", "rbx", "rdi", "rsi"
8932                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8933 #else
8934                 , "eax", "ebx", "edi", "esi"
8935 #endif
8936               );
8937
8938         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8939         if (debugctlmsr)
8940                 update_debugctlmsr(debugctlmsr);
8941
8942 #ifndef CONFIG_X86_64
8943         /*
8944          * The sysexit path does not restore ds/es, so we must set them to
8945          * a reasonable value ourselves.
8946          *
8947          * We can't defer this to vmx_load_host_state() since that function
8948          * may be executed in interrupt context, which saves and restore segments
8949          * around it, nullifying its effect.
8950          */
8951         loadsegment(ds, __USER_DS);
8952         loadsegment(es, __USER_DS);
8953 #endif
8954
8955         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8956                                   | (1 << VCPU_EXREG_RFLAGS)
8957                                   | (1 << VCPU_EXREG_PDPTR)
8958                                   | (1 << VCPU_EXREG_SEGMENTS)
8959                                   | (1 << VCPU_EXREG_CR3));
8960         vcpu->arch.regs_dirty = 0;
8961
8962         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8963
8964         vmx->loaded_vmcs->launched = 1;
8965
8966         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8967
8968         /*
8969          * eager fpu is enabled if PKEY is supported and CR4 is switched
8970          * back on host, so it is safe to read guest PKRU from current
8971          * XSAVE.
8972          */
8973         if (boot_cpu_has(X86_FEATURE_OSPKE)) {
8974                 vmx->guest_pkru = __read_pkru();
8975                 if (vmx->guest_pkru != vmx->host_pkru) {
8976                         vmx->guest_pkru_valid = true;
8977                         __write_pkru(vmx->host_pkru);
8978                 } else
8979                         vmx->guest_pkru_valid = false;
8980         }
8981
8982         /*
8983          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8984          * we did not inject a still-pending event to L1 now because of
8985          * nested_run_pending, we need to re-enable this bit.
8986          */
8987         if (vmx->nested.nested_run_pending)
8988                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8989
8990         vmx->nested.nested_run_pending = 0;
8991
8992         vmx_complete_atomic_exit(vmx);
8993         vmx_recover_nmi_blocking(vmx);
8994         vmx_complete_interrupts(vmx);
8995 }
8996
8997 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8998 {
8999         struct vcpu_vmx *vmx = to_vmx(vcpu);
9000         int cpu;
9001
9002         if (vmx->loaded_vmcs == &vmx->vmcs01)
9003                 return;
9004
9005         cpu = get_cpu();
9006         vmx->loaded_vmcs = &vmx->vmcs01;
9007         vmx_vcpu_put(vcpu);
9008         vmx_vcpu_load(vcpu, cpu);
9009         vcpu->cpu = cpu;
9010         put_cpu();
9011 }
9012
9013 /*
9014  * Ensure that the current vmcs of the logical processor is the
9015  * vmcs01 of the vcpu before calling free_nested().
9016  */
9017 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9018 {
9019        struct vcpu_vmx *vmx = to_vmx(vcpu);
9020        int r;
9021
9022        r = vcpu_load(vcpu);
9023        BUG_ON(r);
9024        vmx_load_vmcs01(vcpu);
9025        free_nested(vmx);
9026        vcpu_put(vcpu);
9027 }
9028
9029 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9030 {
9031         struct vcpu_vmx *vmx = to_vmx(vcpu);
9032
9033         if (enable_pml)
9034                 vmx_destroy_pml_buffer(vmx);
9035         free_vpid(vmx->vpid);
9036         leave_guest_mode(vcpu);
9037         vmx_free_vcpu_nested(vcpu);
9038         free_loaded_vmcs(vmx->loaded_vmcs);
9039         kfree(vmx->guest_msrs);
9040         kvm_vcpu_uninit(vcpu);
9041         kmem_cache_free(kvm_vcpu_cache, vmx);
9042 }
9043
9044 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9045 {
9046         int err;
9047         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9048         int cpu;
9049
9050         if (!vmx)
9051                 return ERR_PTR(-ENOMEM);
9052
9053         vmx->vpid = allocate_vpid();
9054
9055         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9056         if (err)
9057                 goto free_vcpu;
9058
9059         err = -ENOMEM;
9060
9061         /*
9062          * If PML is turned on, failure on enabling PML just results in failure
9063          * of creating the vcpu, therefore we can simplify PML logic (by
9064          * avoiding dealing with cases, such as enabling PML partially on vcpus
9065          * for the guest, etc.
9066          */
9067         if (enable_pml) {
9068                 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9069                 if (!vmx->pml_pg)
9070                         goto uninit_vcpu;
9071         }
9072
9073         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
9074         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9075                      > PAGE_SIZE);
9076
9077         if (!vmx->guest_msrs)
9078                 goto free_pml;
9079
9080         vmx->loaded_vmcs = &vmx->vmcs01;
9081         vmx->loaded_vmcs->vmcs = alloc_vmcs();
9082         if (!vmx->loaded_vmcs->vmcs)
9083                 goto free_msrs;
9084         if (!vmm_exclusive)
9085                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
9086         loaded_vmcs_init(vmx->loaded_vmcs);
9087         if (!vmm_exclusive)
9088                 kvm_cpu_vmxoff();
9089
9090         cpu = get_cpu();
9091         vmx_vcpu_load(&vmx->vcpu, cpu);
9092         vmx->vcpu.cpu = cpu;
9093         err = vmx_vcpu_setup(vmx);
9094         vmx_vcpu_put(&vmx->vcpu);
9095         put_cpu();
9096         if (err)
9097                 goto free_vmcs;
9098         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9099                 err = alloc_apic_access_page(kvm);
9100                 if (err)
9101                         goto free_vmcs;
9102         }
9103
9104         if (enable_ept) {
9105                 if (!kvm->arch.ept_identity_map_addr)
9106                         kvm->arch.ept_identity_map_addr =
9107                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
9108                 err = init_rmode_identity_map(kvm);
9109                 if (err)
9110                         goto free_vmcs;
9111         }
9112
9113         if (nested) {
9114                 nested_vmx_setup_ctls_msrs(vmx);
9115                 vmx->nested.vpid02 = allocate_vpid();
9116         }
9117
9118         vmx->nested.posted_intr_nv = -1;
9119         vmx->nested.current_vmptr = -1ull;
9120         vmx->nested.current_vmcs12 = NULL;
9121
9122         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9123
9124         return &vmx->vcpu;
9125
9126 free_vmcs:
9127         free_vpid(vmx->nested.vpid02);
9128         free_loaded_vmcs(vmx->loaded_vmcs);
9129 free_msrs:
9130         kfree(vmx->guest_msrs);
9131 free_pml:
9132         vmx_destroy_pml_buffer(vmx);
9133 uninit_vcpu:
9134         kvm_vcpu_uninit(&vmx->vcpu);
9135 free_vcpu:
9136         free_vpid(vmx->vpid);
9137         kmem_cache_free(kvm_vcpu_cache, vmx);
9138         return ERR_PTR(err);
9139 }
9140
9141 static void __init vmx_check_processor_compat(void *rtn)
9142 {
9143         struct vmcs_config vmcs_conf;
9144
9145         *(int *)rtn = 0;
9146         if (setup_vmcs_config(&vmcs_conf) < 0)
9147                 *(int *)rtn = -EIO;
9148         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9149                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9150                                 smp_processor_id());
9151                 *(int *)rtn = -EIO;
9152         }
9153 }
9154
9155 static int get_ept_level(void)
9156 {
9157         return VMX_EPT_DEFAULT_GAW + 1;
9158 }
9159
9160 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
9161 {
9162         u8 cache;
9163         u64 ipat = 0;
9164
9165         /* For VT-d and EPT combination
9166          * 1. MMIO: always map as UC
9167          * 2. EPT with VT-d:
9168          *   a. VT-d without snooping control feature: can't guarantee the
9169          *      result, try to trust guest.
9170          *   b. VT-d with snooping control feature: snooping control feature of
9171          *      VT-d engine can guarantee the cache correctness. Just set it
9172          *      to WB to keep consistent with host. So the same as item 3.
9173          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9174          *    consistent with host MTRR
9175          */
9176         if (is_mmio) {
9177                 cache = MTRR_TYPE_UNCACHABLE;
9178                 goto exit;
9179         }
9180
9181         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9182                 ipat = VMX_EPT_IPAT_BIT;
9183                 cache = MTRR_TYPE_WRBACK;
9184                 goto exit;
9185         }
9186
9187         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9188                 ipat = VMX_EPT_IPAT_BIT;
9189                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9190                         cache = MTRR_TYPE_WRBACK;
9191                 else
9192                         cache = MTRR_TYPE_UNCACHABLE;
9193                 goto exit;
9194         }
9195
9196         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9197
9198 exit:
9199         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9200 }
9201
9202 static int vmx_get_lpage_level(void)
9203 {
9204         if (enable_ept && !cpu_has_vmx_ept_1g_page())
9205                 return PT_DIRECTORY_LEVEL;
9206         else
9207                 /* For shadow and EPT supported 1GB page */
9208                 return PT_PDPE_LEVEL;
9209 }
9210
9211 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9212 {
9213         /*
9214          * These bits in the secondary execution controls field
9215          * are dynamic, the others are mostly based on the hypervisor
9216          * architecture and the guest's CPUID.  Do not touch the
9217          * dynamic bits.
9218          */
9219         u32 mask =
9220                 SECONDARY_EXEC_SHADOW_VMCS |
9221                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9222                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9223
9224         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9225
9226         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9227                      (new_ctl & ~mask) | (cur_ctl & mask));
9228 }
9229
9230 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9231 {
9232         struct kvm_cpuid_entry2 *best;
9233         struct vcpu_vmx *vmx = to_vmx(vcpu);
9234         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
9235
9236         if (vmx_rdtscp_supported()) {
9237                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9238                 if (!rdtscp_enabled)
9239                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
9240
9241                 if (nested) {
9242                         if (rdtscp_enabled)
9243                                 vmx->nested.nested_vmx_secondary_ctls_high |=
9244                                         SECONDARY_EXEC_RDTSCP;
9245                         else
9246                                 vmx->nested.nested_vmx_secondary_ctls_high &=
9247                                         ~SECONDARY_EXEC_RDTSCP;
9248                 }
9249         }
9250
9251         /* Exposing INVPCID only when PCID is exposed */
9252         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9253         if (vmx_invpcid_supported() &&
9254             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9255             !guest_cpuid_has_pcid(vcpu))) {
9256                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
9257
9258                 if (best)
9259                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
9260         }
9261
9262         if (cpu_has_secondary_exec_ctrls())
9263                 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9264
9265         if (nested_vmx_allowed(vcpu))
9266                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9267                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9268         else
9269                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9270                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9271 }
9272
9273 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9274 {
9275         if (func == 1 && nested)
9276                 entry->ecx |= bit(X86_FEATURE_VMX);
9277 }
9278
9279 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9280                 struct x86_exception *fault)
9281 {
9282         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9283         u32 exit_reason;
9284
9285         if (fault->error_code & PFERR_RSVD_MASK)
9286                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9287         else
9288                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9289         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
9290         vmcs12->guest_physical_address = fault->address;
9291 }
9292
9293 /* Callbacks for nested_ept_init_mmu_context: */
9294
9295 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9296 {
9297         /* return the page table to be shadowed - in our case, EPT12 */
9298         return get_vmcs12(vcpu)->ept_pointer;
9299 }
9300
9301 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9302 {
9303         WARN_ON(mmu_is_nested(vcpu));
9304         kvm_init_shadow_ept_mmu(vcpu,
9305                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9306                         VMX_EPT_EXECUTE_ONLY_BIT);
9307         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9308         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9309         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9310
9311         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9312 }
9313
9314 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9315 {
9316         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9317 }
9318
9319 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9320                                             u16 error_code)
9321 {
9322         bool inequality, bit;
9323
9324         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9325         inequality =
9326                 (error_code & vmcs12->page_fault_error_code_mask) !=
9327                  vmcs12->page_fault_error_code_match;
9328         return inequality ^ bit;
9329 }
9330
9331 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9332                 struct x86_exception *fault)
9333 {
9334         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9335
9336         WARN_ON(!is_guest_mode(vcpu));
9337
9338         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9339                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9340                                   vmcs_read32(VM_EXIT_INTR_INFO),
9341                                   vmcs_readl(EXIT_QUALIFICATION));
9342         else
9343                 kvm_inject_page_fault(vcpu, fault);
9344 }
9345
9346 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9347                                         struct vmcs12 *vmcs12)
9348 {
9349         struct vcpu_vmx *vmx = to_vmx(vcpu);
9350         int maxphyaddr = cpuid_maxphyaddr(vcpu);
9351
9352         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9353                 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
9354                     vmcs12->apic_access_addr >> maxphyaddr)
9355                         return false;
9356
9357                 /*
9358                  * Translate L1 physical address to host physical
9359                  * address for vmcs02. Keep the page pinned, so this
9360                  * physical address remains valid. We keep a reference
9361                  * to it so we can release it later.
9362                  */
9363                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9364                         nested_release_page(vmx->nested.apic_access_page);
9365                 vmx->nested.apic_access_page =
9366                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9367         }
9368
9369         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9370                 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
9371                     vmcs12->virtual_apic_page_addr >> maxphyaddr)
9372                         return false;
9373
9374                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9375                         nested_release_page(vmx->nested.virtual_apic_page);
9376                 vmx->nested.virtual_apic_page =
9377                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9378
9379                 /*
9380                  * Failing the vm entry is _not_ what the processor does
9381                  * but it's basically the only possibility we have.
9382                  * We could still enter the guest if CR8 load exits are
9383                  * enabled, CR8 store exits are enabled, and virtualize APIC
9384                  * access is disabled; in this case the processor would never
9385                  * use the TPR shadow and we could simply clear the bit from
9386                  * the execution control.  But such a configuration is useless,
9387                  * so let's keep the code simple.
9388                  */
9389                 if (!vmx->nested.virtual_apic_page)
9390                         return false;
9391         }
9392
9393         if (nested_cpu_has_posted_intr(vmcs12)) {
9394                 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
9395                     vmcs12->posted_intr_desc_addr >> maxphyaddr)
9396                         return false;
9397
9398                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9399                         kunmap(vmx->nested.pi_desc_page);
9400                         nested_release_page(vmx->nested.pi_desc_page);
9401                 }
9402                 vmx->nested.pi_desc_page =
9403                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9404                 if (!vmx->nested.pi_desc_page)
9405                         return false;
9406
9407                 vmx->nested.pi_desc =
9408                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9409                 if (!vmx->nested.pi_desc) {
9410                         nested_release_page_clean(vmx->nested.pi_desc_page);
9411                         return false;
9412                 }
9413                 vmx->nested.pi_desc =
9414                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9415                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9416                         (PAGE_SIZE - 1)));
9417         }
9418
9419         return true;
9420 }
9421
9422 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9423 {
9424         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9425         struct vcpu_vmx *vmx = to_vmx(vcpu);
9426
9427         if (vcpu->arch.virtual_tsc_khz == 0)
9428                 return;
9429
9430         /* Make sure short timeouts reliably trigger an immediate vmexit.
9431          * hrtimer_start does not guarantee this. */
9432         if (preemption_timeout <= 1) {
9433                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9434                 return;
9435         }
9436
9437         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9438         preemption_timeout *= 1000000;
9439         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9440         hrtimer_start(&vmx->nested.preemption_timer,
9441                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9442 }
9443
9444 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9445                                                 struct vmcs12 *vmcs12)
9446 {
9447         int maxphyaddr;
9448         u64 addr;
9449
9450         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9451                 return 0;
9452
9453         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9454                 WARN_ON(1);
9455                 return -EINVAL;
9456         }
9457         maxphyaddr = cpuid_maxphyaddr(vcpu);
9458
9459         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9460            ((addr + PAGE_SIZE) >> maxphyaddr))
9461                 return -EINVAL;
9462
9463         return 0;
9464 }
9465
9466 /*
9467  * Merge L0's and L1's MSR bitmap, return false to indicate that
9468  * we do not use the hardware.
9469  */
9470 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9471                                                struct vmcs12 *vmcs12)
9472 {
9473         int msr;
9474         struct page *page;
9475         unsigned long *msr_bitmap;
9476
9477         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9478                 return false;
9479
9480         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9481         if (!page) {
9482                 WARN_ON(1);
9483                 return false;
9484         }
9485         msr_bitmap = (unsigned long *)kmap(page);
9486         if (!msr_bitmap) {
9487                 nested_release_page_clean(page);
9488                 WARN_ON(1);
9489                 return false;
9490         }
9491
9492         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9493                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9494                         for (msr = 0x800; msr <= 0x8ff; msr++)
9495                                 nested_vmx_disable_intercept_for_msr(
9496                                         msr_bitmap,
9497                                         vmx_msr_bitmap_nested,
9498                                         msr, MSR_TYPE_R);
9499                 /* TPR is allowed */
9500                 nested_vmx_disable_intercept_for_msr(msr_bitmap,
9501                                 vmx_msr_bitmap_nested,
9502                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9503                                 MSR_TYPE_R | MSR_TYPE_W);
9504                 if (nested_cpu_has_vid(vmcs12)) {
9505                         /* EOI and self-IPI are allowed */
9506                         nested_vmx_disable_intercept_for_msr(
9507                                 msr_bitmap,
9508                                 vmx_msr_bitmap_nested,
9509                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9510                                 MSR_TYPE_W);
9511                         nested_vmx_disable_intercept_for_msr(
9512                                 msr_bitmap,
9513                                 vmx_msr_bitmap_nested,
9514                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9515                                 MSR_TYPE_W);
9516                 }
9517         } else {
9518                 /*
9519                  * Enable reading intercept of all the x2apic
9520                  * MSRs. We should not rely on vmcs12 to do any
9521                  * optimizations here, it may have been modified
9522                  * by L1.
9523                  */
9524                 for (msr = 0x800; msr <= 0x8ff; msr++)
9525                         __vmx_enable_intercept_for_msr(
9526                                 vmx_msr_bitmap_nested,
9527                                 msr,
9528                                 MSR_TYPE_R);
9529
9530                 __vmx_enable_intercept_for_msr(
9531                                 vmx_msr_bitmap_nested,
9532                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9533                                 MSR_TYPE_W);
9534                 __vmx_enable_intercept_for_msr(
9535                                 vmx_msr_bitmap_nested,
9536                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9537                                 MSR_TYPE_W);
9538                 __vmx_enable_intercept_for_msr(
9539                                 vmx_msr_bitmap_nested,
9540                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9541                                 MSR_TYPE_W);
9542         }
9543         kunmap(page);
9544         nested_release_page_clean(page);
9545
9546         return true;
9547 }
9548
9549 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9550                                            struct vmcs12 *vmcs12)
9551 {
9552         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9553             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9554             !nested_cpu_has_vid(vmcs12) &&
9555             !nested_cpu_has_posted_intr(vmcs12))
9556                 return 0;
9557
9558         /*
9559          * If virtualize x2apic mode is enabled,
9560          * virtualize apic access must be disabled.
9561          */
9562         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9563             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9564                 return -EINVAL;
9565
9566         /*
9567          * If virtual interrupt delivery is enabled,
9568          * we must exit on external interrupts.
9569          */
9570         if (nested_cpu_has_vid(vmcs12) &&
9571            !nested_exit_on_intr(vcpu))
9572                 return -EINVAL;
9573
9574         /*
9575          * bits 15:8 should be zero in posted_intr_nv,
9576          * the descriptor address has been already checked
9577          * in nested_get_vmcs12_pages.
9578          */
9579         if (nested_cpu_has_posted_intr(vmcs12) &&
9580            (!nested_cpu_has_vid(vmcs12) ||
9581             !nested_exit_intr_ack_set(vcpu) ||
9582             vmcs12->posted_intr_nv & 0xff00))
9583                 return -EINVAL;
9584
9585         /* tpr shadow is needed by all apicv features. */
9586         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9587                 return -EINVAL;
9588
9589         return 0;
9590 }
9591
9592 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9593                                        unsigned long count_field,
9594                                        unsigned long addr_field)
9595 {
9596         int maxphyaddr;
9597         u64 count, addr;
9598
9599         if (vmcs12_read_any(vcpu, count_field, &count) ||
9600             vmcs12_read_any(vcpu, addr_field, &addr)) {
9601                 WARN_ON(1);
9602                 return -EINVAL;
9603         }
9604         if (count == 0)
9605                 return 0;
9606         maxphyaddr = cpuid_maxphyaddr(vcpu);
9607         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9608             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9609                 pr_warn_ratelimited(
9610                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9611                         addr_field, maxphyaddr, count, addr);
9612                 return -EINVAL;
9613         }
9614         return 0;
9615 }
9616
9617 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9618                                                 struct vmcs12 *vmcs12)
9619 {
9620         if (vmcs12->vm_exit_msr_load_count == 0 &&
9621             vmcs12->vm_exit_msr_store_count == 0 &&
9622             vmcs12->vm_entry_msr_load_count == 0)
9623                 return 0; /* Fast path */
9624         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9625                                         VM_EXIT_MSR_LOAD_ADDR) ||
9626             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9627                                         VM_EXIT_MSR_STORE_ADDR) ||
9628             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9629                                         VM_ENTRY_MSR_LOAD_ADDR))
9630                 return -EINVAL;
9631         return 0;
9632 }
9633
9634 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9635                                        struct vmx_msr_entry *e)
9636 {
9637         /* x2APIC MSR accesses are not allowed */
9638         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9639                 return -EINVAL;
9640         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9641             e->index == MSR_IA32_UCODE_REV)
9642                 return -EINVAL;
9643         if (e->reserved != 0)
9644                 return -EINVAL;
9645         return 0;
9646 }
9647
9648 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9649                                      struct vmx_msr_entry *e)
9650 {
9651         if (e->index == MSR_FS_BASE ||
9652             e->index == MSR_GS_BASE ||
9653             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9654             nested_vmx_msr_check_common(vcpu, e))
9655                 return -EINVAL;
9656         return 0;
9657 }
9658
9659 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9660                                       struct vmx_msr_entry *e)
9661 {
9662         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9663             nested_vmx_msr_check_common(vcpu, e))
9664                 return -EINVAL;
9665         return 0;
9666 }
9667
9668 /*
9669  * Load guest's/host's msr at nested entry/exit.
9670  * return 0 for success, entry index for failure.
9671  */
9672 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9673 {
9674         u32 i;
9675         struct vmx_msr_entry e;
9676         struct msr_data msr;
9677
9678         msr.host_initiated = false;
9679         for (i = 0; i < count; i++) {
9680                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9681                                         &e, sizeof(e))) {
9682                         pr_warn_ratelimited(
9683                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9684                                 __func__, i, gpa + i * sizeof(e));
9685                         goto fail;
9686                 }
9687                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9688                         pr_warn_ratelimited(
9689                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9690                                 __func__, i, e.index, e.reserved);
9691                         goto fail;
9692                 }
9693                 msr.index = e.index;
9694                 msr.data = e.value;
9695                 if (kvm_set_msr(vcpu, &msr)) {
9696                         pr_warn_ratelimited(
9697                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9698                                 __func__, i, e.index, e.value);
9699                         goto fail;
9700                 }
9701         }
9702         return 0;
9703 fail:
9704         return i + 1;
9705 }
9706
9707 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9708 {
9709         u32 i;
9710         struct vmx_msr_entry e;
9711
9712         for (i = 0; i < count; i++) {
9713                 struct msr_data msr_info;
9714                 if (kvm_vcpu_read_guest(vcpu,
9715                                         gpa + i * sizeof(e),
9716                                         &e, 2 * sizeof(u32))) {
9717                         pr_warn_ratelimited(
9718                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9719                                 __func__, i, gpa + i * sizeof(e));
9720                         return -EINVAL;
9721                 }
9722                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9723                         pr_warn_ratelimited(
9724                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9725                                 __func__, i, e.index, e.reserved);
9726                         return -EINVAL;
9727                 }
9728                 msr_info.host_initiated = false;
9729                 msr_info.index = e.index;
9730                 if (kvm_get_msr(vcpu, &msr_info)) {
9731                         pr_warn_ratelimited(
9732                                 "%s cannot read MSR (%u, 0x%x)\n",
9733                                 __func__, i, e.index);
9734                         return -EINVAL;
9735                 }
9736                 if (kvm_vcpu_write_guest(vcpu,
9737                                          gpa + i * sizeof(e) +
9738                                              offsetof(struct vmx_msr_entry, value),
9739                                          &msr_info.data, sizeof(msr_info.data))) {
9740                         pr_warn_ratelimited(
9741                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9742                                 __func__, i, e.index, msr_info.data);
9743                         return -EINVAL;
9744                 }
9745         }
9746         return 0;
9747 }
9748
9749 /*
9750  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9751  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9752  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9753  * guest in a way that will both be appropriate to L1's requests, and our
9754  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9755  * function also has additional necessary side-effects, like setting various
9756  * vcpu->arch fields.
9757  */
9758 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9759 {
9760         struct vcpu_vmx *vmx = to_vmx(vcpu);
9761         u32 exec_control;
9762
9763         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9764         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9765         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9766         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9767         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9768         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9769         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9770         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9771         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9772         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9773         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9774         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9775         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9776         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9777         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9778         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9779         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9780         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9781         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9782         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9783         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9784         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9785         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9786         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9787         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9788         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9789         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9790         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9791         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9792         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9793         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9794         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9795         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9796         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9797         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9798         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9799
9800         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9801                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9802                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9803         } else {
9804                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9805                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9806         }
9807         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9808                 vmcs12->vm_entry_intr_info_field);
9809         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9810                 vmcs12->vm_entry_exception_error_code);
9811         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9812                 vmcs12->vm_entry_instruction_len);
9813         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9814                 vmcs12->guest_interruptibility_info);
9815         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9816         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9817         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9818                 vmcs12->guest_pending_dbg_exceptions);
9819         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9820         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9821
9822         if (nested_cpu_has_xsaves(vmcs12))
9823                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9824         vmcs_write64(VMCS_LINK_POINTER, -1ull);
9825
9826         exec_control = vmcs12->pin_based_vm_exec_control;
9827
9828         /* Preemption timer setting is only taken from vmcs01.  */
9829         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9830         exec_control |= vmcs_config.pin_based_exec_ctrl;
9831         if (vmx->hv_deadline_tsc == -1)
9832                 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9833
9834         /* Posted interrupts setting is only taken from vmcs12.  */
9835         if (nested_cpu_has_posted_intr(vmcs12)) {
9836                 /*
9837                  * Note that we use L0's vector here and in
9838                  * vmx_deliver_nested_posted_interrupt.
9839                  */
9840                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9841                 vmx->nested.pi_pending = false;
9842                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9843                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9844                         page_to_phys(vmx->nested.pi_desc_page) +
9845                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9846                         (PAGE_SIZE - 1)));
9847         } else
9848                 exec_control &= ~PIN_BASED_POSTED_INTR;
9849
9850         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9851
9852         vmx->nested.preemption_timer_expired = false;
9853         if (nested_cpu_has_preemption_timer(vmcs12))
9854                 vmx_start_preemption_timer(vcpu);
9855
9856         /*
9857          * Whether page-faults are trapped is determined by a combination of
9858          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9859          * If enable_ept, L0 doesn't care about page faults and we should
9860          * set all of these to L1's desires. However, if !enable_ept, L0 does
9861          * care about (at least some) page faults, and because it is not easy
9862          * (if at all possible?) to merge L0 and L1's desires, we simply ask
9863          * to exit on each and every L2 page fault. This is done by setting
9864          * MASK=MATCH=0 and (see below) EB.PF=1.
9865          * Note that below we don't need special code to set EB.PF beyond the
9866          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9867          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9868          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9869          *
9870          * A problem with this approach (when !enable_ept) is that L1 may be
9871          * injected with more page faults than it asked for. This could have
9872          * caused problems, but in practice existing hypervisors don't care.
9873          * To fix this, we will need to emulate the PFEC checking (on the L1
9874          * page tables), using walk_addr(), when injecting PFs to L1.
9875          */
9876         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9877                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9878         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9879                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9880
9881         if (cpu_has_secondary_exec_ctrls()) {
9882                 exec_control = vmx_secondary_exec_control(vmx);
9883
9884                 /* Take the following fields only from vmcs12 */
9885                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9886                                   SECONDARY_EXEC_RDTSCP |
9887                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9888                                   SECONDARY_EXEC_APIC_REGISTER_VIRT);
9889                 if (nested_cpu_has(vmcs12,
9890                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9891                         exec_control |= vmcs12->secondary_vm_exec_control;
9892
9893                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9894                         /*
9895                          * If translation failed, no matter: This feature asks
9896                          * to exit when accessing the given address, and if it
9897                          * can never be accessed, this feature won't do
9898                          * anything anyway.
9899                          */
9900                         if (!vmx->nested.apic_access_page)
9901                                 exec_control &=
9902                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9903                         else
9904                                 vmcs_write64(APIC_ACCESS_ADDR,
9905                                   page_to_phys(vmx->nested.apic_access_page));
9906                 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9907                             cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9908                         exec_control |=
9909                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9910                         kvm_vcpu_reload_apic_access_page(vcpu);
9911                 }
9912
9913                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9914                         vmcs_write64(EOI_EXIT_BITMAP0,
9915                                 vmcs12->eoi_exit_bitmap0);
9916                         vmcs_write64(EOI_EXIT_BITMAP1,
9917                                 vmcs12->eoi_exit_bitmap1);
9918                         vmcs_write64(EOI_EXIT_BITMAP2,
9919                                 vmcs12->eoi_exit_bitmap2);
9920                         vmcs_write64(EOI_EXIT_BITMAP3,
9921                                 vmcs12->eoi_exit_bitmap3);
9922                         vmcs_write16(GUEST_INTR_STATUS,
9923                                 vmcs12->guest_intr_status);
9924                 }
9925
9926                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9927         }
9928
9929
9930         /*
9931          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9932          * Some constant fields are set here by vmx_set_constant_host_state().
9933          * Other fields are different per CPU, and will be set later when
9934          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9935          */
9936         vmx_set_constant_host_state(vmx);
9937
9938         /*
9939          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9940          * entry, but only if the current (host) sp changed from the value
9941          * we wrote last (vmx->host_rsp). This cache is no longer relevant
9942          * if we switch vmcs, and rather than hold a separate cache per vmcs,
9943          * here we just force the write to happen on entry.
9944          */
9945         vmx->host_rsp = 0;
9946
9947         exec_control = vmx_exec_control(vmx); /* L0's desires */
9948         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9949         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9950         exec_control &= ~CPU_BASED_TPR_SHADOW;
9951         exec_control |= vmcs12->cpu_based_vm_exec_control;
9952
9953         if (exec_control & CPU_BASED_TPR_SHADOW) {
9954                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9955                                 page_to_phys(vmx->nested.virtual_apic_page));
9956                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9957         }
9958
9959         if (cpu_has_vmx_msr_bitmap() &&
9960             exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9961                 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9962                 /* MSR_BITMAP will be set by following vmx_set_efer. */
9963         } else
9964                 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9965
9966         /*
9967          * Merging of IO bitmap not currently supported.
9968          * Rather, exit every time.
9969          */
9970         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9971         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9972
9973         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9974
9975         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9976          * bitwise-or of what L1 wants to trap for L2, and what we want to
9977          * trap. Note that CR0.TS also needs updating - we do this later.
9978          */
9979         update_exception_bitmap(vcpu);
9980         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9981         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9982
9983         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9984          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9985          * bits are further modified by vmx_set_efer() below.
9986          */
9987         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9988
9989         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9990          * emulated by vmx_set_efer(), below.
9991          */
9992         vm_entry_controls_init(vmx,
9993                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9994                         ~VM_ENTRY_IA32E_MODE) |
9995                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9996
9997         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9998                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9999                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
10000         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
10001                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
10002
10003
10004         set_cr4_guest_host_mask(vmx);
10005
10006         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
10007                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10008
10009         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10010                 vmcs_write64(TSC_OFFSET,
10011                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
10012         else
10013                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10014
10015         if (enable_vpid) {
10016                 /*
10017                  * There is no direct mapping between vpid02 and vpid12, the
10018                  * vpid02 is per-vCPU for L0 and reused while the value of
10019                  * vpid12 is changed w/ one invvpid during nested vmentry.
10020                  * The vpid12 is allocated by L1 for L2, so it will not
10021                  * influence global bitmap(for vpid01 and vpid02 allocation)
10022                  * even if spawn a lot of nested vCPUs.
10023                  */
10024                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10025                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10026                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10027                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10028                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10029                         }
10030                 } else {
10031                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10032                         vmx_flush_tlb(vcpu);
10033                 }
10034
10035         }
10036
10037         if (nested_cpu_has_ept(vmcs12)) {
10038                 kvm_mmu_unload(vcpu);
10039                 nested_ept_init_mmu_context(vcpu);
10040         }
10041
10042         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
10043                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10044         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10045                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10046         else
10047                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10048         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10049         vmx_set_efer(vcpu, vcpu->arch.efer);
10050
10051         /*
10052          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
10053          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
10054          * The CR0_READ_SHADOW is what L2 should have expected to read given
10055          * the specifications by L1; It's not enough to take
10056          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10057          * have more bits than L1 expected.
10058          */
10059         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10060         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10061
10062         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10063         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10064
10065         /* shadow page tables on either EPT or shadow page tables */
10066         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
10067         kvm_mmu_reset_context(vcpu);
10068
10069         if (!enable_ept)
10070                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10071
10072         /*
10073          * L1 may access the L2's PDPTR, so save them to construct vmcs12
10074          */
10075         if (enable_ept) {
10076                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10077                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10078                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10079                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10080         }
10081
10082         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10083         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10084 }
10085
10086 /*
10087  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10088  * for running an L2 nested guest.
10089  */
10090 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10091 {
10092         struct vmcs12 *vmcs12;
10093         struct vcpu_vmx *vmx = to_vmx(vcpu);
10094         int cpu;
10095         struct loaded_vmcs *vmcs02;
10096         bool ia32e;
10097         u32 msr_entry_idx;
10098
10099         if (!nested_vmx_check_permission(vcpu) ||
10100             !nested_vmx_check_vmcs12(vcpu))
10101                 return 1;
10102
10103         skip_emulated_instruction(vcpu);
10104         vmcs12 = get_vmcs12(vcpu);
10105
10106         if (enable_shadow_vmcs)
10107                 copy_shadow_to_vmcs12(vmx);
10108
10109         /*
10110          * The nested entry process starts with enforcing various prerequisites
10111          * on vmcs12 as required by the Intel SDM, and act appropriately when
10112          * they fail: As the SDM explains, some conditions should cause the
10113          * instruction to fail, while others will cause the instruction to seem
10114          * to succeed, but return an EXIT_REASON_INVALID_STATE.
10115          * To speed up the normal (success) code path, we should avoid checking
10116          * for misconfigurations which will anyway be caught by the processor
10117          * when using the merged vmcs02.
10118          */
10119         if (vmcs12->launch_state == launch) {
10120                 nested_vmx_failValid(vcpu,
10121                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10122                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10123                 return 1;
10124         }
10125
10126         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10127             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
10128                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10129                 return 1;
10130         }
10131
10132         if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
10133                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10134                 return 1;
10135         }
10136
10137         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
10138                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10139                 return 1;
10140         }
10141
10142         if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
10143                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10144                 return 1;
10145         }
10146
10147         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
10148                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10149                 return 1;
10150         }
10151
10152         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
10153                                 vmx->nested.nested_vmx_true_procbased_ctls_low,
10154                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
10155             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10156                                 vmx->nested.nested_vmx_secondary_ctls_low,
10157                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
10158             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
10159                                 vmx->nested.nested_vmx_pinbased_ctls_low,
10160                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
10161             !vmx_control_verify(vmcs12->vm_exit_controls,
10162                                 vmx->nested.nested_vmx_true_exit_ctls_low,
10163                                 vmx->nested.nested_vmx_exit_ctls_high) ||
10164             !vmx_control_verify(vmcs12->vm_entry_controls,
10165                                 vmx->nested.nested_vmx_true_entry_ctls_low,
10166                                 vmx->nested.nested_vmx_entry_ctls_high))
10167         {
10168                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10169                 return 1;
10170         }
10171
10172         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
10173             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
10174                 nested_vmx_failValid(vcpu,
10175                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
10176                 return 1;
10177         }
10178
10179         if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
10180             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
10181                 nested_vmx_entry_failure(vcpu, vmcs12,
10182                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10183                 return 1;
10184         }
10185         if (vmcs12->vmcs_link_pointer != -1ull) {
10186                 nested_vmx_entry_failure(vcpu, vmcs12,
10187                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
10188                 return 1;
10189         }
10190
10191         /*
10192          * If the load IA32_EFER VM-entry control is 1, the following checks
10193          * are performed on the field for the IA32_EFER MSR:
10194          * - Bits reserved in the IA32_EFER MSR must be 0.
10195          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10196          *   the IA-32e mode guest VM-exit control. It must also be identical
10197          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10198          *   CR0.PG) is 1.
10199          */
10200         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
10201                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10202                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10203                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10204                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10205                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
10206                         nested_vmx_entry_failure(vcpu, vmcs12,
10207                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10208                         return 1;
10209                 }
10210         }
10211
10212         /*
10213          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10214          * IA32_EFER MSR must be 0 in the field for that register. In addition,
10215          * the values of the LMA and LME bits in the field must each be that of
10216          * the host address-space size VM-exit control.
10217          */
10218         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10219                 ia32e = (vmcs12->vm_exit_controls &
10220                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10221                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10222                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10223                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
10224                         nested_vmx_entry_failure(vcpu, vmcs12,
10225                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10226                         return 1;
10227                 }
10228         }
10229
10230         /*
10231          * We're finally done with prerequisite checking, and can start with
10232          * the nested entry.
10233          */
10234
10235         vmcs02 = nested_get_current_vmcs02(vmx);
10236         if (!vmcs02)
10237                 return -ENOMEM;
10238
10239         enter_guest_mode(vcpu);
10240
10241         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
10242
10243         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10244                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10245
10246         cpu = get_cpu();
10247         vmx->loaded_vmcs = vmcs02;
10248         vmx_vcpu_put(vcpu);
10249         vmx_vcpu_load(vcpu, cpu);
10250         vcpu->cpu = cpu;
10251         put_cpu();
10252
10253         vmx_segment_cache_clear(vmx);
10254
10255         prepare_vmcs02(vcpu, vmcs12);
10256
10257         msr_entry_idx = nested_vmx_load_msr(vcpu,
10258                                             vmcs12->vm_entry_msr_load_addr,
10259                                             vmcs12->vm_entry_msr_load_count);
10260         if (msr_entry_idx) {
10261                 leave_guest_mode(vcpu);
10262                 vmx_load_vmcs01(vcpu);
10263                 nested_vmx_entry_failure(vcpu, vmcs12,
10264                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10265                 return 1;
10266         }
10267
10268         vmcs12->launch_state = 1;
10269
10270         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10271                 return kvm_vcpu_halt(vcpu);
10272
10273         vmx->nested.nested_run_pending = 1;
10274
10275         /*
10276          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10277          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10278          * returned as far as L1 is concerned. It will only return (and set
10279          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10280          */
10281         return 1;
10282 }
10283
10284 /*
10285  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10286  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10287  * This function returns the new value we should put in vmcs12.guest_cr0.
10288  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10289  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10290  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10291  *     didn't trap the bit, because if L1 did, so would L0).
10292  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10293  *     been modified by L2, and L1 knows it. So just leave the old value of
10294  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10295  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10296  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10297  *     changed these bits, and therefore they need to be updated, but L0
10298  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10299  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10300  */
10301 static inline unsigned long
10302 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10303 {
10304         return
10305         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10306         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10307         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10308                         vcpu->arch.cr0_guest_owned_bits));
10309 }
10310
10311 static inline unsigned long
10312 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10313 {
10314         return
10315         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10316         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10317         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10318                         vcpu->arch.cr4_guest_owned_bits));
10319 }
10320
10321 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10322                                        struct vmcs12 *vmcs12)
10323 {
10324         u32 idt_vectoring;
10325         unsigned int nr;
10326
10327         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10328                 nr = vcpu->arch.exception.nr;
10329                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10330
10331                 if (kvm_exception_is_soft(nr)) {
10332                         vmcs12->vm_exit_instruction_len =
10333                                 vcpu->arch.event_exit_inst_len;
10334                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10335                 } else
10336                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10337
10338                 if (vcpu->arch.exception.has_error_code) {
10339                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10340                         vmcs12->idt_vectoring_error_code =
10341                                 vcpu->arch.exception.error_code;
10342                 }
10343
10344                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10345         } else if (vcpu->arch.nmi_injected) {
10346                 vmcs12->idt_vectoring_info_field =
10347                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10348         } else if (vcpu->arch.interrupt.pending) {
10349                 nr = vcpu->arch.interrupt.nr;
10350                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10351
10352                 if (vcpu->arch.interrupt.soft) {
10353                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10354                         vmcs12->vm_entry_instruction_len =
10355                                 vcpu->arch.event_exit_inst_len;
10356                 } else
10357                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10358
10359                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10360         }
10361 }
10362
10363 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10364 {
10365         struct vcpu_vmx *vmx = to_vmx(vcpu);
10366
10367         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10368             vmx->nested.preemption_timer_expired) {
10369                 if (vmx->nested.nested_run_pending)
10370                         return -EBUSY;
10371                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10372                 return 0;
10373         }
10374
10375         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10376                 if (vmx->nested.nested_run_pending ||
10377                     vcpu->arch.interrupt.pending)
10378                         return -EBUSY;
10379                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10380                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10381                                   INTR_INFO_VALID_MASK, 0);
10382                 /*
10383                  * The NMI-triggered VM exit counts as injection:
10384                  * clear this one and block further NMIs.
10385                  */
10386                 vcpu->arch.nmi_pending = 0;
10387                 vmx_set_nmi_mask(vcpu, true);
10388                 return 0;
10389         }
10390
10391         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10392             nested_exit_on_intr(vcpu)) {
10393                 if (vmx->nested.nested_run_pending)
10394                         return -EBUSY;
10395                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10396                 return 0;
10397         }
10398
10399         return vmx_complete_nested_posted_interrupt(vcpu);
10400 }
10401
10402 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10403 {
10404         ktime_t remaining =
10405                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10406         u64 value;
10407
10408         if (ktime_to_ns(remaining) <= 0)
10409                 return 0;
10410
10411         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10412         do_div(value, 1000000);
10413         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10414 }
10415
10416 /*
10417  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10418  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10419  * and this function updates it to reflect the changes to the guest state while
10420  * L2 was running (and perhaps made some exits which were handled directly by L0
10421  * without going back to L1), and to reflect the exit reason.
10422  * Note that we do not have to copy here all VMCS fields, just those that
10423  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10424  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10425  * which already writes to vmcs12 directly.
10426  */
10427 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10428                            u32 exit_reason, u32 exit_intr_info,
10429                            unsigned long exit_qualification)
10430 {
10431         /* update guest state fields: */
10432         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10433         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10434
10435         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10436         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10437         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10438
10439         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10440         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10441         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10442         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10443         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10444         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10445         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10446         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10447         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10448         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10449         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10450         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10451         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10452         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10453         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10454         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10455         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10456         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10457         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10458         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10459         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10460         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10461         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10462         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10463         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10464         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10465         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10466         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10467         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10468         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10469         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10470         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10471         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10472         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10473         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10474         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10475
10476         vmcs12->guest_interruptibility_info =
10477                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10478         vmcs12->guest_pending_dbg_exceptions =
10479                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10480         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10481                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10482         else
10483                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10484
10485         if (nested_cpu_has_preemption_timer(vmcs12)) {
10486                 if (vmcs12->vm_exit_controls &
10487                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10488                         vmcs12->vmx_preemption_timer_value =
10489                                 vmx_get_preemption_timer_value(vcpu);
10490                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10491         }
10492
10493         /*
10494          * In some cases (usually, nested EPT), L2 is allowed to change its
10495          * own CR3 without exiting. If it has changed it, we must keep it.
10496          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10497          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10498          *
10499          * Additionally, restore L2's PDPTR to vmcs12.
10500          */
10501         if (enable_ept) {
10502                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10503                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10504                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10505                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10506                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10507         }
10508
10509         if (nested_cpu_has_vid(vmcs12))
10510                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10511
10512         vmcs12->vm_entry_controls =
10513                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10514                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10515
10516         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10517                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10518                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10519         }
10520
10521         /* TODO: These cannot have changed unless we have MSR bitmaps and
10522          * the relevant bit asks not to trap the change */
10523         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10524                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10525         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10526                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10527         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10528         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10529         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10530         if (kvm_mpx_supported())
10531                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10532         if (nested_cpu_has_xsaves(vmcs12))
10533                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10534
10535         /* update exit information fields: */
10536
10537         vmcs12->vm_exit_reason = exit_reason;
10538         vmcs12->exit_qualification = exit_qualification;
10539
10540         vmcs12->vm_exit_intr_info = exit_intr_info;
10541         if ((vmcs12->vm_exit_intr_info &
10542              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10543             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10544                 vmcs12->vm_exit_intr_error_code =
10545                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10546         vmcs12->idt_vectoring_info_field = 0;
10547         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10548         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10549
10550         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10551                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10552                  * instead of reading the real value. */
10553                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10554
10555                 /*
10556                  * Transfer the event that L0 or L1 may wanted to inject into
10557                  * L2 to IDT_VECTORING_INFO_FIELD.
10558                  */
10559                 vmcs12_save_pending_event(vcpu, vmcs12);
10560         }
10561
10562         /*
10563          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10564          * preserved above and would only end up incorrectly in L1.
10565          */
10566         vcpu->arch.nmi_injected = false;
10567         kvm_clear_exception_queue(vcpu);
10568         kvm_clear_interrupt_queue(vcpu);
10569 }
10570
10571 /*
10572  * A part of what we need to when the nested L2 guest exits and we want to
10573  * run its L1 parent, is to reset L1's guest state to the host state specified
10574  * in vmcs12.
10575  * This function is to be called not only on normal nested exit, but also on
10576  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10577  * Failures During or After Loading Guest State").
10578  * This function should be called when the active VMCS is L1's (vmcs01).
10579  */
10580 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10581                                    struct vmcs12 *vmcs12)
10582 {
10583         struct kvm_segment seg;
10584
10585         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10586                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10587         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10588                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10589         else
10590                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10591         vmx_set_efer(vcpu, vcpu->arch.efer);
10592
10593         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10594         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10595         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10596         /*
10597          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10598          * actually changed, because it depends on the current state of
10599          * fpu_active (which may have changed).
10600          * Note that vmx_set_cr0 refers to efer set above.
10601          */
10602         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10603         /*
10604          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10605          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10606          * but we also need to update cr0_guest_host_mask and exception_bitmap.
10607          */
10608         update_exception_bitmap(vcpu);
10609         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10610         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10611
10612         /*
10613          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10614          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10615          */
10616         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10617         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10618
10619         nested_ept_uninit_mmu_context(vcpu);
10620
10621         kvm_set_cr3(vcpu, vmcs12->host_cr3);
10622         kvm_mmu_reset_context(vcpu);
10623
10624         if (!enable_ept)
10625                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10626
10627         if (enable_vpid) {
10628                 /*
10629                  * Trivially support vpid by letting L2s share their parent
10630                  * L1's vpid. TODO: move to a more elaborate solution, giving
10631                  * each L2 its own vpid and exposing the vpid feature to L1.
10632                  */
10633                 vmx_flush_tlb(vcpu);
10634         }
10635
10636
10637         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10638         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10639         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10640         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10641         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10642
10643         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10644         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10645                 vmcs_write64(GUEST_BNDCFGS, 0);
10646
10647         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10648                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10649                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10650         }
10651         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10652                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10653                         vmcs12->host_ia32_perf_global_ctrl);
10654
10655         /* Set L1 segment info according to Intel SDM
10656             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10657         seg = (struct kvm_segment) {
10658                 .base = 0,
10659                 .limit = 0xFFFFFFFF,
10660                 .selector = vmcs12->host_cs_selector,
10661                 .type = 11,
10662                 .present = 1,
10663                 .s = 1,
10664                 .g = 1
10665         };
10666         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10667                 seg.l = 1;
10668         else
10669                 seg.db = 1;
10670         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10671         seg = (struct kvm_segment) {
10672                 .base = 0,
10673                 .limit = 0xFFFFFFFF,
10674                 .type = 3,
10675                 .present = 1,
10676                 .s = 1,
10677                 .db = 1,
10678                 .g = 1
10679         };
10680         seg.selector = vmcs12->host_ds_selector;
10681         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10682         seg.selector = vmcs12->host_es_selector;
10683         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10684         seg.selector = vmcs12->host_ss_selector;
10685         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10686         seg.selector = vmcs12->host_fs_selector;
10687         seg.base = vmcs12->host_fs_base;
10688         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10689         seg.selector = vmcs12->host_gs_selector;
10690         seg.base = vmcs12->host_gs_base;
10691         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10692         seg = (struct kvm_segment) {
10693                 .base = vmcs12->host_tr_base,
10694                 .limit = 0x67,
10695                 .selector = vmcs12->host_tr_selector,
10696                 .type = 11,
10697                 .present = 1
10698         };
10699         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10700
10701         kvm_set_dr(vcpu, 7, 0x400);
10702         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10703
10704         if (cpu_has_vmx_msr_bitmap())
10705                 vmx_set_msr_bitmap(vcpu);
10706
10707         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10708                                 vmcs12->vm_exit_msr_load_count))
10709                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10710 }
10711
10712 /*
10713  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10714  * and modify vmcs12 to make it see what it would expect to see there if
10715  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10716  */
10717 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10718                               u32 exit_intr_info,
10719                               unsigned long exit_qualification)
10720 {
10721         struct vcpu_vmx *vmx = to_vmx(vcpu);
10722         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10723
10724         /* trying to cancel vmlaunch/vmresume is a bug */
10725         WARN_ON_ONCE(vmx->nested.nested_run_pending);
10726
10727         leave_guest_mode(vcpu);
10728         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10729                        exit_qualification);
10730
10731         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10732                                  vmcs12->vm_exit_msr_store_count))
10733                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10734
10735         vmx_load_vmcs01(vcpu);
10736
10737         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10738             && nested_exit_intr_ack_set(vcpu)) {
10739                 int irq = kvm_cpu_get_interrupt(vcpu);
10740                 WARN_ON(irq < 0);
10741                 vmcs12->vm_exit_intr_info = irq |
10742                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10743         }
10744
10745         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10746                                        vmcs12->exit_qualification,
10747                                        vmcs12->idt_vectoring_info_field,
10748                                        vmcs12->vm_exit_intr_info,
10749                                        vmcs12->vm_exit_intr_error_code,
10750                                        KVM_ISA_VMX);
10751
10752         vm_entry_controls_reset_shadow(vmx);
10753         vm_exit_controls_reset_shadow(vmx);
10754         vmx_segment_cache_clear(vmx);
10755
10756         /* if no vmcs02 cache requested, remove the one we used */
10757         if (VMCS02_POOL_SIZE == 0)
10758                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10759
10760         load_vmcs12_host_state(vcpu, vmcs12);
10761
10762         /* Update any VMCS fields that might have changed while L2 ran */
10763         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10764         if (vmx->hv_deadline_tsc == -1)
10765                 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
10766                                 PIN_BASED_VMX_PREEMPTION_TIMER);
10767         else
10768                 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
10769                               PIN_BASED_VMX_PREEMPTION_TIMER);
10770
10771         /* This is needed for same reason as it was needed in prepare_vmcs02 */
10772         vmx->host_rsp = 0;
10773
10774         /* Unpin physical memory we referred to in vmcs02 */
10775         if (vmx->nested.apic_access_page) {
10776                 nested_release_page(vmx->nested.apic_access_page);
10777                 vmx->nested.apic_access_page = NULL;
10778         }
10779         if (vmx->nested.virtual_apic_page) {
10780                 nested_release_page(vmx->nested.virtual_apic_page);
10781                 vmx->nested.virtual_apic_page = NULL;
10782         }
10783         if (vmx->nested.pi_desc_page) {
10784                 kunmap(vmx->nested.pi_desc_page);
10785                 nested_release_page(vmx->nested.pi_desc_page);
10786                 vmx->nested.pi_desc_page = NULL;
10787                 vmx->nested.pi_desc = NULL;
10788         }
10789
10790         /*
10791          * We are now running in L2, mmu_notifier will force to reload the
10792          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10793          */
10794         kvm_vcpu_reload_apic_access_page(vcpu);
10795
10796         /*
10797          * Exiting from L2 to L1, we're now back to L1 which thinks it just
10798          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10799          * success or failure flag accordingly.
10800          */
10801         if (unlikely(vmx->fail)) {
10802                 vmx->fail = 0;
10803                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10804         } else
10805                 nested_vmx_succeed(vcpu);
10806         if (enable_shadow_vmcs)
10807                 vmx->nested.sync_shadow_vmcs = true;
10808
10809         /* in case we halted in L2 */
10810         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10811 }
10812
10813 /*
10814  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10815  */
10816 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10817 {
10818         if (is_guest_mode(vcpu))
10819                 nested_vmx_vmexit(vcpu, -1, 0, 0);
10820         free_nested(to_vmx(vcpu));
10821 }
10822
10823 /*
10824  * L1's failure to enter L2 is a subset of a normal exit, as explained in
10825  * 23.7 "VM-entry failures during or after loading guest state" (this also
10826  * lists the acceptable exit-reason and exit-qualification parameters).
10827  * It should only be called before L2 actually succeeded to run, and when
10828  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10829  */
10830 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10831                         struct vmcs12 *vmcs12,
10832                         u32 reason, unsigned long qualification)
10833 {
10834         load_vmcs12_host_state(vcpu, vmcs12);
10835         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10836         vmcs12->exit_qualification = qualification;
10837         nested_vmx_succeed(vcpu);
10838         if (enable_shadow_vmcs)
10839                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10840 }
10841
10842 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10843                                struct x86_instruction_info *info,
10844                                enum x86_intercept_stage stage)
10845 {
10846         return X86EMUL_CONTINUE;
10847 }
10848
10849 #ifdef CONFIG_X86_64
10850 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
10851 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
10852                                   u64 divisor, u64 *result)
10853 {
10854         u64 low = a << shift, high = a >> (64 - shift);
10855
10856         /* To avoid the overflow on divq */
10857         if (high >= divisor)
10858                 return 1;
10859
10860         /* Low hold the result, high hold rem which is discarded */
10861         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
10862             "rm" (divisor), "0" (low), "1" (high));
10863         *result = low;
10864
10865         return 0;
10866 }
10867
10868 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
10869 {
10870         struct vcpu_vmx *vmx = to_vmx(vcpu);
10871         u64 tscl = rdtsc();
10872         u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
10873         u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
10874
10875         /* Convert to host delta tsc if tsc scaling is enabled */
10876         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
10877                         u64_shl_div_u64(delta_tsc,
10878                                 kvm_tsc_scaling_ratio_frac_bits,
10879                                 vcpu->arch.tsc_scaling_ratio,
10880                                 &delta_tsc))
10881                 return -ERANGE;
10882
10883         /*
10884          * If the delta tsc can't fit in the 32 bit after the multi shift,
10885          * we can't use the preemption timer.
10886          * It's possible that it fits on later vmentries, but checking
10887          * on every vmentry is costly so we just use an hrtimer.
10888          */
10889         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
10890                 return -ERANGE;
10891
10892         vmx->hv_deadline_tsc = tscl + delta_tsc;
10893         vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
10894                         PIN_BASED_VMX_PREEMPTION_TIMER);
10895         return 0;
10896 }
10897
10898 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
10899 {
10900         struct vcpu_vmx *vmx = to_vmx(vcpu);
10901         vmx->hv_deadline_tsc = -1;
10902         vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
10903                         PIN_BASED_VMX_PREEMPTION_TIMER);
10904 }
10905 #endif
10906
10907 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10908 {
10909         if (ple_gap)
10910                 shrink_ple_window(vcpu);
10911 }
10912
10913 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10914                                      struct kvm_memory_slot *slot)
10915 {
10916         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10917         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10918 }
10919
10920 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10921                                        struct kvm_memory_slot *slot)
10922 {
10923         kvm_mmu_slot_set_dirty(kvm, slot);
10924 }
10925
10926 static void vmx_flush_log_dirty(struct kvm *kvm)
10927 {
10928         kvm_flush_pml_buffers(kvm);
10929 }
10930
10931 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10932                                            struct kvm_memory_slot *memslot,
10933                                            gfn_t offset, unsigned long mask)
10934 {
10935         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10936 }
10937
10938 /*
10939  * This routine does the following things for vCPU which is going
10940  * to be blocked if VT-d PI is enabled.
10941  * - Store the vCPU to the wakeup list, so when interrupts happen
10942  *   we can find the right vCPU to wake up.
10943  * - Change the Posted-interrupt descriptor as below:
10944  *      'NDST' <-- vcpu->pre_pcpu
10945  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10946  * - If 'ON' is set during this process, which means at least one
10947  *   interrupt is posted for this vCPU, we cannot block it, in
10948  *   this case, return 1, otherwise, return 0.
10949  *
10950  */
10951 static int pi_pre_block(struct kvm_vcpu *vcpu)
10952 {
10953         unsigned long flags;
10954         unsigned int dest;
10955         struct pi_desc old, new;
10956         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10957
10958         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10959                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
10960                 !kvm_vcpu_apicv_active(vcpu))
10961                 return 0;
10962
10963         vcpu->pre_pcpu = vcpu->cpu;
10964         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10965                           vcpu->pre_pcpu), flags);
10966         list_add_tail(&vcpu->blocked_vcpu_list,
10967                       &per_cpu(blocked_vcpu_on_cpu,
10968                       vcpu->pre_pcpu));
10969         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
10970                                vcpu->pre_pcpu), flags);
10971
10972         do {
10973                 old.control = new.control = pi_desc->control;
10974
10975                 /*
10976                  * We should not block the vCPU if
10977                  * an interrupt is posted for it.
10978                  */
10979                 if (pi_test_on(pi_desc) == 1) {
10980                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10981                                           vcpu->pre_pcpu), flags);
10982                         list_del(&vcpu->blocked_vcpu_list);
10983                         spin_unlock_irqrestore(
10984                                         &per_cpu(blocked_vcpu_on_cpu_lock,
10985                                         vcpu->pre_pcpu), flags);
10986                         vcpu->pre_pcpu = -1;
10987
10988                         return 1;
10989                 }
10990
10991                 WARN((pi_desc->sn == 1),
10992                      "Warning: SN field of posted-interrupts "
10993                      "is set before blocking\n");
10994
10995                 /*
10996                  * Since vCPU can be preempted during this process,
10997                  * vcpu->cpu could be different with pre_pcpu, we
10998                  * need to set pre_pcpu as the destination of wakeup
10999                  * notification event, then we can find the right vCPU
11000                  * to wakeup in wakeup handler if interrupts happen
11001                  * when the vCPU is in blocked state.
11002                  */
11003                 dest = cpu_physical_id(vcpu->pre_pcpu);
11004
11005                 if (x2apic_enabled())
11006                         new.ndst = dest;
11007                 else
11008                         new.ndst = (dest << 8) & 0xFF00;
11009
11010                 /* set 'NV' to 'wakeup vector' */
11011                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
11012         } while (cmpxchg(&pi_desc->control, old.control,
11013                         new.control) != old.control);
11014
11015         return 0;
11016 }
11017
11018 static int vmx_pre_block(struct kvm_vcpu *vcpu)
11019 {
11020         if (pi_pre_block(vcpu))
11021                 return 1;
11022
11023         if (kvm_lapic_hv_timer_in_use(vcpu))
11024                 kvm_lapic_switch_to_sw_timer(vcpu);
11025
11026         return 0;
11027 }
11028
11029 static void pi_post_block(struct kvm_vcpu *vcpu)
11030 {
11031         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11032         struct pi_desc old, new;
11033         unsigned int dest;
11034         unsigned long flags;
11035
11036         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11037                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11038                 !kvm_vcpu_apicv_active(vcpu))
11039                 return;
11040
11041         do {
11042                 old.control = new.control = pi_desc->control;
11043
11044                 dest = cpu_physical_id(vcpu->cpu);
11045
11046                 if (x2apic_enabled())
11047                         new.ndst = dest;
11048                 else
11049                         new.ndst = (dest << 8) & 0xFF00;
11050
11051                 /* Allow posting non-urgent interrupts */
11052                 new.sn = 0;
11053
11054                 /* set 'NV' to 'notification vector' */
11055                 new.nv = POSTED_INTR_VECTOR;
11056         } while (cmpxchg(&pi_desc->control, old.control,
11057                         new.control) != old.control);
11058
11059         if(vcpu->pre_pcpu != -1) {
11060                 spin_lock_irqsave(
11061                         &per_cpu(blocked_vcpu_on_cpu_lock,
11062                         vcpu->pre_pcpu), flags);
11063                 list_del(&vcpu->blocked_vcpu_list);
11064                 spin_unlock_irqrestore(
11065                         &per_cpu(blocked_vcpu_on_cpu_lock,
11066                         vcpu->pre_pcpu), flags);
11067                 vcpu->pre_pcpu = -1;
11068         }
11069 }
11070
11071 static void vmx_post_block(struct kvm_vcpu *vcpu)
11072 {
11073         if (kvm_x86_ops->set_hv_timer)
11074                 kvm_lapic_switch_to_hv_timer(vcpu);
11075
11076         pi_post_block(vcpu);
11077 }
11078
11079 /*
11080  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11081  *
11082  * @kvm: kvm
11083  * @host_irq: host irq of the interrupt
11084  * @guest_irq: gsi of the interrupt
11085  * @set: set or unset PI
11086  * returns 0 on success, < 0 on failure
11087  */
11088 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11089                               uint32_t guest_irq, bool set)
11090 {
11091         struct kvm_kernel_irq_routing_entry *e;
11092         struct kvm_irq_routing_table *irq_rt;
11093         struct kvm_lapic_irq irq;
11094         struct kvm_vcpu *vcpu;
11095         struct vcpu_data vcpu_info;
11096         int idx, ret = -EINVAL;
11097
11098         if (!kvm_arch_has_assigned_device(kvm) ||
11099                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11100                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
11101                 return 0;
11102
11103         idx = srcu_read_lock(&kvm->irq_srcu);
11104         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11105         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
11106
11107         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11108                 if (e->type != KVM_IRQ_ROUTING_MSI)
11109                         continue;
11110                 /*
11111                  * VT-d PI cannot support posting multicast/broadcast
11112                  * interrupts to a vCPU, we still use interrupt remapping
11113                  * for these kind of interrupts.
11114                  *
11115                  * For lowest-priority interrupts, we only support
11116                  * those with single CPU as the destination, e.g. user
11117                  * configures the interrupts via /proc/irq or uses
11118                  * irqbalance to make the interrupts single-CPU.
11119                  *
11120                  * We will support full lowest-priority interrupt later.
11121                  */
11122
11123                 kvm_set_msi_irq(kvm, e, &irq);
11124                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11125                         /*
11126                          * Make sure the IRTE is in remapped mode if
11127                          * we don't handle it in posted mode.
11128                          */
11129                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11130                         if (ret < 0) {
11131                                 printk(KERN_INFO
11132                                    "failed to back to remapped mode, irq: %u\n",
11133                                    host_irq);
11134                                 goto out;
11135                         }
11136
11137                         continue;
11138                 }
11139
11140                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11141                 vcpu_info.vector = irq.vector;
11142
11143                 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
11144                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11145
11146                 if (set)
11147                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11148                 else {
11149                         /* suppress notification event before unposting */
11150                         pi_set_sn(vcpu_to_pi_desc(vcpu));
11151                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11152                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
11153                 }
11154
11155                 if (ret < 0) {
11156                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
11157                                         __func__);
11158                         goto out;
11159                 }
11160         }
11161
11162         ret = 0;
11163 out:
11164         srcu_read_unlock(&kvm->irq_srcu, idx);
11165         return ret;
11166 }
11167
11168 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11169 {
11170         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11171                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11172                         FEATURE_CONTROL_LMCE;
11173         else
11174                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11175                         ~FEATURE_CONTROL_LMCE;
11176 }
11177
11178 static struct kvm_x86_ops vmx_x86_ops = {
11179         .cpu_has_kvm_support = cpu_has_kvm_support,
11180         .disabled_by_bios = vmx_disabled_by_bios,
11181         .hardware_setup = hardware_setup,
11182         .hardware_unsetup = hardware_unsetup,
11183         .check_processor_compatibility = vmx_check_processor_compat,
11184         .hardware_enable = hardware_enable,
11185         .hardware_disable = hardware_disable,
11186         .cpu_has_accelerated_tpr = report_flexpriority,
11187         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
11188
11189         .vcpu_create = vmx_create_vcpu,
11190         .vcpu_free = vmx_free_vcpu,
11191         .vcpu_reset = vmx_vcpu_reset,
11192
11193         .prepare_guest_switch = vmx_save_host_state,
11194         .vcpu_load = vmx_vcpu_load,
11195         .vcpu_put = vmx_vcpu_put,
11196
11197         .update_bp_intercept = update_exception_bitmap,
11198         .get_msr = vmx_get_msr,
11199         .set_msr = vmx_set_msr,
11200         .get_segment_base = vmx_get_segment_base,
11201         .get_segment = vmx_get_segment,
11202         .set_segment = vmx_set_segment,
11203         .get_cpl = vmx_get_cpl,
11204         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
11205         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
11206         .decache_cr3 = vmx_decache_cr3,
11207         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
11208         .set_cr0 = vmx_set_cr0,
11209         .set_cr3 = vmx_set_cr3,
11210         .set_cr4 = vmx_set_cr4,
11211         .set_efer = vmx_set_efer,
11212         .get_idt = vmx_get_idt,
11213         .set_idt = vmx_set_idt,
11214         .get_gdt = vmx_get_gdt,
11215         .set_gdt = vmx_set_gdt,
11216         .get_dr6 = vmx_get_dr6,
11217         .set_dr6 = vmx_set_dr6,
11218         .set_dr7 = vmx_set_dr7,
11219         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
11220         .cache_reg = vmx_cache_reg,
11221         .get_rflags = vmx_get_rflags,
11222         .set_rflags = vmx_set_rflags,
11223
11224         .get_pkru = vmx_get_pkru,
11225
11226         .fpu_activate = vmx_fpu_activate,
11227         .fpu_deactivate = vmx_fpu_deactivate,
11228
11229         .tlb_flush = vmx_flush_tlb,
11230
11231         .run = vmx_vcpu_run,
11232         .handle_exit = vmx_handle_exit,
11233         .skip_emulated_instruction = skip_emulated_instruction,
11234         .set_interrupt_shadow = vmx_set_interrupt_shadow,
11235         .get_interrupt_shadow = vmx_get_interrupt_shadow,
11236         .patch_hypercall = vmx_patch_hypercall,
11237         .set_irq = vmx_inject_irq,
11238         .set_nmi = vmx_inject_nmi,
11239         .queue_exception = vmx_queue_exception,
11240         .cancel_injection = vmx_cancel_injection,
11241         .interrupt_allowed = vmx_interrupt_allowed,
11242         .nmi_allowed = vmx_nmi_allowed,
11243         .get_nmi_mask = vmx_get_nmi_mask,
11244         .set_nmi_mask = vmx_set_nmi_mask,
11245         .enable_nmi_window = enable_nmi_window,
11246         .enable_irq_window = enable_irq_window,
11247         .update_cr8_intercept = update_cr8_intercept,
11248         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
11249         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
11250         .get_enable_apicv = vmx_get_enable_apicv,
11251         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
11252         .load_eoi_exitmap = vmx_load_eoi_exitmap,
11253         .hwapic_irr_update = vmx_hwapic_irr_update,
11254         .hwapic_isr_update = vmx_hwapic_isr_update,
11255         .sync_pir_to_irr = vmx_sync_pir_to_irr,
11256         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
11257
11258         .set_tss_addr = vmx_set_tss_addr,
11259         .get_tdp_level = get_ept_level,
11260         .get_mt_mask = vmx_get_mt_mask,
11261
11262         .get_exit_info = vmx_get_exit_info,
11263
11264         .get_lpage_level = vmx_get_lpage_level,
11265
11266         .cpuid_update = vmx_cpuid_update,
11267
11268         .rdtscp_supported = vmx_rdtscp_supported,
11269         .invpcid_supported = vmx_invpcid_supported,
11270
11271         .set_supported_cpuid = vmx_set_supported_cpuid,
11272
11273         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
11274
11275         .read_tsc_offset = vmx_read_tsc_offset,
11276         .write_tsc_offset = vmx_write_tsc_offset,
11277         .adjust_tsc_offset_guest = vmx_adjust_tsc_offset_guest,
11278         .read_l1_tsc = vmx_read_l1_tsc,
11279
11280         .set_tdp_cr3 = vmx_set_cr3,
11281
11282         .check_intercept = vmx_check_intercept,
11283         .handle_external_intr = vmx_handle_external_intr,
11284         .mpx_supported = vmx_mpx_supported,
11285         .xsaves_supported = vmx_xsaves_supported,
11286
11287         .check_nested_events = vmx_check_nested_events,
11288
11289         .sched_in = vmx_sched_in,
11290
11291         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11292         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11293         .flush_log_dirty = vmx_flush_log_dirty,
11294         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
11295
11296         .pre_block = vmx_pre_block,
11297         .post_block = vmx_post_block,
11298
11299         .pmu_ops = &intel_pmu_ops,
11300
11301         .update_pi_irte = vmx_update_pi_irte,
11302
11303 #ifdef CONFIG_X86_64
11304         .set_hv_timer = vmx_set_hv_timer,
11305         .cancel_hv_timer = vmx_cancel_hv_timer,
11306 #endif
11307
11308         .setup_mce = vmx_setup_mce,
11309 };
11310
11311 static int __init vmx_init(void)
11312 {
11313         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11314                      __alignof__(struct vcpu_vmx), THIS_MODULE);
11315         if (r)
11316                 return r;
11317
11318 #ifdef CONFIG_KEXEC_CORE
11319         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11320                            crash_vmclear_local_loaded_vmcss);
11321 #endif
11322
11323         return 0;
11324 }
11325
11326 static void __exit vmx_exit(void)
11327 {
11328 #ifdef CONFIG_KEXEC_CORE
11329         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
11330         synchronize_rcu();
11331 #endif
11332
11333         kvm_exit();
11334 }
11335
11336 module_init(vmx_init)
11337 module_exit(vmx_exit)