2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include "kvm_cache_regs.h"
40 #include <asm/virtext.h>
44 #include <asm/perf_event.h>
48 #define __ex(x) __kvm_handle_fault_on_reboot(x)
49 #define __ex_clear(x, reg) \
50 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
52 MODULE_AUTHOR("Qumranet");
53 MODULE_LICENSE("GPL");
55 static const struct x86_cpu_id vmx_cpu_id[] = {
56 X86_FEATURE_MATCH(X86_FEATURE_VMX),
59 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
61 static bool __read_mostly enable_vpid = 1;
62 module_param_named(vpid, enable_vpid, bool, 0444);
64 static bool __read_mostly flexpriority_enabled = 1;
65 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
67 static bool __read_mostly enable_ept = 1;
68 module_param_named(ept, enable_ept, bool, S_IRUGO);
70 static bool __read_mostly enable_unrestricted_guest = 1;
71 module_param_named(unrestricted_guest,
72 enable_unrestricted_guest, bool, S_IRUGO);
74 static bool __read_mostly enable_ept_ad_bits = 1;
75 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
77 static bool __read_mostly emulate_invalid_guest_state = true;
78 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
80 static bool __read_mostly vmm_exclusive = 1;
81 module_param(vmm_exclusive, bool, S_IRUGO);
83 static bool __read_mostly fasteoi = 1;
84 module_param(fasteoi, bool, S_IRUGO);
87 * If nested=1, nested virtualization is supported, i.e., guests may use
88 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
89 * use VMX instructions.
91 static bool __read_mostly nested = 0;
92 module_param(nested, bool, S_IRUGO);
94 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
95 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
96 #define KVM_GUEST_CR0_MASK \
97 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
98 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
99 (X86_CR0_WP | X86_CR0_NE)
100 #define KVM_VM_CR0_ALWAYS_ON \
101 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
102 #define KVM_CR4_GUEST_OWNED_BITS \
103 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
104 | X86_CR4_OSXMMEXCPT)
106 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
107 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
109 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
112 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
113 * ple_gap: upper bound on the amount of time between two successive
114 * executions of PAUSE in a loop. Also indicate if ple enabled.
115 * According to test, this time is usually smaller than 128 cycles.
116 * ple_window: upper bound on the amount of time a guest is allowed to execute
117 * in a PAUSE loop. Tests indicate that most spinlocks are held for
118 * less than 2^12 cycles
119 * Time is measured based on a counter that runs at the same rate as the TSC,
120 * refer SDM volume 3b section 21.6.13 & 22.1.3.
122 #define KVM_VMX_DEFAULT_PLE_GAP 128
123 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
124 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
125 module_param(ple_gap, int, S_IRUGO);
127 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
128 module_param(ple_window, int, S_IRUGO);
130 #define NR_AUTOLOAD_MSRS 8
131 #define VMCS02_POOL_SIZE 1
140 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
141 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
142 * loaded on this CPU (so we can clear them if the CPU goes down).
148 struct list_head loaded_vmcss_on_cpu_link;
151 struct shared_msr_entry {
158 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
159 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
160 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
161 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
162 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
163 * More than one of these structures may exist, if L1 runs multiple L2 guests.
164 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
165 * underlying hardware which will be used to run L2.
166 * This structure is packed to ensure that its layout is identical across
167 * machines (necessary for live migration).
168 * If there are changes in this struct, VMCS12_REVISION must be changed.
170 typedef u64 natural_width;
171 struct __packed vmcs12 {
172 /* According to the Intel spec, a VMCS region must start with the
173 * following two fields. Then follow implementation-specific data.
178 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
179 u32 padding[7]; /* room for future expansion */
184 u64 vm_exit_msr_store_addr;
185 u64 vm_exit_msr_load_addr;
186 u64 vm_entry_msr_load_addr;
188 u64 virtual_apic_page_addr;
189 u64 apic_access_addr;
191 u64 guest_physical_address;
192 u64 vmcs_link_pointer;
193 u64 guest_ia32_debugctl;
196 u64 guest_ia32_perf_global_ctrl;
203 u64 host_ia32_perf_global_ctrl;
204 u64 padding64[8]; /* room for future expansion */
206 * To allow migration of L1 (complete with its L2 guests) between
207 * machines of different natural widths (32 or 64 bit), we cannot have
208 * unsigned long fields with no explict size. We use u64 (aliased
209 * natural_width) instead. Luckily, x86 is little-endian.
211 natural_width cr0_guest_host_mask;
212 natural_width cr4_guest_host_mask;
213 natural_width cr0_read_shadow;
214 natural_width cr4_read_shadow;
215 natural_width cr3_target_value0;
216 natural_width cr3_target_value1;
217 natural_width cr3_target_value2;
218 natural_width cr3_target_value3;
219 natural_width exit_qualification;
220 natural_width guest_linear_address;
221 natural_width guest_cr0;
222 natural_width guest_cr3;
223 natural_width guest_cr4;
224 natural_width guest_es_base;
225 natural_width guest_cs_base;
226 natural_width guest_ss_base;
227 natural_width guest_ds_base;
228 natural_width guest_fs_base;
229 natural_width guest_gs_base;
230 natural_width guest_ldtr_base;
231 natural_width guest_tr_base;
232 natural_width guest_gdtr_base;
233 natural_width guest_idtr_base;
234 natural_width guest_dr7;
235 natural_width guest_rsp;
236 natural_width guest_rip;
237 natural_width guest_rflags;
238 natural_width guest_pending_dbg_exceptions;
239 natural_width guest_sysenter_esp;
240 natural_width guest_sysenter_eip;
241 natural_width host_cr0;
242 natural_width host_cr3;
243 natural_width host_cr4;
244 natural_width host_fs_base;
245 natural_width host_gs_base;
246 natural_width host_tr_base;
247 natural_width host_gdtr_base;
248 natural_width host_idtr_base;
249 natural_width host_ia32_sysenter_esp;
250 natural_width host_ia32_sysenter_eip;
251 natural_width host_rsp;
252 natural_width host_rip;
253 natural_width paddingl[8]; /* room for future expansion */
254 u32 pin_based_vm_exec_control;
255 u32 cpu_based_vm_exec_control;
256 u32 exception_bitmap;
257 u32 page_fault_error_code_mask;
258 u32 page_fault_error_code_match;
259 u32 cr3_target_count;
260 u32 vm_exit_controls;
261 u32 vm_exit_msr_store_count;
262 u32 vm_exit_msr_load_count;
263 u32 vm_entry_controls;
264 u32 vm_entry_msr_load_count;
265 u32 vm_entry_intr_info_field;
266 u32 vm_entry_exception_error_code;
267 u32 vm_entry_instruction_len;
269 u32 secondary_vm_exec_control;
270 u32 vm_instruction_error;
272 u32 vm_exit_intr_info;
273 u32 vm_exit_intr_error_code;
274 u32 idt_vectoring_info_field;
275 u32 idt_vectoring_error_code;
276 u32 vm_exit_instruction_len;
277 u32 vmx_instruction_info;
284 u32 guest_ldtr_limit;
286 u32 guest_gdtr_limit;
287 u32 guest_idtr_limit;
288 u32 guest_es_ar_bytes;
289 u32 guest_cs_ar_bytes;
290 u32 guest_ss_ar_bytes;
291 u32 guest_ds_ar_bytes;
292 u32 guest_fs_ar_bytes;
293 u32 guest_gs_ar_bytes;
294 u32 guest_ldtr_ar_bytes;
295 u32 guest_tr_ar_bytes;
296 u32 guest_interruptibility_info;
297 u32 guest_activity_state;
298 u32 guest_sysenter_cs;
299 u32 host_ia32_sysenter_cs;
300 u32 padding32[8]; /* room for future expansion */
301 u16 virtual_processor_id;
302 u16 guest_es_selector;
303 u16 guest_cs_selector;
304 u16 guest_ss_selector;
305 u16 guest_ds_selector;
306 u16 guest_fs_selector;
307 u16 guest_gs_selector;
308 u16 guest_ldtr_selector;
309 u16 guest_tr_selector;
310 u16 host_es_selector;
311 u16 host_cs_selector;
312 u16 host_ss_selector;
313 u16 host_ds_selector;
314 u16 host_fs_selector;
315 u16 host_gs_selector;
316 u16 host_tr_selector;
320 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
321 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
322 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
324 #define VMCS12_REVISION 0x11e57ed0
327 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
328 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
329 * current implementation, 4K are reserved to avoid future complications.
331 #define VMCS12_SIZE 0x1000
333 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
335 struct list_head list;
337 struct loaded_vmcs vmcs02;
341 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
342 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
345 /* Has the level1 guest done vmxon? */
348 /* The guest-physical address of the current VMCS L1 keeps for L2 */
350 /* The host-usable pointer to the above */
351 struct page *current_vmcs12_page;
352 struct vmcs12 *current_vmcs12;
354 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
355 struct list_head vmcs02_pool;
357 u64 vmcs01_tsc_offset;
358 /* L2 must run next, and mustn't decide to exit to L1. */
359 bool nested_run_pending;
361 * Guest pages referred to in vmcs02 with host-physical pointers, so
362 * we must keep them pinned while L2 runs.
364 struct page *apic_access_page;
368 struct kvm_vcpu vcpu;
369 unsigned long host_rsp;
372 bool nmi_known_unmasked;
374 u32 idt_vectoring_info;
376 struct shared_msr_entry *guest_msrs;
380 u64 msr_host_kernel_gs_base;
381 u64 msr_guest_kernel_gs_base;
384 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
385 * non-nested (L1) guest, it always points to vmcs01. For a nested
386 * guest (L2), it points to a different VMCS.
388 struct loaded_vmcs vmcs01;
389 struct loaded_vmcs *loaded_vmcs;
390 bool __launched; /* temporary, used in vmx_vcpu_run */
391 struct msr_autoload {
393 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
394 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
398 u16 fs_sel, gs_sel, ldt_sel;
402 int gs_ldt_reload_needed;
403 int fs_reload_needed;
408 struct kvm_save_segment {
413 } tr, es, ds, fs, gs;
416 u32 bitmask; /* 4 bits per segment (1 bit per field) */
417 struct kvm_save_segment seg[8];
420 bool emulation_required;
422 /* Support for vnmi-less CPUs */
423 int soft_vnmi_blocked;
425 s64 vnmi_blocked_time;
430 /* Support for a guest hypervisor (nested VMX) */
431 struct nested_vmx nested;
434 enum segment_cache_field {
443 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
445 return container_of(vcpu, struct vcpu_vmx, vcpu);
448 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
449 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
450 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
451 [number##_HIGH] = VMCS12_OFFSET(name)+4
453 static unsigned short vmcs_field_to_offset_table[] = {
454 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
455 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
456 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
457 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
458 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
459 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
460 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
461 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
462 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
463 FIELD(HOST_ES_SELECTOR, host_es_selector),
464 FIELD(HOST_CS_SELECTOR, host_cs_selector),
465 FIELD(HOST_SS_SELECTOR, host_ss_selector),
466 FIELD(HOST_DS_SELECTOR, host_ds_selector),
467 FIELD(HOST_FS_SELECTOR, host_fs_selector),
468 FIELD(HOST_GS_SELECTOR, host_gs_selector),
469 FIELD(HOST_TR_SELECTOR, host_tr_selector),
470 FIELD64(IO_BITMAP_A, io_bitmap_a),
471 FIELD64(IO_BITMAP_B, io_bitmap_b),
472 FIELD64(MSR_BITMAP, msr_bitmap),
473 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
474 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
475 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
476 FIELD64(TSC_OFFSET, tsc_offset),
477 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
478 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
479 FIELD64(EPT_POINTER, ept_pointer),
480 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
481 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
482 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
483 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
484 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
485 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
486 FIELD64(GUEST_PDPTR0, guest_pdptr0),
487 FIELD64(GUEST_PDPTR1, guest_pdptr1),
488 FIELD64(GUEST_PDPTR2, guest_pdptr2),
489 FIELD64(GUEST_PDPTR3, guest_pdptr3),
490 FIELD64(HOST_IA32_PAT, host_ia32_pat),
491 FIELD64(HOST_IA32_EFER, host_ia32_efer),
492 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
493 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
494 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
495 FIELD(EXCEPTION_BITMAP, exception_bitmap),
496 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
497 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
498 FIELD(CR3_TARGET_COUNT, cr3_target_count),
499 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
500 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
501 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
502 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
503 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
504 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
505 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
506 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
507 FIELD(TPR_THRESHOLD, tpr_threshold),
508 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
509 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
510 FIELD(VM_EXIT_REASON, vm_exit_reason),
511 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
512 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
513 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
514 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
515 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
516 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
517 FIELD(GUEST_ES_LIMIT, guest_es_limit),
518 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
519 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
520 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
521 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
522 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
523 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
524 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
525 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
526 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
527 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
528 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
529 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
530 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
531 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
532 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
533 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
534 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
535 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
536 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
537 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
538 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
539 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
540 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
541 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
542 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
543 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
544 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
545 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
546 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
547 FIELD(EXIT_QUALIFICATION, exit_qualification),
548 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
549 FIELD(GUEST_CR0, guest_cr0),
550 FIELD(GUEST_CR3, guest_cr3),
551 FIELD(GUEST_CR4, guest_cr4),
552 FIELD(GUEST_ES_BASE, guest_es_base),
553 FIELD(GUEST_CS_BASE, guest_cs_base),
554 FIELD(GUEST_SS_BASE, guest_ss_base),
555 FIELD(GUEST_DS_BASE, guest_ds_base),
556 FIELD(GUEST_FS_BASE, guest_fs_base),
557 FIELD(GUEST_GS_BASE, guest_gs_base),
558 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
559 FIELD(GUEST_TR_BASE, guest_tr_base),
560 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
561 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
562 FIELD(GUEST_DR7, guest_dr7),
563 FIELD(GUEST_RSP, guest_rsp),
564 FIELD(GUEST_RIP, guest_rip),
565 FIELD(GUEST_RFLAGS, guest_rflags),
566 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
567 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
568 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
569 FIELD(HOST_CR0, host_cr0),
570 FIELD(HOST_CR3, host_cr3),
571 FIELD(HOST_CR4, host_cr4),
572 FIELD(HOST_FS_BASE, host_fs_base),
573 FIELD(HOST_GS_BASE, host_gs_base),
574 FIELD(HOST_TR_BASE, host_tr_base),
575 FIELD(HOST_GDTR_BASE, host_gdtr_base),
576 FIELD(HOST_IDTR_BASE, host_idtr_base),
577 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
578 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
579 FIELD(HOST_RSP, host_rsp),
580 FIELD(HOST_RIP, host_rip),
582 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
584 static inline short vmcs_field_to_offset(unsigned long field)
586 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
588 return vmcs_field_to_offset_table[field];
591 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
593 return to_vmx(vcpu)->nested.current_vmcs12;
596 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
598 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
599 if (is_error_page(page)) {
600 kvm_release_page_clean(page);
606 static void nested_release_page(struct page *page)
608 kvm_release_page_dirty(page);
611 static void nested_release_page_clean(struct page *page)
613 kvm_release_page_clean(page);
616 static u64 construct_eptp(unsigned long root_hpa);
617 static void kvm_cpu_vmxon(u64 addr);
618 static void kvm_cpu_vmxoff(void);
619 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
620 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
621 static void vmx_set_segment(struct kvm_vcpu *vcpu,
622 struct kvm_segment *var, int seg);
623 static void vmx_get_segment(struct kvm_vcpu *vcpu,
624 struct kvm_segment *var, int seg);
626 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
627 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
629 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
630 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
632 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
633 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
635 static unsigned long *vmx_io_bitmap_a;
636 static unsigned long *vmx_io_bitmap_b;
637 static unsigned long *vmx_msr_bitmap_legacy;
638 static unsigned long *vmx_msr_bitmap_longmode;
640 static bool cpu_has_load_ia32_efer;
641 static bool cpu_has_load_perf_global_ctrl;
643 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
644 static DEFINE_SPINLOCK(vmx_vpid_lock);
646 static struct vmcs_config {
650 u32 pin_based_exec_ctrl;
651 u32 cpu_based_exec_ctrl;
652 u32 cpu_based_2nd_exec_ctrl;
657 static struct vmx_capability {
662 #define VMX_SEGMENT_FIELD(seg) \
663 [VCPU_SREG_##seg] = { \
664 .selector = GUEST_##seg##_SELECTOR, \
665 .base = GUEST_##seg##_BASE, \
666 .limit = GUEST_##seg##_LIMIT, \
667 .ar_bytes = GUEST_##seg##_AR_BYTES, \
670 static struct kvm_vmx_segment_field {
675 } kvm_vmx_segment_fields[] = {
676 VMX_SEGMENT_FIELD(CS),
677 VMX_SEGMENT_FIELD(DS),
678 VMX_SEGMENT_FIELD(ES),
679 VMX_SEGMENT_FIELD(FS),
680 VMX_SEGMENT_FIELD(GS),
681 VMX_SEGMENT_FIELD(SS),
682 VMX_SEGMENT_FIELD(TR),
683 VMX_SEGMENT_FIELD(LDTR),
686 static u64 host_efer;
688 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
691 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
692 * away by decrementing the array size.
694 static const u32 vmx_msr_index[] = {
696 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
698 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
700 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
702 static inline bool is_page_fault(u32 intr_info)
704 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
705 INTR_INFO_VALID_MASK)) ==
706 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
709 static inline bool is_no_device(u32 intr_info)
711 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
712 INTR_INFO_VALID_MASK)) ==
713 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
716 static inline bool is_invalid_opcode(u32 intr_info)
718 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
719 INTR_INFO_VALID_MASK)) ==
720 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
723 static inline bool is_external_interrupt(u32 intr_info)
725 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
726 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
729 static inline bool is_machine_check(u32 intr_info)
731 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
732 INTR_INFO_VALID_MASK)) ==
733 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
736 static inline bool cpu_has_vmx_msr_bitmap(void)
738 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
741 static inline bool cpu_has_vmx_tpr_shadow(void)
743 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
746 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
748 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
751 static inline bool cpu_has_secondary_exec_ctrls(void)
753 return vmcs_config.cpu_based_exec_ctrl &
754 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
757 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
759 return vmcs_config.cpu_based_2nd_exec_ctrl &
760 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
763 static inline bool cpu_has_vmx_flexpriority(void)
765 return cpu_has_vmx_tpr_shadow() &&
766 cpu_has_vmx_virtualize_apic_accesses();
769 static inline bool cpu_has_vmx_ept_execute_only(void)
771 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
774 static inline bool cpu_has_vmx_eptp_uncacheable(void)
776 return vmx_capability.ept & VMX_EPTP_UC_BIT;
779 static inline bool cpu_has_vmx_eptp_writeback(void)
781 return vmx_capability.ept & VMX_EPTP_WB_BIT;
784 static inline bool cpu_has_vmx_ept_2m_page(void)
786 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
789 static inline bool cpu_has_vmx_ept_1g_page(void)
791 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
794 static inline bool cpu_has_vmx_ept_4levels(void)
796 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
799 static inline bool cpu_has_vmx_ept_ad_bits(void)
801 return vmx_capability.ept & VMX_EPT_AD_BIT;
804 static inline bool cpu_has_vmx_invept_individual_addr(void)
806 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
809 static inline bool cpu_has_vmx_invept_context(void)
811 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
814 static inline bool cpu_has_vmx_invept_global(void)
816 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
819 static inline bool cpu_has_vmx_invvpid_single(void)
821 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
824 static inline bool cpu_has_vmx_invvpid_global(void)
826 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
829 static inline bool cpu_has_vmx_ept(void)
831 return vmcs_config.cpu_based_2nd_exec_ctrl &
832 SECONDARY_EXEC_ENABLE_EPT;
835 static inline bool cpu_has_vmx_unrestricted_guest(void)
837 return vmcs_config.cpu_based_2nd_exec_ctrl &
838 SECONDARY_EXEC_UNRESTRICTED_GUEST;
841 static inline bool cpu_has_vmx_ple(void)
843 return vmcs_config.cpu_based_2nd_exec_ctrl &
844 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
847 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
849 return flexpriority_enabled && irqchip_in_kernel(kvm);
852 static inline bool cpu_has_vmx_vpid(void)
854 return vmcs_config.cpu_based_2nd_exec_ctrl &
855 SECONDARY_EXEC_ENABLE_VPID;
858 static inline bool cpu_has_vmx_rdtscp(void)
860 return vmcs_config.cpu_based_2nd_exec_ctrl &
861 SECONDARY_EXEC_RDTSCP;
864 static inline bool cpu_has_virtual_nmis(void)
866 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
869 static inline bool cpu_has_vmx_wbinvd_exit(void)
871 return vmcs_config.cpu_based_2nd_exec_ctrl &
872 SECONDARY_EXEC_WBINVD_EXITING;
875 static inline bool report_flexpriority(void)
877 return flexpriority_enabled;
880 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
882 return vmcs12->cpu_based_vm_exec_control & bit;
885 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
887 return (vmcs12->cpu_based_vm_exec_control &
888 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
889 (vmcs12->secondary_vm_exec_control & bit);
892 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
893 struct kvm_vcpu *vcpu)
895 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
898 static inline bool is_exception(u32 intr_info)
900 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
901 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
904 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
905 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
906 struct vmcs12 *vmcs12,
907 u32 reason, unsigned long qualification);
909 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
913 for (i = 0; i < vmx->nmsrs; ++i)
914 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
919 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
925 } operand = { vpid, 0, gva };
927 asm volatile (__ex(ASM_VMX_INVVPID)
928 /* CF==1 or ZF==1 --> rc = -1 */
930 : : "a"(&operand), "c"(ext) : "cc", "memory");
933 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
937 } operand = {eptp, gpa};
939 asm volatile (__ex(ASM_VMX_INVEPT)
940 /* CF==1 or ZF==1 --> rc = -1 */
941 "; ja 1f ; ud2 ; 1:\n"
942 : : "a" (&operand), "c" (ext) : "cc", "memory");
945 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
949 i = __find_msr_index(vmx, msr);
951 return &vmx->guest_msrs[i];
955 static void vmcs_clear(struct vmcs *vmcs)
957 u64 phys_addr = __pa(vmcs);
960 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
961 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
964 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
968 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
970 vmcs_clear(loaded_vmcs->vmcs);
971 loaded_vmcs->cpu = -1;
972 loaded_vmcs->launched = 0;
975 static void vmcs_load(struct vmcs *vmcs)
977 u64 phys_addr = __pa(vmcs);
980 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
981 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
984 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
988 static void __loaded_vmcs_clear(void *arg)
990 struct loaded_vmcs *loaded_vmcs = arg;
991 int cpu = raw_smp_processor_id();
993 if (loaded_vmcs->cpu != cpu)
994 return; /* vcpu migration can race with cpu offline */
995 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
996 per_cpu(current_vmcs, cpu) = NULL;
997 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
998 loaded_vmcs_init(loaded_vmcs);
1001 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1003 if (loaded_vmcs->cpu != -1)
1004 smp_call_function_single(
1005 loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
1008 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1013 if (cpu_has_vmx_invvpid_single())
1014 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1017 static inline void vpid_sync_vcpu_global(void)
1019 if (cpu_has_vmx_invvpid_global())
1020 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1023 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1025 if (cpu_has_vmx_invvpid_single())
1026 vpid_sync_vcpu_single(vmx);
1028 vpid_sync_vcpu_global();
1031 static inline void ept_sync_global(void)
1033 if (cpu_has_vmx_invept_global())
1034 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1037 static inline void ept_sync_context(u64 eptp)
1040 if (cpu_has_vmx_invept_context())
1041 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1047 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1050 if (cpu_has_vmx_invept_individual_addr())
1051 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1054 ept_sync_context(eptp);
1058 static __always_inline unsigned long vmcs_readl(unsigned long field)
1060 unsigned long value;
1062 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1063 : "=a"(value) : "d"(field) : "cc");
1067 static __always_inline u16 vmcs_read16(unsigned long field)
1069 return vmcs_readl(field);
1072 static __always_inline u32 vmcs_read32(unsigned long field)
1074 return vmcs_readl(field);
1077 static __always_inline u64 vmcs_read64(unsigned long field)
1079 #ifdef CONFIG_X86_64
1080 return vmcs_readl(field);
1082 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1086 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1088 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1089 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1093 static void vmcs_writel(unsigned long field, unsigned long value)
1097 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1098 : "=q"(error) : "a"(value), "d"(field) : "cc");
1099 if (unlikely(error))
1100 vmwrite_error(field, value);
1103 static void vmcs_write16(unsigned long field, u16 value)
1105 vmcs_writel(field, value);
1108 static void vmcs_write32(unsigned long field, u32 value)
1110 vmcs_writel(field, value);
1113 static void vmcs_write64(unsigned long field, u64 value)
1115 vmcs_writel(field, value);
1116 #ifndef CONFIG_X86_64
1118 vmcs_writel(field+1, value >> 32);
1122 static void vmcs_clear_bits(unsigned long field, u32 mask)
1124 vmcs_writel(field, vmcs_readl(field) & ~mask);
1127 static void vmcs_set_bits(unsigned long field, u32 mask)
1129 vmcs_writel(field, vmcs_readl(field) | mask);
1132 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1134 vmx->segment_cache.bitmask = 0;
1137 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1141 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1143 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1144 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1145 vmx->segment_cache.bitmask = 0;
1147 ret = vmx->segment_cache.bitmask & mask;
1148 vmx->segment_cache.bitmask |= mask;
1152 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1154 u16 *p = &vmx->segment_cache.seg[seg].selector;
1156 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1157 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1161 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1163 ulong *p = &vmx->segment_cache.seg[seg].base;
1165 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1166 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1170 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1172 u32 *p = &vmx->segment_cache.seg[seg].limit;
1174 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1175 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1179 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1181 u32 *p = &vmx->segment_cache.seg[seg].ar;
1183 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1184 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1188 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1192 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1193 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1194 if ((vcpu->guest_debug &
1195 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1196 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1197 eb |= 1u << BP_VECTOR;
1198 if (to_vmx(vcpu)->rmode.vm86_active)
1201 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1202 if (vcpu->fpu_active)
1203 eb &= ~(1u << NM_VECTOR);
1205 /* When we are running a nested L2 guest and L1 specified for it a
1206 * certain exception bitmap, we must trap the same exceptions and pass
1207 * them to L1. When running L2, we will only handle the exceptions
1208 * specified above if L1 did not want them.
1210 if (is_guest_mode(vcpu))
1211 eb |= get_vmcs12(vcpu)->exception_bitmap;
1213 vmcs_write32(EXCEPTION_BITMAP, eb);
1216 static void clear_atomic_switch_msr_special(unsigned long entry,
1219 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1220 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1223 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1226 struct msr_autoload *m = &vmx->msr_autoload;
1230 if (cpu_has_load_ia32_efer) {
1231 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1232 VM_EXIT_LOAD_IA32_EFER);
1236 case MSR_CORE_PERF_GLOBAL_CTRL:
1237 if (cpu_has_load_perf_global_ctrl) {
1238 clear_atomic_switch_msr_special(
1239 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1240 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1246 for (i = 0; i < m->nr; ++i)
1247 if (m->guest[i].index == msr)
1253 m->guest[i] = m->guest[m->nr];
1254 m->host[i] = m->host[m->nr];
1255 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1256 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1259 static void add_atomic_switch_msr_special(unsigned long entry,
1260 unsigned long exit, unsigned long guest_val_vmcs,
1261 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1263 vmcs_write64(guest_val_vmcs, guest_val);
1264 vmcs_write64(host_val_vmcs, host_val);
1265 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1266 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1269 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1270 u64 guest_val, u64 host_val)
1273 struct msr_autoload *m = &vmx->msr_autoload;
1277 if (cpu_has_load_ia32_efer) {
1278 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1279 VM_EXIT_LOAD_IA32_EFER,
1282 guest_val, host_val);
1286 case MSR_CORE_PERF_GLOBAL_CTRL:
1287 if (cpu_has_load_perf_global_ctrl) {
1288 add_atomic_switch_msr_special(
1289 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1290 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1291 GUEST_IA32_PERF_GLOBAL_CTRL,
1292 HOST_IA32_PERF_GLOBAL_CTRL,
1293 guest_val, host_val);
1299 for (i = 0; i < m->nr; ++i)
1300 if (m->guest[i].index == msr)
1303 if (i == NR_AUTOLOAD_MSRS) {
1304 printk_once(KERN_WARNING"Not enough mst switch entries. "
1305 "Can't add msr %x\n", msr);
1307 } else if (i == m->nr) {
1309 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1310 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1313 m->guest[i].index = msr;
1314 m->guest[i].value = guest_val;
1315 m->host[i].index = msr;
1316 m->host[i].value = host_val;
1319 static void reload_tss(void)
1322 * VT restores TR but not its size. Useless.
1324 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1325 struct desc_struct *descs;
1327 descs = (void *)gdt->address;
1328 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1332 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1337 guest_efer = vmx->vcpu.arch.efer;
1340 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1343 ignore_bits = EFER_NX | EFER_SCE;
1344 #ifdef CONFIG_X86_64
1345 ignore_bits |= EFER_LMA | EFER_LME;
1346 /* SCE is meaningful only in long mode on Intel */
1347 if (guest_efer & EFER_LMA)
1348 ignore_bits &= ~(u64)EFER_SCE;
1350 guest_efer &= ~ignore_bits;
1351 guest_efer |= host_efer & ignore_bits;
1352 vmx->guest_msrs[efer_offset].data = guest_efer;
1353 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1355 clear_atomic_switch_msr(vmx, MSR_EFER);
1356 /* On ept, can't emulate nx, and must switch nx atomically */
1357 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1358 guest_efer = vmx->vcpu.arch.efer;
1359 if (!(guest_efer & EFER_LMA))
1360 guest_efer &= ~EFER_LME;
1361 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1368 static unsigned long segment_base(u16 selector)
1370 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1371 struct desc_struct *d;
1372 unsigned long table_base;
1375 if (!(selector & ~3))
1378 table_base = gdt->address;
1380 if (selector & 4) { /* from ldt */
1381 u16 ldt_selector = kvm_read_ldt();
1383 if (!(ldt_selector & ~3))
1386 table_base = segment_base(ldt_selector);
1388 d = (struct desc_struct *)(table_base + (selector & ~7));
1389 v = get_desc_base(d);
1390 #ifdef CONFIG_X86_64
1391 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1392 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1397 static inline unsigned long kvm_read_tr_base(void)
1400 asm("str %0" : "=g"(tr));
1401 return segment_base(tr);
1404 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1406 struct vcpu_vmx *vmx = to_vmx(vcpu);
1409 if (vmx->host_state.loaded)
1412 vmx->host_state.loaded = 1;
1414 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1415 * allow segment selectors with cpl > 0 or ti == 1.
1417 vmx->host_state.ldt_sel = kvm_read_ldt();
1418 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1419 savesegment(fs, vmx->host_state.fs_sel);
1420 if (!(vmx->host_state.fs_sel & 7)) {
1421 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1422 vmx->host_state.fs_reload_needed = 0;
1424 vmcs_write16(HOST_FS_SELECTOR, 0);
1425 vmx->host_state.fs_reload_needed = 1;
1427 savesegment(gs, vmx->host_state.gs_sel);
1428 if (!(vmx->host_state.gs_sel & 7))
1429 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1431 vmcs_write16(HOST_GS_SELECTOR, 0);
1432 vmx->host_state.gs_ldt_reload_needed = 1;
1435 #ifdef CONFIG_X86_64
1436 savesegment(ds, vmx->host_state.ds_sel);
1437 savesegment(es, vmx->host_state.es_sel);
1440 #ifdef CONFIG_X86_64
1441 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1442 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1444 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1445 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1448 #ifdef CONFIG_X86_64
1449 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1450 if (is_long_mode(&vmx->vcpu))
1451 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1453 for (i = 0; i < vmx->save_nmsrs; ++i)
1454 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1455 vmx->guest_msrs[i].data,
1456 vmx->guest_msrs[i].mask);
1459 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1461 if (!vmx->host_state.loaded)
1464 ++vmx->vcpu.stat.host_state_reload;
1465 vmx->host_state.loaded = 0;
1466 #ifdef CONFIG_X86_64
1467 if (is_long_mode(&vmx->vcpu))
1468 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1470 if (vmx->host_state.gs_ldt_reload_needed) {
1471 kvm_load_ldt(vmx->host_state.ldt_sel);
1472 #ifdef CONFIG_X86_64
1473 load_gs_index(vmx->host_state.gs_sel);
1475 loadsegment(gs, vmx->host_state.gs_sel);
1478 if (vmx->host_state.fs_reload_needed)
1479 loadsegment(fs, vmx->host_state.fs_sel);
1480 #ifdef CONFIG_X86_64
1481 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1482 loadsegment(ds, vmx->host_state.ds_sel);
1483 loadsegment(es, vmx->host_state.es_sel);
1487 * The sysexit path does not restore ds/es, so we must set them to
1488 * a reasonable value ourselves.
1490 loadsegment(ds, __USER_DS);
1491 loadsegment(es, __USER_DS);
1494 #ifdef CONFIG_X86_64
1495 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1499 load_gdt(&__get_cpu_var(host_gdt));
1502 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1505 __vmx_load_host_state(vmx);
1510 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1511 * vcpu mutex is already taken.
1513 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1515 struct vcpu_vmx *vmx = to_vmx(vcpu);
1516 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1519 kvm_cpu_vmxon(phys_addr);
1520 else if (vmx->loaded_vmcs->cpu != cpu)
1521 loaded_vmcs_clear(vmx->loaded_vmcs);
1523 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1524 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1525 vmcs_load(vmx->loaded_vmcs->vmcs);
1528 if (vmx->loaded_vmcs->cpu != cpu) {
1529 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1530 unsigned long sysenter_esp;
1532 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1533 local_irq_disable();
1534 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1535 &per_cpu(loaded_vmcss_on_cpu, cpu));
1539 * Linux uses per-cpu TSS and GDT, so set these when switching
1542 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1543 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
1545 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1546 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1547 vmx->loaded_vmcs->cpu = cpu;
1551 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1553 __vmx_load_host_state(to_vmx(vcpu));
1554 if (!vmm_exclusive) {
1555 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1561 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1565 if (vcpu->fpu_active)
1567 vcpu->fpu_active = 1;
1568 cr0 = vmcs_readl(GUEST_CR0);
1569 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1570 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1571 vmcs_writel(GUEST_CR0, cr0);
1572 update_exception_bitmap(vcpu);
1573 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1574 if (is_guest_mode(vcpu))
1575 vcpu->arch.cr0_guest_owned_bits &=
1576 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1577 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1580 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1583 * Return the cr0 value that a nested guest would read. This is a combination
1584 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1585 * its hypervisor (cr0_read_shadow).
1587 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1589 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1590 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1592 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1594 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1595 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1598 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1600 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1601 * set this *before* calling this function.
1603 vmx_decache_cr0_guest_bits(vcpu);
1604 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1605 update_exception_bitmap(vcpu);
1606 vcpu->arch.cr0_guest_owned_bits = 0;
1607 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1608 if (is_guest_mode(vcpu)) {
1610 * L1's specified read shadow might not contain the TS bit,
1611 * so now that we turned on shadowing of this bit, we need to
1612 * set this bit of the shadow. Like in nested_vmx_run we need
1613 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1614 * up-to-date here because we just decached cr0.TS (and we'll
1615 * only update vmcs12->guest_cr0 on nested exit).
1617 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1618 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1619 (vcpu->arch.cr0 & X86_CR0_TS);
1620 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1622 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1625 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1627 unsigned long rflags, save_rflags;
1629 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1630 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1631 rflags = vmcs_readl(GUEST_RFLAGS);
1632 if (to_vmx(vcpu)->rmode.vm86_active) {
1633 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1634 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1635 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1637 to_vmx(vcpu)->rflags = rflags;
1639 return to_vmx(vcpu)->rflags;
1642 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1644 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1645 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1646 to_vmx(vcpu)->rflags = rflags;
1647 if (to_vmx(vcpu)->rmode.vm86_active) {
1648 to_vmx(vcpu)->rmode.save_rflags = rflags;
1649 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1651 vmcs_writel(GUEST_RFLAGS, rflags);
1654 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1656 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1659 if (interruptibility & GUEST_INTR_STATE_STI)
1660 ret |= KVM_X86_SHADOW_INT_STI;
1661 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1662 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1667 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1669 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1670 u32 interruptibility = interruptibility_old;
1672 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1674 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1675 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1676 else if (mask & KVM_X86_SHADOW_INT_STI)
1677 interruptibility |= GUEST_INTR_STATE_STI;
1679 if ((interruptibility != interruptibility_old))
1680 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1683 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1687 rip = kvm_rip_read(vcpu);
1688 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1689 kvm_rip_write(vcpu, rip);
1691 /* skipping an emulated instruction also counts */
1692 vmx_set_interrupt_shadow(vcpu, 0);
1696 * KVM wants to inject page-faults which it got to the guest. This function
1697 * checks whether in a nested guest, we need to inject them to L1 or L2.
1698 * This function assumes it is called with the exit reason in vmcs02 being
1699 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1702 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1704 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1706 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1707 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
1710 nested_vmx_vmexit(vcpu);
1714 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1715 bool has_error_code, u32 error_code,
1718 struct vcpu_vmx *vmx = to_vmx(vcpu);
1719 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1721 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1722 nested_pf_handled(vcpu))
1725 if (has_error_code) {
1726 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1727 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1730 if (vmx->rmode.vm86_active) {
1732 if (kvm_exception_is_soft(nr))
1733 inc_eip = vcpu->arch.event_exit_inst_len;
1734 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1735 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1739 if (kvm_exception_is_soft(nr)) {
1740 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1741 vmx->vcpu.arch.event_exit_inst_len);
1742 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1744 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1746 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1749 static bool vmx_rdtscp_supported(void)
1751 return cpu_has_vmx_rdtscp();
1755 * Swap MSR entry in host/guest MSR entry array.
1757 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1759 struct shared_msr_entry tmp;
1761 tmp = vmx->guest_msrs[to];
1762 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1763 vmx->guest_msrs[from] = tmp;
1767 * Set up the vmcs to automatically save and restore system
1768 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1769 * mode, as fiddling with msrs is very expensive.
1771 static void setup_msrs(struct vcpu_vmx *vmx)
1773 int save_nmsrs, index;
1774 unsigned long *msr_bitmap;
1777 #ifdef CONFIG_X86_64
1778 if (is_long_mode(&vmx->vcpu)) {
1779 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1781 move_msr_up(vmx, index, save_nmsrs++);
1782 index = __find_msr_index(vmx, MSR_LSTAR);
1784 move_msr_up(vmx, index, save_nmsrs++);
1785 index = __find_msr_index(vmx, MSR_CSTAR);
1787 move_msr_up(vmx, index, save_nmsrs++);
1788 index = __find_msr_index(vmx, MSR_TSC_AUX);
1789 if (index >= 0 && vmx->rdtscp_enabled)
1790 move_msr_up(vmx, index, save_nmsrs++);
1792 * MSR_STAR is only needed on long mode guests, and only
1793 * if efer.sce is enabled.
1795 index = __find_msr_index(vmx, MSR_STAR);
1796 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1797 move_msr_up(vmx, index, save_nmsrs++);
1800 index = __find_msr_index(vmx, MSR_EFER);
1801 if (index >= 0 && update_transition_efer(vmx, index))
1802 move_msr_up(vmx, index, save_nmsrs++);
1804 vmx->save_nmsrs = save_nmsrs;
1806 if (cpu_has_vmx_msr_bitmap()) {
1807 if (is_long_mode(&vmx->vcpu))
1808 msr_bitmap = vmx_msr_bitmap_longmode;
1810 msr_bitmap = vmx_msr_bitmap_legacy;
1812 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1817 * reads and returns guest's timestamp counter "register"
1818 * guest_tsc = host_tsc + tsc_offset -- 21.3
1820 static u64 guest_read_tsc(void)
1822 u64 host_tsc, tsc_offset;
1825 tsc_offset = vmcs_read64(TSC_OFFSET);
1826 return host_tsc + tsc_offset;
1830 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1831 * counter, even if a nested guest (L2) is currently running.
1833 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu)
1835 u64 host_tsc, tsc_offset;
1838 tsc_offset = is_guest_mode(vcpu) ?
1839 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1840 vmcs_read64(TSC_OFFSET);
1841 return host_tsc + tsc_offset;
1845 * Engage any workarounds for mis-matched TSC rates. Currently limited to
1846 * software catchup for faster rates on slower CPUs.
1848 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1853 if (user_tsc_khz > tsc_khz) {
1854 vcpu->arch.tsc_catchup = 1;
1855 vcpu->arch.tsc_always_catchup = 1;
1857 WARN(1, "user requested TSC rate below hardware speed\n");
1861 * writes 'offset' into guest's timestamp counter offset register
1863 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1865 if (is_guest_mode(vcpu)) {
1867 * We're here if L1 chose not to trap WRMSR to TSC. According
1868 * to the spec, this should set L1's TSC; The offset that L1
1869 * set for L2 remains unchanged, and still needs to be added
1870 * to the newly set TSC to get L2's TSC.
1872 struct vmcs12 *vmcs12;
1873 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1874 /* recalculate vmcs02.TSC_OFFSET: */
1875 vmcs12 = get_vmcs12(vcpu);
1876 vmcs_write64(TSC_OFFSET, offset +
1877 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1878 vmcs12->tsc_offset : 0));
1880 vmcs_write64(TSC_OFFSET, offset);
1884 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1886 u64 offset = vmcs_read64(TSC_OFFSET);
1887 vmcs_write64(TSC_OFFSET, offset + adjustment);
1888 if (is_guest_mode(vcpu)) {
1889 /* Even when running L2, the adjustment needs to apply to L1 */
1890 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1894 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1896 return target_tsc - native_read_tsc();
1899 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1901 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1902 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1906 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1907 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1908 * all guests if the "nested" module option is off, and can also be disabled
1909 * for a single guest by disabling its VMX cpuid bit.
1911 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1913 return nested && guest_cpuid_has_vmx(vcpu);
1917 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1918 * returned for the various VMX controls MSRs when nested VMX is enabled.
1919 * The same values should also be used to verify that vmcs12 control fields are
1920 * valid during nested entry from L1 to L2.
1921 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1922 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1923 * bit in the high half is on if the corresponding bit in the control field
1924 * may be on. See also vmx_control_verify().
1925 * TODO: allow these variables to be modified (downgraded) by module options
1928 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1929 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1930 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1931 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1932 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1933 static __init void nested_vmx_setup_ctls_msrs(void)
1936 * Note that as a general rule, the high half of the MSRs (bits in
1937 * the control fields which may be 1) should be initialized by the
1938 * intersection of the underlying hardware's MSR (i.e., features which
1939 * can be supported) and the list of features we want to expose -
1940 * because they are known to be properly supported in our code.
1941 * Also, usually, the low half of the MSRs (bits which must be 1) can
1942 * be set to 0, meaning that L1 may turn off any of these bits. The
1943 * reason is that if one of these bits is necessary, it will appear
1944 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1945 * fields of vmcs01 and vmcs02, will turn these bits off - and
1946 * nested_vmx_exit_handled() will not pass related exits to L1.
1947 * These rules have exceptions below.
1950 /* pin-based controls */
1952 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1953 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1955 nested_vmx_pinbased_ctls_low = 0x16 ;
1956 nested_vmx_pinbased_ctls_high = 0x16 |
1957 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1958 PIN_BASED_VIRTUAL_NMIS;
1961 nested_vmx_exit_ctls_low = 0;
1962 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
1963 #ifdef CONFIG_X86_64
1964 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1966 nested_vmx_exit_ctls_high = 0;
1969 /* entry controls */
1970 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1971 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1972 nested_vmx_entry_ctls_low = 0;
1973 nested_vmx_entry_ctls_high &=
1974 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1976 /* cpu-based controls */
1977 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1978 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1979 nested_vmx_procbased_ctls_low = 0;
1980 nested_vmx_procbased_ctls_high &=
1981 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1982 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1983 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1984 CPU_BASED_CR3_STORE_EXITING |
1985 #ifdef CONFIG_X86_64
1986 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1988 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1989 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1990 CPU_BASED_RDPMC_EXITING |
1991 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1993 * We can allow some features even when not supported by the
1994 * hardware. For example, L1 can specify an MSR bitmap - and we
1995 * can use it to avoid exits to L1 - even when L0 runs L2
1996 * without MSR bitmaps.
1998 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2000 /* secondary cpu-based controls */
2001 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2002 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2003 nested_vmx_secondary_ctls_low = 0;
2004 nested_vmx_secondary_ctls_high &=
2005 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2008 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2011 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2013 return ((control & high) | low) == control;
2016 static inline u64 vmx_control_msr(u32 low, u32 high)
2018 return low | ((u64)high << 32);
2022 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2023 * also let it use VMX-specific MSRs.
2024 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2025 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2026 * like all other MSRs).
2028 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2030 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2031 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2033 * According to the spec, processors which do not support VMX
2034 * should throw a #GP(0) when VMX capability MSRs are read.
2036 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2040 switch (msr_index) {
2041 case MSR_IA32_FEATURE_CONTROL:
2044 case MSR_IA32_VMX_BASIC:
2046 * This MSR reports some information about VMX support. We
2047 * should return information about the VMX we emulate for the
2048 * guest, and the VMCS structure we give it - not about the
2049 * VMX support of the underlying hardware.
2051 *pdata = VMCS12_REVISION |
2052 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2053 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2055 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2056 case MSR_IA32_VMX_PINBASED_CTLS:
2057 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2058 nested_vmx_pinbased_ctls_high);
2060 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2061 case MSR_IA32_VMX_PROCBASED_CTLS:
2062 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2063 nested_vmx_procbased_ctls_high);
2065 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2066 case MSR_IA32_VMX_EXIT_CTLS:
2067 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2068 nested_vmx_exit_ctls_high);
2070 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2071 case MSR_IA32_VMX_ENTRY_CTLS:
2072 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2073 nested_vmx_entry_ctls_high);
2075 case MSR_IA32_VMX_MISC:
2079 * These MSRs specify bits which the guest must keep fixed (on or off)
2080 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2081 * We picked the standard core2 setting.
2083 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2084 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2085 case MSR_IA32_VMX_CR0_FIXED0:
2086 *pdata = VMXON_CR0_ALWAYSON;
2088 case MSR_IA32_VMX_CR0_FIXED1:
2091 case MSR_IA32_VMX_CR4_FIXED0:
2092 *pdata = VMXON_CR4_ALWAYSON;
2094 case MSR_IA32_VMX_CR4_FIXED1:
2097 case MSR_IA32_VMX_VMCS_ENUM:
2100 case MSR_IA32_VMX_PROCBASED_CTLS2:
2101 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2102 nested_vmx_secondary_ctls_high);
2104 case MSR_IA32_VMX_EPT_VPID_CAP:
2105 /* Currently, no nested ept or nested vpid */
2115 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2117 if (!nested_vmx_allowed(vcpu))
2120 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2121 /* TODO: the right thing. */
2124 * No need to treat VMX capability MSRs specially: If we don't handle
2125 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2131 * Reads an msr value (of 'msr_index') into 'pdata'.
2132 * Returns 0 on success, non-0 otherwise.
2133 * Assumes vcpu_load() was already called.
2135 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2138 struct shared_msr_entry *msr;
2141 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2145 switch (msr_index) {
2146 #ifdef CONFIG_X86_64
2148 data = vmcs_readl(GUEST_FS_BASE);
2151 data = vmcs_readl(GUEST_GS_BASE);
2153 case MSR_KERNEL_GS_BASE:
2154 vmx_load_host_state(to_vmx(vcpu));
2155 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2159 return kvm_get_msr_common(vcpu, msr_index, pdata);
2161 data = guest_read_tsc();
2163 case MSR_IA32_SYSENTER_CS:
2164 data = vmcs_read32(GUEST_SYSENTER_CS);
2166 case MSR_IA32_SYSENTER_EIP:
2167 data = vmcs_readl(GUEST_SYSENTER_EIP);
2169 case MSR_IA32_SYSENTER_ESP:
2170 data = vmcs_readl(GUEST_SYSENTER_ESP);
2173 if (!to_vmx(vcpu)->rdtscp_enabled)
2175 /* Otherwise falls through */
2177 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2179 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2184 return kvm_get_msr_common(vcpu, msr_index, pdata);
2192 * Writes msr value into into the appropriate "register".
2193 * Returns 0 on success, non-0 otherwise.
2194 * Assumes vcpu_load() was already called.
2196 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2198 struct vcpu_vmx *vmx = to_vmx(vcpu);
2199 struct shared_msr_entry *msr;
2202 switch (msr_index) {
2204 ret = kvm_set_msr_common(vcpu, msr_index, data);
2206 #ifdef CONFIG_X86_64
2208 vmx_segment_cache_clear(vmx);
2209 vmcs_writel(GUEST_FS_BASE, data);
2212 vmx_segment_cache_clear(vmx);
2213 vmcs_writel(GUEST_GS_BASE, data);
2215 case MSR_KERNEL_GS_BASE:
2216 vmx_load_host_state(vmx);
2217 vmx->msr_guest_kernel_gs_base = data;
2220 case MSR_IA32_SYSENTER_CS:
2221 vmcs_write32(GUEST_SYSENTER_CS, data);
2223 case MSR_IA32_SYSENTER_EIP:
2224 vmcs_writel(GUEST_SYSENTER_EIP, data);
2226 case MSR_IA32_SYSENTER_ESP:
2227 vmcs_writel(GUEST_SYSENTER_ESP, data);
2230 kvm_write_tsc(vcpu, data);
2232 case MSR_IA32_CR_PAT:
2233 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2234 vmcs_write64(GUEST_IA32_PAT, data);
2235 vcpu->arch.pat = data;
2238 ret = kvm_set_msr_common(vcpu, msr_index, data);
2241 if (!vmx->rdtscp_enabled)
2243 /* Check reserved bit, higher 32 bits should be zero */
2244 if ((data >> 32) != 0)
2246 /* Otherwise falls through */
2248 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2250 msr = find_msr_entry(vmx, msr_index);
2253 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2255 kvm_set_shared_msr(msr->index, msr->data,
2261 ret = kvm_set_msr_common(vcpu, msr_index, data);
2267 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2269 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2272 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2275 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2277 case VCPU_EXREG_PDPTR:
2279 ept_save_pdptrs(vcpu);
2286 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
2288 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2289 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2291 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2293 update_exception_bitmap(vcpu);
2296 static __init int cpu_has_kvm_support(void)
2298 return cpu_has_vmx();
2301 static __init int vmx_disabled_by_bios(void)
2305 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2306 if (msr & FEATURE_CONTROL_LOCKED) {
2307 /* launched w/ TXT and VMX disabled */
2308 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2311 /* launched w/o TXT and VMX only enabled w/ TXT */
2312 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2313 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2314 && !tboot_enabled()) {
2315 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2316 "activate TXT before enabling KVM\n");
2319 /* launched w/o TXT and VMX disabled */
2320 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2321 && !tboot_enabled())
2328 static void kvm_cpu_vmxon(u64 addr)
2330 asm volatile (ASM_VMX_VMXON_RAX
2331 : : "a"(&addr), "m"(addr)
2335 static int hardware_enable(void *garbage)
2337 int cpu = raw_smp_processor_id();
2338 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2341 if (read_cr4() & X86_CR4_VMXE)
2344 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2345 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2347 test_bits = FEATURE_CONTROL_LOCKED;
2348 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2349 if (tboot_enabled())
2350 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2352 if ((old & test_bits) != test_bits) {
2353 /* enable and lock */
2354 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2356 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2358 if (vmm_exclusive) {
2359 kvm_cpu_vmxon(phys_addr);
2363 store_gdt(&__get_cpu_var(host_gdt));
2368 static void vmclear_local_loaded_vmcss(void)
2370 int cpu = raw_smp_processor_id();
2371 struct loaded_vmcs *v, *n;
2373 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2374 loaded_vmcss_on_cpu_link)
2375 __loaded_vmcs_clear(v);
2379 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2382 static void kvm_cpu_vmxoff(void)
2384 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2387 static void hardware_disable(void *garbage)
2389 if (vmm_exclusive) {
2390 vmclear_local_loaded_vmcss();
2393 write_cr4(read_cr4() & ~X86_CR4_VMXE);
2396 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2397 u32 msr, u32 *result)
2399 u32 vmx_msr_low, vmx_msr_high;
2400 u32 ctl = ctl_min | ctl_opt;
2402 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2404 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2405 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2407 /* Ensure minimum (required) set of control bits are supported. */
2415 static __init bool allow_1_setting(u32 msr, u32 ctl)
2417 u32 vmx_msr_low, vmx_msr_high;
2419 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2420 return vmx_msr_high & ctl;
2423 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2425 u32 vmx_msr_low, vmx_msr_high;
2426 u32 min, opt, min2, opt2;
2427 u32 _pin_based_exec_control = 0;
2428 u32 _cpu_based_exec_control = 0;
2429 u32 _cpu_based_2nd_exec_control = 0;
2430 u32 _vmexit_control = 0;
2431 u32 _vmentry_control = 0;
2433 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2434 opt = PIN_BASED_VIRTUAL_NMIS;
2435 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2436 &_pin_based_exec_control) < 0)
2439 min = CPU_BASED_HLT_EXITING |
2440 #ifdef CONFIG_X86_64
2441 CPU_BASED_CR8_LOAD_EXITING |
2442 CPU_BASED_CR8_STORE_EXITING |
2444 CPU_BASED_CR3_LOAD_EXITING |
2445 CPU_BASED_CR3_STORE_EXITING |
2446 CPU_BASED_USE_IO_BITMAPS |
2447 CPU_BASED_MOV_DR_EXITING |
2448 CPU_BASED_USE_TSC_OFFSETING |
2449 CPU_BASED_MWAIT_EXITING |
2450 CPU_BASED_MONITOR_EXITING |
2451 CPU_BASED_INVLPG_EXITING |
2452 CPU_BASED_RDPMC_EXITING;
2454 opt = CPU_BASED_TPR_SHADOW |
2455 CPU_BASED_USE_MSR_BITMAPS |
2456 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2457 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2458 &_cpu_based_exec_control) < 0)
2460 #ifdef CONFIG_X86_64
2461 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2462 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2463 ~CPU_BASED_CR8_STORE_EXITING;
2465 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2467 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2468 SECONDARY_EXEC_WBINVD_EXITING |
2469 SECONDARY_EXEC_ENABLE_VPID |
2470 SECONDARY_EXEC_ENABLE_EPT |
2471 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2472 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2473 SECONDARY_EXEC_RDTSCP;
2474 if (adjust_vmx_controls(min2, opt2,
2475 MSR_IA32_VMX_PROCBASED_CTLS2,
2476 &_cpu_based_2nd_exec_control) < 0)
2479 #ifndef CONFIG_X86_64
2480 if (!(_cpu_based_2nd_exec_control &
2481 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2482 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2484 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2485 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2487 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2488 CPU_BASED_CR3_STORE_EXITING |
2489 CPU_BASED_INVLPG_EXITING);
2490 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2491 vmx_capability.ept, vmx_capability.vpid);
2495 #ifdef CONFIG_X86_64
2496 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2498 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2499 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2500 &_vmexit_control) < 0)
2504 opt = VM_ENTRY_LOAD_IA32_PAT;
2505 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2506 &_vmentry_control) < 0)
2509 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2511 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2512 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2515 #ifdef CONFIG_X86_64
2516 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2517 if (vmx_msr_high & (1u<<16))
2521 /* Require Write-Back (WB) memory type for VMCS accesses. */
2522 if (((vmx_msr_high >> 18) & 15) != 6)
2525 vmcs_conf->size = vmx_msr_high & 0x1fff;
2526 vmcs_conf->order = get_order(vmcs_config.size);
2527 vmcs_conf->revision_id = vmx_msr_low;
2529 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2530 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2531 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2532 vmcs_conf->vmexit_ctrl = _vmexit_control;
2533 vmcs_conf->vmentry_ctrl = _vmentry_control;
2535 cpu_has_load_ia32_efer =
2536 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2537 VM_ENTRY_LOAD_IA32_EFER)
2538 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2539 VM_EXIT_LOAD_IA32_EFER);
2541 cpu_has_load_perf_global_ctrl =
2542 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2543 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2544 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2545 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2548 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2549 * but due to arrata below it can't be used. Workaround is to use
2550 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2552 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2557 * BC86,AAY89,BD102 (model 44)
2561 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2562 switch (boot_cpu_data.x86_model) {
2568 cpu_has_load_perf_global_ctrl = false;
2569 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2570 "does not work properly. Using workaround\n");
2580 static struct vmcs *alloc_vmcs_cpu(int cpu)
2582 int node = cpu_to_node(cpu);
2586 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2589 vmcs = page_address(pages);
2590 memset(vmcs, 0, vmcs_config.size);
2591 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2595 static struct vmcs *alloc_vmcs(void)
2597 return alloc_vmcs_cpu(raw_smp_processor_id());
2600 static void free_vmcs(struct vmcs *vmcs)
2602 free_pages((unsigned long)vmcs, vmcs_config.order);
2606 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2608 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2610 if (!loaded_vmcs->vmcs)
2612 loaded_vmcs_clear(loaded_vmcs);
2613 free_vmcs(loaded_vmcs->vmcs);
2614 loaded_vmcs->vmcs = NULL;
2617 static void free_kvm_area(void)
2621 for_each_possible_cpu(cpu) {
2622 free_vmcs(per_cpu(vmxarea, cpu));
2623 per_cpu(vmxarea, cpu) = NULL;
2627 static __init int alloc_kvm_area(void)
2631 for_each_possible_cpu(cpu) {
2634 vmcs = alloc_vmcs_cpu(cpu);
2640 per_cpu(vmxarea, cpu) = vmcs;
2645 static __init int hardware_setup(void)
2647 if (setup_vmcs_config(&vmcs_config) < 0)
2650 if (boot_cpu_has(X86_FEATURE_NX))
2651 kvm_enable_efer_bits(EFER_NX);
2653 if (!cpu_has_vmx_vpid())
2656 if (!cpu_has_vmx_ept() ||
2657 !cpu_has_vmx_ept_4levels()) {
2659 enable_unrestricted_guest = 0;
2660 enable_ept_ad_bits = 0;
2663 if (!cpu_has_vmx_ept_ad_bits())
2664 enable_ept_ad_bits = 0;
2666 if (!cpu_has_vmx_unrestricted_guest())
2667 enable_unrestricted_guest = 0;
2669 if (!cpu_has_vmx_flexpriority())
2670 flexpriority_enabled = 0;
2672 if (!cpu_has_vmx_tpr_shadow())
2673 kvm_x86_ops->update_cr8_intercept = NULL;
2675 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2676 kvm_disable_largepages();
2678 if (!cpu_has_vmx_ple())
2682 nested_vmx_setup_ctls_msrs();
2684 return alloc_kvm_area();
2687 static __exit void hardware_unsetup(void)
2692 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2694 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2696 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
2697 vmcs_write16(sf->selector, save->selector);
2698 vmcs_writel(sf->base, save->base);
2699 vmcs_write32(sf->limit, save->limit);
2700 vmcs_write32(sf->ar_bytes, save->ar);
2702 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2704 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2708 static void enter_pmode(struct kvm_vcpu *vcpu)
2710 unsigned long flags;
2711 struct vcpu_vmx *vmx = to_vmx(vcpu);
2713 vmx->emulation_required = 1;
2714 vmx->rmode.vm86_active = 0;
2716 vmx_segment_cache_clear(vmx);
2718 vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
2719 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2720 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2721 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
2723 flags = vmcs_readl(GUEST_RFLAGS);
2724 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2725 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2726 vmcs_writel(GUEST_RFLAGS, flags);
2728 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2729 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2731 update_exception_bitmap(vcpu);
2733 if (emulate_invalid_guest_state)
2736 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2737 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2738 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2739 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
2741 vmx_segment_cache_clear(vmx);
2743 vmcs_write16(GUEST_SS_SELECTOR, 0);
2744 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2746 vmcs_write16(GUEST_CS_SELECTOR,
2747 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2748 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2751 static gva_t rmode_tss_base(struct kvm *kvm)
2753 if (!kvm->arch.tss_addr) {
2754 struct kvm_memslots *slots;
2755 struct kvm_memory_slot *slot;
2758 slots = kvm_memslots(kvm);
2759 slot = id_to_memslot(slots, 0);
2760 base_gfn = slot->base_gfn + slot->npages - 3;
2762 return base_gfn << PAGE_SHIFT;
2764 return kvm->arch.tss_addr;
2767 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2769 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2771 save->selector = vmcs_read16(sf->selector);
2772 save->base = vmcs_readl(sf->base);
2773 save->limit = vmcs_read32(sf->limit);
2774 save->ar = vmcs_read32(sf->ar_bytes);
2775 vmcs_write16(sf->selector, save->base >> 4);
2776 vmcs_write32(sf->base, save->base & 0xffff0);
2777 vmcs_write32(sf->limit, 0xffff);
2778 vmcs_write32(sf->ar_bytes, 0xf3);
2779 if (save->base & 0xf)
2780 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2781 " aligned when entering protected mode (seg=%d)",
2785 static void enter_rmode(struct kvm_vcpu *vcpu)
2787 unsigned long flags;
2788 struct vcpu_vmx *vmx = to_vmx(vcpu);
2789 struct kvm_segment var;
2791 if (enable_unrestricted_guest)
2794 vmx->emulation_required = 1;
2795 vmx->rmode.vm86_active = 1;
2798 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2799 * vcpu. Call it here with phys address pointing 16M below 4G.
2801 if (!vcpu->kvm->arch.tss_addr) {
2802 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2803 "called before entering vcpu\n");
2804 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2805 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2806 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2809 vmx_segment_cache_clear(vmx);
2811 vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
2812 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
2813 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2815 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
2816 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2818 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
2819 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2821 flags = vmcs_readl(GUEST_RFLAGS);
2822 vmx->rmode.save_rflags = flags;
2824 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2826 vmcs_writel(GUEST_RFLAGS, flags);
2827 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2828 update_exception_bitmap(vcpu);
2830 if (emulate_invalid_guest_state)
2831 goto continue_rmode;
2833 vmx_get_segment(vcpu, &var, VCPU_SREG_SS);
2834 vmx_set_segment(vcpu, &var, VCPU_SREG_SS);
2836 vmx_get_segment(vcpu, &var, VCPU_SREG_CS);
2837 vmx_set_segment(vcpu, &var, VCPU_SREG_CS);
2839 vmx_get_segment(vcpu, &var, VCPU_SREG_ES);
2840 vmx_set_segment(vcpu, &var, VCPU_SREG_ES);
2842 vmx_get_segment(vcpu, &var, VCPU_SREG_DS);
2843 vmx_set_segment(vcpu, &var, VCPU_SREG_DS);
2845 vmx_get_segment(vcpu, &var, VCPU_SREG_GS);
2846 vmx_set_segment(vcpu, &var, VCPU_SREG_GS);
2848 vmx_get_segment(vcpu, &var, VCPU_SREG_FS);
2849 vmx_set_segment(vcpu, &var, VCPU_SREG_FS);
2852 kvm_mmu_reset_context(vcpu);
2855 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2857 struct vcpu_vmx *vmx = to_vmx(vcpu);
2858 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2864 * Force kernel_gs_base reloading before EFER changes, as control
2865 * of this msr depends on is_long_mode().
2867 vmx_load_host_state(to_vmx(vcpu));
2868 vcpu->arch.efer = efer;
2869 if (efer & EFER_LMA) {
2870 vmcs_write32(VM_ENTRY_CONTROLS,
2871 vmcs_read32(VM_ENTRY_CONTROLS) |
2872 VM_ENTRY_IA32E_MODE);
2875 vmcs_write32(VM_ENTRY_CONTROLS,
2876 vmcs_read32(VM_ENTRY_CONTROLS) &
2877 ~VM_ENTRY_IA32E_MODE);
2879 msr->data = efer & ~EFER_LME;
2884 #ifdef CONFIG_X86_64
2886 static void enter_lmode(struct kvm_vcpu *vcpu)
2890 vmx_segment_cache_clear(to_vmx(vcpu));
2892 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2893 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2894 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2896 vmcs_write32(GUEST_TR_AR_BYTES,
2897 (guest_tr_ar & ~AR_TYPE_MASK)
2898 | AR_TYPE_BUSY_64_TSS);
2900 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2903 static void exit_lmode(struct kvm_vcpu *vcpu)
2905 vmcs_write32(VM_ENTRY_CONTROLS,
2906 vmcs_read32(VM_ENTRY_CONTROLS)
2907 & ~VM_ENTRY_IA32E_MODE);
2908 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2913 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2915 vpid_sync_context(to_vmx(vcpu));
2917 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2919 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2923 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2925 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2927 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2928 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2931 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2933 if (enable_ept && is_paging(vcpu))
2934 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2935 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2938 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2940 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2942 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2943 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2946 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2948 if (!test_bit(VCPU_EXREG_PDPTR,
2949 (unsigned long *)&vcpu->arch.regs_dirty))
2952 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2953 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2954 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2955 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2956 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
2960 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2962 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2963 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2964 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2965 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2966 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2969 __set_bit(VCPU_EXREG_PDPTR,
2970 (unsigned long *)&vcpu->arch.regs_avail);
2971 __set_bit(VCPU_EXREG_PDPTR,
2972 (unsigned long *)&vcpu->arch.regs_dirty);
2975 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2977 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2979 struct kvm_vcpu *vcpu)
2981 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2982 vmx_decache_cr3(vcpu);
2983 if (!(cr0 & X86_CR0_PG)) {
2984 /* From paging/starting to nonpaging */
2985 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2986 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
2987 (CPU_BASED_CR3_LOAD_EXITING |
2988 CPU_BASED_CR3_STORE_EXITING));
2989 vcpu->arch.cr0 = cr0;
2990 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2991 } else if (!is_paging(vcpu)) {
2992 /* From nonpaging to paging */
2993 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2994 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
2995 ~(CPU_BASED_CR3_LOAD_EXITING |
2996 CPU_BASED_CR3_STORE_EXITING));
2997 vcpu->arch.cr0 = cr0;
2998 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3001 if (!(cr0 & X86_CR0_WP))
3002 *hw_cr0 &= ~X86_CR0_WP;
3005 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3007 struct vcpu_vmx *vmx = to_vmx(vcpu);
3008 unsigned long hw_cr0;
3010 if (enable_unrestricted_guest)
3011 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
3012 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3014 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
3016 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3019 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3022 #ifdef CONFIG_X86_64
3023 if (vcpu->arch.efer & EFER_LME) {
3024 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3026 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3032 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3034 if (!vcpu->fpu_active)
3035 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3037 vmcs_writel(CR0_READ_SHADOW, cr0);
3038 vmcs_writel(GUEST_CR0, hw_cr0);
3039 vcpu->arch.cr0 = cr0;
3040 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3043 static u64 construct_eptp(unsigned long root_hpa)
3047 /* TODO write the value reading from MSR */
3048 eptp = VMX_EPT_DEFAULT_MT |
3049 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3050 if (enable_ept_ad_bits)
3051 eptp |= VMX_EPT_AD_ENABLE_BIT;
3052 eptp |= (root_hpa & PAGE_MASK);
3057 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3059 unsigned long guest_cr3;
3064 eptp = construct_eptp(cr3);
3065 vmcs_write64(EPT_POINTER, eptp);
3066 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3067 vcpu->kvm->arch.ept_identity_map_addr;
3068 ept_load_pdptrs(vcpu);
3071 vmx_flush_tlb(vcpu);
3072 vmcs_writel(GUEST_CR3, guest_cr3);
3075 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3077 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3078 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3080 if (cr4 & X86_CR4_VMXE) {
3082 * To use VMXON (and later other VMX instructions), a guest
3083 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3084 * So basically the check on whether to allow nested VMX
3087 if (!nested_vmx_allowed(vcpu))
3089 } else if (to_vmx(vcpu)->nested.vmxon)
3092 vcpu->arch.cr4 = cr4;
3094 if (!is_paging(vcpu)) {
3095 hw_cr4 &= ~X86_CR4_PAE;
3096 hw_cr4 |= X86_CR4_PSE;
3097 } else if (!(cr4 & X86_CR4_PAE)) {
3098 hw_cr4 &= ~X86_CR4_PAE;
3102 vmcs_writel(CR4_READ_SHADOW, cr4);
3103 vmcs_writel(GUEST_CR4, hw_cr4);
3107 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3108 struct kvm_segment *var, int seg)
3110 struct vcpu_vmx *vmx = to_vmx(vcpu);
3111 struct kvm_save_segment *save;
3114 if (vmx->rmode.vm86_active
3115 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
3116 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
3117 || seg == VCPU_SREG_GS)
3118 && !emulate_invalid_guest_state) {
3120 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
3121 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
3122 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
3123 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
3124 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
3127 var->selector = save->selector;
3128 var->base = save->base;
3129 var->limit = save->limit;
3131 if (seg == VCPU_SREG_TR
3132 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3133 goto use_saved_rmode_seg;
3135 var->base = vmx_read_guest_seg_base(vmx, seg);
3136 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3137 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3138 ar = vmx_read_guest_seg_ar(vmx, seg);
3139 use_saved_rmode_seg:
3140 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
3142 var->type = ar & 15;
3143 var->s = (ar >> 4) & 1;
3144 var->dpl = (ar >> 5) & 3;
3145 var->present = (ar >> 7) & 1;
3146 var->avl = (ar >> 12) & 1;
3147 var->l = (ar >> 13) & 1;
3148 var->db = (ar >> 14) & 1;
3149 var->g = (ar >> 15) & 1;
3150 var->unusable = (ar >> 16) & 1;
3153 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3155 struct kvm_segment s;
3157 if (to_vmx(vcpu)->rmode.vm86_active) {
3158 vmx_get_segment(vcpu, &s, seg);
3161 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3164 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
3166 if (!is_protmode(vcpu))
3169 if (!is_long_mode(vcpu)
3170 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3173 return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
3176 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3178 struct vcpu_vmx *vmx = to_vmx(vcpu);
3181 * If we enter real mode with cs.sel & 3 != 0, the normal CPL calculations
3182 * fail; use the cache instead.
3184 if (unlikely(vmx->emulation_required && emulate_invalid_guest_state)) {
3188 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3189 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3190 vmx->cpl = __vmx_get_cpl(vcpu);
3197 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3201 if (var->unusable || !var->present)
3204 ar = var->type & 15;
3205 ar |= (var->s & 1) << 4;
3206 ar |= (var->dpl & 3) << 5;
3207 ar |= (var->present & 1) << 7;
3208 ar |= (var->avl & 1) << 12;
3209 ar |= (var->l & 1) << 13;
3210 ar |= (var->db & 1) << 14;
3211 ar |= (var->g & 1) << 15;
3217 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3218 struct kvm_segment *var, int seg)
3220 struct vcpu_vmx *vmx = to_vmx(vcpu);
3221 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3224 vmx_segment_cache_clear(vmx);
3226 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
3227 vmcs_write16(sf->selector, var->selector);
3228 vmx->rmode.tr.selector = var->selector;
3229 vmx->rmode.tr.base = var->base;
3230 vmx->rmode.tr.limit = var->limit;
3231 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
3234 vmcs_writel(sf->base, var->base);
3235 vmcs_write32(sf->limit, var->limit);
3236 vmcs_write16(sf->selector, var->selector);
3237 if (vmx->rmode.vm86_active && var->s) {
3239 * Hack real-mode segments into vm86 compatibility.
3241 if (var->base == 0xffff0000 && var->selector == 0xf000)
3242 vmcs_writel(sf->base, 0xf0000);
3245 ar = vmx_segment_access_rights(var);
3248 * Fix the "Accessed" bit in AR field of segment registers for older
3250 * IA32 arch specifies that at the time of processor reset the
3251 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3252 * is setting it to 0 in the usedland code. This causes invalid guest
3253 * state vmexit when "unrestricted guest" mode is turned on.
3254 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3255 * tree. Newer qemu binaries with that qemu fix would not need this
3258 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3259 ar |= 0x1; /* Accessed */
3261 vmcs_write32(sf->ar_bytes, ar);
3262 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3265 * Fix segments for real mode guest in hosts that don't have
3266 * "unrestricted_mode" or it was disabled.
3267 * This is done to allow migration of the guests from hosts with
3268 * unrestricted guest like Westmere to older host that don't have
3269 * unrestricted guest like Nehelem.
3271 if (!enable_unrestricted_guest && vmx->rmode.vm86_active) {
3274 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
3275 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
3276 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
3277 vmcs_writel(GUEST_CS_BASE, 0xf0000);
3278 vmcs_write16(GUEST_CS_SELECTOR,
3279 vmcs_readl(GUEST_CS_BASE) >> 4);
3282 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
3285 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
3288 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
3291 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
3294 vmcs_write16(GUEST_SS_SELECTOR,
3295 vmcs_readl(GUEST_SS_BASE) >> 4);
3296 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
3297 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
3303 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3305 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3307 *db = (ar >> 14) & 1;
3308 *l = (ar >> 13) & 1;
3311 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3313 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3314 dt->address = vmcs_readl(GUEST_IDTR_BASE);
3317 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3319 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3320 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3323 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3325 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3326 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3329 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3331 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3332 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3335 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3337 struct kvm_segment var;
3340 vmx_get_segment(vcpu, &var, seg);
3341 ar = vmx_segment_access_rights(&var);
3343 if (var.base != (var.selector << 4))
3345 if (var.limit != 0xffff)
3353 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3355 struct kvm_segment cs;
3356 unsigned int cs_rpl;
3358 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3359 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3363 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3367 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3368 if (cs.dpl > cs_rpl)
3371 if (cs.dpl != cs_rpl)
3377 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3381 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3383 struct kvm_segment ss;
3384 unsigned int ss_rpl;
3386 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3387 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3391 if (ss.type != 3 && ss.type != 7)
3395 if (ss.dpl != ss_rpl) /* DPL != RPL */
3403 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3405 struct kvm_segment var;
3408 vmx_get_segment(vcpu, &var, seg);
3409 rpl = var.selector & SELECTOR_RPL_MASK;
3417 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3418 if (var.dpl < rpl) /* DPL < RPL */
3422 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3428 static bool tr_valid(struct kvm_vcpu *vcpu)
3430 struct kvm_segment tr;
3432 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3436 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3438 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3446 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3448 struct kvm_segment ldtr;
3450 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3454 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3464 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3466 struct kvm_segment cs, ss;
3468 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3469 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3471 return ((cs.selector & SELECTOR_RPL_MASK) ==
3472 (ss.selector & SELECTOR_RPL_MASK));
3476 * Check if guest state is valid. Returns true if valid, false if
3478 * We assume that registers are always usable
3480 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3482 /* real mode guest state checks */
3483 if (!is_protmode(vcpu)) {
3484 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3486 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3488 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3490 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3492 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3494 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3497 /* protected mode guest state checks */
3498 if (!cs_ss_rpl_check(vcpu))
3500 if (!code_segment_valid(vcpu))
3502 if (!stack_segment_valid(vcpu))
3504 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3506 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3508 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3510 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3512 if (!tr_valid(vcpu))
3514 if (!ldtr_valid(vcpu))
3518 * - Add checks on RIP
3519 * - Add checks on RFLAGS
3525 static int init_rmode_tss(struct kvm *kvm)
3529 int r, idx, ret = 0;
3531 idx = srcu_read_lock(&kvm->srcu);
3532 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3533 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3536 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3537 r = kvm_write_guest_page(kvm, fn++, &data,
3538 TSS_IOPB_BASE_OFFSET, sizeof(u16));
3541 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3544 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3548 r = kvm_write_guest_page(kvm, fn, &data,
3549 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3556 srcu_read_unlock(&kvm->srcu, idx);
3560 static int init_rmode_identity_map(struct kvm *kvm)
3563 pfn_t identity_map_pfn;
3568 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3569 printk(KERN_ERR "EPT: identity-mapping pagetable "
3570 "haven't been allocated!\n");
3573 if (likely(kvm->arch.ept_identity_pagetable_done))
3576 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3577 idx = srcu_read_lock(&kvm->srcu);
3578 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3581 /* Set up identity-mapping pagetable for EPT in real mode */
3582 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3583 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3584 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3585 r = kvm_write_guest_page(kvm, identity_map_pfn,
3586 &tmp, i * sizeof(tmp), sizeof(tmp));
3590 kvm->arch.ept_identity_pagetable_done = true;
3593 srcu_read_unlock(&kvm->srcu, idx);
3597 static void seg_setup(int seg)
3599 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3602 vmcs_write16(sf->selector, 0);
3603 vmcs_writel(sf->base, 0);
3604 vmcs_write32(sf->limit, 0xffff);
3605 if (enable_unrestricted_guest) {
3607 if (seg == VCPU_SREG_CS)
3608 ar |= 0x08; /* code segment */
3612 vmcs_write32(sf->ar_bytes, ar);
3615 static int alloc_apic_access_page(struct kvm *kvm)
3617 struct kvm_userspace_memory_region kvm_userspace_mem;
3620 mutex_lock(&kvm->slots_lock);
3621 if (kvm->arch.apic_access_page)
3623 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3624 kvm_userspace_mem.flags = 0;
3625 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3626 kvm_userspace_mem.memory_size = PAGE_SIZE;
3627 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3631 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
3633 mutex_unlock(&kvm->slots_lock);
3637 static int alloc_identity_pagetable(struct kvm *kvm)
3639 struct kvm_userspace_memory_region kvm_userspace_mem;
3642 mutex_lock(&kvm->slots_lock);
3643 if (kvm->arch.ept_identity_pagetable)
3645 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3646 kvm_userspace_mem.flags = 0;
3647 kvm_userspace_mem.guest_phys_addr =
3648 kvm->arch.ept_identity_map_addr;
3649 kvm_userspace_mem.memory_size = PAGE_SIZE;
3650 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3654 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
3655 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3657 mutex_unlock(&kvm->slots_lock);
3661 static void allocate_vpid(struct vcpu_vmx *vmx)
3668 spin_lock(&vmx_vpid_lock);
3669 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3670 if (vpid < VMX_NR_VPIDS) {
3672 __set_bit(vpid, vmx_vpid_bitmap);
3674 spin_unlock(&vmx_vpid_lock);
3677 static void free_vpid(struct vcpu_vmx *vmx)
3681 spin_lock(&vmx_vpid_lock);
3683 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3684 spin_unlock(&vmx_vpid_lock);
3687 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
3689 int f = sizeof(unsigned long);
3691 if (!cpu_has_vmx_msr_bitmap())
3695 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3696 * have the write-low and read-high bitmap offsets the wrong way round.
3697 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3699 if (msr <= 0x1fff) {
3700 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3701 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
3702 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3704 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3705 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
3709 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3712 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3713 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3717 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3718 * will not change in the lifetime of the guest.
3719 * Note that host-state that does change is set elsewhere. E.g., host-state
3720 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3722 static void vmx_set_constant_host_state(void)
3728 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
3729 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3730 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3732 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
3733 #ifdef CONFIG_X86_64
3735 * Load null selectors, so we can avoid reloading them in
3736 * __vmx_load_host_state(), in case userspace uses the null selectors
3737 * too (the expected case).
3739 vmcs_write16(HOST_DS_SELECTOR, 0);
3740 vmcs_write16(HOST_ES_SELECTOR, 0);
3742 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3743 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3745 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3746 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3748 native_store_idt(&dt);
3749 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3751 asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3752 vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3754 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3755 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3756 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3757 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3759 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3760 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3761 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3765 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3767 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3769 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3770 if (is_guest_mode(&vmx->vcpu))
3771 vmx->vcpu.arch.cr4_guest_owned_bits &=
3772 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3773 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3776 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3778 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3779 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3780 exec_control &= ~CPU_BASED_TPR_SHADOW;
3781 #ifdef CONFIG_X86_64
3782 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3783 CPU_BASED_CR8_LOAD_EXITING;
3787 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3788 CPU_BASED_CR3_LOAD_EXITING |
3789 CPU_BASED_INVLPG_EXITING;
3790 return exec_control;
3793 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3795 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3796 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3797 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3799 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3801 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3802 enable_unrestricted_guest = 0;
3804 if (!enable_unrestricted_guest)
3805 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3807 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3808 return exec_control;
3811 static void ept_set_mmio_spte_mask(void)
3814 * EPT Misconfigurations can be generated if the value of bits 2:0
3815 * of an EPT paging-structure entry is 110b (write/execute).
3816 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3819 kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3823 * Sets up the vmcs for emulated real mode.
3825 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
3827 #ifdef CONFIG_X86_64
3833 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3834 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
3836 if (cpu_has_vmx_msr_bitmap())
3837 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
3839 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3842 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3843 vmcs_config.pin_based_exec_ctrl);
3845 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
3847 if (cpu_has_secondary_exec_ctrls()) {
3848 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3849 vmx_secondary_exec_control(vmx));
3853 vmcs_write32(PLE_GAP, ple_gap);
3854 vmcs_write32(PLE_WINDOW, ple_window);
3857 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3858 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
3859 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
3861 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
3862 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
3863 vmx_set_constant_host_state();
3864 #ifdef CONFIG_X86_64
3865 rdmsrl(MSR_FS_BASE, a);
3866 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3867 rdmsrl(MSR_GS_BASE, a);
3868 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3870 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3871 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3874 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3875 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
3876 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
3877 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
3878 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
3880 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3881 u32 msr_low, msr_high;
3883 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3884 host_pat = msr_low | ((u64) msr_high << 32);
3885 /* Write the default value follow host pat */
3886 vmcs_write64(GUEST_IA32_PAT, host_pat);
3887 /* Keep arch.pat sync with GUEST_IA32_PAT */
3888 vmx->vcpu.arch.pat = host_pat;
3891 for (i = 0; i < NR_VMX_MSR; ++i) {
3892 u32 index = vmx_msr_index[i];
3893 u32 data_low, data_high;
3896 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3898 if (wrmsr_safe(index, data_low, data_high) < 0)
3900 vmx->guest_msrs[j].index = i;
3901 vmx->guest_msrs[j].data = 0;
3902 vmx->guest_msrs[j].mask = -1ull;
3906 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
3908 /* 22.2.1, 20.8.1 */
3909 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3911 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
3912 set_cr4_guest_host_mask(vmx);
3914 kvm_write_tsc(&vmx->vcpu, 0);
3919 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3921 struct vcpu_vmx *vmx = to_vmx(vcpu);
3925 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3927 vmx->rmode.vm86_active = 0;
3929 vmx->soft_vnmi_blocked = 0;
3931 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
3932 kvm_set_cr8(&vmx->vcpu, 0);
3933 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
3934 if (kvm_vcpu_is_bsp(&vmx->vcpu))
3935 msr |= MSR_IA32_APICBASE_BSP;
3936 kvm_set_apic_base(&vmx->vcpu, msr);
3938 ret = fx_init(&vmx->vcpu);
3942 vmx_segment_cache_clear(vmx);
3944 seg_setup(VCPU_SREG_CS);
3946 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3947 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3949 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
3950 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3951 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3953 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3954 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
3957 seg_setup(VCPU_SREG_DS);
3958 seg_setup(VCPU_SREG_ES);
3959 seg_setup(VCPU_SREG_FS);
3960 seg_setup(VCPU_SREG_GS);
3961 seg_setup(VCPU_SREG_SS);
3963 vmcs_write16(GUEST_TR_SELECTOR, 0);
3964 vmcs_writel(GUEST_TR_BASE, 0);
3965 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3966 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3968 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3969 vmcs_writel(GUEST_LDTR_BASE, 0);
3970 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3971 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3973 vmcs_write32(GUEST_SYSENTER_CS, 0);
3974 vmcs_writel(GUEST_SYSENTER_ESP, 0);
3975 vmcs_writel(GUEST_SYSENTER_EIP, 0);
3977 vmcs_writel(GUEST_RFLAGS, 0x02);
3978 if (kvm_vcpu_is_bsp(&vmx->vcpu))
3979 kvm_rip_write(vcpu, 0xfff0);
3981 kvm_rip_write(vcpu, 0);
3982 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
3984 vmcs_writel(GUEST_DR7, 0x400);
3986 vmcs_writel(GUEST_GDTR_BASE, 0);
3987 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3989 vmcs_writel(GUEST_IDTR_BASE, 0);
3990 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3992 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3993 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3994 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3996 /* Special registers */
3997 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4001 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4003 if (cpu_has_vmx_tpr_shadow()) {
4004 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4005 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4006 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4007 __pa(vmx->vcpu.arch.apic->regs));
4008 vmcs_write32(TPR_THRESHOLD, 0);
4011 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4012 vmcs_write64(APIC_ACCESS_ADDR,
4013 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
4016 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4018 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4019 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
4020 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4021 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
4022 vmx_set_cr4(&vmx->vcpu, 0);
4023 vmx_set_efer(&vmx->vcpu, 0);
4024 vmx_fpu_activate(&vmx->vcpu);
4025 update_exception_bitmap(&vmx->vcpu);
4027 vpid_sync_context(vmx);
4031 /* HACK: Don't enable emulation on guest boot/reset */
4032 vmx->emulation_required = 0;
4039 * In nested virtualization, check if L1 asked to exit on external interrupts.
4040 * For most existing hypervisors, this will always return true.
4042 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4044 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4045 PIN_BASED_EXT_INTR_MASK;
4048 static void enable_irq_window(struct kvm_vcpu *vcpu)
4050 u32 cpu_based_vm_exec_control;
4051 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4053 * We get here if vmx_interrupt_allowed() said we can't
4054 * inject to L1 now because L2 must run. Ask L2 to exit
4055 * right after entry, so we can inject to L1 more promptly.
4057 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
4061 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4062 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4063 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4066 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4068 u32 cpu_based_vm_exec_control;
4070 if (!cpu_has_virtual_nmis()) {
4071 enable_irq_window(vcpu);
4075 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4076 enable_irq_window(vcpu);
4079 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4080 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4081 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4084 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4086 struct vcpu_vmx *vmx = to_vmx(vcpu);
4088 int irq = vcpu->arch.interrupt.nr;
4090 trace_kvm_inj_virq(irq);
4092 ++vcpu->stat.irq_injections;
4093 if (vmx->rmode.vm86_active) {
4095 if (vcpu->arch.interrupt.soft)
4096 inc_eip = vcpu->arch.event_exit_inst_len;
4097 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4098 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4101 intr = irq | INTR_INFO_VALID_MASK;
4102 if (vcpu->arch.interrupt.soft) {
4103 intr |= INTR_TYPE_SOFT_INTR;
4104 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4105 vmx->vcpu.arch.event_exit_inst_len);
4107 intr |= INTR_TYPE_EXT_INTR;
4108 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4111 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4113 struct vcpu_vmx *vmx = to_vmx(vcpu);
4115 if (is_guest_mode(vcpu))
4118 if (!cpu_has_virtual_nmis()) {
4120 * Tracking the NMI-blocked state in software is built upon
4121 * finding the next open IRQ window. This, in turn, depends on
4122 * well-behaving guests: They have to keep IRQs disabled at
4123 * least as long as the NMI handler runs. Otherwise we may
4124 * cause NMI nesting, maybe breaking the guest. But as this is
4125 * highly unlikely, we can live with the residual risk.
4127 vmx->soft_vnmi_blocked = 1;
4128 vmx->vnmi_blocked_time = 0;
4131 ++vcpu->stat.nmi_injections;
4132 vmx->nmi_known_unmasked = false;
4133 if (vmx->rmode.vm86_active) {
4134 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4135 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4138 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4139 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4142 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4144 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4147 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4148 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4149 | GUEST_INTR_STATE_NMI));
4152 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4154 if (!cpu_has_virtual_nmis())
4155 return to_vmx(vcpu)->soft_vnmi_blocked;
4156 if (to_vmx(vcpu)->nmi_known_unmasked)
4158 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4161 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4163 struct vcpu_vmx *vmx = to_vmx(vcpu);
4165 if (!cpu_has_virtual_nmis()) {
4166 if (vmx->soft_vnmi_blocked != masked) {
4167 vmx->soft_vnmi_blocked = masked;
4168 vmx->vnmi_blocked_time = 0;
4171 vmx->nmi_known_unmasked = !masked;
4173 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4174 GUEST_INTR_STATE_NMI);
4176 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4177 GUEST_INTR_STATE_NMI);
4181 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4183 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4184 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4185 if (to_vmx(vcpu)->nested.nested_run_pending ||
4186 (vmcs12->idt_vectoring_info_field &
4187 VECTORING_INFO_VALID_MASK))
4189 nested_vmx_vmexit(vcpu);
4190 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4191 vmcs12->vm_exit_intr_info = 0;
4192 /* fall through to normal code, but now in L1, not L2 */
4195 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4196 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4197 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4200 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4203 struct kvm_userspace_memory_region tss_mem = {
4204 .slot = TSS_PRIVATE_MEMSLOT,
4205 .guest_phys_addr = addr,
4206 .memory_size = PAGE_SIZE * 3,
4210 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
4213 kvm->arch.tss_addr = addr;
4214 if (!init_rmode_tss(kvm))
4220 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4221 int vec, u32 err_code)
4224 * Instruction with address size override prefix opcode 0x67
4225 * Cause the #SS fault with 0 error code in VM86 mode.
4227 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
4228 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
4231 * Forward all other exceptions that are valid in real mode.
4232 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4233 * the required debugging infrastructure rework.
4237 if (vcpu->guest_debug &
4238 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4240 kvm_queue_exception(vcpu, vec);
4244 * Update instruction length as we may reinject the exception
4245 * from user space while in guest debugging mode.
4247 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4248 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4249 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4260 kvm_queue_exception(vcpu, vec);
4267 * Trigger machine check on the host. We assume all the MSRs are already set up
4268 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4269 * We pass a fake environment to the machine check handler because we want
4270 * the guest to be always treated like user space, no matter what context
4271 * it used internally.
4273 static void kvm_machine_check(void)
4275 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4276 struct pt_regs regs = {
4277 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4278 .flags = X86_EFLAGS_IF,
4281 do_machine_check(®s, 0);
4285 static int handle_machine_check(struct kvm_vcpu *vcpu)
4287 /* already handled by vcpu_run */
4291 static int handle_exception(struct kvm_vcpu *vcpu)
4293 struct vcpu_vmx *vmx = to_vmx(vcpu);
4294 struct kvm_run *kvm_run = vcpu->run;
4295 u32 intr_info, ex_no, error_code;
4296 unsigned long cr2, rip, dr6;
4298 enum emulation_result er;
4300 vect_info = vmx->idt_vectoring_info;
4301 intr_info = vmx->exit_intr_info;
4303 if (is_machine_check(intr_info))
4304 return handle_machine_check(vcpu);
4306 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4307 !is_page_fault(intr_info)) {
4308 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4309 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4310 vcpu->run->internal.ndata = 2;
4311 vcpu->run->internal.data[0] = vect_info;
4312 vcpu->run->internal.data[1] = intr_info;
4316 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4317 return 1; /* already handled by vmx_vcpu_run() */
4319 if (is_no_device(intr_info)) {
4320 vmx_fpu_activate(vcpu);
4324 if (is_invalid_opcode(intr_info)) {
4325 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4326 if (er != EMULATE_DONE)
4327 kvm_queue_exception(vcpu, UD_VECTOR);
4332 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4333 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4334 if (is_page_fault(intr_info)) {
4335 /* EPT won't cause page fault directly */
4337 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4338 trace_kvm_page_fault(cr2, error_code);
4340 if (kvm_event_needs_reinjection(vcpu))
4341 kvm_mmu_unprotect_page_virt(vcpu, cr2);
4342 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4345 if (vmx->rmode.vm86_active &&
4346 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
4348 if (vcpu->arch.halt_request) {
4349 vcpu->arch.halt_request = 0;
4350 return kvm_emulate_halt(vcpu);
4355 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4358 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4359 if (!(vcpu->guest_debug &
4360 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4361 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4362 kvm_queue_exception(vcpu, DB_VECTOR);
4365 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4366 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4370 * Update instruction length as we may reinject #BP from
4371 * user space while in guest debugging mode. Reading it for
4372 * #DB as well causes no harm, it is not used in that case.
4374 vmx->vcpu.arch.event_exit_inst_len =
4375 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4376 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4377 rip = kvm_rip_read(vcpu);
4378 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4379 kvm_run->debug.arch.exception = ex_no;
4382 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4383 kvm_run->ex.exception = ex_no;
4384 kvm_run->ex.error_code = error_code;
4390 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4392 ++vcpu->stat.irq_exits;
4396 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4398 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4402 static int handle_io(struct kvm_vcpu *vcpu)
4404 unsigned long exit_qualification;
4405 int size, in, string;
4408 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4409 string = (exit_qualification & 16) != 0;
4410 in = (exit_qualification & 8) != 0;
4412 ++vcpu->stat.io_exits;
4415 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4417 port = exit_qualification >> 16;
4418 size = (exit_qualification & 7) + 1;
4419 skip_emulated_instruction(vcpu);
4421 return kvm_fast_pio_out(vcpu, size, port);
4425 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4428 * Patch in the VMCALL instruction:
4430 hypercall[0] = 0x0f;
4431 hypercall[1] = 0x01;
4432 hypercall[2] = 0xc1;
4435 /* called to set cr0 as approriate for a mov-to-cr0 exit. */
4436 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4438 if (to_vmx(vcpu)->nested.vmxon &&
4439 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4442 if (is_guest_mode(vcpu)) {
4444 * We get here when L2 changed cr0 in a way that did not change
4445 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4446 * but did change L0 shadowed bits. This can currently happen
4447 * with the TS bit: L0 may want to leave TS on (for lazy fpu
4448 * loading) while pretending to allow the guest to change it.
4450 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4451 (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4453 vmcs_writel(CR0_READ_SHADOW, val);
4456 return kvm_set_cr0(vcpu, val);
4459 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4461 if (is_guest_mode(vcpu)) {
4462 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4463 (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4465 vmcs_writel(CR4_READ_SHADOW, val);
4468 return kvm_set_cr4(vcpu, val);
4471 /* called to set cr0 as approriate for clts instruction exit. */
4472 static void handle_clts(struct kvm_vcpu *vcpu)
4474 if (is_guest_mode(vcpu)) {
4476 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4477 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4478 * just pretend it's off (also in arch.cr0 for fpu_activate).
4480 vmcs_writel(CR0_READ_SHADOW,
4481 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4482 vcpu->arch.cr0 &= ~X86_CR0_TS;
4484 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4487 static int handle_cr(struct kvm_vcpu *vcpu)
4489 unsigned long exit_qualification, val;
4494 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4495 cr = exit_qualification & 15;
4496 reg = (exit_qualification >> 8) & 15;
4497 switch ((exit_qualification >> 4) & 3) {
4498 case 0: /* mov to cr */
4499 val = kvm_register_read(vcpu, reg);
4500 trace_kvm_cr_write(cr, val);
4503 err = handle_set_cr0(vcpu, val);
4504 kvm_complete_insn_gp(vcpu, err);
4507 err = kvm_set_cr3(vcpu, val);
4508 kvm_complete_insn_gp(vcpu, err);
4511 err = handle_set_cr4(vcpu, val);
4512 kvm_complete_insn_gp(vcpu, err);
4515 u8 cr8_prev = kvm_get_cr8(vcpu);
4516 u8 cr8 = kvm_register_read(vcpu, reg);
4517 err = kvm_set_cr8(vcpu, cr8);
4518 kvm_complete_insn_gp(vcpu, err);
4519 if (irqchip_in_kernel(vcpu->kvm))
4521 if (cr8_prev <= cr8)
4523 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4530 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4531 skip_emulated_instruction(vcpu);
4532 vmx_fpu_activate(vcpu);
4534 case 1: /*mov from cr*/
4537 val = kvm_read_cr3(vcpu);
4538 kvm_register_write(vcpu, reg, val);
4539 trace_kvm_cr_read(cr, val);
4540 skip_emulated_instruction(vcpu);
4543 val = kvm_get_cr8(vcpu);
4544 kvm_register_write(vcpu, reg, val);
4545 trace_kvm_cr_read(cr, val);
4546 skip_emulated_instruction(vcpu);
4551 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4552 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4553 kvm_lmsw(vcpu, val);
4555 skip_emulated_instruction(vcpu);
4560 vcpu->run->exit_reason = 0;
4561 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4562 (int)(exit_qualification >> 4) & 3, cr);
4566 static int handle_dr(struct kvm_vcpu *vcpu)
4568 unsigned long exit_qualification;
4571 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4572 if (!kvm_require_cpl(vcpu, 0))
4574 dr = vmcs_readl(GUEST_DR7);
4577 * As the vm-exit takes precedence over the debug trap, we
4578 * need to emulate the latter, either for the host or the
4579 * guest debugging itself.
4581 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4582 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4583 vcpu->run->debug.arch.dr7 = dr;
4584 vcpu->run->debug.arch.pc =
4585 vmcs_readl(GUEST_CS_BASE) +
4586 vmcs_readl(GUEST_RIP);
4587 vcpu->run->debug.arch.exception = DB_VECTOR;
4588 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4591 vcpu->arch.dr7 &= ~DR7_GD;
4592 vcpu->arch.dr6 |= DR6_BD;
4593 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4594 kvm_queue_exception(vcpu, DB_VECTOR);
4599 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4600 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4601 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4602 if (exit_qualification & TYPE_MOV_FROM_DR) {
4604 if (!kvm_get_dr(vcpu, dr, &val))
4605 kvm_register_write(vcpu, reg, val);
4607 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4608 skip_emulated_instruction(vcpu);
4612 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4614 vmcs_writel(GUEST_DR7, val);
4617 static int handle_cpuid(struct kvm_vcpu *vcpu)
4619 kvm_emulate_cpuid(vcpu);
4623 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4625 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4628 if (vmx_get_msr(vcpu, ecx, &data)) {
4629 trace_kvm_msr_read_ex(ecx);
4630 kvm_inject_gp(vcpu, 0);
4634 trace_kvm_msr_read(ecx, data);
4636 /* FIXME: handling of bits 32:63 of rax, rdx */
4637 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4638 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4639 skip_emulated_instruction(vcpu);
4643 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4645 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4646 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4647 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4649 if (vmx_set_msr(vcpu, ecx, data) != 0) {
4650 trace_kvm_msr_write_ex(ecx, data);
4651 kvm_inject_gp(vcpu, 0);
4655 trace_kvm_msr_write(ecx, data);
4656 skip_emulated_instruction(vcpu);
4660 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4662 kvm_make_request(KVM_REQ_EVENT, vcpu);
4666 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4668 u32 cpu_based_vm_exec_control;
4670 /* clear pending irq */
4671 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4672 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4673 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4675 kvm_make_request(KVM_REQ_EVENT, vcpu);
4677 ++vcpu->stat.irq_window_exits;
4680 * If the user space waits to inject interrupts, exit as soon as
4683 if (!irqchip_in_kernel(vcpu->kvm) &&
4684 vcpu->run->request_interrupt_window &&
4685 !kvm_cpu_has_interrupt(vcpu)) {
4686 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4692 static int handle_halt(struct kvm_vcpu *vcpu)
4694 skip_emulated_instruction(vcpu);
4695 return kvm_emulate_halt(vcpu);
4698 static int handle_vmcall(struct kvm_vcpu *vcpu)
4700 skip_emulated_instruction(vcpu);
4701 kvm_emulate_hypercall(vcpu);
4705 static int handle_invd(struct kvm_vcpu *vcpu)
4707 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4710 static int handle_invlpg(struct kvm_vcpu *vcpu)
4712 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4714 kvm_mmu_invlpg(vcpu, exit_qualification);
4715 skip_emulated_instruction(vcpu);
4719 static int handle_rdpmc(struct kvm_vcpu *vcpu)
4723 err = kvm_rdpmc(vcpu);
4724 kvm_complete_insn_gp(vcpu, err);
4729 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4731 skip_emulated_instruction(vcpu);
4732 kvm_emulate_wbinvd(vcpu);
4736 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4738 u64 new_bv = kvm_read_edx_eax(vcpu);
4739 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4741 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4742 skip_emulated_instruction(vcpu);
4746 static int handle_apic_access(struct kvm_vcpu *vcpu)
4748 if (likely(fasteoi)) {
4749 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4750 int access_type, offset;
4752 access_type = exit_qualification & APIC_ACCESS_TYPE;
4753 offset = exit_qualification & APIC_ACCESS_OFFSET;
4755 * Sane guest uses MOV to write EOI, with written value
4756 * not cared. So make a short-circuit here by avoiding
4757 * heavy instruction emulation.
4759 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4760 (offset == APIC_EOI)) {
4761 kvm_lapic_set_eoi(vcpu);
4762 skip_emulated_instruction(vcpu);
4766 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4769 static int handle_task_switch(struct kvm_vcpu *vcpu)
4771 struct vcpu_vmx *vmx = to_vmx(vcpu);
4772 unsigned long exit_qualification;
4773 bool has_error_code = false;
4776 int reason, type, idt_v, idt_index;
4778 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4779 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
4780 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
4782 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4784 reason = (u32)exit_qualification >> 30;
4785 if (reason == TASK_SWITCH_GATE && idt_v) {
4787 case INTR_TYPE_NMI_INTR:
4788 vcpu->arch.nmi_injected = false;
4789 vmx_set_nmi_mask(vcpu, true);
4791 case INTR_TYPE_EXT_INTR:
4792 case INTR_TYPE_SOFT_INTR:
4793 kvm_clear_interrupt_queue(vcpu);
4795 case INTR_TYPE_HARD_EXCEPTION:
4796 if (vmx->idt_vectoring_info &
4797 VECTORING_INFO_DELIVER_CODE_MASK) {
4798 has_error_code = true;
4800 vmcs_read32(IDT_VECTORING_ERROR_CODE);
4803 case INTR_TYPE_SOFT_EXCEPTION:
4804 kvm_clear_exception_queue(vcpu);
4810 tss_selector = exit_qualification;
4812 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4813 type != INTR_TYPE_EXT_INTR &&
4814 type != INTR_TYPE_NMI_INTR))
4815 skip_emulated_instruction(vcpu);
4817 if (kvm_task_switch(vcpu, tss_selector,
4818 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
4819 has_error_code, error_code) == EMULATE_FAIL) {
4820 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4821 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4822 vcpu->run->internal.ndata = 0;
4826 /* clear all local breakpoint enable flags */
4827 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4830 * TODO: What about debug traps on tss switch?
4831 * Are we supposed to inject them and update dr6?
4837 static int handle_ept_violation(struct kvm_vcpu *vcpu)
4839 unsigned long exit_qualification;
4843 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4845 if (exit_qualification & (1 << 6)) {
4846 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
4850 gla_validity = (exit_qualification >> 7) & 0x3;
4851 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4852 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4853 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4854 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
4855 vmcs_readl(GUEST_LINEAR_ADDRESS));
4856 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4857 (long unsigned int)exit_qualification);
4858 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4859 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
4863 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4864 trace_kvm_page_fault(gpa, exit_qualification);
4865 return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
4868 static u64 ept_rsvd_mask(u64 spte, int level)
4873 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4874 mask |= (1ULL << i);
4877 /* bits 7:3 reserved */
4879 else if (level == 2) {
4880 if (spte & (1ULL << 7))
4881 /* 2MB ref, bits 20:12 reserved */
4884 /* bits 6:3 reserved */
4891 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4894 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4896 /* 010b (write-only) */
4897 WARN_ON((spte & 0x7) == 0x2);
4899 /* 110b (write/execute) */
4900 WARN_ON((spte & 0x7) == 0x6);
4902 /* 100b (execute-only) and value not supported by logical processor */
4903 if (!cpu_has_vmx_ept_execute_only())
4904 WARN_ON((spte & 0x7) == 0x4);
4908 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4910 if (rsvd_bits != 0) {
4911 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4912 __func__, rsvd_bits);
4916 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4917 u64 ept_mem_type = (spte & 0x38) >> 3;
4919 if (ept_mem_type == 2 || ept_mem_type == 3 ||
4920 ept_mem_type == 7) {
4921 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4922 __func__, ept_mem_type);
4929 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
4932 int nr_sptes, i, ret;
4935 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4937 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4938 if (likely(ret == 1))
4939 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4944 /* It is the real ept misconfig */
4945 printk(KERN_ERR "EPT: Misconfiguration.\n");
4946 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4948 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4950 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4951 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4953 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4954 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
4959 static int handle_nmi_window(struct kvm_vcpu *vcpu)
4961 u32 cpu_based_vm_exec_control;
4963 /* clear pending NMI */
4964 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4965 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4966 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4967 ++vcpu->stat.nmi_window_exits;
4968 kvm_make_request(KVM_REQ_EVENT, vcpu);
4973 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
4975 struct vcpu_vmx *vmx = to_vmx(vcpu);
4976 enum emulation_result err = EMULATE_DONE;
4979 bool intr_window_requested;
4980 unsigned count = 130;
4982 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4983 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
4985 while (!guest_state_valid(vcpu) && count-- != 0) {
4986 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
4987 return handle_interrupt_window(&vmx->vcpu);
4989 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
4992 err = emulate_instruction(vcpu, 0);
4994 if (err == EMULATE_DO_MMIO) {
4999 if (err != EMULATE_DONE) {
5000 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5001 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5002 vcpu->run->internal.ndata = 0;
5006 if (signal_pending(current))
5012 vmx->emulation_required = !guest_state_valid(vcpu);
5018 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5019 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5021 static int handle_pause(struct kvm_vcpu *vcpu)
5023 skip_emulated_instruction(vcpu);
5024 kvm_vcpu_on_spin(vcpu);
5029 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5031 kvm_queue_exception(vcpu, UD_VECTOR);
5036 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5037 * We could reuse a single VMCS for all the L2 guests, but we also want the
5038 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5039 * allows keeping them loaded on the processor, and in the future will allow
5040 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5041 * every entry if they never change.
5042 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5043 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5045 * The following functions allocate and free a vmcs02 in this pool.
5048 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5049 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5051 struct vmcs02_list *item;
5052 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5053 if (item->vmptr == vmx->nested.current_vmptr) {
5054 list_move(&item->list, &vmx->nested.vmcs02_pool);
5055 return &item->vmcs02;
5058 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5059 /* Recycle the least recently used VMCS. */
5060 item = list_entry(vmx->nested.vmcs02_pool.prev,
5061 struct vmcs02_list, list);
5062 item->vmptr = vmx->nested.current_vmptr;
5063 list_move(&item->list, &vmx->nested.vmcs02_pool);
5064 return &item->vmcs02;
5067 /* Create a new VMCS */
5068 item = (struct vmcs02_list *)
5069 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5072 item->vmcs02.vmcs = alloc_vmcs();
5073 if (!item->vmcs02.vmcs) {
5077 loaded_vmcs_init(&item->vmcs02);
5078 item->vmptr = vmx->nested.current_vmptr;
5079 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5080 vmx->nested.vmcs02_num++;
5081 return &item->vmcs02;
5084 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5085 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5087 struct vmcs02_list *item;
5088 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5089 if (item->vmptr == vmptr) {
5090 free_loaded_vmcs(&item->vmcs02);
5091 list_del(&item->list);
5093 vmx->nested.vmcs02_num--;
5099 * Free all VMCSs saved for this vcpu, except the one pointed by
5100 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5101 * currently used, if running L2), and vmcs01 when running L2.
5103 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5105 struct vmcs02_list *item, *n;
5106 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5107 if (vmx->loaded_vmcs != &item->vmcs02)
5108 free_loaded_vmcs(&item->vmcs02);
5109 list_del(&item->list);
5112 vmx->nested.vmcs02_num = 0;
5114 if (vmx->loaded_vmcs != &vmx->vmcs01)
5115 free_loaded_vmcs(&vmx->vmcs01);
5119 * Emulate the VMXON instruction.
5120 * Currently, we just remember that VMX is active, and do not save or even
5121 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5122 * do not currently need to store anything in that guest-allocated memory
5123 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5124 * argument is different from the VMXON pointer (which the spec says they do).
5126 static int handle_vmon(struct kvm_vcpu *vcpu)
5128 struct kvm_segment cs;
5129 struct vcpu_vmx *vmx = to_vmx(vcpu);
5131 /* The Intel VMX Instruction Reference lists a bunch of bits that
5132 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5133 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5134 * Otherwise, we should fail with #UD. We test these now:
5136 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5137 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5138 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5139 kvm_queue_exception(vcpu, UD_VECTOR);
5143 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5144 if (is_long_mode(vcpu) && !cs.l) {
5145 kvm_queue_exception(vcpu, UD_VECTOR);
5149 if (vmx_get_cpl(vcpu)) {
5150 kvm_inject_gp(vcpu, 0);
5154 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5155 vmx->nested.vmcs02_num = 0;
5157 vmx->nested.vmxon = true;
5159 skip_emulated_instruction(vcpu);
5164 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5165 * for running VMX instructions (except VMXON, whose prerequisites are
5166 * slightly different). It also specifies what exception to inject otherwise.
5168 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5170 struct kvm_segment cs;
5171 struct vcpu_vmx *vmx = to_vmx(vcpu);
5173 if (!vmx->nested.vmxon) {
5174 kvm_queue_exception(vcpu, UD_VECTOR);
5178 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5179 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5180 (is_long_mode(vcpu) && !cs.l)) {
5181 kvm_queue_exception(vcpu, UD_VECTOR);
5185 if (vmx_get_cpl(vcpu)) {
5186 kvm_inject_gp(vcpu, 0);
5194 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5195 * just stops using VMX.
5197 static void free_nested(struct vcpu_vmx *vmx)
5199 if (!vmx->nested.vmxon)
5201 vmx->nested.vmxon = false;
5202 if (vmx->nested.current_vmptr != -1ull) {
5203 kunmap(vmx->nested.current_vmcs12_page);
5204 nested_release_page(vmx->nested.current_vmcs12_page);
5205 vmx->nested.current_vmptr = -1ull;
5206 vmx->nested.current_vmcs12 = NULL;
5208 /* Unpin physical memory we referred to in current vmcs02 */
5209 if (vmx->nested.apic_access_page) {
5210 nested_release_page(vmx->nested.apic_access_page);
5211 vmx->nested.apic_access_page = 0;
5214 nested_free_all_saved_vmcss(vmx);
5217 /* Emulate the VMXOFF instruction */
5218 static int handle_vmoff(struct kvm_vcpu *vcpu)
5220 if (!nested_vmx_check_permission(vcpu))
5222 free_nested(to_vmx(vcpu));
5223 skip_emulated_instruction(vcpu);
5228 * Decode the memory-address operand of a vmx instruction, as recorded on an
5229 * exit caused by such an instruction (run by a guest hypervisor).
5230 * On success, returns 0. When the operand is invalid, returns 1 and throws
5233 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5234 unsigned long exit_qualification,
5235 u32 vmx_instruction_info, gva_t *ret)
5238 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5239 * Execution", on an exit, vmx_instruction_info holds most of the
5240 * addressing components of the operand. Only the displacement part
5241 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5242 * For how an actual address is calculated from all these components,
5243 * refer to Vol. 1, "Operand Addressing".
5245 int scaling = vmx_instruction_info & 3;
5246 int addr_size = (vmx_instruction_info >> 7) & 7;
5247 bool is_reg = vmx_instruction_info & (1u << 10);
5248 int seg_reg = (vmx_instruction_info >> 15) & 7;
5249 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5250 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5251 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5252 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5255 kvm_queue_exception(vcpu, UD_VECTOR);
5259 /* Addr = segment_base + offset */
5260 /* offset = base + [index * scale] + displacement */
5261 *ret = vmx_get_segment_base(vcpu, seg_reg);
5263 *ret += kvm_register_read(vcpu, base_reg);
5265 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5266 *ret += exit_qualification; /* holds the displacement */
5268 if (addr_size == 1) /* 32 bit */
5272 * TODO: throw #GP (and return 1) in various cases that the VM*
5273 * instructions require it - e.g., offset beyond segment limit,
5274 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5275 * address, and so on. Currently these are not checked.
5281 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5282 * set the success or error code of an emulated VMX instruction, as specified
5283 * by Vol 2B, VMX Instruction Reference, "Conventions".
5285 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5287 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5288 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5289 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5292 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5294 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5295 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5296 X86_EFLAGS_SF | X86_EFLAGS_OF))
5300 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5301 u32 vm_instruction_error)
5303 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5305 * failValid writes the error number to the current VMCS, which
5306 * can't be done there isn't a current VMCS.
5308 nested_vmx_failInvalid(vcpu);
5311 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5312 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5313 X86_EFLAGS_SF | X86_EFLAGS_OF))
5315 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5318 /* Emulate the VMCLEAR instruction */
5319 static int handle_vmclear(struct kvm_vcpu *vcpu)
5321 struct vcpu_vmx *vmx = to_vmx(vcpu);
5324 struct vmcs12 *vmcs12;
5326 struct x86_exception e;
5328 if (!nested_vmx_check_permission(vcpu))
5331 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5332 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5335 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5336 sizeof(vmptr), &e)) {
5337 kvm_inject_page_fault(vcpu, &e);
5341 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5342 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5343 skip_emulated_instruction(vcpu);
5347 if (vmptr == vmx->nested.current_vmptr) {
5348 kunmap(vmx->nested.current_vmcs12_page);
5349 nested_release_page(vmx->nested.current_vmcs12_page);
5350 vmx->nested.current_vmptr = -1ull;
5351 vmx->nested.current_vmcs12 = NULL;
5354 page = nested_get_page(vcpu, vmptr);
5357 * For accurate processor emulation, VMCLEAR beyond available
5358 * physical memory should do nothing at all. However, it is
5359 * possible that a nested vmx bug, not a guest hypervisor bug,
5360 * resulted in this case, so let's shut down before doing any
5363 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5366 vmcs12 = kmap(page);
5367 vmcs12->launch_state = 0;
5369 nested_release_page(page);
5371 nested_free_vmcs02(vmx, vmptr);
5373 skip_emulated_instruction(vcpu);
5374 nested_vmx_succeed(vcpu);
5378 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5380 /* Emulate the VMLAUNCH instruction */
5381 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5383 return nested_vmx_run(vcpu, true);
5386 /* Emulate the VMRESUME instruction */
5387 static int handle_vmresume(struct kvm_vcpu *vcpu)
5390 return nested_vmx_run(vcpu, false);
5393 enum vmcs_field_type {
5394 VMCS_FIELD_TYPE_U16 = 0,
5395 VMCS_FIELD_TYPE_U64 = 1,
5396 VMCS_FIELD_TYPE_U32 = 2,
5397 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5400 static inline int vmcs_field_type(unsigned long field)
5402 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5403 return VMCS_FIELD_TYPE_U32;
5404 return (field >> 13) & 0x3 ;
5407 static inline int vmcs_field_readonly(unsigned long field)
5409 return (((field >> 10) & 0x3) == 1);
5413 * Read a vmcs12 field. Since these can have varying lengths and we return
5414 * one type, we chose the biggest type (u64) and zero-extend the return value
5415 * to that size. Note that the caller, handle_vmread, might need to use only
5416 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5417 * 64-bit fields are to be returned).
5419 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5420 unsigned long field, u64 *ret)
5422 short offset = vmcs_field_to_offset(field);
5428 p = ((char *)(get_vmcs12(vcpu))) + offset;
5430 switch (vmcs_field_type(field)) {
5431 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5432 *ret = *((natural_width *)p);
5434 case VMCS_FIELD_TYPE_U16:
5437 case VMCS_FIELD_TYPE_U32:
5440 case VMCS_FIELD_TYPE_U64:
5444 return 0; /* can never happen. */
5449 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5450 * used before) all generate the same failure when it is missing.
5452 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5454 struct vcpu_vmx *vmx = to_vmx(vcpu);
5455 if (vmx->nested.current_vmptr == -1ull) {
5456 nested_vmx_failInvalid(vcpu);
5457 skip_emulated_instruction(vcpu);
5463 static int handle_vmread(struct kvm_vcpu *vcpu)
5465 unsigned long field;
5467 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5468 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5471 if (!nested_vmx_check_permission(vcpu) ||
5472 !nested_vmx_check_vmcs12(vcpu))
5475 /* Decode instruction info and find the field to read */
5476 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5477 /* Read the field, zero-extended to a u64 field_value */
5478 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5479 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5480 skip_emulated_instruction(vcpu);
5484 * Now copy part of this value to register or memory, as requested.
5485 * Note that the number of bits actually copied is 32 or 64 depending
5486 * on the guest's mode (32 or 64 bit), not on the given field's length.
5488 if (vmx_instruction_info & (1u << 10)) {
5489 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5492 if (get_vmx_mem_address(vcpu, exit_qualification,
5493 vmx_instruction_info, &gva))
5495 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5496 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5497 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5500 nested_vmx_succeed(vcpu);
5501 skip_emulated_instruction(vcpu);
5506 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5508 unsigned long field;
5510 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5511 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5514 /* The value to write might be 32 or 64 bits, depending on L1's long
5515 * mode, and eventually we need to write that into a field of several
5516 * possible lengths. The code below first zero-extends the value to 64
5517 * bit (field_value), and then copies only the approriate number of
5518 * bits into the vmcs12 field.
5520 u64 field_value = 0;
5521 struct x86_exception e;
5523 if (!nested_vmx_check_permission(vcpu) ||
5524 !nested_vmx_check_vmcs12(vcpu))
5527 if (vmx_instruction_info & (1u << 10))
5528 field_value = kvm_register_read(vcpu,
5529 (((vmx_instruction_info) >> 3) & 0xf));
5531 if (get_vmx_mem_address(vcpu, exit_qualification,
5532 vmx_instruction_info, &gva))
5534 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5535 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5536 kvm_inject_page_fault(vcpu, &e);
5542 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5543 if (vmcs_field_readonly(field)) {
5544 nested_vmx_failValid(vcpu,
5545 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5546 skip_emulated_instruction(vcpu);
5550 offset = vmcs_field_to_offset(field);
5552 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5553 skip_emulated_instruction(vcpu);
5556 p = ((char *) get_vmcs12(vcpu)) + offset;
5558 switch (vmcs_field_type(field)) {
5559 case VMCS_FIELD_TYPE_U16:
5560 *(u16 *)p = field_value;
5562 case VMCS_FIELD_TYPE_U32:
5563 *(u32 *)p = field_value;
5565 case VMCS_FIELD_TYPE_U64:
5566 *(u64 *)p = field_value;
5568 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5569 *(natural_width *)p = field_value;
5572 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5573 skip_emulated_instruction(vcpu);
5577 nested_vmx_succeed(vcpu);
5578 skip_emulated_instruction(vcpu);
5582 /* Emulate the VMPTRLD instruction */
5583 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5585 struct vcpu_vmx *vmx = to_vmx(vcpu);
5588 struct x86_exception e;
5590 if (!nested_vmx_check_permission(vcpu))
5593 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5594 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5597 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5598 sizeof(vmptr), &e)) {
5599 kvm_inject_page_fault(vcpu, &e);
5603 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5604 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5605 skip_emulated_instruction(vcpu);
5609 if (vmx->nested.current_vmptr != vmptr) {
5610 struct vmcs12 *new_vmcs12;
5612 page = nested_get_page(vcpu, vmptr);
5614 nested_vmx_failInvalid(vcpu);
5615 skip_emulated_instruction(vcpu);
5618 new_vmcs12 = kmap(page);
5619 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5621 nested_release_page_clean(page);
5622 nested_vmx_failValid(vcpu,
5623 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5624 skip_emulated_instruction(vcpu);
5627 if (vmx->nested.current_vmptr != -1ull) {
5628 kunmap(vmx->nested.current_vmcs12_page);
5629 nested_release_page(vmx->nested.current_vmcs12_page);
5632 vmx->nested.current_vmptr = vmptr;
5633 vmx->nested.current_vmcs12 = new_vmcs12;
5634 vmx->nested.current_vmcs12_page = page;
5637 nested_vmx_succeed(vcpu);
5638 skip_emulated_instruction(vcpu);
5642 /* Emulate the VMPTRST instruction */
5643 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5645 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5646 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5648 struct x86_exception e;
5650 if (!nested_vmx_check_permission(vcpu))
5653 if (get_vmx_mem_address(vcpu, exit_qualification,
5654 vmx_instruction_info, &vmcs_gva))
5656 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5657 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5658 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5660 kvm_inject_page_fault(vcpu, &e);
5663 nested_vmx_succeed(vcpu);
5664 skip_emulated_instruction(vcpu);
5669 * The exit handlers return 1 if the exit was handled fully and guest execution
5670 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5671 * to be done to userspace and return 0.
5673 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5674 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5675 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
5676 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
5677 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
5678 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
5679 [EXIT_REASON_CR_ACCESS] = handle_cr,
5680 [EXIT_REASON_DR_ACCESS] = handle_dr,
5681 [EXIT_REASON_CPUID] = handle_cpuid,
5682 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5683 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5684 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5685 [EXIT_REASON_HLT] = handle_halt,
5686 [EXIT_REASON_INVD] = handle_invd,
5687 [EXIT_REASON_INVLPG] = handle_invlpg,
5688 [EXIT_REASON_RDPMC] = handle_rdpmc,
5689 [EXIT_REASON_VMCALL] = handle_vmcall,
5690 [EXIT_REASON_VMCLEAR] = handle_vmclear,
5691 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
5692 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
5693 [EXIT_REASON_VMPTRST] = handle_vmptrst,
5694 [EXIT_REASON_VMREAD] = handle_vmread,
5695 [EXIT_REASON_VMRESUME] = handle_vmresume,
5696 [EXIT_REASON_VMWRITE] = handle_vmwrite,
5697 [EXIT_REASON_VMOFF] = handle_vmoff,
5698 [EXIT_REASON_VMON] = handle_vmon,
5699 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5700 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
5701 [EXIT_REASON_WBINVD] = handle_wbinvd,
5702 [EXIT_REASON_XSETBV] = handle_xsetbv,
5703 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
5704 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
5705 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5706 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
5707 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
5708 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5709 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
5712 static const int kvm_vmx_max_exit_handlers =
5713 ARRAY_SIZE(kvm_vmx_exit_handlers);
5716 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5717 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5718 * disinterest in the current event (read or write a specific MSR) by using an
5719 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5721 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5722 struct vmcs12 *vmcs12, u32 exit_reason)
5724 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5727 if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5731 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5732 * for the four combinations of read/write and low/high MSR numbers.
5733 * First we need to figure out which of the four to use:
5735 bitmap = vmcs12->msr_bitmap;
5736 if (exit_reason == EXIT_REASON_MSR_WRITE)
5738 if (msr_index >= 0xc0000000) {
5739 msr_index -= 0xc0000000;
5743 /* Then read the msr_index'th bit from this bitmap: */
5744 if (msr_index < 1024*8) {
5746 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5747 return 1 & (b >> (msr_index & 7));
5749 return 1; /* let L1 handle the wrong parameter */
5753 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5754 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5755 * intercept (via guest_host_mask etc.) the current event.
5757 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5758 struct vmcs12 *vmcs12)
5760 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5761 int cr = exit_qualification & 15;
5762 int reg = (exit_qualification >> 8) & 15;
5763 unsigned long val = kvm_register_read(vcpu, reg);
5765 switch ((exit_qualification >> 4) & 3) {
5766 case 0: /* mov to cr */
5769 if (vmcs12->cr0_guest_host_mask &
5770 (val ^ vmcs12->cr0_read_shadow))
5774 if ((vmcs12->cr3_target_count >= 1 &&
5775 vmcs12->cr3_target_value0 == val) ||
5776 (vmcs12->cr3_target_count >= 2 &&
5777 vmcs12->cr3_target_value1 == val) ||
5778 (vmcs12->cr3_target_count >= 3 &&
5779 vmcs12->cr3_target_value2 == val) ||
5780 (vmcs12->cr3_target_count >= 4 &&
5781 vmcs12->cr3_target_value3 == val))
5783 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5787 if (vmcs12->cr4_guest_host_mask &
5788 (vmcs12->cr4_read_shadow ^ val))
5792 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5798 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5799 (vmcs12->cr0_read_shadow & X86_CR0_TS))
5802 case 1: /* mov from cr */
5805 if (vmcs12->cpu_based_vm_exec_control &
5806 CPU_BASED_CR3_STORE_EXITING)
5810 if (vmcs12->cpu_based_vm_exec_control &
5811 CPU_BASED_CR8_STORE_EXITING)
5818 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5819 * cr0. Other attempted changes are ignored, with no exit.
5821 if (vmcs12->cr0_guest_host_mask & 0xe &
5822 (val ^ vmcs12->cr0_read_shadow))
5824 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5825 !(vmcs12->cr0_read_shadow & 0x1) &&
5834 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5835 * should handle it ourselves in L0 (and then continue L2). Only call this
5836 * when in is_guest_mode (L2).
5838 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5840 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5841 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5842 struct vcpu_vmx *vmx = to_vmx(vcpu);
5843 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5845 if (vmx->nested.nested_run_pending)
5848 if (unlikely(vmx->fail)) {
5849 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5850 vmcs_read32(VM_INSTRUCTION_ERROR));
5854 switch (exit_reason) {
5855 case EXIT_REASON_EXCEPTION_NMI:
5856 if (!is_exception(intr_info))
5858 else if (is_page_fault(intr_info))
5860 return vmcs12->exception_bitmap &
5861 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5862 case EXIT_REASON_EXTERNAL_INTERRUPT:
5864 case EXIT_REASON_TRIPLE_FAULT:
5866 case EXIT_REASON_PENDING_INTERRUPT:
5867 case EXIT_REASON_NMI_WINDOW:
5869 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5870 * (aka Interrupt Window Exiting) only when L1 turned it on,
5871 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5872 * Same for NMI Window Exiting.
5875 case EXIT_REASON_TASK_SWITCH:
5877 case EXIT_REASON_CPUID:
5879 case EXIT_REASON_HLT:
5880 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5881 case EXIT_REASON_INVD:
5883 case EXIT_REASON_INVLPG:
5884 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5885 case EXIT_REASON_RDPMC:
5886 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5887 case EXIT_REASON_RDTSC:
5888 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5889 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5890 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5891 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5892 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5893 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5895 * VMX instructions trap unconditionally. This allows L1 to
5896 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5899 case EXIT_REASON_CR_ACCESS:
5900 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5901 case EXIT_REASON_DR_ACCESS:
5902 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5903 case EXIT_REASON_IO_INSTRUCTION:
5904 /* TODO: support IO bitmaps */
5906 case EXIT_REASON_MSR_READ:
5907 case EXIT_REASON_MSR_WRITE:
5908 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5909 case EXIT_REASON_INVALID_STATE:
5911 case EXIT_REASON_MWAIT_INSTRUCTION:
5912 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5913 case EXIT_REASON_MONITOR_INSTRUCTION:
5914 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5915 case EXIT_REASON_PAUSE_INSTRUCTION:
5916 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5917 nested_cpu_has2(vmcs12,
5918 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5919 case EXIT_REASON_MCE_DURING_VMENTRY:
5921 case EXIT_REASON_TPR_BELOW_THRESHOLD:
5923 case EXIT_REASON_APIC_ACCESS:
5924 return nested_cpu_has2(vmcs12,
5925 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5926 case EXIT_REASON_EPT_VIOLATION:
5927 case EXIT_REASON_EPT_MISCONFIG:
5929 case EXIT_REASON_WBINVD:
5930 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5931 case EXIT_REASON_XSETBV:
5938 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5940 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5941 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5945 * The guest has exited. See if we can fix it or if we need userspace
5948 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5950 struct vcpu_vmx *vmx = to_vmx(vcpu);
5951 u32 exit_reason = vmx->exit_reason;
5952 u32 vectoring_info = vmx->idt_vectoring_info;
5954 /* If guest state is invalid, start emulating */
5955 if (vmx->emulation_required && emulate_invalid_guest_state)
5956 return handle_invalid_guest_state(vcpu);
5959 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5960 * we did not inject a still-pending event to L1 now because of
5961 * nested_run_pending, we need to re-enable this bit.
5963 if (vmx->nested.nested_run_pending)
5964 kvm_make_request(KVM_REQ_EVENT, vcpu);
5966 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5967 exit_reason == EXIT_REASON_VMRESUME))
5968 vmx->nested.nested_run_pending = 1;
5970 vmx->nested.nested_run_pending = 0;
5972 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5973 nested_vmx_vmexit(vcpu);
5977 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5978 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5979 vcpu->run->fail_entry.hardware_entry_failure_reason
5984 if (unlikely(vmx->fail)) {
5985 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5986 vcpu->run->fail_entry.hardware_entry_failure_reason
5987 = vmcs_read32(VM_INSTRUCTION_ERROR);
5991 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5992 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5993 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5994 exit_reason != EXIT_REASON_TASK_SWITCH))
5995 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
5996 "(0x%x) and exit reason is 0x%x\n",
5997 __func__, vectoring_info, exit_reason);
5999 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6000 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6001 get_vmcs12(vcpu), vcpu)))) {
6002 if (vmx_interrupt_allowed(vcpu)) {
6003 vmx->soft_vnmi_blocked = 0;
6004 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
6005 vcpu->arch.nmi_pending) {
6007 * This CPU don't support us in finding the end of an
6008 * NMI-blocked window if the guest runs with IRQs
6009 * disabled. So we pull the trigger after 1 s of
6010 * futile waiting, but inform the user about this.
6012 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6013 "state on VCPU %d after 1 s timeout\n",
6014 __func__, vcpu->vcpu_id);
6015 vmx->soft_vnmi_blocked = 0;
6019 if (exit_reason < kvm_vmx_max_exit_handlers
6020 && kvm_vmx_exit_handlers[exit_reason])
6021 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6023 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6024 vcpu->run->hw.hardware_exit_reason = exit_reason;
6029 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6031 if (irr == -1 || tpr < irr) {
6032 vmcs_write32(TPR_THRESHOLD, 0);
6036 vmcs_write32(TPR_THRESHOLD, irr);
6039 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
6043 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6044 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6047 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6048 exit_intr_info = vmx->exit_intr_info;
6050 /* Handle machine checks before interrupts are enabled */
6051 if (is_machine_check(exit_intr_info))
6052 kvm_machine_check();
6054 /* We need to handle NMIs before interrupts are enabled */
6055 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
6056 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6057 kvm_before_handle_nmi(&vmx->vcpu);
6059 kvm_after_handle_nmi(&vmx->vcpu);
6063 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6068 bool idtv_info_valid;
6070 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6072 if (cpu_has_virtual_nmis()) {
6073 if (vmx->nmi_known_unmasked)
6076 * Can't use vmx->exit_intr_info since we're not sure what
6077 * the exit reason is.
6079 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6080 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6081 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6083 * SDM 3: 27.7.1.2 (September 2008)
6084 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6085 * a guest IRET fault.
6086 * SDM 3: 23.2.2 (September 2008)
6087 * Bit 12 is undefined in any of the following cases:
6088 * If the VM exit sets the valid bit in the IDT-vectoring
6089 * information field.
6090 * If the VM exit is due to a double fault.
6092 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6093 vector != DF_VECTOR && !idtv_info_valid)
6094 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6095 GUEST_INTR_STATE_NMI);
6097 vmx->nmi_known_unmasked =
6098 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6099 & GUEST_INTR_STATE_NMI);
6100 } else if (unlikely(vmx->soft_vnmi_blocked))
6101 vmx->vnmi_blocked_time +=
6102 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
6105 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
6106 u32 idt_vectoring_info,
6107 int instr_len_field,
6108 int error_code_field)
6112 bool idtv_info_valid;
6114 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6116 vmx->vcpu.arch.nmi_injected = false;
6117 kvm_clear_exception_queue(&vmx->vcpu);
6118 kvm_clear_interrupt_queue(&vmx->vcpu);
6120 if (!idtv_info_valid)
6123 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6125 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6126 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6129 case INTR_TYPE_NMI_INTR:
6130 vmx->vcpu.arch.nmi_injected = true;
6132 * SDM 3: 27.7.1.2 (September 2008)
6133 * Clear bit "block by NMI" before VM entry if a NMI
6136 vmx_set_nmi_mask(&vmx->vcpu, false);
6138 case INTR_TYPE_SOFT_EXCEPTION:
6139 vmx->vcpu.arch.event_exit_inst_len =
6140 vmcs_read32(instr_len_field);
6142 case INTR_TYPE_HARD_EXCEPTION:
6143 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6144 u32 err = vmcs_read32(error_code_field);
6145 kvm_queue_exception_e(&vmx->vcpu, vector, err);
6147 kvm_queue_exception(&vmx->vcpu, vector);
6149 case INTR_TYPE_SOFT_INTR:
6150 vmx->vcpu.arch.event_exit_inst_len =
6151 vmcs_read32(instr_len_field);
6153 case INTR_TYPE_EXT_INTR:
6154 kvm_queue_interrupt(&vmx->vcpu, vector,
6155 type == INTR_TYPE_SOFT_INTR);
6162 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6164 if (is_guest_mode(&vmx->vcpu))
6166 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6167 VM_EXIT_INSTRUCTION_LEN,
6168 IDT_VECTORING_ERROR_CODE);
6171 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6173 if (is_guest_mode(vcpu))
6175 __vmx_complete_interrupts(to_vmx(vcpu),
6176 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6177 VM_ENTRY_INSTRUCTION_LEN,
6178 VM_ENTRY_EXCEPTION_ERROR_CODE);
6180 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6183 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6186 struct perf_guest_switch_msr *msrs;
6188 msrs = perf_guest_get_msrs(&nr_msrs);
6193 for (i = 0; i < nr_msrs; i++)
6194 if (msrs[i].host == msrs[i].guest)
6195 clear_atomic_switch_msr(vmx, msrs[i].msr);
6197 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6201 #ifdef CONFIG_X86_64
6209 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6211 struct vcpu_vmx *vmx = to_vmx(vcpu);
6213 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6214 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6215 if (vmcs12->idt_vectoring_info_field &
6216 VECTORING_INFO_VALID_MASK) {
6217 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6218 vmcs12->idt_vectoring_info_field);
6219 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6220 vmcs12->vm_exit_instruction_len);
6221 if (vmcs12->idt_vectoring_info_field &
6222 VECTORING_INFO_DELIVER_CODE_MASK)
6223 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6224 vmcs12->idt_vectoring_error_code);
6228 /* Record the guest's net vcpu time for enforced NMI injections. */
6229 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6230 vmx->entry_time = ktime_get();
6232 /* Don't enter VMX if guest state is invalid, let the exit handler
6233 start emulation until we arrive back to a valid state */
6234 if (vmx->emulation_required && emulate_invalid_guest_state)
6237 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6238 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6239 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6240 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6242 /* When single-stepping over STI and MOV SS, we must clear the
6243 * corresponding interruptibility bits in the guest state. Otherwise
6244 * vmentry fails as it then expects bit 14 (BS) in pending debug
6245 * exceptions being set, but that's not correct for the guest debugging
6247 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6248 vmx_set_interrupt_shadow(vcpu, 0);
6250 atomic_switch_perf_msrs(vmx);
6252 vmx->__launched = vmx->loaded_vmcs->launched;
6254 /* Store host registers */
6255 "push %%"R"dx; push %%"R"bp;"
6256 "push %%"R"cx \n\t" /* placeholder for guest rcx */
6258 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
6260 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
6261 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
6263 /* Reload cr2 if changed */
6264 "mov %c[cr2](%0), %%"R"ax \n\t"
6265 "mov %%cr2, %%"R"dx \n\t"
6266 "cmp %%"R"ax, %%"R"dx \n\t"
6268 "mov %%"R"ax, %%cr2 \n\t"
6270 /* Check if vmlaunch of vmresume is needed */
6271 "cmpl $0, %c[launched](%0) \n\t"
6272 /* Load guest registers. Don't clobber flags. */
6273 "mov %c[rax](%0), %%"R"ax \n\t"
6274 "mov %c[rbx](%0), %%"R"bx \n\t"
6275 "mov %c[rdx](%0), %%"R"dx \n\t"
6276 "mov %c[rsi](%0), %%"R"si \n\t"
6277 "mov %c[rdi](%0), %%"R"di \n\t"
6278 "mov %c[rbp](%0), %%"R"bp \n\t"
6279 #ifdef CONFIG_X86_64
6280 "mov %c[r8](%0), %%r8 \n\t"
6281 "mov %c[r9](%0), %%r9 \n\t"
6282 "mov %c[r10](%0), %%r10 \n\t"
6283 "mov %c[r11](%0), %%r11 \n\t"
6284 "mov %c[r12](%0), %%r12 \n\t"
6285 "mov %c[r13](%0), %%r13 \n\t"
6286 "mov %c[r14](%0), %%r14 \n\t"
6287 "mov %c[r15](%0), %%r15 \n\t"
6289 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
6291 /* Enter guest mode */
6292 "jne .Llaunched \n\t"
6293 __ex(ASM_VMX_VMLAUNCH) "\n\t"
6294 "jmp .Lkvm_vmx_return \n\t"
6295 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
6296 ".Lkvm_vmx_return: "
6297 /* Save guest registers, load host registers, keep flags */
6298 "mov %0, %c[wordsize](%%"R"sp) \n\t"
6300 "mov %%"R"ax, %c[rax](%0) \n\t"
6301 "mov %%"R"bx, %c[rbx](%0) \n\t"
6302 "pop"Q" %c[rcx](%0) \n\t"
6303 "mov %%"R"dx, %c[rdx](%0) \n\t"
6304 "mov %%"R"si, %c[rsi](%0) \n\t"
6305 "mov %%"R"di, %c[rdi](%0) \n\t"
6306 "mov %%"R"bp, %c[rbp](%0) \n\t"
6307 #ifdef CONFIG_X86_64
6308 "mov %%r8, %c[r8](%0) \n\t"
6309 "mov %%r9, %c[r9](%0) \n\t"
6310 "mov %%r10, %c[r10](%0) \n\t"
6311 "mov %%r11, %c[r11](%0) \n\t"
6312 "mov %%r12, %c[r12](%0) \n\t"
6313 "mov %%r13, %c[r13](%0) \n\t"
6314 "mov %%r14, %c[r14](%0) \n\t"
6315 "mov %%r15, %c[r15](%0) \n\t"
6317 "mov %%cr2, %%"R"ax \n\t"
6318 "mov %%"R"ax, %c[cr2](%0) \n\t"
6320 "pop %%"R"bp; pop %%"R"dx \n\t"
6321 "setbe %c[fail](%0) \n\t"
6322 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
6323 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
6324 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
6325 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
6326 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6327 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6328 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6329 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6330 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6331 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6332 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
6333 #ifdef CONFIG_X86_64
6334 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6335 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6336 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6337 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6338 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6339 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6340 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6341 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6343 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6344 [wordsize]"i"(sizeof(ulong))
6346 , R"ax", R"bx", R"di", R"si"
6347 #ifdef CONFIG_X86_64
6348 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6352 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6353 | (1 << VCPU_EXREG_RFLAGS)
6354 | (1 << VCPU_EXREG_CPL)
6355 | (1 << VCPU_EXREG_PDPTR)
6356 | (1 << VCPU_EXREG_SEGMENTS)
6357 | (1 << VCPU_EXREG_CR3));
6358 vcpu->arch.regs_dirty = 0;
6360 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6362 if (is_guest_mode(vcpu)) {
6363 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6364 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6365 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6366 vmcs12->idt_vectoring_error_code =
6367 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6368 vmcs12->vm_exit_instruction_len =
6369 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6373 vmx->loaded_vmcs->launched = 1;
6375 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
6376 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
6378 vmx_complete_atomic_exit(vmx);
6379 vmx_recover_nmi_blocking(vmx);
6380 vmx_complete_interrupts(vmx);
6386 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6388 struct vcpu_vmx *vmx = to_vmx(vcpu);
6392 free_loaded_vmcs(vmx->loaded_vmcs);
6393 kfree(vmx->guest_msrs);
6394 kvm_vcpu_uninit(vcpu);
6395 kmem_cache_free(kvm_vcpu_cache, vmx);
6398 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6401 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
6405 return ERR_PTR(-ENOMEM);
6409 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6413 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
6415 if (!vmx->guest_msrs) {
6419 vmx->loaded_vmcs = &vmx->vmcs01;
6420 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6421 if (!vmx->loaded_vmcs->vmcs)
6424 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6425 loaded_vmcs_init(vmx->loaded_vmcs);
6430 vmx_vcpu_load(&vmx->vcpu, cpu);
6431 vmx->vcpu.cpu = cpu;
6432 err = vmx_vcpu_setup(vmx);
6433 vmx_vcpu_put(&vmx->vcpu);
6437 if (vm_need_virtualize_apic_accesses(kvm))
6438 err = alloc_apic_access_page(kvm);
6443 if (!kvm->arch.ept_identity_map_addr)
6444 kvm->arch.ept_identity_map_addr =
6445 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
6447 if (alloc_identity_pagetable(kvm) != 0)
6449 if (!init_rmode_identity_map(kvm))
6453 vmx->nested.current_vmptr = -1ull;
6454 vmx->nested.current_vmcs12 = NULL;
6459 free_loaded_vmcs(vmx->loaded_vmcs);
6461 kfree(vmx->guest_msrs);
6463 kvm_vcpu_uninit(&vmx->vcpu);
6466 kmem_cache_free(kvm_vcpu_cache, vmx);
6467 return ERR_PTR(err);
6470 static void __init vmx_check_processor_compat(void *rtn)
6472 struct vmcs_config vmcs_conf;
6475 if (setup_vmcs_config(&vmcs_conf) < 0)
6477 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6478 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6479 smp_processor_id());
6484 static int get_ept_level(void)
6486 return VMX_EPT_DEFAULT_GAW + 1;
6489 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6493 /* For VT-d and EPT combination
6494 * 1. MMIO: always map as UC
6496 * a. VT-d without snooping control feature: can't guarantee the
6497 * result, try to trust guest.
6498 * b. VT-d with snooping control feature: snooping control feature of
6499 * VT-d engine can guarantee the cache correctness. Just set it
6500 * to WB to keep consistent with host. So the same as item 3.
6501 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6502 * consistent with host MTRR
6505 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
6506 else if (vcpu->kvm->arch.iommu_domain &&
6507 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6508 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6509 VMX_EPT_MT_EPTE_SHIFT;
6511 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
6517 static int vmx_get_lpage_level(void)
6519 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6520 return PT_DIRECTORY_LEVEL;
6522 /* For shadow and EPT supported 1GB page */
6523 return PT_PDPE_LEVEL;
6526 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6528 struct kvm_cpuid_entry2 *best;
6529 struct vcpu_vmx *vmx = to_vmx(vcpu);
6532 vmx->rdtscp_enabled = false;
6533 if (vmx_rdtscp_supported()) {
6534 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6535 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6536 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6537 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6538 vmx->rdtscp_enabled = true;
6540 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6541 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6548 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6550 if (func == 1 && nested)
6551 entry->ecx |= bit(X86_FEATURE_VMX);
6555 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6556 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6557 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6558 * guest in a way that will both be appropriate to L1's requests, and our
6559 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6560 * function also has additional necessary side-effects, like setting various
6561 * vcpu->arch fields.
6563 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6565 struct vcpu_vmx *vmx = to_vmx(vcpu);
6568 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6569 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6570 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6571 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6572 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6573 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6574 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6575 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6576 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6577 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6578 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6579 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6580 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6581 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6582 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6583 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6584 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6585 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6586 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6587 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6588 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6589 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6590 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6591 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6592 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6593 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6594 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6595 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6596 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6597 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6598 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6599 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6600 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6601 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6602 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6603 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6605 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6606 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6607 vmcs12->vm_entry_intr_info_field);
6608 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6609 vmcs12->vm_entry_exception_error_code);
6610 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6611 vmcs12->vm_entry_instruction_len);
6612 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6613 vmcs12->guest_interruptibility_info);
6614 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6615 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6616 vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6617 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6618 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6619 vmcs12->guest_pending_dbg_exceptions);
6620 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6621 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6623 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6625 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6626 (vmcs_config.pin_based_exec_ctrl |
6627 vmcs12->pin_based_vm_exec_control));
6630 * Whether page-faults are trapped is determined by a combination of
6631 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6632 * If enable_ept, L0 doesn't care about page faults and we should
6633 * set all of these to L1's desires. However, if !enable_ept, L0 does
6634 * care about (at least some) page faults, and because it is not easy
6635 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6636 * to exit on each and every L2 page fault. This is done by setting
6637 * MASK=MATCH=0 and (see below) EB.PF=1.
6638 * Note that below we don't need special code to set EB.PF beyond the
6639 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6640 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6641 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6643 * A problem with this approach (when !enable_ept) is that L1 may be
6644 * injected with more page faults than it asked for. This could have
6645 * caused problems, but in practice existing hypervisors don't care.
6646 * To fix this, we will need to emulate the PFEC checking (on the L1
6647 * page tables), using walk_addr(), when injecting PFs to L1.
6649 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6650 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6651 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6652 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6654 if (cpu_has_secondary_exec_ctrls()) {
6655 u32 exec_control = vmx_secondary_exec_control(vmx);
6656 if (!vmx->rdtscp_enabled)
6657 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6658 /* Take the following fields only from vmcs12 */
6659 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6660 if (nested_cpu_has(vmcs12,
6661 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6662 exec_control |= vmcs12->secondary_vm_exec_control;
6664 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6666 * Translate L1 physical address to host physical
6667 * address for vmcs02. Keep the page pinned, so this
6668 * physical address remains valid. We keep a reference
6669 * to it so we can release it later.
6671 if (vmx->nested.apic_access_page) /* shouldn't happen */
6672 nested_release_page(vmx->nested.apic_access_page);
6673 vmx->nested.apic_access_page =
6674 nested_get_page(vcpu, vmcs12->apic_access_addr);
6676 * If translation failed, no matter: This feature asks
6677 * to exit when accessing the given address, and if it
6678 * can never be accessed, this feature won't do
6681 if (!vmx->nested.apic_access_page)
6683 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6685 vmcs_write64(APIC_ACCESS_ADDR,
6686 page_to_phys(vmx->nested.apic_access_page));
6689 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6694 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6695 * Some constant fields are set here by vmx_set_constant_host_state().
6696 * Other fields are different per CPU, and will be set later when
6697 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6699 vmx_set_constant_host_state();
6702 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6703 * entry, but only if the current (host) sp changed from the value
6704 * we wrote last (vmx->host_rsp). This cache is no longer relevant
6705 * if we switch vmcs, and rather than hold a separate cache per vmcs,
6706 * here we just force the write to happen on entry.
6710 exec_control = vmx_exec_control(vmx); /* L0's desires */
6711 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6712 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6713 exec_control &= ~CPU_BASED_TPR_SHADOW;
6714 exec_control |= vmcs12->cpu_based_vm_exec_control;
6716 * Merging of IO and MSR bitmaps not currently supported.
6717 * Rather, exit every time.
6719 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6720 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6721 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6723 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6725 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6726 * bitwise-or of what L1 wants to trap for L2, and what we want to
6727 * trap. Note that CR0.TS also needs updating - we do this later.
6729 update_exception_bitmap(vcpu);
6730 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6731 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6733 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6734 vmcs_write32(VM_EXIT_CONTROLS,
6735 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6736 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6737 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6739 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6740 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6741 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6742 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6745 set_cr4_guest_host_mask(vmx);
6747 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6748 vmcs_write64(TSC_OFFSET,
6749 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6751 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
6755 * Trivially support vpid by letting L2s share their parent
6756 * L1's vpid. TODO: move to a more elaborate solution, giving
6757 * each L2 its own vpid and exposing the vpid feature to L1.
6759 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6760 vmx_flush_tlb(vcpu);
6763 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6764 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6765 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6766 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6768 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6769 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6770 vmx_set_efer(vcpu, vcpu->arch.efer);
6773 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6774 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6775 * The CR0_READ_SHADOW is what L2 should have expected to read given
6776 * the specifications by L1; It's not enough to take
6777 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6778 * have more bits than L1 expected.
6780 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6781 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6783 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6784 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6786 /* shadow page tables on either EPT or shadow page tables */
6787 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6788 kvm_mmu_reset_context(vcpu);
6790 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6791 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6795 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6796 * for running an L2 nested guest.
6798 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6800 struct vmcs12 *vmcs12;
6801 struct vcpu_vmx *vmx = to_vmx(vcpu);
6803 struct loaded_vmcs *vmcs02;
6805 if (!nested_vmx_check_permission(vcpu) ||
6806 !nested_vmx_check_vmcs12(vcpu))
6809 skip_emulated_instruction(vcpu);
6810 vmcs12 = get_vmcs12(vcpu);
6813 * The nested entry process starts with enforcing various prerequisites
6814 * on vmcs12 as required by the Intel SDM, and act appropriately when
6815 * they fail: As the SDM explains, some conditions should cause the
6816 * instruction to fail, while others will cause the instruction to seem
6817 * to succeed, but return an EXIT_REASON_INVALID_STATE.
6818 * To speed up the normal (success) code path, we should avoid checking
6819 * for misconfigurations which will anyway be caught by the processor
6820 * when using the merged vmcs02.
6822 if (vmcs12->launch_state == launch) {
6823 nested_vmx_failValid(vcpu,
6824 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6825 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6829 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6830 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6831 /*TODO: Also verify bits beyond physical address width are 0*/
6832 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6836 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6837 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6838 /*TODO: Also verify bits beyond physical address width are 0*/
6839 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6843 if (vmcs12->vm_entry_msr_load_count > 0 ||
6844 vmcs12->vm_exit_msr_load_count > 0 ||
6845 vmcs12->vm_exit_msr_store_count > 0) {
6846 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6848 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6852 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6853 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6854 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6855 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6856 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6857 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6858 !vmx_control_verify(vmcs12->vm_exit_controls,
6859 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6860 !vmx_control_verify(vmcs12->vm_entry_controls,
6861 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6863 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6867 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6868 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6869 nested_vmx_failValid(vcpu,
6870 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6874 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6875 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6876 nested_vmx_entry_failure(vcpu, vmcs12,
6877 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6880 if (vmcs12->vmcs_link_pointer != -1ull) {
6881 nested_vmx_entry_failure(vcpu, vmcs12,
6882 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6887 * We're finally done with prerequisite checking, and can start with
6891 vmcs02 = nested_get_current_vmcs02(vmx);
6895 enter_guest_mode(vcpu);
6897 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6900 vmx->loaded_vmcs = vmcs02;
6902 vmx_vcpu_load(vcpu, cpu);
6906 vmcs12->launch_state = 1;
6908 prepare_vmcs02(vcpu, vmcs12);
6911 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6912 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6913 * returned as far as L1 is concerned. It will only return (and set
6914 * the success flag) when L2 exits (see nested_vmx_vmexit()).
6920 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6921 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6922 * This function returns the new value we should put in vmcs12.guest_cr0.
6923 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6924 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6925 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6926 * didn't trap the bit, because if L1 did, so would L0).
6927 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6928 * been modified by L2, and L1 knows it. So just leave the old value of
6929 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6930 * isn't relevant, because if L0 traps this bit it can set it to anything.
6931 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6932 * changed these bits, and therefore they need to be updated, but L0
6933 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6934 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6936 static inline unsigned long
6937 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6940 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6941 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6942 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6943 vcpu->arch.cr0_guest_owned_bits));
6946 static inline unsigned long
6947 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6950 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
6951 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
6952 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
6953 vcpu->arch.cr4_guest_owned_bits));
6957 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6958 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6959 * and this function updates it to reflect the changes to the guest state while
6960 * L2 was running (and perhaps made some exits which were handled directly by L0
6961 * without going back to L1), and to reflect the exit reason.
6962 * Note that we do not have to copy here all VMCS fields, just those that
6963 * could have changed by the L2 guest or the exit - i.e., the guest-state and
6964 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
6965 * which already writes to vmcs12 directly.
6967 void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6969 /* update guest state fields: */
6970 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
6971 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
6973 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
6974 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6975 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
6976 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
6978 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
6979 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
6980 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
6981 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
6982 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
6983 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
6984 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
6985 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
6986 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
6987 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
6988 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
6989 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
6990 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
6991 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
6992 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
6993 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
6994 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
6995 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
6996 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
6997 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
6998 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
6999 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7000 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7001 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7002 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7003 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7004 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7005 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7006 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7007 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7008 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7009 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7010 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7011 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7012 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7013 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7015 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
7016 vmcs12->guest_interruptibility_info =
7017 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7018 vmcs12->guest_pending_dbg_exceptions =
7019 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7021 /* TODO: These cannot have changed unless we have MSR bitmaps and
7022 * the relevant bit asks not to trap the change */
7023 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
7024 if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
7025 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7026 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7027 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7028 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7030 /* update exit information fields: */
7032 vmcs12->vm_exit_reason = vmcs_read32(VM_EXIT_REASON);
7033 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7035 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7036 vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7037 vmcs12->idt_vectoring_info_field =
7038 vmcs_read32(IDT_VECTORING_INFO_FIELD);
7039 vmcs12->idt_vectoring_error_code =
7040 vmcs_read32(IDT_VECTORING_ERROR_CODE);
7041 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7042 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7044 /* clear vm-entry fields which are to be cleared on exit */
7045 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
7046 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
7050 * A part of what we need to when the nested L2 guest exits and we want to
7051 * run its L1 parent, is to reset L1's guest state to the host state specified
7053 * This function is to be called not only on normal nested exit, but also on
7054 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7055 * Failures During or After Loading Guest State").
7056 * This function should be called when the active VMCS is L1's (vmcs01).
7058 void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7060 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7061 vcpu->arch.efer = vmcs12->host_ia32_efer;
7062 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7063 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7065 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7066 vmx_set_efer(vcpu, vcpu->arch.efer);
7068 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7069 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
7071 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7072 * actually changed, because it depends on the current state of
7073 * fpu_active (which may have changed).
7074 * Note that vmx_set_cr0 refers to efer set above.
7076 kvm_set_cr0(vcpu, vmcs12->host_cr0);
7078 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7079 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7080 * but we also need to update cr0_guest_host_mask and exception_bitmap.
7082 update_exception_bitmap(vcpu);
7083 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7084 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7087 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7088 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7090 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7091 kvm_set_cr4(vcpu, vmcs12->host_cr4);
7093 /* shadow page tables on either EPT or shadow page tables */
7094 kvm_set_cr3(vcpu, vmcs12->host_cr3);
7095 kvm_mmu_reset_context(vcpu);
7099 * Trivially support vpid by letting L2s share their parent
7100 * L1's vpid. TODO: move to a more elaborate solution, giving
7101 * each L2 its own vpid and exposing the vpid feature to L1.
7103 vmx_flush_tlb(vcpu);
7107 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7108 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7109 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7110 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7111 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7112 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7113 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7114 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7115 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7116 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7117 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7118 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7119 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7120 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7121 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7123 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7124 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7125 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7126 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7127 vmcs12->host_ia32_perf_global_ctrl);
7131 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7132 * and modify vmcs12 to make it see what it would expect to see there if
7133 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7135 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7137 struct vcpu_vmx *vmx = to_vmx(vcpu);
7139 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7141 leave_guest_mode(vcpu);
7142 prepare_vmcs12(vcpu, vmcs12);
7145 vmx->loaded_vmcs = &vmx->vmcs01;
7147 vmx_vcpu_load(vcpu, cpu);
7151 /* if no vmcs02 cache requested, remove the one we used */
7152 if (VMCS02_POOL_SIZE == 0)
7153 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7155 load_vmcs12_host_state(vcpu, vmcs12);
7157 /* Update TSC_OFFSET if TSC was changed while L2 ran */
7158 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7160 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7163 /* Unpin physical memory we referred to in vmcs02 */
7164 if (vmx->nested.apic_access_page) {
7165 nested_release_page(vmx->nested.apic_access_page);
7166 vmx->nested.apic_access_page = 0;
7170 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7171 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7172 * success or failure flag accordingly.
7174 if (unlikely(vmx->fail)) {
7176 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7178 nested_vmx_succeed(vcpu);
7182 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7183 * 23.7 "VM-entry failures during or after loading guest state" (this also
7184 * lists the acceptable exit-reason and exit-qualification parameters).
7185 * It should only be called before L2 actually succeeded to run, and when
7186 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7188 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7189 struct vmcs12 *vmcs12,
7190 u32 reason, unsigned long qualification)
7192 load_vmcs12_host_state(vcpu, vmcs12);
7193 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7194 vmcs12->exit_qualification = qualification;
7195 nested_vmx_succeed(vcpu);
7198 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7199 struct x86_instruction_info *info,
7200 enum x86_intercept_stage stage)
7202 return X86EMUL_CONTINUE;
7205 static struct kvm_x86_ops vmx_x86_ops = {
7206 .cpu_has_kvm_support = cpu_has_kvm_support,
7207 .disabled_by_bios = vmx_disabled_by_bios,
7208 .hardware_setup = hardware_setup,
7209 .hardware_unsetup = hardware_unsetup,
7210 .check_processor_compatibility = vmx_check_processor_compat,
7211 .hardware_enable = hardware_enable,
7212 .hardware_disable = hardware_disable,
7213 .cpu_has_accelerated_tpr = report_flexpriority,
7215 .vcpu_create = vmx_create_vcpu,
7216 .vcpu_free = vmx_free_vcpu,
7217 .vcpu_reset = vmx_vcpu_reset,
7219 .prepare_guest_switch = vmx_save_host_state,
7220 .vcpu_load = vmx_vcpu_load,
7221 .vcpu_put = vmx_vcpu_put,
7223 .set_guest_debug = set_guest_debug,
7224 .get_msr = vmx_get_msr,
7225 .set_msr = vmx_set_msr,
7226 .get_segment_base = vmx_get_segment_base,
7227 .get_segment = vmx_get_segment,
7228 .set_segment = vmx_set_segment,
7229 .get_cpl = vmx_get_cpl,
7230 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7231 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7232 .decache_cr3 = vmx_decache_cr3,
7233 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7234 .set_cr0 = vmx_set_cr0,
7235 .set_cr3 = vmx_set_cr3,
7236 .set_cr4 = vmx_set_cr4,
7237 .set_efer = vmx_set_efer,
7238 .get_idt = vmx_get_idt,
7239 .set_idt = vmx_set_idt,
7240 .get_gdt = vmx_get_gdt,
7241 .set_gdt = vmx_set_gdt,
7242 .set_dr7 = vmx_set_dr7,
7243 .cache_reg = vmx_cache_reg,
7244 .get_rflags = vmx_get_rflags,
7245 .set_rflags = vmx_set_rflags,
7246 .fpu_activate = vmx_fpu_activate,
7247 .fpu_deactivate = vmx_fpu_deactivate,
7249 .tlb_flush = vmx_flush_tlb,
7251 .run = vmx_vcpu_run,
7252 .handle_exit = vmx_handle_exit,
7253 .skip_emulated_instruction = skip_emulated_instruction,
7254 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7255 .get_interrupt_shadow = vmx_get_interrupt_shadow,
7256 .patch_hypercall = vmx_patch_hypercall,
7257 .set_irq = vmx_inject_irq,
7258 .set_nmi = vmx_inject_nmi,
7259 .queue_exception = vmx_queue_exception,
7260 .cancel_injection = vmx_cancel_injection,
7261 .interrupt_allowed = vmx_interrupt_allowed,
7262 .nmi_allowed = vmx_nmi_allowed,
7263 .get_nmi_mask = vmx_get_nmi_mask,
7264 .set_nmi_mask = vmx_set_nmi_mask,
7265 .enable_nmi_window = enable_nmi_window,
7266 .enable_irq_window = enable_irq_window,
7267 .update_cr8_intercept = update_cr8_intercept,
7269 .set_tss_addr = vmx_set_tss_addr,
7270 .get_tdp_level = get_ept_level,
7271 .get_mt_mask = vmx_get_mt_mask,
7273 .get_exit_info = vmx_get_exit_info,
7275 .get_lpage_level = vmx_get_lpage_level,
7277 .cpuid_update = vmx_cpuid_update,
7279 .rdtscp_supported = vmx_rdtscp_supported,
7281 .set_supported_cpuid = vmx_set_supported_cpuid,
7283 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7285 .set_tsc_khz = vmx_set_tsc_khz,
7286 .write_tsc_offset = vmx_write_tsc_offset,
7287 .adjust_tsc_offset = vmx_adjust_tsc_offset,
7288 .compute_tsc_offset = vmx_compute_tsc_offset,
7289 .read_l1_tsc = vmx_read_l1_tsc,
7291 .set_tdp_cr3 = vmx_set_cr3,
7293 .check_intercept = vmx_check_intercept,
7296 static int __init vmx_init(void)
7300 rdmsrl_safe(MSR_EFER, &host_efer);
7302 for (i = 0; i < NR_VMX_MSR; ++i)
7303 kvm_define_shared_msr(i, vmx_msr_index[i]);
7305 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
7306 if (!vmx_io_bitmap_a)
7311 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
7312 if (!vmx_io_bitmap_b)
7315 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
7316 if (!vmx_msr_bitmap_legacy)
7320 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
7321 if (!vmx_msr_bitmap_longmode)
7326 * Allow direct access to the PC debug port (it is often used for I/O
7327 * delays, but the vmexits simply slow things down).
7329 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7330 clear_bit(0x80, vmx_io_bitmap_a);
7332 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
7334 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7335 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
7337 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7339 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7340 __alignof__(struct vcpu_vmx), THIS_MODULE);
7344 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7345 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7346 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7347 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7348 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7349 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
7352 kvm_mmu_set_mask_ptes(0ull,
7353 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
7354 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
7355 0ull, VMX_EPT_EXECUTABLE_MASK);
7356 ept_set_mmio_spte_mask();
7364 free_page((unsigned long)vmx_msr_bitmap_longmode);
7366 free_page((unsigned long)vmx_msr_bitmap_legacy);
7368 free_page((unsigned long)vmx_io_bitmap_b);
7370 free_page((unsigned long)vmx_io_bitmap_a);
7374 static void __exit vmx_exit(void)
7376 free_page((unsigned long)vmx_msr_bitmap_legacy);
7377 free_page((unsigned long)vmx_msr_bitmap_longmode);
7378 free_page((unsigned long)vmx_io_bitmap_b);
7379 free_page((unsigned long)vmx_io_bitmap_a);
7384 module_init(vmx_init)
7385 module_exit(vmx_exit)