arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include "kvm_cache_regs.h"
  35 #include "x86.h"
  36
  37 #include <asm/io.h>
  38 #include <asm/desc.h>
  39 #include <asm/vmx.h>
  40 #include <asm/virtext.h>
  41 #include <asm/mce.h>
  42 #include <asm/i387.h>
  43 #include <asm/xcr.h>
  44 #include <asm/perf_event.h>
  45
  46 #include "trace.h"
  47
  48 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  49 #define __ex_clear(x, reg) \
  50         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  51
  52 MODULE_AUTHOR("Qumranet");
  53 MODULE_LICENSE("GPL");
  54
  55 static const struct x86_cpu_id vmx_cpu_id[] = {
  56         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  57         {}
  58 };
  59 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  60
  61 static bool __read_mostly enable_vpid = 1;
  62 module_param_named(vpid, enable_vpid, bool, 0444);
  63
  64 static bool __read_mostly flexpriority_enabled = 1;
  65 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  66
  67 static bool __read_mostly enable_ept = 1;
  68 module_param_named(ept, enable_ept, bool, S_IRUGO);
  69
  70 static bool __read_mostly enable_unrestricted_guest = 1;
  71 module_param_named(unrestricted_guest,
  72                         enable_unrestricted_guest, bool, S_IRUGO);
  73
  74 static bool __read_mostly enable_ept_ad_bits = 1;
  75 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  76
  77 static bool __read_mostly emulate_invalid_guest_state = 0;
  78 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  79
  80 static bool __read_mostly vmm_exclusive = 1;
  81 module_param(vmm_exclusive, bool, S_IRUGO);
  82
  83 static bool __read_mostly fasteoi = 1;
  84 module_param(fasteoi, bool, S_IRUGO);
  85
  86 /*
  87  * If nested=1, nested virtualization is supported, i.e., guests may use
  88  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  89  * use VMX instructions.
  90  */
  91 static bool __read_mostly nested = 0;
  92 module_param(nested, bool, S_IRUGO);
  93
  94 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  95         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
  96 #define KVM_GUEST_CR0_MASK                                              \
  97         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  98 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
  99         (X86_CR0_WP | X86_CR0_NE)
 100 #define KVM_VM_CR0_ALWAYS_ON                                            \
 101         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 102 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 103         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 104          | X86_CR4_OSXMMEXCPT)
 105
 106 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 107 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 108
 109 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 110
 111 /*
 112  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 113  * ple_gap:    upper bound on the amount of time between two successive
 114  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 115  *             According to test, this time is usually smaller than 128 cycles.
 116  * ple_window: upper bound on the amount of time a guest is allowed to execute
 117  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 118  *             less than 2^12 cycles
 119  * Time is measured based on a counter that runs at the same rate as the TSC,
 120  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 121  */
 122 #define KVM_VMX_DEFAULT_PLE_GAP    128
 123 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 124 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 125 module_param(ple_gap, int, S_IRUGO);
 126
 127 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 128 module_param(ple_window, int, S_IRUGO);
 129
 130 #define NR_AUTOLOAD_MSRS 8
 131 #define VMCS02_POOL_SIZE 1
 132
 133 struct vmcs {
 134         u32 revision_id;
 135         u32 abort;
 136         char data[0];
 137 };
 138
 139 /*
 140  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 141  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 142  * loaded on this CPU (so we can clear them if the CPU goes down).
 143  */
 144 struct loaded_vmcs {
 145         struct vmcs *vmcs;
 146         int cpu;
 147         int launched;
 148         struct list_head loaded_vmcss_on_cpu_link;
 149 };
 150
 151 struct shared_msr_entry {
 152         unsigned index;
 153         u64 data;
 154         u64 mask;
 155 };
 156
 157 /*
 158  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 159  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 160  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 161  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 162  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 163  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 164  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 165  * underlying hardware which will be used to run L2.
 166  * This structure is packed to ensure that its layout is identical across
 167  * machines (necessary for live migration).
 168  * If there are changes in this struct, VMCS12_REVISION must be changed.
 169  */
 170 typedef u64 natural_width;
 171 struct __packed vmcs12 {
 172         /* According to the Intel spec, a VMCS region must start with the
 173          * following two fields. Then follow implementation-specific data.
 174          */
 175         u32 revision_id;
 176         u32 abort;
 177
 178         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 179         u32 padding[7]; /* room for future expansion */
 180
 181         u64 io_bitmap_a;
 182         u64 io_bitmap_b;
 183         u64 msr_bitmap;
 184         u64 vm_exit_msr_store_addr;
 185         u64 vm_exit_msr_load_addr;
 186         u64 vm_entry_msr_load_addr;
 187         u64 tsc_offset;
 188         u64 virtual_apic_page_addr;
 189         u64 apic_access_addr;
 190         u64 ept_pointer;
 191         u64 guest_physical_address;
 192         u64 vmcs_link_pointer;
 193         u64 guest_ia32_debugctl;
 194         u64 guest_ia32_pat;
 195         u64 guest_ia32_efer;
 196         u64 guest_ia32_perf_global_ctrl;
 197         u64 guest_pdptr0;
 198         u64 guest_pdptr1;
 199         u64 guest_pdptr2;
 200         u64 guest_pdptr3;
 201         u64 host_ia32_pat;
 202         u64 host_ia32_efer;
 203         u64 host_ia32_perf_global_ctrl;
 204         u64 padding64[8]; /* room for future expansion */
 205         /*
 206          * To allow migration of L1 (complete with its L2 guests) between
 207          * machines of different natural widths (32 or 64 bit), we cannot have
 208          * unsigned long fields with no explict size. We use u64 (aliased
 209          * natural_width) instead. Luckily, x86 is little-endian.
 210          */
 211         natural_width cr0_guest_host_mask;
 212         natural_width cr4_guest_host_mask;
 213         natural_width cr0_read_shadow;
 214         natural_width cr4_read_shadow;
 215         natural_width cr3_target_value0;
 216         natural_width cr3_target_value1;
 217         natural_width cr3_target_value2;
 218         natural_width cr3_target_value3;
 219         natural_width exit_qualification;
 220         natural_width guest_linear_address;
 221         natural_width guest_cr0;
 222         natural_width guest_cr3;
 223         natural_width guest_cr4;
 224         natural_width guest_es_base;
 225         natural_width guest_cs_base;
 226         natural_width guest_ss_base;
 227         natural_width guest_ds_base;
 228         natural_width guest_fs_base;
 229         natural_width guest_gs_base;
 230         natural_width guest_ldtr_base;
 231         natural_width guest_tr_base;
 232         natural_width guest_gdtr_base;
 233         natural_width guest_idtr_base;
 234         natural_width guest_dr7;
 235         natural_width guest_rsp;
 236         natural_width guest_rip;
 237         natural_width guest_rflags;
 238         natural_width guest_pending_dbg_exceptions;
 239         natural_width guest_sysenter_esp;
 240         natural_width guest_sysenter_eip;
 241         natural_width host_cr0;
 242         natural_width host_cr3;
 243         natural_width host_cr4;
 244         natural_width host_fs_base;
 245         natural_width host_gs_base;
 246         natural_width host_tr_base;
 247         natural_width host_gdtr_base;
 248         natural_width host_idtr_base;
 249         natural_width host_ia32_sysenter_esp;
 250         natural_width host_ia32_sysenter_eip;
 251         natural_width host_rsp;
 252         natural_width host_rip;
 253         natural_width paddingl[8]; /* room for future expansion */
 254         u32 pin_based_vm_exec_control;
 255         u32 cpu_based_vm_exec_control;
 256         u32 exception_bitmap;
 257         u32 page_fault_error_code_mask;
 258         u32 page_fault_error_code_match;
 259         u32 cr3_target_count;
 260         u32 vm_exit_controls;
 261         u32 vm_exit_msr_store_count;
 262         u32 vm_exit_msr_load_count;
 263         u32 vm_entry_controls;
 264         u32 vm_entry_msr_load_count;
 265         u32 vm_entry_intr_info_field;
 266         u32 vm_entry_exception_error_code;
 267         u32 vm_entry_instruction_len;
 268         u32 tpr_threshold;
 269         u32 secondary_vm_exec_control;
 270         u32 vm_instruction_error;
 271         u32 vm_exit_reason;
 272         u32 vm_exit_intr_info;
 273         u32 vm_exit_intr_error_code;
 274         u32 idt_vectoring_info_field;
 275         u32 idt_vectoring_error_code;
 276         u32 vm_exit_instruction_len;
 277         u32 vmx_instruction_info;
 278         u32 guest_es_limit;
 279         u32 guest_cs_limit;
 280         u32 guest_ss_limit;
 281         u32 guest_ds_limit;
 282         u32 guest_fs_limit;
 283         u32 guest_gs_limit;
 284         u32 guest_ldtr_limit;
 285         u32 guest_tr_limit;
 286         u32 guest_gdtr_limit;
 287         u32 guest_idtr_limit;
 288         u32 guest_es_ar_bytes;
 289         u32 guest_cs_ar_bytes;
 290         u32 guest_ss_ar_bytes;
 291         u32 guest_ds_ar_bytes;
 292         u32 guest_fs_ar_bytes;
 293         u32 guest_gs_ar_bytes;
 294         u32 guest_ldtr_ar_bytes;
 295         u32 guest_tr_ar_bytes;
 296         u32 guest_interruptibility_info;
 297         u32 guest_activity_state;
 298         u32 guest_sysenter_cs;
 299         u32 host_ia32_sysenter_cs;
 300         u32 padding32[8]; /* room for future expansion */
 301         u16 virtual_processor_id;
 302         u16 guest_es_selector;
 303         u16 guest_cs_selector;
 304         u16 guest_ss_selector;
 305         u16 guest_ds_selector;
 306         u16 guest_fs_selector;
 307         u16 guest_gs_selector;
 308         u16 guest_ldtr_selector;
 309         u16 guest_tr_selector;
 310         u16 host_es_selector;
 311         u16 host_cs_selector;
 312         u16 host_ss_selector;
 313         u16 host_ds_selector;
 314         u16 host_fs_selector;
 315         u16 host_gs_selector;
 316         u16 host_tr_selector;
 317 };
 318
 319 /*
 320  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 321  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 322  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 323  */
 324 #define VMCS12_REVISION 0x11e57ed0
 325
 326 /*
 327  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 328  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 329  * current implementation, 4K are reserved to avoid future complications.
 330  */
 331 #define VMCS12_SIZE 0x1000
 332
 333 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 334 struct vmcs02_list {
 335         struct list_head list;
 336         gpa_t vmptr;
 337         struct loaded_vmcs vmcs02;
 338 };
 339
 340 /*
 341  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 342  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 343  */
 344 struct nested_vmx {
 345         /* Has the level1 guest done vmxon? */
 346         bool vmxon;
 347
 348         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 349         gpa_t current_vmptr;
 350         /* The host-usable pointer to the above */
 351         struct page *current_vmcs12_page;
 352         struct vmcs12 *current_vmcs12;
 353
 354         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 355         struct list_head vmcs02_pool;
 356         int vmcs02_num;
 357         u64 vmcs01_tsc_offset;
 358         /* L2 must run next, and mustn't decide to exit to L1. */
 359         bool nested_run_pending;
 360         /*
 361          * Guest pages referred to in vmcs02 with host-physical pointers, so
 362          * we must keep them pinned while L2 runs.
 363          */
 364         struct page *apic_access_page;
 365 };
 366
 367 struct vcpu_vmx {
 368         struct kvm_vcpu       vcpu;
 369         unsigned long         host_rsp;
 370         u8                    fail;
 371         u8                    cpl;
 372         bool                  nmi_known_unmasked;
 373         u32                   exit_intr_info;
 374         u32                   idt_vectoring_info;
 375         ulong                 rflags;
 376         struct shared_msr_entry *guest_msrs;
 377         int                   nmsrs;
 378         int                   save_nmsrs;
 379 #ifdef CONFIG_X86_64
 380         u64                   msr_host_kernel_gs_base;
 381         u64                   msr_guest_kernel_gs_base;
 382 #endif
 383         /*
 384          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 385          * non-nested (L1) guest, it always points to vmcs01. For a nested
 386          * guest (L2), it points to a different VMCS.
 387          */
 388         struct loaded_vmcs    vmcs01;
 389         struct loaded_vmcs   *loaded_vmcs;
 390         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 391         struct msr_autoload {
 392                 unsigned nr;
 393                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 394                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 395         } msr_autoload;
 396         struct {
 397                 int           loaded;
 398                 u16           fs_sel, gs_sel, ldt_sel;
 399 #ifdef CONFIG_X86_64
 400                 u16           ds_sel, es_sel;
 401 #endif
 402                 int           gs_ldt_reload_needed;
 403                 int           fs_reload_needed;
 404         } host_state;
 405         struct {
 406                 int vm86_active;
 407                 ulong save_rflags;
 408                 struct kvm_save_segment {
 409                         u16 selector;
 410                         unsigned long base;
 411                         u32 limit;
 412                         u32 ar;
 413                 } tr, es, ds, fs, gs;
 414         } rmode;
 415         struct {
 416                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 417                 struct kvm_save_segment seg[8];
 418         } segment_cache;
 419         int vpid;
 420         bool emulation_required;
 421
 422         /* Support for vnmi-less CPUs */
 423         int soft_vnmi_blocked;
 424         ktime_t entry_time;
 425         s64 vnmi_blocked_time;
 426         u32 exit_reason;
 427
 428         bool rdtscp_enabled;
 429
 430         /* Support for a guest hypervisor (nested VMX) */
 431         struct nested_vmx nested;
 432 };
 433
 434 enum segment_cache_field {
 435         SEG_FIELD_SEL = 0,
 436         SEG_FIELD_BASE = 1,
 437         SEG_FIELD_LIMIT = 2,
 438         SEG_FIELD_AR = 3,
 439
 440         SEG_FIELD_NR = 4
 441 };
 442
 443 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 444 {
 445         return container_of(vcpu, struct vcpu_vmx, vcpu);
 446 }
 447
 448 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 449 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 450 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 451                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 452
 453 static unsigned short vmcs_field_to_offset_table[] = {
 454         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 455         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 456         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 457         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 458         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 459         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 460         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 461         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 462         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 463         FIELD(HOST_ES_SELECTOR, host_es_selector),
 464         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 465         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 466         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 467         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 468         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 469         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 470         FIELD64(IO_BITMAP_A, io_bitmap_a),
 471         FIELD64(IO_BITMAP_B, io_bitmap_b),
 472         FIELD64(MSR_BITMAP, msr_bitmap),
 473         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 474         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 475         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 476         FIELD64(TSC_OFFSET, tsc_offset),
 477         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 478         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 479         FIELD64(EPT_POINTER, ept_pointer),
 480         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 481         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 482         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 483         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 484         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 485         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 486         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 487         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 488         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 489         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 490         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 491         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 492         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 493         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 494         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 495         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 496         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 497         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 498         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 499         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 500         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 501         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 502         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 503         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 504         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 505         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 506         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 507         FIELD(TPR_THRESHOLD, tpr_threshold),
 508         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 509         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 510         FIELD(VM_EXIT_REASON, vm_exit_reason),
 511         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 512         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 513         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 514         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 515         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 516         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 517         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 518         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 519         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 520         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 521         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 522         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 523         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 524         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 525         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 526         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 527         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 528         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 529         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 530         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 531         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 532         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 533         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 534         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 535         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 536         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 537         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 538         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 539         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 540         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 541         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 542         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 543         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 544         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 545         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 546         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 547         FIELD(EXIT_QUALIFICATION, exit_qualification),
 548         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 549         FIELD(GUEST_CR0, guest_cr0),
 550         FIELD(GUEST_CR3, guest_cr3),
 551         FIELD(GUEST_CR4, guest_cr4),
 552         FIELD(GUEST_ES_BASE, guest_es_base),
 553         FIELD(GUEST_CS_BASE, guest_cs_base),
 554         FIELD(GUEST_SS_BASE, guest_ss_base),
 555         FIELD(GUEST_DS_BASE, guest_ds_base),
 556         FIELD(GUEST_FS_BASE, guest_fs_base),
 557         FIELD(GUEST_GS_BASE, guest_gs_base),
 558         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 559         FIELD(GUEST_TR_BASE, guest_tr_base),
 560         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 561         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 562         FIELD(GUEST_DR7, guest_dr7),
 563         FIELD(GUEST_RSP, guest_rsp),
 564         FIELD(GUEST_RIP, guest_rip),
 565         FIELD(GUEST_RFLAGS, guest_rflags),
 566         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 567         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 568         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 569         FIELD(HOST_CR0, host_cr0),
 570         FIELD(HOST_CR3, host_cr3),
 571         FIELD(HOST_CR4, host_cr4),
 572         FIELD(HOST_FS_BASE, host_fs_base),
 573         FIELD(HOST_GS_BASE, host_gs_base),
 574         FIELD(HOST_TR_BASE, host_tr_base),
 575         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 576         FIELD(HOST_IDTR_BASE, host_idtr_base),
 577         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 578         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 579         FIELD(HOST_RSP, host_rsp),
 580         FIELD(HOST_RIP, host_rip),
 581 };
 582 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 583
 584 static inline short vmcs_field_to_offset(unsigned long field)
 585 {
 586         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 587                 return -1;
 588         return vmcs_field_to_offset_table[field];
 589 }
 590
 591 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 592 {
 593         return to_vmx(vcpu)->nested.current_vmcs12;
 594 }
 595
 596 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 597 {
 598         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 599         if (is_error_page(page)) {
 600                 kvm_release_page_clean(page);
 601                 return NULL;
 602         }
 603         return page;
 604 }
 605
 606 static void nested_release_page(struct page *page)
 607 {
 608         kvm_release_page_dirty(page);
 609 }
 610
 611 static void nested_release_page_clean(struct page *page)
 612 {
 613         kvm_release_page_clean(page);
 614 }
 615
 616 static u64 construct_eptp(unsigned long root_hpa);
 617 static void kvm_cpu_vmxon(u64 addr);
 618 static void kvm_cpu_vmxoff(void);
 619 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
 620 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 621 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 622                             struct kvm_segment *var, int seg);
 623 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 624                             struct kvm_segment *var, int seg);
 625
 626 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 627 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 628 /*
 629  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 630  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 631  */
 632 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 633 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 634
 635 static unsigned long *vmx_io_bitmap_a;
 636 static unsigned long *vmx_io_bitmap_b;
 637 static unsigned long *vmx_msr_bitmap_legacy;
 638 static unsigned long *vmx_msr_bitmap_longmode;
 639
 640 static bool cpu_has_load_ia32_efer;
 641 static bool cpu_has_load_perf_global_ctrl;
 642
 643 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 644 static DEFINE_SPINLOCK(vmx_vpid_lock);
 645
 646 static struct vmcs_config {
 647         int size;
 648         int order;
 649         u32 revision_id;
 650         u32 pin_based_exec_ctrl;
 651         u32 cpu_based_exec_ctrl;
 652         u32 cpu_based_2nd_exec_ctrl;
 653         u32 vmexit_ctrl;
 654         u32 vmentry_ctrl;
 655 } vmcs_config;
 656
 657 static struct vmx_capability {
 658         u32 ept;
 659         u32 vpid;
 660 } vmx_capability;
 661
 662 #define VMX_SEGMENT_FIELD(seg)                                  \
 663         [VCPU_SREG_##seg] = {                                   \
 664                 .selector = GUEST_##seg##_SELECTOR,             \
 665                 .base = GUEST_##seg##_BASE,                     \
 666                 .limit = GUEST_##seg##_LIMIT,                   \
 667                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 668         }
 669
 670 static struct kvm_vmx_segment_field {
 671         unsigned selector;
 672         unsigned base;
 673         unsigned limit;
 674         unsigned ar_bytes;
 675 } kvm_vmx_segment_fields[] = {
 676         VMX_SEGMENT_FIELD(CS),
 677         VMX_SEGMENT_FIELD(DS),
 678         VMX_SEGMENT_FIELD(ES),
 679         VMX_SEGMENT_FIELD(FS),
 680         VMX_SEGMENT_FIELD(GS),
 681         VMX_SEGMENT_FIELD(SS),
 682         VMX_SEGMENT_FIELD(TR),
 683         VMX_SEGMENT_FIELD(LDTR),
 684 };
 685
 686 static u64 host_efer;
 687
 688 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 689
 690 /*
 691  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 692  * away by decrementing the array size.
 693  */
 694 static const u32 vmx_msr_index[] = {
 695 #ifdef CONFIG_X86_64
 696         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 697 #endif
 698         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 699 };
 700 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 701
 702 static inline bool is_page_fault(u32 intr_info)
 703 {
 704         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 705                              INTR_INFO_VALID_MASK)) ==
 706                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 707 }
 708
 709 static inline bool is_no_device(u32 intr_info)
 710 {
 711         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 712                              INTR_INFO_VALID_MASK)) ==
 713                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 714 }
 715
 716 static inline bool is_invalid_opcode(u32 intr_info)
 717 {
 718         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 719                              INTR_INFO_VALID_MASK)) ==
 720                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 721 }
 722
 723 static inline bool is_external_interrupt(u32 intr_info)
 724 {
 725         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 726                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 727 }
 728
 729 static inline bool is_machine_check(u32 intr_info)
 730 {
 731         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 732                              INTR_INFO_VALID_MASK)) ==
 733                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 734 }
 735
 736 static inline bool cpu_has_vmx_msr_bitmap(void)
 737 {
 738         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 739 }
 740
 741 static inline bool cpu_has_vmx_tpr_shadow(void)
 742 {
 743         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 744 }
 745
 746 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 747 {
 748         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 749 }
 750
 751 static inline bool cpu_has_secondary_exec_ctrls(void)
 752 {
 753         return vmcs_config.cpu_based_exec_ctrl &
 754                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 755 }
 756
 757 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 758 {
 759         return vmcs_config.cpu_based_2nd_exec_ctrl &
 760                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 761 }
 762
 763 static inline bool cpu_has_vmx_flexpriority(void)
 764 {
 765         return cpu_has_vmx_tpr_shadow() &&
 766                 cpu_has_vmx_virtualize_apic_accesses();
 767 }
 768
 769 static inline bool cpu_has_vmx_ept_execute_only(void)
 770 {
 771         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 772 }
 773
 774 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 775 {
 776         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 777 }
 778
 779 static inline bool cpu_has_vmx_eptp_writeback(void)
 780 {
 781         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 782 }
 783
 784 static inline bool cpu_has_vmx_ept_2m_page(void)
 785 {
 786         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 787 }
 788
 789 static inline bool cpu_has_vmx_ept_1g_page(void)
 790 {
 791         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 792 }
 793
 794 static inline bool cpu_has_vmx_ept_4levels(void)
 795 {
 796         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 797 }
 798
 799 static inline bool cpu_has_vmx_ept_ad_bits(void)
 800 {
 801         return vmx_capability.ept & VMX_EPT_AD_BIT;
 802 }
 803
 804 static inline bool cpu_has_vmx_invept_individual_addr(void)
 805 {
 806         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
 807 }
 808
 809 static inline bool cpu_has_vmx_invept_context(void)
 810 {
 811         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 812 }
 813
 814 static inline bool cpu_has_vmx_invept_global(void)
 815 {
 816         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 817 }
 818
 819 static inline bool cpu_has_vmx_invvpid_single(void)
 820 {
 821         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 822 }
 823
 824 static inline bool cpu_has_vmx_invvpid_global(void)
 825 {
 826         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 827 }
 828
 829 static inline bool cpu_has_vmx_ept(void)
 830 {
 831         return vmcs_config.cpu_based_2nd_exec_ctrl &
 832                 SECONDARY_EXEC_ENABLE_EPT;
 833 }
 834
 835 static inline bool cpu_has_vmx_unrestricted_guest(void)
 836 {
 837         return vmcs_config.cpu_based_2nd_exec_ctrl &
 838                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 839 }
 840
 841 static inline bool cpu_has_vmx_ple(void)
 842 {
 843         return vmcs_config.cpu_based_2nd_exec_ctrl &
 844                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 845 }
 846
 847 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 848 {
 849         return flexpriority_enabled && irqchip_in_kernel(kvm);
 850 }
 851
 852 static inline bool cpu_has_vmx_vpid(void)
 853 {
 854         return vmcs_config.cpu_based_2nd_exec_ctrl &
 855                 SECONDARY_EXEC_ENABLE_VPID;
 856 }
 857
 858 static inline bool cpu_has_vmx_rdtscp(void)
 859 {
 860         return vmcs_config.cpu_based_2nd_exec_ctrl &
 861                 SECONDARY_EXEC_RDTSCP;
 862 }
 863
 864 static inline bool cpu_has_virtual_nmis(void)
 865 {
 866         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 867 }
 868
 869 static inline bool cpu_has_vmx_wbinvd_exit(void)
 870 {
 871         return vmcs_config.cpu_based_2nd_exec_ctrl &
 872                 SECONDARY_EXEC_WBINVD_EXITING;
 873 }
 874
 875 static inline bool report_flexpriority(void)
 876 {
 877         return flexpriority_enabled;
 878 }
 879
 880 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
 881 {
 882         return vmcs12->cpu_based_vm_exec_control & bit;
 883 }
 884
 885 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
 886 {
 887         return (vmcs12->cpu_based_vm_exec_control &
 888                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
 889                 (vmcs12->secondary_vm_exec_control & bit);
 890 }
 891
 892 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
 893         struct kvm_vcpu *vcpu)
 894 {
 895         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
 896 }
 897
 898 static inline bool is_exception(u32 intr_info)
 899 {
 900         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 901                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
 902 }
 903
 904 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
 905 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
 906                         struct vmcs12 *vmcs12,
 907                         u32 reason, unsigned long qualification);
 908
 909 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 910 {
 911         int i;
 912
 913         for (i = 0; i < vmx->nmsrs; ++i)
 914                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 915                         return i;
 916         return -1;
 917 }
 918
 919 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 920 {
 921     struct {
 922         u64 vpid : 16;
 923         u64 rsvd : 48;
 924         u64 gva;
 925     } operand = { vpid, 0, gva };
 926
 927     asm volatile (__ex(ASM_VMX_INVVPID)
 928                   /* CF==1 or ZF==1 --> rc = -1 */
 929                   "; ja 1f ; ud2 ; 1:"
 930                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 931 }
 932
 933 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 934 {
 935         struct {
 936                 u64 eptp, gpa;
 937         } operand = {eptp, gpa};
 938
 939         asm volatile (__ex(ASM_VMX_INVEPT)
 940                         /* CF==1 or ZF==1 --> rc = -1 */
 941                         "; ja 1f ; ud2 ; 1:\n"
 942                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 943 }
 944
 945 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 946 {
 947         int i;
 948
 949         i = __find_msr_index(vmx, msr);
 950         if (i >= 0)
 951                 return &vmx->guest_msrs[i];
 952         return NULL;
 953 }
 954
 955 static void vmcs_clear(struct vmcs *vmcs)
 956 {
 957         u64 phys_addr = __pa(vmcs);
 958         u8 error;
 959
 960         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 961                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 962                       : "cc", "memory");
 963         if (error)
 964                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 965                        vmcs, phys_addr);
 966 }
 967
 968 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
 969 {
 970         vmcs_clear(loaded_vmcs->vmcs);
 971         loaded_vmcs->cpu = -1;
 972         loaded_vmcs->launched = 0;
 973 }
 974
 975 static void vmcs_load(struct vmcs *vmcs)
 976 {
 977         u64 phys_addr = __pa(vmcs);
 978         u8 error;
 979
 980         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 981                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 982                         : "cc", "memory");
 983         if (error)
 984                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
 985                        vmcs, phys_addr);
 986 }
 987
 988 static void __loaded_vmcs_clear(void *arg)
 989 {
 990         struct loaded_vmcs *loaded_vmcs = arg;
 991         int cpu = raw_smp_processor_id();
 992
 993         if (loaded_vmcs->cpu != cpu)
 994                 return; /* vcpu migration can race with cpu offline */
 995         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
 996                 per_cpu(current_vmcs, cpu) = NULL;
 997         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
 998         loaded_vmcs_init(loaded_vmcs);
 999 }
1000
1001 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1002 {
1003         if (loaded_vmcs->cpu != -1)
1004                 smp_call_function_single(
1005                         loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
1006 }
1007
1008 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1009 {
1010         if (vmx->vpid == 0)
1011                 return;
1012
1013         if (cpu_has_vmx_invvpid_single())
1014                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1015 }
1016
1017 static inline void vpid_sync_vcpu_global(void)
1018 {
1019         if (cpu_has_vmx_invvpid_global())
1020                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1021 }
1022
1023 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1024 {
1025         if (cpu_has_vmx_invvpid_single())
1026                 vpid_sync_vcpu_single(vmx);
1027         else
1028                 vpid_sync_vcpu_global();
1029 }
1030
1031 static inline void ept_sync_global(void)
1032 {
1033         if (cpu_has_vmx_invept_global())
1034                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1035 }
1036
1037 static inline void ept_sync_context(u64 eptp)
1038 {
1039         if (enable_ept) {
1040                 if (cpu_has_vmx_invept_context())
1041                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1042                 else
1043                         ept_sync_global();
1044         }
1045 }
1046
1047 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1048 {
1049         if (enable_ept) {
1050                 if (cpu_has_vmx_invept_individual_addr())
1051                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1052                                         eptp, gpa);
1053                 else
1054                         ept_sync_context(eptp);
1055         }
1056 }
1057
1058 static __always_inline unsigned long vmcs_readl(unsigned long field)
1059 {
1060         unsigned long value;
1061
1062         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1063                       : "=a"(value) : "d"(field) : "cc");
1064         return value;
1065 }
1066
1067 static __always_inline u16 vmcs_read16(unsigned long field)
1068 {
1069         return vmcs_readl(field);
1070 }
1071
1072 static __always_inline u32 vmcs_read32(unsigned long field)
1073 {
1074         return vmcs_readl(field);
1075 }
1076
1077 static __always_inline u64 vmcs_read64(unsigned long field)
1078 {
1079 #ifdef CONFIG_X86_64
1080         return vmcs_readl(field);
1081 #else
1082         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1083 #endif
1084 }
1085
1086 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1087 {
1088         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1089                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1090         dump_stack();
1091 }
1092
1093 static void vmcs_writel(unsigned long field, unsigned long value)
1094 {
1095         u8 error;
1096
1097         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1098                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1099         if (unlikely(error))
1100                 vmwrite_error(field, value);
1101 }
1102
1103 static void vmcs_write16(unsigned long field, u16 value)
1104 {
1105         vmcs_writel(field, value);
1106 }
1107
1108 static void vmcs_write32(unsigned long field, u32 value)
1109 {
1110         vmcs_writel(field, value);
1111 }
1112
1113 static void vmcs_write64(unsigned long field, u64 value)
1114 {
1115         vmcs_writel(field, value);
1116 #ifndef CONFIG_X86_64
1117         asm volatile ("");
1118         vmcs_writel(field+1, value >> 32);
1119 #endif
1120 }
1121
1122 static void vmcs_clear_bits(unsigned long field, u32 mask)
1123 {
1124         vmcs_writel(field, vmcs_readl(field) & ~mask);
1125 }
1126
1127 static void vmcs_set_bits(unsigned long field, u32 mask)
1128 {
1129         vmcs_writel(field, vmcs_readl(field) | mask);
1130 }
1131
1132 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1133 {
1134         vmx->segment_cache.bitmask = 0;
1135 }
1136
1137 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1138                                        unsigned field)
1139 {
1140         bool ret;
1141         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1142
1143         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1144                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1145                 vmx->segment_cache.bitmask = 0;
1146         }
1147         ret = vmx->segment_cache.bitmask & mask;
1148         vmx->segment_cache.bitmask |= mask;
1149         return ret;
1150 }
1151
1152 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1153 {
1154         u16 *p = &vmx->segment_cache.seg[seg].selector;
1155
1156         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1157                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1158         return *p;
1159 }
1160
1161 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1162 {
1163         ulong *p = &vmx->segment_cache.seg[seg].base;
1164
1165         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1166                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1167         return *p;
1168 }
1169
1170 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1171 {
1172         u32 *p = &vmx->segment_cache.seg[seg].limit;
1173
1174         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1175                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1176         return *p;
1177 }
1178
1179 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1180 {
1181         u32 *p = &vmx->segment_cache.seg[seg].ar;
1182
1183         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1184                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1185         return *p;
1186 }
1187
1188 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1189 {
1190         u32 eb;
1191
1192         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1193              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1194         if ((vcpu->guest_debug &
1195              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1196             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1197                 eb |= 1u << BP_VECTOR;
1198         if (to_vmx(vcpu)->rmode.vm86_active)
1199                 eb = ~0;
1200         if (enable_ept)
1201                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1202         if (vcpu->fpu_active)
1203                 eb &= ~(1u << NM_VECTOR);
1204
1205         /* When we are running a nested L2 guest and L1 specified for it a
1206          * certain exception bitmap, we must trap the same exceptions and pass
1207          * them to L1. When running L2, we will only handle the exceptions
1208          * specified above if L1 did not want them.
1209          */
1210         if (is_guest_mode(vcpu))
1211                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1212
1213         vmcs_write32(EXCEPTION_BITMAP, eb);
1214 }
1215
1216 static void clear_atomic_switch_msr_special(unsigned long entry,
1217                 unsigned long exit)
1218 {
1219         vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1220         vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1221 }
1222
1223 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1224 {
1225         unsigned i;
1226         struct msr_autoload *m = &vmx->msr_autoload;
1227
1228         switch (msr) {
1229         case MSR_EFER:
1230                 if (cpu_has_load_ia32_efer) {
1231                         clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1232                                         VM_EXIT_LOAD_IA32_EFER);
1233                         return;
1234                 }
1235                 break;
1236         case MSR_CORE_PERF_GLOBAL_CTRL:
1237                 if (cpu_has_load_perf_global_ctrl) {
1238                         clear_atomic_switch_msr_special(
1239                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1240                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1241                         return;
1242                 }
1243                 break;
1244         }
1245
1246         for (i = 0; i < m->nr; ++i)
1247                 if (m->guest[i].index == msr)
1248                         break;
1249
1250         if (i == m->nr)
1251                 return;
1252         --m->nr;
1253         m->guest[i] = m->guest[m->nr];
1254         m->host[i] = m->host[m->nr];
1255         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1256         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1257 }
1258
1259 static void add_atomic_switch_msr_special(unsigned long entry,
1260                 unsigned long exit, unsigned long guest_val_vmcs,
1261                 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1262 {
1263         vmcs_write64(guest_val_vmcs, guest_val);
1264         vmcs_write64(host_val_vmcs, host_val);
1265         vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1266         vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1267 }
1268
1269 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1270                                   u64 guest_val, u64 host_val)
1271 {
1272         unsigned i;
1273         struct msr_autoload *m = &vmx->msr_autoload;
1274
1275         switch (msr) {
1276         case MSR_EFER:
1277                 if (cpu_has_load_ia32_efer) {
1278                         add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1279                                         VM_EXIT_LOAD_IA32_EFER,
1280                                         GUEST_IA32_EFER,
1281                                         HOST_IA32_EFER,
1282                                         guest_val, host_val);
1283                         return;
1284                 }
1285                 break;
1286         case MSR_CORE_PERF_GLOBAL_CTRL:
1287                 if (cpu_has_load_perf_global_ctrl) {
1288                         add_atomic_switch_msr_special(
1289                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1290                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1291                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1292                                         HOST_IA32_PERF_GLOBAL_CTRL,
1293                                         guest_val, host_val);
1294                         return;
1295                 }
1296                 break;
1297         }
1298
1299         for (i = 0; i < m->nr; ++i)
1300                 if (m->guest[i].index == msr)
1301                         break;
1302
1303         if (i == NR_AUTOLOAD_MSRS) {
1304                 printk_once(KERN_WARNING"Not enough mst switch entries. "
1305                                 "Can't add msr %x\n", msr);
1306                 return;
1307         } else if (i == m->nr) {
1308                 ++m->nr;
1309                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1310                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1311         }
1312
1313         m->guest[i].index = msr;
1314         m->guest[i].value = guest_val;
1315         m->host[i].index = msr;
1316         m->host[i].value = host_val;
1317 }
1318
1319 static void reload_tss(void)
1320 {
1321         /*
1322          * VT restores TR but not its size.  Useless.
1323          */
1324         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1325         struct desc_struct *descs;
1326
1327         descs = (void *)gdt->address;
1328         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1329         load_TR_desc();
1330 }
1331
1332 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1333 {
1334         u64 guest_efer;
1335         u64 ignore_bits;
1336
1337         guest_efer = vmx->vcpu.arch.efer;
1338
1339         /*
1340          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1341          * outside long mode
1342          */
1343         ignore_bits = EFER_NX | EFER_SCE;
1344 #ifdef CONFIG_X86_64
1345         ignore_bits |= EFER_LMA | EFER_LME;
1346         /* SCE is meaningful only in long mode on Intel */
1347         if (guest_efer & EFER_LMA)
1348                 ignore_bits &= ~(u64)EFER_SCE;
1349 #endif
1350         guest_efer &= ~ignore_bits;
1351         guest_efer |= host_efer & ignore_bits;
1352         vmx->guest_msrs[efer_offset].data = guest_efer;
1353         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1354
1355         clear_atomic_switch_msr(vmx, MSR_EFER);
1356         /* On ept, can't emulate nx, and must switch nx atomically */
1357         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1358                 guest_efer = vmx->vcpu.arch.efer;
1359                 if (!(guest_efer & EFER_LMA))
1360                         guest_efer &= ~EFER_LME;
1361                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1362                 return false;
1363         }
1364
1365         return true;
1366 }
1367
1368 static unsigned long segment_base(u16 selector)
1369 {
1370         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1371         struct desc_struct *d;
1372         unsigned long table_base;
1373         unsigned long v;
1374
1375         if (!(selector & ~3))
1376                 return 0;
1377
1378         table_base = gdt->address;
1379
1380         if (selector & 4) {           /* from ldt */
1381                 u16 ldt_selector = kvm_read_ldt();
1382
1383                 if (!(ldt_selector & ~3))
1384                         return 0;
1385
1386                 table_base = segment_base(ldt_selector);
1387         }
1388         d = (struct desc_struct *)(table_base + (selector & ~7));
1389         v = get_desc_base(d);
1390 #ifdef CONFIG_X86_64
1391        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1392                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1393 #endif
1394         return v;
1395 }
1396
1397 static inline unsigned long kvm_read_tr_base(void)
1398 {
1399         u16 tr;
1400         asm("str %0" : "=g"(tr));
1401         return segment_base(tr);
1402 }
1403
1404 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1405 {
1406         struct vcpu_vmx *vmx = to_vmx(vcpu);
1407         int i;
1408
1409         if (vmx->host_state.loaded)
1410                 return;
1411
1412         vmx->host_state.loaded = 1;
1413         /*
1414          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1415          * allow segment selectors with cpl > 0 or ti == 1.
1416          */
1417         vmx->host_state.ldt_sel = kvm_read_ldt();
1418         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1419         savesegment(fs, vmx->host_state.fs_sel);
1420         if (!(vmx->host_state.fs_sel & 7)) {
1421                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1422                 vmx->host_state.fs_reload_needed = 0;
1423         } else {
1424                 vmcs_write16(HOST_FS_SELECTOR, 0);
1425                 vmx->host_state.fs_reload_needed = 1;
1426         }
1427         savesegment(gs, vmx->host_state.gs_sel);
1428         if (!(vmx->host_state.gs_sel & 7))
1429                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1430         else {
1431                 vmcs_write16(HOST_GS_SELECTOR, 0);
1432                 vmx->host_state.gs_ldt_reload_needed = 1;
1433         }
1434
1435 #ifdef CONFIG_X86_64
1436         savesegment(ds, vmx->host_state.ds_sel);
1437         savesegment(es, vmx->host_state.es_sel);
1438 #endif
1439
1440 #ifdef CONFIG_X86_64
1441         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1442         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1443 #else
1444         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1445         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1446 #endif
1447
1448 #ifdef CONFIG_X86_64
1449         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1450         if (is_long_mode(&vmx->vcpu))
1451                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1452 #endif
1453         for (i = 0; i < vmx->save_nmsrs; ++i)
1454                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1455                                    vmx->guest_msrs[i].data,
1456                                    vmx->guest_msrs[i].mask);
1457 }
1458
1459 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1460 {
1461         if (!vmx->host_state.loaded)
1462                 return;
1463
1464         ++vmx->vcpu.stat.host_state_reload;
1465         vmx->host_state.loaded = 0;
1466 #ifdef CONFIG_X86_64
1467         if (is_long_mode(&vmx->vcpu))
1468                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1469 #endif
1470         if (vmx->host_state.gs_ldt_reload_needed) {
1471                 kvm_load_ldt(vmx->host_state.ldt_sel);
1472 #ifdef CONFIG_X86_64
1473                 load_gs_index(vmx->host_state.gs_sel);
1474 #else
1475                 loadsegment(gs, vmx->host_state.gs_sel);
1476 #endif
1477         }
1478         if (vmx->host_state.fs_reload_needed)
1479                 loadsegment(fs, vmx->host_state.fs_sel);
1480 #ifdef CONFIG_X86_64
1481         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1482                 loadsegment(ds, vmx->host_state.ds_sel);
1483                 loadsegment(es, vmx->host_state.es_sel);
1484         }
1485 #else
1486         /*
1487          * The sysexit path does not restore ds/es, so we must set them to
1488          * a reasonable value ourselves.
1489          */
1490         loadsegment(ds, __USER_DS);
1491         loadsegment(es, __USER_DS);
1492 #endif
1493         reload_tss();
1494 #ifdef CONFIG_X86_64
1495         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1496 #endif
1497         if (user_has_fpu())
1498                 clts();
1499         load_gdt(&__get_cpu_var(host_gdt));
1500 }
1501
1502 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1503 {
1504         preempt_disable();
1505         __vmx_load_host_state(vmx);
1506         preempt_enable();
1507 }
1508
1509 /*
1510  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1511  * vcpu mutex is already taken.
1512  */
1513 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1514 {
1515         struct vcpu_vmx *vmx = to_vmx(vcpu);
1516         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1517
1518         if (!vmm_exclusive)
1519                 kvm_cpu_vmxon(phys_addr);
1520         else if (vmx->loaded_vmcs->cpu != cpu)
1521                 loaded_vmcs_clear(vmx->loaded_vmcs);
1522
1523         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1524                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1525                 vmcs_load(vmx->loaded_vmcs->vmcs);
1526         }
1527
1528         if (vmx->loaded_vmcs->cpu != cpu) {
1529                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1530                 unsigned long sysenter_esp;
1531
1532                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1533                 local_irq_disable();
1534                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1535                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1536                 local_irq_enable();
1537
1538                 /*
1539                  * Linux uses per-cpu TSS and GDT, so set these when switching
1540                  * processors.
1541                  */
1542                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1543                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1544
1545                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1546                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1547                 vmx->loaded_vmcs->cpu = cpu;
1548         }
1549 }
1550
1551 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1552 {
1553         __vmx_load_host_state(to_vmx(vcpu));
1554         if (!vmm_exclusive) {
1555                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1556                 vcpu->cpu = -1;
1557                 kvm_cpu_vmxoff();
1558         }
1559 }
1560
1561 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1562 {
1563         ulong cr0;
1564
1565         if (vcpu->fpu_active)
1566                 return;
1567         vcpu->fpu_active = 1;
1568         cr0 = vmcs_readl(GUEST_CR0);
1569         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1570         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1571         vmcs_writel(GUEST_CR0, cr0);
1572         update_exception_bitmap(vcpu);
1573         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1574         if (is_guest_mode(vcpu))
1575                 vcpu->arch.cr0_guest_owned_bits &=
1576                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1577         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1578 }
1579
1580 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1581
1582 /*
1583  * Return the cr0 value that a nested guest would read. This is a combination
1584  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1585  * its hypervisor (cr0_read_shadow).
1586  */
1587 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1588 {
1589         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1590                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1591 }
1592 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1593 {
1594         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1595                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1596 }
1597
1598 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1599 {
1600         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1601          * set this *before* calling this function.
1602          */
1603         vmx_decache_cr0_guest_bits(vcpu);
1604         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1605         update_exception_bitmap(vcpu);
1606         vcpu->arch.cr0_guest_owned_bits = 0;
1607         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1608         if (is_guest_mode(vcpu)) {
1609                 /*
1610                  * L1's specified read shadow might not contain the TS bit,
1611                  * so now that we turned on shadowing of this bit, we need to
1612                  * set this bit of the shadow. Like in nested_vmx_run we need
1613                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1614                  * up-to-date here because we just decached cr0.TS (and we'll
1615                  * only update vmcs12->guest_cr0 on nested exit).
1616                  */
1617                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1618                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1619                         (vcpu->arch.cr0 & X86_CR0_TS);
1620                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1621         } else
1622                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1623 }
1624
1625 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1626 {
1627         unsigned long rflags, save_rflags;
1628
1629         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1630                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1631                 rflags = vmcs_readl(GUEST_RFLAGS);
1632                 if (to_vmx(vcpu)->rmode.vm86_active) {
1633                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1634                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1635                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1636                 }
1637                 to_vmx(vcpu)->rflags = rflags;
1638         }
1639         return to_vmx(vcpu)->rflags;
1640 }
1641
1642 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1643 {
1644         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1645         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1646         to_vmx(vcpu)->rflags = rflags;
1647         if (to_vmx(vcpu)->rmode.vm86_active) {
1648                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1649                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1650         }
1651         vmcs_writel(GUEST_RFLAGS, rflags);
1652 }
1653
1654 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1655 {
1656         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1657         int ret = 0;
1658
1659         if (interruptibility & GUEST_INTR_STATE_STI)
1660                 ret |= KVM_X86_SHADOW_INT_STI;
1661         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1662                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1663
1664         return ret & mask;
1665 }
1666
1667 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1668 {
1669         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1670         u32 interruptibility = interruptibility_old;
1671
1672         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1673
1674         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1675                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1676         else if (mask & KVM_X86_SHADOW_INT_STI)
1677                 interruptibility |= GUEST_INTR_STATE_STI;
1678
1679         if ((interruptibility != interruptibility_old))
1680                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1681 }
1682
1683 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1684 {
1685         unsigned long rip;
1686
1687         rip = kvm_rip_read(vcpu);
1688         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1689         kvm_rip_write(vcpu, rip);
1690
1691         /* skipping an emulated instruction also counts */
1692         vmx_set_interrupt_shadow(vcpu, 0);
1693 }
1694
1695 /*
1696  * KVM wants to inject page-faults which it got to the guest. This function
1697  * checks whether in a nested guest, we need to inject them to L1 or L2.
1698  * This function assumes it is called with the exit reason in vmcs02 being
1699  * a #PF exception (this is the only case in which KVM injects a #PF when L2
1700  * is running).
1701  */
1702 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1703 {
1704         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1705
1706         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1707         if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
1708                 return 0;
1709
1710         nested_vmx_vmexit(vcpu);
1711         return 1;
1712 }
1713
1714 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1715                                 bool has_error_code, u32 error_code,
1716                                 bool reinject)
1717 {
1718         struct vcpu_vmx *vmx = to_vmx(vcpu);
1719         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1720
1721         if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1722                 nested_pf_handled(vcpu))
1723                 return;
1724
1725         if (has_error_code) {
1726                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1727                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1728         }
1729
1730         if (vmx->rmode.vm86_active) {
1731                 int inc_eip = 0;
1732                 if (kvm_exception_is_soft(nr))
1733                         inc_eip = vcpu->arch.event_exit_inst_len;
1734                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1735                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1736                 return;
1737         }
1738
1739         if (kvm_exception_is_soft(nr)) {
1740                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1741                              vmx->vcpu.arch.event_exit_inst_len);
1742                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1743         } else
1744                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1745
1746         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1747 }
1748
1749 static bool vmx_rdtscp_supported(void)
1750 {
1751         return cpu_has_vmx_rdtscp();
1752 }
1753
1754 /*
1755  * Swap MSR entry in host/guest MSR entry array.
1756  */
1757 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1758 {
1759         struct shared_msr_entry tmp;
1760
1761         tmp = vmx->guest_msrs[to];
1762         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1763         vmx->guest_msrs[from] = tmp;
1764 }
1765
1766 /*
1767  * Set up the vmcs to automatically save and restore system
1768  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1769  * mode, as fiddling with msrs is very expensive.
1770  */
1771 static void setup_msrs(struct vcpu_vmx *vmx)
1772 {
1773         int save_nmsrs, index;
1774         unsigned long *msr_bitmap;
1775
1776         save_nmsrs = 0;
1777 #ifdef CONFIG_X86_64
1778         if (is_long_mode(&vmx->vcpu)) {
1779                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1780                 if (index >= 0)
1781                         move_msr_up(vmx, index, save_nmsrs++);
1782                 index = __find_msr_index(vmx, MSR_LSTAR);
1783                 if (index >= 0)
1784                         move_msr_up(vmx, index, save_nmsrs++);
1785                 index = __find_msr_index(vmx, MSR_CSTAR);
1786                 if (index >= 0)
1787                         move_msr_up(vmx, index, save_nmsrs++);
1788                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1789                 if (index >= 0 && vmx->rdtscp_enabled)
1790                         move_msr_up(vmx, index, save_nmsrs++);
1791                 /*
1792                  * MSR_STAR is only needed on long mode guests, and only
1793                  * if efer.sce is enabled.
1794                  */
1795                 index = __find_msr_index(vmx, MSR_STAR);
1796                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1797                         move_msr_up(vmx, index, save_nmsrs++);
1798         }
1799 #endif
1800         index = __find_msr_index(vmx, MSR_EFER);
1801         if (index >= 0 && update_transition_efer(vmx, index))
1802                 move_msr_up(vmx, index, save_nmsrs++);
1803
1804         vmx->save_nmsrs = save_nmsrs;
1805
1806         if (cpu_has_vmx_msr_bitmap()) {
1807                 if (is_long_mode(&vmx->vcpu))
1808                         msr_bitmap = vmx_msr_bitmap_longmode;
1809                 else
1810                         msr_bitmap = vmx_msr_bitmap_legacy;
1811
1812                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1813         }
1814 }
1815
1816 /*
1817  * reads and returns guest's timestamp counter "register"
1818  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1819  */
1820 static u64 guest_read_tsc(void)
1821 {
1822         u64 host_tsc, tsc_offset;
1823
1824         rdtscll(host_tsc);
1825         tsc_offset = vmcs_read64(TSC_OFFSET);
1826         return host_tsc + tsc_offset;
1827 }
1828
1829 /*
1830  * Like guest_read_tsc, but always returns L1's notion of the timestamp
1831  * counter, even if a nested guest (L2) is currently running.
1832  */
1833 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu)
1834 {
1835         u64 host_tsc, tsc_offset;
1836
1837         rdtscll(host_tsc);
1838         tsc_offset = is_guest_mode(vcpu) ?
1839                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1840                 vmcs_read64(TSC_OFFSET);
1841         return host_tsc + tsc_offset;
1842 }
1843
1844 /*
1845  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
1846  * software catchup for faster rates on slower CPUs.
1847  */
1848 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1849 {
1850         if (!scale)
1851                 return;
1852
1853         if (user_tsc_khz > tsc_khz) {
1854                 vcpu->arch.tsc_catchup = 1;
1855                 vcpu->arch.tsc_always_catchup = 1;
1856         } else
1857                 WARN(1, "user requested TSC rate below hardware speed\n");
1858 }
1859
1860 /*
1861  * writes 'offset' into guest's timestamp counter offset register
1862  */
1863 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1864 {
1865         if (is_guest_mode(vcpu)) {
1866                 /*
1867                  * We're here if L1 chose not to trap WRMSR to TSC. According
1868                  * to the spec, this should set L1's TSC; The offset that L1
1869                  * set for L2 remains unchanged, and still needs to be added
1870                  * to the newly set TSC to get L2's TSC.
1871                  */
1872                 struct vmcs12 *vmcs12;
1873                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1874                 /* recalculate vmcs02.TSC_OFFSET: */
1875                 vmcs12 = get_vmcs12(vcpu);
1876                 vmcs_write64(TSC_OFFSET, offset +
1877                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1878                          vmcs12->tsc_offset : 0));
1879         } else {
1880                 vmcs_write64(TSC_OFFSET, offset);
1881         }
1882 }
1883
1884 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1885 {
1886         u64 offset = vmcs_read64(TSC_OFFSET);
1887         vmcs_write64(TSC_OFFSET, offset + adjustment);
1888         if (is_guest_mode(vcpu)) {
1889                 /* Even when running L2, the adjustment needs to apply to L1 */
1890                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1891         }
1892 }
1893
1894 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1895 {
1896         return target_tsc - native_read_tsc();
1897 }
1898
1899 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1900 {
1901         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1902         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1903 }
1904
1905 /*
1906  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1907  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1908  * all guests if the "nested" module option is off, and can also be disabled
1909  * for a single guest by disabling its VMX cpuid bit.
1910  */
1911 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1912 {
1913         return nested && guest_cpuid_has_vmx(vcpu);
1914 }
1915
1916 /*
1917  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1918  * returned for the various VMX controls MSRs when nested VMX is enabled.
1919  * The same values should also be used to verify that vmcs12 control fields are
1920  * valid during nested entry from L1 to L2.
1921  * Each of these control msrs has a low and high 32-bit half: A low bit is on
1922  * if the corresponding bit in the (32-bit) control field *must* be on, and a
1923  * bit in the high half is on if the corresponding bit in the control field
1924  * may be on. See also vmx_control_verify().
1925  * TODO: allow these variables to be modified (downgraded) by module options
1926  * or other means.
1927  */
1928 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1929 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1930 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1931 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1932 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1933 static __init void nested_vmx_setup_ctls_msrs(void)
1934 {
1935         /*
1936          * Note that as a general rule, the high half of the MSRs (bits in
1937          * the control fields which may be 1) should be initialized by the
1938          * intersection of the underlying hardware's MSR (i.e., features which
1939          * can be supported) and the list of features we want to expose -
1940          * because they are known to be properly supported in our code.
1941          * Also, usually, the low half of the MSRs (bits which must be 1) can
1942          * be set to 0, meaning that L1 may turn off any of these bits. The
1943          * reason is that if one of these bits is necessary, it will appear
1944          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1945          * fields of vmcs01 and vmcs02, will turn these bits off - and
1946          * nested_vmx_exit_handled() will not pass related exits to L1.
1947          * These rules have exceptions below.
1948          */
1949
1950         /* pin-based controls */
1951         /*
1952          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1953          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1954          */
1955         nested_vmx_pinbased_ctls_low = 0x16 ;
1956         nested_vmx_pinbased_ctls_high = 0x16 |
1957                 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1958                 PIN_BASED_VIRTUAL_NMIS;
1959
1960         /* exit controls */
1961         nested_vmx_exit_ctls_low = 0;
1962         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
1963 #ifdef CONFIG_X86_64
1964         nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1965 #else
1966         nested_vmx_exit_ctls_high = 0;
1967 #endif
1968
1969         /* entry controls */
1970         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1971                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1972         nested_vmx_entry_ctls_low = 0;
1973         nested_vmx_entry_ctls_high &=
1974                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1975
1976         /* cpu-based controls */
1977         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1978                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1979         nested_vmx_procbased_ctls_low = 0;
1980         nested_vmx_procbased_ctls_high &=
1981                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1982                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1983                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1984                 CPU_BASED_CR3_STORE_EXITING |
1985 #ifdef CONFIG_X86_64
1986                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1987 #endif
1988                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1989                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1990                 CPU_BASED_RDPMC_EXITING |
1991                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1992         /*
1993          * We can allow some features even when not supported by the
1994          * hardware. For example, L1 can specify an MSR bitmap - and we
1995          * can use it to avoid exits to L1 - even when L0 runs L2
1996          * without MSR bitmaps.
1997          */
1998         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1999
2000         /* secondary cpu-based controls */
2001         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2002                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2003         nested_vmx_secondary_ctls_low = 0;
2004         nested_vmx_secondary_ctls_high &=
2005                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2006 }
2007
2008 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2009 {
2010         /*
2011          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2012          */
2013         return ((control & high) | low) == control;
2014 }
2015
2016 static inline u64 vmx_control_msr(u32 low, u32 high)
2017 {
2018         return low | ((u64)high << 32);
2019 }
2020
2021 /*
2022  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2023  * also let it use VMX-specific MSRs.
2024  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2025  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2026  * like all other MSRs).
2027  */
2028 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2029 {
2030         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2031                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2032                 /*
2033                  * According to the spec, processors which do not support VMX
2034                  * should throw a #GP(0) when VMX capability MSRs are read.
2035                  */
2036                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2037                 return 1;
2038         }
2039
2040         switch (msr_index) {
2041         case MSR_IA32_FEATURE_CONTROL:
2042                 *pdata = 0;
2043                 break;
2044         case MSR_IA32_VMX_BASIC:
2045                 /*
2046                  * This MSR reports some information about VMX support. We
2047                  * should return information about the VMX we emulate for the
2048                  * guest, and the VMCS structure we give it - not about the
2049                  * VMX support of the underlying hardware.
2050                  */
2051                 *pdata = VMCS12_REVISION |
2052                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2053                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2054                 break;
2055         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2056         case MSR_IA32_VMX_PINBASED_CTLS:
2057                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2058                                         nested_vmx_pinbased_ctls_high);
2059                 break;
2060         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2061         case MSR_IA32_VMX_PROCBASED_CTLS:
2062                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2063                                         nested_vmx_procbased_ctls_high);
2064                 break;
2065         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2066         case MSR_IA32_VMX_EXIT_CTLS:
2067                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2068                                         nested_vmx_exit_ctls_high);
2069                 break;
2070         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2071         case MSR_IA32_VMX_ENTRY_CTLS:
2072                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2073                                         nested_vmx_entry_ctls_high);
2074                 break;
2075         case MSR_IA32_VMX_MISC:
2076                 *pdata = 0;
2077                 break;
2078         /*
2079          * These MSRs specify bits which the guest must keep fixed (on or off)
2080          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2081          * We picked the standard core2 setting.
2082          */
2083 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2084 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2085         case MSR_IA32_VMX_CR0_FIXED0:
2086                 *pdata = VMXON_CR0_ALWAYSON;
2087                 break;
2088         case MSR_IA32_VMX_CR0_FIXED1:
2089                 *pdata = -1ULL;
2090                 break;
2091         case MSR_IA32_VMX_CR4_FIXED0:
2092                 *pdata = VMXON_CR4_ALWAYSON;
2093                 break;
2094         case MSR_IA32_VMX_CR4_FIXED1:
2095                 *pdata = -1ULL;
2096                 break;
2097         case MSR_IA32_VMX_VMCS_ENUM:
2098                 *pdata = 0x1f;
2099                 break;
2100         case MSR_IA32_VMX_PROCBASED_CTLS2:
2101                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2102                                         nested_vmx_secondary_ctls_high);
2103                 break;
2104         case MSR_IA32_VMX_EPT_VPID_CAP:
2105                 /* Currently, no nested ept or nested vpid */
2106                 *pdata = 0;
2107                 break;
2108         default:
2109                 return 0;
2110         }
2111
2112         return 1;
2113 }
2114
2115 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2116 {
2117         if (!nested_vmx_allowed(vcpu))
2118                 return 0;
2119
2120         if (msr_index == MSR_IA32_FEATURE_CONTROL)
2121                 /* TODO: the right thing. */
2122                 return 1;
2123         /*
2124          * No need to treat VMX capability MSRs specially: If we don't handle
2125          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2126          */
2127         return 0;
2128 }
2129
2130 /*
2131  * Reads an msr value (of 'msr_index') into 'pdata'.
2132  * Returns 0 on success, non-0 otherwise.
2133  * Assumes vcpu_load() was already called.
2134  */
2135 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2136 {
2137         u64 data;
2138         struct shared_msr_entry *msr;
2139
2140         if (!pdata) {
2141                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2142                 return -EINVAL;
2143         }
2144
2145         switch (msr_index) {
2146 #ifdef CONFIG_X86_64
2147         case MSR_FS_BASE:
2148                 data = vmcs_readl(GUEST_FS_BASE);
2149                 break;
2150         case MSR_GS_BASE:
2151                 data = vmcs_readl(GUEST_GS_BASE);
2152                 break;
2153         case MSR_KERNEL_GS_BASE:
2154                 vmx_load_host_state(to_vmx(vcpu));
2155                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2156                 break;
2157 #endif
2158         case MSR_EFER:
2159                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2160         case MSR_IA32_TSC:
2161                 data = guest_read_tsc();
2162                 break;
2163         case MSR_IA32_SYSENTER_CS:
2164                 data = vmcs_read32(GUEST_SYSENTER_CS);
2165                 break;
2166         case MSR_IA32_SYSENTER_EIP:
2167                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2168                 break;
2169         case MSR_IA32_SYSENTER_ESP:
2170                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2171                 break;
2172         case MSR_TSC_AUX:
2173                 if (!to_vmx(vcpu)->rdtscp_enabled)
2174                         return 1;
2175                 /* Otherwise falls through */
2176         default:
2177                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2178                         return 0;
2179                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2180                 if (msr) {
2181                         data = msr->data;
2182                         break;
2183                 }
2184                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2185         }
2186
2187         *pdata = data;
2188         return 0;
2189 }
2190
2191 /*
2192  * Writes msr value into into the appropriate "register".
2193  * Returns 0 on success, non-0 otherwise.
2194  * Assumes vcpu_load() was already called.
2195  */
2196 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2197 {
2198         struct vcpu_vmx *vmx = to_vmx(vcpu);
2199         struct shared_msr_entry *msr;
2200         int ret = 0;
2201
2202         switch (msr_index) {
2203         case MSR_EFER:
2204                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2205                 break;
2206 #ifdef CONFIG_X86_64
2207         case MSR_FS_BASE:
2208                 vmx_segment_cache_clear(vmx);
2209                 vmcs_writel(GUEST_FS_BASE, data);
2210                 break;
2211         case MSR_GS_BASE:
2212                 vmx_segment_cache_clear(vmx);
2213                 vmcs_writel(GUEST_GS_BASE, data);
2214                 break;
2215         case MSR_KERNEL_GS_BASE:
2216                 vmx_load_host_state(vmx);
2217                 vmx->msr_guest_kernel_gs_base = data;
2218                 break;
2219 #endif
2220         case MSR_IA32_SYSENTER_CS:
2221                 vmcs_write32(GUEST_SYSENTER_CS, data);
2222                 break;
2223         case MSR_IA32_SYSENTER_EIP:
2224                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2225                 break;
2226         case MSR_IA32_SYSENTER_ESP:
2227                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2228                 break;
2229         case MSR_IA32_TSC:
2230                 kvm_write_tsc(vcpu, data);
2231                 break;
2232         case MSR_IA32_CR_PAT:
2233                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2234                         vmcs_write64(GUEST_IA32_PAT, data);
2235                         vcpu->arch.pat = data;
2236                         break;
2237                 }
2238                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2239                 break;
2240         case MSR_TSC_AUX:
2241                 if (!vmx->rdtscp_enabled)
2242                         return 1;
2243                 /* Check reserved bit, higher 32 bits should be zero */
2244                 if ((data >> 32) != 0)
2245                         return 1;
2246                 /* Otherwise falls through */
2247         default:
2248                 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2249                         break;
2250                 msr = find_msr_entry(vmx, msr_index);
2251                 if (msr) {
2252                         msr->data = data;
2253                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2254                                 preempt_disable();
2255                                 kvm_set_shared_msr(msr->index, msr->data,
2256                                                    msr->mask);
2257                                 preempt_enable();
2258                         }
2259                         break;
2260                 }
2261                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2262         }
2263
2264         return ret;
2265 }
2266
2267 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2268 {
2269         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2270         switch (reg) {
2271         case VCPU_REGS_RSP:
2272                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2273                 break;
2274         case VCPU_REGS_RIP:
2275                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2276                 break;
2277         case VCPU_EXREG_PDPTR:
2278                 if (enable_ept)
2279                         ept_save_pdptrs(vcpu);
2280                 break;
2281         default:
2282                 break;
2283         }
2284 }
2285
2286 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
2287 {
2288         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2289                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2290         else
2291                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2292
2293         update_exception_bitmap(vcpu);
2294 }
2295
2296 static __init int cpu_has_kvm_support(void)
2297 {
2298         return cpu_has_vmx();
2299 }
2300
2301 static __init int vmx_disabled_by_bios(void)
2302 {
2303         u64 msr;
2304
2305         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2306         if (msr & FEATURE_CONTROL_LOCKED) {
2307                 /* launched w/ TXT and VMX disabled */
2308                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2309                         && tboot_enabled())
2310                         return 1;
2311                 /* launched w/o TXT and VMX only enabled w/ TXT */
2312                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2313                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2314                         && !tboot_enabled()) {
2315                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2316                                 "activate TXT before enabling KVM\n");
2317                         return 1;
2318                 }
2319                 /* launched w/o TXT and VMX disabled */
2320                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2321                         && !tboot_enabled())
2322                         return 1;
2323         }
2324
2325         return 0;
2326 }
2327
2328 static void kvm_cpu_vmxon(u64 addr)
2329 {
2330         asm volatile (ASM_VMX_VMXON_RAX
2331                         : : "a"(&addr), "m"(addr)
2332                         : "memory", "cc");
2333 }
2334
2335 static int hardware_enable(void *garbage)
2336 {
2337         int cpu = raw_smp_processor_id();
2338         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2339         u64 old, test_bits;
2340
2341         if (read_cr4() & X86_CR4_VMXE)
2342                 return -EBUSY;
2343
2344         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2345         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2346
2347         test_bits = FEATURE_CONTROL_LOCKED;
2348         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2349         if (tboot_enabled())
2350                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2351
2352         if ((old & test_bits) != test_bits) {
2353                 /* enable and lock */
2354                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2355         }
2356         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2357
2358         if (vmm_exclusive) {
2359                 kvm_cpu_vmxon(phys_addr);
2360                 ept_sync_global();
2361         }
2362
2363         store_gdt(&__get_cpu_var(host_gdt));
2364
2365         return 0;
2366 }
2367
2368 static void vmclear_local_loaded_vmcss(void)
2369 {
2370         int cpu = raw_smp_processor_id();
2371         struct loaded_vmcs *v, *n;
2372
2373         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2374                                  loaded_vmcss_on_cpu_link)
2375                 __loaded_vmcs_clear(v);
2376 }
2377
2378
2379 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2380  * tricks.
2381  */
2382 static void kvm_cpu_vmxoff(void)
2383 {
2384         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2385 }
2386
2387 static void hardware_disable(void *garbage)
2388 {
2389         if (vmm_exclusive) {
2390                 vmclear_local_loaded_vmcss();
2391                 kvm_cpu_vmxoff();
2392         }
2393         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2394 }
2395
2396 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2397                                       u32 msr, u32 *result)
2398 {
2399         u32 vmx_msr_low, vmx_msr_high;
2400         u32 ctl = ctl_min | ctl_opt;
2401
2402         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2403
2404         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2405         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2406
2407         /* Ensure minimum (required) set of control bits are supported. */
2408         if (ctl_min & ~ctl)
2409                 return -EIO;
2410
2411         *result = ctl;
2412         return 0;
2413 }
2414
2415 static __init bool allow_1_setting(u32 msr, u32 ctl)
2416 {
2417         u32 vmx_msr_low, vmx_msr_high;
2418
2419         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2420         return vmx_msr_high & ctl;
2421 }
2422
2423 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2424 {
2425         u32 vmx_msr_low, vmx_msr_high;
2426         u32 min, opt, min2, opt2;
2427         u32 _pin_based_exec_control = 0;
2428         u32 _cpu_based_exec_control = 0;
2429         u32 _cpu_based_2nd_exec_control = 0;
2430         u32 _vmexit_control = 0;
2431         u32 _vmentry_control = 0;
2432
2433         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2434         opt = PIN_BASED_VIRTUAL_NMIS;
2435         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2436                                 &_pin_based_exec_control) < 0)
2437                 return -EIO;
2438
2439         min = CPU_BASED_HLT_EXITING |
2440 #ifdef CONFIG_X86_64
2441               CPU_BASED_CR8_LOAD_EXITING |
2442               CPU_BASED_CR8_STORE_EXITING |
2443 #endif
2444               CPU_BASED_CR3_LOAD_EXITING |
2445               CPU_BASED_CR3_STORE_EXITING |
2446               CPU_BASED_USE_IO_BITMAPS |
2447               CPU_BASED_MOV_DR_EXITING |
2448               CPU_BASED_USE_TSC_OFFSETING |
2449               CPU_BASED_MWAIT_EXITING |
2450               CPU_BASED_MONITOR_EXITING |
2451               CPU_BASED_INVLPG_EXITING |
2452               CPU_BASED_RDPMC_EXITING;
2453
2454         opt = CPU_BASED_TPR_SHADOW |
2455               CPU_BASED_USE_MSR_BITMAPS |
2456               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2457         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2458                                 &_cpu_based_exec_control) < 0)
2459                 return -EIO;
2460 #ifdef CONFIG_X86_64
2461         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2462                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2463                                            ~CPU_BASED_CR8_STORE_EXITING;
2464 #endif
2465         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2466                 min2 = 0;
2467                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2468                         SECONDARY_EXEC_WBINVD_EXITING |
2469                         SECONDARY_EXEC_ENABLE_VPID |
2470                         SECONDARY_EXEC_ENABLE_EPT |
2471                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2472                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2473                         SECONDARY_EXEC_RDTSCP;
2474                 if (adjust_vmx_controls(min2, opt2,
2475                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2476                                         &_cpu_based_2nd_exec_control) < 0)
2477                         return -EIO;
2478         }
2479 #ifndef CONFIG_X86_64
2480         if (!(_cpu_based_2nd_exec_control &
2481                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2482                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2483 #endif
2484         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2485                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2486                    enabled */
2487                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2488                                              CPU_BASED_CR3_STORE_EXITING |
2489                                              CPU_BASED_INVLPG_EXITING);
2490                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2491                       vmx_capability.ept, vmx_capability.vpid);
2492         }
2493
2494         min = 0;
2495 #ifdef CONFIG_X86_64
2496         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2497 #endif
2498         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2499         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2500                                 &_vmexit_control) < 0)
2501                 return -EIO;
2502
2503         min = 0;
2504         opt = VM_ENTRY_LOAD_IA32_PAT;
2505         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2506                                 &_vmentry_control) < 0)
2507                 return -EIO;
2508
2509         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2510
2511         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2512         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2513                 return -EIO;
2514
2515 #ifdef CONFIG_X86_64
2516         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2517         if (vmx_msr_high & (1u<<16))
2518                 return -EIO;
2519 #endif
2520
2521         /* Require Write-Back (WB) memory type for VMCS accesses. */
2522         if (((vmx_msr_high >> 18) & 15) != 6)
2523                 return -EIO;
2524
2525         vmcs_conf->size = vmx_msr_high & 0x1fff;
2526         vmcs_conf->order = get_order(vmcs_config.size);
2527         vmcs_conf->revision_id = vmx_msr_low;
2528
2529         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2530         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2531         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2532         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2533         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2534
2535         cpu_has_load_ia32_efer =
2536                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2537                                 VM_ENTRY_LOAD_IA32_EFER)
2538                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2539                                    VM_EXIT_LOAD_IA32_EFER);
2540
2541         cpu_has_load_perf_global_ctrl =
2542                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2543                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2544                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2545                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2546
2547         /*
2548          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2549          * but due to arrata below it can't be used. Workaround is to use
2550          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2551          *
2552          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2553          *
2554          * AAK155             (model 26)
2555          * AAP115             (model 30)
2556          * AAT100             (model 37)
2557          * BC86,AAY89,BD102   (model 44)
2558          * BA97               (model 46)
2559          *
2560          */
2561         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2562                 switch (boot_cpu_data.x86_model) {
2563                 case 26:
2564                 case 30:
2565                 case 37:
2566                 case 44:
2567                 case 46:
2568                         cpu_has_load_perf_global_ctrl = false;
2569                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2570                                         "does not work properly. Using workaround\n");
2571                         break;
2572                 default:
2573                         break;
2574                 }
2575         }
2576
2577         return 0;
2578 }
2579
2580 static struct vmcs *alloc_vmcs_cpu(int cpu)
2581 {
2582         int node = cpu_to_node(cpu);
2583         struct page *pages;
2584         struct vmcs *vmcs;
2585
2586         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2587         if (!pages)
2588                 return NULL;
2589         vmcs = page_address(pages);
2590         memset(vmcs, 0, vmcs_config.size);
2591         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2592         return vmcs;
2593 }
2594
2595 static struct vmcs *alloc_vmcs(void)
2596 {
2597         return alloc_vmcs_cpu(raw_smp_processor_id());
2598 }
2599
2600 static void free_vmcs(struct vmcs *vmcs)
2601 {
2602         free_pages((unsigned long)vmcs, vmcs_config.order);
2603 }
2604
2605 /*
2606  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2607  */
2608 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2609 {
2610         if (!loaded_vmcs->vmcs)
2611                 return;
2612         loaded_vmcs_clear(loaded_vmcs);
2613         free_vmcs(loaded_vmcs->vmcs);
2614         loaded_vmcs->vmcs = NULL;
2615 }
2616
2617 static void free_kvm_area(void)
2618 {
2619         int cpu;
2620
2621         for_each_possible_cpu(cpu) {
2622                 free_vmcs(per_cpu(vmxarea, cpu));
2623                 per_cpu(vmxarea, cpu) = NULL;
2624         }
2625 }
2626
2627 static __init int alloc_kvm_area(void)
2628 {
2629         int cpu;
2630
2631         for_each_possible_cpu(cpu) {
2632                 struct vmcs *vmcs;
2633
2634                 vmcs = alloc_vmcs_cpu(cpu);
2635                 if (!vmcs) {
2636                         free_kvm_area();
2637                         return -ENOMEM;
2638                 }
2639
2640                 per_cpu(vmxarea, cpu) = vmcs;
2641         }
2642         return 0;
2643 }
2644
2645 static __init int hardware_setup(void)
2646 {
2647         if (setup_vmcs_config(&vmcs_config) < 0)
2648                 return -EIO;
2649
2650         if (boot_cpu_has(X86_FEATURE_NX))
2651                 kvm_enable_efer_bits(EFER_NX);
2652
2653         if (!cpu_has_vmx_vpid())
2654                 enable_vpid = 0;
2655
2656         if (!cpu_has_vmx_ept() ||
2657             !cpu_has_vmx_ept_4levels()) {
2658                 enable_ept = 0;
2659                 enable_unrestricted_guest = 0;
2660                 enable_ept_ad_bits = 0;
2661         }
2662
2663         if (!cpu_has_vmx_ept_ad_bits())
2664                 enable_ept_ad_bits = 0;
2665
2666         if (!cpu_has_vmx_unrestricted_guest())
2667                 enable_unrestricted_guest = 0;
2668
2669         if (!cpu_has_vmx_flexpriority())
2670                 flexpriority_enabled = 0;
2671
2672         if (!cpu_has_vmx_tpr_shadow())
2673                 kvm_x86_ops->update_cr8_intercept = NULL;
2674
2675         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2676                 kvm_disable_largepages();
2677
2678         if (!cpu_has_vmx_ple())
2679                 ple_gap = 0;
2680
2681         if (nested)
2682                 nested_vmx_setup_ctls_msrs();
2683
2684         return alloc_kvm_area();
2685 }
2686
2687 static __exit void hardware_unsetup(void)
2688 {
2689         free_kvm_area();
2690 }
2691
2692 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2693 {
2694         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2695
2696         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
2697                 vmcs_write16(sf->selector, save->selector);
2698                 vmcs_writel(sf->base, save->base);
2699                 vmcs_write32(sf->limit, save->limit);
2700                 vmcs_write32(sf->ar_bytes, save->ar);
2701         } else {
2702                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2703                         << AR_DPL_SHIFT;
2704                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2705         }
2706 }
2707
2708 static void enter_pmode(struct kvm_vcpu *vcpu)
2709 {
2710         unsigned long flags;
2711         struct vcpu_vmx *vmx = to_vmx(vcpu);
2712
2713         vmx->emulation_required = 1;
2714         vmx->rmode.vm86_active = 0;
2715
2716         vmx_segment_cache_clear(vmx);
2717
2718         vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
2719         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2720         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2721         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
2722
2723         flags = vmcs_readl(GUEST_RFLAGS);
2724         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2725         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2726         vmcs_writel(GUEST_RFLAGS, flags);
2727
2728         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2729                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2730
2731         update_exception_bitmap(vcpu);
2732
2733         if (emulate_invalid_guest_state)
2734                 return;
2735
2736         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2737         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2738         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2739         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
2740
2741         vmx_segment_cache_clear(vmx);
2742
2743         vmcs_write16(GUEST_SS_SELECTOR, 0);
2744         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2745
2746         vmcs_write16(GUEST_CS_SELECTOR,
2747                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2748         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2749 }
2750
2751 static gva_t rmode_tss_base(struct kvm *kvm)
2752 {
2753         if (!kvm->arch.tss_addr) {
2754                 struct kvm_memslots *slots;
2755                 struct kvm_memory_slot *slot;
2756                 gfn_t base_gfn;
2757
2758                 slots = kvm_memslots(kvm);
2759                 slot = id_to_memslot(slots, 0);
2760                 base_gfn = slot->base_gfn + slot->npages - 3;
2761
2762                 return base_gfn << PAGE_SHIFT;
2763         }
2764         return kvm->arch.tss_addr;
2765 }
2766
2767 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2768 {
2769         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2770
2771         save->selector = vmcs_read16(sf->selector);
2772         save->base = vmcs_readl(sf->base);
2773         save->limit = vmcs_read32(sf->limit);
2774         save->ar = vmcs_read32(sf->ar_bytes);
2775         vmcs_write16(sf->selector, save->base >> 4);
2776         vmcs_write32(sf->base, save->base & 0xffff0);
2777         vmcs_write32(sf->limit, 0xffff);
2778         vmcs_write32(sf->ar_bytes, 0xf3);
2779         if (save->base & 0xf)
2780                 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2781                             " aligned when entering protected mode (seg=%d)",
2782                             seg);
2783 }
2784
2785 static void enter_rmode(struct kvm_vcpu *vcpu)
2786 {
2787         unsigned long flags;
2788         struct vcpu_vmx *vmx = to_vmx(vcpu);
2789         struct kvm_segment var;
2790
2791         if (enable_unrestricted_guest)
2792                 return;
2793
2794         vmx->emulation_required = 1;
2795         vmx->rmode.vm86_active = 1;
2796
2797         /*
2798          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2799          * vcpu. Call it here with phys address pointing 16M below 4G.
2800          */
2801         if (!vcpu->kvm->arch.tss_addr) {
2802                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2803                              "called before entering vcpu\n");
2804                 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2805                 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2806                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2807         }
2808
2809         vmx_segment_cache_clear(vmx);
2810
2811         vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
2812         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
2813         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2814
2815         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
2816         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2817
2818         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
2819         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2820
2821         flags = vmcs_readl(GUEST_RFLAGS);
2822         vmx->rmode.save_rflags = flags;
2823
2824         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2825
2826         vmcs_writel(GUEST_RFLAGS, flags);
2827         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2828         update_exception_bitmap(vcpu);
2829
2830         if (emulate_invalid_guest_state)
2831                 goto continue_rmode;
2832
2833         vmx_get_segment(vcpu, &var, VCPU_SREG_SS);
2834         vmx_set_segment(vcpu, &var, VCPU_SREG_SS);
2835
2836         vmx_get_segment(vcpu, &var, VCPU_SREG_CS);
2837         vmx_set_segment(vcpu, &var, VCPU_SREG_CS);
2838
2839         vmx_get_segment(vcpu, &var, VCPU_SREG_ES);
2840         vmx_set_segment(vcpu, &var, VCPU_SREG_ES);
2841
2842         vmx_get_segment(vcpu, &var, VCPU_SREG_DS);
2843         vmx_set_segment(vcpu, &var, VCPU_SREG_DS);
2844
2845         vmx_get_segment(vcpu, &var, VCPU_SREG_GS);
2846         vmx_set_segment(vcpu, &var, VCPU_SREG_GS);
2847
2848         vmx_get_segment(vcpu, &var, VCPU_SREG_FS);
2849         vmx_set_segment(vcpu, &var, VCPU_SREG_FS);
2850
2851 continue_rmode:
2852         kvm_mmu_reset_context(vcpu);
2853 }
2854
2855 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2856 {
2857         struct vcpu_vmx *vmx = to_vmx(vcpu);
2858         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2859
2860         if (!msr)
2861                 return;
2862
2863         /*
2864          * Force kernel_gs_base reloading before EFER changes, as control
2865          * of this msr depends on is_long_mode().
2866          */
2867         vmx_load_host_state(to_vmx(vcpu));
2868         vcpu->arch.efer = efer;
2869         if (efer & EFER_LMA) {
2870                 vmcs_write32(VM_ENTRY_CONTROLS,
2871                              vmcs_read32(VM_ENTRY_CONTROLS) |
2872                              VM_ENTRY_IA32E_MODE);
2873                 msr->data = efer;
2874         } else {
2875                 vmcs_write32(VM_ENTRY_CONTROLS,
2876                              vmcs_read32(VM_ENTRY_CONTROLS) &
2877                              ~VM_ENTRY_IA32E_MODE);
2878
2879                 msr->data = efer & ~EFER_LME;
2880         }
2881         setup_msrs(vmx);
2882 }
2883
2884 #ifdef CONFIG_X86_64
2885
2886 static void enter_lmode(struct kvm_vcpu *vcpu)
2887 {
2888         u32 guest_tr_ar;
2889
2890         vmx_segment_cache_clear(to_vmx(vcpu));
2891
2892         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2893         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2894                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2895                                      __func__);
2896                 vmcs_write32(GUEST_TR_AR_BYTES,
2897                              (guest_tr_ar & ~AR_TYPE_MASK)
2898                              | AR_TYPE_BUSY_64_TSS);
2899         }
2900         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2901 }
2902
2903 static void exit_lmode(struct kvm_vcpu *vcpu)
2904 {
2905         vmcs_write32(VM_ENTRY_CONTROLS,
2906                      vmcs_read32(VM_ENTRY_CONTROLS)
2907                      & ~VM_ENTRY_IA32E_MODE);
2908         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2909 }
2910
2911 #endif
2912
2913 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2914 {
2915         vpid_sync_context(to_vmx(vcpu));
2916         if (enable_ept) {
2917                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2918                         return;
2919                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2920         }
2921 }
2922
2923 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2924 {
2925         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2926
2927         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2928         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2929 }
2930
2931 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2932 {
2933         if (enable_ept && is_paging(vcpu))
2934                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2935         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2936 }
2937
2938 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2939 {
2940         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2941
2942         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2943         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2944 }
2945
2946 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2947 {
2948         if (!test_bit(VCPU_EXREG_PDPTR,
2949                       (unsigned long *)&vcpu->arch.regs_dirty))
2950                 return;
2951
2952         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2953                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2954                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2955                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2956                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
2957         }
2958 }
2959
2960 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2961 {
2962         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2963                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2964                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2965                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2966                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2967         }
2968
2969         __set_bit(VCPU_EXREG_PDPTR,
2970                   (unsigned long *)&vcpu->arch.regs_avail);
2971         __set_bit(VCPU_EXREG_PDPTR,
2972                   (unsigned long *)&vcpu->arch.regs_dirty);
2973 }
2974
2975 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2976
2977 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2978                                         unsigned long cr0,
2979                                         struct kvm_vcpu *vcpu)
2980 {
2981         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2982                 vmx_decache_cr3(vcpu);
2983         if (!(cr0 & X86_CR0_PG)) {
2984                 /* From paging/starting to nonpaging */
2985                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2986                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
2987                              (CPU_BASED_CR3_LOAD_EXITING |
2988                               CPU_BASED_CR3_STORE_EXITING));
2989                 vcpu->arch.cr0 = cr0;
2990                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2991         } else if (!is_paging(vcpu)) {
2992                 /* From nonpaging to paging */
2993                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2994                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
2995                              ~(CPU_BASED_CR3_LOAD_EXITING |
2996                                CPU_BASED_CR3_STORE_EXITING));
2997                 vcpu->arch.cr0 = cr0;
2998                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2999         }
3000
3001         if (!(cr0 & X86_CR0_WP))
3002                 *hw_cr0 &= ~X86_CR0_WP;
3003 }
3004
3005 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3006 {
3007         struct vcpu_vmx *vmx = to_vmx(vcpu);
3008         unsigned long hw_cr0;
3009
3010         if (enable_unrestricted_guest)
3011                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
3012                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3013         else
3014                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
3015
3016         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3017                 enter_pmode(vcpu);
3018
3019         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3020                 enter_rmode(vcpu);
3021
3022 #ifdef CONFIG_X86_64
3023         if (vcpu->arch.efer & EFER_LME) {
3024                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3025                         enter_lmode(vcpu);
3026                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3027                         exit_lmode(vcpu);
3028         }
3029 #endif
3030
3031         if (enable_ept)
3032                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3033
3034         if (!vcpu->fpu_active)
3035                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3036
3037         vmcs_writel(CR0_READ_SHADOW, cr0);
3038         vmcs_writel(GUEST_CR0, hw_cr0);
3039         vcpu->arch.cr0 = cr0;
3040         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3041 }
3042
3043 static u64 construct_eptp(unsigned long root_hpa)
3044 {
3045         u64 eptp;
3046
3047         /* TODO write the value reading from MSR */
3048         eptp = VMX_EPT_DEFAULT_MT |
3049                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3050         if (enable_ept_ad_bits)
3051                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3052         eptp |= (root_hpa & PAGE_MASK);
3053
3054         return eptp;
3055 }
3056
3057 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3058 {
3059         unsigned long guest_cr3;
3060         u64 eptp;
3061
3062         guest_cr3 = cr3;
3063         if (enable_ept) {
3064                 eptp = construct_eptp(cr3);
3065                 vmcs_write64(EPT_POINTER, eptp);
3066                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3067                         vcpu->kvm->arch.ept_identity_map_addr;
3068                 ept_load_pdptrs(vcpu);
3069         }
3070
3071         vmx_flush_tlb(vcpu);
3072         vmcs_writel(GUEST_CR3, guest_cr3);
3073 }
3074
3075 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3076 {
3077         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3078                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3079
3080         if (cr4 & X86_CR4_VMXE) {
3081                 /*
3082                  * To use VMXON (and later other VMX instructions), a guest
3083                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3084                  * So basically the check on whether to allow nested VMX
3085                  * is here.
3086                  */
3087                 if (!nested_vmx_allowed(vcpu))
3088                         return 1;
3089         } else if (to_vmx(vcpu)->nested.vmxon)
3090                 return 1;
3091
3092         vcpu->arch.cr4 = cr4;
3093         if (enable_ept) {
3094                 if (!is_paging(vcpu)) {
3095                         hw_cr4 &= ~X86_CR4_PAE;
3096                         hw_cr4 |= X86_CR4_PSE;
3097                 } else if (!(cr4 & X86_CR4_PAE)) {
3098                         hw_cr4 &= ~X86_CR4_PAE;
3099                 }
3100         }
3101
3102         vmcs_writel(CR4_READ_SHADOW, cr4);
3103         vmcs_writel(GUEST_CR4, hw_cr4);
3104         return 0;
3105 }
3106
3107 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3108                             struct kvm_segment *var, int seg)
3109 {
3110         struct vcpu_vmx *vmx = to_vmx(vcpu);
3111         struct kvm_save_segment *save;
3112         u32 ar;
3113
3114         if (vmx->rmode.vm86_active
3115             && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
3116                 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
3117                 || seg == VCPU_SREG_GS)
3118             && !emulate_invalid_guest_state) {
3119                 switch (seg) {
3120                 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
3121                 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
3122                 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
3123                 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
3124                 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
3125                 default: BUG();
3126                 }
3127                 var->selector = save->selector;
3128                 var->base = save->base;
3129                 var->limit = save->limit;
3130                 ar = save->ar;
3131                 if (seg == VCPU_SREG_TR
3132                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3133                         goto use_saved_rmode_seg;
3134         }
3135         var->base = vmx_read_guest_seg_base(vmx, seg);
3136         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3137         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3138         ar = vmx_read_guest_seg_ar(vmx, seg);
3139 use_saved_rmode_seg:
3140         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
3141                 ar = 0;
3142         var->type = ar & 15;
3143         var->s = (ar >> 4) & 1;
3144         var->dpl = (ar >> 5) & 3;
3145         var->present = (ar >> 7) & 1;
3146         var->avl = (ar >> 12) & 1;
3147         var->l = (ar >> 13) & 1;
3148         var->db = (ar >> 14) & 1;
3149         var->g = (ar >> 15) & 1;
3150         var->unusable = (ar >> 16) & 1;
3151 }
3152
3153 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3154 {
3155         struct kvm_segment s;
3156
3157         if (to_vmx(vcpu)->rmode.vm86_active) {
3158                 vmx_get_segment(vcpu, &s, seg);
3159                 return s.base;
3160         }
3161         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3162 }
3163
3164 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
3165 {
3166         if (!is_protmode(vcpu))
3167                 return 0;
3168
3169         if (!is_long_mode(vcpu)
3170             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3171                 return 3;
3172
3173         return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
3174 }
3175
3176 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3177 {
3178         struct vcpu_vmx *vmx = to_vmx(vcpu);
3179
3180         /*
3181          * If we enter real mode with cs.sel & 3 != 0, the normal CPL calculations
3182          * fail; use the cache instead.
3183          */
3184         if (unlikely(vmx->emulation_required && emulate_invalid_guest_state)) {
3185                 return vmx->cpl;
3186         }
3187
3188         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3189                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3190                 vmx->cpl = __vmx_get_cpl(vcpu);
3191         }
3192
3193         return vmx->cpl;
3194 }
3195
3196
3197 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3198 {
3199         u32 ar;
3200
3201         if (var->unusable)
3202                 ar = 1 << 16;
3203         else {
3204                 ar = var->type & 15;
3205                 ar |= (var->s & 1) << 4;
3206                 ar |= (var->dpl & 3) << 5;
3207                 ar |= (var->present & 1) << 7;
3208                 ar |= (var->avl & 1) << 12;
3209                 ar |= (var->l & 1) << 13;
3210                 ar |= (var->db & 1) << 14;
3211                 ar |= (var->g & 1) << 15;
3212         }
3213         if (ar == 0) /* a 0 value means unusable */
3214                 ar = AR_UNUSABLE_MASK;
3215
3216         return ar;
3217 }
3218
3219 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3220                             struct kvm_segment *var, int seg)
3221 {
3222         struct vcpu_vmx *vmx = to_vmx(vcpu);
3223         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3224         u32 ar;
3225
3226         vmx_segment_cache_clear(vmx);
3227
3228         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
3229                 vmcs_write16(sf->selector, var->selector);
3230                 vmx->rmode.tr.selector = var->selector;
3231                 vmx->rmode.tr.base = var->base;
3232                 vmx->rmode.tr.limit = var->limit;
3233                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
3234                 return;
3235         }
3236         vmcs_writel(sf->base, var->base);
3237         vmcs_write32(sf->limit, var->limit);
3238         vmcs_write16(sf->selector, var->selector);
3239         if (vmx->rmode.vm86_active && var->s) {
3240                 /*
3241                  * Hack real-mode segments into vm86 compatibility.
3242                  */
3243                 if (var->base == 0xffff0000 && var->selector == 0xf000)
3244                         vmcs_writel(sf->base, 0xf0000);
3245                 ar = 0xf3;
3246         } else
3247                 ar = vmx_segment_access_rights(var);
3248
3249         /*
3250          *   Fix the "Accessed" bit in AR field of segment registers for older
3251          * qemu binaries.
3252          *   IA32 arch specifies that at the time of processor reset the
3253          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3254          * is setting it to 0 in the usedland code. This causes invalid guest
3255          * state vmexit when "unrestricted guest" mode is turned on.
3256          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3257          * tree. Newer qemu binaries with that qemu fix would not need this
3258          * kvm hack.
3259          */
3260         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3261                 ar |= 0x1; /* Accessed */
3262
3263         vmcs_write32(sf->ar_bytes, ar);
3264         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3265
3266         /*
3267          * Fix segments for real mode guest in hosts that don't have
3268          * "unrestricted_mode" or it was disabled.
3269          * This is done to allow migration of the guests from hosts with
3270          * unrestricted guest like Westmere to older host that don't have
3271          * unrestricted guest like Nehelem.
3272          */
3273         if (!enable_unrestricted_guest && vmx->rmode.vm86_active) {
3274                 switch (seg) {
3275                 case VCPU_SREG_CS:
3276                         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
3277                         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
3278                         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
3279                                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
3280                         vmcs_write16(GUEST_CS_SELECTOR,
3281                                      vmcs_readl(GUEST_CS_BASE) >> 4);
3282                         break;
3283                 case VCPU_SREG_ES:
3284                         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
3285                         break;
3286                 case VCPU_SREG_DS:
3287                         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
3288                         break;
3289                 case VCPU_SREG_GS:
3290                         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
3291                         break;
3292                 case VCPU_SREG_FS:
3293                         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
3294                         break;
3295                 case VCPU_SREG_SS:
3296                         vmcs_write16(GUEST_SS_SELECTOR,
3297                                      vmcs_readl(GUEST_SS_BASE) >> 4);
3298                         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
3299                         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
3300                         break;
3301                 }
3302         }
3303 }
3304
3305 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3306 {
3307         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3308
3309         *db = (ar >> 14) & 1;
3310         *l = (ar >> 13) & 1;
3311 }
3312
3313 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3314 {
3315         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3316         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3317 }
3318
3319 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3320 {
3321         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3322         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3323 }
3324
3325 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3326 {
3327         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3328         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3329 }
3330
3331 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3332 {
3333         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3334         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3335 }
3336
3337 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3338 {
3339         struct kvm_segment var;
3340         u32 ar;
3341
3342         vmx_get_segment(vcpu, &var, seg);
3343         ar = vmx_segment_access_rights(&var);
3344
3345         if (var.base != (var.selector << 4))
3346                 return false;
3347         if (var.limit != 0xffff)
3348                 return false;
3349         if (ar != 0xf3)
3350                 return false;
3351
3352         return true;
3353 }
3354
3355 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3356 {
3357         struct kvm_segment cs;
3358         unsigned int cs_rpl;
3359
3360         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3361         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3362
3363         if (cs.unusable)
3364                 return false;
3365         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3366                 return false;
3367         if (!cs.s)
3368                 return false;
3369         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3370                 if (cs.dpl > cs_rpl)
3371                         return false;
3372         } else {
3373                 if (cs.dpl != cs_rpl)
3374                         return false;
3375         }
3376         if (!cs.present)
3377                 return false;
3378
3379         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3380         return true;
3381 }
3382
3383 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3384 {
3385         struct kvm_segment ss;
3386         unsigned int ss_rpl;
3387
3388         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3389         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3390
3391         if (ss.unusable)
3392                 return true;
3393         if (ss.type != 3 && ss.type != 7)
3394                 return false;
3395         if (!ss.s)
3396                 return false;
3397         if (ss.dpl != ss_rpl) /* DPL != RPL */
3398                 return false;
3399         if (!ss.present)
3400                 return false;
3401
3402         return true;
3403 }
3404
3405 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3406 {
3407         struct kvm_segment var;
3408         unsigned int rpl;
3409
3410         vmx_get_segment(vcpu, &var, seg);
3411         rpl = var.selector & SELECTOR_RPL_MASK;
3412
3413         if (var.unusable)
3414                 return true;
3415         if (!var.s)
3416                 return false;
3417         if (!var.present)
3418                 return false;
3419         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3420                 if (var.dpl < rpl) /* DPL < RPL */
3421                         return false;
3422         }
3423
3424         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3425          * rights flags
3426          */
3427         return true;
3428 }
3429
3430 static bool tr_valid(struct kvm_vcpu *vcpu)
3431 {
3432         struct kvm_segment tr;
3433
3434         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3435
3436         if (tr.unusable)
3437                 return false;
3438         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3439                 return false;
3440         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3441                 return false;
3442         if (!tr.present)
3443                 return false;
3444
3445         return true;
3446 }
3447
3448 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3449 {
3450         struct kvm_segment ldtr;
3451
3452         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3453
3454         if (ldtr.unusable)
3455                 return true;
3456         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3457                 return false;
3458         if (ldtr.type != 2)
3459                 return false;
3460         if (!ldtr.present)
3461                 return false;
3462
3463         return true;
3464 }
3465
3466 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3467 {
3468         struct kvm_segment cs, ss;
3469
3470         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3471         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3472
3473         return ((cs.selector & SELECTOR_RPL_MASK) ==
3474                  (ss.selector & SELECTOR_RPL_MASK));
3475 }
3476
3477 /*
3478  * Check if guest state is valid. Returns true if valid, false if
3479  * not.
3480  * We assume that registers are always usable
3481  */
3482 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3483 {
3484         /* real mode guest state checks */
3485         if (!is_protmode(vcpu)) {
3486                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3487                         return false;
3488                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3489                         return false;
3490                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3491                         return false;
3492                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3493                         return false;
3494                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3495                         return false;
3496                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3497                         return false;
3498         } else {
3499         /* protected mode guest state checks */
3500                 if (!cs_ss_rpl_check(vcpu))
3501                         return false;
3502                 if (!code_segment_valid(vcpu))
3503                         return false;
3504                 if (!stack_segment_valid(vcpu))
3505                         return false;
3506                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3507                         return false;
3508                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3509                         return false;
3510                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3511                         return false;
3512                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3513                         return false;
3514                 if (!tr_valid(vcpu))
3515                         return false;
3516                 if (!ldtr_valid(vcpu))
3517                         return false;
3518         }
3519         /* TODO:
3520          * - Add checks on RIP
3521          * - Add checks on RFLAGS
3522          */
3523
3524         return true;
3525 }
3526
3527 static int init_rmode_tss(struct kvm *kvm)
3528 {
3529         gfn_t fn;
3530         u16 data = 0;
3531         int r, idx, ret = 0;
3532
3533         idx = srcu_read_lock(&kvm->srcu);
3534         fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3535         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3536         if (r < 0)
3537                 goto out;
3538         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3539         r = kvm_write_guest_page(kvm, fn++, &data,
3540                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3541         if (r < 0)
3542                 goto out;
3543         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3544         if (r < 0)
3545                 goto out;
3546         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3547         if (r < 0)
3548                 goto out;
3549         data = ~0;
3550         r = kvm_write_guest_page(kvm, fn, &data,
3551                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3552                                  sizeof(u8));
3553         if (r < 0)
3554                 goto out;
3555
3556         ret = 1;
3557 out:
3558         srcu_read_unlock(&kvm->srcu, idx);
3559         return ret;
3560 }
3561
3562 static int init_rmode_identity_map(struct kvm *kvm)
3563 {
3564         int i, idx, r, ret;
3565         pfn_t identity_map_pfn;
3566         u32 tmp;
3567
3568         if (!enable_ept)
3569                 return 1;
3570         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3571                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3572                         "haven't been allocated!\n");
3573                 return 0;
3574         }
3575         if (likely(kvm->arch.ept_identity_pagetable_done))
3576                 return 1;
3577         ret = 0;
3578         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3579         idx = srcu_read_lock(&kvm->srcu);
3580         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3581         if (r < 0)
3582                 goto out;
3583         /* Set up identity-mapping pagetable for EPT in real mode */
3584         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3585                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3586                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3587                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3588                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3589                 if (r < 0)
3590                         goto out;
3591         }
3592         kvm->arch.ept_identity_pagetable_done = true;
3593         ret = 1;
3594 out:
3595         srcu_read_unlock(&kvm->srcu, idx);
3596         return ret;
3597 }
3598
3599 static void seg_setup(int seg)
3600 {
3601         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3602         unsigned int ar;
3603
3604         vmcs_write16(sf->selector, 0);
3605         vmcs_writel(sf->base, 0);
3606         vmcs_write32(sf->limit, 0xffff);
3607         if (enable_unrestricted_guest) {
3608                 ar = 0x93;
3609                 if (seg == VCPU_SREG_CS)
3610                         ar |= 0x08; /* code segment */
3611         } else
3612                 ar = 0xf3;
3613
3614         vmcs_write32(sf->ar_bytes, ar);
3615 }
3616
3617 static int alloc_apic_access_page(struct kvm *kvm)
3618 {
3619         struct kvm_userspace_memory_region kvm_userspace_mem;
3620         int r = 0;
3621
3622         mutex_lock(&kvm->slots_lock);
3623         if (kvm->arch.apic_access_page)
3624                 goto out;
3625         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3626         kvm_userspace_mem.flags = 0;
3627         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3628         kvm_userspace_mem.memory_size = PAGE_SIZE;
3629         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3630         if (r)
3631                 goto out;
3632
3633         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
3634 out:
3635         mutex_unlock(&kvm->slots_lock);
3636         return r;
3637 }
3638
3639 static int alloc_identity_pagetable(struct kvm *kvm)
3640 {
3641         struct kvm_userspace_memory_region kvm_userspace_mem;
3642         int r = 0;
3643
3644         mutex_lock(&kvm->slots_lock);
3645         if (kvm->arch.ept_identity_pagetable)
3646                 goto out;
3647         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3648         kvm_userspace_mem.flags = 0;
3649         kvm_userspace_mem.guest_phys_addr =
3650                 kvm->arch.ept_identity_map_addr;
3651         kvm_userspace_mem.memory_size = PAGE_SIZE;
3652         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3653         if (r)
3654                 goto out;
3655
3656         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
3657                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3658 out:
3659         mutex_unlock(&kvm->slots_lock);
3660         return r;
3661 }
3662
3663 static void allocate_vpid(struct vcpu_vmx *vmx)
3664 {
3665         int vpid;
3666
3667         vmx->vpid = 0;
3668         if (!enable_vpid)
3669                 return;
3670         spin_lock(&vmx_vpid_lock);
3671         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3672         if (vpid < VMX_NR_VPIDS) {
3673                 vmx->vpid = vpid;
3674                 __set_bit(vpid, vmx_vpid_bitmap);
3675         }
3676         spin_unlock(&vmx_vpid_lock);
3677 }
3678
3679 static void free_vpid(struct vcpu_vmx *vmx)
3680 {
3681         if (!enable_vpid)
3682                 return;
3683         spin_lock(&vmx_vpid_lock);
3684         if (vmx->vpid != 0)
3685                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3686         spin_unlock(&vmx_vpid_lock);
3687 }
3688
3689 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
3690 {
3691         int f = sizeof(unsigned long);
3692
3693         if (!cpu_has_vmx_msr_bitmap())
3694                 return;
3695
3696         /*
3697          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3698          * have the write-low and read-high bitmap offsets the wrong way round.
3699          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3700          */
3701         if (msr <= 0x1fff) {
3702                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3703                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
3704         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3705                 msr &= 0x1fff;
3706                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3707                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
3708         }
3709 }
3710
3711 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3712 {
3713         if (!longmode_only)
3714                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3715         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3716 }
3717
3718 /*
3719  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3720  * will not change in the lifetime of the guest.
3721  * Note that host-state that does change is set elsewhere. E.g., host-state
3722  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3723  */
3724 static void vmx_set_constant_host_state(void)
3725 {
3726         u32 low32, high32;
3727         unsigned long tmpl;
3728         struct desc_ptr dt;
3729
3730         vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS);  /* 22.2.3 */
3731         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
3732         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
3733
3734         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
3735 #ifdef CONFIG_X86_64
3736         /*
3737          * Load null selectors, so we can avoid reloading them in
3738          * __vmx_load_host_state(), in case userspace uses the null selectors
3739          * too (the expected case).
3740          */
3741         vmcs_write16(HOST_DS_SELECTOR, 0);
3742         vmcs_write16(HOST_ES_SELECTOR, 0);
3743 #else
3744         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3745         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3746 #endif
3747         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3748         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
3749
3750         native_store_idt(&dt);
3751         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
3752
3753         asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3754         vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3755
3756         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3757         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3758         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3759         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
3760
3761         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3762                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3763                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3764         }
3765 }
3766
3767 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3768 {
3769         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3770         if (enable_ept)
3771                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3772         if (is_guest_mode(&vmx->vcpu))
3773                 vmx->vcpu.arch.cr4_guest_owned_bits &=
3774                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3775         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3776 }
3777
3778 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3779 {
3780         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3781         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3782                 exec_control &= ~CPU_BASED_TPR_SHADOW;
3783 #ifdef CONFIG_X86_64
3784                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3785                                 CPU_BASED_CR8_LOAD_EXITING;
3786 #endif
3787         }
3788         if (!enable_ept)
3789                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3790                                 CPU_BASED_CR3_LOAD_EXITING  |
3791                                 CPU_BASED_INVLPG_EXITING;
3792         return exec_control;
3793 }
3794
3795 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3796 {
3797         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3798         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3799                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3800         if (vmx->vpid == 0)
3801                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3802         if (!enable_ept) {
3803                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3804                 enable_unrestricted_guest = 0;
3805         }
3806         if (!enable_unrestricted_guest)
3807                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3808         if (!ple_gap)
3809                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3810         return exec_control;
3811 }
3812
3813 static void ept_set_mmio_spte_mask(void)
3814 {
3815         /*
3816          * EPT Misconfigurations can be generated if the value of bits 2:0
3817          * of an EPT paging-structure entry is 110b (write/execute).
3818          * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3819          * spte.
3820          */
3821         kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3822 }
3823
3824 /*
3825  * Sets up the vmcs for emulated real mode.
3826  */
3827 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
3828 {
3829 #ifdef CONFIG_X86_64
3830         unsigned long a;
3831 #endif
3832         int i;
3833
3834         /* I/O */
3835         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3836         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
3837
3838         if (cpu_has_vmx_msr_bitmap())
3839                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
3840
3841         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3842
3843         /* Control */
3844         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3845                 vmcs_config.pin_based_exec_ctrl);
3846
3847         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
3848
3849         if (cpu_has_secondary_exec_ctrls()) {
3850                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3851                                 vmx_secondary_exec_control(vmx));
3852         }
3853
3854         if (ple_gap) {
3855                 vmcs_write32(PLE_GAP, ple_gap);
3856                 vmcs_write32(PLE_WINDOW, ple_window);
3857         }
3858
3859         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3860         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
3861         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
3862
3863         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
3864         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
3865         vmx_set_constant_host_state();
3866 #ifdef CONFIG_X86_64
3867         rdmsrl(MSR_FS_BASE, a);
3868         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3869         rdmsrl(MSR_GS_BASE, a);
3870         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3871 #else
3872         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3873         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3874 #endif
3875
3876         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3877         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
3878         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
3879         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
3880         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
3881
3882         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3883                 u32 msr_low, msr_high;
3884                 u64 host_pat;
3885                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3886                 host_pat = msr_low | ((u64) msr_high << 32);
3887                 /* Write the default value follow host pat */
3888                 vmcs_write64(GUEST_IA32_PAT, host_pat);
3889                 /* Keep arch.pat sync with GUEST_IA32_PAT */
3890                 vmx->vcpu.arch.pat = host_pat;
3891         }
3892
3893         for (i = 0; i < NR_VMX_MSR; ++i) {
3894                 u32 index = vmx_msr_index[i];
3895                 u32 data_low, data_high;
3896                 int j = vmx->nmsrs;
3897
3898                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3899                         continue;
3900                 if (wrmsr_safe(index, data_low, data_high) < 0)
3901                         continue;
3902                 vmx->guest_msrs[j].index = i;
3903                 vmx->guest_msrs[j].data = 0;
3904                 vmx->guest_msrs[j].mask = -1ull;
3905                 ++vmx->nmsrs;
3906         }
3907
3908         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
3909
3910         /* 22.2.1, 20.8.1 */
3911         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3912
3913         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
3914         set_cr4_guest_host_mask(vmx);
3915
3916         kvm_write_tsc(&vmx->vcpu, 0);
3917
3918         return 0;
3919 }
3920
3921 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3922 {
3923         struct vcpu_vmx *vmx = to_vmx(vcpu);
3924         u64 msr;
3925         int ret;
3926
3927         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3928
3929         vmx->rmode.vm86_active = 0;
3930
3931         vmx->soft_vnmi_blocked = 0;
3932
3933         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
3934         kvm_set_cr8(&vmx->vcpu, 0);
3935         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
3936         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3937                 msr |= MSR_IA32_APICBASE_BSP;
3938         kvm_set_apic_base(&vmx->vcpu, msr);
3939
3940         ret = fx_init(&vmx->vcpu);
3941         if (ret != 0)
3942                 goto out;
3943
3944         vmx_segment_cache_clear(vmx);
3945
3946         seg_setup(VCPU_SREG_CS);
3947         /*
3948          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3949          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
3950          */
3951         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
3952                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3953                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3954         } else {
3955                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3956                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
3957         }
3958
3959         seg_setup(VCPU_SREG_DS);
3960         seg_setup(VCPU_SREG_ES);
3961         seg_setup(VCPU_SREG_FS);
3962         seg_setup(VCPU_SREG_GS);
3963         seg_setup(VCPU_SREG_SS);
3964
3965         vmcs_write16(GUEST_TR_SELECTOR, 0);
3966         vmcs_writel(GUEST_TR_BASE, 0);
3967         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3968         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3969
3970         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3971         vmcs_writel(GUEST_LDTR_BASE, 0);
3972         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3973         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3974
3975         vmcs_write32(GUEST_SYSENTER_CS, 0);
3976         vmcs_writel(GUEST_SYSENTER_ESP, 0);
3977         vmcs_writel(GUEST_SYSENTER_EIP, 0);
3978
3979         vmcs_writel(GUEST_RFLAGS, 0x02);
3980         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3981                 kvm_rip_write(vcpu, 0xfff0);
3982         else
3983                 kvm_rip_write(vcpu, 0);
3984         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
3985
3986         vmcs_writel(GUEST_DR7, 0x400);
3987
3988         vmcs_writel(GUEST_GDTR_BASE, 0);
3989         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3990
3991         vmcs_writel(GUEST_IDTR_BASE, 0);
3992         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3993
3994         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3995         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3996         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3997
3998         /* Special registers */
3999         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4000
4001         setup_msrs(vmx);
4002
4003         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4004
4005         if (cpu_has_vmx_tpr_shadow()) {
4006                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4007                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4008                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4009                                      __pa(vmx->vcpu.arch.apic->regs));
4010                 vmcs_write32(TPR_THRESHOLD, 0);
4011         }
4012
4013         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4014                 vmcs_write64(APIC_ACCESS_ADDR,
4015                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
4016
4017         if (vmx->vpid != 0)
4018                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4019
4020         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4021         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
4022         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4023         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
4024         vmx_set_cr4(&vmx->vcpu, 0);
4025         vmx_set_efer(&vmx->vcpu, 0);
4026         vmx_fpu_activate(&vmx->vcpu);
4027         update_exception_bitmap(&vmx->vcpu);
4028
4029         vpid_sync_context(vmx);
4030
4031         ret = 0;
4032
4033         /* HACK: Don't enable emulation on guest boot/reset */
4034         vmx->emulation_required = 0;
4035
4036 out:
4037         return ret;
4038 }
4039
4040 /*
4041  * In nested virtualization, check if L1 asked to exit on external interrupts.
4042  * For most existing hypervisors, this will always return true.
4043  */
4044 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4045 {
4046         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4047                 PIN_BASED_EXT_INTR_MASK;
4048 }
4049
4050 static void enable_irq_window(struct kvm_vcpu *vcpu)
4051 {
4052         u32 cpu_based_vm_exec_control;
4053         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4054                 /*
4055                  * We get here if vmx_interrupt_allowed() said we can't
4056                  * inject to L1 now because L2 must run. Ask L2 to exit
4057                  * right after entry, so we can inject to L1 more promptly.
4058                  */
4059                 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
4060                 return;
4061         }
4062
4063         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4064         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4065         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4066 }
4067
4068 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4069 {
4070         u32 cpu_based_vm_exec_control;
4071
4072         if (!cpu_has_virtual_nmis()) {
4073                 enable_irq_window(vcpu);
4074                 return;
4075         }
4076
4077         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4078                 enable_irq_window(vcpu);
4079                 return;
4080         }
4081         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4082         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4083         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4084 }
4085
4086 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4087 {
4088         struct vcpu_vmx *vmx = to_vmx(vcpu);
4089         uint32_t intr;
4090         int irq = vcpu->arch.interrupt.nr;
4091
4092         trace_kvm_inj_virq(irq);
4093
4094         ++vcpu->stat.irq_injections;
4095         if (vmx->rmode.vm86_active) {
4096                 int inc_eip = 0;
4097                 if (vcpu->arch.interrupt.soft)
4098                         inc_eip = vcpu->arch.event_exit_inst_len;
4099                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4100                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4101                 return;
4102         }
4103         intr = irq | INTR_INFO_VALID_MASK;
4104         if (vcpu->arch.interrupt.soft) {
4105                 intr |= INTR_TYPE_SOFT_INTR;
4106                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4107                              vmx->vcpu.arch.event_exit_inst_len);
4108         } else
4109                 intr |= INTR_TYPE_EXT_INTR;
4110         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4111 }
4112
4113 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4114 {
4115         struct vcpu_vmx *vmx = to_vmx(vcpu);
4116
4117         if (is_guest_mode(vcpu))
4118                 return;
4119
4120         if (!cpu_has_virtual_nmis()) {
4121                 /*
4122                  * Tracking the NMI-blocked state in software is built upon
4123                  * finding the next open IRQ window. This, in turn, depends on
4124                  * well-behaving guests: They have to keep IRQs disabled at
4125                  * least as long as the NMI handler runs. Otherwise we may
4126                  * cause NMI nesting, maybe breaking the guest. But as this is
4127                  * highly unlikely, we can live with the residual risk.
4128                  */
4129                 vmx->soft_vnmi_blocked = 1;
4130                 vmx->vnmi_blocked_time = 0;
4131         }
4132
4133         ++vcpu->stat.nmi_injections;
4134         vmx->nmi_known_unmasked = false;
4135         if (vmx->rmode.vm86_active) {
4136                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4137                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4138                 return;
4139         }
4140         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4141                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4142 }
4143
4144 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4145 {
4146         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4147                 return 0;
4148
4149         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4150                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4151                    | GUEST_INTR_STATE_NMI));
4152 }
4153
4154 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4155 {
4156         if (!cpu_has_virtual_nmis())
4157                 return to_vmx(vcpu)->soft_vnmi_blocked;
4158         if (to_vmx(vcpu)->nmi_known_unmasked)
4159                 return false;
4160         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4161 }
4162
4163 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4164 {
4165         struct vcpu_vmx *vmx = to_vmx(vcpu);
4166
4167         if (!cpu_has_virtual_nmis()) {
4168                 if (vmx->soft_vnmi_blocked != masked) {
4169                         vmx->soft_vnmi_blocked = masked;
4170                         vmx->vnmi_blocked_time = 0;
4171                 }
4172         } else {
4173                 vmx->nmi_known_unmasked = !masked;
4174                 if (masked)
4175                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4176                                       GUEST_INTR_STATE_NMI);
4177                 else
4178                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4179                                         GUEST_INTR_STATE_NMI);
4180         }
4181 }
4182
4183 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4184 {
4185         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4186                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4187                 if (to_vmx(vcpu)->nested.nested_run_pending ||
4188                     (vmcs12->idt_vectoring_info_field &
4189                      VECTORING_INFO_VALID_MASK))
4190                         return 0;
4191                 nested_vmx_vmexit(vcpu);
4192                 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4193                 vmcs12->vm_exit_intr_info = 0;
4194                 /* fall through to normal code, but now in L1, not L2 */
4195         }
4196
4197         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4198                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4199                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4200 }
4201
4202 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4203 {
4204         int ret;
4205         struct kvm_userspace_memory_region tss_mem = {
4206                 .slot = TSS_PRIVATE_MEMSLOT,
4207                 .guest_phys_addr = addr,
4208                 .memory_size = PAGE_SIZE * 3,
4209                 .flags = 0,
4210         };
4211
4212         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
4213         if (ret)
4214                 return ret;
4215         kvm->arch.tss_addr = addr;
4216         if (!init_rmode_tss(kvm))
4217                 return  -ENOMEM;
4218
4219         return 0;
4220 }
4221
4222 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4223                                   int vec, u32 err_code)
4224 {
4225         /*
4226          * Instruction with address size override prefix opcode 0x67
4227          * Cause the #SS fault with 0 error code in VM86 mode.
4228          */
4229         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
4230                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
4231                         return 1;
4232         /*
4233          * Forward all other exceptions that are valid in real mode.
4234          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4235          *        the required debugging infrastructure rework.
4236          */
4237         switch (vec) {
4238         case DB_VECTOR:
4239                 if (vcpu->guest_debug &
4240                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4241                         return 0;
4242                 kvm_queue_exception(vcpu, vec);
4243                 return 1;
4244         case BP_VECTOR:
4245                 /*
4246                  * Update instruction length as we may reinject the exception
4247                  * from user space while in guest debugging mode.
4248                  */
4249                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4250                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4251                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4252                         return 0;
4253                 /* fall through */
4254         case DE_VECTOR:
4255         case OF_VECTOR:
4256         case BR_VECTOR:
4257         case UD_VECTOR:
4258         case DF_VECTOR:
4259         case SS_VECTOR:
4260         case GP_VECTOR:
4261         case MF_VECTOR:
4262                 kvm_queue_exception(vcpu, vec);
4263                 return 1;
4264         }
4265         return 0;
4266 }
4267
4268 /*
4269  * Trigger machine check on the host. We assume all the MSRs are already set up
4270  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4271  * We pass a fake environment to the machine check handler because we want
4272  * the guest to be always treated like user space, no matter what context
4273  * it used internally.
4274  */
4275 static void kvm_machine_check(void)
4276 {
4277 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4278         struct pt_regs regs = {
4279                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4280                 .flags = X86_EFLAGS_IF,
4281         };
4282
4283         do_machine_check(&regs, 0);
4284 #endif
4285 }
4286
4287 static int handle_machine_check(struct kvm_vcpu *vcpu)
4288 {
4289         /* already handled by vcpu_run */
4290         return 1;
4291 }
4292
4293 static int handle_exception(struct kvm_vcpu *vcpu)
4294 {
4295         struct vcpu_vmx *vmx = to_vmx(vcpu);
4296         struct kvm_run *kvm_run = vcpu->run;
4297         u32 intr_info, ex_no, error_code;
4298         unsigned long cr2, rip, dr6;
4299         u32 vect_info;
4300         enum emulation_result er;
4301
4302         vect_info = vmx->idt_vectoring_info;
4303         intr_info = vmx->exit_intr_info;
4304
4305         if (is_machine_check(intr_info))
4306                 return handle_machine_check(vcpu);
4307
4308         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4309             !is_page_fault(intr_info)) {
4310                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4311                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4312                 vcpu->run->internal.ndata = 2;
4313                 vcpu->run->internal.data[0] = vect_info;
4314                 vcpu->run->internal.data[1] = intr_info;
4315                 return 0;
4316         }
4317
4318         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4319                 return 1;  /* already handled by vmx_vcpu_run() */
4320
4321         if (is_no_device(intr_info)) {
4322                 vmx_fpu_activate(vcpu);
4323                 return 1;
4324         }
4325
4326         if (is_invalid_opcode(intr_info)) {
4327                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4328                 if (er != EMULATE_DONE)
4329                         kvm_queue_exception(vcpu, UD_VECTOR);
4330                 return 1;
4331         }
4332
4333         error_code = 0;
4334         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4335                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4336         if (is_page_fault(intr_info)) {
4337                 /* EPT won't cause page fault directly */
4338                 BUG_ON(enable_ept);
4339                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4340                 trace_kvm_page_fault(cr2, error_code);
4341
4342                 if (kvm_event_needs_reinjection(vcpu))
4343                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4344                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4345         }
4346
4347         if (vmx->rmode.vm86_active &&
4348             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
4349                                                                 error_code)) {
4350                 if (vcpu->arch.halt_request) {
4351                         vcpu->arch.halt_request = 0;
4352                         return kvm_emulate_halt(vcpu);
4353                 }
4354                 return 1;
4355         }
4356
4357         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4358         switch (ex_no) {
4359         case DB_VECTOR:
4360                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4361                 if (!(vcpu->guest_debug &
4362                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4363                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4364                         kvm_queue_exception(vcpu, DB_VECTOR);
4365                         return 1;
4366                 }
4367                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4368                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4369                 /* fall through */
4370         case BP_VECTOR:
4371                 /*
4372                  * Update instruction length as we may reinject #BP from
4373                  * user space while in guest debugging mode. Reading it for
4374                  * #DB as well causes no harm, it is not used in that case.
4375                  */
4376                 vmx->vcpu.arch.event_exit_inst_len =
4377                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4378                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4379                 rip = kvm_rip_read(vcpu);
4380                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4381                 kvm_run->debug.arch.exception = ex_no;
4382                 break;
4383         default:
4384                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4385                 kvm_run->ex.exception = ex_no;
4386                 kvm_run->ex.error_code = error_code;
4387                 break;
4388         }
4389         return 0;
4390 }
4391
4392 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4393 {
4394         ++vcpu->stat.irq_exits;
4395         return 1;
4396 }
4397
4398 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4399 {
4400         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4401         return 0;
4402 }
4403
4404 static int handle_io(struct kvm_vcpu *vcpu)
4405 {
4406         unsigned long exit_qualification;
4407         int size, in, string;
4408         unsigned port;
4409
4410         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4411         string = (exit_qualification & 16) != 0;
4412         in = (exit_qualification & 8) != 0;
4413
4414         ++vcpu->stat.io_exits;
4415
4416         if (string || in)
4417                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4418
4419         port = exit_qualification >> 16;
4420         size = (exit_qualification & 7) + 1;
4421         skip_emulated_instruction(vcpu);
4422
4423         return kvm_fast_pio_out(vcpu, size, port);
4424 }
4425
4426 static void
4427 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4428 {
4429         /*
4430          * Patch in the VMCALL instruction:
4431          */
4432         hypercall[0] = 0x0f;
4433         hypercall[1] = 0x01;
4434         hypercall[2] = 0xc1;
4435 }
4436
4437 /* called to set cr0 as approriate for a mov-to-cr0 exit. */
4438 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4439 {
4440         if (to_vmx(vcpu)->nested.vmxon &&
4441             ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4442                 return 1;
4443
4444         if (is_guest_mode(vcpu)) {
4445                 /*
4446                  * We get here when L2 changed cr0 in a way that did not change
4447                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4448                  * but did change L0 shadowed bits. This can currently happen
4449                  * with the TS bit: L0 may want to leave TS on (for lazy fpu
4450                  * loading) while pretending to allow the guest to change it.
4451                  */
4452                 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4453                          (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4454                         return 1;
4455                 vmcs_writel(CR0_READ_SHADOW, val);
4456                 return 0;
4457         } else
4458                 return kvm_set_cr0(vcpu, val);
4459 }
4460
4461 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4462 {
4463         if (is_guest_mode(vcpu)) {
4464                 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4465                          (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4466                         return 1;
4467                 vmcs_writel(CR4_READ_SHADOW, val);
4468                 return 0;
4469         } else
4470                 return kvm_set_cr4(vcpu, val);
4471 }
4472
4473 /* called to set cr0 as approriate for clts instruction exit. */
4474 static void handle_clts(struct kvm_vcpu *vcpu)
4475 {
4476         if (is_guest_mode(vcpu)) {
4477                 /*
4478                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4479                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4480                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4481                  */
4482                 vmcs_writel(CR0_READ_SHADOW,
4483                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4484                 vcpu->arch.cr0 &= ~X86_CR0_TS;
4485         } else
4486                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4487 }
4488
4489 static int handle_cr(struct kvm_vcpu *vcpu)
4490 {
4491         unsigned long exit_qualification, val;
4492         int cr;
4493         int reg;
4494         int err;
4495
4496         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4497         cr = exit_qualification & 15;
4498         reg = (exit_qualification >> 8) & 15;
4499         switch ((exit_qualification >> 4) & 3) {
4500         case 0: /* mov to cr */
4501                 val = kvm_register_read(vcpu, reg);
4502                 trace_kvm_cr_write(cr, val);
4503                 switch (cr) {
4504                 case 0:
4505                         err = handle_set_cr0(vcpu, val);
4506                         kvm_complete_insn_gp(vcpu, err);
4507                         return 1;
4508                 case 3:
4509                         err = kvm_set_cr3(vcpu, val);
4510                         kvm_complete_insn_gp(vcpu, err);
4511                         return 1;
4512                 case 4:
4513                         err = handle_set_cr4(vcpu, val);
4514                         kvm_complete_insn_gp(vcpu, err);
4515                         return 1;
4516                 case 8: {
4517                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4518                                 u8 cr8 = kvm_register_read(vcpu, reg);
4519                                 err = kvm_set_cr8(vcpu, cr8);
4520                                 kvm_complete_insn_gp(vcpu, err);
4521                                 if (irqchip_in_kernel(vcpu->kvm))
4522                                         return 1;
4523                                 if (cr8_prev <= cr8)
4524                                         return 1;
4525                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4526                                 return 0;
4527                         }
4528                 };
4529                 break;
4530         case 2: /* clts */
4531                 handle_clts(vcpu);
4532                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4533                 skip_emulated_instruction(vcpu);
4534                 vmx_fpu_activate(vcpu);
4535                 return 1;
4536         case 1: /*mov from cr*/
4537                 switch (cr) {
4538                 case 3:
4539                         val = kvm_read_cr3(vcpu);
4540                         kvm_register_write(vcpu, reg, val);
4541                         trace_kvm_cr_read(cr, val);
4542                         skip_emulated_instruction(vcpu);
4543                         return 1;
4544                 case 8:
4545                         val = kvm_get_cr8(vcpu);
4546                         kvm_register_write(vcpu, reg, val);
4547                         trace_kvm_cr_read(cr, val);
4548                         skip_emulated_instruction(vcpu);
4549                         return 1;
4550                 }
4551                 break;
4552         case 3: /* lmsw */
4553                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4554                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4555                 kvm_lmsw(vcpu, val);
4556
4557                 skip_emulated_instruction(vcpu);
4558                 return 1;
4559         default:
4560                 break;
4561         }
4562         vcpu->run->exit_reason = 0;
4563         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4564                (int)(exit_qualification >> 4) & 3, cr);
4565         return 0;
4566 }
4567
4568 static int handle_dr(struct kvm_vcpu *vcpu)
4569 {
4570         unsigned long exit_qualification;
4571         int dr, reg;
4572
4573         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4574         if (!kvm_require_cpl(vcpu, 0))
4575                 return 1;
4576         dr = vmcs_readl(GUEST_DR7);
4577         if (dr & DR7_GD) {
4578                 /*
4579                  * As the vm-exit takes precedence over the debug trap, we
4580                  * need to emulate the latter, either for the host or the
4581                  * guest debugging itself.
4582                  */
4583                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4584                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4585                         vcpu->run->debug.arch.dr7 = dr;
4586                         vcpu->run->debug.arch.pc =
4587                                 vmcs_readl(GUEST_CS_BASE) +
4588                                 vmcs_readl(GUEST_RIP);
4589                         vcpu->run->debug.arch.exception = DB_VECTOR;
4590                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4591                         return 0;
4592                 } else {
4593                         vcpu->arch.dr7 &= ~DR7_GD;
4594                         vcpu->arch.dr6 |= DR6_BD;
4595                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4596                         kvm_queue_exception(vcpu, DB_VECTOR);
4597                         return 1;
4598                 }
4599         }
4600
4601         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4602         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4603         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4604         if (exit_qualification & TYPE_MOV_FROM_DR) {
4605                 unsigned long val;
4606                 if (!kvm_get_dr(vcpu, dr, &val))
4607                         kvm_register_write(vcpu, reg, val);
4608         } else
4609                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4610         skip_emulated_instruction(vcpu);
4611         return 1;
4612 }
4613
4614 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4615 {
4616         vmcs_writel(GUEST_DR7, val);
4617 }
4618
4619 static int handle_cpuid(struct kvm_vcpu *vcpu)
4620 {
4621         kvm_emulate_cpuid(vcpu);
4622         return 1;
4623 }
4624
4625 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4626 {
4627         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4628         u64 data;
4629
4630         if (vmx_get_msr(vcpu, ecx, &data)) {
4631                 trace_kvm_msr_read_ex(ecx);
4632                 kvm_inject_gp(vcpu, 0);
4633                 return 1;
4634         }
4635
4636         trace_kvm_msr_read(ecx, data);
4637
4638         /* FIXME: handling of bits 32:63 of rax, rdx */
4639         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4640         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4641         skip_emulated_instruction(vcpu);
4642         return 1;
4643 }
4644
4645 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4646 {
4647         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4648         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4649                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4650
4651         if (vmx_set_msr(vcpu, ecx, data) != 0) {
4652                 trace_kvm_msr_write_ex(ecx, data);
4653                 kvm_inject_gp(vcpu, 0);
4654                 return 1;
4655         }
4656
4657         trace_kvm_msr_write(ecx, data);
4658         skip_emulated_instruction(vcpu);
4659         return 1;
4660 }
4661
4662 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4663 {
4664         kvm_make_request(KVM_REQ_EVENT, vcpu);
4665         return 1;
4666 }
4667
4668 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4669 {
4670         u32 cpu_based_vm_exec_control;
4671
4672         /* clear pending irq */
4673         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4674         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4675         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4676
4677         kvm_make_request(KVM_REQ_EVENT, vcpu);
4678
4679         ++vcpu->stat.irq_window_exits;
4680
4681         /*
4682          * If the user space waits to inject interrupts, exit as soon as
4683          * possible
4684          */
4685         if (!irqchip_in_kernel(vcpu->kvm) &&
4686             vcpu->run->request_interrupt_window &&
4687             !kvm_cpu_has_interrupt(vcpu)) {
4688                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4689                 return 0;
4690         }
4691         return 1;
4692 }
4693
4694 static int handle_halt(struct kvm_vcpu *vcpu)
4695 {
4696         skip_emulated_instruction(vcpu);
4697         return kvm_emulate_halt(vcpu);
4698 }
4699
4700 static int handle_vmcall(struct kvm_vcpu *vcpu)
4701 {
4702         skip_emulated_instruction(vcpu);
4703         kvm_emulate_hypercall(vcpu);
4704         return 1;
4705 }
4706
4707 static int handle_invd(struct kvm_vcpu *vcpu)
4708 {
4709         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4710 }
4711
4712 static int handle_invlpg(struct kvm_vcpu *vcpu)
4713 {
4714         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4715
4716         kvm_mmu_invlpg(vcpu, exit_qualification);
4717         skip_emulated_instruction(vcpu);
4718         return 1;
4719 }
4720
4721 static int handle_rdpmc(struct kvm_vcpu *vcpu)
4722 {
4723         int err;
4724
4725         err = kvm_rdpmc(vcpu);
4726         kvm_complete_insn_gp(vcpu, err);
4727
4728         return 1;
4729 }
4730
4731 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4732 {
4733         skip_emulated_instruction(vcpu);
4734         kvm_emulate_wbinvd(vcpu);
4735         return 1;
4736 }
4737
4738 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4739 {
4740         u64 new_bv = kvm_read_edx_eax(vcpu);
4741         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4742
4743         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4744                 skip_emulated_instruction(vcpu);
4745         return 1;
4746 }
4747
4748 static int handle_apic_access(struct kvm_vcpu *vcpu)
4749 {
4750         if (likely(fasteoi)) {
4751                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4752                 int access_type, offset;
4753
4754                 access_type = exit_qualification & APIC_ACCESS_TYPE;
4755                 offset = exit_qualification & APIC_ACCESS_OFFSET;
4756                 /*
4757                  * Sane guest uses MOV to write EOI, with written value
4758                  * not cared. So make a short-circuit here by avoiding
4759                  * heavy instruction emulation.
4760                  */
4761                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4762                     (offset == APIC_EOI)) {
4763                         kvm_lapic_set_eoi(vcpu);
4764                         skip_emulated_instruction(vcpu);
4765                         return 1;
4766                 }
4767         }
4768         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4769 }
4770
4771 static int handle_task_switch(struct kvm_vcpu *vcpu)
4772 {
4773         struct vcpu_vmx *vmx = to_vmx(vcpu);
4774         unsigned long exit_qualification;
4775         bool has_error_code = false;
4776         u32 error_code = 0;
4777         u16 tss_selector;
4778         int reason, type, idt_v, idt_index;
4779
4780         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4781         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
4782         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
4783
4784         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4785
4786         reason = (u32)exit_qualification >> 30;
4787         if (reason == TASK_SWITCH_GATE && idt_v) {
4788                 switch (type) {
4789                 case INTR_TYPE_NMI_INTR:
4790                         vcpu->arch.nmi_injected = false;
4791                         vmx_set_nmi_mask(vcpu, true);
4792                         break;
4793                 case INTR_TYPE_EXT_INTR:
4794                 case INTR_TYPE_SOFT_INTR:
4795                         kvm_clear_interrupt_queue(vcpu);
4796                         break;
4797                 case INTR_TYPE_HARD_EXCEPTION:
4798                         if (vmx->idt_vectoring_info &
4799                             VECTORING_INFO_DELIVER_CODE_MASK) {
4800                                 has_error_code = true;
4801                                 error_code =
4802                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
4803                         }
4804                         /* fall through */
4805                 case INTR_TYPE_SOFT_EXCEPTION:
4806                         kvm_clear_exception_queue(vcpu);
4807                         break;
4808                 default:
4809                         break;
4810                 }
4811         }
4812         tss_selector = exit_qualification;
4813
4814         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4815                        type != INTR_TYPE_EXT_INTR &&
4816                        type != INTR_TYPE_NMI_INTR))
4817                 skip_emulated_instruction(vcpu);
4818
4819         if (kvm_task_switch(vcpu, tss_selector,
4820                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
4821                             has_error_code, error_code) == EMULATE_FAIL) {
4822                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4823                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4824                 vcpu->run->internal.ndata = 0;
4825                 return 0;
4826         }
4827
4828         /* clear all local breakpoint enable flags */
4829         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4830
4831         /*
4832          * TODO: What about debug traps on tss switch?
4833          *       Are we supposed to inject them and update dr6?
4834          */
4835
4836         return 1;
4837 }
4838
4839 static int handle_ept_violation(struct kvm_vcpu *vcpu)
4840 {
4841         unsigned long exit_qualification;
4842         gpa_t gpa;
4843         int gla_validity;
4844
4845         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4846
4847         if (exit_qualification & (1 << 6)) {
4848                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
4849                 return -EINVAL;
4850         }
4851
4852         gla_validity = (exit_qualification >> 7) & 0x3;
4853         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4854                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4855                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4856                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
4857                         vmcs_readl(GUEST_LINEAR_ADDRESS));
4858                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4859                         (long unsigned int)exit_qualification);
4860                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4861                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
4862                 return 0;
4863         }
4864
4865         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4866         trace_kvm_page_fault(gpa, exit_qualification);
4867         return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
4868 }
4869
4870 static u64 ept_rsvd_mask(u64 spte, int level)
4871 {
4872         int i;
4873         u64 mask = 0;
4874
4875         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4876                 mask |= (1ULL << i);
4877
4878         if (level > 2)
4879                 /* bits 7:3 reserved */
4880                 mask |= 0xf8;
4881         else if (level == 2) {
4882                 if (spte & (1ULL << 7))
4883                         /* 2MB ref, bits 20:12 reserved */
4884                         mask |= 0x1ff000;
4885                 else
4886                         /* bits 6:3 reserved */
4887                         mask |= 0x78;
4888         }
4889
4890         return mask;
4891 }
4892
4893 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4894                                        int level)
4895 {
4896         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4897
4898         /* 010b (write-only) */
4899         WARN_ON((spte & 0x7) == 0x2);
4900
4901         /* 110b (write/execute) */
4902         WARN_ON((spte & 0x7) == 0x6);
4903
4904         /* 100b (execute-only) and value not supported by logical processor */
4905         if (!cpu_has_vmx_ept_execute_only())
4906                 WARN_ON((spte & 0x7) == 0x4);
4907
4908         /* not 000b */
4909         if ((spte & 0x7)) {
4910                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4911
4912                 if (rsvd_bits != 0) {
4913                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4914                                          __func__, rsvd_bits);
4915                         WARN_ON(1);
4916                 }
4917
4918                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4919                         u64 ept_mem_type = (spte & 0x38) >> 3;
4920
4921                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
4922                             ept_mem_type == 7) {
4923                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4924                                                 __func__, ept_mem_type);
4925                                 WARN_ON(1);
4926                         }
4927                 }
4928         }
4929 }
4930
4931 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
4932 {
4933         u64 sptes[4];
4934         int nr_sptes, i, ret;
4935         gpa_t gpa;
4936
4937         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4938
4939         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4940         if (likely(ret == 1))
4941                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4942                                               EMULATE_DONE;
4943         if (unlikely(!ret))
4944                 return 1;
4945
4946         /* It is the real ept misconfig */
4947         printk(KERN_ERR "EPT: Misconfiguration.\n");
4948         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4949
4950         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4951
4952         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4953                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4954
4955         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4956         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
4957
4958         return 0;
4959 }
4960
4961 static int handle_nmi_window(struct kvm_vcpu *vcpu)
4962 {
4963         u32 cpu_based_vm_exec_control;
4964
4965         /* clear pending NMI */
4966         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4967         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4968         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4969         ++vcpu->stat.nmi_window_exits;
4970         kvm_make_request(KVM_REQ_EVENT, vcpu);
4971
4972         return 1;
4973 }
4974
4975 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
4976 {
4977         struct vcpu_vmx *vmx = to_vmx(vcpu);
4978         enum emulation_result err = EMULATE_DONE;
4979         int ret = 1;
4980         u32 cpu_exec_ctrl;
4981         bool intr_window_requested;
4982
4983         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4984         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
4985
4986         while (!guest_state_valid(vcpu)) {
4987                 if (intr_window_requested
4988                     && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
4989                         return handle_interrupt_window(&vmx->vcpu);
4990
4991                 err = emulate_instruction(vcpu, 0);
4992
4993                 if (err == EMULATE_DO_MMIO) {
4994                         ret = 0;
4995                         goto out;
4996                 }
4997
4998                 if (err != EMULATE_DONE)
4999                         return 0;
5000
5001                 if (signal_pending(current))
5002                         goto out;
5003                 if (need_resched())
5004                         schedule();
5005         }
5006
5007         vmx->emulation_required = 0;
5008 out:
5009         return ret;
5010 }
5011
5012 /*
5013  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5014  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5015  */
5016 static int handle_pause(struct kvm_vcpu *vcpu)
5017 {
5018         skip_emulated_instruction(vcpu);
5019         kvm_vcpu_on_spin(vcpu);
5020
5021         return 1;
5022 }
5023
5024 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5025 {
5026         kvm_queue_exception(vcpu, UD_VECTOR);
5027         return 1;
5028 }
5029
5030 /*
5031  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5032  * We could reuse a single VMCS for all the L2 guests, but we also want the
5033  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5034  * allows keeping them loaded on the processor, and in the future will allow
5035  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5036  * every entry if they never change.
5037  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5038  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5039  *
5040  * The following functions allocate and free a vmcs02 in this pool.
5041  */
5042
5043 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5044 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5045 {
5046         struct vmcs02_list *item;
5047         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5048                 if (item->vmptr == vmx->nested.current_vmptr) {
5049                         list_move(&item->list, &vmx->nested.vmcs02_pool);
5050                         return &item->vmcs02;
5051                 }
5052
5053         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5054                 /* Recycle the least recently used VMCS. */
5055                 item = list_entry(vmx->nested.vmcs02_pool.prev,
5056                         struct vmcs02_list, list);
5057                 item->vmptr = vmx->nested.current_vmptr;
5058                 list_move(&item->list, &vmx->nested.vmcs02_pool);
5059                 return &item->vmcs02;
5060         }
5061
5062         /* Create a new VMCS */
5063         item = (struct vmcs02_list *)
5064                 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5065         if (!item)
5066                 return NULL;
5067         item->vmcs02.vmcs = alloc_vmcs();
5068         if (!item->vmcs02.vmcs) {
5069                 kfree(item);
5070                 return NULL;
5071         }
5072         loaded_vmcs_init(&item->vmcs02);
5073         item->vmptr = vmx->nested.current_vmptr;
5074         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5075         vmx->nested.vmcs02_num++;
5076         return &item->vmcs02;
5077 }
5078
5079 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5080 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5081 {
5082         struct vmcs02_list *item;
5083         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5084                 if (item->vmptr == vmptr) {
5085                         free_loaded_vmcs(&item->vmcs02);
5086                         list_del(&item->list);
5087                         kfree(item);
5088                         vmx->nested.vmcs02_num--;
5089                         return;
5090                 }
5091 }
5092
5093 /*
5094  * Free all VMCSs saved for this vcpu, except the one pointed by
5095  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5096  * currently used, if running L2), and vmcs01 when running L2.
5097  */
5098 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5099 {
5100         struct vmcs02_list *item, *n;
5101         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5102                 if (vmx->loaded_vmcs != &item->vmcs02)
5103                         free_loaded_vmcs(&item->vmcs02);
5104                 list_del(&item->list);
5105                 kfree(item);
5106         }
5107         vmx->nested.vmcs02_num = 0;
5108
5109         if (vmx->loaded_vmcs != &vmx->vmcs01)
5110                 free_loaded_vmcs(&vmx->vmcs01);
5111 }
5112
5113 /*
5114  * Emulate the VMXON instruction.
5115  * Currently, we just remember that VMX is active, and do not save or even
5116  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5117  * do not currently need to store anything in that guest-allocated memory
5118  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5119  * argument is different from the VMXON pointer (which the spec says they do).
5120  */
5121 static int handle_vmon(struct kvm_vcpu *vcpu)
5122 {
5123         struct kvm_segment cs;
5124         struct vcpu_vmx *vmx = to_vmx(vcpu);
5125
5126         /* The Intel VMX Instruction Reference lists a bunch of bits that
5127          * are prerequisite to running VMXON, most notably cr4.VMXE must be
5128          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5129          * Otherwise, we should fail with #UD. We test these now:
5130          */
5131         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5132             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5133             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5134                 kvm_queue_exception(vcpu, UD_VECTOR);
5135                 return 1;
5136         }
5137
5138         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5139         if (is_long_mode(vcpu) && !cs.l) {
5140                 kvm_queue_exception(vcpu, UD_VECTOR);
5141                 return 1;
5142         }
5143
5144         if (vmx_get_cpl(vcpu)) {
5145                 kvm_inject_gp(vcpu, 0);
5146                 return 1;
5147         }
5148
5149         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5150         vmx->nested.vmcs02_num = 0;
5151
5152         vmx->nested.vmxon = true;
5153
5154         skip_emulated_instruction(vcpu);
5155         return 1;
5156 }
5157
5158 /*
5159  * Intel's VMX Instruction Reference specifies a common set of prerequisites
5160  * for running VMX instructions (except VMXON, whose prerequisites are
5161  * slightly different). It also specifies what exception to inject otherwise.
5162  */
5163 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5164 {
5165         struct kvm_segment cs;
5166         struct vcpu_vmx *vmx = to_vmx(vcpu);
5167
5168         if (!vmx->nested.vmxon) {
5169                 kvm_queue_exception(vcpu, UD_VECTOR);
5170                 return 0;
5171         }
5172
5173         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5174         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5175             (is_long_mode(vcpu) && !cs.l)) {
5176                 kvm_queue_exception(vcpu, UD_VECTOR);
5177                 return 0;
5178         }
5179
5180         if (vmx_get_cpl(vcpu)) {
5181                 kvm_inject_gp(vcpu, 0);
5182                 return 0;
5183         }
5184
5185         return 1;
5186 }
5187
5188 /*
5189  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5190  * just stops using VMX.
5191  */
5192 static void free_nested(struct vcpu_vmx *vmx)
5193 {
5194         if (!vmx->nested.vmxon)
5195                 return;
5196         vmx->nested.vmxon = false;
5197         if (vmx->nested.current_vmptr != -1ull) {
5198                 kunmap(vmx->nested.current_vmcs12_page);
5199                 nested_release_page(vmx->nested.current_vmcs12_page);
5200                 vmx->nested.current_vmptr = -1ull;
5201                 vmx->nested.current_vmcs12 = NULL;
5202         }
5203         /* Unpin physical memory we referred to in current vmcs02 */
5204         if (vmx->nested.apic_access_page) {
5205                 nested_release_page(vmx->nested.apic_access_page);
5206                 vmx->nested.apic_access_page = 0;
5207         }
5208
5209         nested_free_all_saved_vmcss(vmx);
5210 }
5211
5212 /* Emulate the VMXOFF instruction */
5213 static int handle_vmoff(struct kvm_vcpu *vcpu)
5214 {
5215         if (!nested_vmx_check_permission(vcpu))
5216                 return 1;
5217         free_nested(to_vmx(vcpu));
5218         skip_emulated_instruction(vcpu);
5219         return 1;
5220 }
5221
5222 /*
5223  * Decode the memory-address operand of a vmx instruction, as recorded on an
5224  * exit caused by such an instruction (run by a guest hypervisor).
5225  * On success, returns 0. When the operand is invalid, returns 1 and throws
5226  * #UD or #GP.
5227  */
5228 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5229                                  unsigned long exit_qualification,
5230                                  u32 vmx_instruction_info, gva_t *ret)
5231 {
5232         /*
5233          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5234          * Execution", on an exit, vmx_instruction_info holds most of the
5235          * addressing components of the operand. Only the displacement part
5236          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5237          * For how an actual address is calculated from all these components,
5238          * refer to Vol. 1, "Operand Addressing".
5239          */
5240         int  scaling = vmx_instruction_info & 3;
5241         int  addr_size = (vmx_instruction_info >> 7) & 7;
5242         bool is_reg = vmx_instruction_info & (1u << 10);
5243         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5244         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5245         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5246         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5247         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5248
5249         if (is_reg) {
5250                 kvm_queue_exception(vcpu, UD_VECTOR);
5251                 return 1;
5252         }
5253
5254         /* Addr = segment_base + offset */
5255         /* offset = base + [index * scale] + displacement */
5256         *ret = vmx_get_segment_base(vcpu, seg_reg);
5257         if (base_is_valid)
5258                 *ret += kvm_register_read(vcpu, base_reg);
5259         if (index_is_valid)
5260                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5261         *ret += exit_qualification; /* holds the displacement */
5262
5263         if (addr_size == 1) /* 32 bit */
5264                 *ret &= 0xffffffff;
5265
5266         /*
5267          * TODO: throw #GP (and return 1) in various cases that the VM*
5268          * instructions require it - e.g., offset beyond segment limit,
5269          * unusable or unreadable/unwritable segment, non-canonical 64-bit
5270          * address, and so on. Currently these are not checked.
5271          */
5272         return 0;
5273 }
5274
5275 /*
5276  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5277  * set the success or error code of an emulated VMX instruction, as specified
5278  * by Vol 2B, VMX Instruction Reference, "Conventions".
5279  */
5280 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5281 {
5282         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5283                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5284                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5285 }
5286
5287 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5288 {
5289         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5290                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5291                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5292                         | X86_EFLAGS_CF);
5293 }
5294
5295 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5296                                         u32 vm_instruction_error)
5297 {
5298         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5299                 /*
5300                  * failValid writes the error number to the current VMCS, which
5301                  * can't be done there isn't a current VMCS.
5302                  */
5303                 nested_vmx_failInvalid(vcpu);
5304                 return;
5305         }
5306         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5307                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5308                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5309                         | X86_EFLAGS_ZF);
5310         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5311 }
5312
5313 /* Emulate the VMCLEAR instruction */
5314 static int handle_vmclear(struct kvm_vcpu *vcpu)
5315 {
5316         struct vcpu_vmx *vmx = to_vmx(vcpu);
5317         gva_t gva;
5318         gpa_t vmptr;
5319         struct vmcs12 *vmcs12;
5320         struct page *page;
5321         struct x86_exception e;
5322
5323         if (!nested_vmx_check_permission(vcpu))
5324                 return 1;
5325
5326         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5327                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5328                 return 1;
5329
5330         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5331                                 sizeof(vmptr), &e)) {
5332                 kvm_inject_page_fault(vcpu, &e);
5333                 return 1;
5334         }
5335
5336         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5337                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5338                 skip_emulated_instruction(vcpu);
5339                 return 1;
5340         }
5341
5342         if (vmptr == vmx->nested.current_vmptr) {
5343                 kunmap(vmx->nested.current_vmcs12_page);
5344                 nested_release_page(vmx->nested.current_vmcs12_page);
5345                 vmx->nested.current_vmptr = -1ull;
5346                 vmx->nested.current_vmcs12 = NULL;
5347         }
5348
5349         page = nested_get_page(vcpu, vmptr);
5350         if (page == NULL) {
5351                 /*
5352                  * For accurate processor emulation, VMCLEAR beyond available
5353                  * physical memory should do nothing at all. However, it is
5354                  * possible that a nested vmx bug, not a guest hypervisor bug,
5355                  * resulted in this case, so let's shut down before doing any
5356                  * more damage:
5357                  */
5358                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5359                 return 1;
5360         }
5361         vmcs12 = kmap(page);
5362         vmcs12->launch_state = 0;
5363         kunmap(page);
5364         nested_release_page(page);
5365
5366         nested_free_vmcs02(vmx, vmptr);
5367
5368         skip_emulated_instruction(vcpu);
5369         nested_vmx_succeed(vcpu);
5370         return 1;
5371 }
5372
5373 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5374
5375 /* Emulate the VMLAUNCH instruction */
5376 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5377 {
5378         return nested_vmx_run(vcpu, true);
5379 }
5380
5381 /* Emulate the VMRESUME instruction */
5382 static int handle_vmresume(struct kvm_vcpu *vcpu)
5383 {
5384
5385         return nested_vmx_run(vcpu, false);
5386 }
5387
5388 enum vmcs_field_type {
5389         VMCS_FIELD_TYPE_U16 = 0,
5390         VMCS_FIELD_TYPE_U64 = 1,
5391         VMCS_FIELD_TYPE_U32 = 2,
5392         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5393 };
5394
5395 static inline int vmcs_field_type(unsigned long field)
5396 {
5397         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
5398                 return VMCS_FIELD_TYPE_U32;
5399         return (field >> 13) & 0x3 ;
5400 }
5401
5402 static inline int vmcs_field_readonly(unsigned long field)
5403 {
5404         return (((field >> 10) & 0x3) == 1);
5405 }
5406
5407 /*
5408  * Read a vmcs12 field. Since these can have varying lengths and we return
5409  * one type, we chose the biggest type (u64) and zero-extend the return value
5410  * to that size. Note that the caller, handle_vmread, might need to use only
5411  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5412  * 64-bit fields are to be returned).
5413  */
5414 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5415                                         unsigned long field, u64 *ret)
5416 {
5417         short offset = vmcs_field_to_offset(field);
5418         char *p;
5419
5420         if (offset < 0)
5421                 return 0;
5422
5423         p = ((char *)(get_vmcs12(vcpu))) + offset;
5424
5425         switch (vmcs_field_type(field)) {
5426         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5427                 *ret = *((natural_width *)p);
5428                 return 1;
5429         case VMCS_FIELD_TYPE_U16:
5430                 *ret = *((u16 *)p);
5431                 return 1;
5432         case VMCS_FIELD_TYPE_U32:
5433                 *ret = *((u32 *)p);
5434                 return 1;
5435         case VMCS_FIELD_TYPE_U64:
5436                 *ret = *((u64 *)p);
5437                 return 1;
5438         default:
5439                 return 0; /* can never happen. */
5440         }
5441 }
5442
5443 /*
5444  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5445  * used before) all generate the same failure when it is missing.
5446  */
5447 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5448 {
5449         struct vcpu_vmx *vmx = to_vmx(vcpu);
5450         if (vmx->nested.current_vmptr == -1ull) {
5451                 nested_vmx_failInvalid(vcpu);
5452                 skip_emulated_instruction(vcpu);
5453                 return 0;
5454         }
5455         return 1;
5456 }
5457
5458 static int handle_vmread(struct kvm_vcpu *vcpu)
5459 {
5460         unsigned long field;
5461         u64 field_value;
5462         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5463         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5464         gva_t gva = 0;
5465
5466         if (!nested_vmx_check_permission(vcpu) ||
5467             !nested_vmx_check_vmcs12(vcpu))
5468                 return 1;
5469
5470         /* Decode instruction info and find the field to read */
5471         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5472         /* Read the field, zero-extended to a u64 field_value */
5473         if (!vmcs12_read_any(vcpu, field, &field_value)) {
5474                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5475                 skip_emulated_instruction(vcpu);
5476                 return 1;
5477         }
5478         /*
5479          * Now copy part of this value to register or memory, as requested.
5480          * Note that the number of bits actually copied is 32 or 64 depending
5481          * on the guest's mode (32 or 64 bit), not on the given field's length.
5482          */
5483         if (vmx_instruction_info & (1u << 10)) {
5484                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5485                         field_value);
5486         } else {
5487                 if (get_vmx_mem_address(vcpu, exit_qualification,
5488                                 vmx_instruction_info, &gva))
5489                         return 1;
5490                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5491                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5492                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5493         }
5494
5495         nested_vmx_succeed(vcpu);
5496         skip_emulated_instruction(vcpu);
5497         return 1;
5498 }
5499
5500
5501 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5502 {
5503         unsigned long field;
5504         gva_t gva;
5505         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5506         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5507         char *p;
5508         short offset;
5509         /* The value to write might be 32 or 64 bits, depending on L1's long
5510          * mode, and eventually we need to write that into a field of several
5511          * possible lengths. The code below first zero-extends the value to 64
5512          * bit (field_value), and then copies only the approriate number of
5513          * bits into the vmcs12 field.
5514          */
5515         u64 field_value = 0;
5516         struct x86_exception e;
5517
5518         if (!nested_vmx_check_permission(vcpu) ||
5519             !nested_vmx_check_vmcs12(vcpu))
5520                 return 1;
5521
5522         if (vmx_instruction_info & (1u << 10))
5523                 field_value = kvm_register_read(vcpu,
5524                         (((vmx_instruction_info) >> 3) & 0xf));
5525         else {
5526                 if (get_vmx_mem_address(vcpu, exit_qualification,
5527                                 vmx_instruction_info, &gva))
5528                         return 1;
5529                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5530                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5531                         kvm_inject_page_fault(vcpu, &e);
5532                         return 1;
5533                 }
5534         }
5535
5536
5537         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5538         if (vmcs_field_readonly(field)) {
5539                 nested_vmx_failValid(vcpu,
5540                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5541                 skip_emulated_instruction(vcpu);
5542                 return 1;
5543         }
5544
5545         offset = vmcs_field_to_offset(field);
5546         if (offset < 0) {
5547                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5548                 skip_emulated_instruction(vcpu);
5549                 return 1;
5550         }
5551         p = ((char *) get_vmcs12(vcpu)) + offset;
5552
5553         switch (vmcs_field_type(field)) {
5554         case VMCS_FIELD_TYPE_U16:
5555                 *(u16 *)p = field_value;
5556                 break;
5557         case VMCS_FIELD_TYPE_U32:
5558                 *(u32 *)p = field_value;
5559                 break;
5560         case VMCS_FIELD_TYPE_U64:
5561                 *(u64 *)p = field_value;
5562                 break;
5563         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5564                 *(natural_width *)p = field_value;
5565                 break;
5566         default:
5567                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5568                 skip_emulated_instruction(vcpu);
5569                 return 1;
5570         }
5571
5572         nested_vmx_succeed(vcpu);
5573         skip_emulated_instruction(vcpu);
5574         return 1;
5575 }
5576
5577 /* Emulate the VMPTRLD instruction */
5578 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5579 {
5580         struct vcpu_vmx *vmx = to_vmx(vcpu);
5581         gva_t gva;
5582         gpa_t vmptr;
5583         struct x86_exception e;
5584
5585         if (!nested_vmx_check_permission(vcpu))
5586                 return 1;
5587
5588         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5589                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5590                 return 1;
5591
5592         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5593                                 sizeof(vmptr), &e)) {
5594                 kvm_inject_page_fault(vcpu, &e);
5595                 return 1;
5596         }
5597
5598         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5599                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5600                 skip_emulated_instruction(vcpu);
5601                 return 1;
5602         }
5603
5604         if (vmx->nested.current_vmptr != vmptr) {
5605                 struct vmcs12 *new_vmcs12;
5606                 struct page *page;
5607                 page = nested_get_page(vcpu, vmptr);
5608                 if (page == NULL) {
5609                         nested_vmx_failInvalid(vcpu);
5610                         skip_emulated_instruction(vcpu);
5611                         return 1;
5612                 }
5613                 new_vmcs12 = kmap(page);
5614                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5615                         kunmap(page);
5616                         nested_release_page_clean(page);
5617                         nested_vmx_failValid(vcpu,
5618                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5619                         skip_emulated_instruction(vcpu);
5620                         return 1;
5621                 }
5622                 if (vmx->nested.current_vmptr != -1ull) {
5623                         kunmap(vmx->nested.current_vmcs12_page);
5624                         nested_release_page(vmx->nested.current_vmcs12_page);
5625                 }
5626
5627                 vmx->nested.current_vmptr = vmptr;
5628                 vmx->nested.current_vmcs12 = new_vmcs12;
5629                 vmx->nested.current_vmcs12_page = page;
5630         }
5631
5632         nested_vmx_succeed(vcpu);
5633         skip_emulated_instruction(vcpu);
5634         return 1;
5635 }
5636
5637 /* Emulate the VMPTRST instruction */
5638 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5639 {
5640         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5641         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5642         gva_t vmcs_gva;
5643         struct x86_exception e;
5644
5645         if (!nested_vmx_check_permission(vcpu))
5646                 return 1;
5647
5648         if (get_vmx_mem_address(vcpu, exit_qualification,
5649                         vmx_instruction_info, &vmcs_gva))
5650                 return 1;
5651         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5652         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5653                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
5654                                  sizeof(u64), &e)) {
5655                 kvm_inject_page_fault(vcpu, &e);
5656                 return 1;
5657         }
5658         nested_vmx_succeed(vcpu);
5659         skip_emulated_instruction(vcpu);
5660         return 1;
5661 }
5662
5663 /*
5664  * The exit handlers return 1 if the exit was handled fully and guest execution
5665  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5666  * to be done to userspace and return 0.
5667  */
5668 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5669         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
5670         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5671         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5672         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5673         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5674         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5675         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5676         [EXIT_REASON_CPUID]                   = handle_cpuid,
5677         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
5678         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
5679         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
5680         [EXIT_REASON_HLT]                     = handle_halt,
5681         [EXIT_REASON_INVD]                    = handle_invd,
5682         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5683         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
5684         [EXIT_REASON_VMCALL]                  = handle_vmcall,
5685         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
5686         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
5687         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
5688         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
5689         [EXIT_REASON_VMREAD]                  = handle_vmread,
5690         [EXIT_REASON_VMRESUME]                = handle_vmresume,
5691         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
5692         [EXIT_REASON_VMOFF]                   = handle_vmoff,
5693         [EXIT_REASON_VMON]                    = handle_vmon,
5694         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5695         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5696         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
5697         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
5698         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5699         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5700         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5701         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5702         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5703         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
5704         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
5705 };
5706
5707 static const int kvm_vmx_max_exit_handlers =
5708         ARRAY_SIZE(kvm_vmx_exit_handlers);
5709
5710 /*
5711  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5712  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5713  * disinterest in the current event (read or write a specific MSR) by using an
5714  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5715  */
5716 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5717         struct vmcs12 *vmcs12, u32 exit_reason)
5718 {
5719         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5720         gpa_t bitmap;
5721
5722         if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5723                 return 1;
5724
5725         /*
5726          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5727          * for the four combinations of read/write and low/high MSR numbers.
5728          * First we need to figure out which of the four to use:
5729          */
5730         bitmap = vmcs12->msr_bitmap;
5731         if (exit_reason == EXIT_REASON_MSR_WRITE)
5732                 bitmap += 2048;
5733         if (msr_index >= 0xc0000000) {
5734                 msr_index -= 0xc0000000;
5735                 bitmap += 1024;
5736         }
5737
5738         /* Then read the msr_index'th bit from this bitmap: */
5739         if (msr_index < 1024*8) {
5740                 unsigned char b;
5741                 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5742                 return 1 & (b >> (msr_index & 7));
5743         } else
5744                 return 1; /* let L1 handle the wrong parameter */
5745 }
5746
5747 /*
5748  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5749  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5750  * intercept (via guest_host_mask etc.) the current event.
5751  */
5752 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5753         struct vmcs12 *vmcs12)
5754 {
5755         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5756         int cr = exit_qualification & 15;
5757         int reg = (exit_qualification >> 8) & 15;
5758         unsigned long val = kvm_register_read(vcpu, reg);
5759
5760         switch ((exit_qualification >> 4) & 3) {
5761         case 0: /* mov to cr */
5762                 switch (cr) {
5763                 case 0:
5764                         if (vmcs12->cr0_guest_host_mask &
5765                             (val ^ vmcs12->cr0_read_shadow))
5766                                 return 1;
5767                         break;
5768                 case 3:
5769                         if ((vmcs12->cr3_target_count >= 1 &&
5770                                         vmcs12->cr3_target_value0 == val) ||
5771                                 (vmcs12->cr3_target_count >= 2 &&
5772                                         vmcs12->cr3_target_value1 == val) ||
5773                                 (vmcs12->cr3_target_count >= 3 &&
5774                                         vmcs12->cr3_target_value2 == val) ||
5775                                 (vmcs12->cr3_target_count >= 4 &&
5776                                         vmcs12->cr3_target_value3 == val))
5777                                 return 0;
5778                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5779                                 return 1;
5780                         break;
5781                 case 4:
5782                         if (vmcs12->cr4_guest_host_mask &
5783                             (vmcs12->cr4_read_shadow ^ val))
5784                                 return 1;
5785                         break;
5786                 case 8:
5787                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5788                                 return 1;
5789                         break;
5790                 }
5791                 break;
5792         case 2: /* clts */
5793                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5794                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
5795                         return 1;
5796                 break;
5797         case 1: /* mov from cr */
5798                 switch (cr) {
5799                 case 3:
5800                         if (vmcs12->cpu_based_vm_exec_control &
5801                             CPU_BASED_CR3_STORE_EXITING)
5802                                 return 1;
5803                         break;
5804                 case 8:
5805                         if (vmcs12->cpu_based_vm_exec_control &
5806                             CPU_BASED_CR8_STORE_EXITING)
5807                                 return 1;
5808                         break;
5809                 }
5810                 break;
5811         case 3: /* lmsw */
5812                 /*
5813                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5814                  * cr0. Other attempted changes are ignored, with no exit.
5815                  */
5816                 if (vmcs12->cr0_guest_host_mask & 0xe &
5817                     (val ^ vmcs12->cr0_read_shadow))
5818                         return 1;
5819                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5820                     !(vmcs12->cr0_read_shadow & 0x1) &&
5821                     (val & 0x1))
5822                         return 1;
5823                 break;
5824         }
5825         return 0;
5826 }
5827
5828 /*
5829  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5830  * should handle it ourselves in L0 (and then continue L2). Only call this
5831  * when in is_guest_mode (L2).
5832  */
5833 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5834 {
5835         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5836         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5837         struct vcpu_vmx *vmx = to_vmx(vcpu);
5838         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5839
5840         if (vmx->nested.nested_run_pending)
5841                 return 0;
5842
5843         if (unlikely(vmx->fail)) {
5844                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5845                                     vmcs_read32(VM_INSTRUCTION_ERROR));
5846                 return 1;
5847         }
5848
5849         switch (exit_reason) {
5850         case EXIT_REASON_EXCEPTION_NMI:
5851                 if (!is_exception(intr_info))
5852                         return 0;
5853                 else if (is_page_fault(intr_info))
5854                         return enable_ept;
5855                 return vmcs12->exception_bitmap &
5856                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5857         case EXIT_REASON_EXTERNAL_INTERRUPT:
5858                 return 0;
5859         case EXIT_REASON_TRIPLE_FAULT:
5860                 return 1;
5861         case EXIT_REASON_PENDING_INTERRUPT:
5862         case EXIT_REASON_NMI_WINDOW:
5863                 /*
5864                  * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5865                  * (aka Interrupt Window Exiting) only when L1 turned it on,
5866                  * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5867                  * Same for NMI Window Exiting.
5868                  */
5869                 return 1;
5870         case EXIT_REASON_TASK_SWITCH:
5871                 return 1;
5872         case EXIT_REASON_CPUID:
5873                 return 1;
5874         case EXIT_REASON_HLT:
5875                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5876         case EXIT_REASON_INVD:
5877                 return 1;
5878         case EXIT_REASON_INVLPG:
5879                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5880         case EXIT_REASON_RDPMC:
5881                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5882         case EXIT_REASON_RDTSC:
5883                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5884         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5885         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5886         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5887         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5888         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5889                 /*
5890                  * VMX instructions trap unconditionally. This allows L1 to
5891                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
5892                  */
5893                 return 1;
5894         case EXIT_REASON_CR_ACCESS:
5895                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5896         case EXIT_REASON_DR_ACCESS:
5897                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5898         case EXIT_REASON_IO_INSTRUCTION:
5899                 /* TODO: support IO bitmaps */
5900                 return 1;
5901         case EXIT_REASON_MSR_READ:
5902         case EXIT_REASON_MSR_WRITE:
5903                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5904         case EXIT_REASON_INVALID_STATE:
5905                 return 1;
5906         case EXIT_REASON_MWAIT_INSTRUCTION:
5907                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5908         case EXIT_REASON_MONITOR_INSTRUCTION:
5909                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5910         case EXIT_REASON_PAUSE_INSTRUCTION:
5911                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5912                         nested_cpu_has2(vmcs12,
5913                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5914         case EXIT_REASON_MCE_DURING_VMENTRY:
5915                 return 0;
5916         case EXIT_REASON_TPR_BELOW_THRESHOLD:
5917                 return 1;
5918         case EXIT_REASON_APIC_ACCESS:
5919                 return nested_cpu_has2(vmcs12,
5920                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5921         case EXIT_REASON_EPT_VIOLATION:
5922         case EXIT_REASON_EPT_MISCONFIG:
5923                 return 0;
5924         case EXIT_REASON_WBINVD:
5925                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5926         case EXIT_REASON_XSETBV:
5927                 return 1;
5928         default:
5929                 return 1;
5930         }
5931 }
5932
5933 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5934 {
5935         *info1 = vmcs_readl(EXIT_QUALIFICATION);
5936         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5937 }
5938
5939 /*
5940  * The guest has exited.  See if we can fix it or if we need userspace
5941  * assistance.
5942  */
5943 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5944 {
5945         struct vcpu_vmx *vmx = to_vmx(vcpu);
5946         u32 exit_reason = vmx->exit_reason;
5947         u32 vectoring_info = vmx->idt_vectoring_info;
5948
5949         /* If guest state is invalid, start emulating */
5950         if (vmx->emulation_required && emulate_invalid_guest_state)
5951                 return handle_invalid_guest_state(vcpu);
5952
5953         /*
5954          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5955          * we did not inject a still-pending event to L1 now because of
5956          * nested_run_pending, we need to re-enable this bit.
5957          */
5958         if (vmx->nested.nested_run_pending)
5959                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5960
5961         if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5962             exit_reason == EXIT_REASON_VMRESUME))
5963                 vmx->nested.nested_run_pending = 1;
5964         else
5965                 vmx->nested.nested_run_pending = 0;
5966
5967         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5968                 nested_vmx_vmexit(vcpu);
5969                 return 1;
5970         }
5971
5972         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5973                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5974                 vcpu->run->fail_entry.hardware_entry_failure_reason
5975                         = exit_reason;
5976                 return 0;
5977         }
5978
5979         if (unlikely(vmx->fail)) {
5980                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5981                 vcpu->run->fail_entry.hardware_entry_failure_reason
5982                         = vmcs_read32(VM_INSTRUCTION_ERROR);
5983                 return 0;
5984         }
5985
5986         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5987                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5988                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
5989                         exit_reason != EXIT_REASON_TASK_SWITCH))
5990                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
5991                        "(0x%x) and exit reason is 0x%x\n",
5992                        __func__, vectoring_info, exit_reason);
5993
5994         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
5995             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
5996                                         get_vmcs12(vcpu), vcpu)))) {
5997                 if (vmx_interrupt_allowed(vcpu)) {
5998                         vmx->soft_vnmi_blocked = 0;
5999                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
6000                            vcpu->arch.nmi_pending) {
6001                         /*
6002                          * This CPU don't support us in finding the end of an
6003                          * NMI-blocked window if the guest runs with IRQs
6004                          * disabled. So we pull the trigger after 1 s of
6005                          * futile waiting, but inform the user about this.
6006                          */
6007                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6008                                "state on VCPU %d after 1 s timeout\n",
6009                                __func__, vcpu->vcpu_id);
6010                         vmx->soft_vnmi_blocked = 0;
6011                 }
6012         }
6013
6014         if (exit_reason < kvm_vmx_max_exit_handlers
6015             && kvm_vmx_exit_handlers[exit_reason])
6016                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6017         else {
6018                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6019                 vcpu->run->hw.hardware_exit_reason = exit_reason;
6020         }
6021         return 0;
6022 }
6023
6024 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6025 {
6026         if (irr == -1 || tpr < irr) {
6027                 vmcs_write32(TPR_THRESHOLD, 0);
6028                 return;
6029         }
6030
6031         vmcs_write32(TPR_THRESHOLD, irr);
6032 }
6033
6034 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
6035 {
6036         u32 exit_intr_info;
6037
6038         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6039               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6040                 return;
6041
6042         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6043         exit_intr_info = vmx->exit_intr_info;
6044
6045         /* Handle machine checks before interrupts are enabled */
6046         if (is_machine_check(exit_intr_info))
6047                 kvm_machine_check();
6048
6049         /* We need to handle NMIs before interrupts are enabled */
6050         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
6051             (exit_intr_info & INTR_INFO_VALID_MASK)) {
6052                 kvm_before_handle_nmi(&vmx->vcpu);
6053                 asm("int $2");
6054                 kvm_after_handle_nmi(&vmx->vcpu);
6055         }
6056 }
6057
6058 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6059 {
6060         u32 exit_intr_info;
6061         bool unblock_nmi;
6062         u8 vector;
6063         bool idtv_info_valid;
6064
6065         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6066
6067         if (cpu_has_virtual_nmis()) {
6068                 if (vmx->nmi_known_unmasked)
6069                         return;
6070                 /*
6071                  * Can't use vmx->exit_intr_info since we're not sure what
6072                  * the exit reason is.
6073                  */
6074                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6075                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6076                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6077                 /*
6078                  * SDM 3: 27.7.1.2 (September 2008)
6079                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6080                  * a guest IRET fault.
6081                  * SDM 3: 23.2.2 (September 2008)
6082                  * Bit 12 is undefined in any of the following cases:
6083                  *  If the VM exit sets the valid bit in the IDT-vectoring
6084                  *   information field.
6085                  *  If the VM exit is due to a double fault.
6086                  */
6087                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6088                     vector != DF_VECTOR && !idtv_info_valid)
6089                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6090                                       GUEST_INTR_STATE_NMI);
6091                 else
6092                         vmx->nmi_known_unmasked =
6093                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6094                                   & GUEST_INTR_STATE_NMI);
6095         } else if (unlikely(vmx->soft_vnmi_blocked))
6096                 vmx->vnmi_blocked_time +=
6097                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
6098 }
6099
6100 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
6101                                       u32 idt_vectoring_info,
6102                                       int instr_len_field,
6103                                       int error_code_field)
6104 {
6105         u8 vector;
6106         int type;
6107         bool idtv_info_valid;
6108
6109         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6110
6111         vmx->vcpu.arch.nmi_injected = false;
6112         kvm_clear_exception_queue(&vmx->vcpu);
6113         kvm_clear_interrupt_queue(&vmx->vcpu);
6114
6115         if (!idtv_info_valid)
6116                 return;
6117
6118         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6119
6120         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6121         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6122
6123         switch (type) {
6124         case INTR_TYPE_NMI_INTR:
6125                 vmx->vcpu.arch.nmi_injected = true;
6126                 /*
6127                  * SDM 3: 27.7.1.2 (September 2008)
6128                  * Clear bit "block by NMI" before VM entry if a NMI
6129                  * delivery faulted.
6130                  */
6131                 vmx_set_nmi_mask(&vmx->vcpu, false);
6132                 break;
6133         case INTR_TYPE_SOFT_EXCEPTION:
6134                 vmx->vcpu.arch.event_exit_inst_len =
6135                         vmcs_read32(instr_len_field);
6136                 /* fall through */
6137         case INTR_TYPE_HARD_EXCEPTION:
6138                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6139                         u32 err = vmcs_read32(error_code_field);
6140                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
6141                 } else
6142                         kvm_queue_exception(&vmx->vcpu, vector);
6143                 break;
6144         case INTR_TYPE_SOFT_INTR:
6145                 vmx->vcpu.arch.event_exit_inst_len =
6146                         vmcs_read32(instr_len_field);
6147                 /* fall through */
6148         case INTR_TYPE_EXT_INTR:
6149                 kvm_queue_interrupt(&vmx->vcpu, vector,
6150                         type == INTR_TYPE_SOFT_INTR);
6151                 break;
6152         default:
6153                 break;
6154         }
6155 }
6156
6157 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6158 {
6159         if (is_guest_mode(&vmx->vcpu))
6160                 return;
6161         __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6162                                   VM_EXIT_INSTRUCTION_LEN,
6163                                   IDT_VECTORING_ERROR_CODE);
6164 }
6165
6166 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6167 {
6168         if (is_guest_mode(vcpu))
6169                 return;
6170         __vmx_complete_interrupts(to_vmx(vcpu),
6171                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6172                                   VM_ENTRY_INSTRUCTION_LEN,
6173                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6174
6175         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6176 }
6177
6178 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6179 {
6180         int i, nr_msrs;
6181         struct perf_guest_switch_msr *msrs;
6182
6183         msrs = perf_guest_get_msrs(&nr_msrs);
6184
6185         if (!msrs)
6186                 return;
6187
6188         for (i = 0; i < nr_msrs; i++)
6189                 if (msrs[i].host == msrs[i].guest)
6190                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6191                 else
6192                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6193                                         msrs[i].host);
6194 }
6195
6196 #ifdef CONFIG_X86_64
6197 #define R "r"
6198 #define Q "q"
6199 #else
6200 #define R "e"
6201 #define Q "l"
6202 #endif
6203
6204 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6205 {
6206         struct vcpu_vmx *vmx = to_vmx(vcpu);
6207
6208         if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6209                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6210                 if (vmcs12->idt_vectoring_info_field &
6211                                 VECTORING_INFO_VALID_MASK) {
6212                         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6213                                 vmcs12->idt_vectoring_info_field);
6214                         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6215                                 vmcs12->vm_exit_instruction_len);
6216                         if (vmcs12->idt_vectoring_info_field &
6217                                         VECTORING_INFO_DELIVER_CODE_MASK)
6218                                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6219                                         vmcs12->idt_vectoring_error_code);
6220                 }
6221         }
6222
6223         /* Record the guest's net vcpu time for enforced NMI injections. */
6224         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6225                 vmx->entry_time = ktime_get();
6226
6227         /* Don't enter VMX if guest state is invalid, let the exit handler
6228            start emulation until we arrive back to a valid state */
6229         if (vmx->emulation_required && emulate_invalid_guest_state)
6230                 return;
6231
6232         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6233                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6234         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6235                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6236
6237         /* When single-stepping over STI and MOV SS, we must clear the
6238          * corresponding interruptibility bits in the guest state. Otherwise
6239          * vmentry fails as it then expects bit 14 (BS) in pending debug
6240          * exceptions being set, but that's not correct for the guest debugging
6241          * case. */
6242         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6243                 vmx_set_interrupt_shadow(vcpu, 0);
6244
6245         atomic_switch_perf_msrs(vmx);
6246
6247         vmx->__launched = vmx->loaded_vmcs->launched;
6248         asm(
6249                 /* Store host registers */
6250                 "push %%"R"dx; push %%"R"bp;"
6251                 "push %%"R"cx \n\t" /* placeholder for guest rcx */
6252                 "push %%"R"cx \n\t"
6253                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
6254                 "je 1f \n\t"
6255                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
6256                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
6257                 "1: \n\t"
6258                 /* Reload cr2 if changed */
6259                 "mov %c[cr2](%0), %%"R"ax \n\t"
6260                 "mov %%cr2, %%"R"dx \n\t"
6261                 "cmp %%"R"ax, %%"R"dx \n\t"
6262                 "je 2f \n\t"
6263                 "mov %%"R"ax, %%cr2 \n\t"
6264                 "2: \n\t"
6265                 /* Check if vmlaunch of vmresume is needed */
6266                 "cmpl $0, %c[launched](%0) \n\t"
6267                 /* Load guest registers.  Don't clobber flags. */
6268                 "mov %c[rax](%0), %%"R"ax \n\t"
6269                 "mov %c[rbx](%0), %%"R"bx \n\t"
6270                 "mov %c[rdx](%0), %%"R"dx \n\t"
6271                 "mov %c[rsi](%0), %%"R"si \n\t"
6272                 "mov %c[rdi](%0), %%"R"di \n\t"
6273                 "mov %c[rbp](%0), %%"R"bp \n\t"
6274 #ifdef CONFIG_X86_64
6275                 "mov %c[r8](%0),  %%r8  \n\t"
6276                 "mov %c[r9](%0),  %%r9  \n\t"
6277                 "mov %c[r10](%0), %%r10 \n\t"
6278                 "mov %c[r11](%0), %%r11 \n\t"
6279                 "mov %c[r12](%0), %%r12 \n\t"
6280                 "mov %c[r13](%0), %%r13 \n\t"
6281                 "mov %c[r14](%0), %%r14 \n\t"
6282                 "mov %c[r15](%0), %%r15 \n\t"
6283 #endif
6284                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
6285
6286                 /* Enter guest mode */
6287                 "jne .Llaunched \n\t"
6288                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
6289                 "jmp .Lkvm_vmx_return \n\t"
6290                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
6291                 ".Lkvm_vmx_return: "
6292                 /* Save guest registers, load host registers, keep flags */
6293                 "mov %0, %c[wordsize](%%"R"sp) \n\t"
6294                 "pop %0 \n\t"
6295                 "mov %%"R"ax, %c[rax](%0) \n\t"
6296                 "mov %%"R"bx, %c[rbx](%0) \n\t"
6297                 "pop"Q" %c[rcx](%0) \n\t"
6298                 "mov %%"R"dx, %c[rdx](%0) \n\t"
6299                 "mov %%"R"si, %c[rsi](%0) \n\t"
6300                 "mov %%"R"di, %c[rdi](%0) \n\t"
6301                 "mov %%"R"bp, %c[rbp](%0) \n\t"
6302 #ifdef CONFIG_X86_64
6303                 "mov %%r8,  %c[r8](%0) \n\t"
6304                 "mov %%r9,  %c[r9](%0) \n\t"
6305                 "mov %%r10, %c[r10](%0) \n\t"
6306                 "mov %%r11, %c[r11](%0) \n\t"
6307                 "mov %%r12, %c[r12](%0) \n\t"
6308                 "mov %%r13, %c[r13](%0) \n\t"
6309                 "mov %%r14, %c[r14](%0) \n\t"
6310                 "mov %%r15, %c[r15](%0) \n\t"
6311 #endif
6312                 "mov %%cr2, %%"R"ax   \n\t"
6313                 "mov %%"R"ax, %c[cr2](%0) \n\t"
6314
6315                 "pop  %%"R"bp; pop  %%"R"dx \n\t"
6316                 "setbe %c[fail](%0) \n\t"
6317               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
6318                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
6319                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
6320                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
6321                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6322                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6323                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6324                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6325                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6326                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6327                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
6328 #ifdef CONFIG_X86_64
6329                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6330                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6331                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6332                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6333                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6334                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6335                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6336                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6337 #endif
6338                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6339                 [wordsize]"i"(sizeof(ulong))
6340               : "cc", "memory"
6341                 , R"ax", R"bx", R"di", R"si"
6342 #ifdef CONFIG_X86_64
6343                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6344 #endif
6345               );
6346
6347         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6348                                   | (1 << VCPU_EXREG_RFLAGS)
6349                                   | (1 << VCPU_EXREG_CPL)
6350                                   | (1 << VCPU_EXREG_PDPTR)
6351                                   | (1 << VCPU_EXREG_SEGMENTS)
6352                                   | (1 << VCPU_EXREG_CR3));
6353         vcpu->arch.regs_dirty = 0;
6354
6355         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6356
6357         if (is_guest_mode(vcpu)) {
6358                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6359                 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6360                 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6361                         vmcs12->idt_vectoring_error_code =
6362                                 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6363                         vmcs12->vm_exit_instruction_len =
6364                                 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6365                 }
6366         }
6367
6368         vmx->loaded_vmcs->launched = 1;
6369
6370         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
6371         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
6372
6373         vmx_complete_atomic_exit(vmx);
6374         vmx_recover_nmi_blocking(vmx);
6375         vmx_complete_interrupts(vmx);
6376 }
6377
6378 #undef R
6379 #undef Q
6380
6381 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6382 {
6383         struct vcpu_vmx *vmx = to_vmx(vcpu);
6384
6385         free_vpid(vmx);
6386         free_nested(vmx);
6387         free_loaded_vmcs(vmx->loaded_vmcs);
6388         kfree(vmx->guest_msrs);
6389         kvm_vcpu_uninit(vcpu);
6390         kmem_cache_free(kvm_vcpu_cache, vmx);
6391 }
6392
6393 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6394 {
6395         int err;
6396         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
6397         int cpu;
6398
6399         if (!vmx)
6400                 return ERR_PTR(-ENOMEM);
6401
6402         allocate_vpid(vmx);
6403
6404         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6405         if (err)
6406                 goto free_vcpu;
6407
6408         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
6409         err = -ENOMEM;
6410         if (!vmx->guest_msrs) {
6411                 goto uninit_vcpu;
6412         }
6413
6414         vmx->loaded_vmcs = &vmx->vmcs01;
6415         vmx->loaded_vmcs->vmcs = alloc_vmcs();
6416         if (!vmx->loaded_vmcs->vmcs)
6417                 goto free_msrs;
6418         if (!vmm_exclusive)
6419                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6420         loaded_vmcs_init(vmx->loaded_vmcs);
6421         if (!vmm_exclusive)
6422                 kvm_cpu_vmxoff();
6423
6424         cpu = get_cpu();
6425         vmx_vcpu_load(&vmx->vcpu, cpu);
6426         vmx->vcpu.cpu = cpu;
6427         err = vmx_vcpu_setup(vmx);
6428         vmx_vcpu_put(&vmx->vcpu);
6429         put_cpu();
6430         if (err)
6431                 goto free_vmcs;
6432         if (vm_need_virtualize_apic_accesses(kvm))
6433                 err = alloc_apic_access_page(kvm);
6434                 if (err)
6435                         goto free_vmcs;
6436
6437         if (enable_ept) {
6438                 if (!kvm->arch.ept_identity_map_addr)
6439                         kvm->arch.ept_identity_map_addr =
6440                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
6441                 err = -ENOMEM;
6442                 if (alloc_identity_pagetable(kvm) != 0)
6443                         goto free_vmcs;
6444                 if (!init_rmode_identity_map(kvm))
6445                         goto free_vmcs;
6446         }
6447
6448         vmx->nested.current_vmptr = -1ull;
6449         vmx->nested.current_vmcs12 = NULL;
6450
6451         return &vmx->vcpu;
6452
6453 free_vmcs:
6454         free_loaded_vmcs(vmx->loaded_vmcs);
6455 free_msrs:
6456         kfree(vmx->guest_msrs);
6457 uninit_vcpu:
6458         kvm_vcpu_uninit(&vmx->vcpu);
6459 free_vcpu:
6460         free_vpid(vmx);
6461         kmem_cache_free(kvm_vcpu_cache, vmx);
6462         return ERR_PTR(err);
6463 }
6464
6465 static void __init vmx_check_processor_compat(void *rtn)
6466 {
6467         struct vmcs_config vmcs_conf;
6468
6469         *(int *)rtn = 0;
6470         if (setup_vmcs_config(&vmcs_conf) < 0)
6471                 *(int *)rtn = -EIO;
6472         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6473                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6474                                 smp_processor_id());
6475                 *(int *)rtn = -EIO;
6476         }
6477 }
6478
6479 static int get_ept_level(void)
6480 {
6481         return VMX_EPT_DEFAULT_GAW + 1;
6482 }
6483
6484 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6485 {
6486         u64 ret;
6487
6488         /* For VT-d and EPT combination
6489          * 1. MMIO: always map as UC
6490          * 2. EPT with VT-d:
6491          *   a. VT-d without snooping control feature: can't guarantee the
6492          *      result, try to trust guest.
6493          *   b. VT-d with snooping control feature: snooping control feature of
6494          *      VT-d engine can guarantee the cache correctness. Just set it
6495          *      to WB to keep consistent with host. So the same as item 3.
6496          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6497          *    consistent with host MTRR
6498          */
6499         if (is_mmio)
6500                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
6501         else if (vcpu->kvm->arch.iommu_domain &&
6502                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6503                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6504                       VMX_EPT_MT_EPTE_SHIFT;
6505         else
6506                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
6507                         | VMX_EPT_IPAT_BIT;
6508
6509         return ret;
6510 }
6511
6512 static int vmx_get_lpage_level(void)
6513 {
6514         if (enable_ept && !cpu_has_vmx_ept_1g_page())
6515                 return PT_DIRECTORY_LEVEL;
6516         else
6517                 /* For shadow and EPT supported 1GB page */
6518                 return PT_PDPE_LEVEL;
6519 }
6520
6521 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6522 {
6523         struct kvm_cpuid_entry2 *best;
6524         struct vcpu_vmx *vmx = to_vmx(vcpu);
6525         u32 exec_control;
6526
6527         vmx->rdtscp_enabled = false;
6528         if (vmx_rdtscp_supported()) {
6529                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6530                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6531                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6532                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6533                                 vmx->rdtscp_enabled = true;
6534                         else {
6535                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6536                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6537                                                 exec_control);
6538                         }
6539                 }
6540         }
6541 }
6542
6543 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6544 {
6545         if (func == 1 && nested)
6546                 entry->ecx |= bit(X86_FEATURE_VMX);
6547 }
6548
6549 /*
6550  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6551  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6552  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6553  * guest in a way that will both be appropriate to L1's requests, and our
6554  * needs. In addition to modifying the active vmcs (which is vmcs02), this
6555  * function also has additional necessary side-effects, like setting various
6556  * vcpu->arch fields.
6557  */
6558 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6559 {
6560         struct vcpu_vmx *vmx = to_vmx(vcpu);
6561         u32 exec_control;
6562
6563         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6564         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6565         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6566         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6567         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6568         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6569         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6570         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6571         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6572         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6573         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6574         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6575         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6576         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6577         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6578         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6579         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6580         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6581         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6582         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6583         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6584         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6585         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6586         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6587         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6588         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6589         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6590         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6591         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6592         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6593         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6594         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6595         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6596         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6597         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6598         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6599
6600         vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6601         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6602                 vmcs12->vm_entry_intr_info_field);
6603         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6604                 vmcs12->vm_entry_exception_error_code);
6605         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6606                 vmcs12->vm_entry_instruction_len);
6607         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6608                 vmcs12->guest_interruptibility_info);
6609         vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6610         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6611         vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6612         vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6613         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6614                 vmcs12->guest_pending_dbg_exceptions);
6615         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6616         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6617
6618         vmcs_write64(VMCS_LINK_POINTER, -1ull);
6619
6620         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6621                 (vmcs_config.pin_based_exec_ctrl |
6622                  vmcs12->pin_based_vm_exec_control));
6623
6624         /*
6625          * Whether page-faults are trapped is determined by a combination of
6626          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6627          * If enable_ept, L0 doesn't care about page faults and we should
6628          * set all of these to L1's desires. However, if !enable_ept, L0 does
6629          * care about (at least some) page faults, and because it is not easy
6630          * (if at all possible?) to merge L0 and L1's desires, we simply ask
6631          * to exit on each and every L2 page fault. This is done by setting
6632          * MASK=MATCH=0 and (see below) EB.PF=1.
6633          * Note that below we don't need special code to set EB.PF beyond the
6634          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6635          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6636          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6637          *
6638          * A problem with this approach (when !enable_ept) is that L1 may be
6639          * injected with more page faults than it asked for. This could have
6640          * caused problems, but in practice existing hypervisors don't care.
6641          * To fix this, we will need to emulate the PFEC checking (on the L1
6642          * page tables), using walk_addr(), when injecting PFs to L1.
6643          */
6644         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6645                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6646         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6647                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6648
6649         if (cpu_has_secondary_exec_ctrls()) {
6650                 u32 exec_control = vmx_secondary_exec_control(vmx);
6651                 if (!vmx->rdtscp_enabled)
6652                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
6653                 /* Take the following fields only from vmcs12 */
6654                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6655                 if (nested_cpu_has(vmcs12,
6656                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6657                         exec_control |= vmcs12->secondary_vm_exec_control;
6658
6659                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6660                         /*
6661                          * Translate L1 physical address to host physical
6662                          * address for vmcs02. Keep the page pinned, so this
6663                          * physical address remains valid. We keep a reference
6664                          * to it so we can release it later.
6665                          */
6666                         if (vmx->nested.apic_access_page) /* shouldn't happen */
6667                                 nested_release_page(vmx->nested.apic_access_page);
6668                         vmx->nested.apic_access_page =
6669                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
6670                         /*
6671                          * If translation failed, no matter: This feature asks
6672                          * to exit when accessing the given address, and if it
6673                          * can never be accessed, this feature won't do
6674                          * anything anyway.
6675                          */
6676                         if (!vmx->nested.apic_access_page)
6677                                 exec_control &=
6678                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6679                         else
6680                                 vmcs_write64(APIC_ACCESS_ADDR,
6681                                   page_to_phys(vmx->nested.apic_access_page));
6682                 }
6683
6684                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6685         }
6686
6687
6688         /*
6689          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6690          * Some constant fields are set here by vmx_set_constant_host_state().
6691          * Other fields are different per CPU, and will be set later when
6692          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6693          */
6694         vmx_set_constant_host_state();
6695
6696         /*
6697          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6698          * entry, but only if the current (host) sp changed from the value
6699          * we wrote last (vmx->host_rsp). This cache is no longer relevant
6700          * if we switch vmcs, and rather than hold a separate cache per vmcs,
6701          * here we just force the write to happen on entry.
6702          */
6703         vmx->host_rsp = 0;
6704
6705         exec_control = vmx_exec_control(vmx); /* L0's desires */
6706         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6707         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6708         exec_control &= ~CPU_BASED_TPR_SHADOW;
6709         exec_control |= vmcs12->cpu_based_vm_exec_control;
6710         /*
6711          * Merging of IO and MSR bitmaps not currently supported.
6712          * Rather, exit every time.
6713          */
6714         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6715         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6716         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6717
6718         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6719
6720         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6721          * bitwise-or of what L1 wants to trap for L2, and what we want to
6722          * trap. Note that CR0.TS also needs updating - we do this later.
6723          */
6724         update_exception_bitmap(vcpu);
6725         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6726         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6727
6728         /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6729         vmcs_write32(VM_EXIT_CONTROLS,
6730                 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6731         vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6732                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6733
6734         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6735                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6736         else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6737                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6738
6739
6740         set_cr4_guest_host_mask(vmx);
6741
6742         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6743                 vmcs_write64(TSC_OFFSET,
6744                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6745         else
6746                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
6747
6748         if (enable_vpid) {
6749                 /*
6750                  * Trivially support vpid by letting L2s share their parent
6751                  * L1's vpid. TODO: move to a more elaborate solution, giving
6752                  * each L2 its own vpid and exposing the vpid feature to L1.
6753                  */
6754                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6755                 vmx_flush_tlb(vcpu);
6756         }
6757
6758         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6759                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6760         if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6761                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6762         else
6763                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6764         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6765         vmx_set_efer(vcpu, vcpu->arch.efer);
6766
6767         /*
6768          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6769          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6770          * The CR0_READ_SHADOW is what L2 should have expected to read given
6771          * the specifications by L1; It's not enough to take
6772          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6773          * have more bits than L1 expected.
6774          */
6775         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6776         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6777
6778         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6779         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6780
6781         /* shadow page tables on either EPT or shadow page tables */
6782         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6783         kvm_mmu_reset_context(vcpu);
6784
6785         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6786         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6787 }
6788
6789 /*
6790  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6791  * for running an L2 nested guest.
6792  */
6793 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6794 {
6795         struct vmcs12 *vmcs12;
6796         struct vcpu_vmx *vmx = to_vmx(vcpu);
6797         int cpu;
6798         struct loaded_vmcs *vmcs02;
6799
6800         if (!nested_vmx_check_permission(vcpu) ||
6801             !nested_vmx_check_vmcs12(vcpu))
6802                 return 1;
6803
6804         skip_emulated_instruction(vcpu);
6805         vmcs12 = get_vmcs12(vcpu);
6806
6807         /*
6808          * The nested entry process starts with enforcing various prerequisites
6809          * on vmcs12 as required by the Intel SDM, and act appropriately when
6810          * they fail: As the SDM explains, some conditions should cause the
6811          * instruction to fail, while others will cause the instruction to seem
6812          * to succeed, but return an EXIT_REASON_INVALID_STATE.
6813          * To speed up the normal (success) code path, we should avoid checking
6814          * for misconfigurations which will anyway be caught by the processor
6815          * when using the merged vmcs02.
6816          */
6817         if (vmcs12->launch_state == launch) {
6818                 nested_vmx_failValid(vcpu,
6819                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6820                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6821                 return 1;
6822         }
6823
6824         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6825                         !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6826                 /*TODO: Also verify bits beyond physical address width are 0*/
6827                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6828                 return 1;
6829         }
6830
6831         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6832                         !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6833                 /*TODO: Also verify bits beyond physical address width are 0*/
6834                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6835                 return 1;
6836         }
6837
6838         if (vmcs12->vm_entry_msr_load_count > 0 ||
6839             vmcs12->vm_exit_msr_load_count > 0 ||
6840             vmcs12->vm_exit_msr_store_count > 0) {
6841                 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6842                                     __func__);
6843                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6844                 return 1;
6845         }
6846
6847         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6848               nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6849             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6850               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6851             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6852               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6853             !vmx_control_verify(vmcs12->vm_exit_controls,
6854               nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6855             !vmx_control_verify(vmcs12->vm_entry_controls,
6856               nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6857         {
6858                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6859                 return 1;
6860         }
6861
6862         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6863             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6864                 nested_vmx_failValid(vcpu,
6865                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6866                 return 1;
6867         }
6868
6869         if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6870             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6871                 nested_vmx_entry_failure(vcpu, vmcs12,
6872                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6873                 return 1;
6874         }
6875         if (vmcs12->vmcs_link_pointer != -1ull) {
6876                 nested_vmx_entry_failure(vcpu, vmcs12,
6877                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6878                 return 1;
6879         }
6880
6881         /*
6882          * We're finally done with prerequisite checking, and can start with
6883          * the nested entry.
6884          */
6885
6886         vmcs02 = nested_get_current_vmcs02(vmx);
6887         if (!vmcs02)
6888                 return -ENOMEM;
6889
6890         enter_guest_mode(vcpu);
6891
6892         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6893
6894         cpu = get_cpu();
6895         vmx->loaded_vmcs = vmcs02;
6896         vmx_vcpu_put(vcpu);
6897         vmx_vcpu_load(vcpu, cpu);
6898         vcpu->cpu = cpu;
6899         put_cpu();
6900
6901         vmcs12->launch_state = 1;
6902
6903         prepare_vmcs02(vcpu, vmcs12);
6904
6905         /*
6906          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6907          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6908          * returned as far as L1 is concerned. It will only return (and set
6909          * the success flag) when L2 exits (see nested_vmx_vmexit()).
6910          */
6911         return 1;
6912 }
6913
6914 /*
6915  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6916  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6917  * This function returns the new value we should put in vmcs12.guest_cr0.
6918  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6919  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6920  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6921  *     didn't trap the bit, because if L1 did, so would L0).
6922  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6923  *     been modified by L2, and L1 knows it. So just leave the old value of
6924  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6925  *     isn't relevant, because if L0 traps this bit it can set it to anything.
6926  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6927  *     changed these bits, and therefore they need to be updated, but L0
6928  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6929  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6930  */
6931 static inline unsigned long
6932 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6933 {
6934         return
6935         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6936         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6937         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6938                         vcpu->arch.cr0_guest_owned_bits));
6939 }
6940
6941 static inline unsigned long
6942 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6943 {
6944         return
6945         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
6946         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
6947         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
6948                         vcpu->arch.cr4_guest_owned_bits));
6949 }
6950
6951 /*
6952  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6953  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6954  * and this function updates it to reflect the changes to the guest state while
6955  * L2 was running (and perhaps made some exits which were handled directly by L0
6956  * without going back to L1), and to reflect the exit reason.
6957  * Note that we do not have to copy here all VMCS fields, just those that
6958  * could have changed by the L2 guest or the exit - i.e., the guest-state and
6959  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
6960  * which already writes to vmcs12 directly.
6961  */
6962 void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6963 {
6964         /* update guest state fields: */
6965         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
6966         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
6967
6968         kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
6969         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6970         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
6971         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
6972
6973         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
6974         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
6975         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
6976         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
6977         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
6978         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
6979         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
6980         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
6981         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
6982         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
6983         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
6984         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
6985         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
6986         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
6987         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
6988         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
6989         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
6990         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
6991         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
6992         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
6993         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
6994         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
6995         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
6996         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
6997         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
6998         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
6999         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7000         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7001         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7002         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7003         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7004         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7005         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7006         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7007         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7008         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7009
7010         vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
7011         vmcs12->guest_interruptibility_info =
7012                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7013         vmcs12->guest_pending_dbg_exceptions =
7014                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7015
7016         /* TODO: These cannot have changed unless we have MSR bitmaps and
7017          * the relevant bit asks not to trap the change */
7018         vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
7019         if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
7020                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7021         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7022         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7023         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7024
7025         /* update exit information fields: */
7026
7027         vmcs12->vm_exit_reason  = vmcs_read32(VM_EXIT_REASON);
7028         vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7029
7030         vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7031         vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7032         vmcs12->idt_vectoring_info_field =
7033                 vmcs_read32(IDT_VECTORING_INFO_FIELD);
7034         vmcs12->idt_vectoring_error_code =
7035                 vmcs_read32(IDT_VECTORING_ERROR_CODE);
7036         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7037         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7038
7039         /* clear vm-entry fields which are to be cleared on exit */
7040         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
7041                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
7042 }
7043
7044 /*
7045  * A part of what we need to when the nested L2 guest exits and we want to
7046  * run its L1 parent, is to reset L1's guest state to the host state specified
7047  * in vmcs12.
7048  * This function is to be called not only on normal nested exit, but also on
7049  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7050  * Failures During or After Loading Guest State").
7051  * This function should be called when the active VMCS is L1's (vmcs01).
7052  */
7053 void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7054 {
7055         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7056                 vcpu->arch.efer = vmcs12->host_ia32_efer;
7057         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7058                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7059         else
7060                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7061         vmx_set_efer(vcpu, vcpu->arch.efer);
7062
7063         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7064         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
7065         /*
7066          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7067          * actually changed, because it depends on the current state of
7068          * fpu_active (which may have changed).
7069          * Note that vmx_set_cr0 refers to efer set above.
7070          */
7071         kvm_set_cr0(vcpu, vmcs12->host_cr0);
7072         /*
7073          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7074          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7075          * but we also need to update cr0_guest_host_mask and exception_bitmap.
7076          */
7077         update_exception_bitmap(vcpu);
7078         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7079         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7080
7081         /*
7082          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7083          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7084          */
7085         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7086         kvm_set_cr4(vcpu, vmcs12->host_cr4);
7087
7088         /* shadow page tables on either EPT or shadow page tables */
7089         kvm_set_cr3(vcpu, vmcs12->host_cr3);
7090         kvm_mmu_reset_context(vcpu);
7091
7092         if (enable_vpid) {
7093                 /*
7094                  * Trivially support vpid by letting L2s share their parent
7095                  * L1's vpid. TODO: move to a more elaborate solution, giving
7096                  * each L2 its own vpid and exposing the vpid feature to L1.
7097                  */
7098                 vmx_flush_tlb(vcpu);
7099         }
7100
7101
7102         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7103         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7104         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7105         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7106         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7107         vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7108         vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7109         vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7110         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7111         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7112         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7113         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7114         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7115         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7116         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7117
7118         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7119                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7120         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7121                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7122                         vmcs12->host_ia32_perf_global_ctrl);
7123 }
7124
7125 /*
7126  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7127  * and modify vmcs12 to make it see what it would expect to see there if
7128  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7129  */
7130 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7131 {
7132         struct vcpu_vmx *vmx = to_vmx(vcpu);
7133         int cpu;
7134         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7135
7136         leave_guest_mode(vcpu);
7137         prepare_vmcs12(vcpu, vmcs12);
7138
7139         cpu = get_cpu();
7140         vmx->loaded_vmcs = &vmx->vmcs01;
7141         vmx_vcpu_put(vcpu);
7142         vmx_vcpu_load(vcpu, cpu);
7143         vcpu->cpu = cpu;
7144         put_cpu();
7145
7146         /* if no vmcs02 cache requested, remove the one we used */
7147         if (VMCS02_POOL_SIZE == 0)
7148                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7149
7150         load_vmcs12_host_state(vcpu, vmcs12);
7151
7152         /* Update TSC_OFFSET if TSC was changed while L2 ran */
7153         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7154
7155         /* This is needed for same reason as it was needed in prepare_vmcs02 */
7156         vmx->host_rsp = 0;
7157
7158         /* Unpin physical memory we referred to in vmcs02 */
7159         if (vmx->nested.apic_access_page) {
7160                 nested_release_page(vmx->nested.apic_access_page);
7161                 vmx->nested.apic_access_page = 0;
7162         }
7163
7164         /*
7165          * Exiting from L2 to L1, we're now back to L1 which thinks it just
7166          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7167          * success or failure flag accordingly.
7168          */
7169         if (unlikely(vmx->fail)) {
7170                 vmx->fail = 0;
7171                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7172         } else
7173                 nested_vmx_succeed(vcpu);
7174 }
7175
7176 /*
7177  * L1's failure to enter L2 is a subset of a normal exit, as explained in
7178  * 23.7 "VM-entry failures during or after loading guest state" (this also
7179  * lists the acceptable exit-reason and exit-qualification parameters).
7180  * It should only be called before L2 actually succeeded to run, and when
7181  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7182  */
7183 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7184                         struct vmcs12 *vmcs12,
7185                         u32 reason, unsigned long qualification)
7186 {
7187         load_vmcs12_host_state(vcpu, vmcs12);
7188         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7189         vmcs12->exit_qualification = qualification;
7190         nested_vmx_succeed(vcpu);
7191 }
7192
7193 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7194                                struct x86_instruction_info *info,
7195                                enum x86_intercept_stage stage)
7196 {
7197         return X86EMUL_CONTINUE;
7198 }
7199
7200 static struct kvm_x86_ops vmx_x86_ops = {
7201         .cpu_has_kvm_support = cpu_has_kvm_support,
7202         .disabled_by_bios = vmx_disabled_by_bios,
7203         .hardware_setup = hardware_setup,
7204         .hardware_unsetup = hardware_unsetup,
7205         .check_processor_compatibility = vmx_check_processor_compat,
7206         .hardware_enable = hardware_enable,
7207         .hardware_disable = hardware_disable,
7208         .cpu_has_accelerated_tpr = report_flexpriority,
7209
7210         .vcpu_create = vmx_create_vcpu,
7211         .vcpu_free = vmx_free_vcpu,
7212         .vcpu_reset = vmx_vcpu_reset,
7213
7214         .prepare_guest_switch = vmx_save_host_state,
7215         .vcpu_load = vmx_vcpu_load,
7216         .vcpu_put = vmx_vcpu_put,
7217
7218         .set_guest_debug = set_guest_debug,
7219         .get_msr = vmx_get_msr,
7220         .set_msr = vmx_set_msr,
7221         .get_segment_base = vmx_get_segment_base,
7222         .get_segment = vmx_get_segment,
7223         .set_segment = vmx_set_segment,
7224         .get_cpl = vmx_get_cpl,
7225         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7226         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7227         .decache_cr3 = vmx_decache_cr3,
7228         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7229         .set_cr0 = vmx_set_cr0,
7230         .set_cr3 = vmx_set_cr3,
7231         .set_cr4 = vmx_set_cr4,
7232         .set_efer = vmx_set_efer,
7233         .get_idt = vmx_get_idt,
7234         .set_idt = vmx_set_idt,
7235         .get_gdt = vmx_get_gdt,
7236         .set_gdt = vmx_set_gdt,
7237         .set_dr7 = vmx_set_dr7,
7238         .cache_reg = vmx_cache_reg,
7239         .get_rflags = vmx_get_rflags,
7240         .set_rflags = vmx_set_rflags,
7241         .fpu_activate = vmx_fpu_activate,
7242         .fpu_deactivate = vmx_fpu_deactivate,
7243
7244         .tlb_flush = vmx_flush_tlb,
7245
7246         .run = vmx_vcpu_run,
7247         .handle_exit = vmx_handle_exit,
7248         .skip_emulated_instruction = skip_emulated_instruction,
7249         .set_interrupt_shadow = vmx_set_interrupt_shadow,
7250         .get_interrupt_shadow = vmx_get_interrupt_shadow,
7251         .patch_hypercall = vmx_patch_hypercall,
7252         .set_irq = vmx_inject_irq,
7253         .set_nmi = vmx_inject_nmi,
7254         .queue_exception = vmx_queue_exception,
7255         .cancel_injection = vmx_cancel_injection,
7256         .interrupt_allowed = vmx_interrupt_allowed,
7257         .nmi_allowed = vmx_nmi_allowed,
7258         .get_nmi_mask = vmx_get_nmi_mask,
7259         .set_nmi_mask = vmx_set_nmi_mask,
7260         .enable_nmi_window = enable_nmi_window,
7261         .enable_irq_window = enable_irq_window,
7262         .update_cr8_intercept = update_cr8_intercept,
7263
7264         .set_tss_addr = vmx_set_tss_addr,
7265         .get_tdp_level = get_ept_level,
7266         .get_mt_mask = vmx_get_mt_mask,
7267
7268         .get_exit_info = vmx_get_exit_info,
7269
7270         .get_lpage_level = vmx_get_lpage_level,
7271
7272         .cpuid_update = vmx_cpuid_update,
7273
7274         .rdtscp_supported = vmx_rdtscp_supported,
7275
7276         .set_supported_cpuid = vmx_set_supported_cpuid,
7277
7278         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7279
7280         .set_tsc_khz = vmx_set_tsc_khz,
7281         .write_tsc_offset = vmx_write_tsc_offset,
7282         .adjust_tsc_offset = vmx_adjust_tsc_offset,
7283         .compute_tsc_offset = vmx_compute_tsc_offset,
7284         .read_l1_tsc = vmx_read_l1_tsc,
7285
7286         .set_tdp_cr3 = vmx_set_cr3,
7287
7288         .check_intercept = vmx_check_intercept,
7289 };
7290
7291 static int __init vmx_init(void)
7292 {
7293         int r, i;
7294
7295         rdmsrl_safe(MSR_EFER, &host_efer);
7296
7297         for (i = 0; i < NR_VMX_MSR; ++i)
7298                 kvm_define_shared_msr(i, vmx_msr_index[i]);
7299
7300         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
7301         if (!vmx_io_bitmap_a)
7302                 return -ENOMEM;
7303
7304         r = -ENOMEM;
7305
7306         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
7307         if (!vmx_io_bitmap_b)
7308                 goto out;
7309
7310         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
7311         if (!vmx_msr_bitmap_legacy)
7312                 goto out1;
7313
7314
7315         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
7316         if (!vmx_msr_bitmap_longmode)
7317                 goto out2;
7318
7319
7320         /*
7321          * Allow direct access to the PC debug port (it is often used for I/O
7322          * delays, but the vmexits simply slow things down).
7323          */
7324         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7325         clear_bit(0x80, vmx_io_bitmap_a);
7326
7327         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
7328
7329         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7330         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
7331
7332         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7333
7334         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7335                      __alignof__(struct vcpu_vmx), THIS_MODULE);
7336         if (r)
7337                 goto out3;
7338
7339         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7340         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7341         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7342         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7343         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7344         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
7345
7346         if (enable_ept) {
7347                 kvm_mmu_set_mask_ptes(0ull,
7348                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
7349                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
7350                         0ull, VMX_EPT_EXECUTABLE_MASK);
7351                 ept_set_mmio_spte_mask();
7352                 kvm_enable_tdp();
7353         } else
7354                 kvm_disable_tdp();
7355
7356         return 0;
7357
7358 out3:
7359         free_page((unsigned long)vmx_msr_bitmap_longmode);
7360 out2:
7361         free_page((unsigned long)vmx_msr_bitmap_legacy);
7362 out1:
7363         free_page((unsigned long)vmx_io_bitmap_b);
7364 out:
7365         free_page((unsigned long)vmx_io_bitmap_a);
7366         return r;
7367 }
7368
7369 static void __exit vmx_exit(void)
7370 {
7371         free_page((unsigned long)vmx_msr_bitmap_legacy);
7372         free_page((unsigned long)vmx_msr_bitmap_longmode);
7373         free_page((unsigned long)vmx_io_bitmap_b);
7374         free_page((unsigned long)vmx_io_bitmap_a);
7375
7376         kvm_exit();
7377 }
7378
7379 module_init(vmx_init)
7380 module_exit(vmx_exit)