arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include <linux/frame.h>
  37 #include "kvm_cache_regs.h"
  38 #include "x86.h"
  39
  40 #include <asm/cpu.h>
  41 #include <asm/io.h>
  42 #include <asm/desc.h>
  43 #include <asm/vmx.h>
  44 #include <asm/virtext.h>
  45 #include <asm/mce.h>
  46 #include <asm/fpu/internal.h>
  47 #include <asm/perf_event.h>
  48 #include <asm/debugreg.h>
  49 #include <asm/kexec.h>
  50 #include <asm/apic.h>
  51 #include <asm/irq_remapping.h>
  52 #include <asm/mmu_context.h>
  53
  54 #include "trace.h"
  55 #include "pmu.h"
  56
  57 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  58 #define __ex_clear(x, reg) \
  59         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  60
  61 MODULE_AUTHOR("Qumranet");
  62 MODULE_LICENSE("GPL");
  63
  64 static const struct x86_cpu_id vmx_cpu_id[] = {
  65         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  66         {}
  67 };
  68 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  69
  70 static bool __read_mostly enable_vpid = 1;
  71 module_param_named(vpid, enable_vpid, bool, 0444);
  72
  73 static bool __read_mostly flexpriority_enabled = 1;
  74 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  75
  76 static bool __read_mostly enable_ept = 1;
  77 module_param_named(ept, enable_ept, bool, S_IRUGO);
  78
  79 static bool __read_mostly enable_unrestricted_guest = 1;
  80 module_param_named(unrestricted_guest,
  81                         enable_unrestricted_guest, bool, S_IRUGO);
  82
  83 static bool __read_mostly enable_ept_ad_bits = 1;
  84 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  85
  86 static bool __read_mostly emulate_invalid_guest_state = true;
  87 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  88
  89 static bool __read_mostly fasteoi = 1;
  90 module_param(fasteoi, bool, S_IRUGO);
  91
  92 static bool __read_mostly enable_apicv = 1;
  93 module_param(enable_apicv, bool, S_IRUGO);
  94
  95 static bool __read_mostly enable_shadow_vmcs = 1;
  96 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  97 /*
  98  * If nested=1, nested virtualization is supported, i.e., guests may use
  99  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 100  * use VMX instructions.
 101  */
 102 static bool __read_mostly nested = 0;
 103 module_param(nested, bool, S_IRUGO);
 104
 105 static u64 __read_mostly host_xss;
 106
 107 static bool __read_mostly enable_pml = 1;
 108 module_param_named(pml, enable_pml, bool, S_IRUGO);
 109
 110 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 111
 112 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 113 static int __read_mostly cpu_preemption_timer_multi;
 114 static bool __read_mostly enable_preemption_timer = 1;
 115 #ifdef CONFIG_X86_64
 116 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 117 #endif
 118
 119 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 120 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 121 #define KVM_VM_CR0_ALWAYS_ON                                            \
 122         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 123 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 124         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 125          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 126
 127 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 128 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 129
 130 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 131
 132 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 133
 134 /*
 135  * Hyper-V requires all of these, so mark them as supported even though
 136  * they are just treated the same as all-context.
 137  */
 138 #define VMX_VPID_EXTENT_SUPPORTED_MASK          \
 139         (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT |  \
 140         VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |    \
 141         VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT |    \
 142         VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
 143
 144 /*
 145  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 146  * ple_gap:    upper bound on the amount of time between two successive
 147  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 148  *             According to test, this time is usually smaller than 128 cycles.
 149  * ple_window: upper bound on the amount of time a guest is allowed to execute
 150  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 151  *             less than 2^12 cycles
 152  * Time is measured based on a counter that runs at the same rate as the TSC,
 153  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 154  */
 155 #define KVM_VMX_DEFAULT_PLE_GAP           128
 156 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 157 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 158 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 159 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 160                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 161
 162 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 163 module_param(ple_gap, int, S_IRUGO);
 164
 165 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 166 module_param(ple_window, int, S_IRUGO);
 167
 168 /* Default doubles per-vcpu window every exit. */
 169 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 170 module_param(ple_window_grow, int, S_IRUGO);
 171
 172 /* Default resets per-vcpu window every exit to ple_window. */
 173 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 174 module_param(ple_window_shrink, int, S_IRUGO);
 175
 176 /* Default is to compute the maximum so we can never overflow. */
 177 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 178 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 179 module_param(ple_window_max, int, S_IRUGO);
 180
 181 extern const ulong vmx_return;
 182
 183 #define NR_AUTOLOAD_MSRS 8
 184 #define VMCS02_POOL_SIZE 1
 185
 186 struct vmcs {
 187         u32 revision_id;
 188         u32 abort;
 189         char data[0];
 190 };
 191
 192 /*
 193  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 194  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 195  * loaded on this CPU (so we can clear them if the CPU goes down).
 196  */
 197 struct loaded_vmcs {
 198         struct vmcs *vmcs;
 199         struct vmcs *shadow_vmcs;
 200         int cpu;
 201         bool launched;
 202         bool nmi_known_unmasked;
 203         struct list_head loaded_vmcss_on_cpu_link;
 204 };
 205
 206 struct shared_msr_entry {
 207         unsigned index;
 208         u64 data;
 209         u64 mask;
 210 };
 211
 212 /*
 213  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 214  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 215  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 216  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 217  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 218  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 219  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 220  * underlying hardware which will be used to run L2.
 221  * This structure is packed to ensure that its layout is identical across
 222  * machines (necessary for live migration).
 223  * If there are changes in this struct, VMCS12_REVISION must be changed.
 224  */
 225 typedef u64 natural_width;
 226 struct __packed vmcs12 {
 227         /* According to the Intel spec, a VMCS region must start with the
 228          * following two fields. Then follow implementation-specific data.
 229          */
 230         u32 revision_id;
 231         u32 abort;
 232
 233         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 234         u32 padding[7]; /* room for future expansion */
 235
 236         u64 io_bitmap_a;
 237         u64 io_bitmap_b;
 238         u64 msr_bitmap;
 239         u64 vm_exit_msr_store_addr;
 240         u64 vm_exit_msr_load_addr;
 241         u64 vm_entry_msr_load_addr;
 242         u64 tsc_offset;
 243         u64 virtual_apic_page_addr;
 244         u64 apic_access_addr;
 245         u64 posted_intr_desc_addr;
 246         u64 vm_function_control;
 247         u64 ept_pointer;
 248         u64 eoi_exit_bitmap0;
 249         u64 eoi_exit_bitmap1;
 250         u64 eoi_exit_bitmap2;
 251         u64 eoi_exit_bitmap3;
 252         u64 eptp_list_address;
 253         u64 xss_exit_bitmap;
 254         u64 guest_physical_address;
 255         u64 vmcs_link_pointer;
 256         u64 pml_address;
 257         u64 guest_ia32_debugctl;
 258         u64 guest_ia32_pat;
 259         u64 guest_ia32_efer;
 260         u64 guest_ia32_perf_global_ctrl;
 261         u64 guest_pdptr0;
 262         u64 guest_pdptr1;
 263         u64 guest_pdptr2;
 264         u64 guest_pdptr3;
 265         u64 guest_bndcfgs;
 266         u64 host_ia32_pat;
 267         u64 host_ia32_efer;
 268         u64 host_ia32_perf_global_ctrl;
 269         u64 padding64[8]; /* room for future expansion */
 270         /*
 271          * To allow migration of L1 (complete with its L2 guests) between
 272          * machines of different natural widths (32 or 64 bit), we cannot have
 273          * unsigned long fields with no explict size. We use u64 (aliased
 274          * natural_width) instead. Luckily, x86 is little-endian.
 275          */
 276         natural_width cr0_guest_host_mask;
 277         natural_width cr4_guest_host_mask;
 278         natural_width cr0_read_shadow;
 279         natural_width cr4_read_shadow;
 280         natural_width cr3_target_value0;
 281         natural_width cr3_target_value1;
 282         natural_width cr3_target_value2;
 283         natural_width cr3_target_value3;
 284         natural_width exit_qualification;
 285         natural_width guest_linear_address;
 286         natural_width guest_cr0;
 287         natural_width guest_cr3;
 288         natural_width guest_cr4;
 289         natural_width guest_es_base;
 290         natural_width guest_cs_base;
 291         natural_width guest_ss_base;
 292         natural_width guest_ds_base;
 293         natural_width guest_fs_base;
 294         natural_width guest_gs_base;
 295         natural_width guest_ldtr_base;
 296         natural_width guest_tr_base;
 297         natural_width guest_gdtr_base;
 298         natural_width guest_idtr_base;
 299         natural_width guest_dr7;
 300         natural_width guest_rsp;
 301         natural_width guest_rip;
 302         natural_width guest_rflags;
 303         natural_width guest_pending_dbg_exceptions;
 304         natural_width guest_sysenter_esp;
 305         natural_width guest_sysenter_eip;
 306         natural_width host_cr0;
 307         natural_width host_cr3;
 308         natural_width host_cr4;
 309         natural_width host_fs_base;
 310         natural_width host_gs_base;
 311         natural_width host_tr_base;
 312         natural_width host_gdtr_base;
 313         natural_width host_idtr_base;
 314         natural_width host_ia32_sysenter_esp;
 315         natural_width host_ia32_sysenter_eip;
 316         natural_width host_rsp;
 317         natural_width host_rip;
 318         natural_width paddingl[8]; /* room for future expansion */
 319         u32 pin_based_vm_exec_control;
 320         u32 cpu_based_vm_exec_control;
 321         u32 exception_bitmap;
 322         u32 page_fault_error_code_mask;
 323         u32 page_fault_error_code_match;
 324         u32 cr3_target_count;
 325         u32 vm_exit_controls;
 326         u32 vm_exit_msr_store_count;
 327         u32 vm_exit_msr_load_count;
 328         u32 vm_entry_controls;
 329         u32 vm_entry_msr_load_count;
 330         u32 vm_entry_intr_info_field;
 331         u32 vm_entry_exception_error_code;
 332         u32 vm_entry_instruction_len;
 333         u32 tpr_threshold;
 334         u32 secondary_vm_exec_control;
 335         u32 vm_instruction_error;
 336         u32 vm_exit_reason;
 337         u32 vm_exit_intr_info;
 338         u32 vm_exit_intr_error_code;
 339         u32 idt_vectoring_info_field;
 340         u32 idt_vectoring_error_code;
 341         u32 vm_exit_instruction_len;
 342         u32 vmx_instruction_info;
 343         u32 guest_es_limit;
 344         u32 guest_cs_limit;
 345         u32 guest_ss_limit;
 346         u32 guest_ds_limit;
 347         u32 guest_fs_limit;
 348         u32 guest_gs_limit;
 349         u32 guest_ldtr_limit;
 350         u32 guest_tr_limit;
 351         u32 guest_gdtr_limit;
 352         u32 guest_idtr_limit;
 353         u32 guest_es_ar_bytes;
 354         u32 guest_cs_ar_bytes;
 355         u32 guest_ss_ar_bytes;
 356         u32 guest_ds_ar_bytes;
 357         u32 guest_fs_ar_bytes;
 358         u32 guest_gs_ar_bytes;
 359         u32 guest_ldtr_ar_bytes;
 360         u32 guest_tr_ar_bytes;
 361         u32 guest_interruptibility_info;
 362         u32 guest_activity_state;
 363         u32 guest_sysenter_cs;
 364         u32 host_ia32_sysenter_cs;
 365         u32 vmx_preemption_timer_value;
 366         u32 padding32[7]; /* room for future expansion */
 367         u16 virtual_processor_id;
 368         u16 posted_intr_nv;
 369         u16 guest_es_selector;
 370         u16 guest_cs_selector;
 371         u16 guest_ss_selector;
 372         u16 guest_ds_selector;
 373         u16 guest_fs_selector;
 374         u16 guest_gs_selector;
 375         u16 guest_ldtr_selector;
 376         u16 guest_tr_selector;
 377         u16 guest_intr_status;
 378         u16 guest_pml_index;
 379         u16 host_es_selector;
 380         u16 host_cs_selector;
 381         u16 host_ss_selector;
 382         u16 host_ds_selector;
 383         u16 host_fs_selector;
 384         u16 host_gs_selector;
 385         u16 host_tr_selector;
 386 };
 387
 388 /*
 389  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 390  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 391  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 392  */
 393 #define VMCS12_REVISION 0x11e57ed0
 394
 395 /*
 396  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 397  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 398  * current implementation, 4K are reserved to avoid future complications.
 399  */
 400 #define VMCS12_SIZE 0x1000
 401
 402 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 403 struct vmcs02_list {
 404         struct list_head list;
 405         gpa_t vmptr;
 406         struct loaded_vmcs vmcs02;
 407 };
 408
 409 /*
 410  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 411  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 412  */
 413 struct nested_vmx {
 414         /* Has the level1 guest done vmxon? */
 415         bool vmxon;
 416         gpa_t vmxon_ptr;
 417         bool pml_full;
 418
 419         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 420         gpa_t current_vmptr;
 421         /*
 422          * Cache of the guest's VMCS, existing outside of guest memory.
 423          * Loaded from guest memory during VMPTRLD. Flushed to guest
 424          * memory during VMCLEAR and VMPTRLD.
 425          */
 426         struct vmcs12 *cached_vmcs12;
 427         /*
 428          * Indicates if the shadow vmcs must be updated with the
 429          * data hold by vmcs12
 430          */
 431         bool sync_shadow_vmcs;
 432
 433         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 434         struct list_head vmcs02_pool;
 435         int vmcs02_num;
 436         bool change_vmcs01_virtual_x2apic_mode;
 437         /* L2 must run next, and mustn't decide to exit to L1. */
 438         bool nested_run_pending;
 439         /*
 440          * Guest pages referred to in vmcs02 with host-physical pointers, so
 441          * we must keep them pinned while L2 runs.
 442          */
 443         struct page *apic_access_page;
 444         struct page *virtual_apic_page;
 445         struct page *pi_desc_page;
 446         struct pi_desc *pi_desc;
 447         bool pi_pending;
 448         u16 posted_intr_nv;
 449
 450         unsigned long *msr_bitmap;
 451
 452         struct hrtimer preemption_timer;
 453         bool preemption_timer_expired;
 454
 455         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 456         u64 vmcs01_debugctl;
 457
 458         u16 vpid02;
 459         u16 last_vpid;
 460
 461         /*
 462          * We only store the "true" versions of the VMX capability MSRs. We
 463          * generate the "non-true" versions by setting the must-be-1 bits
 464          * according to the SDM.
 465          */
 466         u32 nested_vmx_procbased_ctls_low;
 467         u32 nested_vmx_procbased_ctls_high;
 468         u32 nested_vmx_secondary_ctls_low;
 469         u32 nested_vmx_secondary_ctls_high;
 470         u32 nested_vmx_pinbased_ctls_low;
 471         u32 nested_vmx_pinbased_ctls_high;
 472         u32 nested_vmx_exit_ctls_low;
 473         u32 nested_vmx_exit_ctls_high;
 474         u32 nested_vmx_entry_ctls_low;
 475         u32 nested_vmx_entry_ctls_high;
 476         u32 nested_vmx_misc_low;
 477         u32 nested_vmx_misc_high;
 478         u32 nested_vmx_ept_caps;
 479         u32 nested_vmx_vpid_caps;
 480         u64 nested_vmx_basic;
 481         u64 nested_vmx_cr0_fixed0;
 482         u64 nested_vmx_cr0_fixed1;
 483         u64 nested_vmx_cr4_fixed0;
 484         u64 nested_vmx_cr4_fixed1;
 485         u64 nested_vmx_vmcs_enum;
 486         u64 nested_vmx_vmfunc_controls;
 487 };
 488
 489 #define POSTED_INTR_ON  0
 490 #define POSTED_INTR_SN  1
 491
 492 /* Posted-Interrupt Descriptor */
 493 struct pi_desc {
 494         u32 pir[8];     /* Posted interrupt requested */
 495         union {
 496                 struct {
 497                                 /* bit 256 - Outstanding Notification */
 498                         u16     on      : 1,
 499                                 /* bit 257 - Suppress Notification */
 500                                 sn      : 1,
 501                                 /* bit 271:258 - Reserved */
 502                                 rsvd_1  : 14;
 503                                 /* bit 279:272 - Notification Vector */
 504                         u8      nv;
 505                                 /* bit 287:280 - Reserved */
 506                         u8      rsvd_2;
 507                                 /* bit 319:288 - Notification Destination */
 508                         u32     ndst;
 509                 };
 510                 u64 control;
 511         };
 512         u32 rsvd[6];
 513 } __aligned(64);
 514
 515 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 516 {
 517         return test_and_set_bit(POSTED_INTR_ON,
 518                         (unsigned long *)&pi_desc->control);
 519 }
 520
 521 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 522 {
 523         return test_and_clear_bit(POSTED_INTR_ON,
 524                         (unsigned long *)&pi_desc->control);
 525 }
 526
 527 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 528 {
 529         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 530 }
 531
 532 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 533 {
 534         return clear_bit(POSTED_INTR_SN,
 535                         (unsigned long *)&pi_desc->control);
 536 }
 537
 538 static inline void pi_set_sn(struct pi_desc *pi_desc)
 539 {
 540         return set_bit(POSTED_INTR_SN,
 541                         (unsigned long *)&pi_desc->control);
 542 }
 543
 544 static inline void pi_clear_on(struct pi_desc *pi_desc)
 545 {
 546         clear_bit(POSTED_INTR_ON,
 547                   (unsigned long *)&pi_desc->control);
 548 }
 549
 550 static inline int pi_test_on(struct pi_desc *pi_desc)
 551 {
 552         return test_bit(POSTED_INTR_ON,
 553                         (unsigned long *)&pi_desc->control);
 554 }
 555
 556 static inline int pi_test_sn(struct pi_desc *pi_desc)
 557 {
 558         return test_bit(POSTED_INTR_SN,
 559                         (unsigned long *)&pi_desc->control);
 560 }
 561
 562 struct vcpu_vmx {
 563         struct kvm_vcpu       vcpu;
 564         unsigned long         host_rsp;
 565         u8                    fail;
 566         u32                   exit_intr_info;
 567         u32                   idt_vectoring_info;
 568         ulong                 rflags;
 569         struct shared_msr_entry *guest_msrs;
 570         int                   nmsrs;
 571         int                   save_nmsrs;
 572         unsigned long         host_idt_base;
 573 #ifdef CONFIG_X86_64
 574         u64                   msr_host_kernel_gs_base;
 575         u64                   msr_guest_kernel_gs_base;
 576 #endif
 577         u32 vm_entry_controls_shadow;
 578         u32 vm_exit_controls_shadow;
 579         /*
 580          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 581          * non-nested (L1) guest, it always points to vmcs01. For a nested
 582          * guest (L2), it points to a different VMCS.
 583          */
 584         struct loaded_vmcs    vmcs01;
 585         struct loaded_vmcs   *loaded_vmcs;
 586         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 587         struct msr_autoload {
 588                 unsigned nr;
 589                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 590                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 591         } msr_autoload;
 592         struct {
 593                 int           loaded;
 594                 u16           fs_sel, gs_sel, ldt_sel;
 595 #ifdef CONFIG_X86_64
 596                 u16           ds_sel, es_sel;
 597 #endif
 598                 int           gs_ldt_reload_needed;
 599                 int           fs_reload_needed;
 600                 u64           msr_host_bndcfgs;
 601                 unsigned long vmcs_host_cr3;    /* May not match real cr3 */
 602                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 603         } host_state;
 604         struct {
 605                 int vm86_active;
 606                 ulong save_rflags;
 607                 struct kvm_segment segs[8];
 608         } rmode;
 609         struct {
 610                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 611                 struct kvm_save_segment {
 612                         u16 selector;
 613                         unsigned long base;
 614                         u32 limit;
 615                         u32 ar;
 616                 } seg[8];
 617         } segment_cache;
 618         int vpid;
 619         bool emulation_required;
 620
 621         u32 exit_reason;
 622
 623         /* Posted interrupt descriptor */
 624         struct pi_desc pi_desc;
 625
 626         /* Support for a guest hypervisor (nested VMX) */
 627         struct nested_vmx nested;
 628
 629         /* Dynamic PLE window. */
 630         int ple_window;
 631         bool ple_window_dirty;
 632
 633         /* Support for PML */
 634 #define PML_ENTITY_NUM          512
 635         struct page *pml_pg;
 636
 637         /* apic deadline value in host tsc */
 638         u64 hv_deadline_tsc;
 639
 640         u64 current_tsc_ratio;
 641
 642         bool guest_pkru_valid;
 643         u32 guest_pkru;
 644         u32 host_pkru;
 645
 646         /*
 647          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
 648          * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
 649          * in msr_ia32_feature_control_valid_bits.
 650          */
 651         u64 msr_ia32_feature_control;
 652         u64 msr_ia32_feature_control_valid_bits;
 653 };
 654
 655 enum segment_cache_field {
 656         SEG_FIELD_SEL = 0,
 657         SEG_FIELD_BASE = 1,
 658         SEG_FIELD_LIMIT = 2,
 659         SEG_FIELD_AR = 3,
 660
 661         SEG_FIELD_NR = 4
 662 };
 663
 664 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 665 {
 666         return container_of(vcpu, struct vcpu_vmx, vcpu);
 667 }
 668
 669 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 670 {
 671         return &(to_vmx(vcpu)->pi_desc);
 672 }
 673
 674 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 675 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 676 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 677                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 678
 679
 680 static unsigned long shadow_read_only_fields[] = {
 681         /*
 682          * We do NOT shadow fields that are modified when L0
 683          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 684          * VMXON...) executed by L1.
 685          * For example, VM_INSTRUCTION_ERROR is read
 686          * by L1 if a vmx instruction fails (part of the error path).
 687          * Note the code assumes this logic. If for some reason
 688          * we start shadowing these fields then we need to
 689          * force a shadow sync when L0 emulates vmx instructions
 690          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 691          * by nested_vmx_failValid)
 692          */
 693         VM_EXIT_REASON,
 694         VM_EXIT_INTR_INFO,
 695         VM_EXIT_INSTRUCTION_LEN,
 696         IDT_VECTORING_INFO_FIELD,
 697         IDT_VECTORING_ERROR_CODE,
 698         VM_EXIT_INTR_ERROR_CODE,
 699         EXIT_QUALIFICATION,
 700         GUEST_LINEAR_ADDRESS,
 701         GUEST_PHYSICAL_ADDRESS
 702 };
 703 static int max_shadow_read_only_fields =
 704         ARRAY_SIZE(shadow_read_only_fields);
 705
 706 static unsigned long shadow_read_write_fields[] = {
 707         TPR_THRESHOLD,
 708         GUEST_RIP,
 709         GUEST_RSP,
 710         GUEST_CR0,
 711         GUEST_CR3,
 712         GUEST_CR4,
 713         GUEST_INTERRUPTIBILITY_INFO,
 714         GUEST_RFLAGS,
 715         GUEST_CS_SELECTOR,
 716         GUEST_CS_AR_BYTES,
 717         GUEST_CS_LIMIT,
 718         GUEST_CS_BASE,
 719         GUEST_ES_BASE,
 720         GUEST_BNDCFGS,
 721         CR0_GUEST_HOST_MASK,
 722         CR0_READ_SHADOW,
 723         CR4_READ_SHADOW,
 724         TSC_OFFSET,
 725         EXCEPTION_BITMAP,
 726         CPU_BASED_VM_EXEC_CONTROL,
 727         VM_ENTRY_EXCEPTION_ERROR_CODE,
 728         VM_ENTRY_INTR_INFO_FIELD,
 729         VM_ENTRY_INSTRUCTION_LEN,
 730         VM_ENTRY_EXCEPTION_ERROR_CODE,
 731         HOST_FS_BASE,
 732         HOST_GS_BASE,
 733         HOST_FS_SELECTOR,
 734         HOST_GS_SELECTOR
 735 };
 736 static int max_shadow_read_write_fields =
 737         ARRAY_SIZE(shadow_read_write_fields);
 738
 739 static const unsigned short vmcs_field_to_offset_table[] = {
 740         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 741         FIELD(POSTED_INTR_NV, posted_intr_nv),
 742         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 743         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 744         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 745         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 746         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 747         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 748         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 749         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 750         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 751         FIELD(GUEST_PML_INDEX, guest_pml_index),
 752         FIELD(HOST_ES_SELECTOR, host_es_selector),
 753         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 754         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 755         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 756         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 757         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 758         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 759         FIELD64(IO_BITMAP_A, io_bitmap_a),
 760         FIELD64(IO_BITMAP_B, io_bitmap_b),
 761         FIELD64(MSR_BITMAP, msr_bitmap),
 762         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 763         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 764         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 765         FIELD64(TSC_OFFSET, tsc_offset),
 766         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 767         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 768         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 769         FIELD64(VM_FUNCTION_CONTROL, vm_function_control),
 770         FIELD64(EPT_POINTER, ept_pointer),
 771         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 772         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 773         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 774         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 775         FIELD64(EPTP_LIST_ADDRESS, eptp_list_address),
 776         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 777         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 778         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 779         FIELD64(PML_ADDRESS, pml_address),
 780         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 781         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 782         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 783         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 784         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 785         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 786         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 787         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 788         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 789         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 790         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 791         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 792         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 793         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 794         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 795         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 796         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 797         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 798         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 799         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 800         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 801         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 802         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 803         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 804         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 805         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 806         FIELD(TPR_THRESHOLD, tpr_threshold),
 807         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 808         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 809         FIELD(VM_EXIT_REASON, vm_exit_reason),
 810         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 811         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 812         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 813         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 814         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 815         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 816         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 817         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 818         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 819         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 820         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 821         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 822         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 823         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 824         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 825         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 826         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 827         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 828         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 829         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 830         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 831         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 832         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 833         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 834         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 835         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 836         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 837         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 838         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 839         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 840         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 841         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 842         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 843         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 844         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 845         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 846         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 847         FIELD(EXIT_QUALIFICATION, exit_qualification),
 848         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 849         FIELD(GUEST_CR0, guest_cr0),
 850         FIELD(GUEST_CR3, guest_cr3),
 851         FIELD(GUEST_CR4, guest_cr4),
 852         FIELD(GUEST_ES_BASE, guest_es_base),
 853         FIELD(GUEST_CS_BASE, guest_cs_base),
 854         FIELD(GUEST_SS_BASE, guest_ss_base),
 855         FIELD(GUEST_DS_BASE, guest_ds_base),
 856         FIELD(GUEST_FS_BASE, guest_fs_base),
 857         FIELD(GUEST_GS_BASE, guest_gs_base),
 858         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 859         FIELD(GUEST_TR_BASE, guest_tr_base),
 860         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 861         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 862         FIELD(GUEST_DR7, guest_dr7),
 863         FIELD(GUEST_RSP, guest_rsp),
 864         FIELD(GUEST_RIP, guest_rip),
 865         FIELD(GUEST_RFLAGS, guest_rflags),
 866         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 867         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 868         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 869         FIELD(HOST_CR0, host_cr0),
 870         FIELD(HOST_CR3, host_cr3),
 871         FIELD(HOST_CR4, host_cr4),
 872         FIELD(HOST_FS_BASE, host_fs_base),
 873         FIELD(HOST_GS_BASE, host_gs_base),
 874         FIELD(HOST_TR_BASE, host_tr_base),
 875         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 876         FIELD(HOST_IDTR_BASE, host_idtr_base),
 877         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 878         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 879         FIELD(HOST_RSP, host_rsp),
 880         FIELD(HOST_RIP, host_rip),
 881 };
 882
 883 static inline short vmcs_field_to_offset(unsigned long field)
 884 {
 885         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 886
 887         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 888             vmcs_field_to_offset_table[field] == 0)
 889                 return -ENOENT;
 890
 891         return vmcs_field_to_offset_table[field];
 892 }
 893
 894 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 895 {
 896         return to_vmx(vcpu)->nested.cached_vmcs12;
 897 }
 898
 899 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu);
 900 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 901 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
 902 static bool vmx_xsaves_supported(void);
 903 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 904 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 905                             struct kvm_segment *var, int seg);
 906 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 907                             struct kvm_segment *var, int seg);
 908 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 909 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 910 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 911 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 912 static int alloc_identity_pagetable(struct kvm *kvm);
 913 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
 914 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
 915 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
 916                                             u16 error_code);
 917
 918 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 919 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 920 /*
 921  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 922  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 923  */
 924 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 925
 926 /*
 927  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 928  * can find which vCPU should be waken up.
 929  */
 930 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 931 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 932
 933 enum {
 934         VMX_IO_BITMAP_A,
 935         VMX_IO_BITMAP_B,
 936         VMX_MSR_BITMAP_LEGACY,
 937         VMX_MSR_BITMAP_LONGMODE,
 938         VMX_MSR_BITMAP_LEGACY_X2APIC_APICV,
 939         VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV,
 940         VMX_MSR_BITMAP_LEGACY_X2APIC,
 941         VMX_MSR_BITMAP_LONGMODE_X2APIC,
 942         VMX_VMREAD_BITMAP,
 943         VMX_VMWRITE_BITMAP,
 944         VMX_BITMAP_NR
 945 };
 946
 947 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
 948
 949 #define vmx_io_bitmap_a                      (vmx_bitmap[VMX_IO_BITMAP_A])
 950 #define vmx_io_bitmap_b                      (vmx_bitmap[VMX_IO_BITMAP_B])
 951 #define vmx_msr_bitmap_legacy                (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
 952 #define vmx_msr_bitmap_longmode              (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
 953 #define vmx_msr_bitmap_legacy_x2apic_apicv   (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
 954 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
 955 #define vmx_msr_bitmap_legacy_x2apic         (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
 956 #define vmx_msr_bitmap_longmode_x2apic       (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
 957 #define vmx_vmread_bitmap                    (vmx_bitmap[VMX_VMREAD_BITMAP])
 958 #define vmx_vmwrite_bitmap                   (vmx_bitmap[VMX_VMWRITE_BITMAP])
 959
 960 static bool cpu_has_load_ia32_efer;
 961 static bool cpu_has_load_perf_global_ctrl;
 962
 963 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 964 static DEFINE_SPINLOCK(vmx_vpid_lock);
 965
 966 static struct vmcs_config {
 967         int size;
 968         int order;
 969         u32 basic_cap;
 970         u32 revision_id;
 971         u32 pin_based_exec_ctrl;
 972         u32 cpu_based_exec_ctrl;
 973         u32 cpu_based_2nd_exec_ctrl;
 974         u32 vmexit_ctrl;
 975         u32 vmentry_ctrl;
 976 } vmcs_config;
 977
 978 static struct vmx_capability {
 979         u32 ept;
 980         u32 vpid;
 981 } vmx_capability;
 982
 983 #define VMX_SEGMENT_FIELD(seg)                                  \
 984         [VCPU_SREG_##seg] = {                                   \
 985                 .selector = GUEST_##seg##_SELECTOR,             \
 986                 .base = GUEST_##seg##_BASE,                     \
 987                 .limit = GUEST_##seg##_LIMIT,                   \
 988                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 989         }
 990
 991 static const struct kvm_vmx_segment_field {
 992         unsigned selector;
 993         unsigned base;
 994         unsigned limit;
 995         unsigned ar_bytes;
 996 } kvm_vmx_segment_fields[] = {
 997         VMX_SEGMENT_FIELD(CS),
 998         VMX_SEGMENT_FIELD(DS),
 999         VMX_SEGMENT_FIELD(ES),
1000         VMX_SEGMENT_FIELD(FS),
1001         VMX_SEGMENT_FIELD(GS),
1002         VMX_SEGMENT_FIELD(SS),
1003         VMX_SEGMENT_FIELD(TR),
1004         VMX_SEGMENT_FIELD(LDTR),
1005 };
1006
1007 static u64 host_efer;
1008
1009 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1010
1011 /*
1012  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1013  * away by decrementing the array size.
1014  */
1015 static const u32 vmx_msr_index[] = {
1016 #ifdef CONFIG_X86_64
1017         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1018 #endif
1019         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1020 };
1021
1022 static inline bool is_exception_n(u32 intr_info, u8 vector)
1023 {
1024         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1025                              INTR_INFO_VALID_MASK)) ==
1026                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1027 }
1028
1029 static inline bool is_debug(u32 intr_info)
1030 {
1031         return is_exception_n(intr_info, DB_VECTOR);
1032 }
1033
1034 static inline bool is_breakpoint(u32 intr_info)
1035 {
1036         return is_exception_n(intr_info, BP_VECTOR);
1037 }
1038
1039 static inline bool is_page_fault(u32 intr_info)
1040 {
1041         return is_exception_n(intr_info, PF_VECTOR);
1042 }
1043
1044 static inline bool is_no_device(u32 intr_info)
1045 {
1046         return is_exception_n(intr_info, NM_VECTOR);
1047 }
1048
1049 static inline bool is_invalid_opcode(u32 intr_info)
1050 {
1051         return is_exception_n(intr_info, UD_VECTOR);
1052 }
1053
1054 static inline bool is_external_interrupt(u32 intr_info)
1055 {
1056         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1057                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1058 }
1059
1060 static inline bool is_machine_check(u32 intr_info)
1061 {
1062         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1063                              INTR_INFO_VALID_MASK)) ==
1064                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1065 }
1066
1067 static inline bool cpu_has_vmx_msr_bitmap(void)
1068 {
1069         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1070 }
1071
1072 static inline bool cpu_has_vmx_tpr_shadow(void)
1073 {
1074         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1075 }
1076
1077 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1078 {
1079         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1080 }
1081
1082 static inline bool cpu_has_secondary_exec_ctrls(void)
1083 {
1084         return vmcs_config.cpu_based_exec_ctrl &
1085                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1086 }
1087
1088 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1089 {
1090         return vmcs_config.cpu_based_2nd_exec_ctrl &
1091                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1092 }
1093
1094 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1095 {
1096         return vmcs_config.cpu_based_2nd_exec_ctrl &
1097                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1098 }
1099
1100 static inline bool cpu_has_vmx_apic_register_virt(void)
1101 {
1102         return vmcs_config.cpu_based_2nd_exec_ctrl &
1103                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1104 }
1105
1106 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1107 {
1108         return vmcs_config.cpu_based_2nd_exec_ctrl &
1109                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1110 }
1111
1112 /*
1113  * Comment's format: document - errata name - stepping - processor name.
1114  * Refer from
1115  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1116  */
1117 static u32 vmx_preemption_cpu_tfms[] = {
1118 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
1119 0x000206E6,
1120 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
1121 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1122 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1123 0x00020652,
1124 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1125 0x00020655,
1126 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
1127 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
1128 /*
1129  * 320767.pdf - AAP86  - B1 -
1130  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1131  */
1132 0x000106E5,
1133 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1134 0x000106A0,
1135 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1136 0x000106A1,
1137 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1138 0x000106A4,
1139  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1140  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1141  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1142 0x000106A5,
1143 };
1144
1145 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1146 {
1147         u32 eax = cpuid_eax(0x00000001), i;
1148
1149         /* Clear the reserved bits */
1150         eax &= ~(0x3U << 14 | 0xfU << 28);
1151         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1152                 if (eax == vmx_preemption_cpu_tfms[i])
1153                         return true;
1154
1155         return false;
1156 }
1157
1158 static inline bool cpu_has_vmx_preemption_timer(void)
1159 {
1160         return vmcs_config.pin_based_exec_ctrl &
1161                 PIN_BASED_VMX_PREEMPTION_TIMER;
1162 }
1163
1164 static inline bool cpu_has_vmx_posted_intr(void)
1165 {
1166         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1167                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1168 }
1169
1170 static inline bool cpu_has_vmx_apicv(void)
1171 {
1172         return cpu_has_vmx_apic_register_virt() &&
1173                 cpu_has_vmx_virtual_intr_delivery() &&
1174                 cpu_has_vmx_posted_intr();
1175 }
1176
1177 static inline bool cpu_has_vmx_flexpriority(void)
1178 {
1179         return cpu_has_vmx_tpr_shadow() &&
1180                 cpu_has_vmx_virtualize_apic_accesses();
1181 }
1182
1183 static inline bool cpu_has_vmx_ept_execute_only(void)
1184 {
1185         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1186 }
1187
1188 static inline bool cpu_has_vmx_ept_2m_page(void)
1189 {
1190         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1191 }
1192
1193 static inline bool cpu_has_vmx_ept_1g_page(void)
1194 {
1195         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1196 }
1197
1198 static inline bool cpu_has_vmx_ept_4levels(void)
1199 {
1200         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1201 }
1202
1203 static inline bool cpu_has_vmx_ept_ad_bits(void)
1204 {
1205         return vmx_capability.ept & VMX_EPT_AD_BIT;
1206 }
1207
1208 static inline bool cpu_has_vmx_invept_context(void)
1209 {
1210         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1211 }
1212
1213 static inline bool cpu_has_vmx_invept_global(void)
1214 {
1215         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1216 }
1217
1218 static inline bool cpu_has_vmx_invvpid_single(void)
1219 {
1220         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1221 }
1222
1223 static inline bool cpu_has_vmx_invvpid_global(void)
1224 {
1225         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1226 }
1227
1228 static inline bool cpu_has_vmx_invvpid(void)
1229 {
1230         return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1231 }
1232
1233 static inline bool cpu_has_vmx_ept(void)
1234 {
1235         return vmcs_config.cpu_based_2nd_exec_ctrl &
1236                 SECONDARY_EXEC_ENABLE_EPT;
1237 }
1238
1239 static inline bool cpu_has_vmx_unrestricted_guest(void)
1240 {
1241         return vmcs_config.cpu_based_2nd_exec_ctrl &
1242                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1243 }
1244
1245 static inline bool cpu_has_vmx_ple(void)
1246 {
1247         return vmcs_config.cpu_based_2nd_exec_ctrl &
1248                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1249 }
1250
1251 static inline bool cpu_has_vmx_basic_inout(void)
1252 {
1253         return  (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1254 }
1255
1256 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1257 {
1258         return flexpriority_enabled && lapic_in_kernel(vcpu);
1259 }
1260
1261 static inline bool cpu_has_vmx_vpid(void)
1262 {
1263         return vmcs_config.cpu_based_2nd_exec_ctrl &
1264                 SECONDARY_EXEC_ENABLE_VPID;
1265 }
1266
1267 static inline bool cpu_has_vmx_rdtscp(void)
1268 {
1269         return vmcs_config.cpu_based_2nd_exec_ctrl &
1270                 SECONDARY_EXEC_RDTSCP;
1271 }
1272
1273 static inline bool cpu_has_vmx_invpcid(void)
1274 {
1275         return vmcs_config.cpu_based_2nd_exec_ctrl &
1276                 SECONDARY_EXEC_ENABLE_INVPCID;
1277 }
1278
1279 static inline bool cpu_has_vmx_wbinvd_exit(void)
1280 {
1281         return vmcs_config.cpu_based_2nd_exec_ctrl &
1282                 SECONDARY_EXEC_WBINVD_EXITING;
1283 }
1284
1285 static inline bool cpu_has_vmx_shadow_vmcs(void)
1286 {
1287         u64 vmx_msr;
1288         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1289         /* check if the cpu supports writing r/o exit information fields */
1290         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1291                 return false;
1292
1293         return vmcs_config.cpu_based_2nd_exec_ctrl &
1294                 SECONDARY_EXEC_SHADOW_VMCS;
1295 }
1296
1297 static inline bool cpu_has_vmx_pml(void)
1298 {
1299         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1300 }
1301
1302 static inline bool cpu_has_vmx_tsc_scaling(void)
1303 {
1304         return vmcs_config.cpu_based_2nd_exec_ctrl &
1305                 SECONDARY_EXEC_TSC_SCALING;
1306 }
1307
1308 static inline bool cpu_has_vmx_vmfunc(void)
1309 {
1310         return vmcs_config.cpu_based_2nd_exec_ctrl &
1311                 SECONDARY_EXEC_ENABLE_VMFUNC;
1312 }
1313
1314 static inline bool report_flexpriority(void)
1315 {
1316         return flexpriority_enabled;
1317 }
1318
1319 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
1320 {
1321         return vmx_misc_cr3_count(to_vmx(vcpu)->nested.nested_vmx_misc_low);
1322 }
1323
1324 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1325 {
1326         return vmcs12->cpu_based_vm_exec_control & bit;
1327 }
1328
1329 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1330 {
1331         return (vmcs12->cpu_based_vm_exec_control &
1332                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1333                 (vmcs12->secondary_vm_exec_control & bit);
1334 }
1335
1336 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1337 {
1338         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1339 }
1340
1341 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1342 {
1343         return vmcs12->pin_based_vm_exec_control &
1344                 PIN_BASED_VMX_PREEMPTION_TIMER;
1345 }
1346
1347 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1348 {
1349         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1350 }
1351
1352 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1353 {
1354         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1355                 vmx_xsaves_supported();
1356 }
1357
1358 static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
1359 {
1360         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
1361 }
1362
1363 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1364 {
1365         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1366 }
1367
1368 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1369 {
1370         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1371 }
1372
1373 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1374 {
1375         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1376 }
1377
1378 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1379 {
1380         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1381 }
1382
1383 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1384 {
1385         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1386 }
1387
1388 static inline bool nested_cpu_has_vmfunc(struct vmcs12 *vmcs12)
1389 {
1390         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VMFUNC);
1391 }
1392
1393 static inline bool nested_cpu_has_eptp_switching(struct vmcs12 *vmcs12)
1394 {
1395         return nested_cpu_has_vmfunc(vmcs12) &&
1396                 (vmcs12->vm_function_control &
1397                  VMX_VMFUNC_EPTP_SWITCHING);
1398 }
1399
1400 static inline bool is_nmi(u32 intr_info)
1401 {
1402         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1403                 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1404 }
1405
1406 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1407                               u32 exit_intr_info,
1408                               unsigned long exit_qualification);
1409 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1410                         struct vmcs12 *vmcs12,
1411                         u32 reason, unsigned long qualification);
1412
1413 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1414 {
1415         int i;
1416
1417         for (i = 0; i < vmx->nmsrs; ++i)
1418                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1419                         return i;
1420         return -1;
1421 }
1422
1423 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1424 {
1425     struct {
1426         u64 vpid : 16;
1427         u64 rsvd : 48;
1428         u64 gva;
1429     } operand = { vpid, 0, gva };
1430
1431     asm volatile (__ex(ASM_VMX_INVVPID)
1432                   /* CF==1 or ZF==1 --> rc = -1 */
1433                   "; ja 1f ; ud2 ; 1:"
1434                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1435 }
1436
1437 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1438 {
1439         struct {
1440                 u64 eptp, gpa;
1441         } operand = {eptp, gpa};
1442
1443         asm volatile (__ex(ASM_VMX_INVEPT)
1444                         /* CF==1 or ZF==1 --> rc = -1 */
1445                         "; ja 1f ; ud2 ; 1:\n"
1446                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1447 }
1448
1449 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1450 {
1451         int i;
1452
1453         i = __find_msr_index(vmx, msr);
1454         if (i >= 0)
1455                 return &vmx->guest_msrs[i];
1456         return NULL;
1457 }
1458
1459 static void vmcs_clear(struct vmcs *vmcs)
1460 {
1461         u64 phys_addr = __pa(vmcs);
1462         u8 error;
1463
1464         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1465                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1466                       : "cc", "memory");
1467         if (error)
1468                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1469                        vmcs, phys_addr);
1470 }
1471
1472 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1473 {
1474         vmcs_clear(loaded_vmcs->vmcs);
1475         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1476                 vmcs_clear(loaded_vmcs->shadow_vmcs);
1477         loaded_vmcs->cpu = -1;
1478         loaded_vmcs->launched = 0;
1479 }
1480
1481 static void vmcs_load(struct vmcs *vmcs)
1482 {
1483         u64 phys_addr = __pa(vmcs);
1484         u8 error;
1485
1486         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1487                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1488                         : "cc", "memory");
1489         if (error)
1490                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1491                        vmcs, phys_addr);
1492 }
1493
1494 #ifdef CONFIG_KEXEC_CORE
1495 /*
1496  * This bitmap is used to indicate whether the vmclear
1497  * operation is enabled on all cpus. All disabled by
1498  * default.
1499  */
1500 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1501
1502 static inline void crash_enable_local_vmclear(int cpu)
1503 {
1504         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1505 }
1506
1507 static inline void crash_disable_local_vmclear(int cpu)
1508 {
1509         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1510 }
1511
1512 static inline int crash_local_vmclear_enabled(int cpu)
1513 {
1514         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1515 }
1516
1517 static void crash_vmclear_local_loaded_vmcss(void)
1518 {
1519         int cpu = raw_smp_processor_id();
1520         struct loaded_vmcs *v;
1521
1522         if (!crash_local_vmclear_enabled(cpu))
1523                 return;
1524
1525         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1526                             loaded_vmcss_on_cpu_link)
1527                 vmcs_clear(v->vmcs);
1528 }
1529 #else
1530 static inline void crash_enable_local_vmclear(int cpu) { }
1531 static inline void crash_disable_local_vmclear(int cpu) { }
1532 #endif /* CONFIG_KEXEC_CORE */
1533
1534 static void __loaded_vmcs_clear(void *arg)
1535 {
1536         struct loaded_vmcs *loaded_vmcs = arg;
1537         int cpu = raw_smp_processor_id();
1538
1539         if (loaded_vmcs->cpu != cpu)
1540                 return; /* vcpu migration can race with cpu offline */
1541         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1542                 per_cpu(current_vmcs, cpu) = NULL;
1543         crash_disable_local_vmclear(cpu);
1544         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1545
1546         /*
1547          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1548          * is before setting loaded_vmcs->vcpu to -1 which is done in
1549          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1550          * then adds the vmcs into percpu list before it is deleted.
1551          */
1552         smp_wmb();
1553
1554         loaded_vmcs_init(loaded_vmcs);
1555         crash_enable_local_vmclear(cpu);
1556 }
1557
1558 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1559 {
1560         int cpu = loaded_vmcs->cpu;
1561
1562         if (cpu != -1)
1563                 smp_call_function_single(cpu,
1564                          __loaded_vmcs_clear, loaded_vmcs, 1);
1565 }
1566
1567 static inline void vpid_sync_vcpu_single(int vpid)
1568 {
1569         if (vpid == 0)
1570                 return;
1571
1572         if (cpu_has_vmx_invvpid_single())
1573                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1574 }
1575
1576 static inline void vpid_sync_vcpu_global(void)
1577 {
1578         if (cpu_has_vmx_invvpid_global())
1579                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1580 }
1581
1582 static inline void vpid_sync_context(int vpid)
1583 {
1584         if (cpu_has_vmx_invvpid_single())
1585                 vpid_sync_vcpu_single(vpid);
1586         else
1587                 vpid_sync_vcpu_global();
1588 }
1589
1590 static inline void ept_sync_global(void)
1591 {
1592         if (cpu_has_vmx_invept_global())
1593                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1594 }
1595
1596 static inline void ept_sync_context(u64 eptp)
1597 {
1598         if (enable_ept) {
1599                 if (cpu_has_vmx_invept_context())
1600                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1601                 else
1602                         ept_sync_global();
1603         }
1604 }
1605
1606 static __always_inline void vmcs_check16(unsigned long field)
1607 {
1608         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1609                          "16-bit accessor invalid for 64-bit field");
1610         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1611                          "16-bit accessor invalid for 64-bit high field");
1612         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1613                          "16-bit accessor invalid for 32-bit high field");
1614         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1615                          "16-bit accessor invalid for natural width field");
1616 }
1617
1618 static __always_inline void vmcs_check32(unsigned long field)
1619 {
1620         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1621                          "32-bit accessor invalid for 16-bit field");
1622         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1623                          "32-bit accessor invalid for natural width field");
1624 }
1625
1626 static __always_inline void vmcs_check64(unsigned long field)
1627 {
1628         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1629                          "64-bit accessor invalid for 16-bit field");
1630         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1631                          "64-bit accessor invalid for 64-bit high field");
1632         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1633                          "64-bit accessor invalid for 32-bit field");
1634         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1635                          "64-bit accessor invalid for natural width field");
1636 }
1637
1638 static __always_inline void vmcs_checkl(unsigned long field)
1639 {
1640         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1641                          "Natural width accessor invalid for 16-bit field");
1642         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1643                          "Natural width accessor invalid for 64-bit field");
1644         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1645                          "Natural width accessor invalid for 64-bit high field");
1646         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1647                          "Natural width accessor invalid for 32-bit field");
1648 }
1649
1650 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1651 {
1652         unsigned long value;
1653
1654         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1655                       : "=a"(value) : "d"(field) : "cc");
1656         return value;
1657 }
1658
1659 static __always_inline u16 vmcs_read16(unsigned long field)
1660 {
1661         vmcs_check16(field);
1662         return __vmcs_readl(field);
1663 }
1664
1665 static __always_inline u32 vmcs_read32(unsigned long field)
1666 {
1667         vmcs_check32(field);
1668         return __vmcs_readl(field);
1669 }
1670
1671 static __always_inline u64 vmcs_read64(unsigned long field)
1672 {
1673         vmcs_check64(field);
1674 #ifdef CONFIG_X86_64
1675         return __vmcs_readl(field);
1676 #else
1677         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1678 #endif
1679 }
1680
1681 static __always_inline unsigned long vmcs_readl(unsigned long field)
1682 {
1683         vmcs_checkl(field);
1684         return __vmcs_readl(field);
1685 }
1686
1687 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1688 {
1689         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1690                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1691         dump_stack();
1692 }
1693
1694 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1695 {
1696         u8 error;
1697
1698         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1699                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1700         if (unlikely(error))
1701                 vmwrite_error(field, value);
1702 }
1703
1704 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1705 {
1706         vmcs_check16(field);
1707         __vmcs_writel(field, value);
1708 }
1709
1710 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1711 {
1712         vmcs_check32(field);
1713         __vmcs_writel(field, value);
1714 }
1715
1716 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1717 {
1718         vmcs_check64(field);
1719         __vmcs_writel(field, value);
1720 #ifndef CONFIG_X86_64
1721         asm volatile ("");
1722         __vmcs_writel(field+1, value >> 32);
1723 #endif
1724 }
1725
1726 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1727 {
1728         vmcs_checkl(field);
1729         __vmcs_writel(field, value);
1730 }
1731
1732 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1733 {
1734         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1735                          "vmcs_clear_bits does not support 64-bit fields");
1736         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1737 }
1738
1739 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1740 {
1741         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1742                          "vmcs_set_bits does not support 64-bit fields");
1743         __vmcs_writel(field, __vmcs_readl(field) | mask);
1744 }
1745
1746 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1747 {
1748         vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1749 }
1750
1751 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1752 {
1753         vmcs_write32(VM_ENTRY_CONTROLS, val);
1754         vmx->vm_entry_controls_shadow = val;
1755 }
1756
1757 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1758 {
1759         if (vmx->vm_entry_controls_shadow != val)
1760                 vm_entry_controls_init(vmx, val);
1761 }
1762
1763 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1764 {
1765         return vmx->vm_entry_controls_shadow;
1766 }
1767
1768
1769 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1770 {
1771         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1772 }
1773
1774 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1775 {
1776         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1777 }
1778
1779 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1780 {
1781         vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1782 }
1783
1784 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1785 {
1786         vmcs_write32(VM_EXIT_CONTROLS, val);
1787         vmx->vm_exit_controls_shadow = val;
1788 }
1789
1790 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1791 {
1792         if (vmx->vm_exit_controls_shadow != val)
1793                 vm_exit_controls_init(vmx, val);
1794 }
1795
1796 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1797 {
1798         return vmx->vm_exit_controls_shadow;
1799 }
1800
1801
1802 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1803 {
1804         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1805 }
1806
1807 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1808 {
1809         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1810 }
1811
1812 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1813 {
1814         vmx->segment_cache.bitmask = 0;
1815 }
1816
1817 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1818                                        unsigned field)
1819 {
1820         bool ret;
1821         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1822
1823         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1824                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1825                 vmx->segment_cache.bitmask = 0;
1826         }
1827         ret = vmx->segment_cache.bitmask & mask;
1828         vmx->segment_cache.bitmask |= mask;
1829         return ret;
1830 }
1831
1832 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1833 {
1834         u16 *p = &vmx->segment_cache.seg[seg].selector;
1835
1836         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1837                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1838         return *p;
1839 }
1840
1841 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1842 {
1843         ulong *p = &vmx->segment_cache.seg[seg].base;
1844
1845         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1846                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1847         return *p;
1848 }
1849
1850 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1851 {
1852         u32 *p = &vmx->segment_cache.seg[seg].limit;
1853
1854         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1855                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1856         return *p;
1857 }
1858
1859 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1860 {
1861         u32 *p = &vmx->segment_cache.seg[seg].ar;
1862
1863         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1864                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1865         return *p;
1866 }
1867
1868 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1869 {
1870         u32 eb;
1871
1872         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1873              (1u << DB_VECTOR) | (1u << AC_VECTOR);
1874         if ((vcpu->guest_debug &
1875              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1876             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1877                 eb |= 1u << BP_VECTOR;
1878         if (to_vmx(vcpu)->rmode.vm86_active)
1879                 eb = ~0;
1880         if (enable_ept)
1881                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1882
1883         /* When we are running a nested L2 guest and L1 specified for it a
1884          * certain exception bitmap, we must trap the same exceptions and pass
1885          * them to L1. When running L2, we will only handle the exceptions
1886          * specified above if L1 did not want them.
1887          */
1888         if (is_guest_mode(vcpu))
1889                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1890
1891         vmcs_write32(EXCEPTION_BITMAP, eb);
1892 }
1893
1894 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1895                 unsigned long entry, unsigned long exit)
1896 {
1897         vm_entry_controls_clearbit(vmx, entry);
1898         vm_exit_controls_clearbit(vmx, exit);
1899 }
1900
1901 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1902 {
1903         unsigned i;
1904         struct msr_autoload *m = &vmx->msr_autoload;
1905
1906         switch (msr) {
1907         case MSR_EFER:
1908                 if (cpu_has_load_ia32_efer) {
1909                         clear_atomic_switch_msr_special(vmx,
1910                                         VM_ENTRY_LOAD_IA32_EFER,
1911                                         VM_EXIT_LOAD_IA32_EFER);
1912                         return;
1913                 }
1914                 break;
1915         case MSR_CORE_PERF_GLOBAL_CTRL:
1916                 if (cpu_has_load_perf_global_ctrl) {
1917                         clear_atomic_switch_msr_special(vmx,
1918                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1919                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1920                         return;
1921                 }
1922                 break;
1923         }
1924
1925         for (i = 0; i < m->nr; ++i)
1926                 if (m->guest[i].index == msr)
1927                         break;
1928
1929         if (i == m->nr)
1930                 return;
1931         --m->nr;
1932         m->guest[i] = m->guest[m->nr];
1933         m->host[i] = m->host[m->nr];
1934         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1935         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1936 }
1937
1938 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1939                 unsigned long entry, unsigned long exit,
1940                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1941                 u64 guest_val, u64 host_val)
1942 {
1943         vmcs_write64(guest_val_vmcs, guest_val);
1944         vmcs_write64(host_val_vmcs, host_val);
1945         vm_entry_controls_setbit(vmx, entry);
1946         vm_exit_controls_setbit(vmx, exit);
1947 }
1948
1949 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1950                                   u64 guest_val, u64 host_val)
1951 {
1952         unsigned i;
1953         struct msr_autoload *m = &vmx->msr_autoload;
1954
1955         switch (msr) {
1956         case MSR_EFER:
1957                 if (cpu_has_load_ia32_efer) {
1958                         add_atomic_switch_msr_special(vmx,
1959                                         VM_ENTRY_LOAD_IA32_EFER,
1960                                         VM_EXIT_LOAD_IA32_EFER,
1961                                         GUEST_IA32_EFER,
1962                                         HOST_IA32_EFER,
1963                                         guest_val, host_val);
1964                         return;
1965                 }
1966                 break;
1967         case MSR_CORE_PERF_GLOBAL_CTRL:
1968                 if (cpu_has_load_perf_global_ctrl) {
1969                         add_atomic_switch_msr_special(vmx,
1970                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1971                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1972                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1973                                         HOST_IA32_PERF_GLOBAL_CTRL,
1974                                         guest_val, host_val);
1975                         return;
1976                 }
1977                 break;
1978         case MSR_IA32_PEBS_ENABLE:
1979                 /* PEBS needs a quiescent period after being disabled (to write
1980                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
1981                  * provide that period, so a CPU could write host's record into
1982                  * guest's memory.
1983                  */
1984                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1985         }
1986
1987         for (i = 0; i < m->nr; ++i)
1988                 if (m->guest[i].index == msr)
1989                         break;
1990
1991         if (i == NR_AUTOLOAD_MSRS) {
1992                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1993                                 "Can't add msr %x\n", msr);
1994                 return;
1995         } else if (i == m->nr) {
1996                 ++m->nr;
1997                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1998                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1999         }
2000
2001         m->guest[i].index = msr;
2002         m->guest[i].value = guest_val;
2003         m->host[i].index = msr;
2004         m->host[i].value = host_val;
2005 }
2006
2007 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2008 {
2009         u64 guest_efer = vmx->vcpu.arch.efer;
2010         u64 ignore_bits = 0;
2011
2012         if (!enable_ept) {
2013                 /*
2014                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
2015                  * host CPUID is more efficient than testing guest CPUID
2016                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
2017                  */
2018                 if (boot_cpu_has(X86_FEATURE_SMEP))
2019                         guest_efer |= EFER_NX;
2020                 else if (!(guest_efer & EFER_NX))
2021                         ignore_bits |= EFER_NX;
2022         }
2023
2024         /*
2025          * LMA and LME handled by hardware; SCE meaningless outside long mode.
2026          */
2027         ignore_bits |= EFER_SCE;
2028 #ifdef CONFIG_X86_64
2029         ignore_bits |= EFER_LMA | EFER_LME;
2030         /* SCE is meaningful only in long mode on Intel */
2031         if (guest_efer & EFER_LMA)
2032                 ignore_bits &= ~(u64)EFER_SCE;
2033 #endif
2034
2035         clear_atomic_switch_msr(vmx, MSR_EFER);
2036
2037         /*
2038          * On EPT, we can't emulate NX, so we must switch EFER atomically.
2039          * On CPUs that support "load IA32_EFER", always switch EFER
2040          * atomically, since it's faster than switching it manually.
2041          */
2042         if (cpu_has_load_ia32_efer ||
2043             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2044                 if (!(guest_efer & EFER_LMA))
2045                         guest_efer &= ~EFER_LME;
2046                 if (guest_efer != host_efer)
2047                         add_atomic_switch_msr(vmx, MSR_EFER,
2048                                               guest_efer, host_efer);
2049                 return false;
2050         } else {
2051                 guest_efer &= ~ignore_bits;
2052                 guest_efer |= host_efer & ignore_bits;
2053
2054                 vmx->guest_msrs[efer_offset].data = guest_efer;
2055                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2056
2057                 return true;
2058         }
2059 }
2060
2061 #ifdef CONFIG_X86_32
2062 /*
2063  * On 32-bit kernels, VM exits still load the FS and GS bases from the
2064  * VMCS rather than the segment table.  KVM uses this helper to figure
2065  * out the current bases to poke them into the VMCS before entry.
2066  */
2067 static unsigned long segment_base(u16 selector)
2068 {
2069         struct desc_struct *table;
2070         unsigned long v;
2071
2072         if (!(selector & ~SEGMENT_RPL_MASK))
2073                 return 0;
2074
2075         table = get_current_gdt_ro();
2076
2077         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2078                 u16 ldt_selector = kvm_read_ldt();
2079
2080                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2081                         return 0;
2082
2083                 table = (struct desc_struct *)segment_base(ldt_selector);
2084         }
2085         v = get_desc_base(&table[selector >> 3]);
2086         return v;
2087 }
2088 #endif
2089
2090 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2091 {
2092         struct vcpu_vmx *vmx = to_vmx(vcpu);
2093         int i;
2094
2095         if (vmx->host_state.loaded)
2096                 return;
2097
2098         vmx->host_state.loaded = 1;
2099         /*
2100          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
2101          * allow segment selectors with cpl > 0 or ti == 1.
2102          */
2103         vmx->host_state.ldt_sel = kvm_read_ldt();
2104         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2105         savesegment(fs, vmx->host_state.fs_sel);
2106         if (!(vmx->host_state.fs_sel & 7)) {
2107                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2108                 vmx->host_state.fs_reload_needed = 0;
2109         } else {
2110                 vmcs_write16(HOST_FS_SELECTOR, 0);
2111                 vmx->host_state.fs_reload_needed = 1;
2112         }
2113         savesegment(gs, vmx->host_state.gs_sel);
2114         if (!(vmx->host_state.gs_sel & 7))
2115                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2116         else {
2117                 vmcs_write16(HOST_GS_SELECTOR, 0);
2118                 vmx->host_state.gs_ldt_reload_needed = 1;
2119         }
2120
2121 #ifdef CONFIG_X86_64
2122         savesegment(ds, vmx->host_state.ds_sel);
2123         savesegment(es, vmx->host_state.es_sel);
2124 #endif
2125
2126 #ifdef CONFIG_X86_64
2127         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2128         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2129 #else
2130         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2131         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2132 #endif
2133
2134 #ifdef CONFIG_X86_64
2135         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2136         if (is_long_mode(&vmx->vcpu))
2137                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2138 #endif
2139         if (boot_cpu_has(X86_FEATURE_MPX))
2140                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2141         for (i = 0; i < vmx->save_nmsrs; ++i)
2142                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2143                                    vmx->guest_msrs[i].data,
2144                                    vmx->guest_msrs[i].mask);
2145 }
2146
2147 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2148 {
2149         if (!vmx->host_state.loaded)
2150                 return;
2151
2152         ++vmx->vcpu.stat.host_state_reload;
2153         vmx->host_state.loaded = 0;
2154 #ifdef CONFIG_X86_64
2155         if (is_long_mode(&vmx->vcpu))
2156                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2157 #endif
2158         if (vmx->host_state.gs_ldt_reload_needed) {
2159                 kvm_load_ldt(vmx->host_state.ldt_sel);
2160 #ifdef CONFIG_X86_64
2161                 load_gs_index(vmx->host_state.gs_sel);
2162 #else
2163                 loadsegment(gs, vmx->host_state.gs_sel);
2164 #endif
2165         }
2166         if (vmx->host_state.fs_reload_needed)
2167                 loadsegment(fs, vmx->host_state.fs_sel);
2168 #ifdef CONFIG_X86_64
2169         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2170                 loadsegment(ds, vmx->host_state.ds_sel);
2171                 loadsegment(es, vmx->host_state.es_sel);
2172         }
2173 #endif
2174         invalidate_tss_limit();
2175 #ifdef CONFIG_X86_64
2176         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2177 #endif
2178         if (vmx->host_state.msr_host_bndcfgs)
2179                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2180         load_fixmap_gdt(raw_smp_processor_id());
2181 }
2182
2183 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2184 {
2185         preempt_disable();
2186         __vmx_load_host_state(vmx);
2187         preempt_enable();
2188 }
2189
2190 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2191 {
2192         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2193         struct pi_desc old, new;
2194         unsigned int dest;
2195
2196         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2197                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2198                 !kvm_vcpu_apicv_active(vcpu))
2199                 return;
2200
2201         do {
2202                 old.control = new.control = pi_desc->control;
2203
2204                 /*
2205                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2206                  * are two possible cases:
2207                  * 1. After running 'pre_block', context switch
2208                  *    happened. For this case, 'sn' was set in
2209                  *    vmx_vcpu_put(), so we need to clear it here.
2210                  * 2. After running 'pre_block', we were blocked,
2211                  *    and woken up by some other guy. For this case,
2212                  *    we don't need to do anything, 'pi_post_block'
2213                  *    will do everything for us. However, we cannot
2214                  *    check whether it is case #1 or case #2 here
2215                  *    (maybe, not needed), so we also clear sn here,
2216                  *    I think it is not a big deal.
2217                  */
2218                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2219                         if (vcpu->cpu != cpu) {
2220                                 dest = cpu_physical_id(cpu);
2221
2222                                 if (x2apic_enabled())
2223                                         new.ndst = dest;
2224                                 else
2225                                         new.ndst = (dest << 8) & 0xFF00;
2226                         }
2227
2228                         /* set 'NV' to 'notification vector' */
2229                         new.nv = POSTED_INTR_VECTOR;
2230                 }
2231
2232                 /* Allow posting non-urgent interrupts */
2233                 new.sn = 0;
2234         } while (cmpxchg(&pi_desc->control, old.control,
2235                         new.control) != old.control);
2236 }
2237
2238 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2239 {
2240         vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2241         vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2242 }
2243
2244 /*
2245  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2246  * vcpu mutex is already taken.
2247  */
2248 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2249 {
2250         struct vcpu_vmx *vmx = to_vmx(vcpu);
2251         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2252
2253         if (!already_loaded) {
2254                 loaded_vmcs_clear(vmx->loaded_vmcs);
2255                 local_irq_disable();
2256                 crash_disable_local_vmclear(cpu);
2257
2258                 /*
2259                  * Read loaded_vmcs->cpu should be before fetching
2260                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2261                  * See the comments in __loaded_vmcs_clear().
2262                  */
2263                 smp_rmb();
2264
2265                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2266                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2267                 crash_enable_local_vmclear(cpu);
2268                 local_irq_enable();
2269         }
2270
2271         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2272                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2273                 vmcs_load(vmx->loaded_vmcs->vmcs);
2274         }
2275
2276         if (!already_loaded) {
2277                 void *gdt = get_current_gdt_ro();
2278                 unsigned long sysenter_esp;
2279
2280                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2281
2282                 /*
2283                  * Linux uses per-cpu TSS and GDT, so set these when switching
2284                  * processors.  See 22.2.4.
2285                  */
2286                 vmcs_writel(HOST_TR_BASE,
2287                             (unsigned long)this_cpu_ptr(&cpu_tss));
2288                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
2289
2290                 /*
2291                  * VM exits change the host TR limit to 0x67 after a VM
2292                  * exit.  This is okay, since 0x67 covers everything except
2293                  * the IO bitmap and have have code to handle the IO bitmap
2294                  * being lost after a VM exit.
2295                  */
2296                 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2297
2298                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2299                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2300
2301                 vmx->loaded_vmcs->cpu = cpu;
2302         }
2303
2304         /* Setup TSC multiplier */
2305         if (kvm_has_tsc_control &&
2306             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2307                 decache_tsc_multiplier(vmx);
2308
2309         vmx_vcpu_pi_load(vcpu, cpu);
2310         vmx->host_pkru = read_pkru();
2311 }
2312
2313 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2314 {
2315         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2316
2317         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2318                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2319                 !kvm_vcpu_apicv_active(vcpu))
2320                 return;
2321
2322         /* Set SN when the vCPU is preempted */
2323         if (vcpu->preempted)
2324                 pi_set_sn(pi_desc);
2325 }
2326
2327 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2328 {
2329         vmx_vcpu_pi_put(vcpu);
2330
2331         __vmx_load_host_state(to_vmx(vcpu));
2332 }
2333
2334 static bool emulation_required(struct kvm_vcpu *vcpu)
2335 {
2336         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2337 }
2338
2339 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2340
2341 /*
2342  * Return the cr0 value that a nested guest would read. This is a combination
2343  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2344  * its hypervisor (cr0_read_shadow).
2345  */
2346 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2347 {
2348         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2349                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2350 }
2351 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2352 {
2353         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2354                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2355 }
2356
2357 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2358 {
2359         unsigned long rflags, save_rflags;
2360
2361         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2362                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2363                 rflags = vmcs_readl(GUEST_RFLAGS);
2364                 if (to_vmx(vcpu)->rmode.vm86_active) {
2365                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2366                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2367                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2368                 }
2369                 to_vmx(vcpu)->rflags = rflags;
2370         }
2371         return to_vmx(vcpu)->rflags;
2372 }
2373
2374 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2375 {
2376         unsigned long old_rflags = vmx_get_rflags(vcpu);
2377
2378         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2379         to_vmx(vcpu)->rflags = rflags;
2380         if (to_vmx(vcpu)->rmode.vm86_active) {
2381                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2382                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2383         }
2384         vmcs_writel(GUEST_RFLAGS, rflags);
2385
2386         if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
2387                 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
2388 }
2389
2390 static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2391 {
2392         return to_vmx(vcpu)->guest_pkru;
2393 }
2394
2395 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2396 {
2397         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2398         int ret = 0;
2399
2400         if (interruptibility & GUEST_INTR_STATE_STI)
2401                 ret |= KVM_X86_SHADOW_INT_STI;
2402         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2403                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2404
2405         return ret;
2406 }
2407
2408 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2409 {
2410         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2411         u32 interruptibility = interruptibility_old;
2412
2413         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2414
2415         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2416                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2417         else if (mask & KVM_X86_SHADOW_INT_STI)
2418                 interruptibility |= GUEST_INTR_STATE_STI;
2419
2420         if ((interruptibility != interruptibility_old))
2421                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2422 }
2423
2424 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2425 {
2426         unsigned long rip;
2427
2428         rip = kvm_rip_read(vcpu);
2429         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2430         kvm_rip_write(vcpu, rip);
2431
2432         /* skipping an emulated instruction also counts */
2433         vmx_set_interrupt_shadow(vcpu, 0);
2434 }
2435
2436 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu,
2437                                                unsigned long exit_qual)
2438 {
2439         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2440         unsigned int nr = vcpu->arch.exception.nr;
2441         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2442
2443         if (vcpu->arch.exception.has_error_code) {
2444                 vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code;
2445                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2446         }
2447
2448         if (kvm_exception_is_soft(nr))
2449                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2450         else
2451                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2452
2453         if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) &&
2454             vmx_get_nmi_mask(vcpu))
2455                 intr_info |= INTR_INFO_UNBLOCK_NMI;
2456
2457         nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual);
2458 }
2459
2460 /*
2461  * KVM wants to inject page-faults which it got to the guest. This function
2462  * checks whether in a nested guest, we need to inject them to L1 or L2.
2463  */
2464 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu)
2465 {
2466         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2467         unsigned int nr = vcpu->arch.exception.nr;
2468
2469         if (nr == PF_VECTOR) {
2470                 if (vcpu->arch.exception.nested_apf) {
2471                         nested_vmx_inject_exception_vmexit(vcpu,
2472                                                            vcpu->arch.apf.nested_apf_token);
2473                         return 1;
2474                 }
2475                 /*
2476                  * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
2477                  * The fix is to add the ancillary datum (CR2 or DR6) to structs
2478                  * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
2479                  * can be written only when inject_pending_event runs.  This should be
2480                  * conditional on a new capability---if the capability is disabled,
2481                  * kvm_multiple_exception would write the ancillary information to
2482                  * CR2 or DR6, for backwards ABI-compatibility.
2483                  */
2484                 if (nested_vmx_is_page_fault_vmexit(vmcs12,
2485                                                     vcpu->arch.exception.error_code)) {
2486                         nested_vmx_inject_exception_vmexit(vcpu, vcpu->arch.cr2);
2487                         return 1;
2488                 }
2489         } else {
2490                 unsigned long exit_qual = 0;
2491                 if (nr == DB_VECTOR)
2492                         exit_qual = vcpu->arch.dr6;
2493
2494                 if (vmcs12->exception_bitmap & (1u << nr)) {
2495                         nested_vmx_inject_exception_vmexit(vcpu, exit_qual);
2496                         return 1;
2497                 }
2498         }
2499
2500         return 0;
2501 }
2502
2503 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
2504 {
2505         struct vcpu_vmx *vmx = to_vmx(vcpu);
2506         unsigned nr = vcpu->arch.exception.nr;
2507         bool has_error_code = vcpu->arch.exception.has_error_code;
2508         bool reinject = vcpu->arch.exception.reinject;
2509         u32 error_code = vcpu->arch.exception.error_code;
2510         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2511
2512         if (!reinject && is_guest_mode(vcpu) &&
2513             nested_vmx_check_exception(vcpu))
2514                 return;
2515
2516         if (has_error_code) {
2517                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2518                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2519         }
2520
2521         if (vmx->rmode.vm86_active) {
2522                 int inc_eip = 0;
2523                 if (kvm_exception_is_soft(nr))
2524                         inc_eip = vcpu->arch.event_exit_inst_len;
2525                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2526                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2527                 return;
2528         }
2529
2530         if (kvm_exception_is_soft(nr)) {
2531                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2532                              vmx->vcpu.arch.event_exit_inst_len);
2533                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2534         } else
2535                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2536
2537         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2538 }
2539
2540 static bool vmx_rdtscp_supported(void)
2541 {
2542         return cpu_has_vmx_rdtscp();
2543 }
2544
2545 static bool vmx_invpcid_supported(void)
2546 {
2547         return cpu_has_vmx_invpcid() && enable_ept;
2548 }
2549
2550 /*
2551  * Swap MSR entry in host/guest MSR entry array.
2552  */
2553 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2554 {
2555         struct shared_msr_entry tmp;
2556
2557         tmp = vmx->guest_msrs[to];
2558         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2559         vmx->guest_msrs[from] = tmp;
2560 }
2561
2562 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2563 {
2564         unsigned long *msr_bitmap;
2565
2566         if (is_guest_mode(vcpu))
2567                 msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap;
2568         else if (cpu_has_secondary_exec_ctrls() &&
2569                  (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2570                   SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
2571                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) {
2572                         if (is_long_mode(vcpu))
2573                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv;
2574                         else
2575                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv;
2576                 } else {
2577                         if (is_long_mode(vcpu))
2578                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2579                         else
2580                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2581                 }
2582         } else {
2583                 if (is_long_mode(vcpu))
2584                         msr_bitmap = vmx_msr_bitmap_longmode;
2585                 else
2586                         msr_bitmap = vmx_msr_bitmap_legacy;
2587         }
2588
2589         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2590 }
2591
2592 /*
2593  * Set up the vmcs to automatically save and restore system
2594  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2595  * mode, as fiddling with msrs is very expensive.
2596  */
2597 static void setup_msrs(struct vcpu_vmx *vmx)
2598 {
2599         int save_nmsrs, index;
2600
2601         save_nmsrs = 0;
2602 #ifdef CONFIG_X86_64
2603         if (is_long_mode(&vmx->vcpu)) {
2604                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2605                 if (index >= 0)
2606                         move_msr_up(vmx, index, save_nmsrs++);
2607                 index = __find_msr_index(vmx, MSR_LSTAR);
2608                 if (index >= 0)
2609                         move_msr_up(vmx, index, save_nmsrs++);
2610                 index = __find_msr_index(vmx, MSR_CSTAR);
2611                 if (index >= 0)
2612                         move_msr_up(vmx, index, save_nmsrs++);
2613                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2614                 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
2615                         move_msr_up(vmx, index, save_nmsrs++);
2616                 /*
2617                  * MSR_STAR is only needed on long mode guests, and only
2618                  * if efer.sce is enabled.
2619                  */
2620                 index = __find_msr_index(vmx, MSR_STAR);
2621                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2622                         move_msr_up(vmx, index, save_nmsrs++);
2623         }
2624 #endif
2625         index = __find_msr_index(vmx, MSR_EFER);
2626         if (index >= 0 && update_transition_efer(vmx, index))
2627                 move_msr_up(vmx, index, save_nmsrs++);
2628
2629         vmx->save_nmsrs = save_nmsrs;
2630
2631         if (cpu_has_vmx_msr_bitmap())
2632                 vmx_set_msr_bitmap(&vmx->vcpu);
2633 }
2634
2635 /*
2636  * reads and returns guest's timestamp counter "register"
2637  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2638  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2639  */
2640 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2641 {
2642         u64 host_tsc, tsc_offset;
2643
2644         host_tsc = rdtsc();
2645         tsc_offset = vmcs_read64(TSC_OFFSET);
2646         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2647 }
2648
2649 /*
2650  * writes 'offset' into guest's timestamp counter offset register
2651  */
2652 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2653 {
2654         if (is_guest_mode(vcpu)) {
2655                 /*
2656                  * We're here if L1 chose not to trap WRMSR to TSC. According
2657                  * to the spec, this should set L1's TSC; The offset that L1
2658                  * set for L2 remains unchanged, and still needs to be added
2659                  * to the newly set TSC to get L2's TSC.
2660                  */
2661                 struct vmcs12 *vmcs12;
2662                 /* recalculate vmcs02.TSC_OFFSET: */
2663                 vmcs12 = get_vmcs12(vcpu);
2664                 vmcs_write64(TSC_OFFSET, offset +
2665                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2666                          vmcs12->tsc_offset : 0));
2667         } else {
2668                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2669                                            vmcs_read64(TSC_OFFSET), offset);
2670                 vmcs_write64(TSC_OFFSET, offset);
2671         }
2672 }
2673
2674 /*
2675  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2676  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2677  * all guests if the "nested" module option is off, and can also be disabled
2678  * for a single guest by disabling its VMX cpuid bit.
2679  */
2680 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2681 {
2682         return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
2683 }
2684
2685 /*
2686  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2687  * returned for the various VMX controls MSRs when nested VMX is enabled.
2688  * The same values should also be used to verify that vmcs12 control fields are
2689  * valid during nested entry from L1 to L2.
2690  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2691  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2692  * bit in the high half is on if the corresponding bit in the control field
2693  * may be on. See also vmx_control_verify().
2694  */
2695 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2696 {
2697         /*
2698          * Note that as a general rule, the high half of the MSRs (bits in
2699          * the control fields which may be 1) should be initialized by the
2700          * intersection of the underlying hardware's MSR (i.e., features which
2701          * can be supported) and the list of features we want to expose -
2702          * because they are known to be properly supported in our code.
2703          * Also, usually, the low half of the MSRs (bits which must be 1) can
2704          * be set to 0, meaning that L1 may turn off any of these bits. The
2705          * reason is that if one of these bits is necessary, it will appear
2706          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2707          * fields of vmcs01 and vmcs02, will turn these bits off - and
2708          * nested_vmx_exit_reflected() will not pass related exits to L1.
2709          * These rules have exceptions below.
2710          */
2711
2712         /* pin-based controls */
2713         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2714                 vmx->nested.nested_vmx_pinbased_ctls_low,
2715                 vmx->nested.nested_vmx_pinbased_ctls_high);
2716         vmx->nested.nested_vmx_pinbased_ctls_low |=
2717                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2718         vmx->nested.nested_vmx_pinbased_ctls_high &=
2719                 PIN_BASED_EXT_INTR_MASK |
2720                 PIN_BASED_NMI_EXITING |
2721                 PIN_BASED_VIRTUAL_NMIS;
2722         vmx->nested.nested_vmx_pinbased_ctls_high |=
2723                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2724                 PIN_BASED_VMX_PREEMPTION_TIMER;
2725         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2726                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2727                         PIN_BASED_POSTED_INTR;
2728
2729         /* exit controls */
2730         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2731                 vmx->nested.nested_vmx_exit_ctls_low,
2732                 vmx->nested.nested_vmx_exit_ctls_high);
2733         vmx->nested.nested_vmx_exit_ctls_low =
2734                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2735
2736         vmx->nested.nested_vmx_exit_ctls_high &=
2737 #ifdef CONFIG_X86_64
2738                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2739 #endif
2740                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2741         vmx->nested.nested_vmx_exit_ctls_high |=
2742                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2743                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2744                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2745
2746         if (kvm_mpx_supported())
2747                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2748
2749         /* We support free control of debug control saving. */
2750         vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2751
2752         /* entry controls */
2753         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2754                 vmx->nested.nested_vmx_entry_ctls_low,
2755                 vmx->nested.nested_vmx_entry_ctls_high);
2756         vmx->nested.nested_vmx_entry_ctls_low =
2757                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2758         vmx->nested.nested_vmx_entry_ctls_high &=
2759 #ifdef CONFIG_X86_64
2760                 VM_ENTRY_IA32E_MODE |
2761 #endif
2762                 VM_ENTRY_LOAD_IA32_PAT;
2763         vmx->nested.nested_vmx_entry_ctls_high |=
2764                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2765         if (kvm_mpx_supported())
2766                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2767
2768         /* We support free control of debug control loading. */
2769         vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2770
2771         /* cpu-based controls */
2772         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2773                 vmx->nested.nested_vmx_procbased_ctls_low,
2774                 vmx->nested.nested_vmx_procbased_ctls_high);
2775         vmx->nested.nested_vmx_procbased_ctls_low =
2776                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2777         vmx->nested.nested_vmx_procbased_ctls_high &=
2778                 CPU_BASED_VIRTUAL_INTR_PENDING |
2779                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2780                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2781                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2782                 CPU_BASED_CR3_STORE_EXITING |
2783 #ifdef CONFIG_X86_64
2784                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2785 #endif
2786                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2787                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2788                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2789                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2790                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2791         /*
2792          * We can allow some features even when not supported by the
2793          * hardware. For example, L1 can specify an MSR bitmap - and we
2794          * can use it to avoid exits to L1 - even when L0 runs L2
2795          * without MSR bitmaps.
2796          */
2797         vmx->nested.nested_vmx_procbased_ctls_high |=
2798                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2799                 CPU_BASED_USE_MSR_BITMAPS;
2800
2801         /* We support free control of CR3 access interception. */
2802         vmx->nested.nested_vmx_procbased_ctls_low &=
2803                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2804
2805         /* secondary cpu-based controls */
2806         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2807                 vmx->nested.nested_vmx_secondary_ctls_low,
2808                 vmx->nested.nested_vmx_secondary_ctls_high);
2809         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2810         vmx->nested.nested_vmx_secondary_ctls_high &=
2811                 SECONDARY_EXEC_RDRAND | SECONDARY_EXEC_RDSEED |
2812                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2813                 SECONDARY_EXEC_RDTSCP |
2814                 SECONDARY_EXEC_DESC |
2815                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2816                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2817                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2818                 SECONDARY_EXEC_WBINVD_EXITING |
2819                 SECONDARY_EXEC_XSAVES;
2820
2821         if (enable_ept) {
2822                 /* nested EPT: emulate EPT also to L1 */
2823                 vmx->nested.nested_vmx_secondary_ctls_high |=
2824                         SECONDARY_EXEC_ENABLE_EPT;
2825                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2826                          VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
2827                 if (cpu_has_vmx_ept_execute_only())
2828                         vmx->nested.nested_vmx_ept_caps |=
2829                                 VMX_EPT_EXECUTE_ONLY_BIT;
2830                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2831                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2832                         VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
2833                         VMX_EPT_1GB_PAGE_BIT;
2834                 if (enable_ept_ad_bits) {
2835                         vmx->nested.nested_vmx_secondary_ctls_high |=
2836                                 SECONDARY_EXEC_ENABLE_PML;
2837                         vmx->nested.nested_vmx_ept_caps |= VMX_EPT_AD_BIT;
2838                 }
2839         } else
2840                 vmx->nested.nested_vmx_ept_caps = 0;
2841
2842         if (cpu_has_vmx_vmfunc()) {
2843                 vmx->nested.nested_vmx_secondary_ctls_high |=
2844                         SECONDARY_EXEC_ENABLE_VMFUNC;
2845                 /*
2846                  * Advertise EPTP switching unconditionally
2847                  * since we emulate it
2848                  */
2849                 vmx->nested.nested_vmx_vmfunc_controls =
2850                         VMX_VMFUNC_EPTP_SWITCHING;
2851         }
2852
2853         /*
2854          * Old versions of KVM use the single-context version without
2855          * checking for support, so declare that it is supported even
2856          * though it is treated as global context.  The alternative is
2857          * not failing the single-context invvpid, and it is worse.
2858          */
2859         if (enable_vpid) {
2860                 vmx->nested.nested_vmx_secondary_ctls_high |=
2861                         SECONDARY_EXEC_ENABLE_VPID;
2862                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2863                         VMX_VPID_EXTENT_SUPPORTED_MASK;
2864         } else
2865                 vmx->nested.nested_vmx_vpid_caps = 0;
2866
2867         if (enable_unrestricted_guest)
2868                 vmx->nested.nested_vmx_secondary_ctls_high |=
2869                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2870
2871         /* miscellaneous data */
2872         rdmsr(MSR_IA32_VMX_MISC,
2873                 vmx->nested.nested_vmx_misc_low,
2874                 vmx->nested.nested_vmx_misc_high);
2875         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2876         vmx->nested.nested_vmx_misc_low |=
2877                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2878                 VMX_MISC_ACTIVITY_HLT;
2879         vmx->nested.nested_vmx_misc_high = 0;
2880
2881         /*
2882          * This MSR reports some information about VMX support. We
2883          * should return information about the VMX we emulate for the
2884          * guest, and the VMCS structure we give it - not about the
2885          * VMX support of the underlying hardware.
2886          */
2887         vmx->nested.nested_vmx_basic =
2888                 VMCS12_REVISION |
2889                 VMX_BASIC_TRUE_CTLS |
2890                 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2891                 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2892
2893         if (cpu_has_vmx_basic_inout())
2894                 vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT;
2895
2896         /*
2897          * These MSRs specify bits which the guest must keep fixed on
2898          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2899          * We picked the standard core2 setting.
2900          */
2901 #define VMXON_CR0_ALWAYSON     (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2902 #define VMXON_CR4_ALWAYSON     X86_CR4_VMXE
2903         vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON;
2904         vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON;
2905
2906         /* These MSRs specify bits which the guest must keep fixed off. */
2907         rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1);
2908         rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1);
2909
2910         /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2911         vmx->nested.nested_vmx_vmcs_enum = 0x2e;
2912 }
2913
2914 /*
2915  * if fixed0[i] == 1: val[i] must be 1
2916  * if fixed1[i] == 0: val[i] must be 0
2917  */
2918 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
2919 {
2920         return ((val & fixed1) | fixed0) == val;
2921 }
2922
2923 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2924 {
2925         return fixed_bits_valid(control, low, high);
2926 }
2927
2928 static inline u64 vmx_control_msr(u32 low, u32 high)
2929 {
2930         return low | ((u64)high << 32);
2931 }
2932
2933 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
2934 {
2935         superset &= mask;
2936         subset &= mask;
2937
2938         return (superset | subset) == superset;
2939 }
2940
2941 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
2942 {
2943         const u64 feature_and_reserved =
2944                 /* feature (except bit 48; see below) */
2945                 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2946                 /* reserved */
2947                 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2948         u64 vmx_basic = vmx->nested.nested_vmx_basic;
2949
2950         if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
2951                 return -EINVAL;
2952
2953         /*
2954          * KVM does not emulate a version of VMX that constrains physical
2955          * addresses of VMX structures (e.g. VMCS) to 32-bits.
2956          */
2957         if (data & BIT_ULL(48))
2958                 return -EINVAL;
2959
2960         if (vmx_basic_vmcs_revision_id(vmx_basic) !=
2961             vmx_basic_vmcs_revision_id(data))
2962                 return -EINVAL;
2963
2964         if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
2965                 return -EINVAL;
2966
2967         vmx->nested.nested_vmx_basic = data;
2968         return 0;
2969 }
2970
2971 static int
2972 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2973 {
2974         u64 supported;
2975         u32 *lowp, *highp;
2976
2977         switch (msr_index) {
2978         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2979                 lowp = &vmx->nested.nested_vmx_pinbased_ctls_low;
2980                 highp = &vmx->nested.nested_vmx_pinbased_ctls_high;
2981                 break;
2982         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2983                 lowp = &vmx->nested.nested_vmx_procbased_ctls_low;
2984                 highp = &vmx->nested.nested_vmx_procbased_ctls_high;
2985                 break;
2986         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2987                 lowp = &vmx->nested.nested_vmx_exit_ctls_low;
2988                 highp = &vmx->nested.nested_vmx_exit_ctls_high;
2989                 break;
2990         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2991                 lowp = &vmx->nested.nested_vmx_entry_ctls_low;
2992                 highp = &vmx->nested.nested_vmx_entry_ctls_high;
2993                 break;
2994         case MSR_IA32_VMX_PROCBASED_CTLS2:
2995                 lowp = &vmx->nested.nested_vmx_secondary_ctls_low;
2996                 highp = &vmx->nested.nested_vmx_secondary_ctls_high;
2997                 break;
2998         default:
2999                 BUG();
3000         }
3001
3002         supported = vmx_control_msr(*lowp, *highp);
3003
3004         /* Check must-be-1 bits are still 1. */
3005         if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
3006                 return -EINVAL;
3007
3008         /* Check must-be-0 bits are still 0. */
3009         if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
3010                 return -EINVAL;
3011
3012         *lowp = data;
3013         *highp = data >> 32;
3014         return 0;
3015 }
3016
3017 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
3018 {
3019         const u64 feature_and_reserved_bits =
3020                 /* feature */
3021                 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3022                 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3023                 /* reserved */
3024                 GENMASK_ULL(13, 9) | BIT_ULL(31);
3025         u64 vmx_misc;
3026
3027         vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low,
3028                                    vmx->nested.nested_vmx_misc_high);
3029
3030         if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
3031                 return -EINVAL;
3032
3033         if ((vmx->nested.nested_vmx_pinbased_ctls_high &
3034              PIN_BASED_VMX_PREEMPTION_TIMER) &&
3035             vmx_misc_preemption_timer_rate(data) !=
3036             vmx_misc_preemption_timer_rate(vmx_misc))
3037                 return -EINVAL;
3038
3039         if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
3040                 return -EINVAL;
3041
3042         if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
3043                 return -EINVAL;
3044
3045         if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
3046                 return -EINVAL;
3047
3048         vmx->nested.nested_vmx_misc_low = data;
3049         vmx->nested.nested_vmx_misc_high = data >> 32;
3050         return 0;
3051 }
3052
3053 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
3054 {
3055         u64 vmx_ept_vpid_cap;
3056
3057         vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps,
3058                                            vmx->nested.nested_vmx_vpid_caps);
3059
3060         /* Every bit is either reserved or a feature bit. */
3061         if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
3062                 return -EINVAL;
3063
3064         vmx->nested.nested_vmx_ept_caps = data;
3065         vmx->nested.nested_vmx_vpid_caps = data >> 32;
3066         return 0;
3067 }
3068
3069 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3070 {
3071         u64 *msr;
3072
3073         switch (msr_index) {
3074         case MSR_IA32_VMX_CR0_FIXED0:
3075                 msr = &vmx->nested.nested_vmx_cr0_fixed0;
3076                 break;
3077         case MSR_IA32_VMX_CR4_FIXED0:
3078                 msr = &vmx->nested.nested_vmx_cr4_fixed0;
3079                 break;
3080         default:
3081                 BUG();
3082         }
3083
3084         /*
3085          * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3086          * must be 1 in the restored value.
3087          */
3088         if (!is_bitwise_subset(data, *msr, -1ULL))
3089                 return -EINVAL;
3090
3091         *msr = data;
3092         return 0;
3093 }
3094
3095 /*
3096  * Called when userspace is restoring VMX MSRs.
3097  *
3098  * Returns 0 on success, non-0 otherwise.
3099  */
3100 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3101 {
3102         struct vcpu_vmx *vmx = to_vmx(vcpu);
3103
3104         switch (msr_index) {
3105         case MSR_IA32_VMX_BASIC:
3106                 return vmx_restore_vmx_basic(vmx, data);
3107         case MSR_IA32_VMX_PINBASED_CTLS:
3108         case MSR_IA32_VMX_PROCBASED_CTLS:
3109         case MSR_IA32_VMX_EXIT_CTLS:
3110         case MSR_IA32_VMX_ENTRY_CTLS:
3111                 /*
3112                  * The "non-true" VMX capability MSRs are generated from the
3113                  * "true" MSRs, so we do not support restoring them directly.
3114                  *
3115                  * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3116                  * should restore the "true" MSRs with the must-be-1 bits
3117                  * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3118                  * DEFAULT SETTINGS".
3119                  */
3120                 return -EINVAL;
3121         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3122         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3123         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3124         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3125         case MSR_IA32_VMX_PROCBASED_CTLS2:
3126                 return vmx_restore_control_msr(vmx, msr_index, data);
3127         case MSR_IA32_VMX_MISC:
3128                 return vmx_restore_vmx_misc(vmx, data);
3129         case MSR_IA32_VMX_CR0_FIXED0:
3130         case MSR_IA32_VMX_CR4_FIXED0:
3131                 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3132         case MSR_IA32_VMX_CR0_FIXED1:
3133         case MSR_IA32_VMX_CR4_FIXED1:
3134                 /*
3135                  * These MSRs are generated based on the vCPU's CPUID, so we
3136                  * do not support restoring them directly.
3137                  */
3138                 return -EINVAL;
3139         case MSR_IA32_VMX_EPT_VPID_CAP:
3140                 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3141         case MSR_IA32_VMX_VMCS_ENUM:
3142                 vmx->nested.nested_vmx_vmcs_enum = data;
3143                 return 0;
3144         default:
3145                 /*
3146                  * The rest of the VMX capability MSRs do not support restore.
3147                  */
3148                 return -EINVAL;
3149         }
3150 }
3151
3152 /* Returns 0 on success, non-0 otherwise. */
3153 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3154 {
3155         struct vcpu_vmx *vmx = to_vmx(vcpu);
3156
3157         switch (msr_index) {
3158         case MSR_IA32_VMX_BASIC:
3159                 *pdata = vmx->nested.nested_vmx_basic;
3160                 break;
3161         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3162         case MSR_IA32_VMX_PINBASED_CTLS:
3163                 *pdata = vmx_control_msr(
3164                         vmx->nested.nested_vmx_pinbased_ctls_low,
3165                         vmx->nested.nested_vmx_pinbased_ctls_high);
3166                 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3167                         *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3168                 break;
3169         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3170         case MSR_IA32_VMX_PROCBASED_CTLS:
3171                 *pdata = vmx_control_msr(
3172                         vmx->nested.nested_vmx_procbased_ctls_low,
3173                         vmx->nested.nested_vmx_procbased_ctls_high);
3174                 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3175                         *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3176                 break;
3177         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3178         case MSR_IA32_VMX_EXIT_CTLS:
3179                 *pdata = vmx_control_msr(
3180                         vmx->nested.nested_vmx_exit_ctls_low,
3181                         vmx->nested.nested_vmx_exit_ctls_high);
3182                 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3183                         *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3184                 break;
3185         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3186         case MSR_IA32_VMX_ENTRY_CTLS:
3187                 *pdata = vmx_control_msr(
3188                         vmx->nested.nested_vmx_entry_ctls_low,
3189                         vmx->nested.nested_vmx_entry_ctls_high);
3190                 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3191                         *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3192                 break;
3193         case MSR_IA32_VMX_MISC:
3194                 *pdata = vmx_control_msr(
3195                         vmx->nested.nested_vmx_misc_low,
3196                         vmx->nested.nested_vmx_misc_high);
3197                 break;
3198         case MSR_IA32_VMX_CR0_FIXED0:
3199                 *pdata = vmx->nested.nested_vmx_cr0_fixed0;
3200                 break;
3201         case MSR_IA32_VMX_CR0_FIXED1:
3202                 *pdata = vmx->nested.nested_vmx_cr0_fixed1;
3203                 break;
3204         case MSR_IA32_VMX_CR4_FIXED0:
3205                 *pdata = vmx->nested.nested_vmx_cr4_fixed0;
3206                 break;
3207         case MSR_IA32_VMX_CR4_FIXED1:
3208                 *pdata = vmx->nested.nested_vmx_cr4_fixed1;
3209                 break;
3210         case MSR_IA32_VMX_VMCS_ENUM:
3211                 *pdata = vmx->nested.nested_vmx_vmcs_enum;
3212                 break;
3213         case MSR_IA32_VMX_PROCBASED_CTLS2:
3214                 *pdata = vmx_control_msr(
3215                         vmx->nested.nested_vmx_secondary_ctls_low,
3216                         vmx->nested.nested_vmx_secondary_ctls_high);
3217                 break;
3218         case MSR_IA32_VMX_EPT_VPID_CAP:
3219                 *pdata = vmx->nested.nested_vmx_ept_caps |
3220                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
3221                 break;
3222         case MSR_IA32_VMX_VMFUNC:
3223                 *pdata = vmx->nested.nested_vmx_vmfunc_controls;
3224                 break;
3225         default:
3226                 return 1;
3227         }
3228
3229         return 0;
3230 }
3231
3232 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3233                                                  uint64_t val)
3234 {
3235         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3236
3237         return !(val & ~valid_bits);
3238 }
3239
3240 /*
3241  * Reads an msr value (of 'msr_index') into 'pdata'.
3242  * Returns 0 on success, non-0 otherwise.
3243  * Assumes vcpu_load() was already called.
3244  */
3245 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3246 {
3247         struct shared_msr_entry *msr;
3248
3249         switch (msr_info->index) {
3250 #ifdef CONFIG_X86_64
3251         case MSR_FS_BASE:
3252                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3253                 break;
3254         case MSR_GS_BASE:
3255                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3256                 break;
3257         case MSR_KERNEL_GS_BASE:
3258                 vmx_load_host_state(to_vmx(vcpu));
3259                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
3260                 break;
3261 #endif
3262         case MSR_EFER:
3263                 return kvm_get_msr_common(vcpu, msr_info);
3264         case MSR_IA32_TSC:
3265                 msr_info->data = guest_read_tsc(vcpu);
3266                 break;
3267         case MSR_IA32_SYSENTER_CS:
3268                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3269                 break;
3270         case MSR_IA32_SYSENTER_EIP:
3271                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3272                 break;
3273         case MSR_IA32_SYSENTER_ESP:
3274                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3275                 break;
3276         case MSR_IA32_BNDCFGS:
3277                 if (!kvm_mpx_supported() ||
3278                     (!msr_info->host_initiated &&
3279                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
3280                         return 1;
3281                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3282                 break;
3283         case MSR_IA32_MCG_EXT_CTL:
3284                 if (!msr_info->host_initiated &&
3285                     !(to_vmx(vcpu)->msr_ia32_feature_control &
3286                       FEATURE_CONTROL_LMCE))
3287                         return 1;
3288                 msr_info->data = vcpu->arch.mcg_ext_ctl;
3289                 break;
3290         case MSR_IA32_FEATURE_CONTROL:
3291                 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
3292                 break;
3293         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3294                 if (!nested_vmx_allowed(vcpu))
3295                         return 1;
3296                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
3297         case MSR_IA32_XSS:
3298                 if (!vmx_xsaves_supported())
3299                         return 1;
3300                 msr_info->data = vcpu->arch.ia32_xss;
3301                 break;
3302         case MSR_TSC_AUX:
3303                 if (!msr_info->host_initiated &&
3304                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
3305                         return 1;
3306                 /* Otherwise falls through */
3307         default:
3308                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3309                 if (msr) {
3310                         msr_info->data = msr->data;
3311                         break;
3312                 }
3313                 return kvm_get_msr_common(vcpu, msr_info);
3314         }
3315
3316         return 0;
3317 }
3318
3319 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3320
3321 /*
3322  * Writes msr value into into the appropriate "register".
3323  * Returns 0 on success, non-0 otherwise.
3324  * Assumes vcpu_load() was already called.
3325  */
3326 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3327 {
3328         struct vcpu_vmx *vmx = to_vmx(vcpu);
3329         struct shared_msr_entry *msr;
3330         int ret = 0;
3331         u32 msr_index = msr_info->index;
3332         u64 data = msr_info->data;
3333
3334         switch (msr_index) {
3335         case MSR_EFER:
3336                 ret = kvm_set_msr_common(vcpu, msr_info);
3337                 break;
3338 #ifdef CONFIG_X86_64
3339         case MSR_FS_BASE:
3340                 vmx_segment_cache_clear(vmx);
3341                 vmcs_writel(GUEST_FS_BASE, data);
3342                 break;
3343         case MSR_GS_BASE:
3344                 vmx_segment_cache_clear(vmx);
3345                 vmcs_writel(GUEST_GS_BASE, data);
3346                 break;
3347         case MSR_KERNEL_GS_BASE:
3348                 vmx_load_host_state(vmx);
3349                 vmx->msr_guest_kernel_gs_base = data;
3350                 break;
3351 #endif
3352         case MSR_IA32_SYSENTER_CS:
3353                 vmcs_write32(GUEST_SYSENTER_CS, data);
3354                 break;
3355         case MSR_IA32_SYSENTER_EIP:
3356                 vmcs_writel(GUEST_SYSENTER_EIP, data);
3357                 break;
3358         case MSR_IA32_SYSENTER_ESP:
3359                 vmcs_writel(GUEST_SYSENTER_ESP, data);
3360                 break;
3361         case MSR_IA32_BNDCFGS:
3362                 if (!kvm_mpx_supported() ||
3363                     (!msr_info->host_initiated &&
3364                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
3365                         return 1;
3366                 if (is_noncanonical_address(data & PAGE_MASK) ||
3367                     (data & MSR_IA32_BNDCFGS_RSVD))
3368                         return 1;
3369                 vmcs_write64(GUEST_BNDCFGS, data);
3370                 break;
3371         case MSR_IA32_TSC:
3372                 kvm_write_tsc(vcpu, msr_info);
3373                 break;
3374         case MSR_IA32_CR_PAT:
3375                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3376                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3377                                 return 1;
3378                         vmcs_write64(GUEST_IA32_PAT, data);
3379                         vcpu->arch.pat = data;
3380                         break;
3381                 }
3382                 ret = kvm_set_msr_common(vcpu, msr_info);
3383                 break;
3384         case MSR_IA32_TSC_ADJUST:
3385                 ret = kvm_set_msr_common(vcpu, msr_info);
3386                 break;
3387         case MSR_IA32_MCG_EXT_CTL:
3388                 if ((!msr_info->host_initiated &&
3389                      !(to_vmx(vcpu)->msr_ia32_feature_control &
3390                        FEATURE_CONTROL_LMCE)) ||
3391                     (data & ~MCG_EXT_CTL_LMCE_EN))
3392                         return 1;
3393                 vcpu->arch.mcg_ext_ctl = data;
3394                 break;
3395         case MSR_IA32_FEATURE_CONTROL:
3396                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3397                     (to_vmx(vcpu)->msr_ia32_feature_control &
3398                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3399                         return 1;
3400                 vmx->msr_ia32_feature_control = data;
3401                 if (msr_info->host_initiated && data == 0)
3402                         vmx_leave_nested(vcpu);
3403                 break;
3404         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3405                 if (!msr_info->host_initiated)
3406                         return 1; /* they are read-only */
3407                 if (!nested_vmx_allowed(vcpu))
3408                         return 1;
3409                 return vmx_set_vmx_msr(vcpu, msr_index, data);
3410         case MSR_IA32_XSS:
3411                 if (!vmx_xsaves_supported())
3412                         return 1;
3413                 /*
3414                  * The only supported bit as of Skylake is bit 8, but
3415                  * it is not supported on KVM.
3416                  */
3417                 if (data != 0)
3418                         return 1;
3419                 vcpu->arch.ia32_xss = data;
3420                 if (vcpu->arch.ia32_xss != host_xss)
3421                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3422                                 vcpu->arch.ia32_xss, host_xss);
3423                 else
3424                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3425                 break;
3426         case MSR_TSC_AUX:
3427                 if (!msr_info->host_initiated &&
3428                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
3429                         return 1;
3430                 /* Check reserved bit, higher 32 bits should be zero */
3431                 if ((data >> 32) != 0)
3432                         return 1;
3433                 /* Otherwise falls through */
3434         default:
3435                 msr = find_msr_entry(vmx, msr_index);
3436                 if (msr) {
3437                         u64 old_msr_data = msr->data;
3438                         msr->data = data;
3439                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3440                                 preempt_disable();
3441                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3442                                                          msr->mask);
3443                                 preempt_enable();
3444                                 if (ret)
3445                                         msr->data = old_msr_data;
3446                         }
3447                         break;
3448                 }
3449                 ret = kvm_set_msr_common(vcpu, msr_info);
3450         }
3451
3452         return ret;
3453 }
3454
3455 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3456 {
3457         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3458         switch (reg) {
3459         case VCPU_REGS_RSP:
3460                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3461                 break;
3462         case VCPU_REGS_RIP:
3463                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3464                 break;
3465         case VCPU_EXREG_PDPTR:
3466                 if (enable_ept)
3467                         ept_save_pdptrs(vcpu);
3468                 break;
3469         default:
3470                 break;
3471         }
3472 }
3473
3474 static __init int cpu_has_kvm_support(void)
3475 {
3476         return cpu_has_vmx();
3477 }
3478
3479 static __init int vmx_disabled_by_bios(void)
3480 {
3481         u64 msr;
3482
3483         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3484         if (msr & FEATURE_CONTROL_LOCKED) {
3485                 /* launched w/ TXT and VMX disabled */
3486                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3487                         && tboot_enabled())
3488                         return 1;
3489                 /* launched w/o TXT and VMX only enabled w/ TXT */
3490                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3491                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3492                         && !tboot_enabled()) {
3493                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3494                                 "activate TXT before enabling KVM\n");
3495                         return 1;
3496                 }
3497                 /* launched w/o TXT and VMX disabled */
3498                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3499                         && !tboot_enabled())
3500                         return 1;
3501         }
3502
3503         return 0;
3504 }
3505
3506 static void kvm_cpu_vmxon(u64 addr)
3507 {
3508         cr4_set_bits(X86_CR4_VMXE);
3509         intel_pt_handle_vmx(1);
3510
3511         asm volatile (ASM_VMX_VMXON_RAX
3512                         : : "a"(&addr), "m"(addr)
3513                         : "memory", "cc");
3514 }
3515
3516 static int hardware_enable(void)
3517 {
3518         int cpu = raw_smp_processor_id();
3519         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3520         u64 old, test_bits;
3521
3522         if (cr4_read_shadow() & X86_CR4_VMXE)
3523                 return -EBUSY;
3524
3525         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3526         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3527         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3528
3529         /*
3530          * Now we can enable the vmclear operation in kdump
3531          * since the loaded_vmcss_on_cpu list on this cpu
3532          * has been initialized.
3533          *
3534          * Though the cpu is not in VMX operation now, there
3535          * is no problem to enable the vmclear operation
3536          * for the loaded_vmcss_on_cpu list is empty!
3537          */
3538         crash_enable_local_vmclear(cpu);
3539
3540         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3541
3542         test_bits = FEATURE_CONTROL_LOCKED;
3543         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3544         if (tboot_enabled())
3545                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3546
3547         if ((old & test_bits) != test_bits) {
3548                 /* enable and lock */
3549                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3550         }
3551         kvm_cpu_vmxon(phys_addr);
3552         ept_sync_global();
3553
3554         return 0;
3555 }
3556
3557 static void vmclear_local_loaded_vmcss(void)
3558 {
3559         int cpu = raw_smp_processor_id();
3560         struct loaded_vmcs *v, *n;
3561
3562         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3563                                  loaded_vmcss_on_cpu_link)
3564                 __loaded_vmcs_clear(v);
3565 }
3566
3567
3568 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3569  * tricks.
3570  */
3571 static void kvm_cpu_vmxoff(void)
3572 {
3573         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3574
3575         intel_pt_handle_vmx(0);
3576         cr4_clear_bits(X86_CR4_VMXE);
3577 }
3578
3579 static void hardware_disable(void)
3580 {
3581         vmclear_local_loaded_vmcss();
3582         kvm_cpu_vmxoff();
3583 }
3584
3585 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3586                                       u32 msr, u32 *result)
3587 {
3588         u32 vmx_msr_low, vmx_msr_high;
3589         u32 ctl = ctl_min | ctl_opt;
3590
3591         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3592
3593         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3594         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3595
3596         /* Ensure minimum (required) set of control bits are supported. */
3597         if (ctl_min & ~ctl)
3598                 return -EIO;
3599
3600         *result = ctl;
3601         return 0;
3602 }
3603
3604 static __init bool allow_1_setting(u32 msr, u32 ctl)
3605 {
3606         u32 vmx_msr_low, vmx_msr_high;
3607
3608         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3609         return vmx_msr_high & ctl;
3610 }
3611
3612 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3613 {
3614         u32 vmx_msr_low, vmx_msr_high;
3615         u32 min, opt, min2, opt2;
3616         u32 _pin_based_exec_control = 0;
3617         u32 _cpu_based_exec_control = 0;
3618         u32 _cpu_based_2nd_exec_control = 0;
3619         u32 _vmexit_control = 0;
3620         u32 _vmentry_control = 0;
3621
3622         min = CPU_BASED_HLT_EXITING |
3623 #ifdef CONFIG_X86_64
3624               CPU_BASED_CR8_LOAD_EXITING |
3625               CPU_BASED_CR8_STORE_EXITING |
3626 #endif
3627               CPU_BASED_CR3_LOAD_EXITING |
3628               CPU_BASED_CR3_STORE_EXITING |
3629               CPU_BASED_USE_IO_BITMAPS |
3630               CPU_BASED_MOV_DR_EXITING |
3631               CPU_BASED_USE_TSC_OFFSETING |
3632               CPU_BASED_INVLPG_EXITING |
3633               CPU_BASED_RDPMC_EXITING;
3634
3635         if (!kvm_mwait_in_guest())
3636                 min |= CPU_BASED_MWAIT_EXITING |
3637                         CPU_BASED_MONITOR_EXITING;
3638
3639         opt = CPU_BASED_TPR_SHADOW |
3640               CPU_BASED_USE_MSR_BITMAPS |
3641               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3642         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3643                                 &_cpu_based_exec_control) < 0)
3644                 return -EIO;
3645 #ifdef CONFIG_X86_64
3646         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3647                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3648                                            ~CPU_BASED_CR8_STORE_EXITING;
3649 #endif
3650         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3651                 min2 = 0;
3652                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3653                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3654                         SECONDARY_EXEC_WBINVD_EXITING |
3655                         SECONDARY_EXEC_ENABLE_VPID |
3656                         SECONDARY_EXEC_ENABLE_EPT |
3657                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3658                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3659                         SECONDARY_EXEC_RDTSCP |
3660                         SECONDARY_EXEC_ENABLE_INVPCID |
3661                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3662                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3663                         SECONDARY_EXEC_SHADOW_VMCS |
3664                         SECONDARY_EXEC_XSAVES |
3665                         SECONDARY_EXEC_ENABLE_PML |
3666                         SECONDARY_EXEC_TSC_SCALING |
3667                         SECONDARY_EXEC_ENABLE_VMFUNC;
3668                 if (adjust_vmx_controls(min2, opt2,
3669                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3670                                         &_cpu_based_2nd_exec_control) < 0)
3671                         return -EIO;
3672         }
3673 #ifndef CONFIG_X86_64
3674         if (!(_cpu_based_2nd_exec_control &
3675                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3676                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3677 #endif
3678
3679         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3680                 _cpu_based_2nd_exec_control &= ~(
3681                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3682                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3683                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3684
3685         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3686                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3687                    enabled */
3688                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3689                                              CPU_BASED_CR3_STORE_EXITING |
3690                                              CPU_BASED_INVLPG_EXITING);
3691                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3692                       vmx_capability.ept, vmx_capability.vpid);
3693         }
3694
3695         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
3696 #ifdef CONFIG_X86_64
3697         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3698 #endif
3699         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3700                 VM_EXIT_CLEAR_BNDCFGS;
3701         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3702                                 &_vmexit_control) < 0)
3703                 return -EIO;
3704
3705         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
3706                 PIN_BASED_VIRTUAL_NMIS;
3707         opt = PIN_BASED_POSTED_INTR | PIN_BASED_VMX_PREEMPTION_TIMER;
3708         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3709                                 &_pin_based_exec_control) < 0)
3710                 return -EIO;
3711
3712         if (cpu_has_broken_vmx_preemption_timer())
3713                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3714         if (!(_cpu_based_2nd_exec_control &
3715                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
3716                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3717
3718         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3719         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3720         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3721                                 &_vmentry_control) < 0)
3722                 return -EIO;
3723
3724         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3725
3726         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3727         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3728                 return -EIO;
3729
3730 #ifdef CONFIG_X86_64
3731         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3732         if (vmx_msr_high & (1u<<16))
3733                 return -EIO;
3734 #endif
3735
3736         /* Require Write-Back (WB) memory type for VMCS accesses. */
3737         if (((vmx_msr_high >> 18) & 15) != 6)
3738                 return -EIO;
3739
3740         vmcs_conf->size = vmx_msr_high & 0x1fff;
3741         vmcs_conf->order = get_order(vmcs_conf->size);
3742         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
3743         vmcs_conf->revision_id = vmx_msr_low;
3744
3745         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3746         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3747         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3748         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3749         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3750
3751         cpu_has_load_ia32_efer =
3752                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3753                                 VM_ENTRY_LOAD_IA32_EFER)
3754                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3755                                    VM_EXIT_LOAD_IA32_EFER);
3756
3757         cpu_has_load_perf_global_ctrl =
3758                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3759                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3760                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3761                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3762
3763         /*
3764          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3765          * but due to errata below it can't be used. Workaround is to use
3766          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3767          *
3768          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3769          *
3770          * AAK155             (model 26)
3771          * AAP115             (model 30)
3772          * AAT100             (model 37)
3773          * BC86,AAY89,BD102   (model 44)
3774          * BA97               (model 46)
3775          *
3776          */
3777         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3778                 switch (boot_cpu_data.x86_model) {
3779                 case 26:
3780                 case 30:
3781                 case 37:
3782                 case 44:
3783                 case 46:
3784                         cpu_has_load_perf_global_ctrl = false;
3785                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3786                                         "does not work properly. Using workaround\n");
3787                         break;
3788                 default:
3789                         break;
3790                 }
3791         }
3792
3793         if (boot_cpu_has(X86_FEATURE_XSAVES))
3794                 rdmsrl(MSR_IA32_XSS, host_xss);
3795
3796         return 0;
3797 }
3798
3799 static struct vmcs *alloc_vmcs_cpu(int cpu)
3800 {
3801         int node = cpu_to_node(cpu);
3802         struct page *pages;
3803         struct vmcs *vmcs;
3804
3805         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3806         if (!pages)
3807                 return NULL;
3808         vmcs = page_address(pages);
3809         memset(vmcs, 0, vmcs_config.size);
3810         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3811         return vmcs;
3812 }
3813
3814 static struct vmcs *alloc_vmcs(void)
3815 {
3816         return alloc_vmcs_cpu(raw_smp_processor_id());
3817 }
3818
3819 static void free_vmcs(struct vmcs *vmcs)
3820 {
3821         free_pages((unsigned long)vmcs, vmcs_config.order);
3822 }
3823
3824 /*
3825  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3826  */
3827 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3828 {
3829         if (!loaded_vmcs->vmcs)
3830                 return;
3831         loaded_vmcs_clear(loaded_vmcs);
3832         free_vmcs(loaded_vmcs->vmcs);
3833         loaded_vmcs->vmcs = NULL;
3834         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
3835 }
3836
3837 static void free_kvm_area(void)
3838 {
3839         int cpu;
3840
3841         for_each_possible_cpu(cpu) {
3842                 free_vmcs(per_cpu(vmxarea, cpu));
3843                 per_cpu(vmxarea, cpu) = NULL;
3844         }
3845 }
3846
3847 enum vmcs_field_type {
3848         VMCS_FIELD_TYPE_U16 = 0,
3849         VMCS_FIELD_TYPE_U64 = 1,
3850         VMCS_FIELD_TYPE_U32 = 2,
3851         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
3852 };
3853
3854 static inline int vmcs_field_type(unsigned long field)
3855 {
3856         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
3857                 return VMCS_FIELD_TYPE_U32;
3858         return (field >> 13) & 0x3 ;
3859 }
3860
3861 static inline int vmcs_field_readonly(unsigned long field)
3862 {
3863         return (((field >> 10) & 0x3) == 1);
3864 }
3865
3866 static void init_vmcs_shadow_fields(void)
3867 {
3868         int i, j;
3869
3870         /* No checks for read only fields yet */
3871
3872         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3873                 switch (shadow_read_write_fields[i]) {
3874                 case GUEST_BNDCFGS:
3875                         if (!kvm_mpx_supported())
3876                                 continue;
3877                         break;
3878                 default:
3879                         break;
3880                 }
3881
3882                 if (j < i)
3883                         shadow_read_write_fields[j] =
3884                                 shadow_read_write_fields[i];
3885                 j++;
3886         }
3887         max_shadow_read_write_fields = j;
3888
3889         /* shadowed fields guest access without vmexit */
3890         for (i = 0; i < max_shadow_read_write_fields; i++) {
3891                 unsigned long field = shadow_read_write_fields[i];
3892
3893                 clear_bit(field, vmx_vmwrite_bitmap);
3894                 clear_bit(field, vmx_vmread_bitmap);
3895                 if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64) {
3896                         clear_bit(field + 1, vmx_vmwrite_bitmap);
3897                         clear_bit(field + 1, vmx_vmread_bitmap);
3898                 }
3899         }
3900         for (i = 0; i < max_shadow_read_only_fields; i++) {
3901                 unsigned long field = shadow_read_only_fields[i];
3902
3903                 clear_bit(field, vmx_vmread_bitmap);
3904                 if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64)
3905                         clear_bit(field + 1, vmx_vmread_bitmap);
3906         }
3907 }
3908
3909 static __init int alloc_kvm_area(void)
3910 {
3911         int cpu;
3912
3913         for_each_possible_cpu(cpu) {
3914                 struct vmcs *vmcs;
3915
3916                 vmcs = alloc_vmcs_cpu(cpu);
3917                 if (!vmcs) {
3918                         free_kvm_area();
3919                         return -ENOMEM;
3920                 }
3921
3922                 per_cpu(vmxarea, cpu) = vmcs;
3923         }
3924         return 0;
3925 }
3926
3927 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3928                 struct kvm_segment *save)
3929 {
3930         if (!emulate_invalid_guest_state) {
3931                 /*
3932                  * CS and SS RPL should be equal during guest entry according
3933                  * to VMX spec, but in reality it is not always so. Since vcpu
3934                  * is in the middle of the transition from real mode to
3935                  * protected mode it is safe to assume that RPL 0 is a good
3936                  * default value.
3937                  */
3938                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3939                         save->selector &= ~SEGMENT_RPL_MASK;
3940                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3941                 save->s = 1;
3942         }
3943         vmx_set_segment(vcpu, save, seg);
3944 }
3945
3946 static void enter_pmode(struct kvm_vcpu *vcpu)
3947 {
3948         unsigned long flags;
3949         struct vcpu_vmx *vmx = to_vmx(vcpu);
3950
3951         /*
3952          * Update real mode segment cache. It may be not up-to-date if sement
3953          * register was written while vcpu was in a guest mode.
3954          */
3955         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3956         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3957         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3958         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3959         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3960         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3961
3962         vmx->rmode.vm86_active = 0;
3963
3964         vmx_segment_cache_clear(vmx);
3965
3966         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3967
3968         flags = vmcs_readl(GUEST_RFLAGS);
3969         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3970         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3971         vmcs_writel(GUEST_RFLAGS, flags);
3972
3973         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3974                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3975
3976         update_exception_bitmap(vcpu);
3977
3978         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3979         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3980         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3981         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3982         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3983         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3984 }
3985
3986 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3987 {
3988         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3989         struct kvm_segment var = *save;
3990
3991         var.dpl = 0x3;
3992         if (seg == VCPU_SREG_CS)
3993                 var.type = 0x3;
3994
3995         if (!emulate_invalid_guest_state) {
3996                 var.selector = var.base >> 4;
3997                 var.base = var.base & 0xffff0;
3998                 var.limit = 0xffff;
3999                 var.g = 0;
4000                 var.db = 0;
4001                 var.present = 1;
4002                 var.s = 1;
4003                 var.l = 0;
4004                 var.unusable = 0;
4005                 var.type = 0x3;
4006                 var.avl = 0;
4007                 if (save->base & 0xf)
4008                         printk_once(KERN_WARNING "kvm: segment base is not "
4009                                         "paragraph aligned when entering "
4010                                         "protected mode (seg=%d)", seg);
4011         }
4012
4013         vmcs_write16(sf->selector, var.selector);
4014         vmcs_writel(sf->base, var.base);
4015         vmcs_write32(sf->limit, var.limit);
4016         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
4017 }
4018
4019 static void enter_rmode(struct kvm_vcpu *vcpu)
4020 {
4021         unsigned long flags;
4022         struct vcpu_vmx *vmx = to_vmx(vcpu);
4023
4024         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
4025         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4026         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4027         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4028         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
4029         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4030         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
4031
4032         vmx->rmode.vm86_active = 1;
4033
4034         /*
4035          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4036          * vcpu. Warn the user that an update is overdue.
4037          */
4038         if (!vcpu->kvm->arch.tss_addr)
4039                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
4040                              "called before entering vcpu\n");
4041
4042         vmx_segment_cache_clear(vmx);
4043
4044         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
4045         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
4046         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4047
4048         flags = vmcs_readl(GUEST_RFLAGS);
4049         vmx->rmode.save_rflags = flags;
4050
4051         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
4052
4053         vmcs_writel(GUEST_RFLAGS, flags);
4054         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
4055         update_exception_bitmap(vcpu);
4056
4057         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4058         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4059         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4060         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4061         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4062         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4063
4064         kvm_mmu_reset_context(vcpu);
4065 }
4066
4067 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
4068 {
4069         struct vcpu_vmx *vmx = to_vmx(vcpu);
4070         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
4071
4072         if (!msr)
4073                 return;
4074
4075         /*
4076          * Force kernel_gs_base reloading before EFER changes, as control
4077          * of this msr depends on is_long_mode().
4078          */
4079         vmx_load_host_state(to_vmx(vcpu));
4080         vcpu->arch.efer = efer;
4081         if (efer & EFER_LMA) {
4082                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4083                 msr->data = efer;
4084         } else {
4085                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4086
4087                 msr->data = efer & ~EFER_LME;
4088         }
4089         setup_msrs(vmx);
4090 }
4091
4092 #ifdef CONFIG_X86_64
4093
4094 static void enter_lmode(struct kvm_vcpu *vcpu)
4095 {
4096         u32 guest_tr_ar;
4097
4098         vmx_segment_cache_clear(to_vmx(vcpu));
4099
4100         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4101         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
4102                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4103                                      __func__);
4104                 vmcs_write32(GUEST_TR_AR_BYTES,
4105                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
4106                              | VMX_AR_TYPE_BUSY_64_TSS);
4107         }
4108         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
4109 }
4110
4111 static void exit_lmode(struct kvm_vcpu *vcpu)
4112 {
4113         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4114         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
4115 }
4116
4117 #endif
4118
4119 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
4120 {
4121         if (enable_ept) {
4122                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4123                         return;
4124                 ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa));
4125         } else {
4126                 vpid_sync_context(vpid);
4127         }
4128 }
4129
4130 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
4131 {
4132         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
4133 }
4134
4135 static void vmx_flush_tlb_ept_only(struct kvm_vcpu *vcpu)
4136 {
4137         if (enable_ept)
4138                 vmx_flush_tlb(vcpu);
4139 }
4140
4141 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4142 {
4143         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4144
4145         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4146         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4147 }
4148
4149 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4150 {
4151         if (enable_ept && is_paging(vcpu))
4152                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4153         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4154 }
4155
4156 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
4157 {
4158         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4159
4160         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4161         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
4162 }
4163
4164 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4165 {
4166         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4167
4168         if (!test_bit(VCPU_EXREG_PDPTR,
4169                       (unsigned long *)&vcpu->arch.regs_dirty))
4170                 return;
4171
4172         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4173                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4174                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4175                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4176                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
4177         }
4178 }
4179
4180 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4181 {
4182         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4183
4184         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4185                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4186                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4187                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4188                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
4189         }
4190
4191         __set_bit(VCPU_EXREG_PDPTR,
4192                   (unsigned long *)&vcpu->arch.regs_avail);
4193         __set_bit(VCPU_EXREG_PDPTR,
4194                   (unsigned long *)&vcpu->arch.regs_dirty);
4195 }
4196
4197 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4198 {
4199         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4200         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4201         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4202
4203         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
4204                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4205             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4206                 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4207
4208         return fixed_bits_valid(val, fixed0, fixed1);
4209 }
4210
4211 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4212 {
4213         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4214         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4215
4216         return fixed_bits_valid(val, fixed0, fixed1);
4217 }
4218
4219 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4220 {
4221         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0;
4222         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1;
4223
4224         return fixed_bits_valid(val, fixed0, fixed1);
4225 }
4226
4227 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4228 #define nested_guest_cr4_valid  nested_cr4_valid
4229 #define nested_host_cr4_valid   nested_cr4_valid
4230
4231 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
4232
4233 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4234                                         unsigned long cr0,
4235                                         struct kvm_vcpu *vcpu)
4236 {
4237         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4238                 vmx_decache_cr3(vcpu);
4239         if (!(cr0 & X86_CR0_PG)) {
4240                 /* From paging/starting to nonpaging */
4241                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4242                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
4243                              (CPU_BASED_CR3_LOAD_EXITING |
4244                               CPU_BASED_CR3_STORE_EXITING));
4245                 vcpu->arch.cr0 = cr0;
4246                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4247         } else if (!is_paging(vcpu)) {
4248                 /* From nonpaging to paging */
4249                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4250                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
4251                              ~(CPU_BASED_CR3_LOAD_EXITING |
4252                                CPU_BASED_CR3_STORE_EXITING));
4253                 vcpu->arch.cr0 = cr0;
4254                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4255         }
4256
4257         if (!(cr0 & X86_CR0_WP))
4258                 *hw_cr0 &= ~X86_CR0_WP;
4259 }
4260
4261 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4262 {
4263         struct vcpu_vmx *vmx = to_vmx(vcpu);
4264         unsigned long hw_cr0;
4265
4266         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
4267         if (enable_unrestricted_guest)
4268                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
4269         else {
4270                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
4271
4272                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4273                         enter_pmode(vcpu);
4274
4275                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4276                         enter_rmode(vcpu);
4277         }
4278
4279 #ifdef CONFIG_X86_64
4280         if (vcpu->arch.efer & EFER_LME) {
4281                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
4282                         enter_lmode(vcpu);
4283                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
4284                         exit_lmode(vcpu);
4285         }
4286 #endif
4287
4288         if (enable_ept)
4289                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4290
4291         vmcs_writel(CR0_READ_SHADOW, cr0);
4292         vmcs_writel(GUEST_CR0, hw_cr0);
4293         vcpu->arch.cr0 = cr0;
4294
4295         /* depends on vcpu->arch.cr0 to be set to a new value */
4296         vmx->emulation_required = emulation_required(vcpu);
4297 }
4298
4299 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
4300 {
4301         u64 eptp;
4302
4303         /* TODO write the value reading from MSR */
4304         eptp = VMX_EPT_DEFAULT_MT |
4305                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
4306         if (enable_ept_ad_bits &&
4307             (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
4308                 eptp |= VMX_EPT_AD_ENABLE_BIT;
4309         eptp |= (root_hpa & PAGE_MASK);
4310
4311         return eptp;
4312 }
4313
4314 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4315 {
4316         unsigned long guest_cr3;
4317         u64 eptp;
4318
4319         guest_cr3 = cr3;
4320         if (enable_ept) {
4321                 eptp = construct_eptp(vcpu, cr3);
4322                 vmcs_write64(EPT_POINTER, eptp);
4323                 if (is_paging(vcpu) || is_guest_mode(vcpu))
4324                         guest_cr3 = kvm_read_cr3(vcpu);
4325                 else
4326                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
4327                 ept_load_pdptrs(vcpu);
4328         }
4329
4330         vmx_flush_tlb(vcpu);
4331         vmcs_writel(GUEST_CR3, guest_cr3);
4332 }
4333
4334 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
4335 {
4336         /*
4337          * Pass through host's Machine Check Enable value to hw_cr4, which
4338          * is in force while we are in guest mode.  Do not let guests control
4339          * this bit, even if host CR4.MCE == 0.
4340          */
4341         unsigned long hw_cr4 =
4342                 (cr4_read_shadow() & X86_CR4_MCE) |
4343                 (cr4 & ~X86_CR4_MCE) |
4344                 (to_vmx(vcpu)->rmode.vm86_active ?
4345                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
4346
4347         if (cr4 & X86_CR4_VMXE) {
4348                 /*
4349                  * To use VMXON (and later other VMX instructions), a guest
4350                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
4351                  * So basically the check on whether to allow nested VMX
4352                  * is here.
4353                  */
4354                 if (!nested_vmx_allowed(vcpu))
4355                         return 1;
4356         }
4357
4358         if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
4359                 return 1;
4360
4361         vcpu->arch.cr4 = cr4;
4362         if (enable_ept) {
4363                 if (!is_paging(vcpu)) {
4364                         hw_cr4 &= ~X86_CR4_PAE;
4365                         hw_cr4 |= X86_CR4_PSE;
4366                 } else if (!(cr4 & X86_CR4_PAE)) {
4367                         hw_cr4 &= ~X86_CR4_PAE;
4368                 }
4369         }
4370
4371         if (!enable_unrestricted_guest && !is_paging(vcpu))
4372                 /*
4373                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4374                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
4375                  * to be manually disabled when guest switches to non-paging
4376                  * mode.
4377                  *
4378                  * If !enable_unrestricted_guest, the CPU is always running
4379                  * with CR0.PG=1 and CR4 needs to be modified.
4380                  * If enable_unrestricted_guest, the CPU automatically
4381                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4382                  */
4383                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4384
4385         vmcs_writel(CR4_READ_SHADOW, cr4);
4386         vmcs_writel(GUEST_CR4, hw_cr4);
4387         return 0;
4388 }
4389
4390 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4391                             struct kvm_segment *var, int seg)
4392 {
4393         struct vcpu_vmx *vmx = to_vmx(vcpu);
4394         u32 ar;
4395
4396         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4397                 *var = vmx->rmode.segs[seg];
4398                 if (seg == VCPU_SREG_TR
4399                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4400                         return;
4401                 var->base = vmx_read_guest_seg_base(vmx, seg);
4402                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4403                 return;
4404         }
4405         var->base = vmx_read_guest_seg_base(vmx, seg);
4406         var->limit = vmx_read_guest_seg_limit(vmx, seg);
4407         var->selector = vmx_read_guest_seg_selector(vmx, seg);
4408         ar = vmx_read_guest_seg_ar(vmx, seg);
4409         var->unusable = (ar >> 16) & 1;
4410         var->type = ar & 15;
4411         var->s = (ar >> 4) & 1;
4412         var->dpl = (ar >> 5) & 3;
4413         /*
4414          * Some userspaces do not preserve unusable property. Since usable
4415          * segment has to be present according to VMX spec we can use present
4416          * property to amend userspace bug by making unusable segment always
4417          * nonpresent. vmx_segment_access_rights() already marks nonpresent
4418          * segment as unusable.
4419          */
4420         var->present = !var->unusable;
4421         var->avl = (ar >> 12) & 1;
4422         var->l = (ar >> 13) & 1;
4423         var->db = (ar >> 14) & 1;
4424         var->g = (ar >> 15) & 1;
4425 }
4426
4427 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4428 {
4429         struct kvm_segment s;
4430
4431         if (to_vmx(vcpu)->rmode.vm86_active) {
4432                 vmx_get_segment(vcpu, &s, seg);
4433                 return s.base;
4434         }
4435         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4436 }
4437
4438 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4439 {
4440         struct vcpu_vmx *vmx = to_vmx(vcpu);
4441
4442         if (unlikely(vmx->rmode.vm86_active))
4443                 return 0;
4444         else {
4445                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4446                 return VMX_AR_DPL(ar);
4447         }
4448 }
4449
4450 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4451 {
4452         u32 ar;
4453
4454         if (var->unusable || !var->present)
4455                 ar = 1 << 16;
4456         else {
4457                 ar = var->type & 15;
4458                 ar |= (var->s & 1) << 4;
4459                 ar |= (var->dpl & 3) << 5;
4460                 ar |= (var->present & 1) << 7;
4461                 ar |= (var->avl & 1) << 12;
4462                 ar |= (var->l & 1) << 13;
4463                 ar |= (var->db & 1) << 14;
4464                 ar |= (var->g & 1) << 15;
4465         }
4466
4467         return ar;
4468 }
4469
4470 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4471                             struct kvm_segment *var, int seg)
4472 {
4473         struct vcpu_vmx *vmx = to_vmx(vcpu);
4474         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4475
4476         vmx_segment_cache_clear(vmx);
4477
4478         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4479                 vmx->rmode.segs[seg] = *var;
4480                 if (seg == VCPU_SREG_TR)
4481                         vmcs_write16(sf->selector, var->selector);
4482                 else if (var->s)
4483                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4484                 goto out;
4485         }
4486
4487         vmcs_writel(sf->base, var->base);
4488         vmcs_write32(sf->limit, var->limit);
4489         vmcs_write16(sf->selector, var->selector);
4490
4491         /*
4492          *   Fix the "Accessed" bit in AR field of segment registers for older
4493          * qemu binaries.
4494          *   IA32 arch specifies that at the time of processor reset the
4495          * "Accessed" bit in the AR field of segment registers is 1. And qemu
4496          * is setting it to 0 in the userland code. This causes invalid guest
4497          * state vmexit when "unrestricted guest" mode is turned on.
4498          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
4499          * tree. Newer qemu binaries with that qemu fix would not need this
4500          * kvm hack.
4501          */
4502         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4503                 var->type |= 0x1; /* Accessed */
4504
4505         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4506
4507 out:
4508         vmx->emulation_required = emulation_required(vcpu);
4509 }
4510
4511 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4512 {
4513         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4514
4515         *db = (ar >> 14) & 1;
4516         *l = (ar >> 13) & 1;
4517 }
4518
4519 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4520 {
4521         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4522         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4523 }
4524
4525 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4526 {
4527         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4528         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4529 }
4530
4531 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4532 {
4533         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4534         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4535 }
4536
4537 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4538 {
4539         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4540         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4541 }
4542
4543 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4544 {
4545         struct kvm_segment var;
4546         u32 ar;
4547
4548         vmx_get_segment(vcpu, &var, seg);
4549         var.dpl = 0x3;
4550         if (seg == VCPU_SREG_CS)
4551                 var.type = 0x3;
4552         ar = vmx_segment_access_rights(&var);
4553
4554         if (var.base != (var.selector << 4))
4555                 return false;
4556         if (var.limit != 0xffff)
4557                 return false;
4558         if (ar != 0xf3)
4559                 return false;
4560
4561         return true;
4562 }
4563
4564 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4565 {
4566         struct kvm_segment cs;
4567         unsigned int cs_rpl;
4568
4569         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4570         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4571
4572         if (cs.unusable)
4573                 return false;
4574         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4575                 return false;
4576         if (!cs.s)
4577                 return false;
4578         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4579                 if (cs.dpl > cs_rpl)
4580                         return false;
4581         } else {
4582                 if (cs.dpl != cs_rpl)
4583                         return false;
4584         }
4585         if (!cs.present)
4586                 return false;
4587
4588         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4589         return true;
4590 }
4591
4592 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4593 {
4594         struct kvm_segment ss;
4595         unsigned int ss_rpl;
4596
4597         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4598         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4599
4600         if (ss.unusable)
4601                 return true;
4602         if (ss.type != 3 && ss.type != 7)
4603                 return false;
4604         if (!ss.s)
4605                 return false;
4606         if (ss.dpl != ss_rpl) /* DPL != RPL */
4607                 return false;
4608         if (!ss.present)
4609                 return false;
4610
4611         return true;
4612 }
4613
4614 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4615 {
4616         struct kvm_segment var;
4617         unsigned int rpl;
4618
4619         vmx_get_segment(vcpu, &var, seg);
4620         rpl = var.selector & SEGMENT_RPL_MASK;
4621
4622         if (var.unusable)
4623                 return true;
4624         if (!var.s)
4625                 return false;
4626         if (!var.present)
4627                 return false;
4628         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4629                 if (var.dpl < rpl) /* DPL < RPL */
4630                         return false;
4631         }
4632
4633         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4634          * rights flags
4635          */
4636         return true;
4637 }
4638
4639 static bool tr_valid(struct kvm_vcpu *vcpu)
4640 {
4641         struct kvm_segment tr;
4642
4643         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4644
4645         if (tr.unusable)
4646                 return false;
4647         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4648                 return false;
4649         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4650                 return false;
4651         if (!tr.present)
4652                 return false;
4653
4654         return true;
4655 }
4656
4657 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4658 {
4659         struct kvm_segment ldtr;
4660
4661         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4662
4663         if (ldtr.unusable)
4664                 return true;
4665         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4666                 return false;
4667         if (ldtr.type != 2)
4668                 return false;
4669         if (!ldtr.present)
4670                 return false;
4671
4672         return true;
4673 }
4674
4675 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4676 {
4677         struct kvm_segment cs, ss;
4678
4679         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4680         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4681
4682         return ((cs.selector & SEGMENT_RPL_MASK) ==
4683                  (ss.selector & SEGMENT_RPL_MASK));
4684 }
4685
4686 /*
4687  * Check if guest state is valid. Returns true if valid, false if
4688  * not.
4689  * We assume that registers are always usable
4690  */
4691 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4692 {
4693         if (enable_unrestricted_guest)
4694                 return true;
4695
4696         /* real mode guest state checks */
4697         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4698                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4699                         return false;
4700                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4701                         return false;
4702                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4703                         return false;
4704                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4705                         return false;
4706                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4707                         return false;
4708                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4709                         return false;
4710         } else {
4711         /* protected mode guest state checks */
4712                 if (!cs_ss_rpl_check(vcpu))
4713                         return false;
4714                 if (!code_segment_valid(vcpu))
4715                         return false;
4716                 if (!stack_segment_valid(vcpu))
4717                         return false;
4718                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4719                         return false;
4720                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4721                         return false;
4722                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4723                         return false;
4724                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4725                         return false;
4726                 if (!tr_valid(vcpu))
4727                         return false;
4728                 if (!ldtr_valid(vcpu))
4729                         return false;
4730         }
4731         /* TODO:
4732          * - Add checks on RIP
4733          * - Add checks on RFLAGS
4734          */
4735
4736         return true;
4737 }
4738
4739 static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa)
4740 {
4741         return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu));
4742 }
4743
4744 static int init_rmode_tss(struct kvm *kvm)
4745 {
4746         gfn_t fn;
4747         u16 data = 0;
4748         int idx, r;
4749
4750         idx = srcu_read_lock(&kvm->srcu);
4751         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4752         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4753         if (r < 0)
4754                 goto out;
4755         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4756         r = kvm_write_guest_page(kvm, fn++, &data,
4757                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4758         if (r < 0)
4759                 goto out;
4760         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4761         if (r < 0)
4762                 goto out;
4763         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4764         if (r < 0)
4765                 goto out;
4766         data = ~0;
4767         r = kvm_write_guest_page(kvm, fn, &data,
4768                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4769                                  sizeof(u8));
4770 out:
4771         srcu_read_unlock(&kvm->srcu, idx);
4772         return r;
4773 }
4774
4775 static int init_rmode_identity_map(struct kvm *kvm)
4776 {
4777         int i, idx, r = 0;
4778         kvm_pfn_t identity_map_pfn;
4779         u32 tmp;
4780
4781         if (!enable_ept)
4782                 return 0;
4783
4784         /* Protect kvm->arch.ept_identity_pagetable_done. */
4785         mutex_lock(&kvm->slots_lock);
4786
4787         if (likely(kvm->arch.ept_identity_pagetable_done))
4788                 goto out2;
4789
4790         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4791
4792         r = alloc_identity_pagetable(kvm);
4793         if (r < 0)
4794                 goto out2;
4795
4796         idx = srcu_read_lock(&kvm->srcu);
4797         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4798         if (r < 0)
4799                 goto out;
4800         /* Set up identity-mapping pagetable for EPT in real mode */
4801         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4802                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4803                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4804                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4805                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4806                 if (r < 0)
4807                         goto out;
4808         }
4809         kvm->arch.ept_identity_pagetable_done = true;
4810
4811 out:
4812         srcu_read_unlock(&kvm->srcu, idx);
4813
4814 out2:
4815         mutex_unlock(&kvm->slots_lock);
4816         return r;
4817 }
4818
4819 static void seg_setup(int seg)
4820 {
4821         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4822         unsigned int ar;
4823
4824         vmcs_write16(sf->selector, 0);
4825         vmcs_writel(sf->base, 0);
4826         vmcs_write32(sf->limit, 0xffff);
4827         ar = 0x93;
4828         if (seg == VCPU_SREG_CS)
4829                 ar |= 0x08; /* code segment */
4830
4831         vmcs_write32(sf->ar_bytes, ar);
4832 }
4833
4834 static int alloc_apic_access_page(struct kvm *kvm)
4835 {
4836         struct page *page;
4837         int r = 0;
4838
4839         mutex_lock(&kvm->slots_lock);
4840         if (kvm->arch.apic_access_page_done)
4841                 goto out;
4842         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4843                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4844         if (r)
4845                 goto out;
4846
4847         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4848         if (is_error_page(page)) {
4849                 r = -EFAULT;
4850                 goto out;
4851         }
4852
4853         /*
4854          * Do not pin the page in memory, so that memory hot-unplug
4855          * is able to migrate it.
4856          */
4857         put_page(page);
4858         kvm->arch.apic_access_page_done = true;
4859 out:
4860         mutex_unlock(&kvm->slots_lock);
4861         return r;
4862 }
4863
4864 static int alloc_identity_pagetable(struct kvm *kvm)
4865 {
4866         /* Called with kvm->slots_lock held. */
4867
4868         int r = 0;
4869
4870         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4871
4872         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4873                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4874
4875         return r;
4876 }
4877
4878 static int allocate_vpid(void)
4879 {
4880         int vpid;
4881
4882         if (!enable_vpid)
4883                 return 0;
4884         spin_lock(&vmx_vpid_lock);
4885         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4886         if (vpid < VMX_NR_VPIDS)
4887                 __set_bit(vpid, vmx_vpid_bitmap);
4888         else
4889                 vpid = 0;
4890         spin_unlock(&vmx_vpid_lock);
4891         return vpid;
4892 }
4893
4894 static void free_vpid(int vpid)
4895 {
4896         if (!enable_vpid || vpid == 0)
4897                 return;
4898         spin_lock(&vmx_vpid_lock);
4899         __clear_bit(vpid, vmx_vpid_bitmap);
4900         spin_unlock(&vmx_vpid_lock);
4901 }
4902
4903 #define MSR_TYPE_R      1
4904 #define MSR_TYPE_W      2
4905 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4906                                                 u32 msr, int type)
4907 {
4908         int f = sizeof(unsigned long);
4909
4910         if (!cpu_has_vmx_msr_bitmap())
4911                 return;
4912
4913         /*
4914          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4915          * have the write-low and read-high bitmap offsets the wrong way round.
4916          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4917          */
4918         if (msr <= 0x1fff) {
4919                 if (type & MSR_TYPE_R)
4920                         /* read-low */
4921                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4922
4923                 if (type & MSR_TYPE_W)
4924                         /* write-low */
4925                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4926
4927         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4928                 msr &= 0x1fff;
4929                 if (type & MSR_TYPE_R)
4930                         /* read-high */
4931                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4932
4933                 if (type & MSR_TYPE_W)
4934                         /* write-high */
4935                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4936
4937         }
4938 }
4939
4940 /*
4941  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4942  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4943  */
4944 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4945                                                unsigned long *msr_bitmap_nested,
4946                                                u32 msr, int type)
4947 {
4948         int f = sizeof(unsigned long);
4949
4950         if (!cpu_has_vmx_msr_bitmap()) {
4951                 WARN_ON(1);
4952                 return;
4953         }
4954
4955         /*
4956          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4957          * have the write-low and read-high bitmap offsets the wrong way round.
4958          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4959          */
4960         if (msr <= 0x1fff) {
4961                 if (type & MSR_TYPE_R &&
4962                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4963                         /* read-low */
4964                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4965
4966                 if (type & MSR_TYPE_W &&
4967                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4968                         /* write-low */
4969                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4970
4971         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4972                 msr &= 0x1fff;
4973                 if (type & MSR_TYPE_R &&
4974                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4975                         /* read-high */
4976                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4977
4978                 if (type & MSR_TYPE_W &&
4979                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4980                         /* write-high */
4981                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4982
4983         }
4984 }
4985
4986 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4987 {
4988         if (!longmode_only)
4989                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4990                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4991         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4992                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4993 }
4994
4995 static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active)
4996 {
4997         if (apicv_active) {
4998                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
4999                                 msr, type);
5000                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,
5001                                 msr, type);
5002         } else {
5003                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
5004                                 msr, type);
5005                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
5006                                 msr, type);
5007         }
5008 }
5009
5010 static bool vmx_get_enable_apicv(void)
5011 {
5012         return enable_apicv;
5013 }
5014
5015 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu)
5016 {
5017         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5018         gfn_t gfn;
5019
5020         /*
5021          * Don't need to mark the APIC access page dirty; it is never
5022          * written to by the CPU during APIC virtualization.
5023          */
5024
5025         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
5026                 gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT;
5027                 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5028         }
5029
5030         if (nested_cpu_has_posted_intr(vmcs12)) {
5031                 gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT;
5032                 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5033         }
5034 }
5035
5036
5037 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
5038 {
5039         struct vcpu_vmx *vmx = to_vmx(vcpu);
5040         int max_irr;
5041         void *vapic_page;
5042         u16 status;
5043
5044         if (!vmx->nested.pi_desc || !vmx->nested.pi_pending)
5045                 return;
5046
5047         vmx->nested.pi_pending = false;
5048         if (!pi_test_and_clear_on(vmx->nested.pi_desc))
5049                 return;
5050
5051         max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256);
5052         if (max_irr != 256) {
5053                 vapic_page = kmap(vmx->nested.virtual_apic_page);
5054                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
5055                 kunmap(vmx->nested.virtual_apic_page);
5056
5057                 status = vmcs_read16(GUEST_INTR_STATUS);
5058                 if ((u8)max_irr > ((u8)status & 0xff)) {
5059                         status &= ~0xff;
5060                         status |= (u8)max_irr;
5061                         vmcs_write16(GUEST_INTR_STATUS, status);
5062                 }
5063         }
5064
5065         nested_mark_vmcs12_pages_dirty(vcpu);
5066 }
5067
5068 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
5069                                                      bool nested)
5070 {
5071 #ifdef CONFIG_SMP
5072         int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
5073
5074         if (vcpu->mode == IN_GUEST_MODE) {
5075                 struct vcpu_vmx *vmx = to_vmx(vcpu);
5076
5077                 /*
5078                  * Currently, we don't support urgent interrupt,
5079                  * all interrupts are recognized as non-urgent
5080                  * interrupt, so we cannot post interrupts when
5081                  * 'SN' is set.
5082                  *
5083                  * If the vcpu is in guest mode, it means it is
5084                  * running instead of being scheduled out and
5085                  * waiting in the run queue, and that's the only
5086                  * case when 'SN' is set currently, warning if
5087                  * 'SN' is set.
5088                  */
5089                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
5090
5091                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
5092                 return true;
5093         }
5094 #endif
5095         return false;
5096 }
5097
5098 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
5099                                                 int vector)
5100 {
5101         struct vcpu_vmx *vmx = to_vmx(vcpu);
5102
5103         if (is_guest_mode(vcpu) &&
5104             vector == vmx->nested.posted_intr_nv) {
5105                 /* the PIR and ON have been set by L1. */
5106                 kvm_vcpu_trigger_posted_interrupt(vcpu, true);
5107                 /*
5108                  * If a posted intr is not recognized by hardware,
5109                  * we will accomplish it in the next vmentry.
5110                  */
5111                 vmx->nested.pi_pending = true;
5112                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5113                 return 0;
5114         }
5115         return -1;
5116 }
5117 /*
5118  * Send interrupt to vcpu via posted interrupt way.
5119  * 1. If target vcpu is running(non-root mode), send posted interrupt
5120  * notification to vcpu and hardware will sync PIR to vIRR atomically.
5121  * 2. If target vcpu isn't running(root mode), kick it to pick up the
5122  * interrupt from PIR in next vmentry.
5123  */
5124 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
5125 {
5126         struct vcpu_vmx *vmx = to_vmx(vcpu);
5127         int r;
5128
5129         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
5130         if (!r)
5131                 return;
5132
5133         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
5134                 return;
5135
5136         /* If a previous notification has sent the IPI, nothing to do.  */
5137         if (pi_test_and_set_on(&vmx->pi_desc))
5138                 return;
5139
5140         if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
5141                 kvm_vcpu_kick(vcpu);
5142 }
5143
5144 /*
5145  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5146  * will not change in the lifetime of the guest.
5147  * Note that host-state that does change is set elsewhere. E.g., host-state
5148  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5149  */
5150 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
5151 {
5152         u32 low32, high32;
5153         unsigned long tmpl;
5154         struct desc_ptr dt;
5155         unsigned long cr0, cr3, cr4;
5156
5157         cr0 = read_cr0();
5158         WARN_ON(cr0 & X86_CR0_TS);
5159         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
5160
5161         /*
5162          * Save the most likely value for this task's CR3 in the VMCS.
5163          * We can't use __get_current_cr3_fast() because we're not atomic.
5164          */
5165         cr3 = __read_cr3();
5166         vmcs_writel(HOST_CR3, cr3);             /* 22.2.3  FIXME: shadow tables */
5167         vmx->host_state.vmcs_host_cr3 = cr3;
5168
5169         /* Save the most likely value for this task's CR4 in the VMCS. */
5170         cr4 = cr4_read_shadow();
5171         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
5172         vmx->host_state.vmcs_host_cr4 = cr4;
5173
5174         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
5175 #ifdef CONFIG_X86_64
5176         /*
5177          * Load null selectors, so we can avoid reloading them in
5178          * __vmx_load_host_state(), in case userspace uses the null selectors
5179          * too (the expected case).
5180          */
5181         vmcs_write16(HOST_DS_SELECTOR, 0);
5182         vmcs_write16(HOST_ES_SELECTOR, 0);
5183 #else
5184         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5185         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5186 #endif
5187         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5188         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
5189
5190         native_store_idt(&dt);
5191         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
5192         vmx->host_idt_base = dt.address;
5193
5194         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
5195
5196         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5197         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5198         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5199         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
5200
5201         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5202                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5203                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5204         }
5205 }
5206
5207 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5208 {
5209         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5210         if (enable_ept)
5211                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
5212         if (is_guest_mode(&vmx->vcpu))
5213                 vmx->vcpu.arch.cr4_guest_owned_bits &=
5214                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
5215         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5216 }
5217
5218 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5219 {
5220         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5221
5222         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5223                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
5224         /* Enable the preemption timer dynamically */
5225         pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
5226         return pin_based_exec_ctrl;
5227 }
5228
5229 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5230 {
5231         struct vcpu_vmx *vmx = to_vmx(vcpu);
5232
5233         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5234         if (cpu_has_secondary_exec_ctrls()) {
5235                 if (kvm_vcpu_apicv_active(vcpu))
5236                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5237                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
5238                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5239                 else
5240                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5241                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
5242                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5243         }
5244
5245         if (cpu_has_vmx_msr_bitmap())
5246                 vmx_set_msr_bitmap(vcpu);
5247 }
5248
5249 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5250 {
5251         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
5252
5253         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5254                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5255
5256         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
5257                 exec_control &= ~CPU_BASED_TPR_SHADOW;
5258 #ifdef CONFIG_X86_64
5259                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5260                                 CPU_BASED_CR8_LOAD_EXITING;
5261 #endif
5262         }
5263         if (!enable_ept)
5264                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5265                                 CPU_BASED_CR3_LOAD_EXITING  |
5266                                 CPU_BASED_INVLPG_EXITING;
5267         return exec_control;
5268 }
5269
5270 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
5271 {
5272         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
5273         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
5274                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5275         if (vmx->vpid == 0)
5276                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5277         if (!enable_ept) {
5278                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5279                 enable_unrestricted_guest = 0;
5280                 /* Enable INVPCID for non-ept guests may cause performance regression. */
5281                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5282         }
5283         if (!enable_unrestricted_guest)
5284                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5285         if (!ple_gap)
5286                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
5287         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5288                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5289                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5290         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
5291         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5292            (handle_vmptrld).
5293            We can NOT enable shadow_vmcs here because we don't have yet
5294            a current VMCS12
5295         */
5296         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5297
5298         if (!enable_pml)
5299                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
5300
5301         return exec_control;
5302 }
5303
5304 static void ept_set_mmio_spte_mask(void)
5305 {
5306         /*
5307          * EPT Misconfigurations can be generated if the value of bits 2:0
5308          * of an EPT paging-structure entry is 110b (write/execute).
5309          */
5310         kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
5311                                    VMX_EPT_MISCONFIG_WX_VALUE);
5312 }
5313
5314 #define VMX_XSS_EXIT_BITMAP 0
5315 /*
5316  * Sets up the vmcs for emulated real mode.
5317  */
5318 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
5319 {
5320 #ifdef CONFIG_X86_64
5321         unsigned long a;
5322 #endif
5323         int i;
5324
5325         /* I/O */
5326         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
5327         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
5328
5329         if (enable_shadow_vmcs) {
5330                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5331                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5332         }
5333         if (cpu_has_vmx_msr_bitmap())
5334                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
5335
5336         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5337
5338         /* Control */
5339         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5340         vmx->hv_deadline_tsc = -1;
5341
5342         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
5343
5344         if (cpu_has_secondary_exec_ctrls()) {
5345                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5346                                 vmx_secondary_exec_control(vmx));
5347         }
5348
5349         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
5350                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5351                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5352                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5353                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5354
5355                 vmcs_write16(GUEST_INTR_STATUS, 0);
5356
5357                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
5358                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
5359         }
5360
5361         if (ple_gap) {
5362                 vmcs_write32(PLE_GAP, ple_gap);
5363                 vmx->ple_window = ple_window;
5364                 vmx->ple_window_dirty = true;
5365         }
5366
5367         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5368         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5369         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
5370
5371         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
5372         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
5373         vmx_set_constant_host_state(vmx);
5374 #ifdef CONFIG_X86_64
5375         rdmsrl(MSR_FS_BASE, a);
5376         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5377         rdmsrl(MSR_GS_BASE, a);
5378         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5379 #else
5380         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5381         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5382 #endif
5383
5384         if (cpu_has_vmx_vmfunc())
5385                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
5386
5387         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5388         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5389         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
5390         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5391         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
5392
5393         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5394                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5395
5396         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5397                 u32 index = vmx_msr_index[i];
5398                 u32 data_low, data_high;
5399                 int j = vmx->nmsrs;
5400
5401                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5402                         continue;
5403                 if (wrmsr_safe(index, data_low, data_high) < 0)
5404                         continue;
5405                 vmx->guest_msrs[j].index = i;
5406                 vmx->guest_msrs[j].data = 0;
5407                 vmx->guest_msrs[j].mask = -1ull;
5408                 ++vmx->nmsrs;
5409         }
5410
5411
5412         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5413
5414         /* 22.2.1, 20.8.1 */
5415         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5416
5417         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
5418         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
5419
5420         set_cr4_guest_host_mask(vmx);
5421
5422         if (vmx_xsaves_supported())
5423                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5424
5425         if (enable_pml) {
5426                 ASSERT(vmx->pml_pg);
5427                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5428                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5429         }
5430
5431         return 0;
5432 }
5433
5434 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5435 {
5436         struct vcpu_vmx *vmx = to_vmx(vcpu);
5437         struct msr_data apic_base_msr;
5438         u64 cr0;
5439
5440         vmx->rmode.vm86_active = 0;
5441
5442         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5443         kvm_set_cr8(vcpu, 0);
5444
5445         if (!init_event) {
5446                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5447                                      MSR_IA32_APICBASE_ENABLE;
5448                 if (kvm_vcpu_is_reset_bsp(vcpu))
5449                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5450                 apic_base_msr.host_initiated = true;
5451                 kvm_set_apic_base(vcpu, &apic_base_msr);
5452         }
5453
5454         vmx_segment_cache_clear(vmx);
5455
5456         seg_setup(VCPU_SREG_CS);
5457         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5458         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5459
5460         seg_setup(VCPU_SREG_DS);
5461         seg_setup(VCPU_SREG_ES);
5462         seg_setup(VCPU_SREG_FS);
5463         seg_setup(VCPU_SREG_GS);
5464         seg_setup(VCPU_SREG_SS);
5465
5466         vmcs_write16(GUEST_TR_SELECTOR, 0);
5467         vmcs_writel(GUEST_TR_BASE, 0);
5468         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5469         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5470
5471         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5472         vmcs_writel(GUEST_LDTR_BASE, 0);
5473         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5474         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5475
5476         if (!init_event) {
5477                 vmcs_write32(GUEST_SYSENTER_CS, 0);
5478                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5479                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5480                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5481         }
5482
5483         vmcs_writel(GUEST_RFLAGS, 0x02);
5484         kvm_rip_write(vcpu, 0xfff0);
5485
5486         vmcs_writel(GUEST_GDTR_BASE, 0);
5487         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5488
5489         vmcs_writel(GUEST_IDTR_BASE, 0);
5490         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5491
5492         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5493         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5494         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5495
5496         setup_msrs(vmx);
5497
5498         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
5499
5500         if (cpu_has_vmx_tpr_shadow() && !init_event) {
5501                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5502                 if (cpu_need_tpr_shadow(vcpu))
5503                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5504                                      __pa(vcpu->arch.apic->regs));
5505                 vmcs_write32(TPR_THRESHOLD, 0);
5506         }
5507
5508         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5509
5510         if (kvm_vcpu_apicv_active(vcpu))
5511                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5512
5513         if (vmx->vpid != 0)
5514                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5515
5516         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5517         vmx->vcpu.arch.cr0 = cr0;
5518         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5519         vmx_set_cr4(vcpu, 0);
5520         vmx_set_efer(vcpu, 0);
5521
5522         update_exception_bitmap(vcpu);
5523
5524         vpid_sync_context(vmx->vpid);
5525 }
5526
5527 /*
5528  * In nested virtualization, check if L1 asked to exit on external interrupts.
5529  * For most existing hypervisors, this will always return true.
5530  */
5531 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5532 {
5533         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5534                 PIN_BASED_EXT_INTR_MASK;
5535 }
5536
5537 /*
5538  * In nested virtualization, check if L1 has set
5539  * VM_EXIT_ACK_INTR_ON_EXIT
5540  */
5541 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5542 {
5543         return get_vmcs12(vcpu)->vm_exit_controls &
5544                 VM_EXIT_ACK_INTR_ON_EXIT;
5545 }
5546
5547 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5548 {
5549         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5550                 PIN_BASED_NMI_EXITING;
5551 }
5552
5553 static void enable_irq_window(struct kvm_vcpu *vcpu)
5554 {
5555         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5556                       CPU_BASED_VIRTUAL_INTR_PENDING);
5557 }
5558
5559 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5560 {
5561         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5562                 enable_irq_window(vcpu);
5563                 return;
5564         }
5565
5566         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5567                       CPU_BASED_VIRTUAL_NMI_PENDING);
5568 }
5569
5570 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5571 {
5572         struct vcpu_vmx *vmx = to_vmx(vcpu);
5573         uint32_t intr;
5574         int irq = vcpu->arch.interrupt.nr;
5575
5576         trace_kvm_inj_virq(irq);
5577
5578         ++vcpu->stat.irq_injections;
5579         if (vmx->rmode.vm86_active) {
5580                 int inc_eip = 0;
5581                 if (vcpu->arch.interrupt.soft)
5582                         inc_eip = vcpu->arch.event_exit_inst_len;
5583                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5584                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5585                 return;
5586         }
5587         intr = irq | INTR_INFO_VALID_MASK;
5588         if (vcpu->arch.interrupt.soft) {
5589                 intr |= INTR_TYPE_SOFT_INTR;
5590                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5591                              vmx->vcpu.arch.event_exit_inst_len);
5592         } else
5593                 intr |= INTR_TYPE_EXT_INTR;
5594         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5595 }
5596
5597 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5598 {
5599         struct vcpu_vmx *vmx = to_vmx(vcpu);
5600
5601         ++vcpu->stat.nmi_injections;
5602         vmx->loaded_vmcs->nmi_known_unmasked = false;
5603
5604         if (vmx->rmode.vm86_active) {
5605                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5606                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5607                 return;
5608         }
5609
5610         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5611                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5612 }
5613
5614 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5615 {
5616         struct vcpu_vmx *vmx = to_vmx(vcpu);
5617         bool masked;
5618
5619         if (vmx->loaded_vmcs->nmi_known_unmasked)
5620                 return false;
5621         masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5622         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
5623         return masked;
5624 }
5625
5626 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5627 {
5628         struct vcpu_vmx *vmx = to_vmx(vcpu);
5629
5630         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
5631         if (masked)
5632                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5633                               GUEST_INTR_STATE_NMI);
5634         else
5635                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5636                                 GUEST_INTR_STATE_NMI);
5637 }
5638
5639 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5640 {
5641         if (to_vmx(vcpu)->nested.nested_run_pending)
5642                 return 0;
5643
5644         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5645                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5646                    | GUEST_INTR_STATE_NMI));
5647 }
5648
5649 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5650 {
5651         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5652                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5653                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5654                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5655 }
5656
5657 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5658 {
5659         int ret;
5660
5661         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5662                                     PAGE_SIZE * 3);
5663         if (ret)
5664                 return ret;
5665         kvm->arch.tss_addr = addr;
5666         return init_rmode_tss(kvm);
5667 }
5668
5669 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5670 {
5671         switch (vec) {
5672         case BP_VECTOR:
5673                 /*
5674                  * Update instruction length as we may reinject the exception
5675                  * from user space while in guest debugging mode.
5676                  */
5677                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5678                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5679                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5680                         return false;
5681                 /* fall through */
5682         case DB_VECTOR:
5683                 if (vcpu->guest_debug &
5684                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5685                         return false;
5686                 /* fall through */
5687         case DE_VECTOR:
5688         case OF_VECTOR:
5689         case BR_VECTOR:
5690         case UD_VECTOR:
5691         case DF_VECTOR:
5692         case SS_VECTOR:
5693         case GP_VECTOR:
5694         case MF_VECTOR:
5695                 return true;
5696         break;
5697         }
5698         return false;
5699 }
5700
5701 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5702                                   int vec, u32 err_code)
5703 {
5704         /*
5705          * Instruction with address size override prefix opcode 0x67
5706          * Cause the #SS fault with 0 error code in VM86 mode.
5707          */
5708         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5709                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5710                         if (vcpu->arch.halt_request) {
5711                                 vcpu->arch.halt_request = 0;
5712                                 return kvm_vcpu_halt(vcpu);
5713                         }
5714                         return 1;
5715                 }
5716                 return 0;
5717         }
5718
5719         /*
5720          * Forward all other exceptions that are valid in real mode.
5721          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5722          *        the required debugging infrastructure rework.
5723          */
5724         kvm_queue_exception(vcpu, vec);
5725         return 1;
5726 }
5727
5728 /*
5729  * Trigger machine check on the host. We assume all the MSRs are already set up
5730  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5731  * We pass a fake environment to the machine check handler because we want
5732  * the guest to be always treated like user space, no matter what context
5733  * it used internally.
5734  */
5735 static void kvm_machine_check(void)
5736 {
5737 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5738         struct pt_regs regs = {
5739                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5740                 .flags = X86_EFLAGS_IF,
5741         };
5742
5743         do_machine_check(&regs, 0);
5744 #endif
5745 }
5746
5747 static int handle_machine_check(struct kvm_vcpu *vcpu)
5748 {
5749         /* already handled by vcpu_run */
5750         return 1;
5751 }
5752
5753 static int handle_exception(struct kvm_vcpu *vcpu)
5754 {
5755         struct vcpu_vmx *vmx = to_vmx(vcpu);
5756         struct kvm_run *kvm_run = vcpu->run;
5757         u32 intr_info, ex_no, error_code;
5758         unsigned long cr2, rip, dr6;
5759         u32 vect_info;
5760         enum emulation_result er;
5761
5762         vect_info = vmx->idt_vectoring_info;
5763         intr_info = vmx->exit_intr_info;
5764
5765         if (is_machine_check(intr_info))
5766                 return handle_machine_check(vcpu);
5767
5768         if (is_nmi(intr_info))
5769                 return 1;  /* already handled by vmx_vcpu_run() */
5770
5771         if (is_invalid_opcode(intr_info)) {
5772                 if (is_guest_mode(vcpu)) {
5773                         kvm_queue_exception(vcpu, UD_VECTOR);
5774                         return 1;
5775                 }
5776                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5777                 if (er != EMULATE_DONE)
5778                         kvm_queue_exception(vcpu, UD_VECTOR);
5779                 return 1;
5780         }
5781
5782         error_code = 0;
5783         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5784                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5785
5786         /*
5787          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5788          * MMIO, it is better to report an internal error.
5789          * See the comments in vmx_handle_exit.
5790          */
5791         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5792             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5793                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5794                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5795                 vcpu->run->internal.ndata = 3;
5796                 vcpu->run->internal.data[0] = vect_info;
5797                 vcpu->run->internal.data[1] = intr_info;
5798                 vcpu->run->internal.data[2] = error_code;
5799                 return 0;
5800         }
5801
5802         if (is_page_fault(intr_info)) {
5803                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5804                 /* EPT won't cause page fault directly */
5805                 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
5806                 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0,
5807                                 true);
5808         }
5809
5810         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5811
5812         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5813                 return handle_rmode_exception(vcpu, ex_no, error_code);
5814
5815         switch (ex_no) {
5816         case AC_VECTOR:
5817                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5818                 return 1;
5819         case DB_VECTOR:
5820                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5821                 if (!(vcpu->guest_debug &
5822                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5823                         vcpu->arch.dr6 &= ~15;
5824                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5825                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5826                                 skip_emulated_instruction(vcpu);
5827
5828                         kvm_queue_exception(vcpu, DB_VECTOR);
5829                         return 1;
5830                 }
5831                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5832                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5833                 /* fall through */
5834         case BP_VECTOR:
5835                 /*
5836                  * Update instruction length as we may reinject #BP from
5837                  * user space while in guest debugging mode. Reading it for
5838                  * #DB as well causes no harm, it is not used in that case.
5839                  */
5840                 vmx->vcpu.arch.event_exit_inst_len =
5841                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5842                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5843                 rip = kvm_rip_read(vcpu);
5844                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5845                 kvm_run->debug.arch.exception = ex_no;
5846                 break;
5847         default:
5848                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5849                 kvm_run->ex.exception = ex_no;
5850                 kvm_run->ex.error_code = error_code;
5851                 break;
5852         }
5853         return 0;
5854 }
5855
5856 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5857 {
5858         ++vcpu->stat.irq_exits;
5859         return 1;
5860 }
5861
5862 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5863 {
5864         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5865         vcpu->mmio_needed = 0;
5866         return 0;
5867 }
5868
5869 static int handle_io(struct kvm_vcpu *vcpu)
5870 {
5871         unsigned long exit_qualification;
5872         int size, in, string, ret;
5873         unsigned port;
5874
5875         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5876         string = (exit_qualification & 16) != 0;
5877         in = (exit_qualification & 8) != 0;
5878
5879         ++vcpu->stat.io_exits;
5880
5881         if (string || in)
5882                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5883
5884         port = exit_qualification >> 16;
5885         size = (exit_qualification & 7) + 1;
5886
5887         ret = kvm_skip_emulated_instruction(vcpu);
5888
5889         /*
5890          * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5891          * KVM_EXIT_DEBUG here.
5892          */
5893         return kvm_fast_pio_out(vcpu, size, port) && ret;
5894 }
5895
5896 static void
5897 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5898 {
5899         /*
5900          * Patch in the VMCALL instruction:
5901          */
5902         hypercall[0] = 0x0f;
5903         hypercall[1] = 0x01;
5904         hypercall[2] = 0xc1;
5905 }
5906
5907 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5908 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5909 {
5910         if (is_guest_mode(vcpu)) {
5911                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5912                 unsigned long orig_val = val;
5913
5914                 /*
5915                  * We get here when L2 changed cr0 in a way that did not change
5916                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5917                  * but did change L0 shadowed bits. So we first calculate the
5918                  * effective cr0 value that L1 would like to write into the
5919                  * hardware. It consists of the L2-owned bits from the new
5920                  * value combined with the L1-owned bits from L1's guest_cr0.
5921                  */
5922                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5923                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5924
5925                 if (!nested_guest_cr0_valid(vcpu, val))
5926                         return 1;
5927
5928                 if (kvm_set_cr0(vcpu, val))
5929                         return 1;
5930                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5931                 return 0;
5932         } else {
5933                 if (to_vmx(vcpu)->nested.vmxon &&
5934                     !nested_host_cr0_valid(vcpu, val))
5935                         return 1;
5936
5937                 return kvm_set_cr0(vcpu, val);
5938         }
5939 }
5940
5941 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5942 {
5943         if (is_guest_mode(vcpu)) {
5944                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5945                 unsigned long orig_val = val;
5946
5947                 /* analogously to handle_set_cr0 */
5948                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5949                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5950                 if (kvm_set_cr4(vcpu, val))
5951                         return 1;
5952                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5953                 return 0;
5954         } else
5955                 return kvm_set_cr4(vcpu, val);
5956 }
5957
5958 static int handle_cr(struct kvm_vcpu *vcpu)
5959 {
5960         unsigned long exit_qualification, val;
5961         int cr;
5962         int reg;
5963         int err;
5964         int ret;
5965
5966         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5967         cr = exit_qualification & 15;
5968         reg = (exit_qualification >> 8) & 15;
5969         switch ((exit_qualification >> 4) & 3) {
5970         case 0: /* mov to cr */
5971                 val = kvm_register_readl(vcpu, reg);
5972                 trace_kvm_cr_write(cr, val);
5973                 switch (cr) {
5974                 case 0:
5975                         err = handle_set_cr0(vcpu, val);
5976                         return kvm_complete_insn_gp(vcpu, err);
5977                 case 3:
5978                         err = kvm_set_cr3(vcpu, val);
5979                         return kvm_complete_insn_gp(vcpu, err);
5980                 case 4:
5981                         err = handle_set_cr4(vcpu, val);
5982                         return kvm_complete_insn_gp(vcpu, err);
5983                 case 8: {
5984                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5985                                 u8 cr8 = (u8)val;
5986                                 err = kvm_set_cr8(vcpu, cr8);
5987                                 ret = kvm_complete_insn_gp(vcpu, err);
5988                                 if (lapic_in_kernel(vcpu))
5989                                         return ret;
5990                                 if (cr8_prev <= cr8)
5991                                         return ret;
5992                                 /*
5993                                  * TODO: we might be squashing a
5994                                  * KVM_GUESTDBG_SINGLESTEP-triggered
5995                                  * KVM_EXIT_DEBUG here.
5996                                  */
5997                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5998                                 return 0;
5999                         }
6000                 }
6001                 break;
6002         case 2: /* clts */
6003                 WARN_ONCE(1, "Guest should always own CR0.TS");
6004                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6005                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
6006                 return kvm_skip_emulated_instruction(vcpu);
6007         case 1: /*mov from cr*/
6008                 switch (cr) {
6009                 case 3:
6010                         val = kvm_read_cr3(vcpu);
6011                         kvm_register_write(vcpu, reg, val);
6012                         trace_kvm_cr_read(cr, val);
6013                         return kvm_skip_emulated_instruction(vcpu);
6014                 case 8:
6015                         val = kvm_get_cr8(vcpu);
6016                         kvm_register_write(vcpu, reg, val);
6017                         trace_kvm_cr_read(cr, val);
6018                         return kvm_skip_emulated_instruction(vcpu);
6019                 }
6020                 break;
6021         case 3: /* lmsw */
6022                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
6023                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
6024                 kvm_lmsw(vcpu, val);
6025
6026                 return kvm_skip_emulated_instruction(vcpu);
6027         default:
6028                 break;
6029         }
6030         vcpu->run->exit_reason = 0;
6031         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6032                (int)(exit_qualification >> 4) & 3, cr);
6033         return 0;
6034 }
6035
6036 static int handle_dr(struct kvm_vcpu *vcpu)
6037 {
6038         unsigned long exit_qualification;
6039         int dr, dr7, reg;
6040
6041         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6042         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
6043
6044         /* First, if DR does not exist, trigger UD */
6045         if (!kvm_require_dr(vcpu, dr))
6046                 return 1;
6047
6048         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
6049         if (!kvm_require_cpl(vcpu, 0))
6050                 return 1;
6051         dr7 = vmcs_readl(GUEST_DR7);
6052         if (dr7 & DR7_GD) {
6053                 /*
6054                  * As the vm-exit takes precedence over the debug trap, we
6055                  * need to emulate the latter, either for the host or the
6056                  * guest debugging itself.
6057                  */
6058                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6059                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
6060                         vcpu->run->debug.arch.dr7 = dr7;
6061                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
6062                         vcpu->run->debug.arch.exception = DB_VECTOR;
6063                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
6064                         return 0;
6065                 } else {
6066                         vcpu->arch.dr6 &= ~15;
6067                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
6068                         kvm_queue_exception(vcpu, DB_VECTOR);
6069                         return 1;
6070                 }
6071         }
6072
6073         if (vcpu->guest_debug == 0) {
6074                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6075                                 CPU_BASED_MOV_DR_EXITING);
6076
6077                 /*
6078                  * No more DR vmexits; force a reload of the debug registers
6079                  * and reenter on this instruction.  The next vmexit will
6080                  * retrieve the full state of the debug registers.
6081                  */
6082                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
6083                 return 1;
6084         }
6085
6086         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
6087         if (exit_qualification & TYPE_MOV_FROM_DR) {
6088                 unsigned long val;
6089
6090                 if (kvm_get_dr(vcpu, dr, &val))
6091                         return 1;
6092                 kvm_register_write(vcpu, reg, val);
6093         } else
6094                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
6095                         return 1;
6096
6097         return kvm_skip_emulated_instruction(vcpu);
6098 }
6099
6100 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
6101 {
6102         return vcpu->arch.dr6;
6103 }
6104
6105 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
6106 {
6107 }
6108
6109 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
6110 {
6111         get_debugreg(vcpu->arch.db[0], 0);
6112         get_debugreg(vcpu->arch.db[1], 1);
6113         get_debugreg(vcpu->arch.db[2], 2);
6114         get_debugreg(vcpu->arch.db[3], 3);
6115         get_debugreg(vcpu->arch.dr6, 6);
6116         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
6117
6118         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
6119         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
6120 }
6121
6122 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
6123 {
6124         vmcs_writel(GUEST_DR7, val);
6125 }
6126
6127 static int handle_cpuid(struct kvm_vcpu *vcpu)
6128 {
6129         return kvm_emulate_cpuid(vcpu);
6130 }
6131
6132 static int handle_rdmsr(struct kvm_vcpu *vcpu)
6133 {
6134         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6135         struct msr_data msr_info;
6136
6137         msr_info.index = ecx;
6138         msr_info.host_initiated = false;
6139         if (vmx_get_msr(vcpu, &msr_info)) {
6140                 trace_kvm_msr_read_ex(ecx);
6141                 kvm_inject_gp(vcpu, 0);
6142                 return 1;
6143         }
6144
6145         trace_kvm_msr_read(ecx, msr_info.data);
6146
6147         /* FIXME: handling of bits 32:63 of rax, rdx */
6148         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
6149         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6150         return kvm_skip_emulated_instruction(vcpu);
6151 }
6152
6153 static int handle_wrmsr(struct kvm_vcpu *vcpu)
6154 {
6155         struct msr_data msr;
6156         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6157         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
6158                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6159
6160         msr.data = data;
6161         msr.index = ecx;
6162         msr.host_initiated = false;
6163         if (kvm_set_msr(vcpu, &msr) != 0) {
6164                 trace_kvm_msr_write_ex(ecx, data);
6165                 kvm_inject_gp(vcpu, 0);
6166                 return 1;
6167         }
6168
6169         trace_kvm_msr_write(ecx, data);
6170         return kvm_skip_emulated_instruction(vcpu);
6171 }
6172
6173 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6174 {
6175         kvm_apic_update_ppr(vcpu);
6176         return 1;
6177 }
6178
6179 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6180 {
6181         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6182                         CPU_BASED_VIRTUAL_INTR_PENDING);
6183
6184         kvm_make_request(KVM_REQ_EVENT, vcpu);
6185
6186         ++vcpu->stat.irq_window_exits;
6187         return 1;
6188 }
6189
6190 static int handle_halt(struct kvm_vcpu *vcpu)
6191 {
6192         return kvm_emulate_halt(vcpu);
6193 }
6194
6195 static int handle_vmcall(struct kvm_vcpu *vcpu)
6196 {
6197         return kvm_emulate_hypercall(vcpu);
6198 }
6199
6200 static int handle_invd(struct kvm_vcpu *vcpu)
6201 {
6202         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6203 }
6204
6205 static int handle_invlpg(struct kvm_vcpu *vcpu)
6206 {
6207         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6208
6209         kvm_mmu_invlpg(vcpu, exit_qualification);
6210         return kvm_skip_emulated_instruction(vcpu);
6211 }
6212
6213 static int handle_rdpmc(struct kvm_vcpu *vcpu)
6214 {
6215         int err;
6216
6217         err = kvm_rdpmc(vcpu);
6218         return kvm_complete_insn_gp(vcpu, err);
6219 }
6220
6221 static int handle_wbinvd(struct kvm_vcpu *vcpu)
6222 {
6223         return kvm_emulate_wbinvd(vcpu);
6224 }
6225
6226 static int handle_xsetbv(struct kvm_vcpu *vcpu)
6227 {
6228         u64 new_bv = kvm_read_edx_eax(vcpu);
6229         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6230
6231         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6232                 return kvm_skip_emulated_instruction(vcpu);
6233         return 1;
6234 }
6235
6236 static int handle_xsaves(struct kvm_vcpu *vcpu)
6237 {
6238         kvm_skip_emulated_instruction(vcpu);
6239         WARN(1, "this should never happen\n");
6240         return 1;
6241 }
6242
6243 static int handle_xrstors(struct kvm_vcpu *vcpu)
6244 {
6245         kvm_skip_emulated_instruction(vcpu);
6246         WARN(1, "this should never happen\n");
6247         return 1;
6248 }
6249
6250 static int handle_apic_access(struct kvm_vcpu *vcpu)
6251 {
6252         if (likely(fasteoi)) {
6253                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6254                 int access_type, offset;
6255
6256                 access_type = exit_qualification & APIC_ACCESS_TYPE;
6257                 offset = exit_qualification & APIC_ACCESS_OFFSET;
6258                 /*
6259                  * Sane guest uses MOV to write EOI, with written value
6260                  * not cared. So make a short-circuit here by avoiding
6261                  * heavy instruction emulation.
6262                  */
6263                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6264                     (offset == APIC_EOI)) {
6265                         kvm_lapic_set_eoi(vcpu);
6266                         return kvm_skip_emulated_instruction(vcpu);
6267                 }
6268         }
6269         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6270 }
6271
6272 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6273 {
6274         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6275         int vector = exit_qualification & 0xff;
6276
6277         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6278         kvm_apic_set_eoi_accelerated(vcpu, vector);
6279         return 1;
6280 }
6281
6282 static int handle_apic_write(struct kvm_vcpu *vcpu)
6283 {
6284         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6285         u32 offset = exit_qualification & 0xfff;
6286
6287         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6288         kvm_apic_write_nodecode(vcpu, offset);
6289         return 1;
6290 }
6291
6292 static int handle_task_switch(struct kvm_vcpu *vcpu)
6293 {
6294         struct vcpu_vmx *vmx = to_vmx(vcpu);
6295         unsigned long exit_qualification;
6296         bool has_error_code = false;
6297         u32 error_code = 0;
6298         u16 tss_selector;
6299         int reason, type, idt_v, idt_index;
6300
6301         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6302         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6303         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6304
6305         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6306
6307         reason = (u32)exit_qualification >> 30;
6308         if (reason == TASK_SWITCH_GATE && idt_v) {
6309                 switch (type) {
6310                 case INTR_TYPE_NMI_INTR:
6311                         vcpu->arch.nmi_injected = false;
6312                         vmx_set_nmi_mask(vcpu, true);
6313                         break;
6314                 case INTR_TYPE_EXT_INTR:
6315                 case INTR_TYPE_SOFT_INTR:
6316                         kvm_clear_interrupt_queue(vcpu);
6317                         break;
6318                 case INTR_TYPE_HARD_EXCEPTION:
6319                         if (vmx->idt_vectoring_info &
6320                             VECTORING_INFO_DELIVER_CODE_MASK) {
6321                                 has_error_code = true;
6322                                 error_code =
6323                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
6324                         }
6325                         /* fall through */
6326                 case INTR_TYPE_SOFT_EXCEPTION:
6327                         kvm_clear_exception_queue(vcpu);
6328                         break;
6329                 default:
6330                         break;
6331                 }
6332         }
6333         tss_selector = exit_qualification;
6334
6335         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6336                        type != INTR_TYPE_EXT_INTR &&
6337                        type != INTR_TYPE_NMI_INTR))
6338                 skip_emulated_instruction(vcpu);
6339
6340         if (kvm_task_switch(vcpu, tss_selector,
6341                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6342                             has_error_code, error_code) == EMULATE_FAIL) {
6343                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6344                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6345                 vcpu->run->internal.ndata = 0;
6346                 return 0;
6347         }
6348
6349         /*
6350          * TODO: What about debug traps on tss switch?
6351          *       Are we supposed to inject them and update dr6?
6352          */
6353
6354         return 1;
6355 }
6356
6357 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6358 {
6359         unsigned long exit_qualification;
6360         gpa_t gpa;
6361         u64 error_code;
6362
6363         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6364
6365         /*
6366          * EPT violation happened while executing iret from NMI,
6367          * "blocked by NMI" bit has to be set before next VM entry.
6368          * There are errata that may cause this bit to not be set:
6369          * AAK134, BY25.
6370          */
6371         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6372                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6373                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6374
6375         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6376         trace_kvm_page_fault(gpa, exit_qualification);
6377
6378         /* Is it a read fault? */
6379         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
6380                      ? PFERR_USER_MASK : 0;
6381         /* Is it a write fault? */
6382         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
6383                       ? PFERR_WRITE_MASK : 0;
6384         /* Is it a fetch fault? */
6385         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
6386                       ? PFERR_FETCH_MASK : 0;
6387         /* ept page table entry is present? */
6388         error_code |= (exit_qualification &
6389                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
6390                         EPT_VIOLATION_EXECUTABLE))
6391                       ? PFERR_PRESENT_MASK : 0;
6392
6393         error_code |= (exit_qualification & 0x100) != 0 ?
6394                PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
6395
6396         vcpu->arch.gpa_available = true;
6397         vcpu->arch.exit_qualification = exit_qualification;
6398
6399         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6400 }
6401
6402 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6403 {
6404         int ret;
6405         gpa_t gpa;
6406
6407         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6408         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6409                 trace_kvm_fast_mmio(gpa);
6410                 return kvm_skip_emulated_instruction(vcpu);
6411         }
6412
6413         vcpu->arch.gpa_available = true;
6414         ret = kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
6415         if (ret >= 0)
6416                 return ret;
6417
6418         /* It is the real ept misconfig */
6419         WARN_ON(1);
6420
6421         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6422         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6423
6424         return 0;
6425 }
6426
6427 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6428 {
6429         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6430                         CPU_BASED_VIRTUAL_NMI_PENDING);
6431         ++vcpu->stat.nmi_window_exits;
6432         kvm_make_request(KVM_REQ_EVENT, vcpu);
6433
6434         return 1;
6435 }
6436
6437 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6438 {
6439         struct vcpu_vmx *vmx = to_vmx(vcpu);
6440         enum emulation_result err = EMULATE_DONE;
6441         int ret = 1;
6442         u32 cpu_exec_ctrl;
6443         bool intr_window_requested;
6444         unsigned count = 130;
6445
6446         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6447         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6448
6449         while (vmx->emulation_required && count-- != 0) {
6450                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6451                         return handle_interrupt_window(&vmx->vcpu);
6452
6453                 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
6454                         return 1;
6455
6456                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6457
6458                 if (err == EMULATE_USER_EXIT) {
6459                         ++vcpu->stat.mmio_exits;
6460                         ret = 0;
6461                         goto out;
6462                 }
6463
6464                 if (err != EMULATE_DONE) {
6465                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6466                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6467                         vcpu->run->internal.ndata = 0;
6468                         return 0;
6469                 }
6470
6471                 if (vcpu->arch.halt_request) {
6472                         vcpu->arch.halt_request = 0;
6473                         ret = kvm_vcpu_halt(vcpu);
6474                         goto out;
6475                 }
6476
6477                 if (signal_pending(current))
6478                         goto out;
6479                 if (need_resched())
6480                         schedule();
6481         }
6482
6483 out:
6484         return ret;
6485 }
6486
6487 static int __grow_ple_window(int val)
6488 {
6489         if (ple_window_grow < 1)
6490                 return ple_window;
6491
6492         val = min(val, ple_window_actual_max);
6493
6494         if (ple_window_grow < ple_window)
6495                 val *= ple_window_grow;
6496         else
6497                 val += ple_window_grow;
6498
6499         return val;
6500 }
6501
6502 static int __shrink_ple_window(int val, int modifier, int minimum)
6503 {
6504         if (modifier < 1)
6505                 return ple_window;
6506
6507         if (modifier < ple_window)
6508                 val /= modifier;
6509         else
6510                 val -= modifier;
6511
6512         return max(val, minimum);
6513 }
6514
6515 static void grow_ple_window(struct kvm_vcpu *vcpu)
6516 {
6517         struct vcpu_vmx *vmx = to_vmx(vcpu);
6518         int old = vmx->ple_window;
6519
6520         vmx->ple_window = __grow_ple_window(old);
6521
6522         if (vmx->ple_window != old)
6523                 vmx->ple_window_dirty = true;
6524
6525         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6526 }
6527
6528 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6529 {
6530         struct vcpu_vmx *vmx = to_vmx(vcpu);
6531         int old = vmx->ple_window;
6532
6533         vmx->ple_window = __shrink_ple_window(old,
6534                                               ple_window_shrink, ple_window);
6535
6536         if (vmx->ple_window != old)
6537                 vmx->ple_window_dirty = true;
6538
6539         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6540 }
6541
6542 /*
6543  * ple_window_actual_max is computed to be one grow_ple_window() below
6544  * ple_window_max. (See __grow_ple_window for the reason.)
6545  * This prevents overflows, because ple_window_max is int.
6546  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6547  * this process.
6548  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6549  */
6550 static void update_ple_window_actual_max(void)
6551 {
6552         ple_window_actual_max =
6553                         __shrink_ple_window(max(ple_window_max, ple_window),
6554                                             ple_window_grow, INT_MIN);
6555 }
6556
6557 /*
6558  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6559  */
6560 static void wakeup_handler(void)
6561 {
6562         struct kvm_vcpu *vcpu;
6563         int cpu = smp_processor_id();
6564
6565         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6566         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6567                         blocked_vcpu_list) {
6568                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6569
6570                 if (pi_test_on(pi_desc) == 1)
6571                         kvm_vcpu_kick(vcpu);
6572         }
6573         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6574 }
6575
6576 void vmx_enable_tdp(void)
6577 {
6578         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6579                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
6580                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
6581                 0ull, VMX_EPT_EXECUTABLE_MASK,
6582                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
6583                 VMX_EPT_RWX_MASK);
6584
6585         ept_set_mmio_spte_mask();
6586         kvm_enable_tdp();
6587 }
6588
6589 static __init int hardware_setup(void)
6590 {
6591         int r = -ENOMEM, i, msr;
6592
6593         rdmsrl_safe(MSR_EFER, &host_efer);
6594
6595         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6596                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6597
6598         for (i = 0; i < VMX_BITMAP_NR; i++) {
6599                 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
6600                 if (!vmx_bitmap[i])
6601                         goto out;
6602         }
6603
6604         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6605         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6606         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6607
6608         /*
6609          * Allow direct access to the PC debug port (it is often used for I/O
6610          * delays, but the vmexits simply slow things down).
6611          */
6612         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6613         clear_bit(0x80, vmx_io_bitmap_a);
6614
6615         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6616
6617         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6618         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6619
6620         if (setup_vmcs_config(&vmcs_config) < 0) {
6621                 r = -EIO;
6622                 goto out;
6623         }
6624
6625         if (boot_cpu_has(X86_FEATURE_NX))
6626                 kvm_enable_efer_bits(EFER_NX);
6627
6628         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6629                 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6630                 enable_vpid = 0;
6631
6632         if (!cpu_has_vmx_shadow_vmcs())
6633                 enable_shadow_vmcs = 0;
6634         if (enable_shadow_vmcs)
6635                 init_vmcs_shadow_fields();
6636
6637         if (!cpu_has_vmx_ept() ||
6638             !cpu_has_vmx_ept_4levels()) {
6639                 enable_ept = 0;
6640                 enable_unrestricted_guest = 0;
6641                 enable_ept_ad_bits = 0;
6642         }
6643
6644         if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
6645                 enable_ept_ad_bits = 0;
6646
6647         if (!cpu_has_vmx_unrestricted_guest())
6648                 enable_unrestricted_guest = 0;
6649
6650         if (!cpu_has_vmx_flexpriority())
6651                 flexpriority_enabled = 0;
6652
6653         /*
6654          * set_apic_access_page_addr() is used to reload apic access
6655          * page upon invalidation.  No need to do anything if not
6656          * using the APIC_ACCESS_ADDR VMCS field.
6657          */
6658         if (!flexpriority_enabled)
6659                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6660
6661         if (!cpu_has_vmx_tpr_shadow())
6662                 kvm_x86_ops->update_cr8_intercept = NULL;
6663
6664         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6665                 kvm_disable_largepages();
6666
6667         if (!cpu_has_vmx_ple())
6668                 ple_gap = 0;
6669
6670         if (!cpu_has_vmx_apicv()) {
6671                 enable_apicv = 0;
6672                 kvm_x86_ops->sync_pir_to_irr = NULL;
6673         }
6674
6675         if (cpu_has_vmx_tsc_scaling()) {
6676                 kvm_has_tsc_control = true;
6677                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6678                 kvm_tsc_scaling_ratio_frac_bits = 48;
6679         }
6680
6681         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6682         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6683         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6684         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6685         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6686         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6687
6688         memcpy(vmx_msr_bitmap_legacy_x2apic_apicv,
6689                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6690         memcpy(vmx_msr_bitmap_longmode_x2apic_apicv,
6691                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6692         memcpy(vmx_msr_bitmap_legacy_x2apic,
6693                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6694         memcpy(vmx_msr_bitmap_longmode_x2apic,
6695                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6696
6697         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6698
6699         for (msr = 0x800; msr <= 0x8ff; msr++) {
6700                 if (msr == 0x839 /* TMCCT */)
6701                         continue;
6702                 vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true);
6703         }
6704
6705         /*
6706          * TPR reads and writes can be virtualized even if virtual interrupt
6707          * delivery is not in use.
6708          */
6709         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true);
6710         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false);
6711
6712         /* EOI */
6713         vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true);
6714         /* SELF-IPI */
6715         vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true);
6716
6717         if (enable_ept)
6718                 vmx_enable_tdp();
6719         else
6720                 kvm_disable_tdp();
6721
6722         update_ple_window_actual_max();
6723
6724         /*
6725          * Only enable PML when hardware supports PML feature, and both EPT
6726          * and EPT A/D bit features are enabled -- PML depends on them to work.
6727          */
6728         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6729                 enable_pml = 0;
6730
6731         if (!enable_pml) {
6732                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6733                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6734                 kvm_x86_ops->flush_log_dirty = NULL;
6735                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6736         }
6737
6738         if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6739                 u64 vmx_msr;
6740
6741                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6742                 cpu_preemption_timer_multi =
6743                          vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6744         } else {
6745                 kvm_x86_ops->set_hv_timer = NULL;
6746                 kvm_x86_ops->cancel_hv_timer = NULL;
6747         }
6748
6749         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6750
6751         kvm_mce_cap_supported |= MCG_LMCE_P;
6752
6753         return alloc_kvm_area();
6754
6755 out:
6756         for (i = 0; i < VMX_BITMAP_NR; i++)
6757                 free_page((unsigned long)vmx_bitmap[i]);
6758
6759     return r;
6760 }
6761
6762 static __exit void hardware_unsetup(void)
6763 {
6764         int i;
6765
6766         for (i = 0; i < VMX_BITMAP_NR; i++)
6767                 free_page((unsigned long)vmx_bitmap[i]);
6768
6769         free_kvm_area();
6770 }
6771
6772 /*
6773  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6774  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6775  */
6776 static int handle_pause(struct kvm_vcpu *vcpu)
6777 {
6778         if (ple_gap)
6779                 grow_ple_window(vcpu);
6780
6781         /*
6782          * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
6783          * VM-execution control is ignored if CPL > 0. OTOH, KVM
6784          * never set PAUSE_EXITING and just set PLE if supported,
6785          * so the vcpu must be CPL=0 if it gets a PAUSE exit.
6786          */
6787         kvm_vcpu_on_spin(vcpu, true);
6788         return kvm_skip_emulated_instruction(vcpu);
6789 }
6790
6791 static int handle_nop(struct kvm_vcpu *vcpu)
6792 {
6793         return kvm_skip_emulated_instruction(vcpu);
6794 }
6795
6796 static int handle_mwait(struct kvm_vcpu *vcpu)
6797 {
6798         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6799         return handle_nop(vcpu);
6800 }
6801
6802 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6803 {
6804         return 1;
6805 }
6806
6807 static int handle_monitor(struct kvm_vcpu *vcpu)
6808 {
6809         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6810         return handle_nop(vcpu);
6811 }
6812
6813 /*
6814  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6815  * We could reuse a single VMCS for all the L2 guests, but we also want the
6816  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6817  * allows keeping them loaded on the processor, and in the future will allow
6818  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6819  * every entry if they never change.
6820  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6821  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6822  *
6823  * The following functions allocate and free a vmcs02 in this pool.
6824  */
6825
6826 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6827 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6828 {
6829         struct vmcs02_list *item;
6830         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6831                 if (item->vmptr == vmx->nested.current_vmptr) {
6832                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6833                         return &item->vmcs02;
6834                 }
6835
6836         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6837                 /* Recycle the least recently used VMCS. */
6838                 item = list_last_entry(&vmx->nested.vmcs02_pool,
6839                                        struct vmcs02_list, list);
6840                 item->vmptr = vmx->nested.current_vmptr;
6841                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6842                 return &item->vmcs02;
6843         }
6844
6845         /* Create a new VMCS */
6846         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6847         if (!item)
6848                 return NULL;
6849         item->vmcs02.vmcs = alloc_vmcs();
6850         item->vmcs02.shadow_vmcs = NULL;
6851         if (!item->vmcs02.vmcs) {
6852                 kfree(item);
6853                 return NULL;
6854         }
6855         loaded_vmcs_init(&item->vmcs02);
6856         item->vmptr = vmx->nested.current_vmptr;
6857         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6858         vmx->nested.vmcs02_num++;
6859         return &item->vmcs02;
6860 }
6861
6862 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6863 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6864 {
6865         struct vmcs02_list *item;
6866         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6867                 if (item->vmptr == vmptr) {
6868                         free_loaded_vmcs(&item->vmcs02);
6869                         list_del(&item->list);
6870                         kfree(item);
6871                         vmx->nested.vmcs02_num--;
6872                         return;
6873                 }
6874 }
6875
6876 /*
6877  * Free all VMCSs saved for this vcpu, except the one pointed by
6878  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6879  * must be &vmx->vmcs01.
6880  */
6881 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6882 {
6883         struct vmcs02_list *item, *n;
6884
6885         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6886         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6887                 /*
6888                  * Something will leak if the above WARN triggers.  Better than
6889                  * a use-after-free.
6890                  */
6891                 if (vmx->loaded_vmcs == &item->vmcs02)
6892                         continue;
6893
6894                 free_loaded_vmcs(&item->vmcs02);
6895                 list_del(&item->list);
6896                 kfree(item);
6897                 vmx->nested.vmcs02_num--;
6898         }
6899 }
6900
6901 /*
6902  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6903  * set the success or error code of an emulated VMX instruction, as specified
6904  * by Vol 2B, VMX Instruction Reference, "Conventions".
6905  */
6906 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6907 {
6908         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6909                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6910                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6911 }
6912
6913 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6914 {
6915         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6916                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6917                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6918                         | X86_EFLAGS_CF);
6919 }
6920
6921 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6922                                         u32 vm_instruction_error)
6923 {
6924         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6925                 /*
6926                  * failValid writes the error number to the current VMCS, which
6927                  * can't be done there isn't a current VMCS.
6928                  */
6929                 nested_vmx_failInvalid(vcpu);
6930                 return;
6931         }
6932         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6933                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6934                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6935                         | X86_EFLAGS_ZF);
6936         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6937         /*
6938          * We don't need to force a shadow sync because
6939          * VM_INSTRUCTION_ERROR is not shadowed
6940          */
6941 }
6942
6943 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6944 {
6945         /* TODO: not to reset guest simply here. */
6946         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6947         pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
6948 }
6949
6950 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6951 {
6952         struct vcpu_vmx *vmx =
6953                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6954
6955         vmx->nested.preemption_timer_expired = true;
6956         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6957         kvm_vcpu_kick(&vmx->vcpu);
6958
6959         return HRTIMER_NORESTART;
6960 }
6961
6962 /*
6963  * Decode the memory-address operand of a vmx instruction, as recorded on an
6964  * exit caused by such an instruction (run by a guest hypervisor).
6965  * On success, returns 0. When the operand is invalid, returns 1 and throws
6966  * #UD or #GP.
6967  */
6968 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6969                                  unsigned long exit_qualification,
6970                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6971 {
6972         gva_t off;
6973         bool exn;
6974         struct kvm_segment s;
6975
6976         /*
6977          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6978          * Execution", on an exit, vmx_instruction_info holds most of the
6979          * addressing components of the operand. Only the displacement part
6980          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6981          * For how an actual address is calculated from all these components,
6982          * refer to Vol. 1, "Operand Addressing".
6983          */
6984         int  scaling = vmx_instruction_info & 3;
6985         int  addr_size = (vmx_instruction_info >> 7) & 7;
6986         bool is_reg = vmx_instruction_info & (1u << 10);
6987         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6988         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6989         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6990         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6991         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6992
6993         if (is_reg) {
6994                 kvm_queue_exception(vcpu, UD_VECTOR);
6995                 return 1;
6996         }
6997
6998         /* Addr = segment_base + offset */
6999         /* offset = base + [index * scale] + displacement */
7000         off = exit_qualification; /* holds the displacement */
7001         if (base_is_valid)
7002                 off += kvm_register_read(vcpu, base_reg);
7003         if (index_is_valid)
7004                 off += kvm_register_read(vcpu, index_reg)<<scaling;
7005         vmx_get_segment(vcpu, &s, seg_reg);
7006         *ret = s.base + off;
7007
7008         if (addr_size == 1) /* 32 bit */
7009                 *ret &= 0xffffffff;
7010
7011         /* Checks for #GP/#SS exceptions. */
7012         exn = false;
7013         if (is_long_mode(vcpu)) {
7014                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
7015                  * non-canonical form. This is the only check on the memory
7016                  * destination for long mode!
7017                  */
7018                 exn = is_noncanonical_address(*ret);
7019         } else if (is_protmode(vcpu)) {
7020                 /* Protected mode: apply checks for segment validity in the
7021                  * following order:
7022                  * - segment type check (#GP(0) may be thrown)
7023                  * - usability check (#GP(0)/#SS(0))
7024                  * - limit check (#GP(0)/#SS(0))
7025                  */
7026                 if (wr)
7027                         /* #GP(0) if the destination operand is located in a
7028                          * read-only data segment or any code segment.
7029                          */
7030                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
7031                 else
7032                         /* #GP(0) if the source operand is located in an
7033                          * execute-only code segment
7034                          */
7035                         exn = ((s.type & 0xa) == 8);
7036                 if (exn) {
7037                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7038                         return 1;
7039                 }
7040                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
7041                  */
7042                 exn = (s.unusable != 0);
7043                 /* Protected mode: #GP(0)/#SS(0) if the memory
7044                  * operand is outside the segment limit.
7045                  */
7046                 exn = exn || (off + sizeof(u64) > s.limit);
7047         }
7048         if (exn) {
7049                 kvm_queue_exception_e(vcpu,
7050                                       seg_reg == VCPU_SREG_SS ?
7051                                                 SS_VECTOR : GP_VECTOR,
7052                                       0);
7053                 return 1;
7054         }
7055
7056         return 0;
7057 }
7058
7059 static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer)
7060 {
7061         gva_t gva;
7062         struct x86_exception e;
7063
7064         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7065                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
7066                 return 1;
7067
7068         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, vmpointer,
7069                                 sizeof(*vmpointer), &e)) {
7070                 kvm_inject_page_fault(vcpu, &e);
7071                 return 1;
7072         }
7073
7074         return 0;
7075 }
7076
7077 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
7078 {
7079         struct vcpu_vmx *vmx = to_vmx(vcpu);
7080         struct vmcs *shadow_vmcs;
7081
7082         if (cpu_has_vmx_msr_bitmap()) {
7083                 vmx->nested.msr_bitmap =
7084                                 (unsigned long *)__get_free_page(GFP_KERNEL);
7085                 if (!vmx->nested.msr_bitmap)
7086                         goto out_msr_bitmap;
7087         }
7088
7089         vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7090         if (!vmx->nested.cached_vmcs12)
7091                 goto out_cached_vmcs12;
7092
7093         if (enable_shadow_vmcs) {
7094                 shadow_vmcs = alloc_vmcs();
7095                 if (!shadow_vmcs)
7096                         goto out_shadow_vmcs;
7097                 /* mark vmcs as shadow */
7098                 shadow_vmcs->revision_id |= (1u << 31);
7099                 /* init shadow vmcs */
7100                 vmcs_clear(shadow_vmcs);
7101                 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7102         }
7103
7104         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
7105         vmx->nested.vmcs02_num = 0;
7106
7107         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7108                      HRTIMER_MODE_REL_PINNED);
7109         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7110
7111         vmx->nested.vmxon = true;
7112         return 0;
7113
7114 out_shadow_vmcs:
7115         kfree(vmx->nested.cached_vmcs12);
7116
7117 out_cached_vmcs12:
7118         free_page((unsigned long)vmx->nested.msr_bitmap);
7119
7120 out_msr_bitmap:
7121         return -ENOMEM;
7122 }
7123
7124 /*
7125  * Emulate the VMXON instruction.
7126  * Currently, we just remember that VMX is active, and do not save or even
7127  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7128  * do not currently need to store anything in that guest-allocated memory
7129  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7130  * argument is different from the VMXON pointer (which the spec says they do).
7131  */
7132 static int handle_vmon(struct kvm_vcpu *vcpu)
7133 {
7134         int ret;
7135         gpa_t vmptr;
7136         struct page *page;
7137         struct vcpu_vmx *vmx = to_vmx(vcpu);
7138         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7139                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7140
7141         /*
7142          * The Intel VMX Instruction Reference lists a bunch of bits that are
7143          * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7144          * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7145          * Otherwise, we should fail with #UD.  But most faulting conditions
7146          * have already been checked by hardware, prior to the VM-exit for
7147          * VMXON.  We do test guest cr4.VMXE because processor CR4 always has
7148          * that bit set to 1 in non-root mode.
7149          */
7150         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
7151                 kvm_queue_exception(vcpu, UD_VECTOR);
7152                 return 1;
7153         }
7154
7155         if (vmx->nested.vmxon) {
7156                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7157                 return kvm_skip_emulated_instruction(vcpu);
7158         }
7159
7160         if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
7161                         != VMXON_NEEDED_FEATURES) {
7162                 kvm_inject_gp(vcpu, 0);
7163                 return 1;
7164         }
7165
7166         if (nested_vmx_get_vmptr(vcpu, &vmptr))
7167                 return 1;
7168
7169         /*
7170          * SDM 3: 24.11.5
7171          * The first 4 bytes of VMXON region contain the supported
7172          * VMCS revision identifier
7173          *
7174          * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7175          * which replaces physical address width with 32
7176          */
7177         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7178                 nested_vmx_failInvalid(vcpu);
7179                 return kvm_skip_emulated_instruction(vcpu);
7180         }
7181
7182         page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
7183         if (is_error_page(page)) {
7184                 nested_vmx_failInvalid(vcpu);
7185                 return kvm_skip_emulated_instruction(vcpu);
7186         }
7187         if (*(u32 *)kmap(page) != VMCS12_REVISION) {
7188                 kunmap(page);
7189                 kvm_release_page_clean(page);
7190                 nested_vmx_failInvalid(vcpu);
7191                 return kvm_skip_emulated_instruction(vcpu);
7192         }
7193         kunmap(page);
7194         kvm_release_page_clean(page);
7195
7196         vmx->nested.vmxon_ptr = vmptr;
7197         ret = enter_vmx_operation(vcpu);
7198         if (ret)
7199                 return ret;
7200
7201         nested_vmx_succeed(vcpu);
7202         return kvm_skip_emulated_instruction(vcpu);
7203 }
7204
7205 /*
7206  * Intel's VMX Instruction Reference specifies a common set of prerequisites
7207  * for running VMX instructions (except VMXON, whose prerequisites are
7208  * slightly different). It also specifies what exception to inject otherwise.
7209  * Note that many of these exceptions have priority over VM exits, so they
7210  * don't have to be checked again here.
7211  */
7212 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7213 {
7214         if (!to_vmx(vcpu)->nested.vmxon) {
7215                 kvm_queue_exception(vcpu, UD_VECTOR);
7216                 return 0;
7217         }
7218         return 1;
7219 }
7220
7221 static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx)
7222 {
7223         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_SHADOW_VMCS);
7224         vmcs_write64(VMCS_LINK_POINTER, -1ull);
7225 }
7226
7227 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7228 {
7229         if (vmx->nested.current_vmptr == -1ull)
7230                 return;
7231
7232         if (enable_shadow_vmcs) {
7233                 /* copy to memory all shadowed fields in case
7234                    they were modified */
7235                 copy_shadow_to_vmcs12(vmx);
7236                 vmx->nested.sync_shadow_vmcs = false;
7237                 vmx_disable_shadow_vmcs(vmx);
7238         }
7239         vmx->nested.posted_intr_nv = -1;
7240
7241         /* Flush VMCS12 to guest memory */
7242         kvm_vcpu_write_guest_page(&vmx->vcpu,
7243                                   vmx->nested.current_vmptr >> PAGE_SHIFT,
7244                                   vmx->nested.cached_vmcs12, 0, VMCS12_SIZE);
7245
7246         vmx->nested.current_vmptr = -1ull;
7247 }
7248
7249 /*
7250  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7251  * just stops using VMX.
7252  */
7253 static void free_nested(struct vcpu_vmx *vmx)
7254 {
7255         if (!vmx->nested.vmxon)
7256                 return;
7257
7258         vmx->nested.vmxon = false;
7259         free_vpid(vmx->nested.vpid02);
7260         vmx->nested.posted_intr_nv = -1;
7261         vmx->nested.current_vmptr = -1ull;
7262         if (vmx->nested.msr_bitmap) {
7263                 free_page((unsigned long)vmx->nested.msr_bitmap);
7264                 vmx->nested.msr_bitmap = NULL;
7265         }
7266         if (enable_shadow_vmcs) {
7267                 vmx_disable_shadow_vmcs(vmx);
7268                 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7269                 free_vmcs(vmx->vmcs01.shadow_vmcs);
7270                 vmx->vmcs01.shadow_vmcs = NULL;
7271         }
7272         kfree(vmx->nested.cached_vmcs12);
7273         /* Unpin physical memory we referred to in current vmcs02 */
7274         if (vmx->nested.apic_access_page) {
7275                 kvm_release_page_dirty(vmx->nested.apic_access_page);
7276                 vmx->nested.apic_access_page = NULL;
7277         }
7278         if (vmx->nested.virtual_apic_page) {
7279                 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
7280                 vmx->nested.virtual_apic_page = NULL;
7281         }
7282         if (vmx->nested.pi_desc_page) {
7283                 kunmap(vmx->nested.pi_desc_page);
7284                 kvm_release_page_dirty(vmx->nested.pi_desc_page);
7285                 vmx->nested.pi_desc_page = NULL;
7286                 vmx->nested.pi_desc = NULL;
7287         }
7288
7289         nested_free_all_saved_vmcss(vmx);
7290 }
7291
7292 /* Emulate the VMXOFF instruction */
7293 static int handle_vmoff(struct kvm_vcpu *vcpu)
7294 {
7295         if (!nested_vmx_check_permission(vcpu))
7296                 return 1;
7297         free_nested(to_vmx(vcpu));
7298         nested_vmx_succeed(vcpu);
7299         return kvm_skip_emulated_instruction(vcpu);
7300 }
7301
7302 /* Emulate the VMCLEAR instruction */
7303 static int handle_vmclear(struct kvm_vcpu *vcpu)
7304 {
7305         struct vcpu_vmx *vmx = to_vmx(vcpu);
7306         u32 zero = 0;
7307         gpa_t vmptr;
7308
7309         if (!nested_vmx_check_permission(vcpu))
7310                 return 1;
7311
7312         if (nested_vmx_get_vmptr(vcpu, &vmptr))
7313                 return 1;
7314
7315         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7316                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
7317                 return kvm_skip_emulated_instruction(vcpu);
7318         }
7319
7320         if (vmptr == vmx->nested.vmxon_ptr) {
7321                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER);
7322                 return kvm_skip_emulated_instruction(vcpu);
7323         }
7324
7325         if (vmptr == vmx->nested.current_vmptr)
7326                 nested_release_vmcs12(vmx);
7327
7328         kvm_vcpu_write_guest(vcpu,
7329                         vmptr + offsetof(struct vmcs12, launch_state),
7330                         &zero, sizeof(zero));
7331
7332         nested_free_vmcs02(vmx, vmptr);
7333
7334         nested_vmx_succeed(vcpu);
7335         return kvm_skip_emulated_instruction(vcpu);
7336 }
7337
7338 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7339
7340 /* Emulate the VMLAUNCH instruction */
7341 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7342 {
7343         return nested_vmx_run(vcpu, true);
7344 }
7345
7346 /* Emulate the VMRESUME instruction */
7347 static int handle_vmresume(struct kvm_vcpu *vcpu)
7348 {
7349
7350         return nested_vmx_run(vcpu, false);
7351 }
7352
7353 /*
7354  * Read a vmcs12 field. Since these can have varying lengths and we return
7355  * one type, we chose the biggest type (u64) and zero-extend the return value
7356  * to that size. Note that the caller, handle_vmread, might need to use only
7357  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7358  * 64-bit fields are to be returned).
7359  */
7360 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7361                                   unsigned long field, u64 *ret)
7362 {
7363         short offset = vmcs_field_to_offset(field);
7364         char *p;
7365
7366         if (offset < 0)
7367                 return offset;
7368
7369         p = ((char *)(get_vmcs12(vcpu))) + offset;
7370
7371         switch (vmcs_field_type(field)) {
7372         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7373                 *ret = *((natural_width *)p);
7374                 return 0;
7375         case VMCS_FIELD_TYPE_U16:
7376                 *ret = *((u16 *)p);
7377                 return 0;
7378         case VMCS_FIELD_TYPE_U32:
7379                 *ret = *((u32 *)p);
7380                 return 0;
7381         case VMCS_FIELD_TYPE_U64:
7382                 *ret = *((u64 *)p);
7383                 return 0;
7384         default:
7385                 WARN_ON(1);
7386                 return -ENOENT;
7387         }
7388 }
7389
7390
7391 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7392                                    unsigned long field, u64 field_value){
7393         short offset = vmcs_field_to_offset(field);
7394         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7395         if (offset < 0)
7396                 return offset;
7397
7398         switch (vmcs_field_type(field)) {
7399         case VMCS_FIELD_TYPE_U16:
7400                 *(u16 *)p = field_value;
7401                 return 0;
7402         case VMCS_FIELD_TYPE_U32:
7403                 *(u32 *)p = field_value;
7404                 return 0;
7405         case VMCS_FIELD_TYPE_U64:
7406                 *(u64 *)p = field_value;
7407                 return 0;
7408         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7409                 *(natural_width *)p = field_value;
7410                 return 0;
7411         default:
7412                 WARN_ON(1);
7413                 return -ENOENT;
7414         }
7415
7416 }
7417
7418 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7419 {
7420         int i;
7421         unsigned long field;
7422         u64 field_value;
7423         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7424         const unsigned long *fields = shadow_read_write_fields;
7425         const int num_fields = max_shadow_read_write_fields;
7426
7427         preempt_disable();
7428
7429         vmcs_load(shadow_vmcs);
7430
7431         for (i = 0; i < num_fields; i++) {
7432                 field = fields[i];
7433                 switch (vmcs_field_type(field)) {
7434                 case VMCS_FIELD_TYPE_U16:
7435                         field_value = vmcs_read16(field);
7436                         break;
7437                 case VMCS_FIELD_TYPE_U32:
7438                         field_value = vmcs_read32(field);
7439                         break;
7440                 case VMCS_FIELD_TYPE_U64:
7441                         field_value = vmcs_read64(field);
7442                         break;
7443                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7444                         field_value = vmcs_readl(field);
7445                         break;
7446                 default:
7447                         WARN_ON(1);
7448                         continue;
7449                 }
7450                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7451         }
7452
7453         vmcs_clear(shadow_vmcs);
7454         vmcs_load(vmx->loaded_vmcs->vmcs);
7455
7456         preempt_enable();
7457 }
7458
7459 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7460 {
7461         const unsigned long *fields[] = {
7462                 shadow_read_write_fields,
7463                 shadow_read_only_fields
7464         };
7465         const int max_fields[] = {
7466                 max_shadow_read_write_fields,
7467                 max_shadow_read_only_fields
7468         };
7469         int i, q;
7470         unsigned long field;
7471         u64 field_value = 0;
7472         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7473
7474         vmcs_load(shadow_vmcs);
7475
7476         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7477                 for (i = 0; i < max_fields[q]; i++) {
7478                         field = fields[q][i];
7479                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7480
7481                         switch (vmcs_field_type(field)) {
7482                         case VMCS_FIELD_TYPE_U16:
7483                                 vmcs_write16(field, (u16)field_value);
7484                                 break;
7485                         case VMCS_FIELD_TYPE_U32:
7486                                 vmcs_write32(field, (u32)field_value);
7487                                 break;
7488                         case VMCS_FIELD_TYPE_U64:
7489                                 vmcs_write64(field, (u64)field_value);
7490                                 break;
7491                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7492                                 vmcs_writel(field, (long)field_value);
7493                                 break;
7494                         default:
7495                                 WARN_ON(1);
7496                                 break;
7497                         }
7498                 }
7499         }
7500
7501         vmcs_clear(shadow_vmcs);
7502         vmcs_load(vmx->loaded_vmcs->vmcs);
7503 }
7504
7505 /*
7506  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7507  * used before) all generate the same failure when it is missing.
7508  */
7509 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7510 {
7511         struct vcpu_vmx *vmx = to_vmx(vcpu);
7512         if (vmx->nested.current_vmptr == -1ull) {
7513                 nested_vmx_failInvalid(vcpu);
7514                 return 0;
7515         }
7516         return 1;
7517 }
7518
7519 static int handle_vmread(struct kvm_vcpu *vcpu)
7520 {
7521         unsigned long field;
7522         u64 field_value;
7523         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7524         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7525         gva_t gva = 0;
7526
7527         if (!nested_vmx_check_permission(vcpu))
7528                 return 1;
7529
7530         if (!nested_vmx_check_vmcs12(vcpu))
7531                 return kvm_skip_emulated_instruction(vcpu);
7532
7533         /* Decode instruction info and find the field to read */
7534         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7535         /* Read the field, zero-extended to a u64 field_value */
7536         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7537                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7538                 return kvm_skip_emulated_instruction(vcpu);
7539         }
7540         /*
7541          * Now copy part of this value to register or memory, as requested.
7542          * Note that the number of bits actually copied is 32 or 64 depending
7543          * on the guest's mode (32 or 64 bit), not on the given field's length.
7544          */
7545         if (vmx_instruction_info & (1u << 10)) {
7546                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7547                         field_value);
7548         } else {
7549                 if (get_vmx_mem_address(vcpu, exit_qualification,
7550                                 vmx_instruction_info, true, &gva))
7551                         return 1;
7552                 /* _system ok, as hardware has verified cpl=0 */
7553                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7554                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7555         }
7556
7557         nested_vmx_succeed(vcpu);
7558         return kvm_skip_emulated_instruction(vcpu);
7559 }
7560
7561
7562 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7563 {
7564         unsigned long field;
7565         gva_t gva;
7566         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7567         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7568         /* The value to write might be 32 or 64 bits, depending on L1's long
7569          * mode, and eventually we need to write that into a field of several
7570          * possible lengths. The code below first zero-extends the value to 64
7571          * bit (field_value), and then copies only the appropriate number of
7572          * bits into the vmcs12 field.
7573          */
7574         u64 field_value = 0;
7575         struct x86_exception e;
7576
7577         if (!nested_vmx_check_permission(vcpu))
7578                 return 1;
7579
7580         if (!nested_vmx_check_vmcs12(vcpu))
7581                 return kvm_skip_emulated_instruction(vcpu);
7582
7583         if (vmx_instruction_info & (1u << 10))
7584                 field_value = kvm_register_readl(vcpu,
7585                         (((vmx_instruction_info) >> 3) & 0xf));
7586         else {
7587                 if (get_vmx_mem_address(vcpu, exit_qualification,
7588                                 vmx_instruction_info, false, &gva))
7589                         return 1;
7590                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7591                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7592                         kvm_inject_page_fault(vcpu, &e);
7593                         return 1;
7594                 }
7595         }
7596
7597
7598         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7599         if (vmcs_field_readonly(field)) {
7600                 nested_vmx_failValid(vcpu,
7601                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7602                 return kvm_skip_emulated_instruction(vcpu);
7603         }
7604
7605         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7606                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7607                 return kvm_skip_emulated_instruction(vcpu);
7608         }
7609
7610         nested_vmx_succeed(vcpu);
7611         return kvm_skip_emulated_instruction(vcpu);
7612 }
7613
7614 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
7615 {
7616         vmx->nested.current_vmptr = vmptr;
7617         if (enable_shadow_vmcs) {
7618                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7619                               SECONDARY_EXEC_SHADOW_VMCS);
7620                 vmcs_write64(VMCS_LINK_POINTER,
7621                              __pa(vmx->vmcs01.shadow_vmcs));
7622                 vmx->nested.sync_shadow_vmcs = true;
7623         }
7624 }
7625
7626 /* Emulate the VMPTRLD instruction */
7627 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7628 {
7629         struct vcpu_vmx *vmx = to_vmx(vcpu);
7630         gpa_t vmptr;
7631
7632         if (!nested_vmx_check_permission(vcpu))
7633                 return 1;
7634
7635         if (nested_vmx_get_vmptr(vcpu, &vmptr))
7636                 return 1;
7637
7638         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7639                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
7640                 return kvm_skip_emulated_instruction(vcpu);
7641         }
7642
7643         if (vmptr == vmx->nested.vmxon_ptr) {
7644                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER);
7645                 return kvm_skip_emulated_instruction(vcpu);
7646         }
7647
7648         if (vmx->nested.current_vmptr != vmptr) {
7649                 struct vmcs12 *new_vmcs12;
7650                 struct page *page;
7651                 page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
7652                 if (is_error_page(page)) {
7653                         nested_vmx_failInvalid(vcpu);
7654                         return kvm_skip_emulated_instruction(vcpu);
7655                 }
7656                 new_vmcs12 = kmap(page);
7657                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7658                         kunmap(page);
7659                         kvm_release_page_clean(page);
7660                         nested_vmx_failValid(vcpu,
7661                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7662                         return kvm_skip_emulated_instruction(vcpu);
7663                 }
7664
7665                 nested_release_vmcs12(vmx);
7666                 /*
7667                  * Load VMCS12 from guest memory since it is not already
7668                  * cached.
7669                  */
7670                 memcpy(vmx->nested.cached_vmcs12, new_vmcs12, VMCS12_SIZE);
7671                 kunmap(page);
7672                 kvm_release_page_clean(page);
7673
7674                 set_current_vmptr(vmx, vmptr);
7675         }
7676
7677         nested_vmx_succeed(vcpu);
7678         return kvm_skip_emulated_instruction(vcpu);
7679 }
7680
7681 /* Emulate the VMPTRST instruction */
7682 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7683 {
7684         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7685         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7686         gva_t vmcs_gva;
7687         struct x86_exception e;
7688
7689         if (!nested_vmx_check_permission(vcpu))
7690                 return 1;
7691
7692         if (get_vmx_mem_address(vcpu, exit_qualification,
7693                         vmx_instruction_info, true, &vmcs_gva))
7694                 return 1;
7695         /* ok to use *_system, as hardware has verified cpl=0 */
7696         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7697                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7698                                  sizeof(u64), &e)) {
7699                 kvm_inject_page_fault(vcpu, &e);
7700                 return 1;
7701         }
7702         nested_vmx_succeed(vcpu);
7703         return kvm_skip_emulated_instruction(vcpu);
7704 }
7705
7706 /* Emulate the INVEPT instruction */
7707 static int handle_invept(struct kvm_vcpu *vcpu)
7708 {
7709         struct vcpu_vmx *vmx = to_vmx(vcpu);
7710         u32 vmx_instruction_info, types;
7711         unsigned long type;
7712         gva_t gva;
7713         struct x86_exception e;
7714         struct {
7715                 u64 eptp, gpa;
7716         } operand;
7717
7718         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7719               SECONDARY_EXEC_ENABLE_EPT) ||
7720             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7721                 kvm_queue_exception(vcpu, UD_VECTOR);
7722                 return 1;
7723         }
7724
7725         if (!nested_vmx_check_permission(vcpu))
7726                 return 1;
7727
7728         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7729         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7730
7731         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7732
7733         if (type >= 32 || !(types & (1 << type))) {
7734                 nested_vmx_failValid(vcpu,
7735                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7736                 return kvm_skip_emulated_instruction(vcpu);
7737         }
7738
7739         /* According to the Intel VMX instruction reference, the memory
7740          * operand is read even if it isn't needed (e.g., for type==global)
7741          */
7742         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7743                         vmx_instruction_info, false, &gva))
7744                 return 1;
7745         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7746                                 sizeof(operand), &e)) {
7747                 kvm_inject_page_fault(vcpu, &e);
7748                 return 1;
7749         }
7750
7751         switch (type) {
7752         case VMX_EPT_EXTENT_GLOBAL:
7753         /*
7754          * TODO: track mappings and invalidate
7755          * single context requests appropriately
7756          */
7757         case VMX_EPT_EXTENT_CONTEXT:
7758                 kvm_mmu_sync_roots(vcpu);
7759                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7760                 nested_vmx_succeed(vcpu);
7761                 break;
7762         default:
7763                 BUG_ON(1);
7764                 break;
7765         }
7766
7767         return kvm_skip_emulated_instruction(vcpu);
7768 }
7769
7770 static int handle_invvpid(struct kvm_vcpu *vcpu)
7771 {
7772         struct vcpu_vmx *vmx = to_vmx(vcpu);
7773         u32 vmx_instruction_info;
7774         unsigned long type, types;
7775         gva_t gva;
7776         struct x86_exception e;
7777         struct {
7778                 u64 vpid;
7779                 u64 gla;
7780         } operand;
7781
7782         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7783               SECONDARY_EXEC_ENABLE_VPID) ||
7784                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7785                 kvm_queue_exception(vcpu, UD_VECTOR);
7786                 return 1;
7787         }
7788
7789         if (!nested_vmx_check_permission(vcpu))
7790                 return 1;
7791
7792         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7793         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7794
7795         types = (vmx->nested.nested_vmx_vpid_caps &
7796                         VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
7797
7798         if (type >= 32 || !(types & (1 << type))) {
7799                 nested_vmx_failValid(vcpu,
7800                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7801                 return kvm_skip_emulated_instruction(vcpu);
7802         }
7803
7804         /* according to the intel vmx instruction reference, the memory
7805          * operand is read even if it isn't needed (e.g., for type==global)
7806          */
7807         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7808                         vmx_instruction_info, false, &gva))
7809                 return 1;
7810         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7811                                 sizeof(operand), &e)) {
7812                 kvm_inject_page_fault(vcpu, &e);
7813                 return 1;
7814         }
7815         if (operand.vpid >> 16) {
7816                 nested_vmx_failValid(vcpu,
7817                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7818                 return kvm_skip_emulated_instruction(vcpu);
7819         }
7820
7821         switch (type) {
7822         case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
7823                 if (is_noncanonical_address(operand.gla)) {
7824                         nested_vmx_failValid(vcpu,
7825                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7826                         return kvm_skip_emulated_instruction(vcpu);
7827                 }
7828                 /* fall through */
7829         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7830         case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
7831                 if (!operand.vpid) {
7832                         nested_vmx_failValid(vcpu,
7833                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7834                         return kvm_skip_emulated_instruction(vcpu);
7835                 }
7836                 break;
7837         case VMX_VPID_EXTENT_ALL_CONTEXT:
7838                 break;
7839         default:
7840                 WARN_ON_ONCE(1);
7841                 return kvm_skip_emulated_instruction(vcpu);
7842         }
7843
7844         __vmx_flush_tlb(vcpu, vmx->nested.vpid02);
7845         nested_vmx_succeed(vcpu);
7846
7847         return kvm_skip_emulated_instruction(vcpu);
7848 }
7849
7850 static int handle_pml_full(struct kvm_vcpu *vcpu)
7851 {
7852         unsigned long exit_qualification;
7853
7854         trace_kvm_pml_full(vcpu->vcpu_id);
7855
7856         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7857
7858         /*
7859          * PML buffer FULL happened while executing iret from NMI,
7860          * "blocked by NMI" bit has to be set before next VM entry.
7861          */
7862         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7863                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7864                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7865                                 GUEST_INTR_STATE_NMI);
7866
7867         /*
7868          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7869          * here.., and there's no userspace involvement needed for PML.
7870          */
7871         return 1;
7872 }
7873
7874 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7875 {
7876         kvm_lapic_expired_hv_timer(vcpu);
7877         return 1;
7878 }
7879
7880 static bool valid_ept_address(struct kvm_vcpu *vcpu, u64 address)
7881 {
7882         struct vcpu_vmx *vmx = to_vmx(vcpu);
7883         u64 mask = address & 0x7;
7884         int maxphyaddr = cpuid_maxphyaddr(vcpu);
7885
7886         /* Check for memory type validity */
7887         switch (mask) {
7888         case 0:
7889                 if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPTP_UC_BIT))
7890                         return false;
7891                 break;
7892         case 6:
7893                 if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPTP_WB_BIT))
7894                         return false;
7895                 break;
7896         default:
7897                 return false;
7898         }
7899
7900         /* Bits 5:3 must be 3 */
7901         if (((address >> VMX_EPT_GAW_EPTP_SHIFT) & 0x7) != VMX_EPT_DEFAULT_GAW)
7902                 return false;
7903
7904         /* Reserved bits should not be set */
7905         if (address >> maxphyaddr || ((address >> 7) & 0x1f))
7906                 return false;
7907
7908         /* AD, if set, should be supported */
7909         if ((address & VMX_EPT_AD_ENABLE_BIT)) {
7910                 if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPT_AD_BIT))
7911                         return false;
7912         }
7913
7914         return true;
7915 }
7916
7917 static int nested_vmx_eptp_switching(struct kvm_vcpu *vcpu,
7918                                      struct vmcs12 *vmcs12)
7919 {
7920         u32 index = vcpu->arch.regs[VCPU_REGS_RCX];
7921         u64 address;
7922         bool accessed_dirty;
7923         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7924
7925         if (!nested_cpu_has_eptp_switching(vmcs12) ||
7926             !nested_cpu_has_ept(vmcs12))
7927                 return 1;
7928
7929         if (index >= VMFUNC_EPTP_ENTRIES)
7930                 return 1;
7931
7932
7933         if (kvm_vcpu_read_guest_page(vcpu, vmcs12->eptp_list_address >> PAGE_SHIFT,
7934                                      &address, index * 8, 8))
7935                 return 1;
7936
7937         accessed_dirty = !!(address & VMX_EPT_AD_ENABLE_BIT);
7938
7939         /*
7940          * If the (L2) guest does a vmfunc to the currently
7941          * active ept pointer, we don't have to do anything else
7942          */
7943         if (vmcs12->ept_pointer != address) {
7944                 if (!valid_ept_address(vcpu, address))
7945                         return 1;
7946
7947                 kvm_mmu_unload(vcpu);
7948                 mmu->ept_ad = accessed_dirty;
7949                 mmu->base_role.ad_disabled = !accessed_dirty;
7950                 vmcs12->ept_pointer = address;
7951                 /*
7952                  * TODO: Check what's the correct approach in case
7953                  * mmu reload fails. Currently, we just let the next
7954                  * reload potentially fail
7955                  */
7956                 kvm_mmu_reload(vcpu);
7957         }
7958
7959         return 0;
7960 }
7961
7962 static int handle_vmfunc(struct kvm_vcpu *vcpu)
7963 {
7964         struct vcpu_vmx *vmx = to_vmx(vcpu);
7965         struct vmcs12 *vmcs12;
7966         u32 function = vcpu->arch.regs[VCPU_REGS_RAX];
7967
7968         /*
7969          * VMFUNC is only supported for nested guests, but we always enable the
7970          * secondary control for simplicity; for non-nested mode, fake that we
7971          * didn't by injecting #UD.
7972          */
7973         if (!is_guest_mode(vcpu)) {
7974                 kvm_queue_exception(vcpu, UD_VECTOR);
7975                 return 1;
7976         }
7977
7978         vmcs12 = get_vmcs12(vcpu);
7979         if ((vmcs12->vm_function_control & (1 << function)) == 0)
7980                 goto fail;
7981
7982         switch (function) {
7983         case 0:
7984                 if (nested_vmx_eptp_switching(vcpu, vmcs12))
7985                         goto fail;
7986                 break;
7987         default:
7988                 goto fail;
7989         }
7990         return kvm_skip_emulated_instruction(vcpu);
7991
7992 fail:
7993         nested_vmx_vmexit(vcpu, vmx->exit_reason,
7994                           vmcs_read32(VM_EXIT_INTR_INFO),
7995                           vmcs_readl(EXIT_QUALIFICATION));
7996         return 1;
7997 }
7998
7999 /*
8000  * The exit handlers return 1 if the exit was handled fully and guest execution
8001  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
8002  * to be done to userspace and return 0.
8003  */
8004 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
8005         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
8006         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
8007         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
8008         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
8009         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
8010         [EXIT_REASON_CR_ACCESS]               = handle_cr,
8011         [EXIT_REASON_DR_ACCESS]               = handle_dr,
8012         [EXIT_REASON_CPUID]                   = handle_cpuid,
8013         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
8014         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
8015         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
8016         [EXIT_REASON_HLT]                     = handle_halt,
8017         [EXIT_REASON_INVD]                    = handle_invd,
8018         [EXIT_REASON_INVLPG]                  = handle_invlpg,
8019         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
8020         [EXIT_REASON_VMCALL]                  = handle_vmcall,
8021         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
8022         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
8023         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
8024         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
8025         [EXIT_REASON_VMREAD]                  = handle_vmread,
8026         [EXIT_REASON_VMRESUME]                = handle_vmresume,
8027         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
8028         [EXIT_REASON_VMOFF]                   = handle_vmoff,
8029         [EXIT_REASON_VMON]                    = handle_vmon,
8030         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
8031         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
8032         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
8033         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
8034         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
8035         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
8036         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
8037         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
8038         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
8039         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
8040         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
8041         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
8042         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
8043         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
8044         [EXIT_REASON_INVEPT]                  = handle_invept,
8045         [EXIT_REASON_INVVPID]                 = handle_invvpid,
8046         [EXIT_REASON_XSAVES]                  = handle_xsaves,
8047         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
8048         [EXIT_REASON_PML_FULL]                = handle_pml_full,
8049         [EXIT_REASON_VMFUNC]                  = handle_vmfunc,
8050         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
8051 };
8052
8053 static const int kvm_vmx_max_exit_handlers =
8054         ARRAY_SIZE(kvm_vmx_exit_handlers);
8055
8056 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
8057                                        struct vmcs12 *vmcs12)
8058 {
8059         unsigned long exit_qualification;
8060         gpa_t bitmap, last_bitmap;
8061         unsigned int port;
8062         int size;
8063         u8 b;
8064
8065         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
8066                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
8067
8068         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8069
8070         port = exit_qualification >> 16;
8071         size = (exit_qualification & 7) + 1;
8072
8073         last_bitmap = (gpa_t)-1;
8074         b = -1;
8075
8076         while (size > 0) {
8077                 if (port < 0x8000)
8078                         bitmap = vmcs12->io_bitmap_a;
8079                 else if (port < 0x10000)
8080                         bitmap = vmcs12->io_bitmap_b;
8081                 else
8082                         return true;
8083                 bitmap += (port & 0x7fff) / 8;
8084
8085                 if (last_bitmap != bitmap)
8086                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
8087                                 return true;
8088                 if (b & (1 << (port & 7)))
8089                         return true;
8090
8091                 port++;
8092                 size--;
8093                 last_bitmap = bitmap;
8094         }
8095
8096         return false;
8097 }
8098
8099 /*
8100  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
8101  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
8102  * disinterest in the current event (read or write a specific MSR) by using an
8103  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
8104  */
8105 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
8106         struct vmcs12 *vmcs12, u32 exit_reason)
8107 {
8108         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
8109         gpa_t bitmap;
8110
8111         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8112                 return true;
8113
8114         /*
8115          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
8116          * for the four combinations of read/write and low/high MSR numbers.
8117          * First we need to figure out which of the four to use:
8118          */
8119         bitmap = vmcs12->msr_bitmap;
8120         if (exit_reason == EXIT_REASON_MSR_WRITE)
8121                 bitmap += 2048;
8122         if (msr_index >= 0xc0000000) {
8123                 msr_index -= 0xc0000000;
8124                 bitmap += 1024;
8125         }
8126
8127         /* Then read the msr_index'th bit from this bitmap: */
8128         if (msr_index < 1024*8) {
8129                 unsigned char b;
8130                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
8131                         return true;
8132                 return 1 & (b >> (msr_index & 7));
8133         } else
8134                 return true; /* let L1 handle the wrong parameter */
8135 }
8136
8137 /*
8138  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
8139  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
8140  * intercept (via guest_host_mask etc.) the current event.
8141  */
8142 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
8143         struct vmcs12 *vmcs12)
8144 {
8145         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8146         int cr = exit_qualification & 15;
8147         int reg;
8148         unsigned long val;
8149
8150         switch ((exit_qualification >> 4) & 3) {
8151         case 0: /* mov to cr */
8152                 reg = (exit_qualification >> 8) & 15;
8153                 val = kvm_register_readl(vcpu, reg);
8154                 switch (cr) {
8155                 case 0:
8156                         if (vmcs12->cr0_guest_host_mask &
8157                             (val ^ vmcs12->cr0_read_shadow))
8158                                 return true;
8159                         break;
8160                 case 3:
8161                         if ((vmcs12->cr3_target_count >= 1 &&
8162                                         vmcs12->cr3_target_value0 == val) ||
8163                                 (vmcs12->cr3_target_count >= 2 &&
8164                                         vmcs12->cr3_target_value1 == val) ||
8165                                 (vmcs12->cr3_target_count >= 3 &&
8166                                         vmcs12->cr3_target_value2 == val) ||
8167                                 (vmcs12->cr3_target_count >= 4 &&
8168                                         vmcs12->cr3_target_value3 == val))
8169                                 return false;
8170                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
8171                                 return true;
8172                         break;
8173                 case 4:
8174                         if (vmcs12->cr4_guest_host_mask &
8175                             (vmcs12->cr4_read_shadow ^ val))
8176                                 return true;
8177                         break;
8178                 case 8:
8179                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
8180                                 return true;
8181                         break;
8182                 }
8183                 break;
8184         case 2: /* clts */
8185                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
8186                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
8187                         return true;
8188                 break;
8189         case 1: /* mov from cr */
8190                 switch (cr) {
8191                 case 3:
8192                         if (vmcs12->cpu_based_vm_exec_control &
8193                             CPU_BASED_CR3_STORE_EXITING)
8194                                 return true;
8195                         break;
8196                 case 8:
8197                         if (vmcs12->cpu_based_vm_exec_control &
8198                             CPU_BASED_CR8_STORE_EXITING)
8199                                 return true;
8200                         break;
8201                 }
8202                 break;
8203         case 3: /* lmsw */
8204                 /*
8205                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8206                  * cr0. Other attempted changes are ignored, with no exit.
8207                  */
8208                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
8209                 if (vmcs12->cr0_guest_host_mask & 0xe &
8210                     (val ^ vmcs12->cr0_read_shadow))
8211                         return true;
8212                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
8213                     !(vmcs12->cr0_read_shadow & 0x1) &&
8214                     (val & 0x1))
8215                         return true;
8216                 break;
8217         }
8218         return false;
8219 }
8220
8221 /*
8222  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8223  * should handle it ourselves in L0 (and then continue L2). Only call this
8224  * when in is_guest_mode (L2).
8225  */
8226 static bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason)
8227 {
8228         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8229         struct vcpu_vmx *vmx = to_vmx(vcpu);
8230         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8231
8232         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
8233                                 vmcs_readl(EXIT_QUALIFICATION),
8234                                 vmx->idt_vectoring_info,
8235                                 intr_info,
8236                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8237                                 KVM_ISA_VMX);
8238
8239         /*
8240          * The host physical addresses of some pages of guest memory
8241          * are loaded into VMCS02 (e.g. L1's Virtual APIC Page). The CPU
8242          * may write to these pages via their host physical address while
8243          * L2 is running, bypassing any address-translation-based dirty
8244          * tracking (e.g. EPT write protection).
8245          *
8246          * Mark them dirty on every exit from L2 to prevent them from
8247          * getting out of sync with dirty tracking.
8248          */
8249         nested_mark_vmcs12_pages_dirty(vcpu);
8250
8251         if (vmx->nested.nested_run_pending)
8252                 return false;
8253
8254         if (unlikely(vmx->fail)) {
8255                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8256                                     vmcs_read32(VM_INSTRUCTION_ERROR));
8257                 return true;
8258         }
8259
8260         switch (exit_reason) {
8261         case EXIT_REASON_EXCEPTION_NMI:
8262                 if (is_nmi(intr_info))
8263                         return false;
8264                 else if (is_page_fault(intr_info))
8265                         return !vmx->vcpu.arch.apf.host_apf_reason && enable_ept;
8266                 else if (is_no_device(intr_info) &&
8267                          !(vmcs12->guest_cr0 & X86_CR0_TS))
8268                         return false;
8269                 else if (is_debug(intr_info) &&
8270                          vcpu->guest_debug &
8271                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8272                         return false;
8273                 else if (is_breakpoint(intr_info) &&
8274                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8275                         return false;
8276                 return vmcs12->exception_bitmap &
8277                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8278         case EXIT_REASON_EXTERNAL_INTERRUPT:
8279                 return false;
8280         case EXIT_REASON_TRIPLE_FAULT:
8281                 return true;
8282         case EXIT_REASON_PENDING_INTERRUPT:
8283                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
8284         case EXIT_REASON_NMI_WINDOW:
8285                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
8286         case EXIT_REASON_TASK_SWITCH:
8287                 return true;
8288         case EXIT_REASON_CPUID:
8289                 return true;
8290         case EXIT_REASON_HLT:
8291                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8292         case EXIT_REASON_INVD:
8293                 return true;
8294         case EXIT_REASON_INVLPG:
8295                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8296         case EXIT_REASON_RDPMC:
8297                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8298         case EXIT_REASON_RDRAND:
8299                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND);
8300         case EXIT_REASON_RDSEED:
8301                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED);
8302         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8303                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8304         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8305         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8306         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8307         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8308         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8309         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8310                 /*
8311                  * VMX instructions trap unconditionally. This allows L1 to
8312                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
8313                  */
8314                 return true;
8315         case EXIT_REASON_CR_ACCESS:
8316                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8317         case EXIT_REASON_DR_ACCESS:
8318                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8319         case EXIT_REASON_IO_INSTRUCTION:
8320                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8321         case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8322                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
8323         case EXIT_REASON_MSR_READ:
8324         case EXIT_REASON_MSR_WRITE:
8325                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8326         case EXIT_REASON_INVALID_STATE:
8327                 return true;
8328         case EXIT_REASON_MWAIT_INSTRUCTION:
8329                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8330         case EXIT_REASON_MONITOR_TRAP_FLAG:
8331                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8332         case EXIT_REASON_MONITOR_INSTRUCTION:
8333                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8334         case EXIT_REASON_PAUSE_INSTRUCTION:
8335                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8336                         nested_cpu_has2(vmcs12,
8337                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8338         case EXIT_REASON_MCE_DURING_VMENTRY:
8339                 return false;
8340         case EXIT_REASON_TPR_BELOW_THRESHOLD:
8341                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8342         case EXIT_REASON_APIC_ACCESS:
8343                 return nested_cpu_has2(vmcs12,
8344                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8345         case EXIT_REASON_APIC_WRITE:
8346         case EXIT_REASON_EOI_INDUCED:
8347                 /* apic_write and eoi_induced should exit unconditionally. */
8348                 return true;
8349         case EXIT_REASON_EPT_VIOLATION:
8350                 /*
8351                  * L0 always deals with the EPT violation. If nested EPT is
8352                  * used, and the nested mmu code discovers that the address is
8353                  * missing in the guest EPT table (EPT12), the EPT violation
8354                  * will be injected with nested_ept_inject_page_fault()
8355                  */
8356                 return false;
8357         case EXIT_REASON_EPT_MISCONFIG:
8358                 /*
8359                  * L2 never uses directly L1's EPT, but rather L0's own EPT
8360                  * table (shadow on EPT) or a merged EPT table that L0 built
8361                  * (EPT on EPT). So any problems with the structure of the
8362                  * table is L0's fault.
8363                  */
8364                 return false;
8365         case EXIT_REASON_INVPCID:
8366                 return
8367                         nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_INVPCID) &&
8368                         nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8369         case EXIT_REASON_WBINVD:
8370                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8371         case EXIT_REASON_XSETBV:
8372                 return true;
8373         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8374                 /*
8375                  * This should never happen, since it is not possible to
8376                  * set XSS to a non-zero value---neither in L1 nor in L2.
8377                  * If if it were, XSS would have to be checked against
8378                  * the XSS exit bitmap in vmcs12.
8379                  */
8380                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8381         case EXIT_REASON_PREEMPTION_TIMER:
8382                 return false;
8383         case EXIT_REASON_PML_FULL:
8384                 /* We emulate PML support to L1. */
8385                 return false;
8386         case EXIT_REASON_VMFUNC:
8387                 /* VM functions are emulated through L2->L0 vmexits. */
8388                 return false;
8389         default:
8390                 return true;
8391         }
8392 }
8393
8394 static int nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason)
8395 {
8396         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8397
8398         /*
8399          * At this point, the exit interruption info in exit_intr_info
8400          * is only valid for EXCEPTION_NMI exits.  For EXTERNAL_INTERRUPT
8401          * we need to query the in-kernel LAPIC.
8402          */
8403         WARN_ON(exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT);
8404         if ((exit_intr_info &
8405              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8406             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) {
8407                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8408                 vmcs12->vm_exit_intr_error_code =
8409                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
8410         }
8411
8412         nested_vmx_vmexit(vcpu, exit_reason, exit_intr_info,
8413                           vmcs_readl(EXIT_QUALIFICATION));
8414         return 1;
8415 }
8416
8417 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8418 {
8419         *info1 = vmcs_readl(EXIT_QUALIFICATION);
8420         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8421 }
8422
8423 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8424 {
8425         if (vmx->pml_pg) {
8426                 __free_page(vmx->pml_pg);
8427                 vmx->pml_pg = NULL;
8428         }
8429 }
8430
8431 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8432 {
8433         struct vcpu_vmx *vmx = to_vmx(vcpu);
8434         u64 *pml_buf;
8435         u16 pml_idx;
8436
8437         pml_idx = vmcs_read16(GUEST_PML_INDEX);
8438
8439         /* Do nothing if PML buffer is empty */
8440         if (pml_idx == (PML_ENTITY_NUM - 1))
8441                 return;
8442
8443         /* PML index always points to next available PML buffer entity */
8444         if (pml_idx >= PML_ENTITY_NUM)
8445                 pml_idx = 0;
8446         else
8447                 pml_idx++;
8448
8449         pml_buf = page_address(vmx->pml_pg);
8450         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8451                 u64 gpa;
8452
8453                 gpa = pml_buf[pml_idx];
8454                 WARN_ON(gpa & (PAGE_SIZE - 1));
8455                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8456         }
8457
8458         /* reset PML index */
8459         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8460 }
8461
8462 /*
8463  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8464  * Called before reporting dirty_bitmap to userspace.
8465  */
8466 static void kvm_flush_pml_buffers(struct kvm *kvm)
8467 {
8468         int i;
8469         struct kvm_vcpu *vcpu;
8470         /*
8471          * We only need to kick vcpu out of guest mode here, as PML buffer
8472          * is flushed at beginning of all VMEXITs, and it's obvious that only
8473          * vcpus running in guest are possible to have unflushed GPAs in PML
8474          * buffer.
8475          */
8476         kvm_for_each_vcpu(i, vcpu, kvm)
8477                 kvm_vcpu_kick(vcpu);
8478 }
8479
8480 static void vmx_dump_sel(char *name, uint32_t sel)
8481 {
8482         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8483                name, vmcs_read16(sel),
8484                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8485                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8486                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8487 }
8488
8489 static void vmx_dump_dtsel(char *name, uint32_t limit)
8490 {
8491         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
8492                name, vmcs_read32(limit),
8493                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8494 }
8495
8496 static void dump_vmcs(void)
8497 {
8498         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8499         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8500         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8501         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8502         u32 secondary_exec_control = 0;
8503         unsigned long cr4 = vmcs_readl(GUEST_CR4);
8504         u64 efer = vmcs_read64(GUEST_IA32_EFER);
8505         int i, n;
8506
8507         if (cpu_has_secondary_exec_ctrls())
8508                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8509
8510         pr_err("*** Guest State ***\n");
8511         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8512                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8513                vmcs_readl(CR0_GUEST_HOST_MASK));
8514         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8515                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8516         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8517         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8518             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8519         {
8520                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
8521                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8522                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
8523                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8524         }
8525         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
8526                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8527         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
8528                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8529         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8530                vmcs_readl(GUEST_SYSENTER_ESP),
8531                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8532         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
8533         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
8534         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
8535         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
8536         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
8537         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
8538         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8539         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8540         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8541         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
8542         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8543             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8544                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
8545                        efer, vmcs_read64(GUEST_IA32_PAT));
8546         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
8547                vmcs_read64(GUEST_IA32_DEBUGCTL),
8548                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8549         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8550                 pr_err("PerfGlobCtl = 0x%016llx\n",
8551                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8552         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8553                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8554         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
8555                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8556                vmcs_read32(GUEST_ACTIVITY_STATE));
8557         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8558                 pr_err("InterruptStatus = %04x\n",
8559                        vmcs_read16(GUEST_INTR_STATUS));
8560
8561         pr_err("*** Host State ***\n");
8562         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8563                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8564         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8565                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8566                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8567                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8568                vmcs_read16(HOST_TR_SELECTOR));
8569         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8570                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8571                vmcs_readl(HOST_TR_BASE));
8572         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8573                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8574         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8575                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8576                vmcs_readl(HOST_CR4));
8577         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8578                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8579                vmcs_read32(HOST_IA32_SYSENTER_CS),
8580                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8581         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8582                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
8583                        vmcs_read64(HOST_IA32_EFER),
8584                        vmcs_read64(HOST_IA32_PAT));
8585         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8586                 pr_err("PerfGlobCtl = 0x%016llx\n",
8587                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8588
8589         pr_err("*** Control State ***\n");
8590         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8591                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8592         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8593         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8594                vmcs_read32(EXCEPTION_BITMAP),
8595                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8596                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8597         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8598                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8599                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8600                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8601         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8602                vmcs_read32(VM_EXIT_INTR_INFO),
8603                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8604                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8605         pr_err("        reason=%08x qualification=%016lx\n",
8606                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8607         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8608                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8609                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8610         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8611         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8612                 pr_err("TSC Multiplier = 0x%016llx\n",
8613                        vmcs_read64(TSC_MULTIPLIER));
8614         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8615                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8616         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8617                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8618         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8619                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8620         n = vmcs_read32(CR3_TARGET_COUNT);
8621         for (i = 0; i + 1 < n; i += 4)
8622                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8623                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8624                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8625         if (i < n)
8626                 pr_err("CR3 target%u=%016lx\n",
8627                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8628         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8629                 pr_err("PLE Gap=%08x Window=%08x\n",
8630                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8631         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8632                 pr_err("Virtual processor ID = 0x%04x\n",
8633                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8634 }
8635
8636 /*
8637  * The guest has exited.  See if we can fix it or if we need userspace
8638  * assistance.
8639  */
8640 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8641 {
8642         struct vcpu_vmx *vmx = to_vmx(vcpu);
8643         u32 exit_reason = vmx->exit_reason;
8644         u32 vectoring_info = vmx->idt_vectoring_info;
8645
8646         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8647         vcpu->arch.gpa_available = false;
8648
8649         /*
8650          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8651          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8652          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8653          * mode as if vcpus is in root mode, the PML buffer must has been
8654          * flushed already.
8655          */
8656         if (enable_pml)
8657                 vmx_flush_pml_buffer(vcpu);
8658
8659         /* If guest state is invalid, start emulating */
8660         if (vmx->emulation_required)
8661                 return handle_invalid_guest_state(vcpu);
8662
8663         if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
8664                 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
8665
8666         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8667                 dump_vmcs();
8668                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8669                 vcpu->run->fail_entry.hardware_entry_failure_reason
8670                         = exit_reason;
8671                 return 0;
8672         }
8673
8674         if (unlikely(vmx->fail)) {
8675                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8676                 vcpu->run->fail_entry.hardware_entry_failure_reason
8677                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8678                 return 0;
8679         }
8680
8681         /*
8682          * Note:
8683          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8684          * delivery event since it indicates guest is accessing MMIO.
8685          * The vm-exit can be triggered again after return to guest that
8686          * will cause infinite loop.
8687          */
8688         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8689                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8690                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8691                         exit_reason != EXIT_REASON_PML_FULL &&
8692                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8693                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8694                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8695                 vcpu->run->internal.ndata = 3;
8696                 vcpu->run->internal.data[0] = vectoring_info;
8697                 vcpu->run->internal.data[1] = exit_reason;
8698                 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
8699                 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
8700                         vcpu->run->internal.ndata++;
8701                         vcpu->run->internal.data[3] =
8702                                 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
8703                 }
8704                 return 0;
8705         }
8706
8707         if (exit_reason < kvm_vmx_max_exit_handlers
8708             && kvm_vmx_exit_handlers[exit_reason])
8709                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8710         else {
8711                 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
8712                                 exit_reason);
8713                 kvm_queue_exception(vcpu, UD_VECTOR);
8714                 return 1;
8715         }
8716 }
8717
8718 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8719 {
8720         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8721
8722         if (is_guest_mode(vcpu) &&
8723                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8724                 return;
8725
8726         if (irr == -1 || tpr < irr) {
8727                 vmcs_write32(TPR_THRESHOLD, 0);
8728                 return;
8729         }
8730
8731         vmcs_write32(TPR_THRESHOLD, irr);
8732 }
8733
8734 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8735 {
8736         u32 sec_exec_control;
8737
8738         /* Postpone execution until vmcs01 is the current VMCS. */
8739         if (is_guest_mode(vcpu)) {
8740                 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8741                 return;
8742         }
8743
8744         if (!cpu_has_vmx_virtualize_x2apic_mode())
8745                 return;
8746
8747         if (!cpu_need_tpr_shadow(vcpu))
8748                 return;
8749
8750         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8751
8752         if (set) {
8753                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8754                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8755         } else {
8756                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8757                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8758                 vmx_flush_tlb_ept_only(vcpu);
8759         }
8760         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8761
8762         vmx_set_msr_bitmap(vcpu);
8763 }
8764
8765 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8766 {
8767         struct vcpu_vmx *vmx = to_vmx(vcpu);
8768
8769         /*
8770          * Currently we do not handle the nested case where L2 has an
8771          * APIC access page of its own; that page is still pinned.
8772          * Hence, we skip the case where the VCPU is in guest mode _and_
8773          * L1 prepared an APIC access page for L2.
8774          *
8775          * For the case where L1 and L2 share the same APIC access page
8776          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8777          * in the vmcs12), this function will only update either the vmcs01
8778          * or the vmcs02.  If the former, the vmcs02 will be updated by
8779          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8780          * the next L2->L1 exit.
8781          */
8782         if (!is_guest_mode(vcpu) ||
8783             !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
8784                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
8785                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8786                 vmx_flush_tlb_ept_only(vcpu);
8787         }
8788 }
8789
8790 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
8791 {
8792         u16 status;
8793         u8 old;
8794
8795         if (max_isr == -1)
8796                 max_isr = 0;
8797
8798         status = vmcs_read16(GUEST_INTR_STATUS);
8799         old = status >> 8;
8800         if (max_isr != old) {
8801                 status &= 0xff;
8802                 status |= max_isr << 8;
8803                 vmcs_write16(GUEST_INTR_STATUS, status);
8804         }
8805 }
8806
8807 static void vmx_set_rvi(int vector)
8808 {
8809         u16 status;
8810         u8 old;
8811
8812         if (vector == -1)
8813                 vector = 0;
8814
8815         status = vmcs_read16(GUEST_INTR_STATUS);
8816         old = (u8)status & 0xff;
8817         if ((u8)vector != old) {
8818                 status &= ~0xff;
8819                 status |= (u8)vector;
8820                 vmcs_write16(GUEST_INTR_STATUS, status);
8821         }
8822 }
8823
8824 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8825 {
8826         if (!is_guest_mode(vcpu)) {
8827                 vmx_set_rvi(max_irr);
8828                 return;
8829         }
8830
8831         if (max_irr == -1)
8832                 return;
8833
8834         /*
8835          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8836          * handles it.
8837          */
8838         if (nested_exit_on_intr(vcpu))
8839                 return;
8840
8841         /*
8842          * Else, fall back to pre-APICv interrupt injection since L2
8843          * is run without virtual interrupt delivery.
8844          */
8845         if (!kvm_event_needs_reinjection(vcpu) &&
8846             vmx_interrupt_allowed(vcpu)) {
8847                 kvm_queue_interrupt(vcpu, max_irr, false);
8848                 vmx_inject_irq(vcpu);
8849         }
8850 }
8851
8852 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
8853 {
8854         struct vcpu_vmx *vmx = to_vmx(vcpu);
8855         int max_irr;
8856
8857         WARN_ON(!vcpu->arch.apicv_active);
8858         if (pi_test_on(&vmx->pi_desc)) {
8859                 pi_clear_on(&vmx->pi_desc);
8860                 /*
8861                  * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8862                  * But on x86 this is just a compiler barrier anyway.
8863                  */
8864                 smp_mb__after_atomic();
8865                 max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
8866         } else {
8867                 max_irr = kvm_lapic_find_highest_irr(vcpu);
8868         }
8869         vmx_hwapic_irr_update(vcpu, max_irr);
8870         return max_irr;
8871 }
8872
8873 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8874 {
8875         if (!kvm_vcpu_apicv_active(vcpu))
8876                 return;
8877
8878         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8879         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8880         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8881         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8882 }
8883
8884 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
8885 {
8886         struct vcpu_vmx *vmx = to_vmx(vcpu);
8887
8888         pi_clear_on(&vmx->pi_desc);
8889         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
8890 }
8891
8892 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8893 {
8894         u32 exit_intr_info = 0;
8895         u16 basic_exit_reason = (u16)vmx->exit_reason;
8896
8897         if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8898               || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI))
8899                 return;
8900
8901         if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
8902                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8903         vmx->exit_intr_info = exit_intr_info;
8904
8905         /* if exit due to PF check for async PF */
8906         if (is_page_fault(exit_intr_info))
8907                 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
8908
8909         /* Handle machine checks before interrupts are enabled */
8910         if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY ||
8911             is_machine_check(exit_intr_info))
8912                 kvm_machine_check();
8913
8914         /* We need to handle NMIs before interrupts are enabled */
8915         if (is_nmi(exit_intr_info)) {
8916                 kvm_before_handle_nmi(&vmx->vcpu);
8917                 asm("int $2");
8918                 kvm_after_handle_nmi(&vmx->vcpu);
8919         }
8920 }
8921
8922 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8923 {
8924         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8925         register void *__sp asm(_ASM_SP);
8926
8927         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8928                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8929                 unsigned int vector;
8930                 unsigned long entry;
8931                 gate_desc *desc;
8932                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8933 #ifdef CONFIG_X86_64
8934                 unsigned long tmp;
8935 #endif
8936
8937                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8938                 desc = (gate_desc *)vmx->host_idt_base + vector;
8939                 entry = gate_offset(*desc);
8940                 asm volatile(
8941 #ifdef CONFIG_X86_64
8942                         "mov %%" _ASM_SP ", %[sp]\n\t"
8943                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8944                         "push $%c[ss]\n\t"
8945                         "push %[sp]\n\t"
8946 #endif
8947                         "pushf\n\t"
8948                         __ASM_SIZE(push) " $%c[cs]\n\t"
8949                         "call *%[entry]\n\t"
8950                         :
8951 #ifdef CONFIG_X86_64
8952                         [sp]"=&r"(tmp),
8953 #endif
8954                         "+r"(__sp)
8955                         :
8956                         [entry]"r"(entry),
8957                         [ss]"i"(__KERNEL_DS),
8958                         [cs]"i"(__KERNEL_CS)
8959                         );
8960         }
8961 }
8962 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
8963
8964 static bool vmx_has_high_real_mode_segbase(void)
8965 {
8966         return enable_unrestricted_guest || emulate_invalid_guest_state;
8967 }
8968
8969 static bool vmx_mpx_supported(void)
8970 {
8971         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8972                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8973 }
8974
8975 static bool vmx_xsaves_supported(void)
8976 {
8977         return vmcs_config.cpu_based_2nd_exec_ctrl &
8978                 SECONDARY_EXEC_XSAVES;
8979 }
8980
8981 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8982 {
8983         u32 exit_intr_info;
8984         bool unblock_nmi;
8985         u8 vector;
8986         bool idtv_info_valid;
8987
8988         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8989
8990         if (vmx->loaded_vmcs->nmi_known_unmasked)
8991                 return;
8992         /*
8993          * Can't use vmx->exit_intr_info since we're not sure what
8994          * the exit reason is.
8995          */
8996         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8997         unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8998         vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8999         /*
9000          * SDM 3: 27.7.1.2 (September 2008)
9001          * Re-set bit "block by NMI" before VM entry if vmexit caused by
9002          * a guest IRET fault.
9003          * SDM 3: 23.2.2 (September 2008)
9004          * Bit 12 is undefined in any of the following cases:
9005          *  If the VM exit sets the valid bit in the IDT-vectoring
9006          *   information field.
9007          *  If the VM exit is due to a double fault.
9008          */
9009         if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
9010             vector != DF_VECTOR && !idtv_info_valid)
9011                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
9012                               GUEST_INTR_STATE_NMI);
9013         else
9014                 vmx->loaded_vmcs->nmi_known_unmasked =
9015                         !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
9016                           & GUEST_INTR_STATE_NMI);
9017 }
9018
9019 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
9020                                       u32 idt_vectoring_info,
9021                                       int instr_len_field,
9022                                       int error_code_field)
9023 {
9024         u8 vector;
9025         int type;
9026         bool idtv_info_valid;
9027
9028         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
9029
9030         vcpu->arch.nmi_injected = false;
9031         kvm_clear_exception_queue(vcpu);
9032         kvm_clear_interrupt_queue(vcpu);
9033
9034         if (!idtv_info_valid)
9035                 return;
9036
9037         kvm_make_request(KVM_REQ_EVENT, vcpu);
9038
9039         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
9040         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
9041
9042         switch (type) {
9043         case INTR_TYPE_NMI_INTR:
9044                 vcpu->arch.nmi_injected = true;
9045                 /*
9046                  * SDM 3: 27.7.1.2 (September 2008)
9047                  * Clear bit "block by NMI" before VM entry if a NMI
9048                  * delivery faulted.
9049                  */
9050                 vmx_set_nmi_mask(vcpu, false);
9051                 break;
9052         case INTR_TYPE_SOFT_EXCEPTION:
9053                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
9054                 /* fall through */
9055         case INTR_TYPE_HARD_EXCEPTION:
9056                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
9057                         u32 err = vmcs_read32(error_code_field);
9058                         kvm_requeue_exception_e(vcpu, vector, err);
9059                 } else
9060                         kvm_requeue_exception(vcpu, vector);
9061                 break;
9062         case INTR_TYPE_SOFT_INTR:
9063                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
9064                 /* fall through */
9065         case INTR_TYPE_EXT_INTR:
9066                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
9067                 break;
9068         default:
9069                 break;
9070         }
9071 }
9072
9073 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
9074 {
9075         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
9076                                   VM_EXIT_INSTRUCTION_LEN,
9077                                   IDT_VECTORING_ERROR_CODE);
9078 }
9079
9080 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
9081 {
9082         __vmx_complete_interrupts(vcpu,
9083                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
9084                                   VM_ENTRY_INSTRUCTION_LEN,
9085                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
9086
9087         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
9088 }
9089
9090 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
9091 {
9092         int i, nr_msrs;
9093         struct perf_guest_switch_msr *msrs;
9094
9095         msrs = perf_guest_get_msrs(&nr_msrs);
9096
9097         if (!msrs)
9098                 return;
9099
9100         for (i = 0; i < nr_msrs; i++)
9101                 if (msrs[i].host == msrs[i].guest)
9102                         clear_atomic_switch_msr(vmx, msrs[i].msr);
9103                 else
9104                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
9105                                         msrs[i].host);
9106 }
9107
9108 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
9109 {
9110         struct vcpu_vmx *vmx = to_vmx(vcpu);
9111         u64 tscl;
9112         u32 delta_tsc;
9113
9114         if (vmx->hv_deadline_tsc == -1)
9115                 return;
9116
9117         tscl = rdtsc();
9118         if (vmx->hv_deadline_tsc > tscl)
9119                 /* sure to be 32 bit only because checked on set_hv_timer */
9120                 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
9121                         cpu_preemption_timer_multi);
9122         else
9123                 delta_tsc = 0;
9124
9125         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
9126 }
9127
9128 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
9129 {
9130         struct vcpu_vmx *vmx = to_vmx(vcpu);
9131         unsigned long debugctlmsr, cr3, cr4;
9132
9133         /* Don't enter VMX if guest state is invalid, let the exit handler
9134            start emulation until we arrive back to a valid state */
9135         if (vmx->emulation_required)
9136                 return;
9137
9138         if (vmx->ple_window_dirty) {
9139                 vmx->ple_window_dirty = false;
9140                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
9141         }
9142
9143         if (vmx->nested.sync_shadow_vmcs) {
9144                 copy_vmcs12_to_shadow(vmx);
9145                 vmx->nested.sync_shadow_vmcs = false;
9146         }
9147
9148         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
9149                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
9150         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
9151                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
9152
9153         cr3 = __get_current_cr3_fast();
9154         if (unlikely(cr3 != vmx->host_state.vmcs_host_cr3)) {
9155                 vmcs_writel(HOST_CR3, cr3);
9156                 vmx->host_state.vmcs_host_cr3 = cr3;
9157         }
9158
9159         cr4 = cr4_read_shadow();
9160         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
9161                 vmcs_writel(HOST_CR4, cr4);
9162                 vmx->host_state.vmcs_host_cr4 = cr4;
9163         }
9164
9165         /* When single-stepping over STI and MOV SS, we must clear the
9166          * corresponding interruptibility bits in the guest state. Otherwise
9167          * vmentry fails as it then expects bit 14 (BS) in pending debug
9168          * exceptions being set, but that's not correct for the guest debugging
9169          * case. */
9170         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9171                 vmx_set_interrupt_shadow(vcpu, 0);
9172
9173         if (vmx->guest_pkru_valid)
9174                 __write_pkru(vmx->guest_pkru);
9175
9176         atomic_switch_perf_msrs(vmx);
9177         debugctlmsr = get_debugctlmsr();
9178
9179         vmx_arm_hv_timer(vcpu);
9180
9181         vmx->__launched = vmx->loaded_vmcs->launched;
9182         asm(
9183                 /* Store host registers */
9184                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
9185                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
9186                 "push %%" _ASM_CX " \n\t"
9187                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
9188                 "je 1f \n\t"
9189                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
9190                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
9191                 "1: \n\t"
9192                 /* Reload cr2 if changed */
9193                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
9194                 "mov %%cr2, %%" _ASM_DX " \n\t"
9195                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
9196                 "je 2f \n\t"
9197                 "mov %%" _ASM_AX", %%cr2 \n\t"
9198                 "2: \n\t"
9199                 /* Check if vmlaunch of vmresume is needed */
9200                 "cmpl $0, %c[launched](%0) \n\t"
9201                 /* Load guest registers.  Don't clobber flags. */
9202                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
9203                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
9204                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
9205                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
9206                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
9207                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
9208 #ifdef CONFIG_X86_64
9209                 "mov %c[r8](%0),  %%r8  \n\t"
9210                 "mov %c[r9](%0),  %%r9  \n\t"
9211                 "mov %c[r10](%0), %%r10 \n\t"
9212                 "mov %c[r11](%0), %%r11 \n\t"
9213                 "mov %c[r12](%0), %%r12 \n\t"
9214                 "mov %c[r13](%0), %%r13 \n\t"
9215                 "mov %c[r14](%0), %%r14 \n\t"
9216                 "mov %c[r15](%0), %%r15 \n\t"
9217 #endif
9218                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
9219
9220                 /* Enter guest mode */
9221                 "jne 1f \n\t"
9222                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
9223                 "jmp 2f \n\t"
9224                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
9225                 "2: "
9226                 /* Save guest registers, load host registers, keep flags */
9227                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
9228                 "pop %0 \n\t"
9229                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
9230                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
9231                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
9232                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
9233                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
9234                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
9235                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
9236 #ifdef CONFIG_X86_64
9237                 "mov %%r8,  %c[r8](%0) \n\t"
9238                 "mov %%r9,  %c[r9](%0) \n\t"
9239                 "mov %%r10, %c[r10](%0) \n\t"
9240                 "mov %%r11, %c[r11](%0) \n\t"
9241                 "mov %%r12, %c[r12](%0) \n\t"
9242                 "mov %%r13, %c[r13](%0) \n\t"
9243                 "mov %%r14, %c[r14](%0) \n\t"
9244                 "mov %%r15, %c[r15](%0) \n\t"
9245 #endif
9246                 "mov %%cr2, %%" _ASM_AX "   \n\t"
9247                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
9248
9249                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
9250                 "setbe %c[fail](%0) \n\t"
9251                 ".pushsection .rodata \n\t"
9252                 ".global vmx_return \n\t"
9253                 "vmx_return: " _ASM_PTR " 2b \n\t"
9254                 ".popsection"
9255               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
9256                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
9257                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
9258                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
9259                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
9260                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
9261                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
9262                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
9263                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
9264                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
9265                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
9266 #ifdef CONFIG_X86_64
9267                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
9268                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
9269                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
9270                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
9271                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
9272                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
9273                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
9274                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
9275 #endif
9276                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
9277                 [wordsize]"i"(sizeof(ulong))
9278               : "cc", "memory"
9279 #ifdef CONFIG_X86_64
9280                 , "rax", "rbx", "rdi", "rsi"
9281                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9282 #else
9283                 , "eax", "ebx", "edi", "esi"
9284 #endif
9285               );
9286
9287         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9288         if (debugctlmsr)
9289                 update_debugctlmsr(debugctlmsr);
9290
9291 #ifndef CONFIG_X86_64
9292         /*
9293          * The sysexit path does not restore ds/es, so we must set them to
9294          * a reasonable value ourselves.
9295          *
9296          * We can't defer this to vmx_load_host_state() since that function
9297          * may be executed in interrupt context, which saves and restore segments
9298          * around it, nullifying its effect.
9299          */
9300         loadsegment(ds, __USER_DS);
9301         loadsegment(es, __USER_DS);
9302 #endif
9303
9304         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
9305                                   | (1 << VCPU_EXREG_RFLAGS)
9306                                   | (1 << VCPU_EXREG_PDPTR)
9307                                   | (1 << VCPU_EXREG_SEGMENTS)
9308                                   | (1 << VCPU_EXREG_CR3));
9309         vcpu->arch.regs_dirty = 0;
9310
9311         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9312
9313         vmx->loaded_vmcs->launched = 1;
9314
9315         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
9316
9317         /*
9318          * eager fpu is enabled if PKEY is supported and CR4 is switched
9319          * back on host, so it is safe to read guest PKRU from current
9320          * XSAVE.
9321          */
9322         if (boot_cpu_has(X86_FEATURE_OSPKE)) {
9323                 vmx->guest_pkru = __read_pkru();
9324                 if (vmx->guest_pkru != vmx->host_pkru) {
9325                         vmx->guest_pkru_valid = true;
9326                         __write_pkru(vmx->host_pkru);
9327                 } else
9328                         vmx->guest_pkru_valid = false;
9329         }
9330
9331         /*
9332          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9333          * we did not inject a still-pending event to L1 now because of
9334          * nested_run_pending, we need to re-enable this bit.
9335          */
9336         if (vmx->nested.nested_run_pending)
9337                 kvm_make_request(KVM_REQ_EVENT, vcpu);
9338
9339         vmx->nested.nested_run_pending = 0;
9340
9341         vmx_complete_atomic_exit(vmx);
9342         vmx_recover_nmi_blocking(vmx);
9343         vmx_complete_interrupts(vmx);
9344 }
9345 STACK_FRAME_NON_STANDARD(vmx_vcpu_run);
9346
9347 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
9348 {
9349         struct vcpu_vmx *vmx = to_vmx(vcpu);
9350         int cpu;
9351
9352         if (vmx->loaded_vmcs == vmcs)
9353                 return;
9354
9355         cpu = get_cpu();
9356         vmx->loaded_vmcs = vmcs;
9357         vmx_vcpu_put(vcpu);
9358         vmx_vcpu_load(vcpu, cpu);
9359         vcpu->cpu = cpu;
9360         put_cpu();
9361 }
9362
9363 /*
9364  * Ensure that the current vmcs of the logical processor is the
9365  * vmcs01 of the vcpu before calling free_nested().
9366  */
9367 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9368 {
9369        struct vcpu_vmx *vmx = to_vmx(vcpu);
9370        int r;
9371
9372        r = vcpu_load(vcpu);
9373        BUG_ON(r);
9374        vmx_switch_vmcs(vcpu, &vmx->vmcs01);
9375        free_nested(vmx);
9376        vcpu_put(vcpu);
9377 }
9378
9379 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9380 {
9381         struct vcpu_vmx *vmx = to_vmx(vcpu);
9382
9383         if (enable_pml)
9384                 vmx_destroy_pml_buffer(vmx);
9385         free_vpid(vmx->vpid);
9386         leave_guest_mode(vcpu);
9387         vmx_free_vcpu_nested(vcpu);
9388         free_loaded_vmcs(vmx->loaded_vmcs);
9389         kfree(vmx->guest_msrs);
9390         kvm_vcpu_uninit(vcpu);
9391         kmem_cache_free(kvm_vcpu_cache, vmx);
9392 }
9393
9394 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9395 {
9396         int err;
9397         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9398         int cpu;
9399
9400         if (!vmx)
9401                 return ERR_PTR(-ENOMEM);
9402
9403         vmx->vpid = allocate_vpid();
9404
9405         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9406         if (err)
9407                 goto free_vcpu;
9408
9409         err = -ENOMEM;
9410
9411         /*
9412          * If PML is turned on, failure on enabling PML just results in failure
9413          * of creating the vcpu, therefore we can simplify PML logic (by
9414          * avoiding dealing with cases, such as enabling PML partially on vcpus
9415          * for the guest, etc.
9416          */
9417         if (enable_pml) {
9418                 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9419                 if (!vmx->pml_pg)
9420                         goto uninit_vcpu;
9421         }
9422
9423         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
9424         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9425                      > PAGE_SIZE);
9426
9427         if (!vmx->guest_msrs)
9428                 goto free_pml;
9429
9430         vmx->loaded_vmcs = &vmx->vmcs01;
9431         vmx->loaded_vmcs->vmcs = alloc_vmcs();
9432         vmx->loaded_vmcs->shadow_vmcs = NULL;
9433         if (!vmx->loaded_vmcs->vmcs)
9434                 goto free_msrs;
9435         loaded_vmcs_init(vmx->loaded_vmcs);
9436
9437         cpu = get_cpu();
9438         vmx_vcpu_load(&vmx->vcpu, cpu);
9439         vmx->vcpu.cpu = cpu;
9440         err = vmx_vcpu_setup(vmx);
9441         vmx_vcpu_put(&vmx->vcpu);
9442         put_cpu();
9443         if (err)
9444                 goto free_vmcs;
9445         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9446                 err = alloc_apic_access_page(kvm);
9447                 if (err)
9448                         goto free_vmcs;
9449         }
9450
9451         if (enable_ept) {
9452                 if (!kvm->arch.ept_identity_map_addr)
9453                         kvm->arch.ept_identity_map_addr =
9454                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
9455                 err = init_rmode_identity_map(kvm);
9456                 if (err)
9457                         goto free_vmcs;
9458         }
9459
9460         if (nested) {
9461                 nested_vmx_setup_ctls_msrs(vmx);
9462                 vmx->nested.vpid02 = allocate_vpid();
9463         }
9464
9465         vmx->nested.posted_intr_nv = -1;
9466         vmx->nested.current_vmptr = -1ull;
9467
9468         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9469
9470         return &vmx->vcpu;
9471
9472 free_vmcs:
9473         free_vpid(vmx->nested.vpid02);
9474         free_loaded_vmcs(vmx->loaded_vmcs);
9475 free_msrs:
9476         kfree(vmx->guest_msrs);
9477 free_pml:
9478         vmx_destroy_pml_buffer(vmx);
9479 uninit_vcpu:
9480         kvm_vcpu_uninit(&vmx->vcpu);
9481 free_vcpu:
9482         free_vpid(vmx->vpid);
9483         kmem_cache_free(kvm_vcpu_cache, vmx);
9484         return ERR_PTR(err);
9485 }
9486
9487 static void __init vmx_check_processor_compat(void *rtn)
9488 {
9489         struct vmcs_config vmcs_conf;
9490
9491         *(int *)rtn = 0;
9492         if (setup_vmcs_config(&vmcs_conf) < 0)
9493                 *(int *)rtn = -EIO;
9494         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9495                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9496                                 smp_processor_id());
9497                 *(int *)rtn = -EIO;
9498         }
9499 }
9500
9501 static int get_ept_level(void)
9502 {
9503         return VMX_EPT_DEFAULT_GAW + 1;
9504 }
9505
9506 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
9507 {
9508         u8 cache;
9509         u64 ipat = 0;
9510
9511         /* For VT-d and EPT combination
9512          * 1. MMIO: always map as UC
9513          * 2. EPT with VT-d:
9514          *   a. VT-d without snooping control feature: can't guarantee the
9515          *      result, try to trust guest.
9516          *   b. VT-d with snooping control feature: snooping control feature of
9517          *      VT-d engine can guarantee the cache correctness. Just set it
9518          *      to WB to keep consistent with host. So the same as item 3.
9519          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9520          *    consistent with host MTRR
9521          */
9522         if (is_mmio) {
9523                 cache = MTRR_TYPE_UNCACHABLE;
9524                 goto exit;
9525         }
9526
9527         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9528                 ipat = VMX_EPT_IPAT_BIT;
9529                 cache = MTRR_TYPE_WRBACK;
9530                 goto exit;
9531         }
9532
9533         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9534                 ipat = VMX_EPT_IPAT_BIT;
9535                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9536                         cache = MTRR_TYPE_WRBACK;
9537                 else
9538                         cache = MTRR_TYPE_UNCACHABLE;
9539                 goto exit;
9540         }
9541
9542         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9543
9544 exit:
9545         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9546 }
9547
9548 static int vmx_get_lpage_level(void)
9549 {
9550         if (enable_ept && !cpu_has_vmx_ept_1g_page())
9551                 return PT_DIRECTORY_LEVEL;
9552         else
9553                 /* For shadow and EPT supported 1GB page */
9554                 return PT_PDPE_LEVEL;
9555 }
9556
9557 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9558 {
9559         /*
9560          * These bits in the secondary execution controls field
9561          * are dynamic, the others are mostly based on the hypervisor
9562          * architecture and the guest's CPUID.  Do not touch the
9563          * dynamic bits.
9564          */
9565         u32 mask =
9566                 SECONDARY_EXEC_SHADOW_VMCS |
9567                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9568                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9569
9570         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9571
9572         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9573                      (new_ctl & ~mask) | (cur_ctl & mask));
9574 }
9575
9576 /*
9577  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9578  * (indicating "allowed-1") if they are supported in the guest's CPUID.
9579  */
9580 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
9581 {
9582         struct vcpu_vmx *vmx = to_vmx(vcpu);
9583         struct kvm_cpuid_entry2 *entry;
9584
9585         vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff;
9586         vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE;
9587
9588 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
9589         if (entry && (entry->_reg & (_cpuid_mask)))                     \
9590                 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask);       \
9591 } while (0)
9592
9593         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
9594         cr4_fixed1_update(X86_CR4_VME,        edx, bit(X86_FEATURE_VME));
9595         cr4_fixed1_update(X86_CR4_PVI,        edx, bit(X86_FEATURE_VME));
9596         cr4_fixed1_update(X86_CR4_TSD,        edx, bit(X86_FEATURE_TSC));
9597         cr4_fixed1_update(X86_CR4_DE,         edx, bit(X86_FEATURE_DE));
9598         cr4_fixed1_update(X86_CR4_PSE,        edx, bit(X86_FEATURE_PSE));
9599         cr4_fixed1_update(X86_CR4_PAE,        edx, bit(X86_FEATURE_PAE));
9600         cr4_fixed1_update(X86_CR4_MCE,        edx, bit(X86_FEATURE_MCE));
9601         cr4_fixed1_update(X86_CR4_PGE,        edx, bit(X86_FEATURE_PGE));
9602         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, bit(X86_FEATURE_FXSR));
9603         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
9604         cr4_fixed1_update(X86_CR4_VMXE,       ecx, bit(X86_FEATURE_VMX));
9605         cr4_fixed1_update(X86_CR4_SMXE,       ecx, bit(X86_FEATURE_SMX));
9606         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, bit(X86_FEATURE_PCID));
9607         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, bit(X86_FEATURE_XSAVE));
9608
9609         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9610         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, bit(X86_FEATURE_FSGSBASE));
9611         cr4_fixed1_update(X86_CR4_SMEP,       ebx, bit(X86_FEATURE_SMEP));
9612         cr4_fixed1_update(X86_CR4_SMAP,       ebx, bit(X86_FEATURE_SMAP));
9613         cr4_fixed1_update(X86_CR4_PKE,        ecx, bit(X86_FEATURE_PKU));
9614         /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9615         cr4_fixed1_update(bit(11),            ecx, bit(2));
9616
9617 #undef cr4_fixed1_update
9618 }
9619
9620 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9621 {
9622         struct vcpu_vmx *vmx = to_vmx(vcpu);
9623         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
9624
9625         if (vmx_rdtscp_supported()) {
9626                 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
9627                 if (!rdtscp_enabled)
9628                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
9629
9630                 if (nested) {
9631                         if (rdtscp_enabled)
9632                                 vmx->nested.nested_vmx_secondary_ctls_high |=
9633                                         SECONDARY_EXEC_RDTSCP;
9634                         else
9635                                 vmx->nested.nested_vmx_secondary_ctls_high &=
9636                                         ~SECONDARY_EXEC_RDTSCP;
9637                 }
9638         }
9639
9640         if (vmx_invpcid_supported()) {
9641                 /* Exposing INVPCID only when PCID is exposed */
9642                 bool invpcid_enabled =
9643                         guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
9644                         guest_cpuid_has(vcpu, X86_FEATURE_PCID);
9645
9646                 if (!invpcid_enabled) {
9647                         secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
9648                         guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
9649                 }
9650
9651                 if (nested) {
9652                         if (invpcid_enabled)
9653                                 vmx->nested.nested_vmx_secondary_ctls_high |=
9654                                         SECONDARY_EXEC_ENABLE_INVPCID;
9655                         else
9656                                 vmx->nested.nested_vmx_secondary_ctls_high &=
9657                                         ~SECONDARY_EXEC_ENABLE_INVPCID;
9658                 }
9659         }
9660
9661         if (cpu_has_secondary_exec_ctrls())
9662                 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9663
9664         if (nested_vmx_allowed(vcpu))
9665                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9666                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9667         else
9668                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9669                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9670
9671         if (nested_vmx_allowed(vcpu))
9672                 nested_vmx_cr_fixed1_bits_update(vcpu);
9673 }
9674
9675 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9676 {
9677         if (func == 1 && nested)
9678                 entry->ecx |= bit(X86_FEATURE_VMX);
9679 }
9680
9681 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9682                 struct x86_exception *fault)
9683 {
9684         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9685         struct vcpu_vmx *vmx = to_vmx(vcpu);
9686         u32 exit_reason;
9687         unsigned long exit_qualification = vcpu->arch.exit_qualification;
9688
9689         if (vmx->nested.pml_full) {
9690                 exit_reason = EXIT_REASON_PML_FULL;
9691                 vmx->nested.pml_full = false;
9692                 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
9693         } else if (fault->error_code & PFERR_RSVD_MASK)
9694                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9695         else
9696                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9697
9698         nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification);
9699         vmcs12->guest_physical_address = fault->address;
9700 }
9701
9702 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu)
9703 {
9704         return nested_ept_get_cr3(vcpu) & VMX_EPT_AD_ENABLE_BIT;
9705 }
9706
9707 /* Callbacks for nested_ept_init_mmu_context: */
9708
9709 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9710 {
9711         /* return the page table to be shadowed - in our case, EPT12 */
9712         return get_vmcs12(vcpu)->ept_pointer;
9713 }
9714
9715 static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9716 {
9717         WARN_ON(mmu_is_nested(vcpu));
9718         if (!valid_ept_address(vcpu, nested_ept_get_cr3(vcpu)))
9719                 return 1;
9720
9721         kvm_mmu_unload(vcpu);
9722         kvm_init_shadow_ept_mmu(vcpu,
9723                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9724                         VMX_EPT_EXECUTE_ONLY_BIT,
9725                         nested_ept_ad_enabled(vcpu));
9726         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9727         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9728         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9729
9730         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9731         return 0;
9732 }
9733
9734 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9735 {
9736         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9737 }
9738
9739 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9740                                             u16 error_code)
9741 {
9742         bool inequality, bit;
9743
9744         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9745         inequality =
9746                 (error_code & vmcs12->page_fault_error_code_mask) !=
9747                  vmcs12->page_fault_error_code_match;
9748         return inequality ^ bit;
9749 }
9750
9751 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9752                 struct x86_exception *fault)
9753 {
9754         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9755
9756         WARN_ON(!is_guest_mode(vcpu));
9757
9758         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code)) {
9759                 vmcs12->vm_exit_intr_error_code = fault->error_code;
9760                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
9761                                   PF_VECTOR | INTR_TYPE_HARD_EXCEPTION |
9762                                   INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK,
9763                                   fault->address);
9764         } else {
9765                 kvm_inject_page_fault(vcpu, fault);
9766         }
9767 }
9768
9769 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9770                                                struct vmcs12 *vmcs12);
9771
9772 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9773                                         struct vmcs12 *vmcs12)
9774 {
9775         struct vcpu_vmx *vmx = to_vmx(vcpu);
9776         struct page *page;
9777         u64 hpa;
9778
9779         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9780                 /*
9781                  * Translate L1 physical address to host physical
9782                  * address for vmcs02. Keep the page pinned, so this
9783                  * physical address remains valid. We keep a reference
9784                  * to it so we can release it later.
9785                  */
9786                 if (vmx->nested.apic_access_page) { /* shouldn't happen */
9787                         kvm_release_page_dirty(vmx->nested.apic_access_page);
9788                         vmx->nested.apic_access_page = NULL;
9789                 }
9790                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->apic_access_addr);
9791                 /*
9792                  * If translation failed, no matter: This feature asks
9793                  * to exit when accessing the given address, and if it
9794                  * can never be accessed, this feature won't do
9795                  * anything anyway.
9796                  */
9797                 if (!is_error_page(page)) {
9798                         vmx->nested.apic_access_page = page;
9799                         hpa = page_to_phys(vmx->nested.apic_access_page);
9800                         vmcs_write64(APIC_ACCESS_ADDR, hpa);
9801                 } else {
9802                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
9803                                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9804                 }
9805         } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9806                    cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9807                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
9808                               SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9809                 kvm_vcpu_reload_apic_access_page(vcpu);
9810         }
9811
9812         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9813                 if (vmx->nested.virtual_apic_page) { /* shouldn't happen */
9814                         kvm_release_page_dirty(vmx->nested.virtual_apic_page);
9815                         vmx->nested.virtual_apic_page = NULL;
9816                 }
9817                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->virtual_apic_page_addr);
9818
9819                 /*
9820                  * If translation failed, VM entry will fail because
9821                  * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9822                  * Failing the vm entry is _not_ what the processor
9823                  * does but it's basically the only possibility we
9824                  * have.  We could still enter the guest if CR8 load
9825                  * exits are enabled, CR8 store exits are enabled, and
9826                  * virtualize APIC access is disabled; in this case
9827                  * the processor would never use the TPR shadow and we
9828                  * could simply clear the bit from the execution
9829                  * control.  But such a configuration is useless, so
9830                  * let's keep the code simple.
9831                  */
9832                 if (!is_error_page(page)) {
9833                         vmx->nested.virtual_apic_page = page;
9834                         hpa = page_to_phys(vmx->nested.virtual_apic_page);
9835                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
9836                 }
9837         }
9838
9839         if (nested_cpu_has_posted_intr(vmcs12)) {
9840                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9841                         kunmap(vmx->nested.pi_desc_page);
9842                         kvm_release_page_dirty(vmx->nested.pi_desc_page);
9843                         vmx->nested.pi_desc_page = NULL;
9844                 }
9845                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->posted_intr_desc_addr);
9846                 if (is_error_page(page))
9847                         return;
9848                 vmx->nested.pi_desc_page = page;
9849                 vmx->nested.pi_desc = kmap(vmx->nested.pi_desc_page);
9850                 vmx->nested.pi_desc =
9851                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9852                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9853                         (PAGE_SIZE - 1)));
9854                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9855                         page_to_phys(vmx->nested.pi_desc_page) +
9856                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9857                         (PAGE_SIZE - 1)));
9858         }
9859         if (cpu_has_vmx_msr_bitmap() &&
9860             nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) &&
9861             nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
9862                 ;
9863         else
9864                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
9865                                 CPU_BASED_USE_MSR_BITMAPS);
9866 }
9867
9868 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9869 {
9870         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9871         struct vcpu_vmx *vmx = to_vmx(vcpu);
9872
9873         if (vcpu->arch.virtual_tsc_khz == 0)
9874                 return;
9875
9876         /* Make sure short timeouts reliably trigger an immediate vmexit.
9877          * hrtimer_start does not guarantee this. */
9878         if (preemption_timeout <= 1) {
9879                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9880                 return;
9881         }
9882
9883         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9884         preemption_timeout *= 1000000;
9885         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9886         hrtimer_start(&vmx->nested.preemption_timer,
9887                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9888 }
9889
9890 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu,
9891                                                struct vmcs12 *vmcs12)
9892 {
9893         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
9894                 return 0;
9895
9896         if (!page_address_valid(vcpu, vmcs12->io_bitmap_a) ||
9897             !page_address_valid(vcpu, vmcs12->io_bitmap_b))
9898                 return -EINVAL;
9899
9900         return 0;
9901 }
9902
9903 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9904                                                 struct vmcs12 *vmcs12)
9905 {
9906         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9907                 return 0;
9908
9909         if (!page_address_valid(vcpu, vmcs12->msr_bitmap))
9910                 return -EINVAL;
9911
9912         return 0;
9913 }
9914
9915 /*
9916  * Merge L0's and L1's MSR bitmap, return false to indicate that
9917  * we do not use the hardware.
9918  */
9919 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9920                                                struct vmcs12 *vmcs12)
9921 {
9922         int msr;
9923         struct page *page;
9924         unsigned long *msr_bitmap_l1;
9925         unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap;
9926
9927         /* This shortcut is ok because we support only x2APIC MSRs so far. */
9928         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9929                 return false;
9930
9931         page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->msr_bitmap);
9932         if (is_error_page(page))
9933                 return false;
9934         msr_bitmap_l1 = (unsigned long *)kmap(page);
9935
9936         memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
9937
9938         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9939                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9940                         for (msr = 0x800; msr <= 0x8ff; msr++)
9941                                 nested_vmx_disable_intercept_for_msr(
9942                                         msr_bitmap_l1, msr_bitmap_l0,
9943                                         msr, MSR_TYPE_R);
9944
9945                 nested_vmx_disable_intercept_for_msr(
9946                                 msr_bitmap_l1, msr_bitmap_l0,
9947                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9948                                 MSR_TYPE_R | MSR_TYPE_W);
9949
9950                 if (nested_cpu_has_vid(vmcs12)) {
9951                         nested_vmx_disable_intercept_for_msr(
9952                                 msr_bitmap_l1, msr_bitmap_l0,
9953                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9954                                 MSR_TYPE_W);
9955                         nested_vmx_disable_intercept_for_msr(
9956                                 msr_bitmap_l1, msr_bitmap_l0,
9957                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9958                                 MSR_TYPE_W);
9959                 }
9960         }
9961         kunmap(page);
9962         kvm_release_page_clean(page);
9963
9964         return true;
9965 }
9966
9967 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9968                                            struct vmcs12 *vmcs12)
9969 {
9970         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9971             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9972             !nested_cpu_has_vid(vmcs12) &&
9973             !nested_cpu_has_posted_intr(vmcs12))
9974                 return 0;
9975
9976         /*
9977          * If virtualize x2apic mode is enabled,
9978          * virtualize apic access must be disabled.
9979          */
9980         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9981             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9982                 return -EINVAL;
9983
9984         /*
9985          * If virtual interrupt delivery is enabled,
9986          * we must exit on external interrupts.
9987          */
9988         if (nested_cpu_has_vid(vmcs12) &&
9989            !nested_exit_on_intr(vcpu))
9990                 return -EINVAL;
9991
9992         /*
9993          * bits 15:8 should be zero in posted_intr_nv,
9994          * the descriptor address has been already checked
9995          * in nested_get_vmcs12_pages.
9996          */
9997         if (nested_cpu_has_posted_intr(vmcs12) &&
9998            (!nested_cpu_has_vid(vmcs12) ||
9999             !nested_exit_intr_ack_set(vcpu) ||
10000             vmcs12->posted_intr_nv & 0xff00))
10001                 return -EINVAL;
10002
10003         /* tpr shadow is needed by all apicv features. */
10004         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
10005                 return -EINVAL;
10006
10007         return 0;
10008 }
10009
10010 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
10011                                        unsigned long count_field,
10012                                        unsigned long addr_field)
10013 {
10014         int maxphyaddr;
10015         u64 count, addr;
10016
10017         if (vmcs12_read_any(vcpu, count_field, &count) ||
10018             vmcs12_read_any(vcpu, addr_field, &addr)) {
10019                 WARN_ON(1);
10020                 return -EINVAL;
10021         }
10022         if (count == 0)
10023                 return 0;
10024         maxphyaddr = cpuid_maxphyaddr(vcpu);
10025         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
10026             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
10027                 pr_debug_ratelimited(
10028                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
10029                         addr_field, maxphyaddr, count, addr);
10030                 return -EINVAL;
10031         }
10032         return 0;
10033 }
10034
10035 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
10036                                                 struct vmcs12 *vmcs12)
10037 {
10038         if (vmcs12->vm_exit_msr_load_count == 0 &&
10039             vmcs12->vm_exit_msr_store_count == 0 &&
10040             vmcs12->vm_entry_msr_load_count == 0)
10041                 return 0; /* Fast path */
10042         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
10043                                         VM_EXIT_MSR_LOAD_ADDR) ||
10044             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
10045                                         VM_EXIT_MSR_STORE_ADDR) ||
10046             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
10047                                         VM_ENTRY_MSR_LOAD_ADDR))
10048                 return -EINVAL;
10049         return 0;
10050 }
10051
10052 static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
10053                                          struct vmcs12 *vmcs12)
10054 {
10055         u64 address = vmcs12->pml_address;
10056         int maxphyaddr = cpuid_maxphyaddr(vcpu);
10057
10058         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) {
10059                 if (!nested_cpu_has_ept(vmcs12) ||
10060                     !IS_ALIGNED(address, 4096)  ||
10061                     address >> maxphyaddr)
10062                         return -EINVAL;
10063         }
10064
10065         return 0;
10066 }
10067
10068 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
10069                                        struct vmx_msr_entry *e)
10070 {
10071         /* x2APIC MSR accesses are not allowed */
10072         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
10073                 return -EINVAL;
10074         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
10075             e->index == MSR_IA32_UCODE_REV)
10076                 return -EINVAL;
10077         if (e->reserved != 0)
10078                 return -EINVAL;
10079         return 0;
10080 }
10081
10082 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
10083                                      struct vmx_msr_entry *e)
10084 {
10085         if (e->index == MSR_FS_BASE ||
10086             e->index == MSR_GS_BASE ||
10087             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
10088             nested_vmx_msr_check_common(vcpu, e))
10089                 return -EINVAL;
10090         return 0;
10091 }
10092
10093 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
10094                                       struct vmx_msr_entry *e)
10095 {
10096         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
10097             nested_vmx_msr_check_common(vcpu, e))
10098                 return -EINVAL;
10099         return 0;
10100 }
10101
10102 /*
10103  * Load guest's/host's msr at nested entry/exit.
10104  * return 0 for success, entry index for failure.
10105  */
10106 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
10107 {
10108         u32 i;
10109         struct vmx_msr_entry e;
10110         struct msr_data msr;
10111
10112         msr.host_initiated = false;
10113         for (i = 0; i < count; i++) {
10114                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
10115                                         &e, sizeof(e))) {
10116                         pr_debug_ratelimited(
10117                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10118                                 __func__, i, gpa + i * sizeof(e));
10119                         goto fail;
10120                 }
10121                 if (nested_vmx_load_msr_check(vcpu, &e)) {
10122                         pr_debug_ratelimited(
10123                                 "%s check failed (%u, 0x%x, 0x%x)\n",
10124                                 __func__, i, e.index, e.reserved);
10125                         goto fail;
10126                 }
10127                 msr.index = e.index;
10128                 msr.data = e.value;
10129                 if (kvm_set_msr(vcpu, &msr)) {
10130                         pr_debug_ratelimited(
10131                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10132                                 __func__, i, e.index, e.value);
10133                         goto fail;
10134                 }
10135         }
10136         return 0;
10137 fail:
10138         return i + 1;
10139 }
10140
10141 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
10142 {
10143         u32 i;
10144         struct vmx_msr_entry e;
10145
10146         for (i = 0; i < count; i++) {
10147                 struct msr_data msr_info;
10148                 if (kvm_vcpu_read_guest(vcpu,
10149                                         gpa + i * sizeof(e),
10150                                         &e, 2 * sizeof(u32))) {
10151                         pr_debug_ratelimited(
10152                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10153                                 __func__, i, gpa + i * sizeof(e));
10154                         return -EINVAL;
10155                 }
10156                 if (nested_vmx_store_msr_check(vcpu, &e)) {
10157                         pr_debug_ratelimited(
10158                                 "%s check failed (%u, 0x%x, 0x%x)\n",
10159                                 __func__, i, e.index, e.reserved);
10160                         return -EINVAL;
10161                 }
10162                 msr_info.host_initiated = false;
10163                 msr_info.index = e.index;
10164                 if (kvm_get_msr(vcpu, &msr_info)) {
10165                         pr_debug_ratelimited(
10166                                 "%s cannot read MSR (%u, 0x%x)\n",
10167                                 __func__, i, e.index);
10168                         return -EINVAL;
10169                 }
10170                 if (kvm_vcpu_write_guest(vcpu,
10171                                          gpa + i * sizeof(e) +
10172                                              offsetof(struct vmx_msr_entry, value),
10173                                          &msr_info.data, sizeof(msr_info.data))) {
10174                         pr_debug_ratelimited(
10175                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10176                                 __func__, i, e.index, msr_info.data);
10177                         return -EINVAL;
10178                 }
10179         }
10180         return 0;
10181 }
10182
10183 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
10184 {
10185         unsigned long invalid_mask;
10186
10187         invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
10188         return (val & invalid_mask) == 0;
10189 }
10190
10191 /*
10192  * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
10193  * emulating VM entry into a guest with EPT enabled.
10194  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10195  * is assigned to entry_failure_code on failure.
10196  */
10197 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
10198                                u32 *entry_failure_code)
10199 {
10200         if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
10201                 if (!nested_cr3_valid(vcpu, cr3)) {
10202                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
10203                         return 1;
10204                 }
10205
10206                 /*
10207                  * If PAE paging and EPT are both on, CR3 is not used by the CPU and
10208                  * must not be dereferenced.
10209                  */
10210                 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
10211                     !nested_ept) {
10212                         if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
10213                                 *entry_failure_code = ENTRY_FAIL_PDPTE;
10214                                 return 1;
10215                         }
10216                 }
10217
10218                 vcpu->arch.cr3 = cr3;
10219                 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
10220         }
10221
10222         kvm_mmu_reset_context(vcpu);
10223         return 0;
10224 }
10225
10226 /*
10227  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
10228  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
10229  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
10230  * guest in a way that will both be appropriate to L1's requests, and our
10231  * needs. In addition to modifying the active vmcs (which is vmcs02), this
10232  * function also has additional necessary side-effects, like setting various
10233  * vcpu->arch fields.
10234  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10235  * is assigned to entry_failure_code on failure.
10236  */
10237 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10238                           bool from_vmentry, u32 *entry_failure_code)
10239 {
10240         struct vcpu_vmx *vmx = to_vmx(vcpu);
10241         u32 exec_control, vmcs12_exec_ctrl;
10242
10243         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
10244         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
10245         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
10246         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
10247         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
10248         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
10249         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
10250         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
10251         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
10252         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
10253         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
10254         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
10255         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
10256         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
10257         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
10258         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
10259         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
10260         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
10261         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
10262         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
10263         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
10264         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
10265         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
10266         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
10267         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
10268         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
10269         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
10270         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
10271         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
10272         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
10273         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
10274         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
10275         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
10276         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
10277         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
10278         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
10279
10280         if (from_vmentry &&
10281             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
10282                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
10283                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
10284         } else {
10285                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
10286                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
10287         }
10288         if (from_vmentry) {
10289                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
10290                              vmcs12->vm_entry_intr_info_field);
10291                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
10292                              vmcs12->vm_entry_exception_error_code);
10293                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
10294                              vmcs12->vm_entry_instruction_len);
10295                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
10296                              vmcs12->guest_interruptibility_info);
10297                 vmx->loaded_vmcs->nmi_known_unmasked =
10298                         !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI);
10299         } else {
10300                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
10301         }
10302         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
10303         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
10304         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
10305                 vmcs12->guest_pending_dbg_exceptions);
10306         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
10307         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
10308
10309         if (nested_cpu_has_xsaves(vmcs12))
10310                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
10311         vmcs_write64(VMCS_LINK_POINTER, -1ull);
10312
10313         exec_control = vmcs12->pin_based_vm_exec_control;
10314
10315         /* Preemption timer setting is only taken from vmcs01.  */
10316         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10317         exec_control |= vmcs_config.pin_based_exec_ctrl;
10318         if (vmx->hv_deadline_tsc == -1)
10319                 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10320
10321         /* Posted interrupts setting is only taken from vmcs12.  */
10322         if (nested_cpu_has_posted_intr(vmcs12)) {
10323                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
10324                 vmx->nested.pi_pending = false;
10325                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR);
10326         } else {
10327                 exec_control &= ~PIN_BASED_POSTED_INTR;
10328         }
10329
10330         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
10331
10332         vmx->nested.preemption_timer_expired = false;
10333         if (nested_cpu_has_preemption_timer(vmcs12))
10334                 vmx_start_preemption_timer(vcpu);
10335
10336         /*
10337          * Whether page-faults are trapped is determined by a combination of
10338          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10339          * If enable_ept, L0 doesn't care about page faults and we should
10340          * set all of these to L1's desires. However, if !enable_ept, L0 does
10341          * care about (at least some) page faults, and because it is not easy
10342          * (if at all possible?) to merge L0 and L1's desires, we simply ask
10343          * to exit on each and every L2 page fault. This is done by setting
10344          * MASK=MATCH=0 and (see below) EB.PF=1.
10345          * Note that below we don't need special code to set EB.PF beyond the
10346          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10347          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10348          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10349          */
10350         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10351                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10352         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10353                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10354
10355         if (cpu_has_secondary_exec_ctrls()) {
10356                 exec_control = vmx_secondary_exec_control(vmx);
10357
10358                 /* Take the following fields only from vmcs12 */
10359                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10360                                   SECONDARY_EXEC_ENABLE_INVPCID |
10361                                   SECONDARY_EXEC_RDTSCP |
10362                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
10363                                   SECONDARY_EXEC_APIC_REGISTER_VIRT |
10364                                   SECONDARY_EXEC_ENABLE_VMFUNC);
10365                 if (nested_cpu_has(vmcs12,
10366                                    CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) {
10367                         vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control &
10368                                 ~SECONDARY_EXEC_ENABLE_PML;
10369                         exec_control |= vmcs12_exec_ctrl;
10370                 }
10371
10372                 /* All VMFUNCs are currently emulated through L0 vmexits.  */
10373                 if (exec_control & SECONDARY_EXEC_ENABLE_VMFUNC)
10374                         vmcs_write64(VM_FUNCTION_CONTROL, 0);
10375
10376                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
10377                         vmcs_write64(EOI_EXIT_BITMAP0,
10378                                 vmcs12->eoi_exit_bitmap0);
10379                         vmcs_write64(EOI_EXIT_BITMAP1,
10380                                 vmcs12->eoi_exit_bitmap1);
10381                         vmcs_write64(EOI_EXIT_BITMAP2,
10382                                 vmcs12->eoi_exit_bitmap2);
10383                         vmcs_write64(EOI_EXIT_BITMAP3,
10384                                 vmcs12->eoi_exit_bitmap3);
10385                         vmcs_write16(GUEST_INTR_STATUS,
10386                                 vmcs12->guest_intr_status);
10387                 }
10388
10389                 /*
10390                  * Write an illegal value to APIC_ACCESS_ADDR. Later,
10391                  * nested_get_vmcs12_pages will either fix it up or
10392                  * remove the VM execution control.
10393                  */
10394                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
10395                         vmcs_write64(APIC_ACCESS_ADDR, -1ull);
10396
10397                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
10398         }
10399
10400
10401         /*
10402          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10403          * Some constant fields are set here by vmx_set_constant_host_state().
10404          * Other fields are different per CPU, and will be set later when
10405          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10406          */
10407         vmx_set_constant_host_state(vmx);
10408
10409         /*
10410          * Set the MSR load/store lists to match L0's settings.
10411          */
10412         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
10413         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10414         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
10415         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10416         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
10417
10418         /*
10419          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10420          * entry, but only if the current (host) sp changed from the value
10421          * we wrote last (vmx->host_rsp). This cache is no longer relevant
10422          * if we switch vmcs, and rather than hold a separate cache per vmcs,
10423          * here we just force the write to happen on entry.
10424          */
10425         vmx->host_rsp = 0;
10426
10427         exec_control = vmx_exec_control(vmx); /* L0's desires */
10428         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
10429         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
10430         exec_control &= ~CPU_BASED_TPR_SHADOW;
10431         exec_control |= vmcs12->cpu_based_vm_exec_control;
10432
10433         /*
10434          * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10435          * nested_get_vmcs12_pages can't fix it up, the illegal value
10436          * will result in a VM entry failure.
10437          */
10438         if (exec_control & CPU_BASED_TPR_SHADOW) {
10439                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
10440                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
10441         }
10442
10443         /*
10444          * Merging of IO bitmap not currently supported.
10445          * Rather, exit every time.
10446          */
10447         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
10448         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
10449
10450         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
10451
10452         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10453          * bitwise-or of what L1 wants to trap for L2, and what we want to
10454          * trap. Note that CR0.TS also needs updating - we do this later.
10455          */
10456         update_exception_bitmap(vcpu);
10457         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
10458         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10459
10460         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10461          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10462          * bits are further modified by vmx_set_efer() below.
10463          */
10464         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
10465
10466         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10467          * emulated by vmx_set_efer(), below.
10468          */
10469         vm_entry_controls_init(vmx,
10470                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10471                         ~VM_ENTRY_IA32E_MODE) |
10472                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10473
10474         if (from_vmentry &&
10475             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
10476                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
10477                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
10478         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
10479                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
10480         }
10481
10482         set_cr4_guest_host_mask(vmx);
10483
10484         if (from_vmentry &&
10485             vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
10486                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10487
10488         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10489                 vmcs_write64(TSC_OFFSET,
10490                         vcpu->arch.tsc_offset + vmcs12->tsc_offset);
10491         else
10492                 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
10493         if (kvm_has_tsc_control)
10494                 decache_tsc_multiplier(vmx);
10495
10496         if (enable_vpid) {
10497                 /*
10498                  * There is no direct mapping between vpid02 and vpid12, the
10499                  * vpid02 is per-vCPU for L0 and reused while the value of
10500                  * vpid12 is changed w/ one invvpid during nested vmentry.
10501                  * The vpid12 is allocated by L1 for L2, so it will not
10502                  * influence global bitmap(for vpid01 and vpid02 allocation)
10503                  * even if spawn a lot of nested vCPUs.
10504                  */
10505                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10506                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10507                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10508                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10509                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10510                         }
10511                 } else {
10512                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10513                         vmx_flush_tlb(vcpu);
10514                 }
10515
10516         }
10517
10518         if (enable_pml) {
10519                 /*
10520                  * Conceptually we want to copy the PML address and index from
10521                  * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10522                  * since we always flush the log on each vmexit, this happens
10523                  * to be equivalent to simply resetting the fields in vmcs02.
10524                  */
10525                 ASSERT(vmx->pml_pg);
10526                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
10527                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
10528         }
10529
10530         if (nested_cpu_has_ept(vmcs12)) {
10531                 if (nested_ept_init_mmu_context(vcpu)) {
10532                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
10533                         return 1;
10534                 }
10535         } else if (nested_cpu_has2(vmcs12,
10536                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10537                 vmx_flush_tlb_ept_only(vcpu);
10538         }
10539
10540         /*
10541          * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10542          * bits which we consider mandatory enabled.
10543          * The CR0_READ_SHADOW is what L2 should have expected to read given
10544          * the specifications by L1; It's not enough to take
10545          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10546          * have more bits than L1 expected.
10547          */
10548         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10549         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10550
10551         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10552         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10553
10554         if (from_vmentry &&
10555             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
10556                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10557         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10558                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10559         else
10560                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10561         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10562         vmx_set_efer(vcpu, vcpu->arch.efer);
10563
10564         /* Shadow page tables on either EPT or shadow page tables. */
10565         if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
10566                                 entry_failure_code))
10567                 return 1;
10568
10569         if (!enable_ept)
10570                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10571
10572         /*
10573          * L1 may access the L2's PDPTR, so save them to construct vmcs12
10574          */
10575         if (enable_ept) {
10576                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10577                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10578                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10579                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10580         }
10581
10582         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10583         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10584         return 0;
10585 }
10586
10587 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10588 {
10589         struct vcpu_vmx *vmx = to_vmx(vcpu);
10590
10591         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10592             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
10593                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10594
10595         if (nested_vmx_check_io_bitmap_controls(vcpu, vmcs12))
10596                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10597
10598         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
10599                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10600
10601         if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
10602                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10603
10604         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
10605                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10606
10607         if (nested_vmx_check_pml_controls(vcpu, vmcs12))
10608                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10609
10610         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
10611                                 vmx->nested.nested_vmx_procbased_ctls_low,
10612                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
10613             (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
10614              !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10615                                  vmx->nested.nested_vmx_secondary_ctls_low,
10616                                  vmx->nested.nested_vmx_secondary_ctls_high)) ||
10617             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
10618                                 vmx->nested.nested_vmx_pinbased_ctls_low,
10619                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
10620             !vmx_control_verify(vmcs12->vm_exit_controls,
10621                                 vmx->nested.nested_vmx_exit_ctls_low,
10622                                 vmx->nested.nested_vmx_exit_ctls_high) ||
10623             !vmx_control_verify(vmcs12->vm_entry_controls,
10624                                 vmx->nested.nested_vmx_entry_ctls_low,
10625                                 vmx->nested.nested_vmx_entry_ctls_high))
10626                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10627
10628         if (nested_cpu_has_vmfunc(vmcs12)) {
10629                 if (vmcs12->vm_function_control &
10630                     ~vmx->nested.nested_vmx_vmfunc_controls)
10631                         return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10632
10633                 if (nested_cpu_has_eptp_switching(vmcs12)) {
10634                         if (!nested_cpu_has_ept(vmcs12) ||
10635                             !page_address_valid(vcpu, vmcs12->eptp_list_address))
10636                                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10637                 }
10638         }
10639
10640         if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu))
10641                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10642
10643         if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
10644             !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
10645             !nested_cr3_valid(vcpu, vmcs12->host_cr3))
10646                 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
10647
10648         return 0;
10649 }
10650
10651 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10652                                   u32 *exit_qual)
10653 {
10654         bool ia32e;
10655
10656         *exit_qual = ENTRY_FAIL_DEFAULT;
10657
10658         if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
10659             !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
10660                 return 1;
10661
10662         if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
10663             vmcs12->vmcs_link_pointer != -1ull) {
10664                 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
10665                 return 1;
10666         }
10667
10668         /*
10669          * If the load IA32_EFER VM-entry control is 1, the following checks
10670          * are performed on the field for the IA32_EFER MSR:
10671          * - Bits reserved in the IA32_EFER MSR must be 0.
10672          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10673          *   the IA-32e mode guest VM-exit control. It must also be identical
10674          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10675          *   CR0.PG) is 1.
10676          */
10677         if (to_vmx(vcpu)->nested.nested_run_pending &&
10678             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
10679                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10680                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10681                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10682                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10683                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
10684                         return 1;
10685         }
10686
10687         /*
10688          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10689          * IA32_EFER MSR must be 0 in the field for that register. In addition,
10690          * the values of the LMA and LME bits in the field must each be that of
10691          * the host address-space size VM-exit control.
10692          */
10693         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10694                 ia32e = (vmcs12->vm_exit_controls &
10695                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10696                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10697                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10698                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
10699                         return 1;
10700         }
10701
10702         return 0;
10703 }
10704
10705 static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry)
10706 {
10707         struct vcpu_vmx *vmx = to_vmx(vcpu);
10708         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10709         struct loaded_vmcs *vmcs02;
10710         u32 msr_entry_idx;
10711         u32 exit_qual;
10712
10713         vmcs02 = nested_get_current_vmcs02(vmx);
10714         if (!vmcs02)
10715                 return -ENOMEM;
10716
10717         enter_guest_mode(vcpu);
10718
10719         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10720                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10721
10722         vmx_switch_vmcs(vcpu, vmcs02);
10723         vmx_segment_cache_clear(vmx);
10724
10725         if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) {
10726                 leave_guest_mode(vcpu);
10727                 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10728                 nested_vmx_entry_failure(vcpu, vmcs12,
10729                                          EXIT_REASON_INVALID_STATE, exit_qual);
10730                 return 1;
10731         }
10732
10733         nested_get_vmcs12_pages(vcpu, vmcs12);
10734
10735         msr_entry_idx = nested_vmx_load_msr(vcpu,
10736                                             vmcs12->vm_entry_msr_load_addr,
10737                                             vmcs12->vm_entry_msr_load_count);
10738         if (msr_entry_idx) {
10739                 leave_guest_mode(vcpu);
10740                 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10741                 nested_vmx_entry_failure(vcpu, vmcs12,
10742                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10743                 return 1;
10744         }
10745
10746         /*
10747          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10748          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10749          * returned as far as L1 is concerned. It will only return (and set
10750          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10751          */
10752         return 0;
10753 }
10754
10755 /*
10756  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10757  * for running an L2 nested guest.
10758  */
10759 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10760 {
10761         struct vmcs12 *vmcs12;
10762         struct vcpu_vmx *vmx = to_vmx(vcpu);
10763         u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu);
10764         u32 exit_qual;
10765         int ret;
10766
10767         if (!nested_vmx_check_permission(vcpu))
10768                 return 1;
10769
10770         if (!nested_vmx_check_vmcs12(vcpu))
10771                 goto out;
10772
10773         vmcs12 = get_vmcs12(vcpu);
10774
10775         if (enable_shadow_vmcs)
10776                 copy_shadow_to_vmcs12(vmx);
10777
10778         /*
10779          * The nested entry process starts with enforcing various prerequisites
10780          * on vmcs12 as required by the Intel SDM, and act appropriately when
10781          * they fail: As the SDM explains, some conditions should cause the
10782          * instruction to fail, while others will cause the instruction to seem
10783          * to succeed, but return an EXIT_REASON_INVALID_STATE.
10784          * To speed up the normal (success) code path, we should avoid checking
10785          * for misconfigurations which will anyway be caught by the processor
10786          * when using the merged vmcs02.
10787          */
10788         if (interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS) {
10789                 nested_vmx_failValid(vcpu,
10790                                      VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS);
10791                 goto out;
10792         }
10793
10794         if (vmcs12->launch_state == launch) {
10795                 nested_vmx_failValid(vcpu,
10796                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10797                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10798                 goto out;
10799         }
10800
10801         ret = check_vmentry_prereqs(vcpu, vmcs12);
10802         if (ret) {
10803                 nested_vmx_failValid(vcpu, ret);
10804                 goto out;
10805         }
10806
10807         /*
10808          * After this point, the trap flag no longer triggers a singlestep trap
10809          * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10810          * This is not 100% correct; for performance reasons, we delegate most
10811          * of the checks on host state to the processor.  If those fail,
10812          * the singlestep trap is missed.
10813          */
10814         skip_emulated_instruction(vcpu);
10815
10816         ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
10817         if (ret) {
10818                 nested_vmx_entry_failure(vcpu, vmcs12,
10819                                          EXIT_REASON_INVALID_STATE, exit_qual);
10820                 return 1;
10821         }
10822
10823         /*
10824          * We're finally done with prerequisite checking, and can start with
10825          * the nested entry.
10826          */
10827
10828         ret = enter_vmx_non_root_mode(vcpu, true);
10829         if (ret)
10830                 return ret;
10831
10832         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10833                 return kvm_vcpu_halt(vcpu);
10834
10835         vmx->nested.nested_run_pending = 1;
10836
10837         return 1;
10838
10839 out:
10840         return kvm_skip_emulated_instruction(vcpu);
10841 }
10842
10843 /*
10844  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10845  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10846  * This function returns the new value we should put in vmcs12.guest_cr0.
10847  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10848  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10849  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10850  *     didn't trap the bit, because if L1 did, so would L0).
10851  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10852  *     been modified by L2, and L1 knows it. So just leave the old value of
10853  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10854  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10855  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10856  *     changed these bits, and therefore they need to be updated, but L0
10857  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10858  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10859  */
10860 static inline unsigned long
10861 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10862 {
10863         return
10864         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10865         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10866         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10867                         vcpu->arch.cr0_guest_owned_bits));
10868 }
10869
10870 static inline unsigned long
10871 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10872 {
10873         return
10874         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10875         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10876         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10877                         vcpu->arch.cr4_guest_owned_bits));
10878 }
10879
10880 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10881                                        struct vmcs12 *vmcs12)
10882 {
10883         u32 idt_vectoring;
10884         unsigned int nr;
10885
10886         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10887                 nr = vcpu->arch.exception.nr;
10888                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10889
10890                 if (kvm_exception_is_soft(nr)) {
10891                         vmcs12->vm_exit_instruction_len =
10892                                 vcpu->arch.event_exit_inst_len;
10893                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10894                 } else
10895                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10896
10897                 if (vcpu->arch.exception.has_error_code) {
10898                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10899                         vmcs12->idt_vectoring_error_code =
10900                                 vcpu->arch.exception.error_code;
10901                 }
10902
10903                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10904         } else if (vcpu->arch.nmi_injected) {
10905                 vmcs12->idt_vectoring_info_field =
10906                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10907         } else if (vcpu->arch.interrupt.pending) {
10908                 nr = vcpu->arch.interrupt.nr;
10909                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10910
10911                 if (vcpu->arch.interrupt.soft) {
10912                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10913                         vmcs12->vm_entry_instruction_len =
10914                                 vcpu->arch.event_exit_inst_len;
10915                 } else
10916                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10917
10918                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10919         }
10920 }
10921
10922 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10923 {
10924         struct vcpu_vmx *vmx = to_vmx(vcpu);
10925
10926         if (vcpu->arch.exception.pending ||
10927                 vcpu->arch.nmi_injected ||
10928                 vcpu->arch.interrupt.pending)
10929                 return -EBUSY;
10930
10931         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10932             vmx->nested.preemption_timer_expired) {
10933                 if (vmx->nested.nested_run_pending)
10934                         return -EBUSY;
10935                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10936                 return 0;
10937         }
10938
10939         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10940                 if (vmx->nested.nested_run_pending)
10941                         return -EBUSY;
10942                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10943                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10944                                   INTR_INFO_VALID_MASK, 0);
10945                 /*
10946                  * The NMI-triggered VM exit counts as injection:
10947                  * clear this one and block further NMIs.
10948                  */
10949                 vcpu->arch.nmi_pending = 0;
10950                 vmx_set_nmi_mask(vcpu, true);
10951                 return 0;
10952         }
10953
10954         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10955             nested_exit_on_intr(vcpu)) {
10956                 if (vmx->nested.nested_run_pending)
10957                         return -EBUSY;
10958                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10959                 return 0;
10960         }
10961
10962         vmx_complete_nested_posted_interrupt(vcpu);
10963         return 0;
10964 }
10965
10966 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10967 {
10968         ktime_t remaining =
10969                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10970         u64 value;
10971
10972         if (ktime_to_ns(remaining) <= 0)
10973                 return 0;
10974
10975         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10976         do_div(value, 1000000);
10977         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10978 }
10979
10980 /*
10981  * Update the guest state fields of vmcs12 to reflect changes that
10982  * occurred while L2 was running. (The "IA-32e mode guest" bit of the
10983  * VM-entry controls is also updated, since this is really a guest
10984  * state bit.)
10985  */
10986 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10987 {
10988         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10989         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10990
10991         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10992         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10993         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10994
10995         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10996         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10997         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10998         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10999         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
11000         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
11001         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
11002         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
11003         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
11004         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
11005         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
11006         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
11007         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
11008         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
11009         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
11010         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
11011         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
11012         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
11013         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
11014         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
11015         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
11016         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
11017         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
11018         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
11019         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
11020         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
11021         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
11022         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
11023         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
11024         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
11025         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
11026         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
11027         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
11028         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
11029         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
11030         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
11031
11032         vmcs12->guest_interruptibility_info =
11033                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
11034         vmcs12->guest_pending_dbg_exceptions =
11035                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
11036         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
11037                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
11038         else
11039                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
11040
11041         if (nested_cpu_has_preemption_timer(vmcs12)) {
11042                 if (vmcs12->vm_exit_controls &
11043                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
11044                         vmcs12->vmx_preemption_timer_value =
11045                                 vmx_get_preemption_timer_value(vcpu);
11046                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
11047         }
11048
11049         /*
11050          * In some cases (usually, nested EPT), L2 is allowed to change its
11051          * own CR3 without exiting. If it has changed it, we must keep it.
11052          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
11053          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
11054          *
11055          * Additionally, restore L2's PDPTR to vmcs12.
11056          */
11057         if (enable_ept) {
11058                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
11059                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
11060                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
11061                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
11062                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
11063         }
11064
11065         vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
11066
11067         if (nested_cpu_has_vid(vmcs12))
11068                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
11069
11070         vmcs12->vm_entry_controls =
11071                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
11072                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
11073
11074         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
11075                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
11076                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
11077         }
11078
11079         /* TODO: These cannot have changed unless we have MSR bitmaps and
11080          * the relevant bit asks not to trap the change */
11081         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
11082                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
11083         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
11084                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
11085         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
11086         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
11087         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
11088         if (kvm_mpx_supported())
11089                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
11090 }
11091
11092 /*
11093  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
11094  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
11095  * and this function updates it to reflect the changes to the guest state while
11096  * L2 was running (and perhaps made some exits which were handled directly by L0
11097  * without going back to L1), and to reflect the exit reason.
11098  * Note that we do not have to copy here all VMCS fields, just those that
11099  * could have changed by the L2 guest or the exit - i.e., the guest-state and
11100  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
11101  * which already writes to vmcs12 directly.
11102  */
11103 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
11104                            u32 exit_reason, u32 exit_intr_info,
11105                            unsigned long exit_qualification)
11106 {
11107         /* update guest state fields: */
11108         sync_vmcs12(vcpu, vmcs12);
11109
11110         /* update exit information fields: */
11111
11112         vmcs12->vm_exit_reason = exit_reason;
11113         vmcs12->exit_qualification = exit_qualification;
11114         vmcs12->vm_exit_intr_info = exit_intr_info;
11115
11116         vmcs12->idt_vectoring_info_field = 0;
11117         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
11118         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
11119
11120         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
11121                 vmcs12->launch_state = 1;
11122
11123                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
11124                  * instead of reading the real value. */
11125                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
11126
11127                 /*
11128                  * Transfer the event that L0 or L1 may wanted to inject into
11129                  * L2 to IDT_VECTORING_INFO_FIELD.
11130                  */
11131                 vmcs12_save_pending_event(vcpu, vmcs12);
11132         }
11133
11134         /*
11135          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
11136          * preserved above and would only end up incorrectly in L1.
11137          */
11138         vcpu->arch.nmi_injected = false;
11139         kvm_clear_exception_queue(vcpu);
11140         kvm_clear_interrupt_queue(vcpu);
11141 }
11142
11143 /*
11144  * A part of what we need to when the nested L2 guest exits and we want to
11145  * run its L1 parent, is to reset L1's guest state to the host state specified
11146  * in vmcs12.
11147  * This function is to be called not only on normal nested exit, but also on
11148  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
11149  * Failures During or After Loading Guest State").
11150  * This function should be called when the active VMCS is L1's (vmcs01).
11151  */
11152 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
11153                                    struct vmcs12 *vmcs12)
11154 {
11155         struct kvm_segment seg;
11156         u32 entry_failure_code;
11157
11158         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
11159                 vcpu->arch.efer = vmcs12->host_ia32_efer;
11160         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
11161                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
11162         else
11163                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
11164         vmx_set_efer(vcpu, vcpu->arch.efer);
11165
11166         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
11167         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
11168         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
11169         /*
11170          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
11171          * actually changed, because vmx_set_cr0 refers to efer set above.
11172          *
11173          * CR0_GUEST_HOST_MASK is already set in the original vmcs01
11174          * (KVM doesn't change it);
11175          */
11176         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
11177         vmx_set_cr0(vcpu, vmcs12->host_cr0);
11178
11179         /* Same as above - no reason to call set_cr4_guest_host_mask().  */
11180         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
11181         kvm_set_cr4(vcpu, vmcs12->host_cr4);
11182
11183         nested_ept_uninit_mmu_context(vcpu);
11184
11185         /*
11186          * Only PDPTE load can fail as the value of cr3 was checked on entry and
11187          * couldn't have changed.
11188          */
11189         if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
11190                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
11191
11192         if (!enable_ept)
11193                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
11194
11195         if (enable_vpid) {
11196                 /*
11197                  * Trivially support vpid by letting L2s share their parent
11198                  * L1's vpid. TODO: move to a more elaborate solution, giving
11199                  * each L2 its own vpid and exposing the vpid feature to L1.
11200                  */
11201                 vmx_flush_tlb(vcpu);
11202         }
11203         /* Restore posted intr vector. */
11204         if (nested_cpu_has_posted_intr(vmcs12))
11205                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
11206
11207         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
11208         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
11209         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
11210         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
11211         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
11212
11213         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
11214         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
11215                 vmcs_write64(GUEST_BNDCFGS, 0);
11216
11217         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
11218                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
11219                 vcpu->arch.pat = vmcs12->host_ia32_pat;
11220         }
11221         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
11222                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
11223                         vmcs12->host_ia32_perf_global_ctrl);
11224
11225         /* Set L1 segment info according to Intel SDM
11226             27.5.2 Loading Host Segment and Descriptor-Table Registers */
11227         seg = (struct kvm_segment) {
11228                 .base = 0,
11229                 .limit = 0xFFFFFFFF,
11230                 .selector = vmcs12->host_cs_selector,
11231                 .type = 11,
11232                 .present = 1,
11233                 .s = 1,
11234                 .g = 1
11235         };
11236         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
11237                 seg.l = 1;
11238         else
11239                 seg.db = 1;
11240         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
11241         seg = (struct kvm_segment) {
11242                 .base = 0,
11243                 .limit = 0xFFFFFFFF,
11244                 .type = 3,
11245                 .present = 1,
11246                 .s = 1,
11247                 .db = 1,
11248                 .g = 1
11249         };
11250         seg.selector = vmcs12->host_ds_selector;
11251         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
11252         seg.selector = vmcs12->host_es_selector;
11253         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
11254         seg.selector = vmcs12->host_ss_selector;
11255         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
11256         seg.selector = vmcs12->host_fs_selector;
11257         seg.base = vmcs12->host_fs_base;
11258         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
11259         seg.selector = vmcs12->host_gs_selector;
11260         seg.base = vmcs12->host_gs_base;
11261         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
11262         seg = (struct kvm_segment) {
11263                 .base = vmcs12->host_tr_base,
11264                 .limit = 0x67,
11265                 .selector = vmcs12->host_tr_selector,
11266                 .type = 11,
11267                 .present = 1
11268         };
11269         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
11270
11271         kvm_set_dr(vcpu, 7, 0x400);
11272         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
11273
11274         if (cpu_has_vmx_msr_bitmap())
11275                 vmx_set_msr_bitmap(vcpu);
11276
11277         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
11278                                 vmcs12->vm_exit_msr_load_count))
11279                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
11280 }
11281
11282 /*
11283  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11284  * and modify vmcs12 to make it see what it would expect to see there if
11285  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11286  */
11287 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
11288                               u32 exit_intr_info,
11289                               unsigned long exit_qualification)
11290 {
11291         struct vcpu_vmx *vmx = to_vmx(vcpu);
11292         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11293         u32 vm_inst_error = 0;
11294
11295         /* trying to cancel vmlaunch/vmresume is a bug */
11296         WARN_ON_ONCE(vmx->nested.nested_run_pending);
11297
11298         leave_guest_mode(vcpu);
11299         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
11300                        exit_qualification);
11301
11302         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
11303                                  vmcs12->vm_exit_msr_store_count))
11304                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
11305
11306         if (unlikely(vmx->fail))
11307                 vm_inst_error = vmcs_read32(VM_INSTRUCTION_ERROR);
11308
11309         vmx_switch_vmcs(vcpu, &vmx->vmcs01);
11310
11311         /*
11312          * TODO: SDM says that with acknowledge interrupt on exit, bit 31 of
11313          * the VM-exit interrupt information (valid interrupt) is always set to
11314          * 1 on EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't need
11315          * kvm_cpu_has_interrupt().  See the commit message for details.
11316          */
11317         if (nested_exit_intr_ack_set(vcpu) &&
11318             exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT &&
11319             kvm_cpu_has_interrupt(vcpu)) {
11320                 int irq = kvm_cpu_get_interrupt(vcpu);
11321                 WARN_ON(irq < 0);
11322                 vmcs12->vm_exit_intr_info = irq |
11323                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
11324         }
11325
11326         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
11327                                        vmcs12->exit_qualification,
11328                                        vmcs12->idt_vectoring_info_field,
11329                                        vmcs12->vm_exit_intr_info,
11330                                        vmcs12->vm_exit_intr_error_code,
11331                                        KVM_ISA_VMX);
11332
11333         vm_entry_controls_reset_shadow(vmx);
11334         vm_exit_controls_reset_shadow(vmx);
11335         vmx_segment_cache_clear(vmx);
11336
11337         /* if no vmcs02 cache requested, remove the one we used */
11338         if (VMCS02_POOL_SIZE == 0)
11339                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
11340
11341         load_vmcs12_host_state(vcpu, vmcs12);
11342
11343         /* Update any VMCS fields that might have changed while L2 ran */
11344         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11345         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11346         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
11347         if (vmx->hv_deadline_tsc == -1)
11348                 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11349                                 PIN_BASED_VMX_PREEMPTION_TIMER);
11350         else
11351                 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11352                               PIN_BASED_VMX_PREEMPTION_TIMER);
11353         if (kvm_has_tsc_control)
11354                 decache_tsc_multiplier(vmx);
11355
11356         if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
11357                 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
11358                 vmx_set_virtual_x2apic_mode(vcpu,
11359                                 vcpu->arch.apic_base & X2APIC_ENABLE);
11360         } else if (!nested_cpu_has_ept(vmcs12) &&
11361                    nested_cpu_has2(vmcs12,
11362                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11363                 vmx_flush_tlb_ept_only(vcpu);
11364         }
11365
11366         /* This is needed for same reason as it was needed in prepare_vmcs02 */
11367         vmx->host_rsp = 0;
11368
11369         /* Unpin physical memory we referred to in vmcs02 */
11370         if (vmx->nested.apic_access_page) {
11371                 kvm_release_page_dirty(vmx->nested.apic_access_page);
11372                 vmx->nested.apic_access_page = NULL;
11373         }
11374         if (vmx->nested.virtual_apic_page) {
11375                 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
11376                 vmx->nested.virtual_apic_page = NULL;
11377         }
11378         if (vmx->nested.pi_desc_page) {
11379                 kunmap(vmx->nested.pi_desc_page);
11380                 kvm_release_page_dirty(vmx->nested.pi_desc_page);
11381                 vmx->nested.pi_desc_page = NULL;
11382                 vmx->nested.pi_desc = NULL;
11383         }
11384
11385         /*
11386          * We are now running in L2, mmu_notifier will force to reload the
11387          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11388          */
11389         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
11390
11391         /*
11392          * Exiting from L2 to L1, we're now back to L1 which thinks it just
11393          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11394          * success or failure flag accordingly.
11395          */
11396         if (unlikely(vmx->fail)) {
11397                 vmx->fail = 0;
11398                 nested_vmx_failValid(vcpu, vm_inst_error);
11399         } else
11400                 nested_vmx_succeed(vcpu);
11401         if (enable_shadow_vmcs)
11402                 vmx->nested.sync_shadow_vmcs = true;
11403
11404         /* in case we halted in L2 */
11405         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11406 }
11407
11408 /*
11409  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11410  */
11411 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
11412 {
11413         if (is_guest_mode(vcpu)) {
11414                 to_vmx(vcpu)->nested.nested_run_pending = 0;
11415                 nested_vmx_vmexit(vcpu, -1, 0, 0);
11416         }
11417         free_nested(to_vmx(vcpu));
11418 }
11419
11420 /*
11421  * L1's failure to enter L2 is a subset of a normal exit, as explained in
11422  * 23.7 "VM-entry failures during or after loading guest state" (this also
11423  * lists the acceptable exit-reason and exit-qualification parameters).
11424  * It should only be called before L2 actually succeeded to run, and when
11425  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11426  */
11427 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
11428                         struct vmcs12 *vmcs12,
11429                         u32 reason, unsigned long qualification)
11430 {
11431         load_vmcs12_host_state(vcpu, vmcs12);
11432         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
11433         vmcs12->exit_qualification = qualification;
11434         nested_vmx_succeed(vcpu);
11435         if (enable_shadow_vmcs)
11436                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
11437 }
11438
11439 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
11440                                struct x86_instruction_info *info,
11441                                enum x86_intercept_stage stage)
11442 {
11443         return X86EMUL_CONTINUE;
11444 }
11445
11446 #ifdef CONFIG_X86_64
11447 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11448 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
11449                                   u64 divisor, u64 *result)
11450 {
11451         u64 low = a << shift, high = a >> (64 - shift);
11452
11453         /* To avoid the overflow on divq */
11454         if (high >= divisor)
11455                 return 1;
11456
11457         /* Low hold the result, high hold rem which is discarded */
11458         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
11459             "rm" (divisor), "0" (low), "1" (high));
11460         *result = low;
11461
11462         return 0;
11463 }
11464
11465 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
11466 {
11467         struct vcpu_vmx *vmx = to_vmx(vcpu);
11468         u64 tscl = rdtsc();
11469         u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
11470         u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
11471
11472         /* Convert to host delta tsc if tsc scaling is enabled */
11473         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
11474                         u64_shl_div_u64(delta_tsc,
11475                                 kvm_tsc_scaling_ratio_frac_bits,
11476                                 vcpu->arch.tsc_scaling_ratio,
11477                                 &delta_tsc))
11478                 return -ERANGE;
11479
11480         /*
11481          * If the delta tsc can't fit in the 32 bit after the multi shift,
11482          * we can't use the preemption timer.
11483          * It's possible that it fits on later vmentries, but checking
11484          * on every vmentry is costly so we just use an hrtimer.
11485          */
11486         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
11487                 return -ERANGE;
11488
11489         vmx->hv_deadline_tsc = tscl + delta_tsc;
11490         vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11491                         PIN_BASED_VMX_PREEMPTION_TIMER);
11492
11493         return delta_tsc == 0;
11494 }
11495
11496 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
11497 {
11498         struct vcpu_vmx *vmx = to_vmx(vcpu);
11499         vmx->hv_deadline_tsc = -1;
11500         vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11501                         PIN_BASED_VMX_PREEMPTION_TIMER);
11502 }
11503 #endif
11504
11505 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
11506 {
11507         if (ple_gap)
11508                 shrink_ple_window(vcpu);
11509 }
11510
11511 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
11512                                      struct kvm_memory_slot *slot)
11513 {
11514         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
11515         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
11516 }
11517
11518 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
11519                                        struct kvm_memory_slot *slot)
11520 {
11521         kvm_mmu_slot_set_dirty(kvm, slot);
11522 }
11523
11524 static void vmx_flush_log_dirty(struct kvm *kvm)
11525 {
11526         kvm_flush_pml_buffers(kvm);
11527 }
11528
11529 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
11530 {
11531         struct vmcs12 *vmcs12;
11532         struct vcpu_vmx *vmx = to_vmx(vcpu);
11533         gpa_t gpa;
11534         struct page *page = NULL;
11535         u64 *pml_address;
11536
11537         if (is_guest_mode(vcpu)) {
11538                 WARN_ON_ONCE(vmx->nested.pml_full);
11539
11540                 /*
11541                  * Check if PML is enabled for the nested guest.
11542                  * Whether eptp bit 6 is set is already checked
11543                  * as part of A/D emulation.
11544                  */
11545                 vmcs12 = get_vmcs12(vcpu);
11546                 if (!nested_cpu_has_pml(vmcs12))
11547                         return 0;
11548
11549                 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
11550                         vmx->nested.pml_full = true;
11551                         return 1;
11552                 }
11553
11554                 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
11555
11556                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->pml_address);
11557                 if (is_error_page(page))
11558                         return 0;
11559
11560                 pml_address = kmap(page);
11561                 pml_address[vmcs12->guest_pml_index--] = gpa;
11562                 kunmap(page);
11563                 kvm_release_page_clean(page);
11564         }
11565
11566         return 0;
11567 }
11568
11569 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
11570                                            struct kvm_memory_slot *memslot,
11571                                            gfn_t offset, unsigned long mask)
11572 {
11573         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11574 }
11575
11576 /*
11577  * This routine does the following things for vCPU which is going
11578  * to be blocked if VT-d PI is enabled.
11579  * - Store the vCPU to the wakeup list, so when interrupts happen
11580  *   we can find the right vCPU to wake up.
11581  * - Change the Posted-interrupt descriptor as below:
11582  *      'NDST' <-- vcpu->pre_pcpu
11583  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11584  * - If 'ON' is set during this process, which means at least one
11585  *   interrupt is posted for this vCPU, we cannot block it, in
11586  *   this case, return 1, otherwise, return 0.
11587  *
11588  */
11589 static int pi_pre_block(struct kvm_vcpu *vcpu)
11590 {
11591         unsigned long flags;
11592         unsigned int dest;
11593         struct pi_desc old, new;
11594         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11595
11596         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11597                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11598                 !kvm_vcpu_apicv_active(vcpu))
11599                 return 0;
11600
11601         vcpu->pre_pcpu = vcpu->cpu;
11602         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11603                           vcpu->pre_pcpu), flags);
11604         list_add_tail(&vcpu->blocked_vcpu_list,
11605                       &per_cpu(blocked_vcpu_on_cpu,
11606                       vcpu->pre_pcpu));
11607         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
11608                                vcpu->pre_pcpu), flags);
11609
11610         do {
11611                 old.control = new.control = pi_desc->control;
11612
11613                 /*
11614                  * We should not block the vCPU if
11615                  * an interrupt is posted for it.
11616                  */
11617                 if (pi_test_on(pi_desc) == 1) {
11618                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11619                                           vcpu->pre_pcpu), flags);
11620                         list_del(&vcpu->blocked_vcpu_list);
11621                         spin_unlock_irqrestore(
11622                                         &per_cpu(blocked_vcpu_on_cpu_lock,
11623                                         vcpu->pre_pcpu), flags);
11624                         vcpu->pre_pcpu = -1;
11625
11626                         return 1;
11627                 }
11628
11629                 WARN((pi_desc->sn == 1),
11630                      "Warning: SN field of posted-interrupts "
11631                      "is set before blocking\n");
11632
11633                 /*
11634                  * Since vCPU can be preempted during this process,
11635                  * vcpu->cpu could be different with pre_pcpu, we
11636                  * need to set pre_pcpu as the destination of wakeup
11637                  * notification event, then we can find the right vCPU
11638                  * to wakeup in wakeup handler if interrupts happen
11639                  * when the vCPU is in blocked state.
11640                  */
11641                 dest = cpu_physical_id(vcpu->pre_pcpu);
11642
11643                 if (x2apic_enabled())
11644                         new.ndst = dest;
11645                 else
11646                         new.ndst = (dest << 8) & 0xFF00;
11647
11648                 /* set 'NV' to 'wakeup vector' */
11649                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
11650         } while (cmpxchg(&pi_desc->control, old.control,
11651                         new.control) != old.control);
11652
11653         return 0;
11654 }
11655
11656 static int vmx_pre_block(struct kvm_vcpu *vcpu)
11657 {
11658         if (pi_pre_block(vcpu))
11659                 return 1;
11660
11661         if (kvm_lapic_hv_timer_in_use(vcpu))
11662                 kvm_lapic_switch_to_sw_timer(vcpu);
11663
11664         return 0;
11665 }
11666
11667 static void pi_post_block(struct kvm_vcpu *vcpu)
11668 {
11669         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11670         struct pi_desc old, new;
11671         unsigned int dest;
11672         unsigned long flags;
11673
11674         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11675                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11676                 !kvm_vcpu_apicv_active(vcpu))
11677                 return;
11678
11679         do {
11680                 old.control = new.control = pi_desc->control;
11681
11682                 dest = cpu_physical_id(vcpu->cpu);
11683
11684                 if (x2apic_enabled())
11685                         new.ndst = dest;
11686                 else
11687                         new.ndst = (dest << 8) & 0xFF00;
11688
11689                 /* Allow posting non-urgent interrupts */
11690                 new.sn = 0;
11691
11692                 /* set 'NV' to 'notification vector' */
11693                 new.nv = POSTED_INTR_VECTOR;
11694         } while (cmpxchg(&pi_desc->control, old.control,
11695                         new.control) != old.control);
11696
11697         if(vcpu->pre_pcpu != -1) {
11698                 spin_lock_irqsave(
11699                         &per_cpu(blocked_vcpu_on_cpu_lock,
11700                         vcpu->pre_pcpu), flags);
11701                 list_del(&vcpu->blocked_vcpu_list);
11702                 spin_unlock_irqrestore(
11703                         &per_cpu(blocked_vcpu_on_cpu_lock,
11704                         vcpu->pre_pcpu), flags);
11705                 vcpu->pre_pcpu = -1;
11706         }
11707 }
11708
11709 static void vmx_post_block(struct kvm_vcpu *vcpu)
11710 {
11711         if (kvm_x86_ops->set_hv_timer)
11712                 kvm_lapic_switch_to_hv_timer(vcpu);
11713
11714         pi_post_block(vcpu);
11715 }
11716
11717 /*
11718  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11719  *
11720  * @kvm: kvm
11721  * @host_irq: host irq of the interrupt
11722  * @guest_irq: gsi of the interrupt
11723  * @set: set or unset PI
11724  * returns 0 on success, < 0 on failure
11725  */
11726 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11727                               uint32_t guest_irq, bool set)
11728 {
11729         struct kvm_kernel_irq_routing_entry *e;
11730         struct kvm_irq_routing_table *irq_rt;
11731         struct kvm_lapic_irq irq;
11732         struct kvm_vcpu *vcpu;
11733         struct vcpu_data vcpu_info;
11734         int idx, ret = -EINVAL;
11735
11736         if (!kvm_arch_has_assigned_device(kvm) ||
11737                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11738                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
11739                 return 0;
11740
11741         idx = srcu_read_lock(&kvm->irq_srcu);
11742         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11743         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
11744
11745         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11746                 if (e->type != KVM_IRQ_ROUTING_MSI)
11747                         continue;
11748                 /*
11749                  * VT-d PI cannot support posting multicast/broadcast
11750                  * interrupts to a vCPU, we still use interrupt remapping
11751                  * for these kind of interrupts.
11752                  *
11753                  * For lowest-priority interrupts, we only support
11754                  * those with single CPU as the destination, e.g. user
11755                  * configures the interrupts via /proc/irq or uses
11756                  * irqbalance to make the interrupts single-CPU.
11757                  *
11758                  * We will support full lowest-priority interrupt later.
11759                  */
11760
11761                 kvm_set_msi_irq(kvm, e, &irq);
11762                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11763                         /*
11764                          * Make sure the IRTE is in remapped mode if
11765                          * we don't handle it in posted mode.
11766                          */
11767                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11768                         if (ret < 0) {
11769                                 printk(KERN_INFO
11770                                    "failed to back to remapped mode, irq: %u\n",
11771                                    host_irq);
11772                                 goto out;
11773                         }
11774
11775                         continue;
11776                 }
11777
11778                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11779                 vcpu_info.vector = irq.vector;
11780
11781                 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
11782                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11783
11784                 if (set)
11785                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11786                 else {
11787                         /* suppress notification event before unposting */
11788                         pi_set_sn(vcpu_to_pi_desc(vcpu));
11789                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11790                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
11791                 }
11792
11793                 if (ret < 0) {
11794                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
11795                                         __func__);
11796                         goto out;
11797                 }
11798         }
11799
11800         ret = 0;
11801 out:
11802         srcu_read_unlock(&kvm->irq_srcu, idx);
11803         return ret;
11804 }
11805
11806 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11807 {
11808         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11809                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11810                         FEATURE_CONTROL_LMCE;
11811         else
11812                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11813                         ~FEATURE_CONTROL_LMCE;
11814 }
11815
11816 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
11817         .cpu_has_kvm_support = cpu_has_kvm_support,
11818         .disabled_by_bios = vmx_disabled_by_bios,
11819         .hardware_setup = hardware_setup,
11820         .hardware_unsetup = hardware_unsetup,
11821         .check_processor_compatibility = vmx_check_processor_compat,
11822         .hardware_enable = hardware_enable,
11823         .hardware_disable = hardware_disable,
11824         .cpu_has_accelerated_tpr = report_flexpriority,
11825         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
11826
11827         .vcpu_create = vmx_create_vcpu,
11828         .vcpu_free = vmx_free_vcpu,
11829         .vcpu_reset = vmx_vcpu_reset,
11830
11831         .prepare_guest_switch = vmx_save_host_state,
11832         .vcpu_load = vmx_vcpu_load,
11833         .vcpu_put = vmx_vcpu_put,
11834
11835         .update_bp_intercept = update_exception_bitmap,
11836         .get_msr = vmx_get_msr,
11837         .set_msr = vmx_set_msr,
11838         .get_segment_base = vmx_get_segment_base,
11839         .get_segment = vmx_get_segment,
11840         .set_segment = vmx_set_segment,
11841         .get_cpl = vmx_get_cpl,
11842         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
11843         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
11844         .decache_cr3 = vmx_decache_cr3,
11845         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
11846         .set_cr0 = vmx_set_cr0,
11847         .set_cr3 = vmx_set_cr3,
11848         .set_cr4 = vmx_set_cr4,
11849         .set_efer = vmx_set_efer,
11850         .get_idt = vmx_get_idt,
11851         .set_idt = vmx_set_idt,
11852         .get_gdt = vmx_get_gdt,
11853         .set_gdt = vmx_set_gdt,
11854         .get_dr6 = vmx_get_dr6,
11855         .set_dr6 = vmx_set_dr6,
11856         .set_dr7 = vmx_set_dr7,
11857         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
11858         .cache_reg = vmx_cache_reg,
11859         .get_rflags = vmx_get_rflags,
11860         .set_rflags = vmx_set_rflags,
11861
11862         .get_pkru = vmx_get_pkru,
11863
11864         .tlb_flush = vmx_flush_tlb,
11865
11866         .run = vmx_vcpu_run,
11867         .handle_exit = vmx_handle_exit,
11868         .skip_emulated_instruction = skip_emulated_instruction,
11869         .set_interrupt_shadow = vmx_set_interrupt_shadow,
11870         .get_interrupt_shadow = vmx_get_interrupt_shadow,
11871         .patch_hypercall = vmx_patch_hypercall,
11872         .set_irq = vmx_inject_irq,
11873         .set_nmi = vmx_inject_nmi,
11874         .queue_exception = vmx_queue_exception,
11875         .cancel_injection = vmx_cancel_injection,
11876         .interrupt_allowed = vmx_interrupt_allowed,
11877         .nmi_allowed = vmx_nmi_allowed,
11878         .get_nmi_mask = vmx_get_nmi_mask,
11879         .set_nmi_mask = vmx_set_nmi_mask,
11880         .enable_nmi_window = enable_nmi_window,
11881         .enable_irq_window = enable_irq_window,
11882         .update_cr8_intercept = update_cr8_intercept,
11883         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
11884         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
11885         .get_enable_apicv = vmx_get_enable_apicv,
11886         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
11887         .load_eoi_exitmap = vmx_load_eoi_exitmap,
11888         .apicv_post_state_restore = vmx_apicv_post_state_restore,
11889         .hwapic_irr_update = vmx_hwapic_irr_update,
11890         .hwapic_isr_update = vmx_hwapic_isr_update,
11891         .sync_pir_to_irr = vmx_sync_pir_to_irr,
11892         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
11893
11894         .set_tss_addr = vmx_set_tss_addr,
11895         .get_tdp_level = get_ept_level,
11896         .get_mt_mask = vmx_get_mt_mask,
11897
11898         .get_exit_info = vmx_get_exit_info,
11899
11900         .get_lpage_level = vmx_get_lpage_level,
11901
11902         .cpuid_update = vmx_cpuid_update,
11903
11904         .rdtscp_supported = vmx_rdtscp_supported,
11905         .invpcid_supported = vmx_invpcid_supported,
11906
11907         .set_supported_cpuid = vmx_set_supported_cpuid,
11908
11909         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
11910
11911         .write_tsc_offset = vmx_write_tsc_offset,
11912
11913         .set_tdp_cr3 = vmx_set_cr3,
11914
11915         .check_intercept = vmx_check_intercept,
11916         .handle_external_intr = vmx_handle_external_intr,
11917         .mpx_supported = vmx_mpx_supported,
11918         .xsaves_supported = vmx_xsaves_supported,
11919
11920         .check_nested_events = vmx_check_nested_events,
11921
11922         .sched_in = vmx_sched_in,
11923
11924         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11925         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11926         .flush_log_dirty = vmx_flush_log_dirty,
11927         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
11928         .write_log_dirty = vmx_write_pml_buffer,
11929
11930         .pre_block = vmx_pre_block,
11931         .post_block = vmx_post_block,
11932
11933         .pmu_ops = &intel_pmu_ops,
11934
11935         .update_pi_irte = vmx_update_pi_irte,
11936
11937 #ifdef CONFIG_X86_64
11938         .set_hv_timer = vmx_set_hv_timer,
11939         .cancel_hv_timer = vmx_cancel_hv_timer,
11940 #endif
11941
11942         .setup_mce = vmx_setup_mce,
11943 };
11944
11945 static int __init vmx_init(void)
11946 {
11947         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11948                      __alignof__(struct vcpu_vmx), THIS_MODULE);
11949         if (r)
11950                 return r;
11951
11952 #ifdef CONFIG_KEXEC_CORE
11953         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11954                            crash_vmclear_local_loaded_vmcss);
11955 #endif
11956
11957         return 0;
11958 }
11959
11960 static void __exit vmx_exit(void)
11961 {
11962 #ifdef CONFIG_KEXEC_CORE
11963         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
11964         synchronize_rcu();
11965 #endif
11966
11967         kvm_exit();
11968 }
11969
11970 module_init(vmx_init)
11971 module_exit(vmx_exit)