arch/x86/kvm/vmx/vmx.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __KVM_X86_VMX_H
   3 #define __KVM_X86_VMX_H
   4
   5 #include <linux/kvm_host.h>
   6
   7 #include <asm/kvm.h>
   8 #include <asm/intel_pt.h>
   9
  10 #include "capabilities.h"
  11 #include "kvm_cache_regs.h"
  12 #include "posted_intr.h"
  13 #include "vmcs.h"
  14 #include "vmx_ops.h"
  15 #include "cpuid.h"
  16
  17 extern const u32 vmx_msr_index[];
  18
  19 #define MSR_TYPE_R      1
  20 #define MSR_TYPE_W      2
  21 #define MSR_TYPE_RW     3
  22
  23 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
  24
  25 #ifdef CONFIG_X86_64
  26 #define MAX_NR_USER_RETURN_MSRS 7
  27 #else
  28 #define MAX_NR_USER_RETURN_MSRS 4
  29 #endif
  30
  31 #define MAX_NR_LOADSTORE_MSRS   8
  32
  33 struct vmx_msrs {
  34         unsigned int            nr;
  35         struct vmx_msr_entry    val[MAX_NR_LOADSTORE_MSRS];
  36 };
  37
  38 struct vmx_uret_msr {
  39         unsigned int slot; /* The MSR's slot in kvm_user_return_msrs. */
  40         u64 data;
  41         u64 mask;
  42 };
  43
  44 enum segment_cache_field {
  45         SEG_FIELD_SEL = 0,
  46         SEG_FIELD_BASE = 1,
  47         SEG_FIELD_LIMIT = 2,
  48         SEG_FIELD_AR = 3,
  49
  50         SEG_FIELD_NR = 4
  51 };
  52
  53 #define RTIT_ADDR_RANGE         4
  54
  55 struct pt_ctx {
  56         u64 ctl;
  57         u64 status;
  58         u64 output_base;
  59         u64 output_mask;
  60         u64 cr3_match;
  61         u64 addr_a[RTIT_ADDR_RANGE];
  62         u64 addr_b[RTIT_ADDR_RANGE];
  63 };
  64
  65 struct pt_desc {
  66         u64 ctl_bitmask;
  67         u32 addr_range;
  68         u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
  69         struct pt_ctx host;
  70         struct pt_ctx guest;
  71 };
  72
  73 union vmx_exit_reason {
  74         struct {
  75                 u32     basic                   : 16;
  76                 u32     reserved16              : 1;
  77                 u32     reserved17              : 1;
  78                 u32     reserved18              : 1;
  79                 u32     reserved19              : 1;
  80                 u32     reserved20              : 1;
  81                 u32     reserved21              : 1;
  82                 u32     reserved22              : 1;
  83                 u32     reserved23              : 1;
  84                 u32     reserved24              : 1;
  85                 u32     reserved25              : 1;
  86                 u32     bus_lock_detected       : 1;
  87                 u32     enclave_mode            : 1;
  88                 u32     smi_pending_mtf         : 1;
  89                 u32     smi_from_vmx_root       : 1;
  90                 u32     reserved30              : 1;
  91                 u32     failed_vmentry          : 1;
  92         };
  93         u32 full;
  94 };
  95
  96 /*
  97  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
  98  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
  99  */
 100 struct nested_vmx {
 101         /* Has the level1 guest done vmxon? */
 102         bool vmxon;
 103         gpa_t vmxon_ptr;
 104         bool pml_full;
 105
 106         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 107         gpa_t current_vmptr;
 108         /*
 109          * Cache of the guest's VMCS, existing outside of guest memory.
 110          * Loaded from guest memory during VMPTRLD. Flushed to guest
 111          * memory during VMCLEAR and VMPTRLD.
 112          */
 113         struct vmcs12 *cached_vmcs12;
 114         /*
 115          * Cache of the guest's shadow VMCS, existing outside of guest
 116          * memory. Loaded from guest memory during VM entry. Flushed
 117          * to guest memory during VM exit.
 118          */
 119         struct vmcs12 *cached_shadow_vmcs12;
 120
 121         /*
 122          * Indicates if the shadow vmcs or enlightened vmcs must be updated
 123          * with the data held by struct vmcs12.
 124          */
 125         bool need_vmcs12_to_shadow_sync;
 126         bool dirty_vmcs12;
 127
 128         /*
 129          * Indicates lazily loaded guest state has not yet been decached from
 130          * vmcs02.
 131          */
 132         bool need_sync_vmcs02_to_vmcs12_rare;
 133
 134         /*
 135          * vmcs02 has been initialized, i.e. state that is constant for
 136          * vmcs02 has been written to the backing VMCS.  Initialization
 137          * is delayed until L1 actually attempts to run a nested VM.
 138          */
 139         bool vmcs02_initialized;
 140
 141         bool change_vmcs01_virtual_apic_mode;
 142         bool reload_vmcs01_apic_access_page;
 143
 144         /*
 145          * Enlightened VMCS has been enabled. It does not mean that L1 has to
 146          * use it. However, VMX features available to L1 will be limited based
 147          * on what the enlightened VMCS supports.
 148          */
 149         bool enlightened_vmcs_enabled;
 150
 151         /* L2 must run next, and mustn't decide to exit to L1. */
 152         bool nested_run_pending;
 153
 154         /* Pending MTF VM-exit into L1.  */
 155         bool mtf_pending;
 156
 157         struct loaded_vmcs vmcs02;
 158
 159         /*
 160          * Guest pages referred to in the vmcs02 with host-physical
 161          * pointers, so we must keep them pinned while L2 runs.
 162          */
 163         struct page *apic_access_page;
 164         struct kvm_host_map virtual_apic_map;
 165         struct kvm_host_map pi_desc_map;
 166
 167         struct kvm_host_map msr_bitmap_map;
 168
 169         struct pi_desc *pi_desc;
 170         bool pi_pending;
 171         u16 posted_intr_nv;
 172
 173         struct hrtimer preemption_timer;
 174         u64 preemption_timer_deadline;
 175         bool has_preemption_timer_deadline;
 176         bool preemption_timer_expired;
 177
 178         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 179         u64 vmcs01_debugctl;
 180         u64 vmcs01_guest_bndcfgs;
 181
 182         /* to migrate it to L1 if L2 writes to L1's CR8 directly */
 183         int l1_tpr_threshold;
 184
 185         u16 vpid02;
 186         u16 last_vpid;
 187
 188         struct nested_vmx_msrs msrs;
 189
 190         /* SMM related state */
 191         struct {
 192                 /* in VMX operation on SMM entry? */
 193                 bool vmxon;
 194                 /* in guest mode on SMM entry? */
 195                 bool guest_mode;
 196         } smm;
 197
 198         gpa_t hv_evmcs_vmptr;
 199         struct kvm_host_map hv_evmcs_map;
 200         struct hv_enlightened_vmcs *hv_evmcs;
 201 };
 202
 203 struct vcpu_vmx {
 204         struct kvm_vcpu       vcpu;
 205         u8                    fail;
 206         u8                    msr_bitmap_mode;
 207
 208         /*
 209          * If true, host state has been stored in vmx->loaded_vmcs for
 210          * the CPU registers that only need to be switched when transitioning
 211          * to/from the kernel, and the registers have been loaded with guest
 212          * values.  If false, host state is loaded in the CPU registers
 213          * and vmx->loaded_vmcs->host_state is invalid.
 214          */
 215         bool                  guest_state_loaded;
 216
 217         unsigned long         exit_qualification;
 218         u32                   exit_intr_info;
 219         u32                   idt_vectoring_info;
 220         ulong                 rflags;
 221
 222         struct vmx_uret_msr   guest_uret_msrs[MAX_NR_USER_RETURN_MSRS];
 223         int                   nr_uret_msrs;
 224         int                   nr_active_uret_msrs;
 225         bool                  guest_uret_msrs_loaded;
 226 #ifdef CONFIG_X86_64
 227         u64                   msr_host_kernel_gs_base;
 228         u64                   msr_guest_kernel_gs_base;
 229 #endif
 230
 231         u64                   spec_ctrl;
 232         u32                   msr_ia32_umwait_control;
 233
 234         u32 secondary_exec_control;
 235
 236         /*
 237          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 238          * non-nested (L1) guest, it always points to vmcs01. For a nested
 239          * guest (L2), it points to a different VMCS.
 240          */
 241         struct loaded_vmcs    vmcs01;
 242         struct loaded_vmcs   *loaded_vmcs;
 243
 244         struct msr_autoload {
 245                 struct vmx_msrs guest;
 246                 struct vmx_msrs host;
 247         } msr_autoload;
 248
 249         struct msr_autostore {
 250                 struct vmx_msrs guest;
 251         } msr_autostore;
 252
 253         struct {
 254                 int vm86_active;
 255                 ulong save_rflags;
 256                 struct kvm_segment segs[8];
 257         } rmode;
 258         struct {
 259                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 260                 struct kvm_save_segment {
 261                         u16 selector;
 262                         unsigned long base;
 263                         u32 limit;
 264                         u32 ar;
 265                 } seg[8];
 266         } segment_cache;
 267         int vpid;
 268         bool emulation_required;
 269
 270         union vmx_exit_reason exit_reason;
 271
 272         /* Posted interrupt descriptor */
 273         struct pi_desc pi_desc;
 274
 275         /* Support for a guest hypervisor (nested VMX) */
 276         struct nested_vmx nested;
 277
 278         /* Dynamic PLE window. */
 279         unsigned int ple_window;
 280         bool ple_window_dirty;
 281
 282         bool req_immediate_exit;
 283
 284         /* Support for PML */
 285 #define PML_ENTITY_NUM          512
 286         struct page *pml_pg;
 287
 288         /* apic deadline value in host tsc */
 289         u64 hv_deadline_tsc;
 290
 291         u64 current_tsc_ratio;
 292
 293         unsigned long host_debugctlmsr;
 294
 295         /*
 296          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
 297          * msr_ia32_feature_control. FEAT_CTL_LOCKED is always included
 298          * in msr_ia32_feature_control_valid_bits.
 299          */
 300         u64 msr_ia32_feature_control;
 301         u64 msr_ia32_feature_control_valid_bits;
 302         u64 ept_pointer;
 303
 304         struct pt_desc pt_desc;
 305
 306         /* Save desired MSR intercept (read: pass-through) state */
 307 #define MAX_POSSIBLE_PASSTHROUGH_MSRS   13
 308         struct {
 309                 DECLARE_BITMAP(read, MAX_POSSIBLE_PASSTHROUGH_MSRS);
 310                 DECLARE_BITMAP(write, MAX_POSSIBLE_PASSTHROUGH_MSRS);
 311         } shadow_msr_intercept;
 312 };
 313
 314 enum ept_pointers_status {
 315         EPT_POINTERS_CHECK = 0,
 316         EPT_POINTERS_MATCH = 1,
 317         EPT_POINTERS_MISMATCH = 2
 318 };
 319
 320 struct kvm_vmx {
 321         struct kvm kvm;
 322
 323         unsigned int tss_addr;
 324         bool ept_identity_pagetable_done;
 325         gpa_t ept_identity_map_addr;
 326
 327         enum ept_pointers_status ept_pointers_match;
 328         spinlock_t ept_pointer_lock;
 329 };
 330
 331 bool nested_vmx_allowed(struct kvm_vcpu *vcpu);
 332 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu,
 333                         struct loaded_vmcs *buddy);
 334 int allocate_vpid(void);
 335 void free_vpid(int vpid);
 336 void vmx_set_constant_host_state(struct vcpu_vmx *vmx);
 337 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu);
 338 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
 339                         unsigned long fs_base, unsigned long gs_base);
 340 int vmx_get_cpl(struct kvm_vcpu *vcpu);
 341 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu);
 342 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
 343 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu);
 344 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask);
 345 int vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer);
 346 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
 347 void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
 348 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx);
 349 void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 350 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
 351 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
 352 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa,
 353                    int root_level);
 354
 355 void update_exception_bitmap(struct kvm_vcpu *vcpu);
 356 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
 357 bool vmx_nmi_blocked(struct kvm_vcpu *vcpu);
 358 bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu);
 359 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
 360 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
 361 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
 362 struct vmx_uret_msr *vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr);
 363 void pt_update_intercept_for_msr(struct kvm_vcpu *vcpu);
 364 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp);
 365 int vmx_find_loadstore_msr_slot(struct vmx_msrs *m, u32 msr);
 366 void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu);
 367 void vmx_set_intercept_for_msr(struct kvm_vcpu *vcpu,
 368         u32 msr, int type, bool value);
 369
 370 static inline u8 vmx_get_rvi(void)
 371 {
 372         return vmcs_read16(GUEST_INTR_STATUS) & 0xff;
 373 }
 374
 375 #define BUILD_CONTROLS_SHADOW(lname, uname)                                 \
 376 static inline void lname##_controls_set(struct vcpu_vmx *vmx, u32 val)      \
 377 {                                                                           \
 378         if (vmx->loaded_vmcs->controls_shadow.lname != val) {               \
 379                 vmcs_write32(uname, val);                                   \
 380                 vmx->loaded_vmcs->controls_shadow.lname = val;              \
 381         }                                                                   \
 382 }                                                                           \
 383 static inline u32 lname##_controls_get(struct vcpu_vmx *vmx)                \
 384 {                                                                           \
 385         return vmx->loaded_vmcs->controls_shadow.lname;                     \
 386 }                                                                           \
 387 static inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u32 val)   \
 388 {                                                                           \
 389         lname##_controls_set(vmx, lname##_controls_get(vmx) | val);         \
 390 }                                                                           \
 391 static inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u32 val) \
 392 {                                                                           \
 393         lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val);        \
 394 }
 395 BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS)
 396 BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS)
 397 BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL)
 398 BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL)
 399 BUILD_CONTROLS_SHADOW(secondary_exec, SECONDARY_VM_EXEC_CONTROL)
 400
 401 static inline void vmx_register_cache_reset(struct kvm_vcpu *vcpu)
 402 {
 403         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
 404                                   | (1 << VCPU_EXREG_RFLAGS)
 405                                   | (1 << VCPU_EXREG_PDPTR)
 406                                   | (1 << VCPU_EXREG_SEGMENTS)
 407                                   | (1 << VCPU_EXREG_CR0)
 408                                   | (1 << VCPU_EXREG_CR3)
 409                                   | (1 << VCPU_EXREG_CR4)
 410                                   | (1 << VCPU_EXREG_EXIT_INFO_1)
 411                                   | (1 << VCPU_EXREG_EXIT_INFO_2));
 412         vcpu->arch.regs_dirty = 0;
 413 }
 414
 415 static inline u32 vmx_vmentry_ctrl(void)
 416 {
 417         u32 vmentry_ctrl = vmcs_config.vmentry_ctrl;
 418         if (vmx_pt_mode_is_system())
 419                 vmentry_ctrl &= ~(VM_ENTRY_PT_CONCEAL_PIP |
 420                                   VM_ENTRY_LOAD_IA32_RTIT_CTL);
 421         /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
 422         return vmentry_ctrl &
 423                 ~(VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VM_ENTRY_LOAD_IA32_EFER);
 424 }
 425
 426 static inline u32 vmx_vmexit_ctrl(void)
 427 {
 428         u32 vmexit_ctrl = vmcs_config.vmexit_ctrl;
 429         if (vmx_pt_mode_is_system())
 430                 vmexit_ctrl &= ~(VM_EXIT_PT_CONCEAL_PIP |
 431                                  VM_EXIT_CLEAR_IA32_RTIT_CTL);
 432         /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
 433         return vmexit_ctrl &
 434                 ~(VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | VM_EXIT_LOAD_IA32_EFER);
 435 }
 436
 437 u32 vmx_exec_control(struct vcpu_vmx *vmx);
 438 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx);
 439
 440 static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm)
 441 {
 442         return container_of(kvm, struct kvm_vmx, kvm);
 443 }
 444
 445 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 446 {
 447         return container_of(vcpu, struct vcpu_vmx, vcpu);
 448 }
 449
 450 static inline unsigned long vmx_get_exit_qual(struct kvm_vcpu *vcpu)
 451 {
 452         struct vcpu_vmx *vmx = to_vmx(vcpu);
 453
 454         if (!kvm_register_is_available(vcpu, VCPU_EXREG_EXIT_INFO_1)) {
 455                 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_1);
 456                 vmx->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
 457         }
 458         return vmx->exit_qualification;
 459 }
 460
 461 static inline u32 vmx_get_intr_info(struct kvm_vcpu *vcpu)
 462 {
 463         struct vcpu_vmx *vmx = to_vmx(vcpu);
 464
 465         if (!kvm_register_is_available(vcpu, VCPU_EXREG_EXIT_INFO_2)) {
 466                 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_2);
 467                 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
 468         }
 469         return vmx->exit_intr_info;
 470 }
 471
 472 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags);
 473 void free_vmcs(struct vmcs *vmcs);
 474 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
 475 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
 476 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs);
 477
 478 static inline struct vmcs *alloc_vmcs(bool shadow)
 479 {
 480         return alloc_vmcs_cpu(shadow, raw_smp_processor_id(),
 481                               GFP_KERNEL_ACCOUNT);
 482 }
 483
 484 static inline void decache_tsc_multiplier(struct vcpu_vmx *vmx)
 485 {
 486         vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
 487         vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
 488 }
 489
 490 static inline bool vmx_has_waitpkg(struct vcpu_vmx *vmx)
 491 {
 492         return vmx->secondary_exec_control &
 493                 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
 494 }
 495
 496 static inline bool vmx_need_pf_intercept(struct kvm_vcpu *vcpu)
 497 {
 498         if (!enable_ept)
 499                 return true;
 500
 501         return allow_smaller_maxphyaddr && cpuid_maxphyaddr(vcpu) < boot_cpu_data.x86_phys_bits;
 502 }
 503
 504 static inline bool is_unrestricted_guest(struct kvm_vcpu *vcpu)
 505 {
 506         return enable_unrestricted_guest && (!is_guest_mode(vcpu) ||
 507             (secondary_exec_controls_get(to_vmx(vcpu)) &
 508             SECONDARY_EXEC_UNRESTRICTED_GUEST));
 509 }
 510
 511 bool __vmx_guest_state_valid(struct kvm_vcpu *vcpu);
 512 static inline bool vmx_guest_state_valid(struct kvm_vcpu *vcpu)
 513 {
 514         return is_unrestricted_guest(vcpu) || __vmx_guest_state_valid(vcpu);
 515 }
 516
 517 void dump_vmcs(void);
 518
 519 #endif /* __KVM_X86_VMX_H */