arch/x86/kvm/vmx/vmx.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Kernel-based Virtual Machine driver for Linux
   4  *
   5  * This module enables machines with Intel VT-x extensions to run virtual
   6  * machines without emulation or binary translation.
   7  *
   8  * Copyright (C) 2006 Qumranet, Inc.
   9  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  10  *
  11  * Authors:
  12  *   Avi Kivity   <avi@qumranet.com>
  13  *   Yaniv Kamay  <yaniv@qumranet.com>
  14  */
  15
  16 #include <linux/frame.h>
  17 #include <linux/highmem.h>
  18 #include <linux/hrtimer.h>
  19 #include <linux/kernel.h>
  20 #include <linux/kvm_host.h>
  21 #include <linux/module.h>
  22 #include <linux/moduleparam.h>
  23 #include <linux/mod_devicetable.h>
  24 #include <linux/mm.h>
  25 #include <linux/sched.h>
  26 #include <linux/sched/smt.h>
  27 #include <linux/slab.h>
  28 #include <linux/tboot.h>
  29 #include <linux/trace_events.h>
  30
  31 #include <asm/apic.h>
  32 #include <asm/asm.h>
  33 #include <asm/cpu.h>
  34 #include <asm/debugreg.h>
  35 #include <asm/desc.h>
  36 #include <asm/fpu/internal.h>
  37 #include <asm/io.h>
  38 #include <asm/irq_remapping.h>
  39 #include <asm/kexec.h>
  40 #include <asm/perf_event.h>
  41 #include <asm/mce.h>
  42 #include <asm/mmu_context.h>
  43 #include <asm/mshyperv.h>
  44 #include <asm/spec-ctrl.h>
  45 #include <asm/virtext.h>
  46 #include <asm/vmx.h>
  47
  48 #include "capabilities.h"
  49 #include "cpuid.h"
  50 #include "evmcs.h"
  51 #include "irq.h"
  52 #include "kvm_cache_regs.h"
  53 #include "lapic.h"
  54 #include "mmu.h"
  55 #include "nested.h"
  56 #include "ops.h"
  57 #include "pmu.h"
  58 #include "trace.h"
  59 #include "vmcs.h"
  60 #include "vmcs12.h"
  61 #include "vmx.h"
  62 #include "x86.h"
  63
  64 MODULE_AUTHOR("Qumranet");
  65 MODULE_LICENSE("GPL");
  66
  67 static const struct x86_cpu_id vmx_cpu_id[] = {
  68         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  69         {}
  70 };
  71 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  72
  73 bool __read_mostly enable_vpid = 1;
  74 module_param_named(vpid, enable_vpid, bool, 0444);
  75
  76 static bool __read_mostly enable_vnmi = 1;
  77 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
  78
  79 bool __read_mostly flexpriority_enabled = 1;
  80 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  81
  82 bool __read_mostly enable_ept = 1;
  83 module_param_named(ept, enable_ept, bool, S_IRUGO);
  84
  85 bool __read_mostly enable_unrestricted_guest = 1;
  86 module_param_named(unrestricted_guest,
  87                         enable_unrestricted_guest, bool, S_IRUGO);
  88
  89 bool __read_mostly enable_ept_ad_bits = 1;
  90 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  91
  92 static bool __read_mostly emulate_invalid_guest_state = true;
  93 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  94
  95 static bool __read_mostly fasteoi = 1;
  96 module_param(fasteoi, bool, S_IRUGO);
  97
  98 static bool __read_mostly enable_apicv = 1;
  99 module_param(enable_apicv, bool, S_IRUGO);
 100
 101 /*
 102  * If nested=1, nested virtualization is supported, i.e., guests may use
 103  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 104  * use VMX instructions.
 105  */
 106 static bool __read_mostly nested = 1;
 107 module_param(nested, bool, S_IRUGO);
 108
 109 static u64 __read_mostly host_xss;
 110
 111 bool __read_mostly enable_pml = 1;
 112 module_param_named(pml, enable_pml, bool, S_IRUGO);
 113
 114 static bool __read_mostly dump_invalid_vmcs = 0;
 115 module_param(dump_invalid_vmcs, bool, 0644);
 116
 117 #define MSR_BITMAP_MODE_X2APIC          1
 118 #define MSR_BITMAP_MODE_X2APIC_APICV    2
 119
 120 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 121
 122 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 123 static int __read_mostly cpu_preemption_timer_multi;
 124 static bool __read_mostly enable_preemption_timer = 1;
 125 #ifdef CONFIG_X86_64
 126 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 127 #endif
 128
 129 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
 130 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
 131 #define KVM_VM_CR0_ALWAYS_ON                            \
 132         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST |      \
 133          X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
 134 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 135         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 136          | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
 137
 138 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
 139 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 140 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 141
 142 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 143
 144 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
 145         RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
 146         RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
 147         RTIT_STATUS_BYTECNT))
 148
 149 #define MSR_IA32_RTIT_OUTPUT_BASE_MASK \
 150         (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f)
 151
 152 /*
 153  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 154  * ple_gap:    upper bound on the amount of time between two successive
 155  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 156  *             According to test, this time is usually smaller than 128 cycles.
 157  * ple_window: upper bound on the amount of time a guest is allowed to execute
 158  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 159  *             less than 2^12 cycles
 160  * Time is measured based on a counter that runs at the same rate as the TSC,
 161  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 162  */
 163 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
 164 module_param(ple_gap, uint, 0444);
 165
 166 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 167 module_param(ple_window, uint, 0444);
 168
 169 /* Default doubles per-vcpu window every exit. */
 170 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 171 module_param(ple_window_grow, uint, 0444);
 172
 173 /* Default resets per-vcpu window every exit to ple_window. */
 174 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 175 module_param(ple_window_shrink, uint, 0444);
 176
 177 /* Default is to compute the maximum so we can never overflow. */
 178 static unsigned int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 179 module_param(ple_window_max, uint, 0444);
 180
 181 /* Default is SYSTEM mode, 1 for host-guest mode */
 182 int __read_mostly pt_mode = PT_MODE_SYSTEM;
 183 module_param(pt_mode, int, S_IRUGO);
 184
 185 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
 186 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
 187 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
 188
 189 /* Storage for pre module init parameter parsing */
 190 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
 191
 192 static const struct {
 193         const char *option;
 194         bool for_parse;
 195 } vmentry_l1d_param[] = {
 196         [VMENTER_L1D_FLUSH_AUTO]         = {"auto", true},
 197         [VMENTER_L1D_FLUSH_NEVER]        = {"never", true},
 198         [VMENTER_L1D_FLUSH_COND]         = {"cond", true},
 199         [VMENTER_L1D_FLUSH_ALWAYS]       = {"always", true},
 200         [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
 201         [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
 202 };
 203
 204 #define L1D_CACHE_ORDER 4
 205 static void *vmx_l1d_flush_pages;
 206
 207 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
 208 {
 209         struct page *page;
 210         unsigned int i;
 211
 212         if (!boot_cpu_has_bug(X86_BUG_L1TF)) {
 213                 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
 214                 return 0;
 215         }
 216
 217         if (!enable_ept) {
 218                 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
 219                 return 0;
 220         }
 221
 222         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
 223                 u64 msr;
 224
 225                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
 226                 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
 227                         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
 228                         return 0;
 229                 }
 230         }
 231
 232         /* If set to auto use the default l1tf mitigation method */
 233         if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
 234                 switch (l1tf_mitigation) {
 235                 case L1TF_MITIGATION_OFF:
 236                         l1tf = VMENTER_L1D_FLUSH_NEVER;
 237                         break;
 238                 case L1TF_MITIGATION_FLUSH_NOWARN:
 239                 case L1TF_MITIGATION_FLUSH:
 240                 case L1TF_MITIGATION_FLUSH_NOSMT:
 241                         l1tf = VMENTER_L1D_FLUSH_COND;
 242                         break;
 243                 case L1TF_MITIGATION_FULL:
 244                 case L1TF_MITIGATION_FULL_FORCE:
 245                         l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 246                         break;
 247                 }
 248         } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
 249                 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 250         }
 251
 252         if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
 253             !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
 254                 /*
 255                  * This allocation for vmx_l1d_flush_pages is not tied to a VM
 256                  * lifetime and so should not be charged to a memcg.
 257                  */
 258                 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
 259                 if (!page)
 260                         return -ENOMEM;
 261                 vmx_l1d_flush_pages = page_address(page);
 262
 263                 /*
 264                  * Initialize each page with a different pattern in
 265                  * order to protect against KSM in the nested
 266                  * virtualization case.
 267                  */
 268                 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
 269                         memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
 270                                PAGE_SIZE);
 271                 }
 272         }
 273
 274         l1tf_vmx_mitigation = l1tf;
 275
 276         if (l1tf != VMENTER_L1D_FLUSH_NEVER)
 277                 static_branch_enable(&vmx_l1d_should_flush);
 278         else
 279                 static_branch_disable(&vmx_l1d_should_flush);
 280
 281         if (l1tf == VMENTER_L1D_FLUSH_COND)
 282                 static_branch_enable(&vmx_l1d_flush_cond);
 283         else
 284                 static_branch_disable(&vmx_l1d_flush_cond);
 285         return 0;
 286 }
 287
 288 static int vmentry_l1d_flush_parse(const char *s)
 289 {
 290         unsigned int i;
 291
 292         if (s) {
 293                 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
 294                         if (vmentry_l1d_param[i].for_parse &&
 295                             sysfs_streq(s, vmentry_l1d_param[i].option))
 296                                 return i;
 297                 }
 298         }
 299         return -EINVAL;
 300 }
 301
 302 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
 303 {
 304         int l1tf, ret;
 305
 306         l1tf = vmentry_l1d_flush_parse(s);
 307         if (l1tf < 0)
 308                 return l1tf;
 309
 310         if (!boot_cpu_has(X86_BUG_L1TF))
 311                 return 0;
 312
 313         /*
 314          * Has vmx_init() run already? If not then this is the pre init
 315          * parameter parsing. In that case just store the value and let
 316          * vmx_init() do the proper setup after enable_ept has been
 317          * established.
 318          */
 319         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
 320                 vmentry_l1d_flush_param = l1tf;
 321                 return 0;
 322         }
 323
 324         mutex_lock(&vmx_l1d_flush_mutex);
 325         ret = vmx_setup_l1d_flush(l1tf);
 326         mutex_unlock(&vmx_l1d_flush_mutex);
 327         return ret;
 328 }
 329
 330 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
 331 {
 332         if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
 333                 return sprintf(s, "???\n");
 334
 335         return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
 336 }
 337
 338 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
 339         .set = vmentry_l1d_flush_set,
 340         .get = vmentry_l1d_flush_get,
 341 };
 342 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
 343
 344 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 345 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 346 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
 347                                                           u32 msr, int type);
 348
 349 void vmx_vmexit(void);
 350
 351 #define vmx_insn_failed(fmt...)         \
 352 do {                                    \
 353         WARN_ONCE(1, fmt);              \
 354         pr_warn_ratelimited(fmt);       \
 355 } while (0)
 356
 357 asmlinkage void vmread_error(unsigned long field, bool fault)
 358 {
 359         if (fault)
 360                 kvm_spurious_fault();
 361         else
 362                 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field);
 363 }
 364
 365 noinline void vmwrite_error(unsigned long field, unsigned long value)
 366 {
 367         vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n",
 368                         field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 369 }
 370
 371 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr)
 372 {
 373         vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr);
 374 }
 375
 376 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr)
 377 {
 378         vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr);
 379 }
 380
 381 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva)
 382 {
 383         vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n",
 384                         ext, vpid, gva);
 385 }
 386
 387 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa)
 388 {
 389         vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n",
 390                         ext, eptp, gpa);
 391 }
 392
 393 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 394 DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 395 /*
 396  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 397  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 398  */
 399 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 400
 401 /*
 402  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 403  * can find which vCPU should be waken up.
 404  */
 405 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 406 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 407
 408 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 409 static DEFINE_SPINLOCK(vmx_vpid_lock);
 410
 411 struct vmcs_config vmcs_config;
 412 struct vmx_capability vmx_capability;
 413
 414 #define VMX_SEGMENT_FIELD(seg)                                  \
 415         [VCPU_SREG_##seg] = {                                   \
 416                 .selector = GUEST_##seg##_SELECTOR,             \
 417                 .base = GUEST_##seg##_BASE,                     \
 418                 .limit = GUEST_##seg##_LIMIT,                   \
 419                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 420         }
 421
 422 static const struct kvm_vmx_segment_field {
 423         unsigned selector;
 424         unsigned base;
 425         unsigned limit;
 426         unsigned ar_bytes;
 427 } kvm_vmx_segment_fields[] = {
 428         VMX_SEGMENT_FIELD(CS),
 429         VMX_SEGMENT_FIELD(DS),
 430         VMX_SEGMENT_FIELD(ES),
 431         VMX_SEGMENT_FIELD(FS),
 432         VMX_SEGMENT_FIELD(GS),
 433         VMX_SEGMENT_FIELD(SS),
 434         VMX_SEGMENT_FIELD(TR),
 435         VMX_SEGMENT_FIELD(LDTR),
 436 };
 437
 438 u64 host_efer;
 439 static unsigned long host_idt_base;
 440
 441 /*
 442  * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
 443  * will emulate SYSCALL in legacy mode if the vendor string in guest
 444  * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
 445  * support this emulation, IA32_STAR must always be included in
 446  * vmx_msr_index[], even in i386 builds.
 447  */
 448 const u32 vmx_msr_index[] = {
 449 #ifdef CONFIG_X86_64
 450         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 451 #endif
 452         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 453 };
 454
 455 #if IS_ENABLED(CONFIG_HYPERV)
 456 static bool __read_mostly enlightened_vmcs = true;
 457 module_param(enlightened_vmcs, bool, 0444);
 458
 459 /* check_ept_pointer() should be under protection of ept_pointer_lock. */
 460 static void check_ept_pointer_match(struct kvm *kvm)
 461 {
 462         struct kvm_vcpu *vcpu;
 463         u64 tmp_eptp = INVALID_PAGE;
 464         int i;
 465
 466         kvm_for_each_vcpu(i, vcpu, kvm) {
 467                 if (!VALID_PAGE(tmp_eptp)) {
 468                         tmp_eptp = to_vmx(vcpu)->ept_pointer;
 469                 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
 470                         to_kvm_vmx(kvm)->ept_pointers_match
 471                                 = EPT_POINTERS_MISMATCH;
 472                         return;
 473                 }
 474         }
 475
 476         to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
 477 }
 478
 479 static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush,
 480                 void *data)
 481 {
 482         struct kvm_tlb_range *range = data;
 483
 484         return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn,
 485                         range->pages);
 486 }
 487
 488 static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm,
 489                 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range)
 490 {
 491         u64 ept_pointer = to_vmx(vcpu)->ept_pointer;
 492
 493         /*
 494          * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address
 495          * of the base of EPT PML4 table, strip off EPT configuration
 496          * information.
 497          */
 498         if (range)
 499                 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK,
 500                                 kvm_fill_hv_flush_list_func, (void *)range);
 501         else
 502                 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK);
 503 }
 504
 505 static int hv_remote_flush_tlb_with_range(struct kvm *kvm,
 506                 struct kvm_tlb_range *range)
 507 {
 508         struct kvm_vcpu *vcpu;
 509         int ret = 0, i;
 510
 511         spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
 512
 513         if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
 514                 check_ept_pointer_match(kvm);
 515
 516         if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
 517                 kvm_for_each_vcpu(i, vcpu, kvm) {
 518                         /* If ept_pointer is invalid pointer, bypass flush request. */
 519                         if (VALID_PAGE(to_vmx(vcpu)->ept_pointer))
 520                                 ret |= __hv_remote_flush_tlb_with_range(
 521                                         kvm, vcpu, range);
 522                 }
 523         } else {
 524                 ret = __hv_remote_flush_tlb_with_range(kvm,
 525                                 kvm_get_vcpu(kvm, 0), range);
 526         }
 527
 528         spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
 529         return ret;
 530 }
 531 static int hv_remote_flush_tlb(struct kvm *kvm)
 532 {
 533         return hv_remote_flush_tlb_with_range(kvm, NULL);
 534 }
 535
 536 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
 537 {
 538         struct hv_enlightened_vmcs *evmcs;
 539         struct hv_partition_assist_pg **p_hv_pa_pg =
 540                         &vcpu->kvm->arch.hyperv.hv_pa_pg;
 541         /*
 542          * Synthetic VM-Exit is not enabled in current code and so All
 543          * evmcs in singe VM shares same assist page.
 544          */
 545         if (!*p_hv_pa_pg)
 546                 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL);
 547
 548         if (!*p_hv_pa_pg)
 549                 return -ENOMEM;
 550
 551         evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
 552
 553         evmcs->partition_assist_page =
 554                 __pa(*p_hv_pa_pg);
 555         evmcs->hv_vm_id = (unsigned long)vcpu->kvm;
 556         evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
 557
 558         return 0;
 559 }
 560
 561 #endif /* IS_ENABLED(CONFIG_HYPERV) */
 562
 563 /*
 564  * Comment's format: document - errata name - stepping - processor name.
 565  * Refer from
 566  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
 567  */
 568 static u32 vmx_preemption_cpu_tfms[] = {
 569 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
 570 0x000206E6,
 571 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
 572 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
 573 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
 574 0x00020652,
 575 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
 576 0x00020655,
 577 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
 578 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
 579 /*
 580  * 320767.pdf - AAP86  - B1 -
 581  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
 582  */
 583 0x000106E5,
 584 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
 585 0x000106A0,
 586 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
 587 0x000106A1,
 588 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
 589 0x000106A4,
 590  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
 591  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
 592  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
 593 0x000106A5,
 594  /* Xeon E3-1220 V2 */
 595 0x000306A8,
 596 };
 597
 598 static inline bool cpu_has_broken_vmx_preemption_timer(void)
 599 {
 600         u32 eax = cpuid_eax(0x00000001), i;
 601
 602         /* Clear the reserved bits */
 603         eax &= ~(0x3U << 14 | 0xfU << 28);
 604         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
 605                 if (eax == vmx_preemption_cpu_tfms[i])
 606                         return true;
 607
 608         return false;
 609 }
 610
 611 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
 612 {
 613         return flexpriority_enabled && lapic_in_kernel(vcpu);
 614 }
 615
 616 static inline bool report_flexpriority(void)
 617 {
 618         return flexpriority_enabled;
 619 }
 620
 621 static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 622 {
 623         int i;
 624
 625         for (i = 0; i < vmx->nmsrs; ++i)
 626                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 627                         return i;
 628         return -1;
 629 }
 630
 631 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 632 {
 633         int i;
 634
 635         i = __find_msr_index(vmx, msr);
 636         if (i >= 0)
 637                 return &vmx->guest_msrs[i];
 638         return NULL;
 639 }
 640
 641 void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
 642 {
 643         vmcs_clear(loaded_vmcs->vmcs);
 644         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
 645                 vmcs_clear(loaded_vmcs->shadow_vmcs);
 646         loaded_vmcs->cpu = -1;
 647         loaded_vmcs->launched = 0;
 648 }
 649
 650 #ifdef CONFIG_KEXEC_CORE
 651 /*
 652  * This bitmap is used to indicate whether the vmclear
 653  * operation is enabled on all cpus. All disabled by
 654  * default.
 655  */
 656 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
 657
 658 static inline void crash_enable_local_vmclear(int cpu)
 659 {
 660         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
 661 }
 662
 663 static inline void crash_disable_local_vmclear(int cpu)
 664 {
 665         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
 666 }
 667
 668 static inline int crash_local_vmclear_enabled(int cpu)
 669 {
 670         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
 671 }
 672
 673 static void crash_vmclear_local_loaded_vmcss(void)
 674 {
 675         int cpu = raw_smp_processor_id();
 676         struct loaded_vmcs *v;
 677
 678         if (!crash_local_vmclear_enabled(cpu))
 679                 return;
 680
 681         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
 682                             loaded_vmcss_on_cpu_link)
 683                 vmcs_clear(v->vmcs);
 684 }
 685 #else
 686 static inline void crash_enable_local_vmclear(int cpu) { }
 687 static inline void crash_disable_local_vmclear(int cpu) { }
 688 #endif /* CONFIG_KEXEC_CORE */
 689
 690 static void __loaded_vmcs_clear(void *arg)
 691 {
 692         struct loaded_vmcs *loaded_vmcs = arg;
 693         int cpu = raw_smp_processor_id();
 694
 695         if (loaded_vmcs->cpu != cpu)
 696                 return; /* vcpu migration can race with cpu offline */
 697         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
 698                 per_cpu(current_vmcs, cpu) = NULL;
 699         crash_disable_local_vmclear(cpu);
 700         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
 701
 702         /*
 703          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
 704          * is before setting loaded_vmcs->vcpu to -1 which is done in
 705          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
 706          * then adds the vmcs into percpu list before it is deleted.
 707          */
 708         smp_wmb();
 709
 710         loaded_vmcs_init(loaded_vmcs);
 711         crash_enable_local_vmclear(cpu);
 712 }
 713
 714 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
 715 {
 716         int cpu = loaded_vmcs->cpu;
 717
 718         if (cpu != -1)
 719                 smp_call_function_single(cpu,
 720                          __loaded_vmcs_clear, loaded_vmcs, 1);
 721 }
 722
 723 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
 724                                        unsigned field)
 725 {
 726         bool ret;
 727         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
 728
 729         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
 730                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
 731                 vmx->segment_cache.bitmask = 0;
 732         }
 733         ret = vmx->segment_cache.bitmask & mask;
 734         vmx->segment_cache.bitmask |= mask;
 735         return ret;
 736 }
 737
 738 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
 739 {
 740         u16 *p = &vmx->segment_cache.seg[seg].selector;
 741
 742         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
 743                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
 744         return *p;
 745 }
 746
 747 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
 748 {
 749         ulong *p = &vmx->segment_cache.seg[seg].base;
 750
 751         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
 752                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
 753         return *p;
 754 }
 755
 756 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
 757 {
 758         u32 *p = &vmx->segment_cache.seg[seg].limit;
 759
 760         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
 761                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
 762         return *p;
 763 }
 764
 765 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
 766 {
 767         u32 *p = &vmx->segment_cache.seg[seg].ar;
 768
 769         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
 770                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
 771         return *p;
 772 }
 773
 774 void update_exception_bitmap(struct kvm_vcpu *vcpu)
 775 {
 776         u32 eb;
 777
 778         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
 779              (1u << DB_VECTOR) | (1u << AC_VECTOR);
 780         /*
 781          * Guest access to VMware backdoor ports could legitimately
 782          * trigger #GP because of TSS I/O permission bitmap.
 783          * We intercept those #GP and allow access to them anyway
 784          * as VMware does.
 785          */
 786         if (enable_vmware_backdoor)
 787                 eb |= (1u << GP_VECTOR);
 788         if ((vcpu->guest_debug &
 789              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
 790             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
 791                 eb |= 1u << BP_VECTOR;
 792         if (to_vmx(vcpu)->rmode.vm86_active)
 793                 eb = ~0;
 794         if (enable_ept)
 795                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 796
 797         /* When we are running a nested L2 guest and L1 specified for it a
 798          * certain exception bitmap, we must trap the same exceptions and pass
 799          * them to L1. When running L2, we will only handle the exceptions
 800          * specified above if L1 did not want them.
 801          */
 802         if (is_guest_mode(vcpu))
 803                 eb |= get_vmcs12(vcpu)->exception_bitmap;
 804
 805         vmcs_write32(EXCEPTION_BITMAP, eb);
 806 }
 807
 808 /*
 809  * Check if MSR is intercepted for currently loaded MSR bitmap.
 810  */
 811 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
 812 {
 813         unsigned long *msr_bitmap;
 814         int f = sizeof(unsigned long);
 815
 816         if (!cpu_has_vmx_msr_bitmap())
 817                 return true;
 818
 819         msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
 820
 821         if (msr <= 0x1fff) {
 822                 return !!test_bit(msr, msr_bitmap + 0x800 / f);
 823         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
 824                 msr &= 0x1fff;
 825                 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
 826         }
 827
 828         return true;
 829 }
 830
 831 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
 832                 unsigned long entry, unsigned long exit)
 833 {
 834         vm_entry_controls_clearbit(vmx, entry);
 835         vm_exit_controls_clearbit(vmx, exit);
 836 }
 837
 838 static int find_msr(struct vmx_msrs *m, unsigned int msr)
 839 {
 840         unsigned int i;
 841
 842         for (i = 0; i < m->nr; ++i) {
 843                 if (m->val[i].index == msr)
 844                         return i;
 845         }
 846         return -ENOENT;
 847 }
 848
 849 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
 850 {
 851         int i;
 852         struct msr_autoload *m = &vmx->msr_autoload;
 853
 854         switch (msr) {
 855         case MSR_EFER:
 856                 if (cpu_has_load_ia32_efer()) {
 857                         clear_atomic_switch_msr_special(vmx,
 858                                         VM_ENTRY_LOAD_IA32_EFER,
 859                                         VM_EXIT_LOAD_IA32_EFER);
 860                         return;
 861                 }
 862                 break;
 863         case MSR_CORE_PERF_GLOBAL_CTRL:
 864                 if (cpu_has_load_perf_global_ctrl()) {
 865                         clear_atomic_switch_msr_special(vmx,
 866                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
 867                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
 868                         return;
 869                 }
 870                 break;
 871         }
 872         i = find_msr(&m->guest, msr);
 873         if (i < 0)
 874                 goto skip_guest;
 875         --m->guest.nr;
 876         m->guest.val[i] = m->guest.val[m->guest.nr];
 877         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
 878
 879 skip_guest:
 880         i = find_msr(&m->host, msr);
 881         if (i < 0)
 882                 return;
 883
 884         --m->host.nr;
 885         m->host.val[i] = m->host.val[m->host.nr];
 886         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
 887 }
 888
 889 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
 890                 unsigned long entry, unsigned long exit,
 891                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
 892                 u64 guest_val, u64 host_val)
 893 {
 894         vmcs_write64(guest_val_vmcs, guest_val);
 895         if (host_val_vmcs != HOST_IA32_EFER)
 896                 vmcs_write64(host_val_vmcs, host_val);
 897         vm_entry_controls_setbit(vmx, entry);
 898         vm_exit_controls_setbit(vmx, exit);
 899 }
 900
 901 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
 902                                   u64 guest_val, u64 host_val, bool entry_only)
 903 {
 904         int i, j = 0;
 905         struct msr_autoload *m = &vmx->msr_autoload;
 906
 907         switch (msr) {
 908         case MSR_EFER:
 909                 if (cpu_has_load_ia32_efer()) {
 910                         add_atomic_switch_msr_special(vmx,
 911                                         VM_ENTRY_LOAD_IA32_EFER,
 912                                         VM_EXIT_LOAD_IA32_EFER,
 913                                         GUEST_IA32_EFER,
 914                                         HOST_IA32_EFER,
 915                                         guest_val, host_val);
 916                         return;
 917                 }
 918                 break;
 919         case MSR_CORE_PERF_GLOBAL_CTRL:
 920                 if (cpu_has_load_perf_global_ctrl()) {
 921                         add_atomic_switch_msr_special(vmx,
 922                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
 923                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
 924                                         GUEST_IA32_PERF_GLOBAL_CTRL,
 925                                         HOST_IA32_PERF_GLOBAL_CTRL,
 926                                         guest_val, host_val);
 927                         return;
 928                 }
 929                 break;
 930         case MSR_IA32_PEBS_ENABLE:
 931                 /* PEBS needs a quiescent period after being disabled (to write
 932                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
 933                  * provide that period, so a CPU could write host's record into
 934                  * guest's memory.
 935                  */
 936                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
 937         }
 938
 939         i = find_msr(&m->guest, msr);
 940         if (!entry_only)
 941                 j = find_msr(&m->host, msr);
 942
 943         if ((i < 0 && m->guest.nr == NR_AUTOLOAD_MSRS) ||
 944                 (j < 0 &&  m->host.nr == NR_AUTOLOAD_MSRS)) {
 945                 printk_once(KERN_WARNING "Not enough msr switch entries. "
 946                                 "Can't add msr %x\n", msr);
 947                 return;
 948         }
 949         if (i < 0) {
 950                 i = m->guest.nr++;
 951                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
 952         }
 953         m->guest.val[i].index = msr;
 954         m->guest.val[i].value = guest_val;
 955
 956         if (entry_only)
 957                 return;
 958
 959         if (j < 0) {
 960                 j = m->host.nr++;
 961                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
 962         }
 963         m->host.val[j].index = msr;
 964         m->host.val[j].value = host_val;
 965 }
 966
 967 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
 968 {
 969         u64 guest_efer = vmx->vcpu.arch.efer;
 970         u64 ignore_bits = 0;
 971
 972         /* Shadow paging assumes NX to be available.  */
 973         if (!enable_ept)
 974                 guest_efer |= EFER_NX;
 975
 976         /*
 977          * LMA and LME handled by hardware; SCE meaningless outside long mode.
 978          */
 979         ignore_bits |= EFER_SCE;
 980 #ifdef CONFIG_X86_64
 981         ignore_bits |= EFER_LMA | EFER_LME;
 982         /* SCE is meaningful only in long mode on Intel */
 983         if (guest_efer & EFER_LMA)
 984                 ignore_bits &= ~(u64)EFER_SCE;
 985 #endif
 986
 987         /*
 988          * On EPT, we can't emulate NX, so we must switch EFER atomically.
 989          * On CPUs that support "load IA32_EFER", always switch EFER
 990          * atomically, since it's faster than switching it manually.
 991          */
 992         if (cpu_has_load_ia32_efer() ||
 993             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
 994                 if (!(guest_efer & EFER_LMA))
 995                         guest_efer &= ~EFER_LME;
 996                 if (guest_efer != host_efer)
 997                         add_atomic_switch_msr(vmx, MSR_EFER,
 998                                               guest_efer, host_efer, false);
 999                 else
1000                         clear_atomic_switch_msr(vmx, MSR_EFER);
1001                 return false;
1002         } else {
1003                 clear_atomic_switch_msr(vmx, MSR_EFER);
1004
1005                 guest_efer &= ~ignore_bits;
1006                 guest_efer |= host_efer & ignore_bits;
1007
1008                 vmx->guest_msrs[efer_offset].data = guest_efer;
1009                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1010
1011                 return true;
1012         }
1013 }
1014
1015 #ifdef CONFIG_X86_32
1016 /*
1017  * On 32-bit kernels, VM exits still load the FS and GS bases from the
1018  * VMCS rather than the segment table.  KVM uses this helper to figure
1019  * out the current bases to poke them into the VMCS before entry.
1020  */
1021 static unsigned long segment_base(u16 selector)
1022 {
1023         struct desc_struct *table;
1024         unsigned long v;
1025
1026         if (!(selector & ~SEGMENT_RPL_MASK))
1027                 return 0;
1028
1029         table = get_current_gdt_ro();
1030
1031         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
1032                 u16 ldt_selector = kvm_read_ldt();
1033
1034                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
1035                         return 0;
1036
1037                 table = (struct desc_struct *)segment_base(ldt_selector);
1038         }
1039         v = get_desc_base(&table[selector >> 3]);
1040         return v;
1041 }
1042 #endif
1043
1044 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
1045 {
1046         u32 i;
1047
1048         wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1049         wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1050         wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1051         wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1052         for (i = 0; i < addr_range; i++) {
1053                 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1054                 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1055         }
1056 }
1057
1058 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
1059 {
1060         u32 i;
1061
1062         rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1063         rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1064         rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1065         rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1066         for (i = 0; i < addr_range; i++) {
1067                 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1068                 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1069         }
1070 }
1071
1072 static void pt_guest_enter(struct vcpu_vmx *vmx)
1073 {
1074         if (pt_mode == PT_MODE_SYSTEM)
1075                 return;
1076
1077         /*
1078          * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1079          * Save host state before VM entry.
1080          */
1081         rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1082         if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1083                 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1084                 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1085                 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1086         }
1087 }
1088
1089 static void pt_guest_exit(struct vcpu_vmx *vmx)
1090 {
1091         if (pt_mode == PT_MODE_SYSTEM)
1092                 return;
1093
1094         if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1095                 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1096                 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1097         }
1098
1099         /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1100         wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1101 }
1102
1103 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1104                         unsigned long fs_base, unsigned long gs_base)
1105 {
1106         if (unlikely(fs_sel != host->fs_sel)) {
1107                 if (!(fs_sel & 7))
1108                         vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1109                 else
1110                         vmcs_write16(HOST_FS_SELECTOR, 0);
1111                 host->fs_sel = fs_sel;
1112         }
1113         if (unlikely(gs_sel != host->gs_sel)) {
1114                 if (!(gs_sel & 7))
1115                         vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1116                 else
1117                         vmcs_write16(HOST_GS_SELECTOR, 0);
1118                 host->gs_sel = gs_sel;
1119         }
1120         if (unlikely(fs_base != host->fs_base)) {
1121                 vmcs_writel(HOST_FS_BASE, fs_base);
1122                 host->fs_base = fs_base;
1123         }
1124         if (unlikely(gs_base != host->gs_base)) {
1125                 vmcs_writel(HOST_GS_BASE, gs_base);
1126                 host->gs_base = gs_base;
1127         }
1128 }
1129
1130 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1131 {
1132         struct vcpu_vmx *vmx = to_vmx(vcpu);
1133         struct vmcs_host_state *host_state;
1134 #ifdef CONFIG_X86_64
1135         int cpu = raw_smp_processor_id();
1136 #endif
1137         unsigned long fs_base, gs_base;
1138         u16 fs_sel, gs_sel;
1139         int i;
1140
1141         vmx->req_immediate_exit = false;
1142
1143         /*
1144          * Note that guest MSRs to be saved/restored can also be changed
1145          * when guest state is loaded. This happens when guest transitions
1146          * to/from long-mode by setting MSR_EFER.LMA.
1147          */
1148         if (!vmx->guest_msrs_ready) {
1149                 vmx->guest_msrs_ready = true;
1150                 for (i = 0; i < vmx->save_nmsrs; ++i)
1151                         kvm_set_shared_msr(vmx->guest_msrs[i].index,
1152                                            vmx->guest_msrs[i].data,
1153                                            vmx->guest_msrs[i].mask);
1154
1155         }
1156         if (vmx->guest_state_loaded)
1157                 return;
1158
1159         host_state = &vmx->loaded_vmcs->host_state;
1160
1161         /*
1162          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1163          * allow segment selectors with cpl > 0 or ti == 1.
1164          */
1165         host_state->ldt_sel = kvm_read_ldt();
1166
1167 #ifdef CONFIG_X86_64
1168         savesegment(ds, host_state->ds_sel);
1169         savesegment(es, host_state->es_sel);
1170
1171         gs_base = cpu_kernelmode_gs_base(cpu);
1172         if (likely(is_64bit_mm(current->mm))) {
1173                 save_fsgs_for_kvm();
1174                 fs_sel = current->thread.fsindex;
1175                 gs_sel = current->thread.gsindex;
1176                 fs_base = current->thread.fsbase;
1177                 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
1178         } else {
1179                 savesegment(fs, fs_sel);
1180                 savesegment(gs, gs_sel);
1181                 fs_base = read_msr(MSR_FS_BASE);
1182                 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
1183         }
1184
1185         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1186 #else
1187         savesegment(fs, fs_sel);
1188         savesegment(gs, gs_sel);
1189         fs_base = segment_base(fs_sel);
1190         gs_base = segment_base(gs_sel);
1191 #endif
1192
1193         vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
1194         vmx->guest_state_loaded = true;
1195 }
1196
1197 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
1198 {
1199         struct vmcs_host_state *host_state;
1200
1201         if (!vmx->guest_state_loaded)
1202                 return;
1203
1204         host_state = &vmx->loaded_vmcs->host_state;
1205
1206         ++vmx->vcpu.stat.host_state_reload;
1207
1208 #ifdef CONFIG_X86_64
1209         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1210 #endif
1211         if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1212                 kvm_load_ldt(host_state->ldt_sel);
1213 #ifdef CONFIG_X86_64
1214                 load_gs_index(host_state->gs_sel);
1215 #else
1216                 loadsegment(gs, host_state->gs_sel);
1217 #endif
1218         }
1219         if (host_state->fs_sel & 7)
1220                 loadsegment(fs, host_state->fs_sel);
1221 #ifdef CONFIG_X86_64
1222         if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1223                 loadsegment(ds, host_state->ds_sel);
1224                 loadsegment(es, host_state->es_sel);
1225         }
1226 #endif
1227         invalidate_tss_limit();
1228 #ifdef CONFIG_X86_64
1229         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1230 #endif
1231         load_fixmap_gdt(raw_smp_processor_id());
1232         vmx->guest_state_loaded = false;
1233         vmx->guest_msrs_ready = false;
1234 }
1235
1236 #ifdef CONFIG_X86_64
1237 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
1238 {
1239         preempt_disable();
1240         if (vmx->guest_state_loaded)
1241                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1242         preempt_enable();
1243         return vmx->msr_guest_kernel_gs_base;
1244 }
1245
1246 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1247 {
1248         preempt_disable();
1249         if (vmx->guest_state_loaded)
1250                 wrmsrl(MSR_KERNEL_GS_BASE, data);
1251         preempt_enable();
1252         vmx->msr_guest_kernel_gs_base = data;
1253 }
1254 #endif
1255
1256 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1257 {
1258         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1259         struct pi_desc old, new;
1260         unsigned int dest;
1261
1262         /*
1263          * In case of hot-plug or hot-unplug, we may have to undo
1264          * vmx_vcpu_pi_put even if there is no assigned device.  And we
1265          * always keep PI.NDST up to date for simplicity: it makes the
1266          * code easier, and CPU migration is not a fast path.
1267          */
1268         if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
1269                 return;
1270
1271         /*
1272          * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
1273          * PI.NDST: pi_post_block is the one expected to change PID.NDST and the
1274          * wakeup handler expects the vCPU to be on the blocked_vcpu_list that
1275          * matches PI.NDST. Otherwise, a vcpu may not be able to be woken up
1276          * correctly.
1277          */
1278         if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || vcpu->cpu == cpu) {
1279                 pi_clear_sn(pi_desc);
1280                 goto after_clear_sn;
1281         }
1282
1283         /* The full case.  */
1284         do {
1285                 old.control = new.control = pi_desc->control;
1286
1287                 dest = cpu_physical_id(cpu);
1288
1289                 if (x2apic_enabled())
1290                         new.ndst = dest;
1291                 else
1292                         new.ndst = (dest << 8) & 0xFF00;
1293
1294                 new.sn = 0;
1295         } while (cmpxchg64(&pi_desc->control, old.control,
1296                            new.control) != old.control);
1297
1298 after_clear_sn:
1299
1300         /*
1301          * Clear SN before reading the bitmap.  The VT-d firmware
1302          * writes the bitmap and reads SN atomically (5.2.3 in the
1303          * spec), so it doesn't really have a memory barrier that
1304          * pairs with this, but we cannot do that and we need one.
1305          */
1306         smp_mb__after_atomic();
1307
1308         if (!pi_is_pir_empty(pi_desc))
1309                 pi_set_on(pi_desc);
1310 }
1311
1312 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu)
1313 {
1314         struct vcpu_vmx *vmx = to_vmx(vcpu);
1315         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
1316
1317         if (!already_loaded) {
1318                 loaded_vmcs_clear(vmx->loaded_vmcs);
1319                 local_irq_disable();
1320                 crash_disable_local_vmclear(cpu);
1321
1322                 /*
1323                  * Read loaded_vmcs->cpu should be before fetching
1324                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1325                  * See the comments in __loaded_vmcs_clear().
1326                  */
1327                 smp_rmb();
1328
1329                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1330                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1331                 crash_enable_local_vmclear(cpu);
1332                 local_irq_enable();
1333         }
1334
1335         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1336                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1337                 vmcs_load(vmx->loaded_vmcs->vmcs);
1338                 indirect_branch_prediction_barrier();
1339         }
1340
1341         if (!already_loaded) {
1342                 void *gdt = get_current_gdt_ro();
1343                 unsigned long sysenter_esp;
1344
1345                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1346
1347                 /*
1348                  * Linux uses per-cpu TSS and GDT, so set these when switching
1349                  * processors.  See 22.2.4.
1350                  */
1351                 vmcs_writel(HOST_TR_BASE,
1352                             (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
1353                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
1354
1355                 /*
1356                  * VM exits change the host TR limit to 0x67 after a VM
1357                  * exit.  This is okay, since 0x67 covers everything except
1358                  * the IO bitmap and have have code to handle the IO bitmap
1359                  * being lost after a VM exit.
1360                  */
1361                 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
1362
1363                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1364                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1365
1366                 vmx->loaded_vmcs->cpu = cpu;
1367         }
1368
1369         /* Setup TSC multiplier */
1370         if (kvm_has_tsc_control &&
1371             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
1372                 decache_tsc_multiplier(vmx);
1373 }
1374
1375 /*
1376  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1377  * vcpu mutex is already taken.
1378  */
1379 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1380 {
1381         struct vcpu_vmx *vmx = to_vmx(vcpu);
1382
1383         vmx_vcpu_load_vmcs(vcpu, cpu);
1384
1385         vmx_vcpu_pi_load(vcpu, cpu);
1386
1387         vmx->host_pkru = read_pkru();
1388         vmx->host_debugctlmsr = get_debugctlmsr();
1389 }
1390
1391 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
1392 {
1393         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1394
1395         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1396                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
1397                 !kvm_vcpu_apicv_active(vcpu))
1398                 return;
1399
1400         /* Set SN when the vCPU is preempted */
1401         if (vcpu->preempted)
1402                 pi_set_sn(pi_desc);
1403 }
1404
1405 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1406 {
1407         vmx_vcpu_pi_put(vcpu);
1408
1409         vmx_prepare_switch_to_host(to_vmx(vcpu));
1410 }
1411
1412 static bool emulation_required(struct kvm_vcpu *vcpu)
1413 {
1414         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
1415 }
1416
1417 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1418
1419 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1420 {
1421         unsigned long rflags, save_rflags;
1422
1423         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1424                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1425                 rflags = vmcs_readl(GUEST_RFLAGS);
1426                 if (to_vmx(vcpu)->rmode.vm86_active) {
1427                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1428                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1429                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1430                 }
1431                 to_vmx(vcpu)->rflags = rflags;
1432         }
1433         return to_vmx(vcpu)->rflags;
1434 }
1435
1436 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1437 {
1438         unsigned long old_rflags = vmx_get_rflags(vcpu);
1439
1440         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1441         to_vmx(vcpu)->rflags = rflags;
1442         if (to_vmx(vcpu)->rmode.vm86_active) {
1443                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1444                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1445         }
1446         vmcs_writel(GUEST_RFLAGS, rflags);
1447
1448         if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
1449                 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
1450 }
1451
1452 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1453 {
1454         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1455         int ret = 0;
1456
1457         if (interruptibility & GUEST_INTR_STATE_STI)
1458                 ret |= KVM_X86_SHADOW_INT_STI;
1459         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1460                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1461
1462         return ret;
1463 }
1464
1465 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1466 {
1467         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1468         u32 interruptibility = interruptibility_old;
1469
1470         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1471
1472         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1473                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1474         else if (mask & KVM_X86_SHADOW_INT_STI)
1475                 interruptibility |= GUEST_INTR_STATE_STI;
1476
1477         if ((interruptibility != interruptibility_old))
1478                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1479 }
1480
1481 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1482 {
1483         struct vcpu_vmx *vmx = to_vmx(vcpu);
1484         unsigned long value;
1485
1486         /*
1487          * Any MSR write that attempts to change bits marked reserved will
1488          * case a #GP fault.
1489          */
1490         if (data & vmx->pt_desc.ctl_bitmask)
1491                 return 1;
1492
1493         /*
1494          * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1495          * result in a #GP unless the same write also clears TraceEn.
1496          */
1497         if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1498                 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1499                 return 1;
1500
1501         /*
1502          * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1503          * and FabricEn would cause #GP, if
1504          * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1505          */
1506         if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1507                 !(data & RTIT_CTL_FABRIC_EN) &&
1508                 !intel_pt_validate_cap(vmx->pt_desc.caps,
1509                                         PT_CAP_single_range_output))
1510                 return 1;
1511
1512         /*
1513          * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1514          * utilize encodings marked reserved will casue a #GP fault.
1515          */
1516         value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1517         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1518                         !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1519                         RTIT_CTL_MTC_RANGE_OFFSET, &value))
1520                 return 1;
1521         value = intel_pt_validate_cap(vmx->pt_desc.caps,
1522                                                 PT_CAP_cycle_thresholds);
1523         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1524                         !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1525                         RTIT_CTL_CYC_THRESH_OFFSET, &value))
1526                 return 1;
1527         value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1528         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1529                         !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1530                         RTIT_CTL_PSB_FREQ_OFFSET, &value))
1531                 return 1;
1532
1533         /*
1534          * If ADDRx_CFG is reserved or the encodings is >2 will
1535          * cause a #GP fault.
1536          */
1537         value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1538         if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
1539                 return 1;
1540         value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1541         if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
1542                 return 1;
1543         value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1544         if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
1545                 return 1;
1546         value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1547         if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
1548                 return 1;
1549
1550         return 0;
1551 }
1552
1553 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
1554 {
1555         unsigned long rip;
1556
1557         /*
1558          * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
1559          * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
1560          * set when EPT misconfig occurs.  In practice, real hardware updates
1561          * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
1562          * (namely Hyper-V) don't set it due to it being undefined behavior,
1563          * i.e. we end up advancing IP with some random value.
1564          */
1565         if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
1566             to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) {
1567                 rip = kvm_rip_read(vcpu);
1568                 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1569                 kvm_rip_write(vcpu, rip);
1570         } else {
1571                 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
1572                         return 0;
1573         }
1574
1575         /* skipping an emulated instruction also counts */
1576         vmx_set_interrupt_shadow(vcpu, 0);
1577
1578         return 1;
1579 }
1580
1581 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1582 {
1583         /*
1584          * Ensure that we clear the HLT state in the VMCS.  We don't need to
1585          * explicitly skip the instruction because if the HLT state is set,
1586          * then the instruction is already executing and RIP has already been
1587          * advanced.
1588          */
1589         if (kvm_hlt_in_guest(vcpu->kvm) &&
1590                         vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1591                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1592 }
1593
1594 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
1595 {
1596         struct vcpu_vmx *vmx = to_vmx(vcpu);
1597         unsigned nr = vcpu->arch.exception.nr;
1598         bool has_error_code = vcpu->arch.exception.has_error_code;
1599         u32 error_code = vcpu->arch.exception.error_code;
1600         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1601
1602         kvm_deliver_exception_payload(vcpu);
1603
1604         if (has_error_code) {
1605                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1606                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1607         }
1608
1609         if (vmx->rmode.vm86_active) {
1610                 int inc_eip = 0;
1611                 if (kvm_exception_is_soft(nr))
1612                         inc_eip = vcpu->arch.event_exit_inst_len;
1613                 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
1614                 return;
1615         }
1616
1617         WARN_ON_ONCE(vmx->emulation_required);
1618
1619         if (kvm_exception_is_soft(nr)) {
1620                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1621                              vmx->vcpu.arch.event_exit_inst_len);
1622                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1623         } else
1624                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1625
1626         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1627
1628         vmx_clear_hlt(vcpu);
1629 }
1630
1631 static bool vmx_rdtscp_supported(void)
1632 {
1633         return cpu_has_vmx_rdtscp();
1634 }
1635
1636 static bool vmx_invpcid_supported(void)
1637 {
1638         return cpu_has_vmx_invpcid();
1639 }
1640
1641 /*
1642  * Swap MSR entry in host/guest MSR entry array.
1643  */
1644 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1645 {
1646         struct shared_msr_entry tmp;
1647
1648         tmp = vmx->guest_msrs[to];
1649         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1650         vmx->guest_msrs[from] = tmp;
1651 }
1652
1653 /*
1654  * Set up the vmcs to automatically save and restore system
1655  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1656  * mode, as fiddling with msrs is very expensive.
1657  */
1658 static void setup_msrs(struct vcpu_vmx *vmx)
1659 {
1660         int save_nmsrs, index;
1661
1662         save_nmsrs = 0;
1663 #ifdef CONFIG_X86_64
1664         /*
1665          * The SYSCALL MSRs are only needed on long mode guests, and only
1666          * when EFER.SCE is set.
1667          */
1668         if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) {
1669                 index = __find_msr_index(vmx, MSR_STAR);
1670                 if (index >= 0)
1671                         move_msr_up(vmx, index, save_nmsrs++);
1672                 index = __find_msr_index(vmx, MSR_LSTAR);
1673                 if (index >= 0)
1674                         move_msr_up(vmx, index, save_nmsrs++);
1675                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1676                 if (index >= 0)
1677                         move_msr_up(vmx, index, save_nmsrs++);
1678         }
1679 #endif
1680         index = __find_msr_index(vmx, MSR_EFER);
1681         if (index >= 0 && update_transition_efer(vmx, index))
1682                 move_msr_up(vmx, index, save_nmsrs++);
1683         index = __find_msr_index(vmx, MSR_TSC_AUX);
1684         if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
1685                 move_msr_up(vmx, index, save_nmsrs++);
1686
1687         vmx->save_nmsrs = save_nmsrs;
1688         vmx->guest_msrs_ready = false;
1689
1690         if (cpu_has_vmx_msr_bitmap())
1691                 vmx_update_msr_bitmap(&vmx->vcpu);
1692 }
1693
1694 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1695 {
1696         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1697
1698         if (is_guest_mode(vcpu) &&
1699             (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
1700                 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
1701
1702         return vcpu->arch.tsc_offset;
1703 }
1704
1705 static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1706 {
1707         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1708         u64 g_tsc_offset = 0;
1709
1710         /*
1711          * We're here if L1 chose not to trap WRMSR to TSC. According
1712          * to the spec, this should set L1's TSC; The offset that L1
1713          * set for L2 remains unchanged, and still needs to be added
1714          * to the newly set TSC to get L2's TSC.
1715          */
1716         if (is_guest_mode(vcpu) &&
1717             (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
1718                 g_tsc_offset = vmcs12->tsc_offset;
1719
1720         trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1721                                    vcpu->arch.tsc_offset - g_tsc_offset,
1722                                    offset);
1723         vmcs_write64(TSC_OFFSET, offset + g_tsc_offset);
1724         return offset + g_tsc_offset;
1725 }
1726
1727 /*
1728  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1729  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1730  * all guests if the "nested" module option is off, and can also be disabled
1731  * for a single guest by disabling its VMX cpuid bit.
1732  */
1733 bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1734 {
1735         return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
1736 }
1737
1738 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1739                                                  uint64_t val)
1740 {
1741         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
1742
1743         return !(val & ~valid_bits);
1744 }
1745
1746 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
1747 {
1748         switch (msr->index) {
1749         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1750                 if (!nested)
1751                         return 1;
1752                 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1753         default:
1754                 return 1;
1755         }
1756
1757         return 0;
1758 }
1759
1760 /*
1761  * Reads an msr value (of 'msr_index') into 'pdata'.
1762  * Returns 0 on success, non-0 otherwise.
1763  * Assumes vcpu_load() was already called.
1764  */
1765 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1766 {
1767         struct vcpu_vmx *vmx = to_vmx(vcpu);
1768         struct shared_msr_entry *msr;
1769         u32 index;
1770
1771         switch (msr_info->index) {
1772 #ifdef CONFIG_X86_64
1773         case MSR_FS_BASE:
1774                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
1775                 break;
1776         case MSR_GS_BASE:
1777                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
1778                 break;
1779         case MSR_KERNEL_GS_BASE:
1780                 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
1781                 break;
1782 #endif
1783         case MSR_EFER:
1784                 return kvm_get_msr_common(vcpu, msr_info);
1785         case MSR_IA32_UMWAIT_CONTROL:
1786                 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1787                         return 1;
1788
1789                 msr_info->data = vmx->msr_ia32_umwait_control;
1790                 break;
1791         case MSR_IA32_SPEC_CTRL:
1792                 if (!msr_info->host_initiated &&
1793                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1794                         return 1;
1795
1796                 msr_info->data = to_vmx(vcpu)->spec_ctrl;
1797                 break;
1798         case MSR_IA32_SYSENTER_CS:
1799                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
1800                 break;
1801         case MSR_IA32_SYSENTER_EIP:
1802                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
1803                 break;
1804         case MSR_IA32_SYSENTER_ESP:
1805                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
1806                 break;
1807         case MSR_IA32_BNDCFGS:
1808                 if (!kvm_mpx_supported() ||
1809                     (!msr_info->host_initiated &&
1810                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1811                         return 1;
1812                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
1813                 break;
1814         case MSR_IA32_MCG_EXT_CTL:
1815                 if (!msr_info->host_initiated &&
1816                     !(vmx->msr_ia32_feature_control &
1817                       FEATURE_CONTROL_LMCE))
1818                         return 1;
1819                 msr_info->data = vcpu->arch.mcg_ext_ctl;
1820                 break;
1821         case MSR_IA32_FEATURE_CONTROL:
1822                 msr_info->data = vmx->msr_ia32_feature_control;
1823                 break;
1824         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1825                 if (!nested_vmx_allowed(vcpu))
1826                         return 1;
1827                 return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1828                                        &msr_info->data);
1829         case MSR_IA32_XSS:
1830                 if (!vmx_xsaves_supported() ||
1831                     (!msr_info->host_initiated &&
1832                      !(guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
1833                        guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))))
1834                         return 1;
1835                 msr_info->data = vcpu->arch.ia32_xss;
1836                 break;
1837         case MSR_IA32_RTIT_CTL:
1838                 if (pt_mode != PT_MODE_HOST_GUEST)
1839                         return 1;
1840                 msr_info->data = vmx->pt_desc.guest.ctl;
1841                 break;
1842         case MSR_IA32_RTIT_STATUS:
1843                 if (pt_mode != PT_MODE_HOST_GUEST)
1844                         return 1;
1845                 msr_info->data = vmx->pt_desc.guest.status;
1846                 break;
1847         case MSR_IA32_RTIT_CR3_MATCH:
1848                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1849                         !intel_pt_validate_cap(vmx->pt_desc.caps,
1850                                                 PT_CAP_cr3_filtering))
1851                         return 1;
1852                 msr_info->data = vmx->pt_desc.guest.cr3_match;
1853                 break;
1854         case MSR_IA32_RTIT_OUTPUT_BASE:
1855                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1856                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1857                                         PT_CAP_topa_output) &&
1858                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1859                                         PT_CAP_single_range_output)))
1860                         return 1;
1861                 msr_info->data = vmx->pt_desc.guest.output_base;
1862                 break;
1863         case MSR_IA32_RTIT_OUTPUT_MASK:
1864                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1865                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1866                                         PT_CAP_topa_output) &&
1867                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1868                                         PT_CAP_single_range_output)))
1869                         return 1;
1870                 msr_info->data = vmx->pt_desc.guest.output_mask;
1871                 break;
1872         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1873                 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1874                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1875                         (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
1876                                         PT_CAP_num_address_ranges)))
1877                         return 1;
1878                 if (index % 2)
1879                         msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1880                 else
1881                         msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1882                 break;
1883         case MSR_TSC_AUX:
1884                 if (!msr_info->host_initiated &&
1885                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
1886                         return 1;
1887                 /* Else, falls through */
1888         default:
1889                 msr = find_msr_entry(vmx, msr_info->index);
1890                 if (msr) {
1891                         msr_info->data = msr->data;
1892                         break;
1893                 }
1894                 return kvm_get_msr_common(vcpu, msr_info);
1895         }
1896
1897         return 0;
1898 }
1899
1900 /*
1901  * Writes msr value into into the appropriate "register".
1902  * Returns 0 on success, non-0 otherwise.
1903  * Assumes vcpu_load() was already called.
1904  */
1905 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1906 {
1907         struct vcpu_vmx *vmx = to_vmx(vcpu);
1908         struct shared_msr_entry *msr;
1909         int ret = 0;
1910         u32 msr_index = msr_info->index;
1911         u64 data = msr_info->data;
1912         u32 index;
1913
1914         switch (msr_index) {
1915         case MSR_EFER:
1916                 ret = kvm_set_msr_common(vcpu, msr_info);
1917                 break;
1918 #ifdef CONFIG_X86_64
1919         case MSR_FS_BASE:
1920                 vmx_segment_cache_clear(vmx);
1921                 vmcs_writel(GUEST_FS_BASE, data);
1922                 break;
1923         case MSR_GS_BASE:
1924                 vmx_segment_cache_clear(vmx);
1925                 vmcs_writel(GUEST_GS_BASE, data);
1926                 break;
1927         case MSR_KERNEL_GS_BASE:
1928                 vmx_write_guest_kernel_gs_base(vmx, data);
1929                 break;
1930 #endif
1931         case MSR_IA32_SYSENTER_CS:
1932                 if (is_guest_mode(vcpu))
1933                         get_vmcs12(vcpu)->guest_sysenter_cs = data;
1934                 vmcs_write32(GUEST_SYSENTER_CS, data);
1935                 break;
1936         case MSR_IA32_SYSENTER_EIP:
1937                 if (is_guest_mode(vcpu))
1938                         get_vmcs12(vcpu)->guest_sysenter_eip = data;
1939                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1940                 break;
1941         case MSR_IA32_SYSENTER_ESP:
1942                 if (is_guest_mode(vcpu))
1943                         get_vmcs12(vcpu)->guest_sysenter_esp = data;
1944                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1945                 break;
1946         case MSR_IA32_DEBUGCTLMSR:
1947                 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
1948                                                 VM_EXIT_SAVE_DEBUG_CONTROLS)
1949                         get_vmcs12(vcpu)->guest_ia32_debugctl = data;
1950
1951                 ret = kvm_set_msr_common(vcpu, msr_info);
1952                 break;
1953
1954         case MSR_IA32_BNDCFGS:
1955                 if (!kvm_mpx_supported() ||
1956                     (!msr_info->host_initiated &&
1957                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1958                         return 1;
1959                 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
1960                     (data & MSR_IA32_BNDCFGS_RSVD))
1961                         return 1;
1962                 vmcs_write64(GUEST_BNDCFGS, data);
1963                 break;
1964         case MSR_IA32_UMWAIT_CONTROL:
1965                 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1966                         return 1;
1967
1968                 /* The reserved bit 1 and non-32 bit [63:32] should be zero */
1969                 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
1970                         return 1;
1971
1972                 vmx->msr_ia32_umwait_control = data;
1973                 break;
1974         case MSR_IA32_SPEC_CTRL:
1975                 if (!msr_info->host_initiated &&
1976                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1977                         return 1;
1978
1979                 /* The STIBP bit doesn't fault even if it's not advertised */
1980                 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
1981                         return 1;
1982
1983                 vmx->spec_ctrl = data;
1984
1985                 if (!data)
1986                         break;
1987
1988                 /*
1989                  * For non-nested:
1990                  * When it's written (to non-zero) for the first time, pass
1991                  * it through.
1992                  *
1993                  * For nested:
1994                  * The handling of the MSR bitmap for L2 guests is done in
1995                  * nested_vmx_merge_msr_bitmap. We should not touch the
1996                  * vmcs02.msr_bitmap here since it gets completely overwritten
1997                  * in the merging. We update the vmcs01 here for L1 as well
1998                  * since it will end up touching the MSR anyway now.
1999                  */
2000                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
2001                                               MSR_IA32_SPEC_CTRL,
2002                                               MSR_TYPE_RW);
2003                 break;
2004         case MSR_IA32_PRED_CMD:
2005                 if (!msr_info->host_initiated &&
2006                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2007                         return 1;
2008
2009                 if (data & ~PRED_CMD_IBPB)
2010                         return 1;
2011
2012                 if (!data)
2013                         break;
2014
2015                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2016
2017                 /*
2018                  * For non-nested:
2019                  * When it's written (to non-zero) for the first time, pass
2020                  * it through.
2021                  *
2022                  * For nested:
2023                  * The handling of the MSR bitmap for L2 guests is done in
2024                  * nested_vmx_merge_msr_bitmap. We should not touch the
2025                  * vmcs02.msr_bitmap here since it gets completely overwritten
2026                  * in the merging.
2027                  */
2028                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
2029                                               MSR_TYPE_W);
2030                 break;
2031         case MSR_IA32_CR_PAT:
2032                 if (!kvm_pat_valid(data))
2033                         return 1;
2034
2035                 if (is_guest_mode(vcpu) &&
2036                     get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
2037                         get_vmcs12(vcpu)->guest_ia32_pat = data;
2038
2039                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2040                         vmcs_write64(GUEST_IA32_PAT, data);
2041                         vcpu->arch.pat = data;
2042                         break;
2043                 }
2044                 ret = kvm_set_msr_common(vcpu, msr_info);
2045                 break;
2046         case MSR_IA32_TSC_ADJUST:
2047                 ret = kvm_set_msr_common(vcpu, msr_info);
2048                 break;
2049         case MSR_IA32_MCG_EXT_CTL:
2050                 if ((!msr_info->host_initiated &&
2051                      !(to_vmx(vcpu)->msr_ia32_feature_control &
2052                        FEATURE_CONTROL_LMCE)) ||
2053                     (data & ~MCG_EXT_CTL_LMCE_EN))
2054                         return 1;
2055                 vcpu->arch.mcg_ext_ctl = data;
2056                 break;
2057         case MSR_IA32_FEATURE_CONTROL:
2058                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
2059                     (to_vmx(vcpu)->msr_ia32_feature_control &
2060                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2061                         return 1;
2062                 vmx->msr_ia32_feature_control = data;
2063                 if (msr_info->host_initiated && data == 0)
2064                         vmx_leave_nested(vcpu);
2065                 break;
2066         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2067                 if (!msr_info->host_initiated)
2068                         return 1; /* they are read-only */
2069                 if (!nested_vmx_allowed(vcpu))
2070                         return 1;
2071                 return vmx_set_vmx_msr(vcpu, msr_index, data);
2072         case MSR_IA32_XSS:
2073                 if (!vmx_xsaves_supported() ||
2074                     (!msr_info->host_initiated &&
2075                      !(guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
2076                        guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))))
2077                         return 1;
2078                 /*
2079                  * The only supported bit as of Skylake is bit 8, but
2080                  * it is not supported on KVM.
2081                  */
2082                 if (data != 0)
2083                         return 1;
2084                 vcpu->arch.ia32_xss = data;
2085                 if (vcpu->arch.ia32_xss != host_xss)
2086                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2087                                 vcpu->arch.ia32_xss, host_xss, false);
2088                 else
2089                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2090                 break;
2091         case MSR_IA32_RTIT_CTL:
2092                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2093                         vmx_rtit_ctl_check(vcpu, data) ||
2094                         vmx->nested.vmxon)
2095                         return 1;
2096                 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
2097                 vmx->pt_desc.guest.ctl = data;
2098                 pt_update_intercept_for_msr(vmx);
2099                 break;
2100         case MSR_IA32_RTIT_STATUS:
2101                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2102                         (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2103                         (data & MSR_IA32_RTIT_STATUS_MASK))
2104                         return 1;
2105                 vmx->pt_desc.guest.status = data;
2106                 break;
2107         case MSR_IA32_RTIT_CR3_MATCH:
2108                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2109                         (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2110                         !intel_pt_validate_cap(vmx->pt_desc.caps,
2111                                                 PT_CAP_cr3_filtering))
2112                         return 1;
2113                 vmx->pt_desc.guest.cr3_match = data;
2114                 break;
2115         case MSR_IA32_RTIT_OUTPUT_BASE:
2116                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2117                         (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2118                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
2119                                         PT_CAP_topa_output) &&
2120                          !intel_pt_validate_cap(vmx->pt_desc.caps,
2121                                         PT_CAP_single_range_output)) ||
2122                         (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK))
2123                         return 1;
2124                 vmx->pt_desc.guest.output_base = data;
2125                 break;
2126         case MSR_IA32_RTIT_OUTPUT_MASK:
2127                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2128                         (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2129                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
2130                                         PT_CAP_topa_output) &&
2131                          !intel_pt_validate_cap(vmx->pt_desc.caps,
2132                                         PT_CAP_single_range_output)))
2133                         return 1;
2134                 vmx->pt_desc.guest.output_mask = data;
2135                 break;
2136         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2137                 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2138                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2139                         (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2140                         (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
2141                                         PT_CAP_num_address_ranges)))
2142                         return 1;
2143                 if (index % 2)
2144                         vmx->pt_desc.guest.addr_b[index / 2] = data;
2145                 else
2146                         vmx->pt_desc.guest.addr_a[index / 2] = data;
2147                 break;
2148         case MSR_TSC_AUX:
2149                 if (!msr_info->host_initiated &&
2150                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
2151                         return 1;
2152                 /* Check reserved bit, higher 32 bits should be zero */
2153                 if ((data >> 32) != 0)
2154                         return 1;
2155                 /* Else, falls through */
2156         default:
2157                 msr = find_msr_entry(vmx, msr_index);
2158                 if (msr) {
2159                         u64 old_msr_data = msr->data;
2160                         msr->data = data;
2161                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2162                                 preempt_disable();
2163                                 ret = kvm_set_shared_msr(msr->index, msr->data,
2164                                                          msr->mask);
2165                                 preempt_enable();
2166                                 if (ret)
2167                                         msr->data = old_msr_data;
2168                         }
2169                         break;
2170                 }
2171                 ret = kvm_set_msr_common(vcpu, msr_info);
2172         }
2173
2174         return ret;
2175 }
2176
2177 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2178 {
2179         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2180         switch (reg) {
2181         case VCPU_REGS_RSP:
2182                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2183                 break;
2184         case VCPU_REGS_RIP:
2185                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2186                 break;
2187         case VCPU_EXREG_PDPTR:
2188                 if (enable_ept)
2189                         ept_save_pdptrs(vcpu);
2190                 break;
2191         default:
2192                 break;
2193         }
2194 }
2195
2196 static __init int cpu_has_kvm_support(void)
2197 {
2198         return cpu_has_vmx();
2199 }
2200
2201 static __init int vmx_disabled_by_bios(void)
2202 {
2203         u64 msr;
2204
2205         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2206         if (msr & FEATURE_CONTROL_LOCKED) {
2207                 /* launched w/ TXT and VMX disabled */
2208                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2209                         && tboot_enabled())
2210                         return 1;
2211                 /* launched w/o TXT and VMX only enabled w/ TXT */
2212                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2213                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2214                         && !tboot_enabled()) {
2215                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2216                                 "activate TXT before enabling KVM\n");
2217                         return 1;
2218                 }
2219                 /* launched w/o TXT and VMX disabled */
2220                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2221                         && !tboot_enabled())
2222                         return 1;
2223         }
2224
2225         return 0;
2226 }
2227
2228 static void kvm_cpu_vmxon(u64 addr)
2229 {
2230         cr4_set_bits(X86_CR4_VMXE);
2231         intel_pt_handle_vmx(1);
2232
2233         asm volatile ("vmxon %0" : : "m"(addr));
2234 }
2235
2236 static int hardware_enable(void)
2237 {
2238         int cpu = raw_smp_processor_id();
2239         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2240         u64 old, test_bits;
2241
2242         if (cr4_read_shadow() & X86_CR4_VMXE)
2243                 return -EBUSY;
2244
2245         /*
2246          * This can happen if we hot-added a CPU but failed to allocate
2247          * VP assist page for it.
2248          */
2249         if (static_branch_unlikely(&enable_evmcs) &&
2250             !hv_get_vp_assist_page(cpu))
2251                 return -EFAULT;
2252
2253         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2254         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
2255         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
2256
2257         /*
2258          * Now we can enable the vmclear operation in kdump
2259          * since the loaded_vmcss_on_cpu list on this cpu
2260          * has been initialized.
2261          *
2262          * Though the cpu is not in VMX operation now, there
2263          * is no problem to enable the vmclear operation
2264          * for the loaded_vmcss_on_cpu list is empty!
2265          */
2266         crash_enable_local_vmclear(cpu);
2267
2268         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2269
2270         test_bits = FEATURE_CONTROL_LOCKED;
2271         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2272         if (tboot_enabled())
2273                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2274
2275         if ((old & test_bits) != test_bits) {
2276                 /* enable and lock */
2277                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2278         }
2279         kvm_cpu_vmxon(phys_addr);
2280         if (enable_ept)
2281                 ept_sync_global();
2282
2283         return 0;
2284 }
2285
2286 static void vmclear_local_loaded_vmcss(void)
2287 {
2288         int cpu = raw_smp_processor_id();
2289         struct loaded_vmcs *v, *n;
2290
2291         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2292                                  loaded_vmcss_on_cpu_link)
2293                 __loaded_vmcs_clear(v);
2294 }
2295
2296
2297 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2298  * tricks.
2299  */
2300 static void kvm_cpu_vmxoff(void)
2301 {
2302         asm volatile (__ex("vmxoff"));
2303
2304         intel_pt_handle_vmx(0);
2305         cr4_clear_bits(X86_CR4_VMXE);
2306 }
2307
2308 static void hardware_disable(void)
2309 {
2310         vmclear_local_loaded_vmcss();
2311         kvm_cpu_vmxoff();
2312 }
2313
2314 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2315                                       u32 msr, u32 *result)
2316 {
2317         u32 vmx_msr_low, vmx_msr_high;
2318         u32 ctl = ctl_min | ctl_opt;
2319
2320         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2321
2322         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2323         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2324
2325         /* Ensure minimum (required) set of control bits are supported. */
2326         if (ctl_min & ~ctl)
2327                 return -EIO;
2328
2329         *result = ctl;
2330         return 0;
2331 }
2332
2333 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2334                                     struct vmx_capability *vmx_cap)
2335 {
2336         u32 vmx_msr_low, vmx_msr_high;
2337         u32 min, opt, min2, opt2;
2338         u32 _pin_based_exec_control = 0;
2339         u32 _cpu_based_exec_control = 0;
2340         u32 _cpu_based_2nd_exec_control = 0;
2341         u32 _vmexit_control = 0;
2342         u32 _vmentry_control = 0;
2343
2344         memset(vmcs_conf, 0, sizeof(*vmcs_conf));
2345         min = CPU_BASED_HLT_EXITING |
2346 #ifdef CONFIG_X86_64
2347               CPU_BASED_CR8_LOAD_EXITING |
2348               CPU_BASED_CR8_STORE_EXITING |
2349 #endif
2350               CPU_BASED_CR3_LOAD_EXITING |
2351               CPU_BASED_CR3_STORE_EXITING |
2352               CPU_BASED_UNCOND_IO_EXITING |
2353               CPU_BASED_MOV_DR_EXITING |
2354               CPU_BASED_USE_TSC_OFFSETING |
2355               CPU_BASED_MWAIT_EXITING |
2356               CPU_BASED_MONITOR_EXITING |
2357               CPU_BASED_INVLPG_EXITING |
2358               CPU_BASED_RDPMC_EXITING;
2359
2360         opt = CPU_BASED_TPR_SHADOW |
2361               CPU_BASED_USE_MSR_BITMAPS |
2362               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2363         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2364                                 &_cpu_based_exec_control) < 0)
2365                 return -EIO;
2366 #ifdef CONFIG_X86_64
2367         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2368                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2369                                            ~CPU_BASED_CR8_STORE_EXITING;
2370 #endif
2371         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2372                 min2 = 0;
2373                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2374                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2375                         SECONDARY_EXEC_WBINVD_EXITING |
2376                         SECONDARY_EXEC_ENABLE_VPID |
2377                         SECONDARY_EXEC_ENABLE_EPT |
2378                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2379                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2380                         SECONDARY_EXEC_DESC |
2381                         SECONDARY_EXEC_RDTSCP |
2382                         SECONDARY_EXEC_ENABLE_INVPCID |
2383                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2384                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2385                         SECONDARY_EXEC_SHADOW_VMCS |
2386                         SECONDARY_EXEC_XSAVES |
2387                         SECONDARY_EXEC_RDSEED_EXITING |
2388                         SECONDARY_EXEC_RDRAND_EXITING |
2389                         SECONDARY_EXEC_ENABLE_PML |
2390                         SECONDARY_EXEC_TSC_SCALING |
2391                         SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
2392                         SECONDARY_EXEC_PT_USE_GPA |
2393                         SECONDARY_EXEC_PT_CONCEAL_VMX |
2394                         SECONDARY_EXEC_ENABLE_VMFUNC |
2395                         SECONDARY_EXEC_ENCLS_EXITING;
2396                 if (adjust_vmx_controls(min2, opt2,
2397                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2398                                         &_cpu_based_2nd_exec_control) < 0)
2399                         return -EIO;
2400         }
2401 #ifndef CONFIG_X86_64
2402         if (!(_cpu_based_2nd_exec_control &
2403                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2404                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2405 #endif
2406
2407         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2408                 _cpu_based_2nd_exec_control &= ~(
2409                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2410                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2411                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2412
2413         rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
2414                 &vmx_cap->ept, &vmx_cap->vpid);
2415
2416         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2417                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2418                    enabled */
2419                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2420                                              CPU_BASED_CR3_STORE_EXITING |
2421                                              CPU_BASED_INVLPG_EXITING);
2422         } else if (vmx_cap->ept) {
2423                 vmx_cap->ept = 0;
2424                 pr_warn_once("EPT CAP should not exist if not support "
2425                                 "1-setting enable EPT VM-execution control\n");
2426         }
2427         if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
2428                 vmx_cap->vpid) {
2429                 vmx_cap->vpid = 0;
2430                 pr_warn_once("VPID CAP should not exist if not support "
2431                                 "1-setting enable VPID VM-execution control\n");
2432         }
2433
2434         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
2435 #ifdef CONFIG_X86_64
2436         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2437 #endif
2438         opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2439               VM_EXIT_LOAD_IA32_PAT |
2440               VM_EXIT_LOAD_IA32_EFER |
2441               VM_EXIT_CLEAR_BNDCFGS |
2442               VM_EXIT_PT_CONCEAL_PIP |
2443               VM_EXIT_CLEAR_IA32_RTIT_CTL;
2444         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2445                                 &_vmexit_control) < 0)
2446                 return -EIO;
2447
2448         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2449         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2450                  PIN_BASED_VMX_PREEMPTION_TIMER;
2451         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2452                                 &_pin_based_exec_control) < 0)
2453                 return -EIO;
2454
2455         if (cpu_has_broken_vmx_preemption_timer())
2456                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2457         if (!(_cpu_based_2nd_exec_control &
2458                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
2459                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2460
2461         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2462         opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2463               VM_ENTRY_LOAD_IA32_PAT |
2464               VM_ENTRY_LOAD_IA32_EFER |
2465               VM_ENTRY_LOAD_BNDCFGS |
2466               VM_ENTRY_PT_CONCEAL_PIP |
2467               VM_ENTRY_LOAD_IA32_RTIT_CTL;
2468         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2469                                 &_vmentry_control) < 0)
2470                 return -EIO;
2471
2472         /*
2473          * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2474          * can't be used due to an errata where VM Exit may incorrectly clear
2475          * IA32_PERF_GLOBAL_CTRL[34:32].  Workaround the errata by using the
2476          * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2477          */
2478         if (boot_cpu_data.x86 == 0x6) {
2479                 switch (boot_cpu_data.x86_model) {
2480                 case 26: /* AAK155 */
2481                 case 30: /* AAP115 */
2482                 case 37: /* AAT100 */
2483                 case 44: /* BC86,AAY89,BD102 */
2484                 case 46: /* BA97 */
2485                         _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
2486                         _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2487                         pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2488                                         "does not work properly. Using workaround\n");
2489                         break;
2490                 default:
2491                         break;
2492                 }
2493         }
2494
2495
2496         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2497
2498         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2499         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2500                 return -EIO;
2501
2502 #ifdef CONFIG_X86_64
2503         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2504         if (vmx_msr_high & (1u<<16))
2505                 return -EIO;
2506 #endif
2507
2508         /* Require Write-Back (WB) memory type for VMCS accesses. */
2509         if (((vmx_msr_high >> 18) & 15) != 6)
2510                 return -EIO;
2511
2512         vmcs_conf->size = vmx_msr_high & 0x1fff;
2513         vmcs_conf->order = get_order(vmcs_conf->size);
2514         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
2515
2516         vmcs_conf->revision_id = vmx_msr_low;
2517
2518         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2519         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2520         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2521         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2522         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2523
2524         if (static_branch_unlikely(&enable_evmcs))
2525                 evmcs_sanitize_exec_ctrls(vmcs_conf);
2526
2527         return 0;
2528 }
2529
2530 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
2531 {
2532         int node = cpu_to_node(cpu);
2533         struct page *pages;
2534         struct vmcs *vmcs;
2535
2536         pages = __alloc_pages_node(node, flags, vmcs_config.order);
2537         if (!pages)
2538                 return NULL;
2539         vmcs = page_address(pages);
2540         memset(vmcs, 0, vmcs_config.size);
2541
2542         /* KVM supports Enlightened VMCS v1 only */
2543         if (static_branch_unlikely(&enable_evmcs))
2544                 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2545         else
2546                 vmcs->hdr.revision_id = vmcs_config.revision_id;
2547
2548         if (shadow)
2549                 vmcs->hdr.shadow_vmcs = 1;
2550         return vmcs;
2551 }
2552
2553 void free_vmcs(struct vmcs *vmcs)
2554 {
2555         free_pages((unsigned long)vmcs, vmcs_config.order);
2556 }
2557
2558 /*
2559  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2560  */
2561 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2562 {
2563         if (!loaded_vmcs->vmcs)
2564                 return;
2565         loaded_vmcs_clear(loaded_vmcs);
2566         free_vmcs(loaded_vmcs->vmcs);
2567         loaded_vmcs->vmcs = NULL;
2568         if (loaded_vmcs->msr_bitmap)
2569                 free_page((unsigned long)loaded_vmcs->msr_bitmap);
2570         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
2571 }
2572
2573 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2574 {
2575         loaded_vmcs->vmcs = alloc_vmcs(false);
2576         if (!loaded_vmcs->vmcs)
2577                 return -ENOMEM;
2578
2579         loaded_vmcs->shadow_vmcs = NULL;
2580         loaded_vmcs->hv_timer_soft_disabled = false;
2581         loaded_vmcs_init(loaded_vmcs);
2582
2583         if (cpu_has_vmx_msr_bitmap()) {
2584                 loaded_vmcs->msr_bitmap = (unsigned long *)
2585                                 __get_free_page(GFP_KERNEL_ACCOUNT);
2586                 if (!loaded_vmcs->msr_bitmap)
2587                         goto out_vmcs;
2588                 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
2589
2590                 if (IS_ENABLED(CONFIG_HYPERV) &&
2591                     static_branch_unlikely(&enable_evmcs) &&
2592                     (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2593                         struct hv_enlightened_vmcs *evmcs =
2594                                 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2595
2596                         evmcs->hv_enlightenments_control.msr_bitmap = 1;
2597                 }
2598         }
2599
2600         memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2601         memset(&loaded_vmcs->controls_shadow, 0,
2602                 sizeof(struct vmcs_controls_shadow));
2603
2604         return 0;
2605
2606 out_vmcs:
2607         free_loaded_vmcs(loaded_vmcs);
2608         return -ENOMEM;
2609 }
2610
2611 static void free_kvm_area(void)
2612 {
2613         int cpu;
2614
2615         for_each_possible_cpu(cpu) {
2616                 free_vmcs(per_cpu(vmxarea, cpu));
2617                 per_cpu(vmxarea, cpu) = NULL;
2618         }
2619 }
2620
2621 static __init int alloc_kvm_area(void)
2622 {
2623         int cpu;
2624
2625         for_each_possible_cpu(cpu) {
2626                 struct vmcs *vmcs;
2627
2628                 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
2629                 if (!vmcs) {
2630                         free_kvm_area();
2631                         return -ENOMEM;
2632                 }
2633
2634                 /*
2635                  * When eVMCS is enabled, alloc_vmcs_cpu() sets
2636                  * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2637                  * revision_id reported by MSR_IA32_VMX_BASIC.
2638                  *
2639                  * However, even though not explicitly documented by
2640                  * TLFS, VMXArea passed as VMXON argument should
2641                  * still be marked with revision_id reported by
2642                  * physical CPU.
2643                  */
2644                 if (static_branch_unlikely(&enable_evmcs))
2645                         vmcs->hdr.revision_id = vmcs_config.revision_id;
2646
2647                 per_cpu(vmxarea, cpu) = vmcs;
2648         }
2649         return 0;
2650 }
2651
2652 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2653                 struct kvm_segment *save)
2654 {
2655         if (!emulate_invalid_guest_state) {
2656                 /*
2657                  * CS and SS RPL should be equal during guest entry according
2658                  * to VMX spec, but in reality it is not always so. Since vcpu
2659                  * is in the middle of the transition from real mode to
2660                  * protected mode it is safe to assume that RPL 0 is a good
2661                  * default value.
2662                  */
2663                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2664                         save->selector &= ~SEGMENT_RPL_MASK;
2665                 save->dpl = save->selector & SEGMENT_RPL_MASK;
2666                 save->s = 1;
2667         }
2668         vmx_set_segment(vcpu, save, seg);
2669 }
2670
2671 static void enter_pmode(struct kvm_vcpu *vcpu)
2672 {
2673         unsigned long flags;
2674         struct vcpu_vmx *vmx = to_vmx(vcpu);
2675
2676         /*
2677          * Update real mode segment cache. It may be not up-to-date if sement
2678          * register was written while vcpu was in a guest mode.
2679          */
2680         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2681         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2682         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2683         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2684         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2685         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2686
2687         vmx->rmode.vm86_active = 0;
2688
2689         vmx_segment_cache_clear(vmx);
2690
2691         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2692
2693         flags = vmcs_readl(GUEST_RFLAGS);
2694         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2695         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2696         vmcs_writel(GUEST_RFLAGS, flags);
2697
2698         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2699                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2700
2701         update_exception_bitmap(vcpu);
2702
2703         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2704         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2705         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2706         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2707         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2708         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2709 }
2710
2711 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2712 {
2713         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2714         struct kvm_segment var = *save;
2715
2716         var.dpl = 0x3;
2717         if (seg == VCPU_SREG_CS)
2718                 var.type = 0x3;
2719
2720         if (!emulate_invalid_guest_state) {
2721                 var.selector = var.base >> 4;
2722                 var.base = var.base & 0xffff0;
2723                 var.limit = 0xffff;
2724                 var.g = 0;
2725                 var.db = 0;
2726                 var.present = 1;
2727                 var.s = 1;
2728                 var.l = 0;
2729                 var.unusable = 0;
2730                 var.type = 0x3;
2731                 var.avl = 0;
2732                 if (save->base & 0xf)
2733                         printk_once(KERN_WARNING "kvm: segment base is not "
2734                                         "paragraph aligned when entering "
2735                                         "protected mode (seg=%d)", seg);
2736         }
2737
2738         vmcs_write16(sf->selector, var.selector);
2739         vmcs_writel(sf->base, var.base);
2740         vmcs_write32(sf->limit, var.limit);
2741         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2742 }
2743
2744 static void enter_rmode(struct kvm_vcpu *vcpu)
2745 {
2746         unsigned long flags;
2747         struct vcpu_vmx *vmx = to_vmx(vcpu);
2748         struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
2749
2750         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2751         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2752         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2753         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2754         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2755         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2756         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2757
2758         vmx->rmode.vm86_active = 1;
2759
2760         /*
2761          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2762          * vcpu. Warn the user that an update is overdue.
2763          */
2764         if (!kvm_vmx->tss_addr)
2765                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2766                              "called before entering vcpu\n");
2767
2768         vmx_segment_cache_clear(vmx);
2769
2770         vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
2771         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2772         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2773
2774         flags = vmcs_readl(GUEST_RFLAGS);
2775         vmx->rmode.save_rflags = flags;
2776
2777         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2778
2779         vmcs_writel(GUEST_RFLAGS, flags);
2780         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2781         update_exception_bitmap(vcpu);
2782
2783         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2784         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2785         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2786         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2787         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2788         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2789
2790         kvm_mmu_reset_context(vcpu);
2791 }
2792
2793 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2794 {
2795         struct vcpu_vmx *vmx = to_vmx(vcpu);
2796         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2797
2798         if (!msr)
2799                 return;
2800
2801         vcpu->arch.efer = efer;
2802         if (efer & EFER_LMA) {
2803                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2804                 msr->data = efer;
2805         } else {
2806                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2807
2808                 msr->data = efer & ~EFER_LME;
2809         }
2810         setup_msrs(vmx);
2811 }
2812
2813 #ifdef CONFIG_X86_64
2814
2815 static void enter_lmode(struct kvm_vcpu *vcpu)
2816 {
2817         u32 guest_tr_ar;
2818
2819         vmx_segment_cache_clear(to_vmx(vcpu));
2820
2821         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2822         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
2823                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2824                                      __func__);
2825                 vmcs_write32(GUEST_TR_AR_BYTES,
2826                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2827                              | VMX_AR_TYPE_BUSY_64_TSS);
2828         }
2829         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2830 }
2831
2832 static void exit_lmode(struct kvm_vcpu *vcpu)
2833 {
2834         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2835         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2836 }
2837
2838 #endif
2839
2840 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2841 {
2842         int vpid = to_vmx(vcpu)->vpid;
2843
2844         if (!vpid_sync_vcpu_addr(vpid, addr))
2845                 vpid_sync_context(vpid);
2846
2847         /*
2848          * If VPIDs are not supported or enabled, then the above is a no-op.
2849          * But we don't really need a TLB flush in that case anyway, because
2850          * each VM entry/exit includes an implicit flush when VPID is 0.
2851          */
2852 }
2853
2854 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2855 {
2856         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2857
2858         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2859         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2860 }
2861
2862 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2863 {
2864         if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
2865                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2866         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2867 }
2868
2869 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2870 {
2871         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2872
2873         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2874         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2875 }
2876
2877 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2878 {
2879         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2880
2881         if (!test_bit(VCPU_EXREG_PDPTR,
2882                       (unsigned long *)&vcpu->arch.regs_dirty))
2883                 return;
2884
2885         if (is_pae_paging(vcpu)) {
2886                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2887                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2888                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2889                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
2890         }
2891 }
2892
2893 void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2894 {
2895         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2896
2897         if (is_pae_paging(vcpu)) {
2898                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2899                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2900                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2901                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2902         }
2903
2904         __set_bit(VCPU_EXREG_PDPTR,
2905                   (unsigned long *)&vcpu->arch.regs_avail);
2906         __set_bit(VCPU_EXREG_PDPTR,
2907                   (unsigned long *)&vcpu->arch.regs_dirty);
2908 }
2909
2910 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2911                                         unsigned long cr0,
2912                                         struct kvm_vcpu *vcpu)
2913 {
2914         struct vcpu_vmx *vmx = to_vmx(vcpu);
2915
2916         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2917                 vmx_decache_cr3(vcpu);
2918         if (!(cr0 & X86_CR0_PG)) {
2919                 /* From paging/starting to nonpaging */
2920                 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2921                                           CPU_BASED_CR3_STORE_EXITING);
2922                 vcpu->arch.cr0 = cr0;
2923                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2924         } else if (!is_paging(vcpu)) {
2925                 /* From nonpaging to paging */
2926                 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2927                                             CPU_BASED_CR3_STORE_EXITING);
2928                 vcpu->arch.cr0 = cr0;
2929                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2930         }
2931
2932         if (!(cr0 & X86_CR0_WP))
2933                 *hw_cr0 &= ~X86_CR0_WP;
2934 }
2935
2936 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2937 {
2938         struct vcpu_vmx *vmx = to_vmx(vcpu);
2939         unsigned long hw_cr0;
2940
2941         hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
2942         if (enable_unrestricted_guest)
2943                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2944         else {
2945                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
2946
2947                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2948                         enter_pmode(vcpu);
2949
2950                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2951                         enter_rmode(vcpu);
2952         }
2953
2954 #ifdef CONFIG_X86_64
2955         if (vcpu->arch.efer & EFER_LME) {
2956                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2957                         enter_lmode(vcpu);
2958                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2959                         exit_lmode(vcpu);
2960         }
2961 #endif
2962
2963         if (enable_ept && !enable_unrestricted_guest)
2964                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2965
2966         vmcs_writel(CR0_READ_SHADOW, cr0);
2967         vmcs_writel(GUEST_CR0, hw_cr0);
2968         vcpu->arch.cr0 = cr0;
2969
2970         /* depends on vcpu->arch.cr0 to be set to a new value */
2971         vmx->emulation_required = emulation_required(vcpu);
2972 }
2973
2974 static int get_ept_level(struct kvm_vcpu *vcpu)
2975 {
2976         if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
2977                 return 5;
2978         return 4;
2979 }
2980
2981 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
2982 {
2983         u64 eptp = VMX_EPTP_MT_WB;
2984
2985         eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
2986
2987         if (enable_ept_ad_bits &&
2988             (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
2989                 eptp |= VMX_EPTP_AD_ENABLE_BIT;
2990         eptp |= (root_hpa & PAGE_MASK);
2991
2992         return eptp;
2993 }
2994
2995 void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2996 {
2997         struct kvm *kvm = vcpu->kvm;
2998         unsigned long guest_cr3;
2999         u64 eptp;
3000
3001         guest_cr3 = cr3;
3002         if (enable_ept) {
3003                 eptp = construct_eptp(vcpu, cr3);
3004                 vmcs_write64(EPT_POINTER, eptp);
3005
3006                 if (kvm_x86_ops->tlb_remote_flush) {
3007                         spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3008                         to_vmx(vcpu)->ept_pointer = eptp;
3009                         to_kvm_vmx(kvm)->ept_pointers_match
3010                                 = EPT_POINTERS_CHECK;
3011                         spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3012                 }
3013
3014                 if (enable_unrestricted_guest || is_paging(vcpu) ||
3015                     is_guest_mode(vcpu))
3016                         guest_cr3 = kvm_read_cr3(vcpu);
3017                 else
3018                         guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
3019                 ept_load_pdptrs(vcpu);
3020         }
3021
3022         vmcs_writel(GUEST_CR3, guest_cr3);
3023 }
3024
3025 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3026 {
3027         struct vcpu_vmx *vmx = to_vmx(vcpu);
3028         /*
3029          * Pass through host's Machine Check Enable value to hw_cr4, which
3030          * is in force while we are in guest mode.  Do not let guests control
3031          * this bit, even if host CR4.MCE == 0.
3032          */
3033         unsigned long hw_cr4;
3034
3035         hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
3036         if (enable_unrestricted_guest)
3037                 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
3038         else if (vmx->rmode.vm86_active)
3039                 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
3040         else
3041                 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
3042
3043         if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
3044                 if (cr4 & X86_CR4_UMIP) {
3045                         secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
3046                         hw_cr4 &= ~X86_CR4_UMIP;
3047                 } else if (!is_guest_mode(vcpu) ||
3048                         !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
3049                         secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
3050                 }
3051         }
3052
3053         if (cr4 & X86_CR4_VMXE) {
3054                 /*
3055                  * To use VMXON (and later other VMX instructions), a guest
3056                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3057                  * So basically the check on whether to allow nested VMX
3058                  * is here.  We operate under the default treatment of SMM,
3059                  * so VMX cannot be enabled under SMM.
3060                  */
3061                 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
3062                         return 1;
3063         }
3064
3065         if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
3066                 return 1;
3067
3068         vcpu->arch.cr4 = cr4;
3069
3070         if (!enable_unrestricted_guest) {
3071                 if (enable_ept) {
3072                         if (!is_paging(vcpu)) {
3073                                 hw_cr4 &= ~X86_CR4_PAE;
3074                                 hw_cr4 |= X86_CR4_PSE;
3075                         } else if (!(cr4 & X86_CR4_PAE)) {
3076                                 hw_cr4 &= ~X86_CR4_PAE;
3077                         }
3078                 }
3079
3080                 /*
3081                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3082                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
3083                  * to be manually disabled when guest switches to non-paging
3084                  * mode.
3085                  *
3086                  * If !enable_unrestricted_guest, the CPU is always running
3087                  * with CR0.PG=1 and CR4 needs to be modified.
3088                  * If enable_unrestricted_guest, the CPU automatically
3089                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3090                  */
3091                 if (!is_paging(vcpu))
3092                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3093         }
3094
3095         vmcs_writel(CR4_READ_SHADOW, cr4);
3096         vmcs_writel(GUEST_CR4, hw_cr4);
3097         return 0;
3098 }
3099
3100 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3101 {
3102         struct vcpu_vmx *vmx = to_vmx(vcpu);
3103         u32 ar;
3104
3105         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3106                 *var = vmx->rmode.segs[seg];
3107                 if (seg == VCPU_SREG_TR
3108                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3109                         return;
3110                 var->base = vmx_read_guest_seg_base(vmx, seg);
3111                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3112                 return;
3113         }
3114         var->base = vmx_read_guest_seg_base(vmx, seg);
3115         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3116         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3117         ar = vmx_read_guest_seg_ar(vmx, seg);
3118         var->unusable = (ar >> 16) & 1;
3119         var->type = ar & 15;
3120         var->s = (ar >> 4) & 1;
3121         var->dpl = (ar >> 5) & 3;
3122         /*
3123          * Some userspaces do not preserve unusable property. Since usable
3124          * segment has to be present according to VMX spec we can use present
3125          * property to amend userspace bug by making unusable segment always
3126          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3127          * segment as unusable.
3128          */
3129         var->present = !var->unusable;
3130         var->avl = (ar >> 12) & 1;
3131         var->l = (ar >> 13) & 1;
3132         var->db = (ar >> 14) & 1;
3133         var->g = (ar >> 15) & 1;
3134 }
3135
3136 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3137 {
3138         struct kvm_segment s;
3139
3140         if (to_vmx(vcpu)->rmode.vm86_active) {
3141                 vmx_get_segment(vcpu, &s, seg);
3142                 return s.base;
3143         }
3144         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3145 }
3146
3147 int vmx_get_cpl(struct kvm_vcpu *vcpu)
3148 {
3149         struct vcpu_vmx *vmx = to_vmx(vcpu);
3150
3151         if (unlikely(vmx->rmode.vm86_active))
3152                 return 0;
3153         else {
3154                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3155                 return VMX_AR_DPL(ar);
3156         }
3157 }
3158
3159 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3160 {
3161         u32 ar;
3162
3163         if (var->unusable || !var->present)
3164                 ar = 1 << 16;
3165         else {
3166                 ar = var->type & 15;
3167                 ar |= (var->s & 1) << 4;
3168                 ar |= (var->dpl & 3) << 5;
3169                 ar |= (var->present & 1) << 7;
3170                 ar |= (var->avl & 1) << 12;
3171                 ar |= (var->l & 1) << 13;
3172                 ar |= (var->db & 1) << 14;
3173                 ar |= (var->g & 1) << 15;
3174         }
3175
3176         return ar;
3177 }
3178
3179 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3180 {
3181         struct vcpu_vmx *vmx = to_vmx(vcpu);
3182         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3183
3184         vmx_segment_cache_clear(vmx);
3185
3186         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3187                 vmx->rmode.segs[seg] = *var;
3188                 if (seg == VCPU_SREG_TR)
3189                         vmcs_write16(sf->selector, var->selector);
3190                 else if (var->s)
3191                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3192                 goto out;
3193         }
3194
3195         vmcs_writel(sf->base, var->base);
3196         vmcs_write32(sf->limit, var->limit);
3197         vmcs_write16(sf->selector, var->selector);
3198
3199         /*
3200          *   Fix the "Accessed" bit in AR field of segment registers for older
3201          * qemu binaries.
3202          *   IA32 arch specifies that at the time of processor reset the
3203          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3204          * is setting it to 0 in the userland code. This causes invalid guest
3205          * state vmexit when "unrestricted guest" mode is turned on.
3206          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3207          * tree. Newer qemu binaries with that qemu fix would not need this
3208          * kvm hack.
3209          */
3210         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3211                 var->type |= 0x1; /* Accessed */
3212
3213         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3214
3215 out:
3216         vmx->emulation_required = emulation_required(vcpu);
3217 }
3218
3219 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3220 {
3221         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3222
3223         *db = (ar >> 14) & 1;
3224         *l = (ar >> 13) & 1;
3225 }
3226
3227 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3228 {
3229         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3230         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3231 }
3232
3233 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3234 {
3235         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3236         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3237 }
3238
3239 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3240 {
3241         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3242         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3243 }
3244
3245 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3246 {
3247         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3248         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3249 }
3250
3251 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3252 {
3253         struct kvm_segment var;
3254         u32 ar;
3255
3256         vmx_get_segment(vcpu, &var, seg);
3257         var.dpl = 0x3;
3258         if (seg == VCPU_SREG_CS)
3259                 var.type = 0x3;
3260         ar = vmx_segment_access_rights(&var);
3261
3262         if (var.base != (var.selector << 4))
3263                 return false;
3264         if (var.limit != 0xffff)
3265                 return false;
3266         if (ar != 0xf3)
3267                 return false;
3268
3269         return true;
3270 }
3271
3272 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3273 {
3274         struct kvm_segment cs;
3275         unsigned int cs_rpl;
3276
3277         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3278         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3279
3280         if (cs.unusable)
3281                 return false;
3282         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3283                 return false;
3284         if (!cs.s)
3285                 return false;
3286         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3287                 if (cs.dpl > cs_rpl)
3288                         return false;
3289         } else {
3290                 if (cs.dpl != cs_rpl)
3291                         return false;
3292         }
3293         if (!cs.present)
3294                 return false;
3295
3296         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3297         return true;
3298 }
3299
3300 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3301 {
3302         struct kvm_segment ss;
3303         unsigned int ss_rpl;
3304
3305         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3306         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3307
3308         if (ss.unusable)
3309                 return true;
3310         if (ss.type != 3 && ss.type != 7)
3311                 return false;
3312         if (!ss.s)
3313                 return false;
3314         if (ss.dpl != ss_rpl) /* DPL != RPL */
3315                 return false;
3316         if (!ss.present)
3317                 return false;
3318
3319         return true;
3320 }
3321
3322 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3323 {
3324         struct kvm_segment var;
3325         unsigned int rpl;
3326
3327         vmx_get_segment(vcpu, &var, seg);
3328         rpl = var.selector & SEGMENT_RPL_MASK;
3329
3330         if (var.unusable)
3331                 return true;
3332         if (!var.s)
3333                 return false;
3334         if (!var.present)
3335                 return false;
3336         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
3337                 if (var.dpl < rpl) /* DPL < RPL */
3338                         return false;
3339         }
3340
3341         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3342          * rights flags
3343          */
3344         return true;
3345 }
3346
3347 static bool tr_valid(struct kvm_vcpu *vcpu)
3348 {
3349         struct kvm_segment tr;
3350
3351         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3352
3353         if (tr.unusable)
3354                 return false;
3355         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
3356                 return false;
3357         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3358                 return false;
3359         if (!tr.present)
3360                 return false;
3361
3362         return true;
3363 }
3364
3365 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3366 {
3367         struct kvm_segment ldtr;
3368
3369         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3370
3371         if (ldtr.unusable)
3372                 return true;
3373         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
3374                 return false;
3375         if (ldtr.type != 2)
3376                 return false;
3377         if (!ldtr.present)
3378                 return false;
3379
3380         return true;
3381 }
3382
3383 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3384 {
3385         struct kvm_segment cs, ss;
3386
3387         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3388         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3389
3390         return ((cs.selector & SEGMENT_RPL_MASK) ==
3391                  (ss.selector & SEGMENT_RPL_MASK));
3392 }
3393
3394 /*
3395  * Check if guest state is valid. Returns true if valid, false if
3396  * not.
3397  * We assume that registers are always usable
3398  */
3399 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3400 {
3401         if (enable_unrestricted_guest)
3402                 return true;
3403
3404         /* real mode guest state checks */
3405         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3406                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3407                         return false;
3408                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3409                         return false;
3410                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3411                         return false;
3412                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3413                         return false;
3414                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3415                         return false;
3416                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3417                         return false;
3418         } else {
3419         /* protected mode guest state checks */
3420                 if (!cs_ss_rpl_check(vcpu))
3421                         return false;
3422                 if (!code_segment_valid(vcpu))
3423                         return false;
3424                 if (!stack_segment_valid(vcpu))
3425                         return false;
3426                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3427                         return false;
3428                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3429                         return false;
3430                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3431                         return false;
3432                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3433                         return false;
3434                 if (!tr_valid(vcpu))
3435                         return false;
3436                 if (!ldtr_valid(vcpu))
3437                         return false;
3438         }
3439         /* TODO:
3440          * - Add checks on RIP
3441          * - Add checks on RFLAGS
3442          */
3443
3444         return true;
3445 }
3446
3447 static int init_rmode_tss(struct kvm *kvm)
3448 {
3449         gfn_t fn;
3450         u16 data = 0;
3451         int idx, r;
3452
3453         idx = srcu_read_lock(&kvm->srcu);
3454         fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
3455         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3456         if (r < 0)
3457                 goto out;
3458         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3459         r = kvm_write_guest_page(kvm, fn++, &data,
3460                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3461         if (r < 0)
3462                 goto out;
3463         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3464         if (r < 0)
3465                 goto out;
3466         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3467         if (r < 0)
3468                 goto out;
3469         data = ~0;
3470         r = kvm_write_guest_page(kvm, fn, &data,
3471                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3472                                  sizeof(u8));
3473 out:
3474         srcu_read_unlock(&kvm->srcu, idx);
3475         return r;
3476 }
3477
3478 static int init_rmode_identity_map(struct kvm *kvm)
3479 {
3480         struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
3481         int i, idx, r = 0;
3482         kvm_pfn_t identity_map_pfn;
3483         u32 tmp;
3484
3485         /* Protect kvm_vmx->ept_identity_pagetable_done. */
3486         mutex_lock(&kvm->slots_lock);
3487
3488         if (likely(kvm_vmx->ept_identity_pagetable_done))
3489                 goto out2;
3490
3491         if (!kvm_vmx->ept_identity_map_addr)
3492                 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3493         identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
3494
3495         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
3496                                     kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
3497         if (r < 0)
3498                 goto out2;
3499
3500         idx = srcu_read_lock(&kvm->srcu);
3501         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3502         if (r < 0)
3503                 goto out;
3504         /* Set up identity-mapping pagetable for EPT in real mode */
3505         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3506                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3507                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3508                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3509                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3510                 if (r < 0)
3511                         goto out;
3512         }
3513         kvm_vmx->ept_identity_pagetable_done = true;
3514
3515 out:
3516         srcu_read_unlock(&kvm->srcu, idx);
3517
3518 out2:
3519         mutex_unlock(&kvm->slots_lock);
3520         return r;
3521 }
3522
3523 static void seg_setup(int seg)
3524 {
3525         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3526         unsigned int ar;
3527
3528         vmcs_write16(sf->selector, 0);
3529         vmcs_writel(sf->base, 0);
3530         vmcs_write32(sf->limit, 0xffff);
3531         ar = 0x93;
3532         if (seg == VCPU_SREG_CS)
3533                 ar |= 0x08; /* code segment */
3534
3535         vmcs_write32(sf->ar_bytes, ar);
3536 }
3537
3538 static int alloc_apic_access_page(struct kvm *kvm)
3539 {
3540         struct page *page;
3541         int r = 0;
3542
3543         mutex_lock(&kvm->slots_lock);
3544         if (kvm->arch.apic_access_page_done)
3545                 goto out;
3546         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3547                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
3548         if (r)
3549                 goto out;
3550
3551         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
3552         if (is_error_page(page)) {
3553                 r = -EFAULT;
3554                 goto out;
3555         }
3556
3557         /*
3558          * Do not pin the page in memory, so that memory hot-unplug
3559          * is able to migrate it.
3560          */
3561         put_page(page);
3562         kvm->arch.apic_access_page_done = true;
3563 out:
3564         mutex_unlock(&kvm->slots_lock);
3565         return r;
3566 }
3567
3568 int allocate_vpid(void)
3569 {
3570         int vpid;
3571
3572         if (!enable_vpid)
3573                 return 0;
3574         spin_lock(&vmx_vpid_lock);
3575         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3576         if (vpid < VMX_NR_VPIDS)
3577                 __set_bit(vpid, vmx_vpid_bitmap);
3578         else
3579                 vpid = 0;
3580         spin_unlock(&vmx_vpid_lock);
3581         return vpid;
3582 }
3583
3584 void free_vpid(int vpid)
3585 {
3586         if (!enable_vpid || vpid == 0)
3587                 return;
3588         spin_lock(&vmx_vpid_lock);
3589         __clear_bit(vpid, vmx_vpid_bitmap);
3590         spin_unlock(&vmx_vpid_lock);
3591 }
3592
3593 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3594                                                           u32 msr, int type)
3595 {
3596         int f = sizeof(unsigned long);
3597
3598         if (!cpu_has_vmx_msr_bitmap())
3599                 return;
3600
3601         if (static_branch_unlikely(&enable_evmcs))
3602                 evmcs_touch_msr_bitmap();
3603
3604         /*
3605          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3606          * have the write-low and read-high bitmap offsets the wrong way round.
3607          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3608          */
3609         if (msr <= 0x1fff) {
3610                 if (type & MSR_TYPE_R)
3611                         /* read-low */
3612                         __clear_bit(msr, msr_bitmap + 0x000 / f);
3613
3614                 if (type & MSR_TYPE_W)
3615                         /* write-low */
3616                         __clear_bit(msr, msr_bitmap + 0x800 / f);
3617
3618         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3619                 msr &= 0x1fff;
3620                 if (type & MSR_TYPE_R)
3621                         /* read-high */
3622                         __clear_bit(msr, msr_bitmap + 0x400 / f);
3623
3624                 if (type & MSR_TYPE_W)
3625                         /* write-high */
3626                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
3627
3628         }
3629 }
3630
3631 static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3632                                                          u32 msr, int type)
3633 {
3634         int f = sizeof(unsigned long);
3635
3636         if (!cpu_has_vmx_msr_bitmap())
3637                 return;
3638
3639         if (static_branch_unlikely(&enable_evmcs))
3640                 evmcs_touch_msr_bitmap();
3641
3642         /*
3643          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3644          * have the write-low and read-high bitmap offsets the wrong way round.
3645          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3646          */
3647         if (msr <= 0x1fff) {
3648                 if (type & MSR_TYPE_R)
3649                         /* read-low */
3650                         __set_bit(msr, msr_bitmap + 0x000 / f);
3651
3652                 if (type & MSR_TYPE_W)
3653                         /* write-low */
3654                         __set_bit(msr, msr_bitmap + 0x800 / f);
3655
3656         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3657                 msr &= 0x1fff;
3658                 if (type & MSR_TYPE_R)
3659                         /* read-high */
3660                         __set_bit(msr, msr_bitmap + 0x400 / f);
3661
3662                 if (type & MSR_TYPE_W)
3663                         /* write-high */
3664                         __set_bit(msr, msr_bitmap + 0xc00 / f);
3665
3666         }
3667 }
3668
3669 static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
3670                                                       u32 msr, int type, bool value)
3671 {
3672         if (value)
3673                 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
3674         else
3675                 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
3676 }
3677
3678 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
3679 {
3680         u8 mode = 0;
3681
3682         if (cpu_has_secondary_exec_ctrls() &&
3683             (secondary_exec_controls_get(to_vmx(vcpu)) &
3684              SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3685                 mode |= MSR_BITMAP_MODE_X2APIC;
3686                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3687                         mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3688         }
3689
3690         return mode;
3691 }
3692
3693 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
3694                                          u8 mode)
3695 {
3696         int msr;
3697
3698         for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3699                 unsigned word = msr / BITS_PER_LONG;
3700                 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3701                 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
3702         }
3703
3704         if (mode & MSR_BITMAP_MODE_X2APIC) {
3705                 /*
3706                  * TPR reads and writes can be virtualized even if virtual interrupt
3707                  * delivery is not in use.
3708                  */
3709                 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
3710                 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3711                         vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
3712                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3713                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3714                 }
3715         }
3716 }
3717
3718 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
3719 {
3720         struct vcpu_vmx *vmx = to_vmx(vcpu);
3721         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3722         u8 mode = vmx_msr_bitmap_mode(vcpu);
3723         u8 changed = mode ^ vmx->msr_bitmap_mode;
3724
3725         if (!changed)
3726                 return;
3727
3728         if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
3729                 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
3730
3731         vmx->msr_bitmap_mode = mode;
3732 }
3733
3734 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx)
3735 {
3736         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3737         bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3738         u32 i;
3739
3740         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS,
3741                                                         MSR_TYPE_RW, flag);
3742         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE,
3743                                                         MSR_TYPE_RW, flag);
3744         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK,
3745                                                         MSR_TYPE_RW, flag);
3746         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH,
3747                                                         MSR_TYPE_RW, flag);
3748         for (i = 0; i < vmx->pt_desc.addr_range; i++) {
3749                 vmx_set_intercept_for_msr(msr_bitmap,
3750                         MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3751                 vmx_set_intercept_for_msr(msr_bitmap,
3752                         MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3753         }
3754 }
3755
3756 static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu)
3757 {
3758         return enable_apicv;
3759 }
3760
3761 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3762 {
3763         struct vcpu_vmx *vmx = to_vmx(vcpu);
3764         void *vapic_page;
3765         u32 vppr;
3766         int rvi;
3767
3768         if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3769                 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
3770                 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
3771                 return false;
3772
3773         rvi = vmx_get_rvi();
3774
3775         vapic_page = vmx->nested.virtual_apic_map.hva;
3776         vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
3777
3778         return ((rvi & 0xf0) > (vppr & 0xf0));
3779 }
3780
3781 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3782                                                      bool nested)
3783 {
3784 #ifdef CONFIG_SMP
3785         int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3786
3787         if (vcpu->mode == IN_GUEST_MODE) {
3788                 /*
3789                  * The vector of interrupt to be delivered to vcpu had
3790                  * been set in PIR before this function.
3791                  *
3792                  * Following cases will be reached in this block, and
3793                  * we always send a notification event in all cases as
3794                  * explained below.
3795                  *
3796                  * Case 1: vcpu keeps in non-root mode. Sending a
3797                  * notification event posts the interrupt to vcpu.
3798                  *
3799                  * Case 2: vcpu exits to root mode and is still
3800                  * runnable. PIR will be synced to vIRR before the
3801                  * next vcpu entry. Sending a notification event in
3802                  * this case has no effect, as vcpu is not in root
3803                  * mode.
3804                  *
3805                  * Case 3: vcpu exits to root mode and is blocked.
3806                  * vcpu_block() has already synced PIR to vIRR and
3807                  * never blocks vcpu if vIRR is not cleared. Therefore,
3808                  * a blocked vcpu here does not wait for any requested
3809                  * interrupts in PIR, and sending a notification event
3810                  * which has no effect is safe here.
3811                  */
3812
3813                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
3814                 return true;
3815         }
3816 #endif
3817         return false;
3818 }
3819
3820 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3821                                                 int vector)
3822 {
3823         struct vcpu_vmx *vmx = to_vmx(vcpu);
3824
3825         if (is_guest_mode(vcpu) &&
3826             vector == vmx->nested.posted_intr_nv) {
3827                 /*
3828                  * If a posted intr is not recognized by hardware,
3829                  * we will accomplish it in the next vmentry.
3830                  */
3831                 vmx->nested.pi_pending = true;
3832                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3833                 /* the PIR and ON have been set by L1. */
3834                 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3835                         kvm_vcpu_kick(vcpu);
3836                 return 0;
3837         }
3838         return -1;
3839 }
3840 /*
3841  * Send interrupt to vcpu via posted interrupt way.
3842  * 1. If target vcpu is running(non-root mode), send posted interrupt
3843  * notification to vcpu and hardware will sync PIR to vIRR atomically.
3844  * 2. If target vcpu isn't running(root mode), kick it to pick up the
3845  * interrupt from PIR in next vmentry.
3846  */
3847 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3848 {
3849         struct vcpu_vmx *vmx = to_vmx(vcpu);
3850         int r;
3851
3852         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3853         if (!r)
3854                 return;
3855
3856         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
3857                 return;
3858
3859         /* If a previous notification has sent the IPI, nothing to do.  */
3860         if (pi_test_and_set_on(&vmx->pi_desc))
3861                 return;
3862
3863         if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
3864                 kvm_vcpu_kick(vcpu);
3865 }
3866
3867 /*
3868  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3869  * will not change in the lifetime of the guest.
3870  * Note that host-state that does change is set elsewhere. E.g., host-state
3871  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3872  */
3873 void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
3874 {
3875         u32 low32, high32;
3876         unsigned long tmpl;
3877         unsigned long cr0, cr3, cr4;
3878
3879         cr0 = read_cr0();
3880         WARN_ON(cr0 & X86_CR0_TS);
3881         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
3882
3883         /*
3884          * Save the most likely value for this task's CR3 in the VMCS.
3885          * We can't use __get_current_cr3_fast() because we're not atomic.
3886          */
3887         cr3 = __read_cr3();
3888         vmcs_writel(HOST_CR3, cr3);             /* 22.2.3  FIXME: shadow tables */
3889         vmx->loaded_vmcs->host_state.cr3 = cr3;
3890
3891         /* Save the most likely value for this task's CR4 in the VMCS. */
3892         cr4 = cr4_read_shadow();
3893         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
3894         vmx->loaded_vmcs->host_state.cr4 = cr4;
3895
3896         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
3897 #ifdef CONFIG_X86_64
3898         /*
3899          * Load null selectors, so we can avoid reloading them in
3900          * vmx_prepare_switch_to_host(), in case userspace uses
3901          * the null selectors too (the expected case).
3902          */
3903         vmcs_write16(HOST_DS_SELECTOR, 0);
3904         vmcs_write16(HOST_ES_SELECTOR, 0);
3905 #else
3906         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3907         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3908 #endif
3909         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3910         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
3911
3912         vmcs_writel(HOST_IDTR_BASE, host_idt_base);   /* 22.2.4 */
3913
3914         vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
3915
3916         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3917         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3918         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3919         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
3920
3921         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3922                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3923                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3924         }
3925
3926         if (cpu_has_load_ia32_efer())
3927                 vmcs_write64(HOST_IA32_EFER, host_efer);
3928 }
3929
3930 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3931 {
3932         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3933         if (enable_ept)
3934                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3935         if (is_guest_mode(&vmx->vcpu))
3936                 vmx->vcpu.arch.cr4_guest_owned_bits &=
3937                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3938         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3939 }
3940
3941 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
3942 {
3943         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
3944
3945         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
3946                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
3947
3948         if (!enable_vnmi)
3949                 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
3950
3951         if (!enable_preemption_timer)
3952                 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3953
3954         return pin_based_exec_ctrl;
3955 }
3956
3957 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
3958 {
3959         struct vcpu_vmx *vmx = to_vmx(vcpu);
3960
3961         pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
3962         if (cpu_has_secondary_exec_ctrls()) {
3963                 if (kvm_vcpu_apicv_active(vcpu))
3964                         secondary_exec_controls_setbit(vmx,
3965                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
3966                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3967                 else
3968                         secondary_exec_controls_clearbit(vmx,
3969                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3970                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3971         }
3972
3973         if (cpu_has_vmx_msr_bitmap())
3974                 vmx_update_msr_bitmap(vcpu);
3975 }
3976
3977 u32 vmx_exec_control(struct vcpu_vmx *vmx)
3978 {
3979         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3980
3981         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
3982                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
3983
3984         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
3985                 exec_control &= ~CPU_BASED_TPR_SHADOW;
3986 #ifdef CONFIG_X86_64
3987                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3988                                 CPU_BASED_CR8_LOAD_EXITING;
3989 #endif
3990         }
3991         if (!enable_ept)
3992                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3993                                 CPU_BASED_CR3_LOAD_EXITING  |
3994                                 CPU_BASED_INVLPG_EXITING;
3995         if (kvm_mwait_in_guest(vmx->vcpu.kvm))
3996                 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
3997                                 CPU_BASED_MONITOR_EXITING);
3998         if (kvm_hlt_in_guest(vmx->vcpu.kvm))
3999                 exec_control &= ~CPU_BASED_HLT_EXITING;
4000         return exec_control;
4001 }
4002
4003
4004 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
4005 {
4006         struct kvm_vcpu *vcpu = &vmx->vcpu;
4007
4008         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4009
4010         if (pt_mode == PT_MODE_SYSTEM)
4011                 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
4012         if (!cpu_need_virtualize_apic_accesses(vcpu))
4013                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4014         if (vmx->vpid == 0)
4015                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4016         if (!enable_ept) {
4017                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4018                 enable_unrestricted_guest = 0;
4019         }
4020         if (!enable_unrestricted_guest)
4021                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4022         if (kvm_pause_in_guest(vmx->vcpu.kvm))
4023                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4024         if (!kvm_vcpu_apicv_active(vcpu))
4025                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4026                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4027         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4028
4029         /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
4030          * in vmx_set_cr4.  */
4031         exec_control &= ~SECONDARY_EXEC_DESC;
4032
4033         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4034            (handle_vmptrld).
4035            We can NOT enable shadow_vmcs here because we don't have yet
4036            a current VMCS12
4037         */
4038         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4039
4040         if (!enable_pml)
4041                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4042
4043         if (vmx_xsaves_supported()) {
4044                 /* Exposing XSAVES only when XSAVE is exposed */
4045                 bool xsaves_enabled =
4046                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4047                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
4048
4049                 if (!xsaves_enabled)
4050                         exec_control &= ~SECONDARY_EXEC_XSAVES;
4051
4052                 if (nested) {
4053                         if (xsaves_enabled)
4054                                 vmx->nested.msrs.secondary_ctls_high |=
4055                                         SECONDARY_EXEC_XSAVES;
4056                         else
4057                                 vmx->nested.msrs.secondary_ctls_high &=
4058                                         ~SECONDARY_EXEC_XSAVES;
4059                 }
4060         }
4061
4062         if (vmx_rdtscp_supported()) {
4063                 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
4064                 if (!rdtscp_enabled)
4065                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
4066
4067                 if (nested) {
4068                         if (rdtscp_enabled)
4069                                 vmx->nested.msrs.secondary_ctls_high |=
4070                                         SECONDARY_EXEC_RDTSCP;
4071                         else
4072                                 vmx->nested.msrs.secondary_ctls_high &=
4073                                         ~SECONDARY_EXEC_RDTSCP;
4074                 }
4075         }
4076
4077         if (vmx_invpcid_supported()) {
4078                 /* Exposing INVPCID only when PCID is exposed */
4079                 bool invpcid_enabled =
4080                         guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
4081                         guest_cpuid_has(vcpu, X86_FEATURE_PCID);
4082
4083                 if (!invpcid_enabled) {
4084                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4085                         guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
4086                 }
4087
4088                 if (nested) {
4089                         if (invpcid_enabled)
4090                                 vmx->nested.msrs.secondary_ctls_high |=
4091                                         SECONDARY_EXEC_ENABLE_INVPCID;
4092                         else
4093                                 vmx->nested.msrs.secondary_ctls_high &=
4094                                         ~SECONDARY_EXEC_ENABLE_INVPCID;
4095                 }
4096         }
4097
4098         if (vmx_rdrand_supported()) {
4099                 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
4100                 if (rdrand_enabled)
4101                         exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
4102
4103                 if (nested) {
4104                         if (rdrand_enabled)
4105                                 vmx->nested.msrs.secondary_ctls_high |=
4106                                         SECONDARY_EXEC_RDRAND_EXITING;
4107                         else
4108                                 vmx->nested.msrs.secondary_ctls_high &=
4109                                         ~SECONDARY_EXEC_RDRAND_EXITING;
4110                 }
4111         }
4112
4113         if (vmx_rdseed_supported()) {
4114                 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
4115                 if (rdseed_enabled)
4116                         exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
4117
4118                 if (nested) {
4119                         if (rdseed_enabled)
4120                                 vmx->nested.msrs.secondary_ctls_high |=
4121                                         SECONDARY_EXEC_RDSEED_EXITING;
4122                         else
4123                                 vmx->nested.msrs.secondary_ctls_high &=
4124                                         ~SECONDARY_EXEC_RDSEED_EXITING;
4125                 }
4126         }
4127
4128         if (vmx_waitpkg_supported()) {
4129                 bool waitpkg_enabled =
4130                         guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG);
4131
4132                 if (!waitpkg_enabled)
4133                         exec_control &= ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4134
4135                 if (nested) {
4136                         if (waitpkg_enabled)
4137                                 vmx->nested.msrs.secondary_ctls_high |=
4138                                         SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4139                         else
4140                                 vmx->nested.msrs.secondary_ctls_high &=
4141                                         ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4142                 }
4143         }
4144
4145         vmx->secondary_exec_control = exec_control;
4146 }
4147
4148 static void ept_set_mmio_spte_mask(void)
4149 {
4150         /*
4151          * EPT Misconfigurations can be generated if the value of bits 2:0
4152          * of an EPT paging-structure entry is 110b (write/execute).
4153          */
4154         kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
4155                                    VMX_EPT_MISCONFIG_WX_VALUE, 0);
4156 }
4157
4158 #define VMX_XSS_EXIT_BITMAP 0
4159
4160 /*
4161  * Sets up the vmcs for emulated real mode.
4162  */
4163 static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
4164 {
4165         int i;
4166
4167         if (nested)
4168                 nested_vmx_vcpu_setup();
4169
4170         if (cpu_has_vmx_msr_bitmap())
4171                 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
4172
4173         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4174
4175         /* Control */
4176         pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4177         vmx->hv_deadline_tsc = -1;
4178
4179         exec_controls_set(vmx, vmx_exec_control(vmx));
4180
4181         if (cpu_has_secondary_exec_ctrls()) {
4182                 vmx_compute_secondary_exec_control(vmx);
4183                 secondary_exec_controls_set(vmx, vmx->secondary_exec_control);
4184         }
4185
4186         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4187                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4188                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4189                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4190                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4191
4192                 vmcs_write16(GUEST_INTR_STATUS, 0);
4193
4194                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4195                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4196         }
4197
4198         if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4199                 vmcs_write32(PLE_GAP, ple_gap);
4200                 vmx->ple_window = ple_window;
4201                 vmx->ple_window_dirty = true;
4202         }
4203
4204         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4205         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4206         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4207
4208         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4209         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4210         vmx_set_constant_host_state(vmx);
4211         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4212         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4213
4214         if (cpu_has_vmx_vmfunc())
4215                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4216
4217         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4218         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4219         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
4220         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4221         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
4222
4223         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4224                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4225
4226         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4227                 u32 index = vmx_msr_index[i];
4228                 u32 data_low, data_high;
4229                 int j = vmx->nmsrs;
4230
4231                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4232                         continue;
4233                 if (wrmsr_safe(index, data_low, data_high) < 0)
4234                         continue;
4235                 vmx->guest_msrs[j].index = i;
4236                 vmx->guest_msrs[j].data = 0;
4237                 vmx->guest_msrs[j].mask = -1ull;
4238                 ++vmx->nmsrs;
4239         }
4240
4241         vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
4242
4243         /* 22.2.1, 20.8.1 */
4244         vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
4245
4246         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
4247         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
4248
4249         set_cr4_guest_host_mask(vmx);
4250
4251         if (vmx_xsaves_supported())
4252                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4253
4254         if (enable_pml) {
4255                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4256                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4257         }
4258
4259         if (cpu_has_vmx_encls_vmexit())
4260                 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
4261
4262         if (pt_mode == PT_MODE_HOST_GUEST) {
4263                 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4264                 /* Bit[6~0] are forced to 1, writes are ignored. */
4265                 vmx->pt_desc.guest.output_mask = 0x7F;
4266                 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4267         }
4268 }
4269
4270 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4271 {
4272         struct vcpu_vmx *vmx = to_vmx(vcpu);
4273         struct msr_data apic_base_msr;
4274         u64 cr0;
4275
4276         vmx->rmode.vm86_active = 0;
4277         vmx->spec_ctrl = 0;
4278
4279         vmx->msr_ia32_umwait_control = 0;
4280
4281         vcpu->arch.microcode_version = 0x100000000ULL;
4282         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4283         vmx->hv_deadline_tsc = -1;
4284         kvm_set_cr8(vcpu, 0);
4285
4286         if (!init_event) {
4287                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4288                                      MSR_IA32_APICBASE_ENABLE;
4289                 if (kvm_vcpu_is_reset_bsp(vcpu))
4290                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4291                 apic_base_msr.host_initiated = true;
4292                 kvm_set_apic_base(vcpu, &apic_base_msr);
4293         }
4294
4295         vmx_segment_cache_clear(vmx);
4296
4297         seg_setup(VCPU_SREG_CS);
4298         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4299         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4300
4301         seg_setup(VCPU_SREG_DS);
4302         seg_setup(VCPU_SREG_ES);
4303         seg_setup(VCPU_SREG_FS);
4304         seg_setup(VCPU_SREG_GS);
4305         seg_setup(VCPU_SREG_SS);
4306
4307         vmcs_write16(GUEST_TR_SELECTOR, 0);
4308         vmcs_writel(GUEST_TR_BASE, 0);
4309         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4310         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4311
4312         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4313         vmcs_writel(GUEST_LDTR_BASE, 0);
4314         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4315         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4316
4317         if (!init_event) {
4318                 vmcs_write32(GUEST_SYSENTER_CS, 0);
4319                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4320                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4321                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4322         }
4323
4324         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
4325         kvm_rip_write(vcpu, 0xfff0);
4326
4327         vmcs_writel(GUEST_GDTR_BASE, 0);
4328         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4329
4330         vmcs_writel(GUEST_IDTR_BASE, 0);
4331         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4332
4333         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4334         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4335         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4336         if (kvm_mpx_supported())
4337                 vmcs_write64(GUEST_BNDCFGS, 0);
4338
4339         setup_msrs(vmx);
4340
4341         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4342
4343         if (cpu_has_vmx_tpr_shadow() && !init_event) {
4344                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4345                 if (cpu_need_tpr_shadow(vcpu))
4346                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4347                                      __pa(vcpu->arch.apic->regs));
4348                 vmcs_write32(TPR_THRESHOLD, 0);
4349         }
4350
4351         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4352
4353         if (vmx->vpid != 0)
4354                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4355
4356         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4357         vmx->vcpu.arch.cr0 = cr0;
4358         vmx_set_cr0(vcpu, cr0); /* enter rmode */
4359         vmx_set_cr4(vcpu, 0);
4360         vmx_set_efer(vcpu, 0);
4361
4362         update_exception_bitmap(vcpu);
4363
4364         vpid_sync_context(vmx->vpid);
4365         if (init_event)
4366                 vmx_clear_hlt(vcpu);
4367 }
4368
4369 static void enable_irq_window(struct kvm_vcpu *vcpu)
4370 {
4371         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_INTR_PENDING);
4372 }
4373
4374 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4375 {
4376         if (!enable_vnmi ||
4377             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4378                 enable_irq_window(vcpu);
4379                 return;
4380         }
4381
4382         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_NMI_PENDING);
4383 }
4384
4385 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4386 {
4387         struct vcpu_vmx *vmx = to_vmx(vcpu);
4388         uint32_t intr;
4389         int irq = vcpu->arch.interrupt.nr;
4390
4391         trace_kvm_inj_virq(irq);
4392
4393         ++vcpu->stat.irq_injections;
4394         if (vmx->rmode.vm86_active) {
4395                 int inc_eip = 0;
4396                 if (vcpu->arch.interrupt.soft)
4397                         inc_eip = vcpu->arch.event_exit_inst_len;
4398                 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
4399                 return;
4400         }
4401         intr = irq | INTR_INFO_VALID_MASK;
4402         if (vcpu->arch.interrupt.soft) {
4403                 intr |= INTR_TYPE_SOFT_INTR;
4404                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4405                              vmx->vcpu.arch.event_exit_inst_len);
4406         } else
4407                 intr |= INTR_TYPE_EXT_INTR;
4408         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4409
4410         vmx_clear_hlt(vcpu);
4411 }
4412
4413 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4414 {
4415         struct vcpu_vmx *vmx = to_vmx(vcpu);
4416
4417         if (!enable_vnmi) {
4418                 /*
4419                  * Tracking the NMI-blocked state in software is built upon
4420                  * finding the next open IRQ window. This, in turn, depends on
4421                  * well-behaving guests: They have to keep IRQs disabled at
4422                  * least as long as the NMI handler runs. Otherwise we may
4423                  * cause NMI nesting, maybe breaking the guest. But as this is
4424                  * highly unlikely, we can live with the residual risk.
4425                  */
4426                 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4427                 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4428         }
4429
4430         ++vcpu->stat.nmi_injections;
4431         vmx->loaded_vmcs->nmi_known_unmasked = false;
4432
4433         if (vmx->rmode.vm86_active) {
4434                 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
4435                 return;
4436         }
4437
4438         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4439                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4440
4441         vmx_clear_hlt(vcpu);
4442 }
4443
4444 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4445 {
4446         struct vcpu_vmx *vmx = to_vmx(vcpu);
4447         bool masked;
4448
4449         if (!enable_vnmi)
4450                 return vmx->loaded_vmcs->soft_vnmi_blocked;
4451         if (vmx->loaded_vmcs->nmi_known_unmasked)
4452                 return false;
4453         masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4454         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4455         return masked;
4456 }
4457
4458 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4459 {
4460         struct vcpu_vmx *vmx = to_vmx(vcpu);
4461
4462         if (!enable_vnmi) {
4463                 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4464                         vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4465                         vmx->loaded_vmcs->vnmi_blocked_time = 0;
4466                 }
4467         } else {
4468                 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4469                 if (masked)
4470                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4471                                       GUEST_INTR_STATE_NMI);
4472                 else
4473                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4474                                         GUEST_INTR_STATE_NMI);
4475         }
4476 }
4477
4478 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4479 {
4480         if (to_vmx(vcpu)->nested.nested_run_pending)
4481                 return 0;
4482
4483         if (!enable_vnmi &&
4484             to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4485                 return 0;
4486
4487         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4488                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4489                    | GUEST_INTR_STATE_NMI));
4490 }
4491
4492 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4493 {
4494         return (!to_vmx(vcpu)->nested.nested_run_pending &&
4495                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4496                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4497                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4498 }
4499
4500 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4501 {
4502         int ret;
4503
4504         if (enable_unrestricted_guest)
4505                 return 0;
4506
4507         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4508                                     PAGE_SIZE * 3);
4509         if (ret)
4510                 return ret;
4511         to_kvm_vmx(kvm)->tss_addr = addr;
4512         return init_rmode_tss(kvm);
4513 }
4514
4515 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4516 {
4517         to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
4518         return 0;
4519 }
4520
4521 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4522 {
4523         switch (vec) {
4524         case BP_VECTOR:
4525                 /*
4526                  * Update instruction length as we may reinject the exception
4527                  * from user space while in guest debugging mode.
4528                  */
4529                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4530                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4531                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4532                         return false;
4533                 /* fall through */
4534         case DB_VECTOR:
4535                 if (vcpu->guest_debug &
4536                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4537                         return false;
4538                 /* fall through */
4539         case DE_VECTOR:
4540         case OF_VECTOR:
4541         case BR_VECTOR:
4542         case UD_VECTOR:
4543         case DF_VECTOR:
4544         case SS_VECTOR:
4545         case GP_VECTOR:
4546         case MF_VECTOR:
4547                 return true;
4548         break;
4549         }
4550         return false;
4551 }
4552
4553 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4554                                   int vec, u32 err_code)
4555 {
4556         /*
4557          * Instruction with address size override prefix opcode 0x67
4558          * Cause the #SS fault with 0 error code in VM86 mode.
4559          */
4560         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4561                 if (kvm_emulate_instruction(vcpu, 0)) {
4562                         if (vcpu->arch.halt_request) {
4563                                 vcpu->arch.halt_request = 0;
4564                                 return kvm_vcpu_halt(vcpu);
4565                         }
4566                         return 1;
4567                 }
4568                 return 0;
4569         }
4570
4571         /*
4572          * Forward all other exceptions that are valid in real mode.
4573          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4574          *        the required debugging infrastructure rework.
4575          */
4576         kvm_queue_exception(vcpu, vec);
4577         return 1;
4578 }
4579
4580 /*
4581  * Trigger machine check on the host. We assume all the MSRs are already set up
4582  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4583  * We pass a fake environment to the machine check handler because we want
4584  * the guest to be always treated like user space, no matter what context
4585  * it used internally.
4586  */
4587 static void kvm_machine_check(void)
4588 {
4589 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4590         struct pt_regs regs = {
4591                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4592                 .flags = X86_EFLAGS_IF,
4593         };
4594
4595         do_machine_check(&regs, 0);
4596 #endif
4597 }
4598
4599 static int handle_machine_check(struct kvm_vcpu *vcpu)
4600 {
4601         /* handled by vmx_vcpu_run() */
4602         return 1;
4603 }
4604
4605 static int handle_exception_nmi(struct kvm_vcpu *vcpu)
4606 {
4607         struct vcpu_vmx *vmx = to_vmx(vcpu);
4608         struct kvm_run *kvm_run = vcpu->run;
4609         u32 intr_info, ex_no, error_code;
4610         unsigned long cr2, rip, dr6;
4611         u32 vect_info;
4612
4613         vect_info = vmx->idt_vectoring_info;
4614         intr_info = vmx->exit_intr_info;
4615
4616         if (is_machine_check(intr_info) || is_nmi(intr_info))
4617                 return 1; /* handled by handle_exception_nmi_irqoff() */
4618
4619         if (is_invalid_opcode(intr_info))
4620                 return handle_ud(vcpu);
4621
4622         error_code = 0;
4623         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4624                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4625
4626         if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4627                 WARN_ON_ONCE(!enable_vmware_backdoor);
4628
4629                 /*
4630                  * VMware backdoor emulation on #GP interception only handles
4631                  * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
4632                  * error code on #GP.
4633                  */
4634                 if (error_code) {
4635                         kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4636                         return 1;
4637                 }
4638                 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
4639         }
4640
4641         /*
4642          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4643          * MMIO, it is better to report an internal error.
4644          * See the comments in vmx_handle_exit.
4645          */
4646         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4647             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4648                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4649                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4650                 vcpu->run->internal.ndata = 3;
4651                 vcpu->run->internal.data[0] = vect_info;
4652                 vcpu->run->internal.data[1] = intr_info;
4653                 vcpu->run->internal.data[2] = error_code;
4654                 return 0;
4655         }
4656
4657         if (is_page_fault(intr_info)) {
4658                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4659                 /* EPT won't cause page fault directly */
4660                 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
4661                 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
4662         }
4663
4664         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4665
4666         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4667                 return handle_rmode_exception(vcpu, ex_no, error_code);
4668
4669         switch (ex_no) {
4670         case AC_VECTOR:
4671                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4672                 return 1;
4673         case DB_VECTOR:
4674                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4675                 if (!(vcpu->guest_debug &
4676                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4677                         vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4678                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
4679                         if (is_icebp(intr_info))
4680                                 WARN_ON(!skip_emulated_instruction(vcpu));
4681
4682                         kvm_queue_exception(vcpu, DB_VECTOR);
4683                         return 1;
4684                 }
4685                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4686                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4687                 /* fall through */
4688         case BP_VECTOR:
4689                 /*
4690                  * Update instruction length as we may reinject #BP from
4691                  * user space while in guest debugging mode. Reading it for
4692                  * #DB as well causes no harm, it is not used in that case.
4693                  */
4694                 vmx->vcpu.arch.event_exit_inst_len =
4695                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4696                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4697                 rip = kvm_rip_read(vcpu);
4698                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4699                 kvm_run->debug.arch.exception = ex_no;
4700                 break;
4701         default:
4702                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4703                 kvm_run->ex.exception = ex_no;
4704                 kvm_run->ex.error_code = error_code;
4705                 break;
4706         }
4707         return 0;
4708 }
4709
4710 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4711 {
4712         ++vcpu->stat.irq_exits;
4713         return 1;
4714 }
4715
4716 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4717 {
4718         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4719         vcpu->mmio_needed = 0;
4720         return 0;
4721 }
4722
4723 static int handle_io(struct kvm_vcpu *vcpu)
4724 {
4725         unsigned long exit_qualification;
4726         int size, in, string;
4727         unsigned port;
4728
4729         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4730         string = (exit_qualification & 16) != 0;
4731
4732         ++vcpu->stat.io_exits;
4733
4734         if (string)
4735                 return kvm_emulate_instruction(vcpu, 0);
4736
4737         port = exit_qualification >> 16;
4738         size = (exit_qualification & 7) + 1;
4739         in = (exit_qualification & 8) != 0;
4740
4741         return kvm_fast_pio(vcpu, size, port, in);
4742 }
4743
4744 static void
4745 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4746 {
4747         /*
4748          * Patch in the VMCALL instruction:
4749          */
4750         hypercall[0] = 0x0f;
4751         hypercall[1] = 0x01;
4752         hypercall[2] = 0xc1;
4753 }
4754
4755 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4756 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4757 {
4758         if (is_guest_mode(vcpu)) {
4759                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4760                 unsigned long orig_val = val;
4761
4762                 /*
4763                  * We get here when L2 changed cr0 in a way that did not change
4764                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4765                  * but did change L0 shadowed bits. So we first calculate the
4766                  * effective cr0 value that L1 would like to write into the
4767                  * hardware. It consists of the L2-owned bits from the new
4768                  * value combined with the L1-owned bits from L1's guest_cr0.
4769                  */
4770                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4771                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4772
4773                 if (!nested_guest_cr0_valid(vcpu, val))
4774                         return 1;
4775
4776                 if (kvm_set_cr0(vcpu, val))
4777                         return 1;
4778                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4779                 return 0;
4780         } else {
4781                 if (to_vmx(vcpu)->nested.vmxon &&
4782                     !nested_host_cr0_valid(vcpu, val))
4783                         return 1;
4784
4785                 return kvm_set_cr0(vcpu, val);
4786         }
4787 }
4788
4789 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4790 {
4791         if (is_guest_mode(vcpu)) {
4792                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4793                 unsigned long orig_val = val;
4794
4795                 /* analogously to handle_set_cr0 */
4796                 val = (val & ~vmcs12->cr4_guest_host_mask) |
4797                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4798                 if (kvm_set_cr4(vcpu, val))
4799                         return 1;
4800                 vmcs_writel(CR4_READ_SHADOW, orig_val);
4801                 return 0;
4802         } else
4803                 return kvm_set_cr4(vcpu, val);
4804 }
4805
4806 static int handle_desc(struct kvm_vcpu *vcpu)
4807 {
4808         WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
4809         return kvm_emulate_instruction(vcpu, 0);
4810 }
4811
4812 static int handle_cr(struct kvm_vcpu *vcpu)
4813 {
4814         unsigned long exit_qualification, val;
4815         int cr;
4816         int reg;
4817         int err;
4818         int ret;
4819
4820         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4821         cr = exit_qualification & 15;
4822         reg = (exit_qualification >> 8) & 15;
4823         switch ((exit_qualification >> 4) & 3) {
4824         case 0: /* mov to cr */
4825                 val = kvm_register_readl(vcpu, reg);
4826                 trace_kvm_cr_write(cr, val);
4827                 switch (cr) {
4828                 case 0:
4829                         err = handle_set_cr0(vcpu, val);
4830                         return kvm_complete_insn_gp(vcpu, err);
4831                 case 3:
4832                         WARN_ON_ONCE(enable_unrestricted_guest);
4833                         err = kvm_set_cr3(vcpu, val);
4834                         return kvm_complete_insn_gp(vcpu, err);
4835                 case 4:
4836                         err = handle_set_cr4(vcpu, val);
4837                         return kvm_complete_insn_gp(vcpu, err);
4838                 case 8: {
4839                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4840                                 u8 cr8 = (u8)val;
4841                                 err = kvm_set_cr8(vcpu, cr8);
4842                                 ret = kvm_complete_insn_gp(vcpu, err);
4843                                 if (lapic_in_kernel(vcpu))
4844                                         return ret;
4845                                 if (cr8_prev <= cr8)
4846                                         return ret;
4847                                 /*
4848                                  * TODO: we might be squashing a
4849                                  * KVM_GUESTDBG_SINGLESTEP-triggered
4850                                  * KVM_EXIT_DEBUG here.
4851                                  */
4852                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4853                                 return 0;
4854                         }
4855                 }
4856                 break;
4857         case 2: /* clts */
4858                 WARN_ONCE(1, "Guest should always own CR0.TS");
4859                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4860                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4861                 return kvm_skip_emulated_instruction(vcpu);
4862         case 1: /*mov from cr*/
4863                 switch (cr) {
4864                 case 3:
4865                         WARN_ON_ONCE(enable_unrestricted_guest);
4866                         val = kvm_read_cr3(vcpu);
4867                         kvm_register_write(vcpu, reg, val);
4868                         trace_kvm_cr_read(cr, val);
4869                         return kvm_skip_emulated_instruction(vcpu);
4870                 case 8:
4871                         val = kvm_get_cr8(vcpu);
4872                         kvm_register_write(vcpu, reg, val);
4873                         trace_kvm_cr_read(cr, val);
4874                         return kvm_skip_emulated_instruction(vcpu);
4875                 }
4876                 break;
4877         case 3: /* lmsw */
4878                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4879                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4880                 kvm_lmsw(vcpu, val);
4881
4882                 return kvm_skip_emulated_instruction(vcpu);
4883         default:
4884                 break;
4885         }
4886         vcpu->run->exit_reason = 0;
4887         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4888                (int)(exit_qualification >> 4) & 3, cr);
4889         return 0;
4890 }
4891
4892 static int handle_dr(struct kvm_vcpu *vcpu)
4893 {
4894         unsigned long exit_qualification;
4895         int dr, dr7, reg;
4896
4897         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4898         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4899
4900         /* First, if DR does not exist, trigger UD */
4901         if (!kvm_require_dr(vcpu, dr))
4902                 return 1;
4903
4904         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4905         if (!kvm_require_cpl(vcpu, 0))
4906                 return 1;
4907         dr7 = vmcs_readl(GUEST_DR7);
4908         if (dr7 & DR7_GD) {
4909                 /*
4910                  * As the vm-exit takes precedence over the debug trap, we
4911                  * need to emulate the latter, either for the host or the
4912                  * guest debugging itself.
4913                  */
4914                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4915                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4916                         vcpu->run->debug.arch.dr7 = dr7;
4917                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
4918                         vcpu->run->debug.arch.exception = DB_VECTOR;
4919                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4920                         return 0;
4921                 } else {
4922                         vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4923                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
4924                         kvm_queue_exception(vcpu, DB_VECTOR);
4925                         return 1;
4926                 }
4927         }
4928
4929         if (vcpu->guest_debug == 0) {
4930                 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
4931
4932                 /*
4933                  * No more DR vmexits; force a reload of the debug registers
4934                  * and reenter on this instruction.  The next vmexit will
4935                  * retrieve the full state of the debug registers.
4936                  */
4937                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4938                 return 1;
4939         }
4940
4941         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4942         if (exit_qualification & TYPE_MOV_FROM_DR) {
4943                 unsigned long val;
4944
4945                 if (kvm_get_dr(vcpu, dr, &val))
4946                         return 1;
4947                 kvm_register_write(vcpu, reg, val);
4948         } else
4949                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4950                         return 1;
4951
4952         return kvm_skip_emulated_instruction(vcpu);
4953 }
4954
4955 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
4956 {
4957         return vcpu->arch.dr6;
4958 }
4959
4960 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
4961 {
4962 }
4963
4964 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
4965 {
4966         get_debugreg(vcpu->arch.db[0], 0);
4967         get_debugreg(vcpu->arch.db[1], 1);
4968         get_debugreg(vcpu->arch.db[2], 2);
4969         get_debugreg(vcpu->arch.db[3], 3);
4970         get_debugreg(vcpu->arch.dr6, 6);
4971         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
4972
4973         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
4974         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
4975 }
4976
4977 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4978 {
4979         vmcs_writel(GUEST_DR7, val);
4980 }
4981
4982 static int handle_cpuid(struct kvm_vcpu *vcpu)
4983 {
4984         return kvm_emulate_cpuid(vcpu);
4985 }
4986
4987 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4988 {
4989         return kvm_emulate_rdmsr(vcpu);
4990 }
4991
4992 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4993 {
4994         return kvm_emulate_wrmsr(vcpu);
4995 }
4996
4997 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4998 {
4999         kvm_apic_update_ppr(vcpu);
5000         return 1;
5001 }
5002
5003 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5004 {
5005         exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_INTR_PENDING);
5006
5007         kvm_make_request(KVM_REQ_EVENT, vcpu);
5008
5009         ++vcpu->stat.irq_window_exits;
5010         return 1;
5011 }
5012
5013 static int handle_halt(struct kvm_vcpu *vcpu)
5014 {
5015         return kvm_emulate_halt(vcpu);
5016 }
5017
5018 static int handle_vmcall(struct kvm_vcpu *vcpu)
5019 {
5020         return kvm_emulate_hypercall(vcpu);
5021 }
5022
5023 static int handle_invd(struct kvm_vcpu *vcpu)
5024 {
5025         return kvm_emulate_instruction(vcpu, 0);
5026 }
5027
5028 static int handle_invlpg(struct kvm_vcpu *vcpu)
5029 {
5030         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5031
5032         kvm_mmu_invlpg(vcpu, exit_qualification);
5033         return kvm_skip_emulated_instruction(vcpu);
5034 }
5035
5036 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5037 {
5038         int err;
5039
5040         err = kvm_rdpmc(vcpu);
5041         return kvm_complete_insn_gp(vcpu, err);
5042 }
5043
5044 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5045 {
5046         return kvm_emulate_wbinvd(vcpu);
5047 }
5048
5049 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5050 {
5051         u64 new_bv = kvm_read_edx_eax(vcpu);
5052         u32 index = kvm_rcx_read(vcpu);
5053
5054         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5055                 return kvm_skip_emulated_instruction(vcpu);
5056         return 1;
5057 }
5058
5059 static int handle_apic_access(struct kvm_vcpu *vcpu)
5060 {
5061         if (likely(fasteoi)) {
5062                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5063                 int access_type, offset;
5064
5065                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5066                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5067                 /*
5068                  * Sane guest uses MOV to write EOI, with written value
5069                  * not cared. So make a short-circuit here by avoiding
5070                  * heavy instruction emulation.
5071                  */
5072                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5073                     (offset == APIC_EOI)) {
5074                         kvm_lapic_set_eoi(vcpu);
5075                         return kvm_skip_emulated_instruction(vcpu);
5076                 }
5077         }
5078         return kvm_emulate_instruction(vcpu, 0);
5079 }
5080
5081 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5082 {
5083         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5084         int vector = exit_qualification & 0xff;
5085
5086         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5087         kvm_apic_set_eoi_accelerated(vcpu, vector);
5088         return 1;
5089 }
5090
5091 static int handle_apic_write(struct kvm_vcpu *vcpu)
5092 {
5093         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5094         u32 offset = exit_qualification & 0xfff;
5095
5096         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5097         kvm_apic_write_nodecode(vcpu, offset);
5098         return 1;
5099 }
5100
5101 static int handle_task_switch(struct kvm_vcpu *vcpu)
5102 {
5103         struct vcpu_vmx *vmx = to_vmx(vcpu);
5104         unsigned long exit_qualification;
5105         bool has_error_code = false;
5106         u32 error_code = 0;
5107         u16 tss_selector;
5108         int reason, type, idt_v, idt_index;
5109
5110         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5111         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5112         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5113
5114         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5115
5116         reason = (u32)exit_qualification >> 30;
5117         if (reason == TASK_SWITCH_GATE && idt_v) {
5118                 switch (type) {
5119                 case INTR_TYPE_NMI_INTR:
5120                         vcpu->arch.nmi_injected = false;
5121                         vmx_set_nmi_mask(vcpu, true);
5122                         break;
5123                 case INTR_TYPE_EXT_INTR:
5124                 case INTR_TYPE_SOFT_INTR:
5125                         kvm_clear_interrupt_queue(vcpu);
5126                         break;
5127                 case INTR_TYPE_HARD_EXCEPTION:
5128                         if (vmx->idt_vectoring_info &
5129                             VECTORING_INFO_DELIVER_CODE_MASK) {
5130                                 has_error_code = true;
5131                                 error_code =
5132                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5133                         }
5134                         /* fall through */
5135                 case INTR_TYPE_SOFT_EXCEPTION:
5136                         kvm_clear_exception_queue(vcpu);
5137                         break;
5138                 default:
5139                         break;
5140                 }
5141         }
5142         tss_selector = exit_qualification;
5143
5144         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5145                        type != INTR_TYPE_EXT_INTR &&
5146                        type != INTR_TYPE_NMI_INTR))
5147                 WARN_ON(!skip_emulated_instruction(vcpu));
5148
5149         /*
5150          * TODO: What about debug traps on tss switch?
5151          *       Are we supposed to inject them and update dr6?
5152          */
5153         return kvm_task_switch(vcpu, tss_selector,
5154                                type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
5155                                reason, has_error_code, error_code);
5156 }
5157
5158 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5159 {
5160         unsigned long exit_qualification;
5161         gpa_t gpa;
5162         u64 error_code;
5163
5164         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5165
5166         /*
5167          * EPT violation happened while executing iret from NMI,
5168          * "blocked by NMI" bit has to be set before next VM entry.
5169          * There are errata that may cause this bit to not be set:
5170          * AAK134, BY25.
5171          */
5172         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5173                         enable_vnmi &&
5174                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5175                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5176
5177         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5178         trace_kvm_page_fault(gpa, exit_qualification);
5179
5180         /* Is it a read fault? */
5181         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
5182                      ? PFERR_USER_MASK : 0;
5183         /* Is it a write fault? */
5184         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
5185                       ? PFERR_WRITE_MASK : 0;
5186         /* Is it a fetch fault? */
5187         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
5188                       ? PFERR_FETCH_MASK : 0;
5189         /* ept page table entry is present? */
5190         error_code |= (exit_qualification &
5191                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5192                         EPT_VIOLATION_EXECUTABLE))
5193                       ? PFERR_PRESENT_MASK : 0;
5194
5195         error_code |= (exit_qualification & 0x100) != 0 ?
5196                PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
5197
5198         vcpu->arch.exit_qualification = exit_qualification;
5199         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5200 }
5201
5202 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5203 {
5204         gpa_t gpa;
5205
5206         /*
5207          * A nested guest cannot optimize MMIO vmexits, because we have an
5208          * nGPA here instead of the required GPA.
5209          */
5210         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5211         if (!is_guest_mode(vcpu) &&
5212             !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5213                 trace_kvm_fast_mmio(gpa);
5214                 return kvm_skip_emulated_instruction(vcpu);
5215         }
5216
5217         return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
5218 }
5219
5220 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5221 {
5222         WARN_ON_ONCE(!enable_vnmi);
5223         exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_NMI_PENDING);
5224         ++vcpu->stat.nmi_window_exits;
5225         kvm_make_request(KVM_REQ_EVENT, vcpu);
5226
5227         return 1;
5228 }
5229
5230 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5231 {
5232         struct vcpu_vmx *vmx = to_vmx(vcpu);
5233         bool intr_window_requested;
5234         unsigned count = 130;
5235
5236         /*
5237          * We should never reach the point where we are emulating L2
5238          * due to invalid guest state as that means we incorrectly
5239          * allowed a nested VMEntry with an invalid vmcs12.
5240          */
5241         WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
5242
5243         intr_window_requested = exec_controls_get(vmx) &
5244                                 CPU_BASED_VIRTUAL_INTR_PENDING;
5245
5246         while (vmx->emulation_required && count-- != 0) {
5247                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5248                         return handle_interrupt_window(&vmx->vcpu);
5249
5250                 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
5251                         return 1;
5252
5253                 if (!kvm_emulate_instruction(vcpu, 0))
5254                         return 0;
5255
5256                 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5257                     vcpu->arch.exception.pending) {
5258                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5259                         vcpu->run->internal.suberror =
5260                                                 KVM_INTERNAL_ERROR_EMULATION;
5261                         vcpu->run->internal.ndata = 0;
5262                         return 0;
5263                 }
5264
5265                 if (vcpu->arch.halt_request) {
5266                         vcpu->arch.halt_request = 0;
5267                         return kvm_vcpu_halt(vcpu);
5268                 }
5269
5270                 /*
5271                  * Note, return 1 and not 0, vcpu_run() is responsible for
5272                  * morphing the pending signal into the proper return code.
5273                  */
5274                 if (signal_pending(current))
5275                         return 1;
5276
5277                 if (need_resched())
5278                         schedule();
5279         }
5280
5281         return 1;
5282 }
5283
5284 static void grow_ple_window(struct kvm_vcpu *vcpu)
5285 {
5286         struct vcpu_vmx *vmx = to_vmx(vcpu);
5287         unsigned int old = vmx->ple_window;
5288
5289         vmx->ple_window = __grow_ple_window(old, ple_window,
5290                                             ple_window_grow,
5291                                             ple_window_max);
5292
5293         if (vmx->ple_window != old) {
5294                 vmx->ple_window_dirty = true;
5295                 trace_kvm_ple_window_update(vcpu->vcpu_id,
5296                                             vmx->ple_window, old);
5297         }
5298 }
5299
5300 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5301 {
5302         struct vcpu_vmx *vmx = to_vmx(vcpu);
5303         unsigned int old = vmx->ple_window;
5304
5305         vmx->ple_window = __shrink_ple_window(old, ple_window,
5306                                               ple_window_shrink,
5307                                               ple_window);
5308
5309         if (vmx->ple_window != old) {
5310                 vmx->ple_window_dirty = true;
5311                 trace_kvm_ple_window_update(vcpu->vcpu_id,
5312                                             vmx->ple_window, old);
5313         }
5314 }
5315
5316 /*
5317  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
5318  */
5319 static void wakeup_handler(void)
5320 {
5321         struct kvm_vcpu *vcpu;
5322         int cpu = smp_processor_id();
5323
5324         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5325         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
5326                         blocked_vcpu_list) {
5327                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
5328
5329                 if (pi_test_on(pi_desc) == 1)
5330                         kvm_vcpu_kick(vcpu);
5331         }
5332         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5333 }
5334
5335 static void vmx_enable_tdp(void)
5336 {
5337         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
5338                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
5339                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
5340                 0ull, VMX_EPT_EXECUTABLE_MASK,
5341                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
5342                 VMX_EPT_RWX_MASK, 0ull);
5343
5344         ept_set_mmio_spte_mask();
5345         kvm_enable_tdp();
5346 }
5347
5348 /*
5349  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5350  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5351  */
5352 static int handle_pause(struct kvm_vcpu *vcpu)
5353 {
5354         if (!kvm_pause_in_guest(vcpu->kvm))
5355                 grow_ple_window(vcpu);
5356
5357         /*
5358          * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5359          * VM-execution control is ignored if CPL > 0. OTOH, KVM
5360          * never set PAUSE_EXITING and just set PLE if supported,
5361          * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5362          */
5363         kvm_vcpu_on_spin(vcpu, true);
5364         return kvm_skip_emulated_instruction(vcpu);
5365 }
5366
5367 static int handle_nop(struct kvm_vcpu *vcpu)
5368 {
5369         return kvm_skip_emulated_instruction(vcpu);
5370 }
5371
5372 static int handle_mwait(struct kvm_vcpu *vcpu)
5373 {
5374         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5375         return handle_nop(vcpu);
5376 }
5377
5378 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5379 {
5380         kvm_queue_exception(vcpu, UD_VECTOR);
5381         return 1;
5382 }
5383
5384 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5385 {
5386         return 1;
5387 }
5388
5389 static int handle_monitor(struct kvm_vcpu *vcpu)
5390 {
5391         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5392         return handle_nop(vcpu);
5393 }
5394
5395 static int handle_invpcid(struct kvm_vcpu *vcpu)
5396 {
5397         u32 vmx_instruction_info;
5398         unsigned long type;
5399         bool pcid_enabled;
5400         gva_t gva;
5401         struct x86_exception e;
5402         unsigned i;
5403         unsigned long roots_to_free = 0;
5404         struct {
5405                 u64 pcid;
5406                 u64 gla;
5407         } operand;
5408
5409         if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
5410                 kvm_queue_exception(vcpu, UD_VECTOR);
5411                 return 1;
5412         }
5413
5414         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5415         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5416
5417         if (type > 3) {
5418                 kvm_inject_gp(vcpu, 0);
5419                 return 1;
5420         }
5421
5422         /* According to the Intel instruction reference, the memory operand
5423          * is read even if it isn't needed (e.g., for type==all)
5424          */
5425         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5426                                 vmx_instruction_info, false,
5427                                 sizeof(operand), &gva))
5428                 return 1;
5429
5430         if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
5431                 kvm_inject_page_fault(vcpu, &e);
5432                 return 1;
5433         }
5434
5435         if (operand.pcid >> 12 != 0) {
5436                 kvm_inject_gp(vcpu, 0);
5437                 return 1;
5438         }
5439
5440         pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
5441
5442         switch (type) {
5443         case INVPCID_TYPE_INDIV_ADDR:
5444                 if ((!pcid_enabled && (operand.pcid != 0)) ||
5445                     is_noncanonical_address(operand.gla, vcpu)) {
5446                         kvm_inject_gp(vcpu, 0);
5447                         return 1;
5448                 }
5449                 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
5450                 return kvm_skip_emulated_instruction(vcpu);
5451
5452         case INVPCID_TYPE_SINGLE_CTXT:
5453                 if (!pcid_enabled && (operand.pcid != 0)) {
5454                         kvm_inject_gp(vcpu, 0);
5455                         return 1;
5456                 }
5457
5458                 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
5459                         kvm_mmu_sync_roots(vcpu);
5460                         kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
5461                 }
5462
5463                 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5464                         if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3)
5465                             == operand.pcid)
5466                                 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
5467
5468                 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
5469                 /*
5470                  * If neither the current cr3 nor any of the prev_roots use the
5471                  * given PCID, then nothing needs to be done here because a
5472                  * resync will happen anyway before switching to any other CR3.
5473                  */
5474
5475                 return kvm_skip_emulated_instruction(vcpu);
5476
5477         case INVPCID_TYPE_ALL_NON_GLOBAL:
5478                 /*
5479                  * Currently, KVM doesn't mark global entries in the shadow
5480                  * page tables, so a non-global flush just degenerates to a
5481                  * global flush. If needed, we could optimize this later by
5482                  * keeping track of global entries in shadow page tables.
5483                  */
5484
5485                 /* fall-through */
5486         case INVPCID_TYPE_ALL_INCL_GLOBAL:
5487                 kvm_mmu_unload(vcpu);
5488                 return kvm_skip_emulated_instruction(vcpu);
5489
5490         default:
5491                 BUG(); /* We have already checked above that type <= 3 */
5492         }
5493 }
5494
5495 static int handle_pml_full(struct kvm_vcpu *vcpu)
5496 {
5497         unsigned long exit_qualification;
5498
5499         trace_kvm_pml_full(vcpu->vcpu_id);
5500
5501         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5502
5503         /*
5504          * PML buffer FULL happened while executing iret from NMI,
5505          * "blocked by NMI" bit has to be set before next VM entry.
5506          */
5507         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5508                         enable_vnmi &&
5509                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5510                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5511                                 GUEST_INTR_STATE_NMI);
5512
5513         /*
5514          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5515          * here.., and there's no userspace involvement needed for PML.
5516          */
5517         return 1;
5518 }
5519
5520 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
5521 {
5522         struct vcpu_vmx *vmx = to_vmx(vcpu);
5523
5524         if (!vmx->req_immediate_exit &&
5525             !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled))
5526                 kvm_lapic_expired_hv_timer(vcpu);
5527
5528         return 1;
5529 }
5530
5531 /*
5532  * When nested=0, all VMX instruction VM Exits filter here.  The handlers
5533  * are overwritten by nested_vmx_setup() when nested=1.
5534  */
5535 static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
5536 {
5537         kvm_queue_exception(vcpu, UD_VECTOR);
5538         return 1;
5539 }
5540
5541 static int handle_encls(struct kvm_vcpu *vcpu)
5542 {
5543         /*
5544          * SGX virtualization is not yet supported.  There is no software
5545          * enable bit for SGX, so we have to trap ENCLS and inject a #UD
5546          * to prevent the guest from executing ENCLS.
5547          */
5548         kvm_queue_exception(vcpu, UD_VECTOR);
5549         return 1;
5550 }
5551
5552 /*
5553  * The exit handlers return 1 if the exit was handled fully and guest execution
5554  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5555  * to be done to userspace and return 0.
5556  */
5557 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5558         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception_nmi,
5559         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5560         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5561         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5562         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5563         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5564         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5565         [EXIT_REASON_CPUID]                   = handle_cpuid,
5566         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
5567         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
5568         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
5569         [EXIT_REASON_HLT]                     = handle_halt,
5570         [EXIT_REASON_INVD]                    = handle_invd,
5571         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5572         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
5573         [EXIT_REASON_VMCALL]                  = handle_vmcall,
5574         [EXIT_REASON_VMCLEAR]                 = handle_vmx_instruction,
5575         [EXIT_REASON_VMLAUNCH]                = handle_vmx_instruction,
5576         [EXIT_REASON_VMPTRLD]                 = handle_vmx_instruction,
5577         [EXIT_REASON_VMPTRST]                 = handle_vmx_instruction,
5578         [EXIT_REASON_VMREAD]                  = handle_vmx_instruction,
5579         [EXIT_REASON_VMRESUME]                = handle_vmx_instruction,
5580         [EXIT_REASON_VMWRITE]                 = handle_vmx_instruction,
5581         [EXIT_REASON_VMOFF]                   = handle_vmx_instruction,
5582         [EXIT_REASON_VMON]                    = handle_vmx_instruction,
5583         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5584         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5585         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
5586         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
5587         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
5588         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
5589         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5590         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5591         [EXIT_REASON_GDTR_IDTR]               = handle_desc,
5592         [EXIT_REASON_LDTR_TR]                 = handle_desc,
5593         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5594         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5595         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5596         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
5597         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
5598         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
5599         [EXIT_REASON_INVEPT]                  = handle_vmx_instruction,
5600         [EXIT_REASON_INVVPID]                 = handle_vmx_instruction,
5601         [EXIT_REASON_RDRAND]                  = handle_invalid_op,
5602         [EXIT_REASON_RDSEED]                  = handle_invalid_op,
5603         [EXIT_REASON_PML_FULL]                = handle_pml_full,
5604         [EXIT_REASON_INVPCID]                 = handle_invpcid,
5605         [EXIT_REASON_VMFUNC]                  = handle_vmx_instruction,
5606         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
5607         [EXIT_REASON_ENCLS]                   = handle_encls,
5608 };
5609
5610 static const int kvm_vmx_max_exit_handlers =
5611         ARRAY_SIZE(kvm_vmx_exit_handlers);
5612
5613 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5614 {
5615         *info1 = vmcs_readl(EXIT_QUALIFICATION);
5616         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5617 }
5618
5619 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
5620 {
5621         if (vmx->pml_pg) {
5622                 __free_page(vmx->pml_pg);
5623                 vmx->pml_pg = NULL;
5624         }
5625 }
5626
5627 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
5628 {
5629         struct vcpu_vmx *vmx = to_vmx(vcpu);
5630         u64 *pml_buf;
5631         u16 pml_idx;
5632
5633         pml_idx = vmcs_read16(GUEST_PML_INDEX);
5634
5635         /* Do nothing if PML buffer is empty */
5636         if (pml_idx == (PML_ENTITY_NUM - 1))
5637                 return;
5638
5639         /* PML index always points to next available PML buffer entity */
5640         if (pml_idx >= PML_ENTITY_NUM)
5641                 pml_idx = 0;
5642         else
5643                 pml_idx++;
5644
5645         pml_buf = page_address(vmx->pml_pg);
5646         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5647                 u64 gpa;
5648
5649                 gpa = pml_buf[pml_idx];
5650                 WARN_ON(gpa & (PAGE_SIZE - 1));
5651                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5652         }
5653
5654         /* reset PML index */
5655         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5656 }
5657
5658 /*
5659  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
5660  * Called before reporting dirty_bitmap to userspace.
5661  */
5662 static void kvm_flush_pml_buffers(struct kvm *kvm)
5663 {
5664         int i;
5665         struct kvm_vcpu *vcpu;
5666         /*
5667          * We only need to kick vcpu out of guest mode here, as PML buffer
5668          * is flushed at beginning of all VMEXITs, and it's obvious that only
5669          * vcpus running in guest are possible to have unflushed GPAs in PML
5670          * buffer.
5671          */
5672         kvm_for_each_vcpu(i, vcpu, kvm)
5673                 kvm_vcpu_kick(vcpu);
5674 }
5675
5676 static void vmx_dump_sel(char *name, uint32_t sel)
5677 {
5678         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5679                name, vmcs_read16(sel),
5680                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5681                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5682                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
5683 }
5684
5685 static void vmx_dump_dtsel(char *name, uint32_t limit)
5686 {
5687         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
5688                name, vmcs_read32(limit),
5689                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
5690 }
5691
5692 void dump_vmcs(void)
5693 {
5694         u32 vmentry_ctl, vmexit_ctl;
5695         u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5696         unsigned long cr4;
5697         u64 efer;
5698         int i, n;
5699
5700         if (!dump_invalid_vmcs) {
5701                 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5702                 return;
5703         }
5704
5705         vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5706         vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5707         cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5708         pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5709         cr4 = vmcs_readl(GUEST_CR4);
5710         efer = vmcs_read64(GUEST_IA32_EFER);
5711         secondary_exec_control = 0;
5712         if (cpu_has_secondary_exec_ctrls())
5713                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5714
5715         pr_err("*** Guest State ***\n");
5716         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5717                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5718                vmcs_readl(CR0_GUEST_HOST_MASK));
5719         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5720                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5721         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5722         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
5723             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
5724         {
5725                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
5726                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5727                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
5728                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
5729         }
5730         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
5731                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5732         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
5733                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5734         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5735                vmcs_readl(GUEST_SYSENTER_ESP),
5736                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5737         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
5738         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
5739         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
5740         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
5741         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
5742         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
5743         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5744         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5745         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5746         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
5747         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
5748             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
5749                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
5750                        efer, vmcs_read64(GUEST_IA32_PAT));
5751         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
5752                vmcs_read64(GUEST_IA32_DEBUGCTL),
5753                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5754         if (cpu_has_load_perf_global_ctrl() &&
5755             vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5756                 pr_err("PerfGlobCtl = 0x%016llx\n",
5757                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5758         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5759                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5760         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
5761                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5762                vmcs_read32(GUEST_ACTIVITY_STATE));
5763         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5764                 pr_err("InterruptStatus = %04x\n",
5765                        vmcs_read16(GUEST_INTR_STATUS));
5766
5767         pr_err("*** Host State ***\n");
5768         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
5769                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5770         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5771                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5772                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5773                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5774                vmcs_read16(HOST_TR_SELECTOR));
5775         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5776                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5777                vmcs_readl(HOST_TR_BASE));
5778         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5779                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5780         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5781                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5782                vmcs_readl(HOST_CR4));
5783         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5784                vmcs_readl(HOST_IA32_SYSENTER_ESP),
5785                vmcs_read32(HOST_IA32_SYSENTER_CS),
5786                vmcs_readl(HOST_IA32_SYSENTER_EIP));
5787         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
5788                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
5789                        vmcs_read64(HOST_IA32_EFER),
5790                        vmcs_read64(HOST_IA32_PAT));
5791         if (cpu_has_load_perf_global_ctrl() &&
5792             vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5793                 pr_err("PerfGlobCtl = 0x%016llx\n",
5794                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
5795
5796         pr_err("*** Control State ***\n");
5797         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5798                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5799         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5800         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5801                vmcs_read32(EXCEPTION_BITMAP),
5802                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5803                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5804         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5805                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5806                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5807                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5808         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5809                vmcs_read32(VM_EXIT_INTR_INFO),
5810                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5811                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5812         pr_err("        reason=%08x qualification=%016lx\n",
5813                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5814         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5815                vmcs_read32(IDT_VECTORING_INFO_FIELD),
5816                vmcs_read32(IDT_VECTORING_ERROR_CODE));
5817         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5818         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5819                 pr_err("TSC Multiplier = 0x%016llx\n",
5820                        vmcs_read64(TSC_MULTIPLIER));
5821         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5822                 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5823                         u16 status = vmcs_read16(GUEST_INTR_STATUS);
5824                         pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5825                 }
5826                 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
5827                 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5828                         pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
5829                 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
5830         }
5831         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5832                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5833         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5834                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5835         n = vmcs_read32(CR3_TARGET_COUNT);
5836         for (i = 0; i + 1 < n; i += 4)
5837                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
5838                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
5839                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
5840         if (i < n)
5841                 pr_err("CR3 target%u=%016lx\n",
5842                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
5843         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5844                 pr_err("PLE Gap=%08x Window=%08x\n",
5845                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5846         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5847                 pr_err("Virtual processor ID = 0x%04x\n",
5848                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
5849 }
5850
5851 /*
5852  * The guest has exited.  See if we can fix it or if we need userspace
5853  * assistance.
5854  */
5855 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5856 {
5857         struct vcpu_vmx *vmx = to_vmx(vcpu);
5858         u32 exit_reason = vmx->exit_reason;
5859         u32 vectoring_info = vmx->idt_vectoring_info;
5860
5861         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
5862
5863         /*
5864          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5865          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5866          * querying dirty_bitmap, we only need to kick all vcpus out of guest
5867          * mode as if vcpus is in root mode, the PML buffer must has been
5868          * flushed already.
5869          */
5870         if (enable_pml)
5871                 vmx_flush_pml_buffer(vcpu);
5872
5873         /* If guest state is invalid, start emulating */
5874         if (vmx->emulation_required)
5875                 return handle_invalid_guest_state(vcpu);
5876
5877         if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
5878                 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
5879
5880         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5881                 dump_vmcs();
5882                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5883                 vcpu->run->fail_entry.hardware_entry_failure_reason
5884                         = exit_reason;
5885                 return 0;
5886         }
5887
5888         if (unlikely(vmx->fail)) {
5889                 dump_vmcs();
5890                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5891                 vcpu->run->fail_entry.hardware_entry_failure_reason
5892                         = vmcs_read32(VM_INSTRUCTION_ERROR);
5893                 return 0;
5894         }
5895
5896         /*
5897          * Note:
5898          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5899          * delivery event since it indicates guest is accessing MMIO.
5900          * The vm-exit can be triggered again after return to guest that
5901          * will cause infinite loop.
5902          */
5903         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5904                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5905                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
5906                         exit_reason != EXIT_REASON_PML_FULL &&
5907                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
5908                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5909                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5910                 vcpu->run->internal.ndata = 3;
5911                 vcpu->run->internal.data[0] = vectoring_info;
5912                 vcpu->run->internal.data[1] = exit_reason;
5913                 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5914                 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
5915                         vcpu->run->internal.ndata++;
5916                         vcpu->run->internal.data[3] =
5917                                 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5918                 }
5919                 return 0;
5920         }
5921
5922         if (unlikely(!enable_vnmi &&
5923                      vmx->loaded_vmcs->soft_vnmi_blocked)) {
5924                 if (vmx_interrupt_allowed(vcpu)) {
5925                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5926                 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5927                            vcpu->arch.nmi_pending) {
5928                         /*
5929                          * This CPU don't support us in finding the end of an
5930                          * NMI-blocked window if the guest runs with IRQs
5931                          * disabled. So we pull the trigger after 1 s of
5932                          * futile waiting, but inform the user about this.
5933                          */
5934                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5935                                "state on VCPU %d after 1 s timeout\n",
5936                                __func__, vcpu->vcpu_id);
5937                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5938                 }
5939         }
5940
5941         if (exit_reason < kvm_vmx_max_exit_handlers
5942             && kvm_vmx_exit_handlers[exit_reason])
5943                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5944         else {
5945                 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
5946                                 exit_reason);
5947                 dump_vmcs();
5948                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5949                 vcpu->run->internal.suberror =
5950                         KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
5951                 vcpu->run->internal.ndata = 1;
5952                 vcpu->run->internal.data[0] = exit_reason;
5953                 return 0;
5954         }
5955 }
5956
5957 /*
5958  * Software based L1D cache flush which is used when microcode providing
5959  * the cache control MSR is not loaded.
5960  *
5961  * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
5962  * flush it is required to read in 64 KiB because the replacement algorithm
5963  * is not exactly LRU. This could be sized at runtime via topology
5964  * information but as all relevant affected CPUs have 32KiB L1D cache size
5965  * there is no point in doing so.
5966  */
5967 static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
5968 {
5969         int size = PAGE_SIZE << L1D_CACHE_ORDER;
5970
5971         /*
5972          * This code is only executed when the the flush mode is 'cond' or
5973          * 'always'
5974          */
5975         if (static_branch_likely(&vmx_l1d_flush_cond)) {
5976                 bool flush_l1d;
5977
5978                 /*
5979                  * Clear the per-vcpu flush bit, it gets set again
5980                  * either from vcpu_run() or from one of the unsafe
5981                  * VMEXIT handlers.
5982                  */
5983                 flush_l1d = vcpu->arch.l1tf_flush_l1d;
5984                 vcpu->arch.l1tf_flush_l1d = false;
5985
5986                 /*
5987                  * Clear the per-cpu flush bit, it gets set again from
5988                  * the interrupt handlers.
5989                  */
5990                 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
5991                 kvm_clear_cpu_l1tf_flush_l1d();
5992
5993                 if (!flush_l1d)
5994                         return;
5995         }
5996
5997         vcpu->stat.l1d_flush++;
5998
5999         if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
6000                 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
6001                 return;
6002         }
6003
6004         asm volatile(
6005                 /* First ensure the pages are in the TLB */
6006                 "xorl   %%eax, %%eax\n"
6007                 ".Lpopulate_tlb:\n\t"
6008                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6009                 "addl   $4096, %%eax\n\t"
6010                 "cmpl   %%eax, %[size]\n\t"
6011                 "jne    .Lpopulate_tlb\n\t"
6012                 "xorl   %%eax, %%eax\n\t"
6013                 "cpuid\n\t"
6014                 /* Now fill the cache */
6015                 "xorl   %%eax, %%eax\n"
6016                 ".Lfill_cache:\n"
6017                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6018                 "addl   $64, %%eax\n\t"
6019                 "cmpl   %%eax, %[size]\n\t"
6020                 "jne    .Lfill_cache\n\t"
6021                 "lfence\n"
6022                 :: [flush_pages] "r" (vmx_l1d_flush_pages),
6023                     [size] "r" (size)
6024                 : "eax", "ebx", "ecx", "edx");
6025 }
6026
6027 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6028 {
6029         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6030
6031         if (is_guest_mode(vcpu) &&
6032                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
6033                 return;
6034
6035         if (irr == -1 || tpr < irr) {
6036                 vmcs_write32(TPR_THRESHOLD, 0);
6037                 return;
6038         }
6039
6040         vmcs_write32(TPR_THRESHOLD, irr);
6041 }
6042
6043 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
6044 {
6045         struct vcpu_vmx *vmx = to_vmx(vcpu);
6046         u32 sec_exec_control;
6047
6048         if (!lapic_in_kernel(vcpu))
6049                 return;
6050
6051         if (!flexpriority_enabled &&
6052             !cpu_has_vmx_virtualize_x2apic_mode())
6053                 return;
6054
6055         /* Postpone execution until vmcs01 is the current VMCS. */
6056         if (is_guest_mode(vcpu)) {
6057                 vmx->nested.change_vmcs01_virtual_apic_mode = true;
6058                 return;
6059         }
6060
6061         sec_exec_control = secondary_exec_controls_get(vmx);
6062         sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6063                               SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
6064
6065         switch (kvm_get_apic_mode(vcpu)) {
6066         case LAPIC_MODE_INVALID:
6067                 WARN_ONCE(true, "Invalid local APIC state");
6068         case LAPIC_MODE_DISABLED:
6069                 break;
6070         case LAPIC_MODE_XAPIC:
6071                 if (flexpriority_enabled) {
6072                         sec_exec_control |=
6073                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6074                         vmx_flush_tlb(vcpu, true);
6075                 }
6076                 break;
6077         case LAPIC_MODE_X2APIC:
6078                 if (cpu_has_vmx_virtualize_x2apic_mode())
6079                         sec_exec_control |=
6080                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6081                 break;
6082         }
6083         secondary_exec_controls_set(vmx, sec_exec_control);
6084
6085         vmx_update_msr_bitmap(vcpu);
6086 }
6087
6088 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
6089 {
6090         if (!is_guest_mode(vcpu)) {
6091                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
6092                 vmx_flush_tlb(vcpu, true);
6093         }
6094 }
6095
6096 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6097 {
6098         u16 status;
6099         u8 old;
6100
6101         if (max_isr == -1)
6102                 max_isr = 0;
6103
6104         status = vmcs_read16(GUEST_INTR_STATUS);
6105         old = status >> 8;
6106         if (max_isr != old) {
6107                 status &= 0xff;
6108                 status |= max_isr << 8;
6109                 vmcs_write16(GUEST_INTR_STATUS, status);
6110         }
6111 }
6112
6113 static void vmx_set_rvi(int vector)
6114 {
6115         u16 status;
6116         u8 old;
6117
6118         if (vector == -1)
6119                 vector = 0;
6120
6121         status = vmcs_read16(GUEST_INTR_STATUS);
6122         old = (u8)status & 0xff;
6123         if ((u8)vector != old) {
6124                 status &= ~0xff;
6125                 status |= (u8)vector;
6126                 vmcs_write16(GUEST_INTR_STATUS, status);
6127         }
6128 }
6129
6130 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6131 {
6132         /*
6133          * When running L2, updating RVI is only relevant when
6134          * vmcs12 virtual-interrupt-delivery enabled.
6135          * However, it can be enabled only when L1 also
6136          * intercepts external-interrupts and in that case
6137          * we should not update vmcs02 RVI but instead intercept
6138          * interrupt. Therefore, do nothing when running L2.
6139          */
6140         if (!is_guest_mode(vcpu))
6141                 vmx_set_rvi(max_irr);
6142 }
6143
6144 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6145 {
6146         struct vcpu_vmx *vmx = to_vmx(vcpu);
6147         int max_irr;
6148         bool max_irr_updated;
6149
6150         WARN_ON(!vcpu->arch.apicv_active);
6151         if (pi_test_on(&vmx->pi_desc)) {
6152                 pi_clear_on(&vmx->pi_desc);
6153                 /*
6154                  * IOMMU can write to PID.ON, so the barrier matters even on UP.
6155                  * But on x86 this is just a compiler barrier anyway.
6156                  */
6157                 smp_mb__after_atomic();
6158                 max_irr_updated =
6159                         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
6160
6161                 /*
6162                  * If we are running L2 and L1 has a new pending interrupt
6163                  * which can be injected, we should re-evaluate
6164                  * what should be done with this new L1 interrupt.
6165                  * If L1 intercepts external-interrupts, we should
6166                  * exit from L2 to L1. Otherwise, interrupt should be
6167                  * delivered directly to L2.
6168                  */
6169                 if (is_guest_mode(vcpu) && max_irr_updated) {
6170                         if (nested_exit_on_intr(vcpu))
6171                                 kvm_vcpu_exiting_guest_mode(vcpu);
6172                         else
6173                                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6174                 }
6175         } else {
6176                 max_irr = kvm_lapic_find_highest_irr(vcpu);
6177         }
6178         vmx_hwapic_irr_update(vcpu, max_irr);
6179         return max_irr;
6180 }
6181
6182 static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
6183 {
6184         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6185
6186         return pi_test_on(pi_desc) ||
6187                 (pi_test_sn(pi_desc) && !pi_is_pir_empty(pi_desc));
6188 }
6189
6190 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6191 {
6192         if (!kvm_vcpu_apicv_active(vcpu))
6193                 return;
6194
6195         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6196         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6197         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6198         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6199 }
6200
6201 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
6202 {
6203         struct vcpu_vmx *vmx = to_vmx(vcpu);
6204
6205         pi_clear_on(&vmx->pi_desc);
6206         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6207 }
6208
6209 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
6210 {
6211         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6212
6213         /* if exit due to PF check for async PF */
6214         if (is_page_fault(vmx->exit_intr_info))
6215                 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
6216
6217         /* Handle machine checks before interrupts are enabled */
6218         if (is_machine_check(vmx->exit_intr_info))
6219                 kvm_machine_check();
6220
6221         /* We need to handle NMIs before interrupts are enabled */
6222         if (is_nmi(vmx->exit_intr_info)) {
6223                 kvm_before_interrupt(&vmx->vcpu);
6224                 asm("int $2");
6225                 kvm_after_interrupt(&vmx->vcpu);
6226         }
6227 }
6228
6229 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
6230 {
6231         unsigned int vector;
6232         unsigned long entry;
6233 #ifdef CONFIG_X86_64
6234         unsigned long tmp;
6235 #endif
6236         gate_desc *desc;
6237         u32 intr_info;
6238
6239         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6240         if (WARN_ONCE(!is_external_intr(intr_info),
6241             "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6242                 return;
6243
6244         vector = intr_info & INTR_INFO_VECTOR_MASK;
6245         desc = (gate_desc *)host_idt_base + vector;
6246         entry = gate_offset(desc);
6247
6248         kvm_before_interrupt(vcpu);
6249
6250         asm volatile(
6251 #ifdef CONFIG_X86_64
6252                 "mov %%" _ASM_SP ", %[sp]\n\t"
6253                 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6254                 "push $%c[ss]\n\t"
6255                 "push %[sp]\n\t"
6256 #endif
6257                 "pushf\n\t"
6258                 __ASM_SIZE(push) " $%c[cs]\n\t"
6259                 CALL_NOSPEC
6260                 :
6261 #ifdef CONFIG_X86_64
6262                 [sp]"=&r"(tmp),
6263 #endif
6264                 ASM_CALL_CONSTRAINT
6265                 :
6266                 THUNK_TARGET(entry),
6267                 [ss]"i"(__KERNEL_DS),
6268                 [cs]"i"(__KERNEL_CS)
6269         );
6270
6271         kvm_after_interrupt(vcpu);
6272 }
6273 STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff);
6274
6275 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu)
6276 {
6277         struct vcpu_vmx *vmx = to_vmx(vcpu);
6278
6279         if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
6280                 handle_external_interrupt_irqoff(vcpu);
6281         else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)
6282                 handle_exception_nmi_irqoff(vmx);
6283 }
6284
6285 static bool vmx_has_emulated_msr(int index)
6286 {
6287         switch (index) {
6288         case MSR_IA32_SMBASE:
6289                 /*
6290                  * We cannot do SMM unless we can run the guest in big
6291                  * real mode.
6292                  */
6293                 return enable_unrestricted_guest || emulate_invalid_guest_state;
6294         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6295                 return nested;
6296         case MSR_AMD64_VIRT_SPEC_CTRL:
6297                 /* This is AMD only.  */
6298                 return false;
6299         default:
6300                 return true;
6301         }
6302 }
6303
6304 static bool vmx_pt_supported(void)
6305 {
6306         return pt_mode == PT_MODE_HOST_GUEST;
6307 }
6308
6309 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6310 {
6311         u32 exit_intr_info;
6312         bool unblock_nmi;
6313         u8 vector;
6314         bool idtv_info_valid;
6315
6316         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6317
6318         if (enable_vnmi) {
6319                 if (vmx->loaded_vmcs->nmi_known_unmasked)
6320                         return;
6321                 /*
6322                  * Can't use vmx->exit_intr_info since we're not sure what
6323                  * the exit reason is.
6324                  */
6325                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6326                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6327                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6328                 /*
6329                  * SDM 3: 27.7.1.2 (September 2008)
6330                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6331                  * a guest IRET fault.
6332                  * SDM 3: 23.2.2 (September 2008)
6333                  * Bit 12 is undefined in any of the following cases:
6334                  *  If the VM exit sets the valid bit in the IDT-vectoring
6335                  *   information field.
6336                  *  If the VM exit is due to a double fault.
6337                  */
6338                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6339                     vector != DF_VECTOR && !idtv_info_valid)
6340                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6341                                       GUEST_INTR_STATE_NMI);
6342                 else
6343                         vmx->loaded_vmcs->nmi_known_unmasked =
6344                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6345                                   & GUEST_INTR_STATE_NMI);
6346         } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6347                 vmx->loaded_vmcs->vnmi_blocked_time +=
6348                         ktime_to_ns(ktime_sub(ktime_get(),
6349                                               vmx->loaded_vmcs->entry_time));
6350 }
6351
6352 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6353                                       u32 idt_vectoring_info,
6354                                       int instr_len_field,
6355                                       int error_code_field)
6356 {
6357         u8 vector;
6358         int type;
6359         bool idtv_info_valid;
6360
6361         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6362
6363         vcpu->arch.nmi_injected = false;
6364         kvm_clear_exception_queue(vcpu);
6365         kvm_clear_interrupt_queue(vcpu);
6366
6367         if (!idtv_info_valid)
6368                 return;
6369
6370         kvm_make_request(KVM_REQ_EVENT, vcpu);
6371
6372         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6373         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6374
6375         switch (type) {
6376         case INTR_TYPE_NMI_INTR:
6377                 vcpu->arch.nmi_injected = true;
6378                 /*
6379                  * SDM 3: 27.7.1.2 (September 2008)
6380                  * Clear bit "block by NMI" before VM entry if a NMI
6381                  * delivery faulted.
6382                  */
6383                 vmx_set_nmi_mask(vcpu, false);
6384                 break;
6385         case INTR_TYPE_SOFT_EXCEPTION:
6386                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6387                 /* fall through */
6388         case INTR_TYPE_HARD_EXCEPTION:
6389                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6390                         u32 err = vmcs_read32(error_code_field);
6391                         kvm_requeue_exception_e(vcpu, vector, err);
6392                 } else
6393                         kvm_requeue_exception(vcpu, vector);
6394                 break;
6395         case INTR_TYPE_SOFT_INTR:
6396                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6397                 /* fall through */
6398         case INTR_TYPE_EXT_INTR:
6399                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6400                 break;
6401         default:
6402                 break;
6403         }
6404 }
6405
6406 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6407 {
6408         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6409                                   VM_EXIT_INSTRUCTION_LEN,
6410                                   IDT_VECTORING_ERROR_CODE);
6411 }
6412
6413 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6414 {
6415         __vmx_complete_interrupts(vcpu,
6416                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6417                                   VM_ENTRY_INSTRUCTION_LEN,
6418                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6419
6420         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6421 }
6422
6423 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6424 {
6425         int i, nr_msrs;
6426         struct perf_guest_switch_msr *msrs;
6427
6428         msrs = perf_guest_get_msrs(&nr_msrs);
6429
6430         if (!msrs)
6431                 return;
6432
6433         for (i = 0; i < nr_msrs; i++)
6434                 if (msrs[i].host == msrs[i].guest)
6435                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6436                 else
6437                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6438                                         msrs[i].host, false);
6439 }
6440
6441 static void atomic_switch_umwait_control_msr(struct vcpu_vmx *vmx)
6442 {
6443         u32 host_umwait_control;
6444
6445         if (!vmx_has_waitpkg(vmx))
6446                 return;
6447
6448         host_umwait_control = get_umwait_control_msr();
6449
6450         if (vmx->msr_ia32_umwait_control != host_umwait_control)
6451                 add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL,
6452                         vmx->msr_ia32_umwait_control,
6453                         host_umwait_control, false);
6454         else
6455                 clear_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL);
6456 }
6457
6458 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
6459 {
6460         struct vcpu_vmx *vmx = to_vmx(vcpu);
6461         u64 tscl;
6462         u32 delta_tsc;
6463
6464         if (vmx->req_immediate_exit) {
6465                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6466                 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6467         } else if (vmx->hv_deadline_tsc != -1) {
6468                 tscl = rdtsc();
6469                 if (vmx->hv_deadline_tsc > tscl)
6470                         /* set_hv_timer ensures the delta fits in 32-bits */
6471                         delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6472                                 cpu_preemption_timer_multi);
6473                 else
6474                         delta_tsc = 0;
6475
6476                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6477                 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6478         } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6479                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6480                 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
6481         }
6482 }
6483
6484 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
6485 {
6486         if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6487                 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6488                 vmcs_writel(HOST_RSP, host_rsp);
6489         }
6490 }
6491
6492 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched);
6493
6494 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6495 {
6496         struct vcpu_vmx *vmx = to_vmx(vcpu);
6497         unsigned long cr3, cr4;
6498
6499         /* Record the guest's net vcpu time for enforced NMI injections. */
6500         if (unlikely(!enable_vnmi &&
6501                      vmx->loaded_vmcs->soft_vnmi_blocked))
6502                 vmx->loaded_vmcs->entry_time = ktime_get();
6503
6504         /* Don't enter VMX if guest state is invalid, let the exit handler
6505            start emulation until we arrive back to a valid state */
6506         if (vmx->emulation_required)
6507                 return;
6508
6509         if (vmx->ple_window_dirty) {
6510                 vmx->ple_window_dirty = false;
6511                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6512         }
6513
6514         if (vmx->nested.need_vmcs12_to_shadow_sync)
6515                 nested_sync_vmcs12_to_shadow(vcpu);
6516
6517         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6518                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6519         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6520                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6521
6522         cr3 = __get_current_cr3_fast();
6523         if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6524                 vmcs_writel(HOST_CR3, cr3);
6525                 vmx->loaded_vmcs->host_state.cr3 = cr3;
6526         }
6527
6528         cr4 = cr4_read_shadow();
6529         if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6530                 vmcs_writel(HOST_CR4, cr4);
6531                 vmx->loaded_vmcs->host_state.cr4 = cr4;
6532         }
6533
6534         /* When single-stepping over STI and MOV SS, we must clear the
6535          * corresponding interruptibility bits in the guest state. Otherwise
6536          * vmentry fails as it then expects bit 14 (BS) in pending debug
6537          * exceptions being set, but that's not correct for the guest debugging
6538          * case. */
6539         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6540                 vmx_set_interrupt_shadow(vcpu, 0);
6541
6542         kvm_load_guest_xcr0(vcpu);
6543
6544         if (static_cpu_has(X86_FEATURE_PKU) &&
6545             kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
6546             vcpu->arch.pkru != vmx->host_pkru)
6547                 __write_pkru(vcpu->arch.pkru);
6548
6549         pt_guest_enter(vmx);
6550
6551         atomic_switch_perf_msrs(vmx);
6552         atomic_switch_umwait_control_msr(vmx);
6553
6554         if (enable_preemption_timer)
6555                 vmx_update_hv_timer(vcpu);
6556
6557         if (lapic_in_kernel(vcpu) &&
6558                 vcpu->arch.apic->lapic_timer.timer_advance_ns)
6559                 kvm_wait_lapic_expire(vcpu);
6560
6561         /*
6562          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6563          * it's non-zero. Since vmentry is serialising on affected CPUs, there
6564          * is no need to worry about the conditional branch over the wrmsr
6565          * being speculatively taken.
6566          */
6567         x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6568
6569         /* L1D Flush includes CPU buffer clear to mitigate MDS */
6570         if (static_branch_unlikely(&vmx_l1d_should_flush))
6571                 vmx_l1d_flush(vcpu);
6572         else if (static_branch_unlikely(&mds_user_clear))
6573                 mds_clear_cpu_buffers();
6574
6575         if (vcpu->arch.cr2 != read_cr2())
6576                 write_cr2(vcpu->arch.cr2);
6577
6578         vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6579                                    vmx->loaded_vmcs->launched);
6580
6581         vcpu->arch.cr2 = read_cr2();
6582
6583         /*
6584          * We do not use IBRS in the kernel. If this vCPU has used the
6585          * SPEC_CTRL MSR it may have left it on; save the value and
6586          * turn it off. This is much more efficient than blindly adding
6587          * it to the atomic save/restore list. Especially as the former
6588          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6589          *
6590          * For non-nested case:
6591          * If the L01 MSR bitmap does not intercept the MSR, then we need to
6592          * save it.
6593          *
6594          * For nested case:
6595          * If the L02 MSR bitmap does not intercept the MSR, then we need to
6596          * save it.
6597          */
6598         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6599                 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
6600
6601         x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
6602
6603         /* All fields are clean at this point */
6604         if (static_branch_unlikely(&enable_evmcs))
6605                 current_evmcs->hv_clean_fields |=
6606                         HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
6607
6608         if (static_branch_unlikely(&enable_evmcs))
6609                 current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index;
6610
6611         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6612         if (vmx->host_debugctlmsr)
6613                 update_debugctlmsr(vmx->host_debugctlmsr);
6614
6615 #ifndef CONFIG_X86_64
6616         /*
6617          * The sysexit path does not restore ds/es, so we must set them to
6618          * a reasonable value ourselves.
6619          *
6620          * We can't defer this to vmx_prepare_switch_to_host() since that
6621          * function may be executed in interrupt context, which saves and
6622          * restore segments around it, nullifying its effect.
6623          */
6624         loadsegment(ds, __USER_DS);
6625         loadsegment(es, __USER_DS);
6626 #endif
6627
6628         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6629                                   | (1 << VCPU_EXREG_RFLAGS)
6630                                   | (1 << VCPU_EXREG_PDPTR)
6631                                   | (1 << VCPU_EXREG_SEGMENTS)
6632                                   | (1 << VCPU_EXREG_CR3));
6633         vcpu->arch.regs_dirty = 0;
6634
6635         pt_guest_exit(vmx);
6636
6637         /*
6638          * eager fpu is enabled if PKEY is supported and CR4 is switched
6639          * back on host, so it is safe to read guest PKRU from current
6640          * XSAVE.
6641          */
6642         if (static_cpu_has(X86_FEATURE_PKU) &&
6643             kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
6644                 vcpu->arch.pkru = rdpkru();
6645                 if (vcpu->arch.pkru != vmx->host_pkru)
6646                         __write_pkru(vmx->host_pkru);
6647         }
6648
6649         kvm_put_guest_xcr0(vcpu);
6650
6651         vmx->nested.nested_run_pending = 0;
6652         vmx->idt_vectoring_info = 0;
6653
6654         vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
6655         if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
6656                 kvm_machine_check();
6657
6658         if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6659                 return;
6660
6661         vmx->loaded_vmcs->launched = 1;
6662         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6663
6664         vmx_recover_nmi_blocking(vmx);
6665         vmx_complete_interrupts(vmx);
6666 }
6667
6668 static struct kvm *vmx_vm_alloc(void)
6669 {
6670         struct kvm_vmx *kvm_vmx = __vmalloc(sizeof(struct kvm_vmx),
6671                                             GFP_KERNEL_ACCOUNT | __GFP_ZERO,
6672                                             PAGE_KERNEL);
6673         return &kvm_vmx->kvm;
6674 }
6675
6676 static void vmx_vm_free(struct kvm *kvm)
6677 {
6678         kfree(kvm->arch.hyperv.hv_pa_pg);
6679         vfree(to_kvm_vmx(kvm));
6680 }
6681
6682 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6683 {
6684         struct vcpu_vmx *vmx = to_vmx(vcpu);
6685
6686         if (enable_pml)
6687                 vmx_destroy_pml_buffer(vmx);
6688         free_vpid(vmx->vpid);
6689         nested_vmx_free_vcpu(vcpu);
6690         free_loaded_vmcs(vmx->loaded_vmcs);
6691         kfree(vmx->guest_msrs);
6692         kvm_vcpu_uninit(vcpu);
6693         kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu);
6694         kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
6695         kmem_cache_free(kvm_vcpu_cache, vmx);
6696 }
6697
6698 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6699 {
6700         int err;
6701         struct vcpu_vmx *vmx;
6702         unsigned long *msr_bitmap;
6703         int cpu;
6704
6705         BUILD_BUG_ON_MSG(offsetof(struct vcpu_vmx, vcpu) != 0,
6706                 "struct kvm_vcpu must be at offset 0 for arch usercopy region");
6707
6708         vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL_ACCOUNT);
6709         if (!vmx)
6710                 return ERR_PTR(-ENOMEM);
6711
6712         vmx->vcpu.arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
6713                         GFP_KERNEL_ACCOUNT);
6714         if (!vmx->vcpu.arch.user_fpu) {
6715                 printk(KERN_ERR "kvm: failed to allocate kvm userspace's fpu\n");
6716                 err = -ENOMEM;
6717                 goto free_partial_vcpu;
6718         }
6719
6720         vmx->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
6721                         GFP_KERNEL_ACCOUNT);
6722         if (!vmx->vcpu.arch.guest_fpu) {
6723                 printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n");
6724                 err = -ENOMEM;
6725                 goto free_user_fpu;
6726         }
6727
6728         vmx->vpid = allocate_vpid();
6729
6730         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6731         if (err)
6732                 goto free_vcpu;
6733
6734         err = -ENOMEM;
6735
6736         /*
6737          * If PML is turned on, failure on enabling PML just results in failure
6738          * of creating the vcpu, therefore we can simplify PML logic (by
6739          * avoiding dealing with cases, such as enabling PML partially on vcpus
6740          * for the guest, etc.
6741          */
6742         if (enable_pml) {
6743                 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
6744                 if (!vmx->pml_pg)
6745                         goto uninit_vcpu;
6746         }
6747
6748         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL_ACCOUNT);
6749         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
6750                      > PAGE_SIZE);
6751
6752         if (!vmx->guest_msrs)
6753                 goto free_pml;
6754
6755         err = alloc_loaded_vmcs(&vmx->vmcs01);
6756         if (err < 0)
6757                 goto free_msrs;
6758
6759         msr_bitmap = vmx->vmcs01.msr_bitmap;
6760         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
6761         vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
6762         vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
6763         vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6764         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6765         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6766         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
6767         if (kvm_cstate_in_guest(kvm)) {
6768                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R);
6769                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6770                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6771                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6772         }
6773         vmx->msr_bitmap_mode = 0;
6774
6775         vmx->loaded_vmcs = &vmx->vmcs01;
6776         cpu = get_cpu();
6777         vmx_vcpu_load(&vmx->vcpu, cpu);
6778         vmx->vcpu.cpu = cpu;
6779         vmx_vcpu_setup(vmx);
6780         vmx_vcpu_put(&vmx->vcpu);
6781         put_cpu();
6782         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
6783                 err = alloc_apic_access_page(kvm);
6784                 if (err)
6785                         goto free_vmcs;
6786         }
6787
6788         if (enable_ept && !enable_unrestricted_guest) {
6789                 err = init_rmode_identity_map(kvm);
6790                 if (err)
6791                         goto free_vmcs;
6792         }
6793
6794         if (nested)
6795                 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
6796                                            vmx_capability.ept,
6797                                            kvm_vcpu_apicv_active(&vmx->vcpu));
6798         else
6799                 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
6800
6801         vmx->nested.posted_intr_nv = -1;
6802         vmx->nested.current_vmptr = -1ull;
6803
6804         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
6805
6806         /*
6807          * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
6808          * or POSTED_INTR_WAKEUP_VECTOR.
6809          */
6810         vmx->pi_desc.nv = POSTED_INTR_VECTOR;
6811         vmx->pi_desc.sn = 1;
6812
6813         vmx->ept_pointer = INVALID_PAGE;
6814
6815         return &vmx->vcpu;
6816
6817 free_vmcs:
6818         free_loaded_vmcs(vmx->loaded_vmcs);
6819 free_msrs:
6820         kfree(vmx->guest_msrs);
6821 free_pml:
6822         vmx_destroy_pml_buffer(vmx);
6823 uninit_vcpu:
6824         kvm_vcpu_uninit(&vmx->vcpu);
6825 free_vcpu:
6826         free_vpid(vmx->vpid);
6827         kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
6828 free_user_fpu:
6829         kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu);
6830 free_partial_vcpu:
6831         kmem_cache_free(kvm_vcpu_cache, vmx);
6832         return ERR_PTR(err);
6833 }
6834
6835 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6836 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6837
6838 static int vmx_vm_init(struct kvm *kvm)
6839 {
6840         spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
6841
6842         if (!ple_gap)
6843                 kvm->arch.pause_in_guest = true;
6844
6845         if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6846                 switch (l1tf_mitigation) {
6847                 case L1TF_MITIGATION_OFF:
6848                 case L1TF_MITIGATION_FLUSH_NOWARN:
6849                         /* 'I explicitly don't care' is set */
6850                         break;
6851                 case L1TF_MITIGATION_FLUSH:
6852                 case L1TF_MITIGATION_FLUSH_NOSMT:
6853                 case L1TF_MITIGATION_FULL:
6854                         /*
6855                          * Warn upon starting the first VM in a potentially
6856                          * insecure environment.
6857                          */
6858                         if (sched_smt_active())
6859                                 pr_warn_once(L1TF_MSG_SMT);
6860                         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6861                                 pr_warn_once(L1TF_MSG_L1D);
6862                         break;
6863                 case L1TF_MITIGATION_FULL_FORCE:
6864                         /* Flush is enforced */
6865                         break;
6866                 }
6867         }
6868         return 0;
6869 }
6870
6871 static int __init vmx_check_processor_compat(void)
6872 {
6873         struct vmcs_config vmcs_conf;
6874         struct vmx_capability vmx_cap;
6875
6876         if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
6877                 return -EIO;
6878         if (nested)
6879                 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept,
6880                                            enable_apicv);
6881         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6882                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6883                                 smp_processor_id());
6884                 return -EIO;
6885         }
6886         return 0;
6887 }
6888
6889 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6890 {
6891         u8 cache;
6892         u64 ipat = 0;
6893
6894         /* For VT-d and EPT combination
6895          * 1. MMIO: always map as UC
6896          * 2. EPT with VT-d:
6897          *   a. VT-d without snooping control feature: can't guarantee the
6898          *      result, try to trust guest.
6899          *   b. VT-d with snooping control feature: snooping control feature of
6900          *      VT-d engine can guarantee the cache correctness. Just set it
6901          *      to WB to keep consistent with host. So the same as item 3.
6902          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6903          *    consistent with host MTRR
6904          */
6905         if (is_mmio) {
6906                 cache = MTRR_TYPE_UNCACHABLE;
6907                 goto exit;
6908         }
6909
6910         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
6911                 ipat = VMX_EPT_IPAT_BIT;
6912                 cache = MTRR_TYPE_WRBACK;
6913                 goto exit;
6914         }
6915
6916         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
6917                 ipat = VMX_EPT_IPAT_BIT;
6918                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
6919                         cache = MTRR_TYPE_WRBACK;
6920                 else
6921                         cache = MTRR_TYPE_UNCACHABLE;
6922                 goto exit;
6923         }
6924
6925         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
6926
6927 exit:
6928         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
6929 }
6930
6931 static int vmx_get_lpage_level(void)
6932 {
6933         if (enable_ept && !cpu_has_vmx_ept_1g_page())
6934                 return PT_DIRECTORY_LEVEL;
6935         else
6936                 /* For shadow and EPT supported 1GB page */
6937                 return PT_PDPE_LEVEL;
6938 }
6939
6940 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx)
6941 {
6942         /*
6943          * These bits in the secondary execution controls field
6944          * are dynamic, the others are mostly based on the hypervisor
6945          * architecture and the guest's CPUID.  Do not touch the
6946          * dynamic bits.
6947          */
6948         u32 mask =
6949                 SECONDARY_EXEC_SHADOW_VMCS |
6950                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
6951                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6952                 SECONDARY_EXEC_DESC;
6953
6954         u32 new_ctl = vmx->secondary_exec_control;
6955         u32 cur_ctl = secondary_exec_controls_get(vmx);
6956
6957         secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
6958 }
6959
6960 /*
6961  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
6962  * (indicating "allowed-1") if they are supported in the guest's CPUID.
6963  */
6964 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
6965 {
6966         struct vcpu_vmx *vmx = to_vmx(vcpu);
6967         struct kvm_cpuid_entry2 *entry;
6968
6969         vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
6970         vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
6971
6972 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
6973         if (entry && (entry->_reg & (_cpuid_mask)))                     \
6974                 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask);     \
6975 } while (0)
6976
6977         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
6978         cr4_fixed1_update(X86_CR4_VME,        edx, bit(X86_FEATURE_VME));
6979         cr4_fixed1_update(X86_CR4_PVI,        edx, bit(X86_FEATURE_VME));
6980         cr4_fixed1_update(X86_CR4_TSD,        edx, bit(X86_FEATURE_TSC));
6981         cr4_fixed1_update(X86_CR4_DE,         edx, bit(X86_FEATURE_DE));
6982         cr4_fixed1_update(X86_CR4_PSE,        edx, bit(X86_FEATURE_PSE));
6983         cr4_fixed1_update(X86_CR4_PAE,        edx, bit(X86_FEATURE_PAE));
6984         cr4_fixed1_update(X86_CR4_MCE,        edx, bit(X86_FEATURE_MCE));
6985         cr4_fixed1_update(X86_CR4_PGE,        edx, bit(X86_FEATURE_PGE));
6986         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, bit(X86_FEATURE_FXSR));
6987         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
6988         cr4_fixed1_update(X86_CR4_VMXE,       ecx, bit(X86_FEATURE_VMX));
6989         cr4_fixed1_update(X86_CR4_SMXE,       ecx, bit(X86_FEATURE_SMX));
6990         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, bit(X86_FEATURE_PCID));
6991         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, bit(X86_FEATURE_XSAVE));
6992
6993         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6994         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, bit(X86_FEATURE_FSGSBASE));
6995         cr4_fixed1_update(X86_CR4_SMEP,       ebx, bit(X86_FEATURE_SMEP));
6996         cr4_fixed1_update(X86_CR4_SMAP,       ebx, bit(X86_FEATURE_SMAP));
6997         cr4_fixed1_update(X86_CR4_PKE,        ecx, bit(X86_FEATURE_PKU));
6998         cr4_fixed1_update(X86_CR4_UMIP,       ecx, bit(X86_FEATURE_UMIP));
6999
7000 #undef cr4_fixed1_update
7001 }
7002
7003 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
7004 {
7005         struct vcpu_vmx *vmx = to_vmx(vcpu);
7006
7007         if (kvm_mpx_supported()) {
7008                 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
7009
7010                 if (mpx_enabled) {
7011                         vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
7012                         vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
7013                 } else {
7014                         vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
7015                         vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
7016                 }
7017         }
7018 }
7019
7020 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
7021 {
7022         struct vcpu_vmx *vmx = to_vmx(vcpu);
7023         struct kvm_cpuid_entry2 *best = NULL;
7024         int i;
7025
7026         for (i = 0; i < PT_CPUID_LEAVES; i++) {
7027                 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
7028                 if (!best)
7029                         return;
7030                 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
7031                 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
7032                 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
7033                 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
7034         }
7035
7036         /* Get the number of configurable Address Ranges for filtering */
7037         vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
7038                                                 PT_CAP_num_address_ranges);
7039
7040         /* Initialize and clear the no dependency bits */
7041         vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
7042                         RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
7043
7044         /*
7045          * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
7046          * will inject an #GP
7047          */
7048         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
7049                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
7050
7051         /*
7052          * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
7053          * PSBFreq can be set
7054          */
7055         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
7056                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
7057                                 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
7058
7059         /*
7060          * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
7061          * MTCFreq can be set
7062          */
7063         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
7064                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
7065                                 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
7066
7067         /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
7068         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
7069                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
7070                                                         RTIT_CTL_PTW_EN);
7071
7072         /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7073         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
7074                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
7075
7076         /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7077         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
7078                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
7079
7080         /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */
7081         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
7082                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
7083
7084         /* unmask address range configure area */
7085         for (i = 0; i < vmx->pt_desc.addr_range; i++)
7086                 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
7087 }
7088
7089 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7090 {
7091         struct vcpu_vmx *vmx = to_vmx(vcpu);
7092
7093         if (cpu_has_secondary_exec_ctrls()) {
7094                 vmx_compute_secondary_exec_control(vmx);
7095                 vmcs_set_secondary_exec_control(vmx);
7096         }
7097
7098         if (nested_vmx_allowed(vcpu))
7099                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7100                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7101         else
7102                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7103                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7104
7105         if (nested_vmx_allowed(vcpu)) {
7106                 nested_vmx_cr_fixed1_bits_update(vcpu);
7107                 nested_vmx_entry_exit_ctls_update(vcpu);
7108         }
7109
7110         if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7111                         guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7112                 update_intel_pt_cfg(vcpu);
7113 }
7114
7115 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7116 {
7117         if (func == 1 && nested)
7118                 entry->ecx |= bit(X86_FEATURE_VMX);
7119 }
7120
7121 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
7122 {
7123         to_vmx(vcpu)->req_immediate_exit = true;
7124 }
7125
7126 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7127                                struct x86_instruction_info *info,
7128                                enum x86_intercept_stage stage)
7129 {
7130         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7131         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7132
7133         /*
7134          * RDPID causes #UD if disabled through secondary execution controls.
7135          * Because it is marked as EmulateOnUD, we need to intercept it here.
7136          */
7137         if (info->intercept == x86_intercept_rdtscp &&
7138             !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
7139                 ctxt->exception.vector = UD_VECTOR;
7140                 ctxt->exception.error_code_valid = false;
7141                 return X86EMUL_PROPAGATE_FAULT;
7142         }
7143
7144         /* TODO: check more intercepts... */
7145         return X86EMUL_CONTINUE;
7146 }
7147
7148 #ifdef CONFIG_X86_64
7149 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7150 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7151                                   u64 divisor, u64 *result)
7152 {
7153         u64 low = a << shift, high = a >> (64 - shift);
7154
7155         /* To avoid the overflow on divq */
7156         if (high >= divisor)
7157                 return 1;
7158
7159         /* Low hold the result, high hold rem which is discarded */
7160         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7161             "rm" (divisor), "0" (low), "1" (high));
7162         *result = low;
7163
7164         return 0;
7165 }
7166
7167 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7168                             bool *expired)
7169 {
7170         struct vcpu_vmx *vmx;
7171         u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
7172         struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
7173
7174         if (kvm_mwait_in_guest(vcpu->kvm) ||
7175                 kvm_can_post_timer_interrupt(vcpu))
7176                 return -EOPNOTSUPP;
7177
7178         vmx = to_vmx(vcpu);
7179         tscl = rdtsc();
7180         guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7181         delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
7182         lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7183                                                     ktimer->timer_advance_ns);
7184
7185         if (delta_tsc > lapic_timer_advance_cycles)
7186                 delta_tsc -= lapic_timer_advance_cycles;
7187         else
7188                 delta_tsc = 0;
7189
7190         /* Convert to host delta tsc if tsc scaling is enabled */
7191         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
7192             delta_tsc && u64_shl_div_u64(delta_tsc,
7193                                 kvm_tsc_scaling_ratio_frac_bits,
7194                                 vcpu->arch.tsc_scaling_ratio, &delta_tsc))
7195                 return -ERANGE;
7196
7197         /*
7198          * If the delta tsc can't fit in the 32 bit after the multi shift,
7199          * we can't use the preemption timer.
7200          * It's possible that it fits on later vmentries, but checking
7201          * on every vmentry is costly so we just use an hrtimer.
7202          */
7203         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7204                 return -ERANGE;
7205
7206         vmx->hv_deadline_tsc = tscl + delta_tsc;
7207         *expired = !delta_tsc;
7208         return 0;
7209 }
7210
7211 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7212 {
7213         to_vmx(vcpu)->hv_deadline_tsc = -1;
7214 }
7215 #endif
7216
7217 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
7218 {
7219         if (!kvm_pause_in_guest(vcpu->kvm))
7220                 shrink_ple_window(vcpu);
7221 }
7222
7223 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
7224                                      struct kvm_memory_slot *slot)
7225 {
7226         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
7227         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
7228 }
7229
7230 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
7231                                        struct kvm_memory_slot *slot)
7232 {
7233         kvm_mmu_slot_set_dirty(kvm, slot);
7234 }
7235
7236 static void vmx_flush_log_dirty(struct kvm *kvm)
7237 {
7238         kvm_flush_pml_buffers(kvm);
7239 }
7240
7241 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
7242 {
7243         struct vmcs12 *vmcs12;
7244         struct vcpu_vmx *vmx = to_vmx(vcpu);
7245         gpa_t gpa, dst;
7246
7247         if (is_guest_mode(vcpu)) {
7248                 WARN_ON_ONCE(vmx->nested.pml_full);
7249
7250                 /*
7251                  * Check if PML is enabled for the nested guest.
7252                  * Whether eptp bit 6 is set is already checked
7253                  * as part of A/D emulation.
7254                  */
7255                 vmcs12 = get_vmcs12(vcpu);
7256                 if (!nested_cpu_has_pml(vmcs12))
7257                         return 0;
7258
7259                 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
7260                         vmx->nested.pml_full = true;
7261                         return 1;
7262                 }
7263
7264                 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
7265                 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index;
7266
7267                 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa,
7268                                          offset_in_page(dst), sizeof(gpa)))
7269                         return 0;
7270
7271                 vmcs12->guest_pml_index--;
7272         }
7273
7274         return 0;
7275 }
7276
7277 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
7278                                            struct kvm_memory_slot *memslot,
7279                                            gfn_t offset, unsigned long mask)
7280 {
7281         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
7282 }
7283
7284 static void __pi_post_block(struct kvm_vcpu *vcpu)
7285 {
7286         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7287         struct pi_desc old, new;
7288         unsigned int dest;
7289
7290         do {
7291                 old.control = new.control = pi_desc->control;
7292                 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
7293                      "Wakeup handler not enabled while the VCPU is blocked\n");
7294
7295                 dest = cpu_physical_id(vcpu->cpu);
7296
7297                 if (x2apic_enabled())
7298                         new.ndst = dest;
7299                 else
7300                         new.ndst = (dest << 8) & 0xFF00;
7301
7302                 /* set 'NV' to 'notification vector' */
7303                 new.nv = POSTED_INTR_VECTOR;
7304         } while (cmpxchg64(&pi_desc->control, old.control,
7305                            new.control) != old.control);
7306
7307         if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
7308                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7309                 list_del(&vcpu->blocked_vcpu_list);
7310                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7311                 vcpu->pre_pcpu = -1;
7312         }
7313 }
7314
7315 /*
7316  * This routine does the following things for vCPU which is going
7317  * to be blocked if VT-d PI is enabled.
7318  * - Store the vCPU to the wakeup list, so when interrupts happen
7319  *   we can find the right vCPU to wake up.
7320  * - Change the Posted-interrupt descriptor as below:
7321  *      'NDST' <-- vcpu->pre_pcpu
7322  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
7323  * - If 'ON' is set during this process, which means at least one
7324  *   interrupt is posted for this vCPU, we cannot block it, in
7325  *   this case, return 1, otherwise, return 0.
7326  *
7327  */
7328 static int pi_pre_block(struct kvm_vcpu *vcpu)
7329 {
7330         unsigned int dest;
7331         struct pi_desc old, new;
7332         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7333
7334         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
7335                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
7336                 !kvm_vcpu_apicv_active(vcpu))
7337                 return 0;
7338
7339         WARN_ON(irqs_disabled());
7340         local_irq_disable();
7341         if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
7342                 vcpu->pre_pcpu = vcpu->cpu;
7343                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7344                 list_add_tail(&vcpu->blocked_vcpu_list,
7345                               &per_cpu(blocked_vcpu_on_cpu,
7346                                        vcpu->pre_pcpu));
7347                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7348         }
7349
7350         do {
7351                 old.control = new.control = pi_desc->control;
7352
7353                 WARN((pi_desc->sn == 1),
7354                      "Warning: SN field of posted-interrupts "
7355                      "is set before blocking\n");
7356
7357                 /*
7358                  * Since vCPU can be preempted during this process,
7359                  * vcpu->cpu could be different with pre_pcpu, we
7360                  * need to set pre_pcpu as the destination of wakeup
7361                  * notification event, then we can find the right vCPU
7362                  * to wakeup in wakeup handler if interrupts happen
7363                  * when the vCPU is in blocked state.
7364                  */
7365                 dest = cpu_physical_id(vcpu->pre_pcpu);
7366
7367                 if (x2apic_enabled())
7368                         new.ndst = dest;
7369                 else
7370                         new.ndst = (dest << 8) & 0xFF00;
7371
7372                 /* set 'NV' to 'wakeup vector' */
7373                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
7374         } while (cmpxchg64(&pi_desc->control, old.control,
7375                            new.control) != old.control);
7376
7377         /* We should not block the vCPU if an interrupt is posted for it.  */
7378         if (pi_test_on(pi_desc) == 1)
7379                 __pi_post_block(vcpu);
7380
7381         local_irq_enable();
7382         return (vcpu->pre_pcpu == -1);
7383 }
7384
7385 static int vmx_pre_block(struct kvm_vcpu *vcpu)
7386 {
7387         if (pi_pre_block(vcpu))
7388                 return 1;
7389
7390         if (kvm_lapic_hv_timer_in_use(vcpu))
7391                 kvm_lapic_switch_to_sw_timer(vcpu);
7392
7393         return 0;
7394 }
7395
7396 static void pi_post_block(struct kvm_vcpu *vcpu)
7397 {
7398         if (vcpu->pre_pcpu == -1)
7399                 return;
7400
7401         WARN_ON(irqs_disabled());
7402         local_irq_disable();
7403         __pi_post_block(vcpu);
7404         local_irq_enable();
7405 }
7406
7407 static void vmx_post_block(struct kvm_vcpu *vcpu)
7408 {
7409         if (kvm_x86_ops->set_hv_timer)
7410                 kvm_lapic_switch_to_hv_timer(vcpu);
7411
7412         pi_post_block(vcpu);
7413 }
7414
7415 /*
7416  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
7417  *
7418  * @kvm: kvm
7419  * @host_irq: host irq of the interrupt
7420  * @guest_irq: gsi of the interrupt
7421  * @set: set or unset PI
7422  * returns 0 on success, < 0 on failure
7423  */
7424 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
7425                               uint32_t guest_irq, bool set)
7426 {
7427         struct kvm_kernel_irq_routing_entry *e;
7428         struct kvm_irq_routing_table *irq_rt;
7429         struct kvm_lapic_irq irq;
7430         struct kvm_vcpu *vcpu;
7431         struct vcpu_data vcpu_info;
7432         int idx, ret = 0;
7433
7434         if (!kvm_arch_has_assigned_device(kvm) ||
7435                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7436                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
7437                 return 0;
7438
7439         idx = srcu_read_lock(&kvm->irq_srcu);
7440         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
7441         if (guest_irq >= irq_rt->nr_rt_entries ||
7442             hlist_empty(&irq_rt->map[guest_irq])) {
7443                 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
7444                              guest_irq, irq_rt->nr_rt_entries);
7445                 goto out;
7446         }
7447
7448         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
7449                 if (e->type != KVM_IRQ_ROUTING_MSI)
7450                         continue;
7451                 /*
7452                  * VT-d PI cannot support posting multicast/broadcast
7453                  * interrupts to a vCPU, we still use interrupt remapping
7454                  * for these kind of interrupts.
7455                  *
7456                  * For lowest-priority interrupts, we only support
7457                  * those with single CPU as the destination, e.g. user
7458                  * configures the interrupts via /proc/irq or uses
7459                  * irqbalance to make the interrupts single-CPU.
7460                  *
7461                  * We will support full lowest-priority interrupt later.
7462                  *
7463                  * In addition, we can only inject generic interrupts using
7464                  * the PI mechanism, refuse to route others through it.
7465                  */
7466
7467                 kvm_set_msi_irq(kvm, e, &irq);
7468                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) ||
7469                     !kvm_irq_is_postable(&irq)) {
7470                         /*
7471                          * Make sure the IRTE is in remapped mode if
7472                          * we don't handle it in posted mode.
7473                          */
7474                         ret = irq_set_vcpu_affinity(host_irq, NULL);
7475                         if (ret < 0) {
7476                                 printk(KERN_INFO
7477                                    "failed to back to remapped mode, irq: %u\n",
7478                                    host_irq);
7479                                 goto out;
7480                         }
7481
7482                         continue;
7483                 }
7484
7485                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
7486                 vcpu_info.vector = irq.vector;
7487
7488                 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
7489                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
7490
7491                 if (set)
7492                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
7493                 else
7494                         ret = irq_set_vcpu_affinity(host_irq, NULL);
7495
7496                 if (ret < 0) {
7497                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
7498                                         __func__);
7499                         goto out;
7500                 }
7501         }
7502
7503         ret = 0;
7504 out:
7505         srcu_read_unlock(&kvm->irq_srcu, idx);
7506         return ret;
7507 }
7508
7509 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7510 {
7511         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7512                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7513                         FEATURE_CONTROL_LMCE;
7514         else
7515                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7516                         ~FEATURE_CONTROL_LMCE;
7517 }
7518
7519 static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
7520 {
7521         /* we need a nested vmexit to enter SMM, postpone if run is pending */
7522         if (to_vmx(vcpu)->nested.nested_run_pending)
7523                 return 0;
7524         return 1;
7525 }
7526
7527 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7528 {
7529         struct vcpu_vmx *vmx = to_vmx(vcpu);
7530
7531         vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7532         if (vmx->nested.smm.guest_mode)
7533                 nested_vmx_vmexit(vcpu, -1, 0, 0);
7534
7535         vmx->nested.smm.vmxon = vmx->nested.vmxon;
7536         vmx->nested.vmxon = false;
7537         vmx_clear_hlt(vcpu);
7538         return 0;
7539 }
7540
7541 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
7542 {
7543         struct vcpu_vmx *vmx = to_vmx(vcpu);
7544         int ret;
7545
7546         if (vmx->nested.smm.vmxon) {
7547                 vmx->nested.vmxon = true;
7548                 vmx->nested.smm.vmxon = false;
7549         }
7550
7551         if (vmx->nested.smm.guest_mode) {
7552                 ret = nested_vmx_enter_non_root_mode(vcpu, false);
7553                 if (ret)
7554                         return ret;
7555
7556                 vmx->nested.smm.guest_mode = false;
7557         }
7558         return 0;
7559 }
7560
7561 static int enable_smi_window(struct kvm_vcpu *vcpu)
7562 {
7563         return 0;
7564 }
7565
7566 static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7567 {
7568         return false;
7569 }
7570
7571 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7572 {
7573         return to_vmx(vcpu)->nested.vmxon;
7574 }
7575
7576 static __init int hardware_setup(void)
7577 {
7578         unsigned long host_bndcfgs;
7579         struct desc_ptr dt;
7580         int r, i;
7581
7582         rdmsrl_safe(MSR_EFER, &host_efer);
7583
7584         store_idt(&dt);
7585         host_idt_base = dt.address;
7586
7587         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7588                 kvm_define_shared_msr(i, vmx_msr_index[i]);
7589
7590         if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7591                 return -EIO;
7592
7593         if (boot_cpu_has(X86_FEATURE_NX))
7594                 kvm_enable_efer_bits(EFER_NX);
7595
7596         if (boot_cpu_has(X86_FEATURE_MPX)) {
7597                 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7598                 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7599         }
7600
7601         if (boot_cpu_has(X86_FEATURE_XSAVES))
7602                 rdmsrl(MSR_IA32_XSS, host_xss);
7603
7604         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7605             !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7606                 enable_vpid = 0;
7607
7608         if (!cpu_has_vmx_ept() ||
7609             !cpu_has_vmx_ept_4levels() ||
7610             !cpu_has_vmx_ept_mt_wb() ||
7611             !cpu_has_vmx_invept_global())
7612                 enable_ept = 0;
7613
7614         if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7615                 enable_ept_ad_bits = 0;
7616
7617         if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7618                 enable_unrestricted_guest = 0;
7619
7620         if (!cpu_has_vmx_flexpriority())
7621                 flexpriority_enabled = 0;
7622
7623         if (!cpu_has_virtual_nmis())
7624                 enable_vnmi = 0;
7625
7626         /*
7627          * set_apic_access_page_addr() is used to reload apic access
7628          * page upon invalidation.  No need to do anything if not
7629          * using the APIC_ACCESS_ADDR VMCS field.
7630          */
7631         if (!flexpriority_enabled)
7632                 kvm_x86_ops->set_apic_access_page_addr = NULL;
7633
7634         if (!cpu_has_vmx_tpr_shadow())
7635                 kvm_x86_ops->update_cr8_intercept = NULL;
7636
7637         if (enable_ept && !cpu_has_vmx_ept_2m_page())
7638                 kvm_disable_largepages();
7639
7640 #if IS_ENABLED(CONFIG_HYPERV)
7641         if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7642             && enable_ept) {
7643                 kvm_x86_ops->tlb_remote_flush = hv_remote_flush_tlb;
7644                 kvm_x86_ops->tlb_remote_flush_with_range =
7645                                 hv_remote_flush_tlb_with_range;
7646         }
7647 #endif
7648
7649         if (!cpu_has_vmx_ple()) {
7650                 ple_gap = 0;
7651                 ple_window = 0;
7652                 ple_window_grow = 0;
7653                 ple_window_max = 0;
7654                 ple_window_shrink = 0;
7655         }
7656
7657         if (!cpu_has_vmx_apicv()) {
7658                 enable_apicv = 0;
7659                 kvm_x86_ops->sync_pir_to_irr = NULL;
7660         }
7661
7662         if (cpu_has_vmx_tsc_scaling()) {
7663                 kvm_has_tsc_control = true;
7664                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7665                 kvm_tsc_scaling_ratio_frac_bits = 48;
7666         }
7667
7668         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7669
7670         if (enable_ept)
7671                 vmx_enable_tdp();
7672         else
7673                 kvm_disable_tdp();
7674
7675         /*
7676          * Only enable PML when hardware supports PML feature, and both EPT
7677          * and EPT A/D bit features are enabled -- PML depends on them to work.
7678          */
7679         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7680                 enable_pml = 0;
7681
7682         if (!enable_pml) {
7683                 kvm_x86_ops->slot_enable_log_dirty = NULL;
7684                 kvm_x86_ops->slot_disable_log_dirty = NULL;
7685                 kvm_x86_ops->flush_log_dirty = NULL;
7686                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7687         }
7688
7689         if (!cpu_has_vmx_preemption_timer())
7690                 enable_preemption_timer = false;
7691
7692         if (enable_preemption_timer) {
7693                 u64 use_timer_freq = 5000ULL * 1000 * 1000;
7694                 u64 vmx_msr;
7695
7696                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7697                 cpu_preemption_timer_multi =
7698                         vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7699
7700                 if (tsc_khz)
7701                         use_timer_freq = (u64)tsc_khz * 1000;
7702                 use_timer_freq >>= cpu_preemption_timer_multi;
7703
7704                 /*
7705                  * KVM "disables" the preemption timer by setting it to its max
7706                  * value.  Don't use the timer if it might cause spurious exits
7707                  * at a rate faster than 0.1 Hz (of uninterrupted guest time).
7708                  */
7709                 if (use_timer_freq > 0xffffffffu / 10)
7710                         enable_preemption_timer = false;
7711         }
7712
7713         if (!enable_preemption_timer) {
7714                 kvm_x86_ops->set_hv_timer = NULL;
7715                 kvm_x86_ops->cancel_hv_timer = NULL;
7716                 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit;
7717         }
7718
7719         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
7720
7721         kvm_mce_cap_supported |= MCG_LMCE_P;
7722
7723         if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
7724                 return -EINVAL;
7725         if (!enable_ept || !cpu_has_vmx_intel_pt())
7726                 pt_mode = PT_MODE_SYSTEM;
7727
7728         if (nested) {
7729                 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
7730                                            vmx_capability.ept, enable_apicv);
7731
7732                 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
7733                 if (r)
7734                         return r;
7735         }
7736
7737         r = alloc_kvm_area();
7738         if (r)
7739                 nested_vmx_hardware_unsetup();
7740         return r;
7741 }
7742
7743 static __exit void hardware_unsetup(void)
7744 {
7745         if (nested)
7746                 nested_vmx_hardware_unsetup();
7747
7748         free_kvm_area();
7749 }
7750
7751 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
7752         .cpu_has_kvm_support = cpu_has_kvm_support,
7753         .disabled_by_bios = vmx_disabled_by_bios,
7754         .hardware_setup = hardware_setup,
7755         .hardware_unsetup = hardware_unsetup,
7756         .check_processor_compatibility = vmx_check_processor_compat,
7757         .hardware_enable = hardware_enable,
7758         .hardware_disable = hardware_disable,
7759         .cpu_has_accelerated_tpr = report_flexpriority,
7760         .has_emulated_msr = vmx_has_emulated_msr,
7761
7762         .vm_init = vmx_vm_init,
7763         .vm_alloc = vmx_vm_alloc,
7764         .vm_free = vmx_vm_free,
7765
7766         .vcpu_create = vmx_create_vcpu,
7767         .vcpu_free = vmx_free_vcpu,
7768         .vcpu_reset = vmx_vcpu_reset,
7769
7770         .prepare_guest_switch = vmx_prepare_switch_to_guest,
7771         .vcpu_load = vmx_vcpu_load,
7772         .vcpu_put = vmx_vcpu_put,
7773
7774         .update_bp_intercept = update_exception_bitmap,
7775         .get_msr_feature = vmx_get_msr_feature,
7776         .get_msr = vmx_get_msr,
7777         .set_msr = vmx_set_msr,
7778         .get_segment_base = vmx_get_segment_base,
7779         .get_segment = vmx_get_segment,
7780         .set_segment = vmx_set_segment,
7781         .get_cpl = vmx_get_cpl,
7782         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7783         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7784         .decache_cr3 = vmx_decache_cr3,
7785         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7786         .set_cr0 = vmx_set_cr0,
7787         .set_cr3 = vmx_set_cr3,
7788         .set_cr4 = vmx_set_cr4,
7789         .set_efer = vmx_set_efer,
7790         .get_idt = vmx_get_idt,
7791         .set_idt = vmx_set_idt,
7792         .get_gdt = vmx_get_gdt,
7793         .set_gdt = vmx_set_gdt,
7794         .get_dr6 = vmx_get_dr6,
7795         .set_dr6 = vmx_set_dr6,
7796         .set_dr7 = vmx_set_dr7,
7797         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
7798         .cache_reg = vmx_cache_reg,
7799         .get_rflags = vmx_get_rflags,
7800         .set_rflags = vmx_set_rflags,
7801
7802         .tlb_flush = vmx_flush_tlb,
7803         .tlb_flush_gva = vmx_flush_tlb_gva,
7804
7805         .run = vmx_vcpu_run,
7806         .handle_exit = vmx_handle_exit,
7807         .skip_emulated_instruction = skip_emulated_instruction,
7808         .set_interrupt_shadow = vmx_set_interrupt_shadow,
7809         .get_interrupt_shadow = vmx_get_interrupt_shadow,
7810         .patch_hypercall = vmx_patch_hypercall,
7811         .set_irq = vmx_inject_irq,
7812         .set_nmi = vmx_inject_nmi,
7813         .queue_exception = vmx_queue_exception,
7814         .cancel_injection = vmx_cancel_injection,
7815         .interrupt_allowed = vmx_interrupt_allowed,
7816         .nmi_allowed = vmx_nmi_allowed,
7817         .get_nmi_mask = vmx_get_nmi_mask,
7818         .set_nmi_mask = vmx_set_nmi_mask,
7819         .enable_nmi_window = enable_nmi_window,
7820         .enable_irq_window = enable_irq_window,
7821         .update_cr8_intercept = update_cr8_intercept,
7822         .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
7823         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
7824         .get_enable_apicv = vmx_get_enable_apicv,
7825         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
7826         .load_eoi_exitmap = vmx_load_eoi_exitmap,
7827         .apicv_post_state_restore = vmx_apicv_post_state_restore,
7828         .hwapic_irr_update = vmx_hwapic_irr_update,
7829         .hwapic_isr_update = vmx_hwapic_isr_update,
7830         .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
7831         .sync_pir_to_irr = vmx_sync_pir_to_irr,
7832         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
7833         .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt,
7834
7835         .set_tss_addr = vmx_set_tss_addr,
7836         .set_identity_map_addr = vmx_set_identity_map_addr,
7837         .get_tdp_level = get_ept_level,
7838         .get_mt_mask = vmx_get_mt_mask,
7839
7840         .get_exit_info = vmx_get_exit_info,
7841
7842         .get_lpage_level = vmx_get_lpage_level,
7843
7844         .cpuid_update = vmx_cpuid_update,
7845
7846         .rdtscp_supported = vmx_rdtscp_supported,
7847         .invpcid_supported = vmx_invpcid_supported,
7848
7849         .set_supported_cpuid = vmx_set_supported_cpuid,
7850
7851         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7852
7853         .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
7854         .write_l1_tsc_offset = vmx_write_l1_tsc_offset,
7855
7856         .set_tdp_cr3 = vmx_set_cr3,
7857
7858         .check_intercept = vmx_check_intercept,
7859         .handle_exit_irqoff = vmx_handle_exit_irqoff,
7860         .mpx_supported = vmx_mpx_supported,
7861         .xsaves_supported = vmx_xsaves_supported,
7862         .umip_emulated = vmx_umip_emulated,
7863         .pt_supported = vmx_pt_supported,
7864
7865         .request_immediate_exit = vmx_request_immediate_exit,
7866
7867         .sched_in = vmx_sched_in,
7868
7869         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
7870         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
7871         .flush_log_dirty = vmx_flush_log_dirty,
7872         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
7873         .write_log_dirty = vmx_write_pml_buffer,
7874
7875         .pre_block = vmx_pre_block,
7876         .post_block = vmx_post_block,
7877
7878         .pmu_ops = &intel_pmu_ops,
7879
7880         .update_pi_irte = vmx_update_pi_irte,
7881
7882 #ifdef CONFIG_X86_64
7883         .set_hv_timer = vmx_set_hv_timer,
7884         .cancel_hv_timer = vmx_cancel_hv_timer,
7885 #endif
7886
7887         .setup_mce = vmx_setup_mce,
7888
7889         .smi_allowed = vmx_smi_allowed,
7890         .pre_enter_smm = vmx_pre_enter_smm,
7891         .pre_leave_smm = vmx_pre_leave_smm,
7892         .enable_smi_window = enable_smi_window,
7893
7894         .check_nested_events = NULL,
7895         .get_nested_state = NULL,
7896         .set_nested_state = NULL,
7897         .get_vmcs12_pages = NULL,
7898         .nested_enable_evmcs = NULL,
7899         .nested_get_evmcs_version = NULL,
7900         .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault,
7901         .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
7902 };
7903
7904 static void vmx_cleanup_l1d_flush(void)
7905 {
7906         if (vmx_l1d_flush_pages) {
7907                 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
7908                 vmx_l1d_flush_pages = NULL;
7909         }
7910         /* Restore state so sysfs ignores VMX */
7911         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
7912 }
7913
7914 static void vmx_exit(void)
7915 {
7916 #ifdef CONFIG_KEXEC_CORE
7917         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
7918         synchronize_rcu();
7919 #endif
7920
7921         kvm_exit();
7922
7923 #if IS_ENABLED(CONFIG_HYPERV)
7924         if (static_branch_unlikely(&enable_evmcs)) {
7925                 int cpu;
7926                 struct hv_vp_assist_page *vp_ap;
7927                 /*
7928                  * Reset everything to support using non-enlightened VMCS
7929                  * access later (e.g. when we reload the module with
7930                  * enlightened_vmcs=0)
7931                  */
7932                 for_each_online_cpu(cpu) {
7933                         vp_ap = hv_get_vp_assist_page(cpu);
7934
7935                         if (!vp_ap)
7936                                 continue;
7937
7938                         vp_ap->nested_control.features.directhypercall = 0;
7939                         vp_ap->current_nested_vmcs = 0;
7940                         vp_ap->enlighten_vmentry = 0;
7941                 }
7942
7943                 static_branch_disable(&enable_evmcs);
7944         }
7945 #endif
7946         vmx_cleanup_l1d_flush();
7947 }
7948 module_exit(vmx_exit);
7949
7950 static int __init vmx_init(void)
7951 {
7952         int r;
7953
7954 #if IS_ENABLED(CONFIG_HYPERV)
7955         /*
7956          * Enlightened VMCS usage should be recommended and the host needs
7957          * to support eVMCS v1 or above. We can also disable eVMCS support
7958          * with module parameter.
7959          */
7960         if (enlightened_vmcs &&
7961             ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
7962             (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
7963             KVM_EVMCS_VERSION) {
7964                 int cpu;
7965
7966                 /* Check that we have assist pages on all online CPUs */
7967                 for_each_online_cpu(cpu) {
7968                         if (!hv_get_vp_assist_page(cpu)) {
7969                                 enlightened_vmcs = false;
7970                                 break;
7971                         }
7972                 }
7973
7974                 if (enlightened_vmcs) {
7975                         pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
7976                         static_branch_enable(&enable_evmcs);
7977                 }
7978
7979                 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
7980                         vmx_x86_ops.enable_direct_tlbflush
7981                                 = hv_enable_direct_tlbflush;
7982
7983         } else {
7984                 enlightened_vmcs = false;
7985         }
7986 #endif
7987
7988         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7989                      __alignof__(struct vcpu_vmx), THIS_MODULE);
7990         if (r)
7991                 return r;
7992
7993         /*
7994          * Must be called after kvm_init() so enable_ept is properly set
7995          * up. Hand the parameter mitigation value in which was stored in
7996          * the pre module init parser. If no parameter was given, it will
7997          * contain 'auto' which will be turned into the default 'cond'
7998          * mitigation mode.
7999          */
8000         r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
8001         if (r) {
8002                 vmx_exit();
8003                 return r;
8004         }
8005
8006 #ifdef CONFIG_KEXEC_CORE
8007         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8008                            crash_vmclear_local_loaded_vmcss);
8009 #endif
8010         vmx_check_vmcs12_offsets();
8011
8012         return 0;
8013 }
8014 module_init(vmx_init);