arch/x86/kvm/vmx/vmx.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Kernel-based Virtual Machine driver for Linux
   4  *
   5  * This module enables machines with Intel VT-x extensions to run virtual
   6  * machines without emulation or binary translation.
   7  *
   8  * Copyright (C) 2006 Qumranet, Inc.
   9  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  10  *
  11  * Authors:
  12  *   Avi Kivity   <avi@qumranet.com>
  13  *   Yaniv Kamay  <yaniv@qumranet.com>
  14  */
  15
  16 #include <linux/frame.h>
  17 #include <linux/highmem.h>
  18 #include <linux/hrtimer.h>
  19 #include <linux/kernel.h>
  20 #include <linux/kvm_host.h>
  21 #include <linux/module.h>
  22 #include <linux/moduleparam.h>
  23 #include <linux/mod_devicetable.h>
  24 #include <linux/mm.h>
  25 #include <linux/sched.h>
  26 #include <linux/sched/smt.h>
  27 #include <linux/slab.h>
  28 #include <linux/tboot.h>
  29 #include <linux/trace_events.h>
  30
  31 #include <asm/apic.h>
  32 #include <asm/asm.h>
  33 #include <asm/cpu.h>
  34 #include <asm/debugreg.h>
  35 #include <asm/desc.h>
  36 #include <asm/fpu/internal.h>
  37 #include <asm/io.h>
  38 #include <asm/irq_remapping.h>
  39 #include <asm/kexec.h>
  40 #include <asm/perf_event.h>
  41 #include <asm/mce.h>
  42 #include <asm/mmu_context.h>
  43 #include <asm/mshyperv.h>
  44 #include <asm/spec-ctrl.h>
  45 #include <asm/virtext.h>
  46 #include <asm/vmx.h>
  47
  48 #include "capabilities.h"
  49 #include "cpuid.h"
  50 #include "evmcs.h"
  51 #include "irq.h"
  52 #include "kvm_cache_regs.h"
  53 #include "lapic.h"
  54 #include "mmu.h"
  55 #include "nested.h"
  56 #include "ops.h"
  57 #include "pmu.h"
  58 #include "trace.h"
  59 #include "vmcs.h"
  60 #include "vmcs12.h"
  61 #include "vmx.h"
  62 #include "x86.h"
  63
  64 MODULE_AUTHOR("Qumranet");
  65 MODULE_LICENSE("GPL");
  66
  67 static const struct x86_cpu_id vmx_cpu_id[] = {
  68         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  69         {}
  70 };
  71 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  72
  73 bool __read_mostly enable_vpid = 1;
  74 module_param_named(vpid, enable_vpid, bool, 0444);
  75
  76 static bool __read_mostly enable_vnmi = 1;
  77 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
  78
  79 bool __read_mostly flexpriority_enabled = 1;
  80 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  81
  82 bool __read_mostly enable_ept = 1;
  83 module_param_named(ept, enable_ept, bool, S_IRUGO);
  84
  85 bool __read_mostly enable_unrestricted_guest = 1;
  86 module_param_named(unrestricted_guest,
  87                         enable_unrestricted_guest, bool, S_IRUGO);
  88
  89 bool __read_mostly enable_ept_ad_bits = 1;
  90 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  91
  92 static bool __read_mostly emulate_invalid_guest_state = true;
  93 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  94
  95 static bool __read_mostly fasteoi = 1;
  96 module_param(fasteoi, bool, S_IRUGO);
  97
  98 static bool __read_mostly enable_apicv = 1;
  99 module_param(enable_apicv, bool, S_IRUGO);
 100
 101 /*
 102  * If nested=1, nested virtualization is supported, i.e., guests may use
 103  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 104  * use VMX instructions.
 105  */
 106 static bool __read_mostly nested = 1;
 107 module_param(nested, bool, S_IRUGO);
 108
 109 static u64 __read_mostly host_xss;
 110
 111 bool __read_mostly enable_pml = 1;
 112 module_param_named(pml, enable_pml, bool, S_IRUGO);
 113
 114 static bool __read_mostly dump_invalid_vmcs = 0;
 115 module_param(dump_invalid_vmcs, bool, 0644);
 116
 117 #define MSR_BITMAP_MODE_X2APIC          1
 118 #define MSR_BITMAP_MODE_X2APIC_APICV    2
 119
 120 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 121
 122 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 123 static int __read_mostly cpu_preemption_timer_multi;
 124 static bool __read_mostly enable_preemption_timer = 1;
 125 #ifdef CONFIG_X86_64
 126 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 127 #endif
 128
 129 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
 130 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
 131 #define KVM_VM_CR0_ALWAYS_ON                            \
 132         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST |      \
 133          X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
 134 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 135         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 136          | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
 137
 138 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
 139 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 140 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 141
 142 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 143
 144 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
 145         RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
 146         RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
 147         RTIT_STATUS_BYTECNT))
 148
 149 #define MSR_IA32_RTIT_OUTPUT_BASE_MASK \
 150         (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f)
 151
 152 /*
 153  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 154  * ple_gap:    upper bound on the amount of time between two successive
 155  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 156  *             According to test, this time is usually smaller than 128 cycles.
 157  * ple_window: upper bound on the amount of time a guest is allowed to execute
 158  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 159  *             less than 2^12 cycles
 160  * Time is measured based on a counter that runs at the same rate as the TSC,
 161  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 162  */
 163 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
 164 module_param(ple_gap, uint, 0444);
 165
 166 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 167 module_param(ple_window, uint, 0444);
 168
 169 /* Default doubles per-vcpu window every exit. */
 170 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 171 module_param(ple_window_grow, uint, 0444);
 172
 173 /* Default resets per-vcpu window every exit to ple_window. */
 174 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 175 module_param(ple_window_shrink, uint, 0444);
 176
 177 /* Default is to compute the maximum so we can never overflow. */
 178 static unsigned int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 179 module_param(ple_window_max, uint, 0444);
 180
 181 /* Default is SYSTEM mode, 1 for host-guest mode */
 182 int __read_mostly pt_mode = PT_MODE_SYSTEM;
 183 module_param(pt_mode, int, S_IRUGO);
 184
 185 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
 186 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
 187 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
 188
 189 /* Storage for pre module init parameter parsing */
 190 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
 191
 192 static const struct {
 193         const char *option;
 194         bool for_parse;
 195 } vmentry_l1d_param[] = {
 196         [VMENTER_L1D_FLUSH_AUTO]         = {"auto", true},
 197         [VMENTER_L1D_FLUSH_NEVER]        = {"never", true},
 198         [VMENTER_L1D_FLUSH_COND]         = {"cond", true},
 199         [VMENTER_L1D_FLUSH_ALWAYS]       = {"always", true},
 200         [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
 201         [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
 202 };
 203
 204 #define L1D_CACHE_ORDER 4
 205 static void *vmx_l1d_flush_pages;
 206
 207 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
 208 {
 209         struct page *page;
 210         unsigned int i;
 211
 212         if (!boot_cpu_has_bug(X86_BUG_L1TF)) {
 213                 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
 214                 return 0;
 215         }
 216
 217         if (!enable_ept) {
 218                 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
 219                 return 0;
 220         }
 221
 222         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
 223                 u64 msr;
 224
 225                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
 226                 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
 227                         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
 228                         return 0;
 229                 }
 230         }
 231
 232         /* If set to auto use the default l1tf mitigation method */
 233         if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
 234                 switch (l1tf_mitigation) {
 235                 case L1TF_MITIGATION_OFF:
 236                         l1tf = VMENTER_L1D_FLUSH_NEVER;
 237                         break;
 238                 case L1TF_MITIGATION_FLUSH_NOWARN:
 239                 case L1TF_MITIGATION_FLUSH:
 240                 case L1TF_MITIGATION_FLUSH_NOSMT:
 241                         l1tf = VMENTER_L1D_FLUSH_COND;
 242                         break;
 243                 case L1TF_MITIGATION_FULL:
 244                 case L1TF_MITIGATION_FULL_FORCE:
 245                         l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 246                         break;
 247                 }
 248         } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
 249                 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 250         }
 251
 252         if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
 253             !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
 254                 /*
 255                  * This allocation for vmx_l1d_flush_pages is not tied to a VM
 256                  * lifetime and so should not be charged to a memcg.
 257                  */
 258                 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
 259                 if (!page)
 260                         return -ENOMEM;
 261                 vmx_l1d_flush_pages = page_address(page);
 262
 263                 /*
 264                  * Initialize each page with a different pattern in
 265                  * order to protect against KSM in the nested
 266                  * virtualization case.
 267                  */
 268                 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
 269                         memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
 270                                PAGE_SIZE);
 271                 }
 272         }
 273
 274         l1tf_vmx_mitigation = l1tf;
 275
 276         if (l1tf != VMENTER_L1D_FLUSH_NEVER)
 277                 static_branch_enable(&vmx_l1d_should_flush);
 278         else
 279                 static_branch_disable(&vmx_l1d_should_flush);
 280
 281         if (l1tf == VMENTER_L1D_FLUSH_COND)
 282                 static_branch_enable(&vmx_l1d_flush_cond);
 283         else
 284                 static_branch_disable(&vmx_l1d_flush_cond);
 285         return 0;
 286 }
 287
 288 static int vmentry_l1d_flush_parse(const char *s)
 289 {
 290         unsigned int i;
 291
 292         if (s) {
 293                 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
 294                         if (vmentry_l1d_param[i].for_parse &&
 295                             sysfs_streq(s, vmentry_l1d_param[i].option))
 296                                 return i;
 297                 }
 298         }
 299         return -EINVAL;
 300 }
 301
 302 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
 303 {
 304         int l1tf, ret;
 305
 306         l1tf = vmentry_l1d_flush_parse(s);
 307         if (l1tf < 0)
 308                 return l1tf;
 309
 310         if (!boot_cpu_has(X86_BUG_L1TF))
 311                 return 0;
 312
 313         /*
 314          * Has vmx_init() run already? If not then this is the pre init
 315          * parameter parsing. In that case just store the value and let
 316          * vmx_init() do the proper setup after enable_ept has been
 317          * established.
 318          */
 319         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
 320                 vmentry_l1d_flush_param = l1tf;
 321                 return 0;
 322         }
 323
 324         mutex_lock(&vmx_l1d_flush_mutex);
 325         ret = vmx_setup_l1d_flush(l1tf);
 326         mutex_unlock(&vmx_l1d_flush_mutex);
 327         return ret;
 328 }
 329
 330 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
 331 {
 332         if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
 333                 return sprintf(s, "???\n");
 334
 335         return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
 336 }
 337
 338 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
 339         .set = vmentry_l1d_flush_set,
 340         .get = vmentry_l1d_flush_get,
 341 };
 342 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
 343
 344 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 345 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 346 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
 347                                                           u32 msr, int type);
 348
 349 void vmx_vmexit(void);
 350
 351 #define vmx_insn_failed(fmt...)         \
 352 do {                                    \
 353         WARN_ONCE(1, fmt);              \
 354         pr_warn_ratelimited(fmt);       \
 355 } while (0)
 356
 357 asmlinkage void vmread_error(unsigned long field, bool fault)
 358 {
 359         if (fault)
 360                 kvm_spurious_fault();
 361         else
 362                 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field);
 363 }
 364
 365 noinline void vmwrite_error(unsigned long field, unsigned long value)
 366 {
 367         vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n",
 368                         field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 369 }
 370
 371 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr)
 372 {
 373         vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr);
 374 }
 375
 376 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr)
 377 {
 378         vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr);
 379 }
 380
 381 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva)
 382 {
 383         vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n",
 384                         ext, vpid, gva);
 385 }
 386
 387 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa)
 388 {
 389         vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n",
 390                         ext, eptp, gpa);
 391 }
 392
 393 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 394 DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 395 /*
 396  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 397  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 398  */
 399 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 400
 401 /*
 402  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 403  * can find which vCPU should be waken up.
 404  */
 405 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 406 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 407
 408 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 409 static DEFINE_SPINLOCK(vmx_vpid_lock);
 410
 411 struct vmcs_config vmcs_config;
 412 struct vmx_capability vmx_capability;
 413
 414 #define VMX_SEGMENT_FIELD(seg)                                  \
 415         [VCPU_SREG_##seg] = {                                   \
 416                 .selector = GUEST_##seg##_SELECTOR,             \
 417                 .base = GUEST_##seg##_BASE,                     \
 418                 .limit = GUEST_##seg##_LIMIT,                   \
 419                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 420         }
 421
 422 static const struct kvm_vmx_segment_field {
 423         unsigned selector;
 424         unsigned base;
 425         unsigned limit;
 426         unsigned ar_bytes;
 427 } kvm_vmx_segment_fields[] = {
 428         VMX_SEGMENT_FIELD(CS),
 429         VMX_SEGMENT_FIELD(DS),
 430         VMX_SEGMENT_FIELD(ES),
 431         VMX_SEGMENT_FIELD(FS),
 432         VMX_SEGMENT_FIELD(GS),
 433         VMX_SEGMENT_FIELD(SS),
 434         VMX_SEGMENT_FIELD(TR),
 435         VMX_SEGMENT_FIELD(LDTR),
 436 };
 437
 438 u64 host_efer;
 439 static unsigned long host_idt_base;
 440
 441 /*
 442  * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
 443  * will emulate SYSCALL in legacy mode if the vendor string in guest
 444  * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
 445  * support this emulation, IA32_STAR must always be included in
 446  * vmx_msr_index[], even in i386 builds.
 447  */
 448 const u32 vmx_msr_index[] = {
 449 #ifdef CONFIG_X86_64
 450         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 451 #endif
 452         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 453 };
 454
 455 #if IS_ENABLED(CONFIG_HYPERV)
 456 static bool __read_mostly enlightened_vmcs = true;
 457 module_param(enlightened_vmcs, bool, 0444);
 458
 459 /* check_ept_pointer() should be under protection of ept_pointer_lock. */
 460 static void check_ept_pointer_match(struct kvm *kvm)
 461 {
 462         struct kvm_vcpu *vcpu;
 463         u64 tmp_eptp = INVALID_PAGE;
 464         int i;
 465
 466         kvm_for_each_vcpu(i, vcpu, kvm) {
 467                 if (!VALID_PAGE(tmp_eptp)) {
 468                         tmp_eptp = to_vmx(vcpu)->ept_pointer;
 469                 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
 470                         to_kvm_vmx(kvm)->ept_pointers_match
 471                                 = EPT_POINTERS_MISMATCH;
 472                         return;
 473                 }
 474         }
 475
 476         to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
 477 }
 478
 479 static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush,
 480                 void *data)
 481 {
 482         struct kvm_tlb_range *range = data;
 483
 484         return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn,
 485                         range->pages);
 486 }
 487
 488 static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm,
 489                 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range)
 490 {
 491         u64 ept_pointer = to_vmx(vcpu)->ept_pointer;
 492
 493         /*
 494          * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address
 495          * of the base of EPT PML4 table, strip off EPT configuration
 496          * information.
 497          */
 498         if (range)
 499                 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK,
 500                                 kvm_fill_hv_flush_list_func, (void *)range);
 501         else
 502                 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK);
 503 }
 504
 505 static int hv_remote_flush_tlb_with_range(struct kvm *kvm,
 506                 struct kvm_tlb_range *range)
 507 {
 508         struct kvm_vcpu *vcpu;
 509         int ret = 0, i;
 510
 511         spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
 512
 513         if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
 514                 check_ept_pointer_match(kvm);
 515
 516         if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
 517                 kvm_for_each_vcpu(i, vcpu, kvm) {
 518                         /* If ept_pointer is invalid pointer, bypass flush request. */
 519                         if (VALID_PAGE(to_vmx(vcpu)->ept_pointer))
 520                                 ret |= __hv_remote_flush_tlb_with_range(
 521                                         kvm, vcpu, range);
 522                 }
 523         } else {
 524                 ret = __hv_remote_flush_tlb_with_range(kvm,
 525                                 kvm_get_vcpu(kvm, 0), range);
 526         }
 527
 528         spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
 529         return ret;
 530 }
 531 static int hv_remote_flush_tlb(struct kvm *kvm)
 532 {
 533         return hv_remote_flush_tlb_with_range(kvm, NULL);
 534 }
 535
 536 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
 537 {
 538         struct hv_enlightened_vmcs *evmcs;
 539         struct hv_partition_assist_pg **p_hv_pa_pg =
 540                         &vcpu->kvm->arch.hyperv.hv_pa_pg;
 541         /*
 542          * Synthetic VM-Exit is not enabled in current code and so All
 543          * evmcs in singe VM shares same assist page.
 544          */
 545         if (!*p_hv_pa_pg)
 546                 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL);
 547
 548         if (!*p_hv_pa_pg)
 549                 return -ENOMEM;
 550
 551         evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
 552
 553         evmcs->partition_assist_page =
 554                 __pa(*p_hv_pa_pg);
 555         evmcs->hv_vm_id = (unsigned long)vcpu->kvm;
 556         evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
 557
 558         return 0;
 559 }
 560
 561 #endif /* IS_ENABLED(CONFIG_HYPERV) */
 562
 563 /*
 564  * Comment's format: document - errata name - stepping - processor name.
 565  * Refer from
 566  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
 567  */
 568 static u32 vmx_preemption_cpu_tfms[] = {
 569 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
 570 0x000206E6,
 571 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
 572 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
 573 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
 574 0x00020652,
 575 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
 576 0x00020655,
 577 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
 578 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
 579 /*
 580  * 320767.pdf - AAP86  - B1 -
 581  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
 582  */
 583 0x000106E5,
 584 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
 585 0x000106A0,
 586 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
 587 0x000106A1,
 588 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
 589 0x000106A4,
 590  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
 591  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
 592  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
 593 0x000106A5,
 594  /* Xeon E3-1220 V2 */
 595 0x000306A8,
 596 };
 597
 598 static inline bool cpu_has_broken_vmx_preemption_timer(void)
 599 {
 600         u32 eax = cpuid_eax(0x00000001), i;
 601
 602         /* Clear the reserved bits */
 603         eax &= ~(0x3U << 14 | 0xfU << 28);
 604         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
 605                 if (eax == vmx_preemption_cpu_tfms[i])
 606                         return true;
 607
 608         return false;
 609 }
 610
 611 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
 612 {
 613         return flexpriority_enabled && lapic_in_kernel(vcpu);
 614 }
 615
 616 static inline bool report_flexpriority(void)
 617 {
 618         return flexpriority_enabled;
 619 }
 620
 621 static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 622 {
 623         int i;
 624
 625         for (i = 0; i < vmx->nmsrs; ++i)
 626                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 627                         return i;
 628         return -1;
 629 }
 630
 631 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 632 {
 633         int i;
 634
 635         i = __find_msr_index(vmx, msr);
 636         if (i >= 0)
 637                 return &vmx->guest_msrs[i];
 638         return NULL;
 639 }
 640
 641 void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
 642 {
 643         vmcs_clear(loaded_vmcs->vmcs);
 644         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
 645                 vmcs_clear(loaded_vmcs->shadow_vmcs);
 646         loaded_vmcs->cpu = -1;
 647         loaded_vmcs->launched = 0;
 648 }
 649
 650 #ifdef CONFIG_KEXEC_CORE
 651 /*
 652  * This bitmap is used to indicate whether the vmclear
 653  * operation is enabled on all cpus. All disabled by
 654  * default.
 655  */
 656 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
 657
 658 static inline void crash_enable_local_vmclear(int cpu)
 659 {
 660         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
 661 }
 662
 663 static inline void crash_disable_local_vmclear(int cpu)
 664 {
 665         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
 666 }
 667
 668 static inline int crash_local_vmclear_enabled(int cpu)
 669 {
 670         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
 671 }
 672
 673 static void crash_vmclear_local_loaded_vmcss(void)
 674 {
 675         int cpu = raw_smp_processor_id();
 676         struct loaded_vmcs *v;
 677
 678         if (!crash_local_vmclear_enabled(cpu))
 679                 return;
 680
 681         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
 682                             loaded_vmcss_on_cpu_link)
 683                 vmcs_clear(v->vmcs);
 684 }
 685 #else
 686 static inline void crash_enable_local_vmclear(int cpu) { }
 687 static inline void crash_disable_local_vmclear(int cpu) { }
 688 #endif /* CONFIG_KEXEC_CORE */
 689
 690 static void __loaded_vmcs_clear(void *arg)
 691 {
 692         struct loaded_vmcs *loaded_vmcs = arg;
 693         int cpu = raw_smp_processor_id();
 694
 695         if (loaded_vmcs->cpu != cpu)
 696                 return; /* vcpu migration can race with cpu offline */
 697         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
 698                 per_cpu(current_vmcs, cpu) = NULL;
 699         crash_disable_local_vmclear(cpu);
 700         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
 701
 702         /*
 703          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
 704          * is before setting loaded_vmcs->vcpu to -1 which is done in
 705          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
 706          * then adds the vmcs into percpu list before it is deleted.
 707          */
 708         smp_wmb();
 709
 710         loaded_vmcs_init(loaded_vmcs);
 711         crash_enable_local_vmclear(cpu);
 712 }
 713
 714 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
 715 {
 716         int cpu = loaded_vmcs->cpu;
 717
 718         if (cpu != -1)
 719                 smp_call_function_single(cpu,
 720                          __loaded_vmcs_clear, loaded_vmcs, 1);
 721 }
 722
 723 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
 724                                        unsigned field)
 725 {
 726         bool ret;
 727         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
 728
 729         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
 730                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
 731                 vmx->segment_cache.bitmask = 0;
 732         }
 733         ret = vmx->segment_cache.bitmask & mask;
 734         vmx->segment_cache.bitmask |= mask;
 735         return ret;
 736 }
 737
 738 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
 739 {
 740         u16 *p = &vmx->segment_cache.seg[seg].selector;
 741
 742         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
 743                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
 744         return *p;
 745 }
 746
 747 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
 748 {
 749         ulong *p = &vmx->segment_cache.seg[seg].base;
 750
 751         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
 752                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
 753         return *p;
 754 }
 755
 756 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
 757 {
 758         u32 *p = &vmx->segment_cache.seg[seg].limit;
 759
 760         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
 761                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
 762         return *p;
 763 }
 764
 765 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
 766 {
 767         u32 *p = &vmx->segment_cache.seg[seg].ar;
 768
 769         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
 770                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
 771         return *p;
 772 }
 773
 774 void update_exception_bitmap(struct kvm_vcpu *vcpu)
 775 {
 776         u32 eb;
 777
 778         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
 779              (1u << DB_VECTOR) | (1u << AC_VECTOR);
 780         /*
 781          * Guest access to VMware backdoor ports could legitimately
 782          * trigger #GP because of TSS I/O permission bitmap.
 783          * We intercept those #GP and allow access to them anyway
 784          * as VMware does.
 785          */
 786         if (enable_vmware_backdoor)
 787                 eb |= (1u << GP_VECTOR);
 788         if ((vcpu->guest_debug &
 789              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
 790             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
 791                 eb |= 1u << BP_VECTOR;
 792         if (to_vmx(vcpu)->rmode.vm86_active)
 793                 eb = ~0;
 794         if (enable_ept)
 795                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 796
 797         /* When we are running a nested L2 guest and L1 specified for it a
 798          * certain exception bitmap, we must trap the same exceptions and pass
 799          * them to L1. When running L2, we will only handle the exceptions
 800          * specified above if L1 did not want them.
 801          */
 802         if (is_guest_mode(vcpu))
 803                 eb |= get_vmcs12(vcpu)->exception_bitmap;
 804
 805         vmcs_write32(EXCEPTION_BITMAP, eb);
 806 }
 807
 808 /*
 809  * Check if MSR is intercepted for currently loaded MSR bitmap.
 810  */
 811 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
 812 {
 813         unsigned long *msr_bitmap;
 814         int f = sizeof(unsigned long);
 815
 816         if (!cpu_has_vmx_msr_bitmap())
 817                 return true;
 818
 819         msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
 820
 821         if (msr <= 0x1fff) {
 822                 return !!test_bit(msr, msr_bitmap + 0x800 / f);
 823         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
 824                 msr &= 0x1fff;
 825                 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
 826         }
 827
 828         return true;
 829 }
 830
 831 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
 832                 unsigned long entry, unsigned long exit)
 833 {
 834         vm_entry_controls_clearbit(vmx, entry);
 835         vm_exit_controls_clearbit(vmx, exit);
 836 }
 837
 838 static int find_msr(struct vmx_msrs *m, unsigned int msr)
 839 {
 840         unsigned int i;
 841
 842         for (i = 0; i < m->nr; ++i) {
 843                 if (m->val[i].index == msr)
 844                         return i;
 845         }
 846         return -ENOENT;
 847 }
 848
 849 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
 850 {
 851         int i;
 852         struct msr_autoload *m = &vmx->msr_autoload;
 853
 854         switch (msr) {
 855         case MSR_EFER:
 856                 if (cpu_has_load_ia32_efer()) {
 857                         clear_atomic_switch_msr_special(vmx,
 858                                         VM_ENTRY_LOAD_IA32_EFER,
 859                                         VM_EXIT_LOAD_IA32_EFER);
 860                         return;
 861                 }
 862                 break;
 863         case MSR_CORE_PERF_GLOBAL_CTRL:
 864                 if (cpu_has_load_perf_global_ctrl()) {
 865                         clear_atomic_switch_msr_special(vmx,
 866                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
 867                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
 868                         return;
 869                 }
 870                 break;
 871         }
 872         i = find_msr(&m->guest, msr);
 873         if (i < 0)
 874                 goto skip_guest;
 875         --m->guest.nr;
 876         m->guest.val[i] = m->guest.val[m->guest.nr];
 877         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
 878
 879 skip_guest:
 880         i = find_msr(&m->host, msr);
 881         if (i < 0)
 882                 return;
 883
 884         --m->host.nr;
 885         m->host.val[i] = m->host.val[m->host.nr];
 886         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
 887 }
 888
 889 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
 890                 unsigned long entry, unsigned long exit,
 891                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
 892                 u64 guest_val, u64 host_val)
 893 {
 894         vmcs_write64(guest_val_vmcs, guest_val);
 895         if (host_val_vmcs != HOST_IA32_EFER)
 896                 vmcs_write64(host_val_vmcs, host_val);
 897         vm_entry_controls_setbit(vmx, entry);
 898         vm_exit_controls_setbit(vmx, exit);
 899 }
 900
 901 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
 902                                   u64 guest_val, u64 host_val, bool entry_only)
 903 {
 904         int i, j = 0;
 905         struct msr_autoload *m = &vmx->msr_autoload;
 906
 907         switch (msr) {
 908         case MSR_EFER:
 909                 if (cpu_has_load_ia32_efer()) {
 910                         add_atomic_switch_msr_special(vmx,
 911                                         VM_ENTRY_LOAD_IA32_EFER,
 912                                         VM_EXIT_LOAD_IA32_EFER,
 913                                         GUEST_IA32_EFER,
 914                                         HOST_IA32_EFER,
 915                                         guest_val, host_val);
 916                         return;
 917                 }
 918                 break;
 919         case MSR_CORE_PERF_GLOBAL_CTRL:
 920                 if (cpu_has_load_perf_global_ctrl()) {
 921                         add_atomic_switch_msr_special(vmx,
 922                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
 923                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
 924                                         GUEST_IA32_PERF_GLOBAL_CTRL,
 925                                         HOST_IA32_PERF_GLOBAL_CTRL,
 926                                         guest_val, host_val);
 927                         return;
 928                 }
 929                 break;
 930         case MSR_IA32_PEBS_ENABLE:
 931                 /* PEBS needs a quiescent period after being disabled (to write
 932                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
 933                  * provide that period, so a CPU could write host's record into
 934                  * guest's memory.
 935                  */
 936                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
 937         }
 938
 939         i = find_msr(&m->guest, msr);
 940         if (!entry_only)
 941                 j = find_msr(&m->host, msr);
 942
 943         if ((i < 0 && m->guest.nr == NR_AUTOLOAD_MSRS) ||
 944                 (j < 0 &&  m->host.nr == NR_AUTOLOAD_MSRS)) {
 945                 printk_once(KERN_WARNING "Not enough msr switch entries. "
 946                                 "Can't add msr %x\n", msr);
 947                 return;
 948         }
 949         if (i < 0) {
 950                 i = m->guest.nr++;
 951                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
 952         }
 953         m->guest.val[i].index = msr;
 954         m->guest.val[i].value = guest_val;
 955
 956         if (entry_only)
 957                 return;
 958
 959         if (j < 0) {
 960                 j = m->host.nr++;
 961                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
 962         }
 963         m->host.val[j].index = msr;
 964         m->host.val[j].value = host_val;
 965 }
 966
 967 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
 968 {
 969         u64 guest_efer = vmx->vcpu.arch.efer;
 970         u64 ignore_bits = 0;
 971
 972         /* Shadow paging assumes NX to be available.  */
 973         if (!enable_ept)
 974                 guest_efer |= EFER_NX;
 975
 976         /*
 977          * LMA and LME handled by hardware; SCE meaningless outside long mode.
 978          */
 979         ignore_bits |= EFER_SCE;
 980 #ifdef CONFIG_X86_64
 981         ignore_bits |= EFER_LMA | EFER_LME;
 982         /* SCE is meaningful only in long mode on Intel */
 983         if (guest_efer & EFER_LMA)
 984                 ignore_bits &= ~(u64)EFER_SCE;
 985 #endif
 986
 987         /*
 988          * On EPT, we can't emulate NX, so we must switch EFER atomically.
 989          * On CPUs that support "load IA32_EFER", always switch EFER
 990          * atomically, since it's faster than switching it manually.
 991          */
 992         if (cpu_has_load_ia32_efer() ||
 993             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
 994                 if (!(guest_efer & EFER_LMA))
 995                         guest_efer &= ~EFER_LME;
 996                 if (guest_efer != host_efer)
 997                         add_atomic_switch_msr(vmx, MSR_EFER,
 998                                               guest_efer, host_efer, false);
 999                 else
1000                         clear_atomic_switch_msr(vmx, MSR_EFER);
1001                 return false;
1002         } else {
1003                 clear_atomic_switch_msr(vmx, MSR_EFER);
1004
1005                 guest_efer &= ~ignore_bits;
1006                 guest_efer |= host_efer & ignore_bits;
1007
1008                 vmx->guest_msrs[efer_offset].data = guest_efer;
1009                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1010
1011                 return true;
1012         }
1013 }
1014
1015 #ifdef CONFIG_X86_32
1016 /*
1017  * On 32-bit kernels, VM exits still load the FS and GS bases from the
1018  * VMCS rather than the segment table.  KVM uses this helper to figure
1019  * out the current bases to poke them into the VMCS before entry.
1020  */
1021 static unsigned long segment_base(u16 selector)
1022 {
1023         struct desc_struct *table;
1024         unsigned long v;
1025
1026         if (!(selector & ~SEGMENT_RPL_MASK))
1027                 return 0;
1028
1029         table = get_current_gdt_ro();
1030
1031         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
1032                 u16 ldt_selector = kvm_read_ldt();
1033
1034                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
1035                         return 0;
1036
1037                 table = (struct desc_struct *)segment_base(ldt_selector);
1038         }
1039         v = get_desc_base(&table[selector >> 3]);
1040         return v;
1041 }
1042 #endif
1043
1044 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
1045 {
1046         u32 i;
1047
1048         wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1049         wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1050         wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1051         wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1052         for (i = 0; i < addr_range; i++) {
1053                 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1054                 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1055         }
1056 }
1057
1058 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
1059 {
1060         u32 i;
1061
1062         rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1063         rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1064         rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1065         rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1066         for (i = 0; i < addr_range; i++) {
1067                 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1068                 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1069         }
1070 }
1071
1072 static void pt_guest_enter(struct vcpu_vmx *vmx)
1073 {
1074         if (pt_mode == PT_MODE_SYSTEM)
1075                 return;
1076
1077         /*
1078          * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1079          * Save host state before VM entry.
1080          */
1081         rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1082         if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1083                 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1084                 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1085                 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1086         }
1087 }
1088
1089 static void pt_guest_exit(struct vcpu_vmx *vmx)
1090 {
1091         if (pt_mode == PT_MODE_SYSTEM)
1092                 return;
1093
1094         if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1095                 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1096                 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1097         }
1098
1099         /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1100         wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1101 }
1102
1103 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1104                         unsigned long fs_base, unsigned long gs_base)
1105 {
1106         if (unlikely(fs_sel != host->fs_sel)) {
1107                 if (!(fs_sel & 7))
1108                         vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1109                 else
1110                         vmcs_write16(HOST_FS_SELECTOR, 0);
1111                 host->fs_sel = fs_sel;
1112         }
1113         if (unlikely(gs_sel != host->gs_sel)) {
1114                 if (!(gs_sel & 7))
1115                         vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1116                 else
1117                         vmcs_write16(HOST_GS_SELECTOR, 0);
1118                 host->gs_sel = gs_sel;
1119         }
1120         if (unlikely(fs_base != host->fs_base)) {
1121                 vmcs_writel(HOST_FS_BASE, fs_base);
1122                 host->fs_base = fs_base;
1123         }
1124         if (unlikely(gs_base != host->gs_base)) {
1125                 vmcs_writel(HOST_GS_BASE, gs_base);
1126                 host->gs_base = gs_base;
1127         }
1128 }
1129
1130 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1131 {
1132         struct vcpu_vmx *vmx = to_vmx(vcpu);
1133         struct vmcs_host_state *host_state;
1134 #ifdef CONFIG_X86_64
1135         int cpu = raw_smp_processor_id();
1136 #endif
1137         unsigned long fs_base, gs_base;
1138         u16 fs_sel, gs_sel;
1139         int i;
1140
1141         vmx->req_immediate_exit = false;
1142
1143         /*
1144          * Note that guest MSRs to be saved/restored can also be changed
1145          * when guest state is loaded. This happens when guest transitions
1146          * to/from long-mode by setting MSR_EFER.LMA.
1147          */
1148         if (!vmx->guest_msrs_ready) {
1149                 vmx->guest_msrs_ready = true;
1150                 for (i = 0; i < vmx->save_nmsrs; ++i)
1151                         kvm_set_shared_msr(vmx->guest_msrs[i].index,
1152                                            vmx->guest_msrs[i].data,
1153                                            vmx->guest_msrs[i].mask);
1154
1155         }
1156         if (vmx->guest_state_loaded)
1157                 return;
1158
1159         host_state = &vmx->loaded_vmcs->host_state;
1160
1161         /*
1162          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1163          * allow segment selectors with cpl > 0 or ti == 1.
1164          */
1165         host_state->ldt_sel = kvm_read_ldt();
1166
1167 #ifdef CONFIG_X86_64
1168         savesegment(ds, host_state->ds_sel);
1169         savesegment(es, host_state->es_sel);
1170
1171         gs_base = cpu_kernelmode_gs_base(cpu);
1172         if (likely(is_64bit_mm(current->mm))) {
1173                 save_fsgs_for_kvm();
1174                 fs_sel = current->thread.fsindex;
1175                 gs_sel = current->thread.gsindex;
1176                 fs_base = current->thread.fsbase;
1177                 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
1178         } else {
1179                 savesegment(fs, fs_sel);
1180                 savesegment(gs, gs_sel);
1181                 fs_base = read_msr(MSR_FS_BASE);
1182                 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
1183         }
1184
1185         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1186 #else
1187         savesegment(fs, fs_sel);
1188         savesegment(gs, gs_sel);
1189         fs_base = segment_base(fs_sel);
1190         gs_base = segment_base(gs_sel);
1191 #endif
1192
1193         vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
1194         vmx->guest_state_loaded = true;
1195 }
1196
1197 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
1198 {
1199         struct vmcs_host_state *host_state;
1200
1201         if (!vmx->guest_state_loaded)
1202                 return;
1203
1204         host_state = &vmx->loaded_vmcs->host_state;
1205
1206         ++vmx->vcpu.stat.host_state_reload;
1207
1208 #ifdef CONFIG_X86_64
1209         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1210 #endif
1211         if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1212                 kvm_load_ldt(host_state->ldt_sel);
1213 #ifdef CONFIG_X86_64
1214                 load_gs_index(host_state->gs_sel);
1215 #else
1216                 loadsegment(gs, host_state->gs_sel);
1217 #endif
1218         }
1219         if (host_state->fs_sel & 7)
1220                 loadsegment(fs, host_state->fs_sel);
1221 #ifdef CONFIG_X86_64
1222         if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1223                 loadsegment(ds, host_state->ds_sel);
1224                 loadsegment(es, host_state->es_sel);
1225         }
1226 #endif
1227         invalidate_tss_limit();
1228 #ifdef CONFIG_X86_64
1229         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1230 #endif
1231         load_fixmap_gdt(raw_smp_processor_id());
1232         vmx->guest_state_loaded = false;
1233         vmx->guest_msrs_ready = false;
1234 }
1235
1236 #ifdef CONFIG_X86_64
1237 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
1238 {
1239         preempt_disable();
1240         if (vmx->guest_state_loaded)
1241                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1242         preempt_enable();
1243         return vmx->msr_guest_kernel_gs_base;
1244 }
1245
1246 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1247 {
1248         preempt_disable();
1249         if (vmx->guest_state_loaded)
1250                 wrmsrl(MSR_KERNEL_GS_BASE, data);
1251         preempt_enable();
1252         vmx->msr_guest_kernel_gs_base = data;
1253 }
1254 #endif
1255
1256 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1257 {
1258         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1259         struct pi_desc old, new;
1260         unsigned int dest;
1261
1262         /*
1263          * In case of hot-plug or hot-unplug, we may have to undo
1264          * vmx_vcpu_pi_put even if there is no assigned device.  And we
1265          * always keep PI.NDST up to date for simplicity: it makes the
1266          * code easier, and CPU migration is not a fast path.
1267          */
1268         if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
1269                 return;
1270
1271         /*
1272          * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
1273          * PI.NDST: pi_post_block is the one expected to change PID.NDST and the
1274          * wakeup handler expects the vCPU to be on the blocked_vcpu_list that
1275          * matches PI.NDST. Otherwise, a vcpu may not be able to be woken up
1276          * correctly.
1277          */
1278         if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || vcpu->cpu == cpu) {
1279                 pi_clear_sn(pi_desc);
1280                 goto after_clear_sn;
1281         }
1282
1283         /* The full case.  */
1284         do {
1285                 old.control = new.control = pi_desc->control;
1286
1287                 dest = cpu_physical_id(cpu);
1288
1289                 if (x2apic_enabled())
1290                         new.ndst = dest;
1291                 else
1292                         new.ndst = (dest << 8) & 0xFF00;
1293
1294                 new.sn = 0;
1295         } while (cmpxchg64(&pi_desc->control, old.control,
1296                            new.control) != old.control);
1297
1298 after_clear_sn:
1299
1300         /*
1301          * Clear SN before reading the bitmap.  The VT-d firmware
1302          * writes the bitmap and reads SN atomically (5.2.3 in the
1303          * spec), so it doesn't really have a memory barrier that
1304          * pairs with this, but we cannot do that and we need one.
1305          */
1306         smp_mb__after_atomic();
1307
1308         if (!pi_is_pir_empty(pi_desc))
1309                 pi_set_on(pi_desc);
1310 }
1311
1312 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu)
1313 {
1314         struct vcpu_vmx *vmx = to_vmx(vcpu);
1315         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
1316
1317         if (!already_loaded) {
1318                 loaded_vmcs_clear(vmx->loaded_vmcs);
1319                 local_irq_disable();
1320                 crash_disable_local_vmclear(cpu);
1321
1322                 /*
1323                  * Read loaded_vmcs->cpu should be before fetching
1324                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1325                  * See the comments in __loaded_vmcs_clear().
1326                  */
1327                 smp_rmb();
1328
1329                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1330                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1331                 crash_enable_local_vmclear(cpu);
1332                 local_irq_enable();
1333         }
1334
1335         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1336                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1337                 vmcs_load(vmx->loaded_vmcs->vmcs);
1338                 indirect_branch_prediction_barrier();
1339         }
1340
1341         if (!already_loaded) {
1342                 void *gdt = get_current_gdt_ro();
1343                 unsigned long sysenter_esp;
1344
1345                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1346
1347                 /*
1348                  * Linux uses per-cpu TSS and GDT, so set these when switching
1349                  * processors.  See 22.2.4.
1350                  */
1351                 vmcs_writel(HOST_TR_BASE,
1352                             (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
1353                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
1354
1355                 /*
1356                  * VM exits change the host TR limit to 0x67 after a VM
1357                  * exit.  This is okay, since 0x67 covers everything except
1358                  * the IO bitmap and have have code to handle the IO bitmap
1359                  * being lost after a VM exit.
1360                  */
1361                 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
1362
1363                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1364                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1365
1366                 vmx->loaded_vmcs->cpu = cpu;
1367         }
1368
1369         /* Setup TSC multiplier */
1370         if (kvm_has_tsc_control &&
1371             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
1372                 decache_tsc_multiplier(vmx);
1373 }
1374
1375 /*
1376  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1377  * vcpu mutex is already taken.
1378  */
1379 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1380 {
1381         struct vcpu_vmx *vmx = to_vmx(vcpu);
1382
1383         vmx_vcpu_load_vmcs(vcpu, cpu);
1384
1385         vmx_vcpu_pi_load(vcpu, cpu);
1386
1387         vmx->host_pkru = read_pkru();
1388         vmx->host_debugctlmsr = get_debugctlmsr();
1389 }
1390
1391 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
1392 {
1393         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1394
1395         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1396                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
1397                 !kvm_vcpu_apicv_active(vcpu))
1398                 return;
1399
1400         /* Set SN when the vCPU is preempted */
1401         if (vcpu->preempted)
1402                 pi_set_sn(pi_desc);
1403 }
1404
1405 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1406 {
1407         vmx_vcpu_pi_put(vcpu);
1408
1409         vmx_prepare_switch_to_host(to_vmx(vcpu));
1410 }
1411
1412 static bool emulation_required(struct kvm_vcpu *vcpu)
1413 {
1414         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
1415 }
1416
1417 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1418
1419 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1420 {
1421         unsigned long rflags, save_rflags;
1422
1423         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1424                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1425                 rflags = vmcs_readl(GUEST_RFLAGS);
1426                 if (to_vmx(vcpu)->rmode.vm86_active) {
1427                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1428                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1429                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1430                 }
1431                 to_vmx(vcpu)->rflags = rflags;
1432         }
1433         return to_vmx(vcpu)->rflags;
1434 }
1435
1436 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1437 {
1438         unsigned long old_rflags = vmx_get_rflags(vcpu);
1439
1440         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1441         to_vmx(vcpu)->rflags = rflags;
1442         if (to_vmx(vcpu)->rmode.vm86_active) {
1443                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1444                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1445         }
1446         vmcs_writel(GUEST_RFLAGS, rflags);
1447
1448         if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
1449                 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
1450 }
1451
1452 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1453 {
1454         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1455         int ret = 0;
1456
1457         if (interruptibility & GUEST_INTR_STATE_STI)
1458                 ret |= KVM_X86_SHADOW_INT_STI;
1459         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1460                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1461
1462         return ret;
1463 }
1464
1465 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1466 {
1467         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1468         u32 interruptibility = interruptibility_old;
1469
1470         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1471
1472         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1473                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1474         else if (mask & KVM_X86_SHADOW_INT_STI)
1475                 interruptibility |= GUEST_INTR_STATE_STI;
1476
1477         if ((interruptibility != interruptibility_old))
1478                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1479 }
1480
1481 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1482 {
1483         struct vcpu_vmx *vmx = to_vmx(vcpu);
1484         unsigned long value;
1485
1486         /*
1487          * Any MSR write that attempts to change bits marked reserved will
1488          * case a #GP fault.
1489          */
1490         if (data & vmx->pt_desc.ctl_bitmask)
1491                 return 1;
1492
1493         /*
1494          * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1495          * result in a #GP unless the same write also clears TraceEn.
1496          */
1497         if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1498                 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1499                 return 1;
1500
1501         /*
1502          * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1503          * and FabricEn would cause #GP, if
1504          * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1505          */
1506         if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1507                 !(data & RTIT_CTL_FABRIC_EN) &&
1508                 !intel_pt_validate_cap(vmx->pt_desc.caps,
1509                                         PT_CAP_single_range_output))
1510                 return 1;
1511
1512         /*
1513          * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1514          * utilize encodings marked reserved will casue a #GP fault.
1515          */
1516         value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1517         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1518                         !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1519                         RTIT_CTL_MTC_RANGE_OFFSET, &value))
1520                 return 1;
1521         value = intel_pt_validate_cap(vmx->pt_desc.caps,
1522                                                 PT_CAP_cycle_thresholds);
1523         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1524                         !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1525                         RTIT_CTL_CYC_THRESH_OFFSET, &value))
1526                 return 1;
1527         value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1528         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1529                         !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1530                         RTIT_CTL_PSB_FREQ_OFFSET, &value))
1531                 return 1;
1532
1533         /*
1534          * If ADDRx_CFG is reserved or the encodings is >2 will
1535          * cause a #GP fault.
1536          */
1537         value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1538         if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
1539                 return 1;
1540         value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1541         if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
1542                 return 1;
1543         value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1544         if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
1545                 return 1;
1546         value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1547         if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
1548                 return 1;
1549
1550         return 0;
1551 }
1552
1553 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
1554 {
1555         unsigned long rip;
1556
1557         /*
1558          * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
1559          * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
1560          * set when EPT misconfig occurs.  In practice, real hardware updates
1561          * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
1562          * (namely Hyper-V) don't set it due to it being undefined behavior,
1563          * i.e. we end up advancing IP with some random value.
1564          */
1565         if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
1566             to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) {
1567                 rip = kvm_rip_read(vcpu);
1568                 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1569                 kvm_rip_write(vcpu, rip);
1570         } else {
1571                 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
1572                         return 0;
1573         }
1574
1575         /* skipping an emulated instruction also counts */
1576         vmx_set_interrupt_shadow(vcpu, 0);
1577
1578         return 1;
1579 }
1580
1581 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1582 {
1583         /*
1584          * Ensure that we clear the HLT state in the VMCS.  We don't need to
1585          * explicitly skip the instruction because if the HLT state is set,
1586          * then the instruction is already executing and RIP has already been
1587          * advanced.
1588          */
1589         if (kvm_hlt_in_guest(vcpu->kvm) &&
1590                         vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1591                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1592 }
1593
1594 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
1595 {
1596         struct vcpu_vmx *vmx = to_vmx(vcpu);
1597         unsigned nr = vcpu->arch.exception.nr;
1598         bool has_error_code = vcpu->arch.exception.has_error_code;
1599         u32 error_code = vcpu->arch.exception.error_code;
1600         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1601
1602         kvm_deliver_exception_payload(vcpu);
1603
1604         if (has_error_code) {
1605                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1606                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1607         }
1608
1609         if (vmx->rmode.vm86_active) {
1610                 int inc_eip = 0;
1611                 if (kvm_exception_is_soft(nr))
1612                         inc_eip = vcpu->arch.event_exit_inst_len;
1613                 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
1614                 return;
1615         }
1616
1617         WARN_ON_ONCE(vmx->emulation_required);
1618
1619         if (kvm_exception_is_soft(nr)) {
1620                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1621                              vmx->vcpu.arch.event_exit_inst_len);
1622                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1623         } else
1624                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1625
1626         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1627
1628         vmx_clear_hlt(vcpu);
1629 }
1630
1631 static bool vmx_rdtscp_supported(void)
1632 {
1633         return cpu_has_vmx_rdtscp();
1634 }
1635
1636 static bool vmx_invpcid_supported(void)
1637 {
1638         return cpu_has_vmx_invpcid();
1639 }
1640
1641 /*
1642  * Swap MSR entry in host/guest MSR entry array.
1643  */
1644 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1645 {
1646         struct shared_msr_entry tmp;
1647
1648         tmp = vmx->guest_msrs[to];
1649         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1650         vmx->guest_msrs[from] = tmp;
1651 }
1652
1653 /*
1654  * Set up the vmcs to automatically save and restore system
1655  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1656  * mode, as fiddling with msrs is very expensive.
1657  */
1658 static void setup_msrs(struct vcpu_vmx *vmx)
1659 {
1660         int save_nmsrs, index;
1661
1662         save_nmsrs = 0;
1663 #ifdef CONFIG_X86_64
1664         /*
1665          * The SYSCALL MSRs are only needed on long mode guests, and only
1666          * when EFER.SCE is set.
1667          */
1668         if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) {
1669                 index = __find_msr_index(vmx, MSR_STAR);
1670                 if (index >= 0)
1671                         move_msr_up(vmx, index, save_nmsrs++);
1672                 index = __find_msr_index(vmx, MSR_LSTAR);
1673                 if (index >= 0)
1674                         move_msr_up(vmx, index, save_nmsrs++);
1675                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1676                 if (index >= 0)
1677                         move_msr_up(vmx, index, save_nmsrs++);
1678         }
1679 #endif
1680         index = __find_msr_index(vmx, MSR_EFER);
1681         if (index >= 0 && update_transition_efer(vmx, index))
1682                 move_msr_up(vmx, index, save_nmsrs++);
1683         index = __find_msr_index(vmx, MSR_TSC_AUX);
1684         if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
1685                 move_msr_up(vmx, index, save_nmsrs++);
1686
1687         vmx->save_nmsrs = save_nmsrs;
1688         vmx->guest_msrs_ready = false;
1689
1690         if (cpu_has_vmx_msr_bitmap())
1691                 vmx_update_msr_bitmap(&vmx->vcpu);
1692 }
1693
1694 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1695 {
1696         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1697
1698         if (is_guest_mode(vcpu) &&
1699             (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
1700                 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
1701
1702         return vcpu->arch.tsc_offset;
1703 }
1704
1705 static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1706 {
1707         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1708         u64 g_tsc_offset = 0;
1709
1710         /*
1711          * We're here if L1 chose not to trap WRMSR to TSC. According
1712          * to the spec, this should set L1's TSC; The offset that L1
1713          * set for L2 remains unchanged, and still needs to be added
1714          * to the newly set TSC to get L2's TSC.
1715          */
1716         if (is_guest_mode(vcpu) &&
1717             (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
1718                 g_tsc_offset = vmcs12->tsc_offset;
1719
1720         trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1721                                    vcpu->arch.tsc_offset - g_tsc_offset,
1722                                    offset);
1723         vmcs_write64(TSC_OFFSET, offset + g_tsc_offset);
1724         return offset + g_tsc_offset;
1725 }
1726
1727 /*
1728  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1729  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1730  * all guests if the "nested" module option is off, and can also be disabled
1731  * for a single guest by disabling its VMX cpuid bit.
1732  */
1733 bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1734 {
1735         return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
1736 }
1737
1738 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1739                                                  uint64_t val)
1740 {
1741         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
1742
1743         return !(val & ~valid_bits);
1744 }
1745
1746 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
1747 {
1748         switch (msr->index) {
1749         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1750                 if (!nested)
1751                         return 1;
1752                 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1753         default:
1754                 return 1;
1755         }
1756
1757         return 0;
1758 }
1759
1760 /*
1761  * Reads an msr value (of 'msr_index') into 'pdata'.
1762  * Returns 0 on success, non-0 otherwise.
1763  * Assumes vcpu_load() was already called.
1764  */
1765 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1766 {
1767         struct vcpu_vmx *vmx = to_vmx(vcpu);
1768         struct shared_msr_entry *msr;
1769         u32 index;
1770
1771         switch (msr_info->index) {
1772 #ifdef CONFIG_X86_64
1773         case MSR_FS_BASE:
1774                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
1775                 break;
1776         case MSR_GS_BASE:
1777                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
1778                 break;
1779         case MSR_KERNEL_GS_BASE:
1780                 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
1781                 break;
1782 #endif
1783         case MSR_EFER:
1784                 return kvm_get_msr_common(vcpu, msr_info);
1785         case MSR_IA32_UMWAIT_CONTROL:
1786                 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1787                         return 1;
1788
1789                 msr_info->data = vmx->msr_ia32_umwait_control;
1790                 break;
1791         case MSR_IA32_SPEC_CTRL:
1792                 if (!msr_info->host_initiated &&
1793                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1794                         return 1;
1795
1796                 msr_info->data = to_vmx(vcpu)->spec_ctrl;
1797                 break;
1798         case MSR_IA32_SYSENTER_CS:
1799                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
1800                 break;
1801         case MSR_IA32_SYSENTER_EIP:
1802                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
1803                 break;
1804         case MSR_IA32_SYSENTER_ESP:
1805                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
1806                 break;
1807         case MSR_IA32_BNDCFGS:
1808                 if (!kvm_mpx_supported() ||
1809                     (!msr_info->host_initiated &&
1810                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1811                         return 1;
1812                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
1813                 break;
1814         case MSR_IA32_MCG_EXT_CTL:
1815                 if (!msr_info->host_initiated &&
1816                     !(vmx->msr_ia32_feature_control &
1817                       FEATURE_CONTROL_LMCE))
1818                         return 1;
1819                 msr_info->data = vcpu->arch.mcg_ext_ctl;
1820                 break;
1821         case MSR_IA32_FEATURE_CONTROL:
1822                 msr_info->data = vmx->msr_ia32_feature_control;
1823                 break;
1824         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1825                 if (!nested_vmx_allowed(vcpu))
1826                         return 1;
1827                 return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1828                                        &msr_info->data);
1829         case MSR_IA32_XSS:
1830                 if (!vmx_xsaves_supported() ||
1831                     (!msr_info->host_initiated &&
1832                      !(guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
1833                        guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))))
1834                         return 1;
1835                 msr_info->data = vcpu->arch.ia32_xss;
1836                 break;
1837         case MSR_IA32_RTIT_CTL:
1838                 if (pt_mode != PT_MODE_HOST_GUEST)
1839                         return 1;
1840                 msr_info->data = vmx->pt_desc.guest.ctl;
1841                 break;
1842         case MSR_IA32_RTIT_STATUS:
1843                 if (pt_mode != PT_MODE_HOST_GUEST)
1844                         return 1;
1845                 msr_info->data = vmx->pt_desc.guest.status;
1846                 break;
1847         case MSR_IA32_RTIT_CR3_MATCH:
1848                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1849                         !intel_pt_validate_cap(vmx->pt_desc.caps,
1850                                                 PT_CAP_cr3_filtering))
1851                         return 1;
1852                 msr_info->data = vmx->pt_desc.guest.cr3_match;
1853                 break;
1854         case MSR_IA32_RTIT_OUTPUT_BASE:
1855                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1856                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1857                                         PT_CAP_topa_output) &&
1858                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1859                                         PT_CAP_single_range_output)))
1860                         return 1;
1861                 msr_info->data = vmx->pt_desc.guest.output_base;
1862                 break;
1863         case MSR_IA32_RTIT_OUTPUT_MASK:
1864                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1865                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1866                                         PT_CAP_topa_output) &&
1867                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1868                                         PT_CAP_single_range_output)))
1869                         return 1;
1870                 msr_info->data = vmx->pt_desc.guest.output_mask;
1871                 break;
1872         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1873                 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1874                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1875                         (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
1876                                         PT_CAP_num_address_ranges)))
1877                         return 1;
1878                 if (index % 2)
1879                         msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1880                 else
1881                         msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1882                 break;
1883         case MSR_TSC_AUX:
1884                 if (!msr_info->host_initiated &&
1885                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
1886                         return 1;
1887                 /* Else, falls through */
1888         default:
1889                 msr = find_msr_entry(vmx, msr_info->index);
1890                 if (msr) {
1891                         msr_info->data = msr->data;
1892                         break;
1893                 }
1894                 return kvm_get_msr_common(vcpu, msr_info);
1895         }
1896
1897         return 0;
1898 }
1899
1900 /*
1901  * Writes msr value into into the appropriate "register".
1902  * Returns 0 on success, non-0 otherwise.
1903  * Assumes vcpu_load() was already called.
1904  */
1905 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1906 {
1907         struct vcpu_vmx *vmx = to_vmx(vcpu);
1908         struct shared_msr_entry *msr;
1909         int ret = 0;
1910         u32 msr_index = msr_info->index;
1911         u64 data = msr_info->data;
1912         u32 index;
1913
1914         switch (msr_index) {
1915         case MSR_EFER:
1916                 ret = kvm_set_msr_common(vcpu, msr_info);
1917                 break;
1918 #ifdef CONFIG_X86_64
1919         case MSR_FS_BASE:
1920                 vmx_segment_cache_clear(vmx);
1921                 vmcs_writel(GUEST_FS_BASE, data);
1922                 break;
1923         case MSR_GS_BASE:
1924                 vmx_segment_cache_clear(vmx);
1925                 vmcs_writel(GUEST_GS_BASE, data);
1926                 break;
1927         case MSR_KERNEL_GS_BASE:
1928                 vmx_write_guest_kernel_gs_base(vmx, data);
1929                 break;
1930 #endif
1931         case MSR_IA32_SYSENTER_CS:
1932                 if (is_guest_mode(vcpu))
1933                         get_vmcs12(vcpu)->guest_sysenter_cs = data;
1934                 vmcs_write32(GUEST_SYSENTER_CS, data);
1935                 break;
1936         case MSR_IA32_SYSENTER_EIP:
1937                 if (is_guest_mode(vcpu))
1938                         get_vmcs12(vcpu)->guest_sysenter_eip = data;
1939                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1940                 break;
1941         case MSR_IA32_SYSENTER_ESP:
1942                 if (is_guest_mode(vcpu))
1943                         get_vmcs12(vcpu)->guest_sysenter_esp = data;
1944                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1945                 break;
1946         case MSR_IA32_DEBUGCTLMSR:
1947                 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
1948                                                 VM_EXIT_SAVE_DEBUG_CONTROLS)
1949                         get_vmcs12(vcpu)->guest_ia32_debugctl = data;
1950
1951                 ret = kvm_set_msr_common(vcpu, msr_info);
1952                 break;
1953
1954         case MSR_IA32_BNDCFGS:
1955                 if (!kvm_mpx_supported() ||
1956                     (!msr_info->host_initiated &&
1957                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1958                         return 1;
1959                 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
1960                     (data & MSR_IA32_BNDCFGS_RSVD))
1961                         return 1;
1962                 vmcs_write64(GUEST_BNDCFGS, data);
1963                 break;
1964         case MSR_IA32_UMWAIT_CONTROL:
1965                 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1966                         return 1;
1967
1968                 /* The reserved bit 1 and non-32 bit [63:32] should be zero */
1969                 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
1970                         return 1;
1971
1972                 vmx->msr_ia32_umwait_control = data;
1973                 break;
1974         case MSR_IA32_SPEC_CTRL:
1975                 if (!msr_info->host_initiated &&
1976                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1977                         return 1;
1978
1979                 /* The STIBP bit doesn't fault even if it's not advertised */
1980                 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
1981                         return 1;
1982
1983                 vmx->spec_ctrl = data;
1984
1985                 if (!data)
1986                         break;
1987
1988                 /*
1989                  * For non-nested:
1990                  * When it's written (to non-zero) for the first time, pass
1991                  * it through.
1992                  *
1993                  * For nested:
1994                  * The handling of the MSR bitmap for L2 guests is done in
1995                  * nested_vmx_merge_msr_bitmap. We should not touch the
1996                  * vmcs02.msr_bitmap here since it gets completely overwritten
1997                  * in the merging. We update the vmcs01 here for L1 as well
1998                  * since it will end up touching the MSR anyway now.
1999                  */
2000                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
2001                                               MSR_IA32_SPEC_CTRL,
2002                                               MSR_TYPE_RW);
2003                 break;
2004         case MSR_IA32_PRED_CMD:
2005                 if (!msr_info->host_initiated &&
2006                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2007                         return 1;
2008
2009                 if (data & ~PRED_CMD_IBPB)
2010                         return 1;
2011
2012                 if (!data)
2013                         break;
2014
2015                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2016
2017                 /*
2018                  * For non-nested:
2019                  * When it's written (to non-zero) for the first time, pass
2020                  * it through.
2021                  *
2022                  * For nested:
2023                  * The handling of the MSR bitmap for L2 guests is done in
2024                  * nested_vmx_merge_msr_bitmap. We should not touch the
2025                  * vmcs02.msr_bitmap here since it gets completely overwritten
2026                  * in the merging.
2027                  */
2028                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
2029                                               MSR_TYPE_W);
2030                 break;
2031         case MSR_IA32_CR_PAT:
2032                 if (!kvm_pat_valid(data))
2033                         return 1;
2034
2035                 if (is_guest_mode(vcpu) &&
2036                     get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
2037                         get_vmcs12(vcpu)->guest_ia32_pat = data;
2038
2039                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2040                         vmcs_write64(GUEST_IA32_PAT, data);
2041                         vcpu->arch.pat = data;
2042                         break;
2043                 }
2044                 ret = kvm_set_msr_common(vcpu, msr_info);
2045                 break;
2046         case MSR_IA32_TSC_ADJUST:
2047                 ret = kvm_set_msr_common(vcpu, msr_info);
2048                 break;
2049         case MSR_IA32_MCG_EXT_CTL:
2050                 if ((!msr_info->host_initiated &&
2051                      !(to_vmx(vcpu)->msr_ia32_feature_control &
2052                        FEATURE_CONTROL_LMCE)) ||
2053                     (data & ~MCG_EXT_CTL_LMCE_EN))
2054                         return 1;
2055                 vcpu->arch.mcg_ext_ctl = data;
2056                 break;
2057         case MSR_IA32_FEATURE_CONTROL:
2058                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
2059                     (to_vmx(vcpu)->msr_ia32_feature_control &
2060                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2061                         return 1;
2062                 vmx->msr_ia32_feature_control = data;
2063                 if (msr_info->host_initiated && data == 0)
2064                         vmx_leave_nested(vcpu);
2065                 break;
2066         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2067                 if (!msr_info->host_initiated)
2068                         return 1; /* they are read-only */
2069                 if (!nested_vmx_allowed(vcpu))
2070                         return 1;
2071                 return vmx_set_vmx_msr(vcpu, msr_index, data);
2072         case MSR_IA32_XSS:
2073                 if (!vmx_xsaves_supported() ||
2074                     (!msr_info->host_initiated &&
2075                      !(guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
2076                        guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))))
2077                         return 1;
2078                 /*
2079                  * The only supported bit as of Skylake is bit 8, but
2080                  * it is not supported on KVM.
2081                  */
2082                 if (data != 0)
2083                         return 1;
2084                 vcpu->arch.ia32_xss = data;
2085                 if (vcpu->arch.ia32_xss != host_xss)
2086                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2087                                 vcpu->arch.ia32_xss, host_xss, false);
2088                 else
2089                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2090                 break;
2091         case MSR_IA32_RTIT_CTL:
2092                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2093                         vmx_rtit_ctl_check(vcpu, data) ||
2094                         vmx->nested.vmxon)
2095                         return 1;
2096                 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
2097                 vmx->pt_desc.guest.ctl = data;
2098                 pt_update_intercept_for_msr(vmx);
2099                 break;
2100         case MSR_IA32_RTIT_STATUS:
2101                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2102                         (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2103                         (data & MSR_IA32_RTIT_STATUS_MASK))
2104                         return 1;
2105                 vmx->pt_desc.guest.status = data;
2106                 break;
2107         case MSR_IA32_RTIT_CR3_MATCH:
2108                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2109                         (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2110                         !intel_pt_validate_cap(vmx->pt_desc.caps,
2111                                                 PT_CAP_cr3_filtering))
2112                         return 1;
2113                 vmx->pt_desc.guest.cr3_match = data;
2114                 break;
2115         case MSR_IA32_RTIT_OUTPUT_BASE:
2116                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2117                         (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2118                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
2119                                         PT_CAP_topa_output) &&
2120                          !intel_pt_validate_cap(vmx->pt_desc.caps,
2121                                         PT_CAP_single_range_output)) ||
2122                         (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK))
2123                         return 1;
2124                 vmx->pt_desc.guest.output_base = data;
2125                 break;
2126         case MSR_IA32_RTIT_OUTPUT_MASK:
2127                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2128                         (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2129                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
2130                                         PT_CAP_topa_output) &&
2131                          !intel_pt_validate_cap(vmx->pt_desc.caps,
2132                                         PT_CAP_single_range_output)))
2133                         return 1;
2134                 vmx->pt_desc.guest.output_mask = data;
2135                 break;
2136         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2137                 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2138                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2139                         (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2140                         (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
2141                                         PT_CAP_num_address_ranges)))
2142                         return 1;
2143                 if (index % 2)
2144                         vmx->pt_desc.guest.addr_b[index / 2] = data;
2145                 else
2146                         vmx->pt_desc.guest.addr_a[index / 2] = data;
2147                 break;
2148         case MSR_TSC_AUX:
2149                 if (!msr_info->host_initiated &&
2150                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
2151                         return 1;
2152                 /* Check reserved bit, higher 32 bits should be zero */
2153                 if ((data >> 32) != 0)
2154                         return 1;
2155                 /* Else, falls through */
2156         default:
2157                 msr = find_msr_entry(vmx, msr_index);
2158                 if (msr) {
2159                         u64 old_msr_data = msr->data;
2160                         msr->data = data;
2161                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2162                                 preempt_disable();
2163                                 ret = kvm_set_shared_msr(msr->index, msr->data,
2164                                                          msr->mask);
2165                                 preempt_enable();
2166                                 if (ret)
2167                                         msr->data = old_msr_data;
2168                         }
2169                         break;
2170                 }
2171                 ret = kvm_set_msr_common(vcpu, msr_info);
2172         }
2173
2174         return ret;
2175 }
2176
2177 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2178 {
2179         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2180         switch (reg) {
2181         case VCPU_REGS_RSP:
2182                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2183                 break;
2184         case VCPU_REGS_RIP:
2185                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2186                 break;
2187         case VCPU_EXREG_PDPTR:
2188                 if (enable_ept)
2189                         ept_save_pdptrs(vcpu);
2190                 break;
2191         default:
2192                 break;
2193         }
2194 }
2195
2196 static __init int cpu_has_kvm_support(void)
2197 {
2198         return cpu_has_vmx();
2199 }
2200
2201 static __init int vmx_disabled_by_bios(void)
2202 {
2203         u64 msr;
2204
2205         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2206         if (msr & FEATURE_CONTROL_LOCKED) {
2207                 /* launched w/ TXT and VMX disabled */
2208                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2209                         && tboot_enabled())
2210                         return 1;
2211                 /* launched w/o TXT and VMX only enabled w/ TXT */
2212                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2213                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2214                         && !tboot_enabled()) {
2215                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2216                                 "activate TXT before enabling KVM\n");
2217                         return 1;
2218                 }
2219                 /* launched w/o TXT and VMX disabled */
2220                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2221                         && !tboot_enabled())
2222                         return 1;
2223         }
2224
2225         return 0;
2226 }
2227
2228 static void kvm_cpu_vmxon(u64 addr)
2229 {
2230         cr4_set_bits(X86_CR4_VMXE);
2231         intel_pt_handle_vmx(1);
2232
2233         asm volatile ("vmxon %0" : : "m"(addr));
2234 }
2235
2236 static int hardware_enable(void)
2237 {
2238         int cpu = raw_smp_processor_id();
2239         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2240         u64 old, test_bits;
2241
2242         if (cr4_read_shadow() & X86_CR4_VMXE)
2243                 return -EBUSY;
2244
2245         /*
2246          * This can happen if we hot-added a CPU but failed to allocate
2247          * VP assist page for it.
2248          */
2249         if (static_branch_unlikely(&enable_evmcs) &&
2250             !hv_get_vp_assist_page(cpu))
2251                 return -EFAULT;
2252
2253         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2254         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
2255         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
2256
2257         /*
2258          * Now we can enable the vmclear operation in kdump
2259          * since the loaded_vmcss_on_cpu list on this cpu
2260          * has been initialized.
2261          *
2262          * Though the cpu is not in VMX operation now, there
2263          * is no problem to enable the vmclear operation
2264          * for the loaded_vmcss_on_cpu list is empty!
2265          */
2266         crash_enable_local_vmclear(cpu);
2267
2268         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2269
2270         test_bits = FEATURE_CONTROL_LOCKED;
2271         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2272         if (tboot_enabled())
2273                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2274
2275         if ((old & test_bits) != test_bits) {
2276                 /* enable and lock */
2277                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2278         }
2279         kvm_cpu_vmxon(phys_addr);
2280         if (enable_ept)
2281                 ept_sync_global();
2282
2283         return 0;
2284 }
2285
2286 static void vmclear_local_loaded_vmcss(void)
2287 {
2288         int cpu = raw_smp_processor_id();
2289         struct loaded_vmcs *v, *n;
2290
2291         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2292                                  loaded_vmcss_on_cpu_link)
2293                 __loaded_vmcs_clear(v);
2294 }
2295
2296
2297 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2298  * tricks.
2299  */
2300 static void kvm_cpu_vmxoff(void)
2301 {
2302         asm volatile (__ex("vmxoff"));
2303
2304         intel_pt_handle_vmx(0);
2305         cr4_clear_bits(X86_CR4_VMXE);
2306 }
2307
2308 static void hardware_disable(void)
2309 {
2310         vmclear_local_loaded_vmcss();
2311         kvm_cpu_vmxoff();
2312 }
2313
2314 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2315                                       u32 msr, u32 *result)
2316 {
2317         u32 vmx_msr_low, vmx_msr_high;
2318         u32 ctl = ctl_min | ctl_opt;
2319
2320         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2321
2322         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2323         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2324
2325         /* Ensure minimum (required) set of control bits are supported. */
2326         if (ctl_min & ~ctl)
2327                 return -EIO;
2328
2329         *result = ctl;
2330         return 0;
2331 }
2332
2333 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2334                                     struct vmx_capability *vmx_cap)
2335 {
2336         u32 vmx_msr_low, vmx_msr_high;
2337         u32 min, opt, min2, opt2;
2338         u32 _pin_based_exec_control = 0;
2339         u32 _cpu_based_exec_control = 0;
2340         u32 _cpu_based_2nd_exec_control = 0;
2341         u32 _vmexit_control = 0;
2342         u32 _vmentry_control = 0;
2343
2344         memset(vmcs_conf, 0, sizeof(*vmcs_conf));
2345         min = CPU_BASED_HLT_EXITING |
2346 #ifdef CONFIG_X86_64
2347               CPU_BASED_CR8_LOAD_EXITING |
2348               CPU_BASED_CR8_STORE_EXITING |
2349 #endif
2350               CPU_BASED_CR3_LOAD_EXITING |
2351               CPU_BASED_CR3_STORE_EXITING |
2352               CPU_BASED_UNCOND_IO_EXITING |
2353               CPU_BASED_MOV_DR_EXITING |
2354               CPU_BASED_USE_TSC_OFFSETING |
2355               CPU_BASED_MWAIT_EXITING |
2356               CPU_BASED_MONITOR_EXITING |
2357               CPU_BASED_INVLPG_EXITING |
2358               CPU_BASED_RDPMC_EXITING;
2359
2360         opt = CPU_BASED_TPR_SHADOW |
2361               CPU_BASED_USE_MSR_BITMAPS |
2362               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2363         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2364                                 &_cpu_based_exec_control) < 0)
2365                 return -EIO;
2366 #ifdef CONFIG_X86_64
2367         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2368                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2369                                            ~CPU_BASED_CR8_STORE_EXITING;
2370 #endif
2371         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2372                 min2 = 0;
2373                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2374                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2375                         SECONDARY_EXEC_WBINVD_EXITING |
2376                         SECONDARY_EXEC_ENABLE_VPID |
2377                         SECONDARY_EXEC_ENABLE_EPT |
2378                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2379                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2380                         SECONDARY_EXEC_DESC |
2381                         SECONDARY_EXEC_RDTSCP |
2382                         SECONDARY_EXEC_ENABLE_INVPCID |
2383                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2384                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2385                         SECONDARY_EXEC_SHADOW_VMCS |
2386                         SECONDARY_EXEC_XSAVES |
2387                         SECONDARY_EXEC_RDSEED_EXITING |
2388                         SECONDARY_EXEC_RDRAND_EXITING |
2389                         SECONDARY_EXEC_ENABLE_PML |
2390                         SECONDARY_EXEC_TSC_SCALING |
2391                         SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
2392                         SECONDARY_EXEC_PT_USE_GPA |
2393                         SECONDARY_EXEC_PT_CONCEAL_VMX |
2394                         SECONDARY_EXEC_ENABLE_VMFUNC |
2395                         SECONDARY_EXEC_ENCLS_EXITING;
2396                 if (adjust_vmx_controls(min2, opt2,
2397                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2398                                         &_cpu_based_2nd_exec_control) < 0)
2399                         return -EIO;
2400         }
2401 #ifndef CONFIG_X86_64
2402         if (!(_cpu_based_2nd_exec_control &
2403                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2404                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2405 #endif
2406
2407         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2408                 _cpu_based_2nd_exec_control &= ~(
2409                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2410                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2411                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2412
2413         rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
2414                 &vmx_cap->ept, &vmx_cap->vpid);
2415
2416         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2417                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2418                    enabled */
2419                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2420                                              CPU_BASED_CR3_STORE_EXITING |
2421                                              CPU_BASED_INVLPG_EXITING);
2422         } else if (vmx_cap->ept) {
2423                 vmx_cap->ept = 0;
2424                 pr_warn_once("EPT CAP should not exist if not support "
2425                                 "1-setting enable EPT VM-execution control\n");
2426         }
2427         if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
2428                 vmx_cap->vpid) {
2429                 vmx_cap->vpid = 0;
2430                 pr_warn_once("VPID CAP should not exist if not support "
2431                                 "1-setting enable VPID VM-execution control\n");
2432         }
2433
2434         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
2435 #ifdef CONFIG_X86_64
2436         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2437 #endif
2438         opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2439               VM_EXIT_LOAD_IA32_PAT |
2440               VM_EXIT_LOAD_IA32_EFER |
2441               VM_EXIT_CLEAR_BNDCFGS |
2442               VM_EXIT_PT_CONCEAL_PIP |
2443               VM_EXIT_CLEAR_IA32_RTIT_CTL;
2444         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2445                                 &_vmexit_control) < 0)
2446                 return -EIO;
2447
2448         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2449         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2450                  PIN_BASED_VMX_PREEMPTION_TIMER;
2451         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2452                                 &_pin_based_exec_control) < 0)
2453                 return -EIO;
2454
2455         if (cpu_has_broken_vmx_preemption_timer())
2456                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2457         if (!(_cpu_based_2nd_exec_control &
2458                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
2459                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2460
2461         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2462         opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2463               VM_ENTRY_LOAD_IA32_PAT |
2464               VM_ENTRY_LOAD_IA32_EFER |
2465               VM_ENTRY_LOAD_BNDCFGS |
2466               VM_ENTRY_PT_CONCEAL_PIP |
2467               VM_ENTRY_LOAD_IA32_RTIT_CTL;
2468         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2469                                 &_vmentry_control) < 0)
2470                 return -EIO;
2471
2472         /*
2473          * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2474          * can't be used due to an errata where VM Exit may incorrectly clear
2475          * IA32_PERF_GLOBAL_CTRL[34:32].  Workaround the errata by using the
2476          * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2477          */
2478         if (boot_cpu_data.x86 == 0x6) {
2479                 switch (boot_cpu_data.x86_model) {
2480                 case 26: /* AAK155 */
2481                 case 30: /* AAP115 */
2482                 case 37: /* AAT100 */
2483                 case 44: /* BC86,AAY89,BD102 */
2484                 case 46: /* BA97 */
2485                         _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
2486                         _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2487                         pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2488                                         "does not work properly. Using workaround\n");
2489                         break;
2490                 default:
2491                         break;
2492                 }
2493         }
2494
2495
2496         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2497
2498         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2499         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2500                 return -EIO;
2501
2502 #ifdef CONFIG_X86_64
2503         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2504         if (vmx_msr_high & (1u<<16))
2505                 return -EIO;
2506 #endif
2507
2508         /* Require Write-Back (WB) memory type for VMCS accesses. */
2509         if (((vmx_msr_high >> 18) & 15) != 6)
2510                 return -EIO;
2511
2512         vmcs_conf->size = vmx_msr_high & 0x1fff;
2513         vmcs_conf->order = get_order(vmcs_conf->size);
2514         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
2515
2516         vmcs_conf->revision_id = vmx_msr_low;
2517
2518         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2519         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2520         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2521         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2522         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2523
2524         if (static_branch_unlikely(&enable_evmcs))
2525                 evmcs_sanitize_exec_ctrls(vmcs_conf);
2526
2527         return 0;
2528 }
2529
2530 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
2531 {
2532         int node = cpu_to_node(cpu);
2533         struct page *pages;
2534         struct vmcs *vmcs;
2535
2536         pages = __alloc_pages_node(node, flags, vmcs_config.order);
2537         if (!pages)
2538                 return NULL;
2539         vmcs = page_address(pages);
2540         memset(vmcs, 0, vmcs_config.size);
2541
2542         /* KVM supports Enlightened VMCS v1 only */
2543         if (static_branch_unlikely(&enable_evmcs))
2544                 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2545         else
2546                 vmcs->hdr.revision_id = vmcs_config.revision_id;
2547
2548         if (shadow)
2549                 vmcs->hdr.shadow_vmcs = 1;
2550         return vmcs;
2551 }
2552
2553 void free_vmcs(struct vmcs *vmcs)
2554 {
2555         free_pages((unsigned long)vmcs, vmcs_config.order);
2556 }
2557
2558 /*
2559  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2560  */
2561 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2562 {
2563         if (!loaded_vmcs->vmcs)
2564                 return;
2565         loaded_vmcs_clear(loaded_vmcs);
2566         free_vmcs(loaded_vmcs->vmcs);
2567         loaded_vmcs->vmcs = NULL;
2568         if (loaded_vmcs->msr_bitmap)
2569                 free_page((unsigned long)loaded_vmcs->msr_bitmap);
2570         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
2571 }
2572
2573 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2574 {
2575         loaded_vmcs->vmcs = alloc_vmcs(false);
2576         if (!loaded_vmcs->vmcs)
2577                 return -ENOMEM;
2578
2579         loaded_vmcs->shadow_vmcs = NULL;
2580         loaded_vmcs->hv_timer_soft_disabled = false;
2581         loaded_vmcs_init(loaded_vmcs);
2582
2583         if (cpu_has_vmx_msr_bitmap()) {
2584                 loaded_vmcs->msr_bitmap = (unsigned long *)
2585                                 __get_free_page(GFP_KERNEL_ACCOUNT);
2586                 if (!loaded_vmcs->msr_bitmap)
2587                         goto out_vmcs;
2588                 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
2589
2590                 if (IS_ENABLED(CONFIG_HYPERV) &&
2591                     static_branch_unlikely(&enable_evmcs) &&
2592                     (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2593                         struct hv_enlightened_vmcs *evmcs =
2594                                 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2595
2596                         evmcs->hv_enlightenments_control.msr_bitmap = 1;
2597                 }
2598         }
2599
2600         memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2601         memset(&loaded_vmcs->controls_shadow, 0,
2602                 sizeof(struct vmcs_controls_shadow));
2603
2604         return 0;
2605
2606 out_vmcs:
2607         free_loaded_vmcs(loaded_vmcs);
2608         return -ENOMEM;
2609 }
2610
2611 static void free_kvm_area(void)
2612 {
2613         int cpu;
2614
2615         for_each_possible_cpu(cpu) {
2616                 free_vmcs(per_cpu(vmxarea, cpu));
2617                 per_cpu(vmxarea, cpu) = NULL;
2618         }
2619 }
2620
2621 static __init int alloc_kvm_area(void)
2622 {
2623         int cpu;
2624
2625         for_each_possible_cpu(cpu) {
2626                 struct vmcs *vmcs;
2627
2628                 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
2629                 if (!vmcs) {
2630                         free_kvm_area();
2631                         return -ENOMEM;
2632                 }
2633
2634                 /*
2635                  * When eVMCS is enabled, alloc_vmcs_cpu() sets
2636                  * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2637                  * revision_id reported by MSR_IA32_VMX_BASIC.
2638                  *
2639                  * However, even though not explicitly documented by
2640                  * TLFS, VMXArea passed as VMXON argument should
2641                  * still be marked with revision_id reported by
2642                  * physical CPU.
2643                  */
2644                 if (static_branch_unlikely(&enable_evmcs))
2645                         vmcs->hdr.revision_id = vmcs_config.revision_id;
2646
2647                 per_cpu(vmxarea, cpu) = vmcs;
2648         }
2649         return 0;
2650 }
2651
2652 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2653                 struct kvm_segment *save)
2654 {
2655         if (!emulate_invalid_guest_state) {
2656                 /*
2657                  * CS and SS RPL should be equal during guest entry according
2658                  * to VMX spec, but in reality it is not always so. Since vcpu
2659                  * is in the middle of the transition from real mode to
2660                  * protected mode it is safe to assume that RPL 0 is a good
2661                  * default value.
2662                  */
2663                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2664                         save->selector &= ~SEGMENT_RPL_MASK;
2665                 save->dpl = save->selector & SEGMENT_RPL_MASK;
2666                 save->s = 1;
2667         }
2668         vmx_set_segment(vcpu, save, seg);
2669 }
2670
2671 static void enter_pmode(struct kvm_vcpu *vcpu)
2672 {
2673         unsigned long flags;
2674         struct vcpu_vmx *vmx = to_vmx(vcpu);
2675
2676         /*
2677          * Update real mode segment cache. It may be not up-to-date if sement
2678          * register was written while vcpu was in a guest mode.
2679          */
2680         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2681         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2682         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2683         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2684         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2685         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2686
2687         vmx->rmode.vm86_active = 0;
2688
2689         vmx_segment_cache_clear(vmx);
2690
2691         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2692
2693         flags = vmcs_readl(GUEST_RFLAGS);
2694         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2695         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2696         vmcs_writel(GUEST_RFLAGS, flags);
2697
2698         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2699                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2700
2701         update_exception_bitmap(vcpu);
2702
2703         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2704         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2705         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2706         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2707         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2708         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2709 }
2710
2711 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2712 {
2713         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2714         struct kvm_segment var = *save;
2715
2716         var.dpl = 0x3;
2717         if (seg == VCPU_SREG_CS)
2718                 var.type = 0x3;
2719
2720         if (!emulate_invalid_guest_state) {
2721                 var.selector = var.base >> 4;
2722                 var.base = var.base & 0xffff0;
2723                 var.limit = 0xffff;
2724                 var.g = 0;
2725                 var.db = 0;
2726                 var.present = 1;
2727                 var.s = 1;
2728                 var.l = 0;
2729                 var.unusable = 0;
2730                 var.type = 0x3;
2731                 var.avl = 0;
2732                 if (save->base & 0xf)
2733                         printk_once(KERN_WARNING "kvm: segment base is not "
2734                                         "paragraph aligned when entering "
2735                                         "protected mode (seg=%d)", seg);
2736         }
2737
2738         vmcs_write16(sf->selector, var.selector);
2739         vmcs_writel(sf->base, var.base);
2740         vmcs_write32(sf->limit, var.limit);
2741         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2742 }
2743
2744 static void enter_rmode(struct kvm_vcpu *vcpu)
2745 {
2746         unsigned long flags;
2747         struct vcpu_vmx *vmx = to_vmx(vcpu);
2748         struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
2749
2750         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2751         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2752         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2753         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2754         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2755         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2756         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2757
2758         vmx->rmode.vm86_active = 1;
2759
2760         /*
2761          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2762          * vcpu. Warn the user that an update is overdue.
2763          */
2764         if (!kvm_vmx->tss_addr)
2765                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2766                              "called before entering vcpu\n");
2767
2768         vmx_segment_cache_clear(vmx);
2769
2770         vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
2771         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2772         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2773
2774         flags = vmcs_readl(GUEST_RFLAGS);
2775         vmx->rmode.save_rflags = flags;
2776
2777         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2778
2779         vmcs_writel(GUEST_RFLAGS, flags);
2780         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2781         update_exception_bitmap(vcpu);
2782
2783         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2784         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2785         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2786         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2787         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2788         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2789
2790         kvm_mmu_reset_context(vcpu);
2791 }
2792
2793 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2794 {
2795         struct vcpu_vmx *vmx = to_vmx(vcpu);
2796         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2797
2798         if (!msr)
2799                 return;
2800
2801         vcpu->arch.efer = efer;
2802         if (efer & EFER_LMA) {
2803                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2804                 msr->data = efer;
2805         } else {
2806                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2807
2808                 msr->data = efer & ~EFER_LME;
2809         }
2810         setup_msrs(vmx);
2811 }
2812
2813 #ifdef CONFIG_X86_64
2814
2815 static void enter_lmode(struct kvm_vcpu *vcpu)
2816 {
2817         u32 guest_tr_ar;
2818
2819         vmx_segment_cache_clear(to_vmx(vcpu));
2820
2821         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2822         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
2823                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2824                                      __func__);
2825                 vmcs_write32(GUEST_TR_AR_BYTES,
2826                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2827                              | VMX_AR_TYPE_BUSY_64_TSS);
2828         }
2829         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2830 }
2831
2832 static void exit_lmode(struct kvm_vcpu *vcpu)
2833 {
2834         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2835         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2836 }
2837
2838 #endif
2839
2840 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2841 {
2842         int vpid = to_vmx(vcpu)->vpid;
2843
2844         if (!vpid_sync_vcpu_addr(vpid, addr))
2845                 vpid_sync_context(vpid);
2846
2847         /*
2848          * If VPIDs are not supported or enabled, then the above is a no-op.
2849          * But we don't really need a TLB flush in that case anyway, because
2850          * each VM entry/exit includes an implicit flush when VPID is 0.
2851          */
2852 }
2853
2854 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2855 {
2856         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2857
2858         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2859         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2860 }
2861
2862 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2863 {
2864         if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
2865                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2866         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2867 }
2868
2869 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2870 {
2871         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2872
2873         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2874         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2875 }
2876
2877 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2878 {
2879         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2880
2881         if (!test_bit(VCPU_EXREG_PDPTR,
2882                       (unsigned long *)&vcpu->arch.regs_dirty))
2883                 return;
2884
2885         if (is_pae_paging(vcpu)) {
2886                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2887                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2888                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2889                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
2890         }
2891 }
2892
2893 void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2894 {
2895         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2896
2897         if (is_pae_paging(vcpu)) {
2898                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2899                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2900                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2901                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2902         }
2903
2904         __set_bit(VCPU_EXREG_PDPTR,
2905                   (unsigned long *)&vcpu->arch.regs_avail);
2906         __set_bit(VCPU_EXREG_PDPTR,
2907                   (unsigned long *)&vcpu->arch.regs_dirty);
2908 }
2909
2910 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2911                                         unsigned long cr0,
2912                                         struct kvm_vcpu *vcpu)
2913 {
2914         struct vcpu_vmx *vmx = to_vmx(vcpu);
2915
2916         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2917                 vmx_decache_cr3(vcpu);
2918         if (!(cr0 & X86_CR0_PG)) {
2919                 /* From paging/starting to nonpaging */
2920                 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2921                                           CPU_BASED_CR3_STORE_EXITING);
2922                 vcpu->arch.cr0 = cr0;
2923                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2924         } else if (!is_paging(vcpu)) {
2925                 /* From nonpaging to paging */
2926                 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2927                                             CPU_BASED_CR3_STORE_EXITING);
2928                 vcpu->arch.cr0 = cr0;
2929                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2930         }
2931
2932         if (!(cr0 & X86_CR0_WP))
2933                 *hw_cr0 &= ~X86_CR0_WP;
2934 }
2935
2936 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2937 {
2938         struct vcpu_vmx *vmx = to_vmx(vcpu);
2939         unsigned long hw_cr0;
2940
2941         hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
2942         if (enable_unrestricted_guest)
2943                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2944         else {
2945                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
2946
2947                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2948                         enter_pmode(vcpu);
2949
2950                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2951                         enter_rmode(vcpu);
2952         }
2953
2954 #ifdef CONFIG_X86_64
2955         if (vcpu->arch.efer & EFER_LME) {
2956                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2957                         enter_lmode(vcpu);
2958                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2959                         exit_lmode(vcpu);
2960         }
2961 #endif
2962
2963         if (enable_ept && !enable_unrestricted_guest)
2964                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2965
2966         vmcs_writel(CR0_READ_SHADOW, cr0);
2967         vmcs_writel(GUEST_CR0, hw_cr0);
2968         vcpu->arch.cr0 = cr0;
2969
2970         /* depends on vcpu->arch.cr0 to be set to a new value */
2971         vmx->emulation_required = emulation_required(vcpu);
2972 }
2973
2974 static int get_ept_level(struct kvm_vcpu *vcpu)
2975 {
2976         if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
2977                 return 5;
2978         return 4;
2979 }
2980
2981 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
2982 {
2983         u64 eptp = VMX_EPTP_MT_WB;
2984
2985         eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
2986
2987         if (enable_ept_ad_bits &&
2988             (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
2989                 eptp |= VMX_EPTP_AD_ENABLE_BIT;
2990         eptp |= (root_hpa & PAGE_MASK);
2991
2992         return eptp;
2993 }
2994
2995 void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2996 {
2997         struct kvm *kvm = vcpu->kvm;
2998         bool update_guest_cr3 = true;
2999         unsigned long guest_cr3;
3000         u64 eptp;
3001
3002         guest_cr3 = cr3;
3003         if (enable_ept) {
3004                 eptp = construct_eptp(vcpu, cr3);
3005                 vmcs_write64(EPT_POINTER, eptp);
3006
3007                 if (kvm_x86_ops->tlb_remote_flush) {
3008                         spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3009                         to_vmx(vcpu)->ept_pointer = eptp;
3010                         to_kvm_vmx(kvm)->ept_pointers_match
3011                                 = EPT_POINTERS_CHECK;
3012                         spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3013                 }
3014
3015                 /* Loading vmcs02.GUEST_CR3 is handled by nested VM-Enter. */
3016                 if (is_guest_mode(vcpu))
3017                         update_guest_cr3 = false;
3018                 else if (enable_unrestricted_guest || is_paging(vcpu))
3019                         guest_cr3 = kvm_read_cr3(vcpu);
3020                 else
3021                         guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
3022                 ept_load_pdptrs(vcpu);
3023         }
3024
3025         if (update_guest_cr3)
3026                 vmcs_writel(GUEST_CR3, guest_cr3);
3027 }
3028
3029 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3030 {
3031         struct vcpu_vmx *vmx = to_vmx(vcpu);
3032         /*
3033          * Pass through host's Machine Check Enable value to hw_cr4, which
3034          * is in force while we are in guest mode.  Do not let guests control
3035          * this bit, even if host CR4.MCE == 0.
3036          */
3037         unsigned long hw_cr4;
3038
3039         hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
3040         if (enable_unrestricted_guest)
3041                 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
3042         else if (vmx->rmode.vm86_active)
3043                 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
3044         else
3045                 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
3046
3047         if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
3048                 if (cr4 & X86_CR4_UMIP) {
3049                         secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
3050                         hw_cr4 &= ~X86_CR4_UMIP;
3051                 } else if (!is_guest_mode(vcpu) ||
3052                         !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
3053                         secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
3054                 }
3055         }
3056
3057         if (cr4 & X86_CR4_VMXE) {
3058                 /*
3059                  * To use VMXON (and later other VMX instructions), a guest
3060                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3061                  * So basically the check on whether to allow nested VMX
3062                  * is here.  We operate under the default treatment of SMM,
3063                  * so VMX cannot be enabled under SMM.
3064                  */
3065                 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
3066                         return 1;
3067         }
3068
3069         if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
3070                 return 1;
3071
3072         vcpu->arch.cr4 = cr4;
3073
3074         if (!enable_unrestricted_guest) {
3075                 if (enable_ept) {
3076                         if (!is_paging(vcpu)) {
3077                                 hw_cr4 &= ~X86_CR4_PAE;
3078                                 hw_cr4 |= X86_CR4_PSE;
3079                         } else if (!(cr4 & X86_CR4_PAE)) {
3080                                 hw_cr4 &= ~X86_CR4_PAE;
3081                         }
3082                 }
3083
3084                 /*
3085                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3086                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
3087                  * to be manually disabled when guest switches to non-paging
3088                  * mode.
3089                  *
3090                  * If !enable_unrestricted_guest, the CPU is always running
3091                  * with CR0.PG=1 and CR4 needs to be modified.
3092                  * If enable_unrestricted_guest, the CPU automatically
3093                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3094                  */
3095                 if (!is_paging(vcpu))
3096                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3097         }
3098
3099         vmcs_writel(CR4_READ_SHADOW, cr4);
3100         vmcs_writel(GUEST_CR4, hw_cr4);
3101         return 0;
3102 }
3103
3104 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3105 {
3106         struct vcpu_vmx *vmx = to_vmx(vcpu);
3107         u32 ar;
3108
3109         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3110                 *var = vmx->rmode.segs[seg];
3111                 if (seg == VCPU_SREG_TR
3112                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3113                         return;
3114                 var->base = vmx_read_guest_seg_base(vmx, seg);
3115                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3116                 return;
3117         }
3118         var->base = vmx_read_guest_seg_base(vmx, seg);
3119         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3120         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3121         ar = vmx_read_guest_seg_ar(vmx, seg);
3122         var->unusable = (ar >> 16) & 1;
3123         var->type = ar & 15;
3124         var->s = (ar >> 4) & 1;
3125         var->dpl = (ar >> 5) & 3;
3126         /*
3127          * Some userspaces do not preserve unusable property. Since usable
3128          * segment has to be present according to VMX spec we can use present
3129          * property to amend userspace bug by making unusable segment always
3130          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3131          * segment as unusable.
3132          */
3133         var->present = !var->unusable;
3134         var->avl = (ar >> 12) & 1;
3135         var->l = (ar >> 13) & 1;
3136         var->db = (ar >> 14) & 1;
3137         var->g = (ar >> 15) & 1;
3138 }
3139
3140 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3141 {
3142         struct kvm_segment s;
3143
3144         if (to_vmx(vcpu)->rmode.vm86_active) {
3145                 vmx_get_segment(vcpu, &s, seg);
3146                 return s.base;
3147         }
3148         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3149 }
3150
3151 int vmx_get_cpl(struct kvm_vcpu *vcpu)
3152 {
3153         struct vcpu_vmx *vmx = to_vmx(vcpu);
3154
3155         if (unlikely(vmx->rmode.vm86_active))
3156                 return 0;
3157         else {
3158                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3159                 return VMX_AR_DPL(ar);
3160         }
3161 }
3162
3163 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3164 {
3165         u32 ar;
3166
3167         if (var->unusable || !var->present)
3168                 ar = 1 << 16;
3169         else {
3170                 ar = var->type & 15;
3171                 ar |= (var->s & 1) << 4;
3172                 ar |= (var->dpl & 3) << 5;
3173                 ar |= (var->present & 1) << 7;
3174                 ar |= (var->avl & 1) << 12;
3175                 ar |= (var->l & 1) << 13;
3176                 ar |= (var->db & 1) << 14;
3177                 ar |= (var->g & 1) << 15;
3178         }
3179
3180         return ar;
3181 }
3182
3183 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3184 {
3185         struct vcpu_vmx *vmx = to_vmx(vcpu);
3186         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3187
3188         vmx_segment_cache_clear(vmx);
3189
3190         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3191                 vmx->rmode.segs[seg] = *var;
3192                 if (seg == VCPU_SREG_TR)
3193                         vmcs_write16(sf->selector, var->selector);
3194                 else if (var->s)
3195                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3196                 goto out;
3197         }
3198
3199         vmcs_writel(sf->base, var->base);
3200         vmcs_write32(sf->limit, var->limit);
3201         vmcs_write16(sf->selector, var->selector);
3202
3203         /*
3204          *   Fix the "Accessed" bit in AR field of segment registers for older
3205          * qemu binaries.
3206          *   IA32 arch specifies that at the time of processor reset the
3207          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3208          * is setting it to 0 in the userland code. This causes invalid guest
3209          * state vmexit when "unrestricted guest" mode is turned on.
3210          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3211          * tree. Newer qemu binaries with that qemu fix would not need this
3212          * kvm hack.
3213          */
3214         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3215                 var->type |= 0x1; /* Accessed */
3216
3217         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3218
3219 out:
3220         vmx->emulation_required = emulation_required(vcpu);
3221 }
3222
3223 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3224 {
3225         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3226
3227         *db = (ar >> 14) & 1;
3228         *l = (ar >> 13) & 1;
3229 }
3230
3231 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3232 {
3233         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3234         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3235 }
3236
3237 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3238 {
3239         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3240         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3241 }
3242
3243 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3244 {
3245         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3246         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3247 }
3248
3249 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3250 {
3251         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3252         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3253 }
3254
3255 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3256 {
3257         struct kvm_segment var;
3258         u32 ar;
3259
3260         vmx_get_segment(vcpu, &var, seg);
3261         var.dpl = 0x3;
3262         if (seg == VCPU_SREG_CS)
3263                 var.type = 0x3;
3264         ar = vmx_segment_access_rights(&var);
3265
3266         if (var.base != (var.selector << 4))
3267                 return false;
3268         if (var.limit != 0xffff)
3269                 return false;
3270         if (ar != 0xf3)
3271                 return false;
3272
3273         return true;
3274 }
3275
3276 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3277 {
3278         struct kvm_segment cs;
3279         unsigned int cs_rpl;
3280
3281         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3282         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3283
3284         if (cs.unusable)
3285                 return false;
3286         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3287                 return false;
3288         if (!cs.s)
3289                 return false;
3290         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3291                 if (cs.dpl > cs_rpl)
3292                         return false;
3293         } else {
3294                 if (cs.dpl != cs_rpl)
3295                         return false;
3296         }
3297         if (!cs.present)
3298                 return false;
3299
3300         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3301         return true;
3302 }
3303
3304 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3305 {
3306         struct kvm_segment ss;
3307         unsigned int ss_rpl;
3308
3309         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3310         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3311
3312         if (ss.unusable)
3313                 return true;
3314         if (ss.type != 3 && ss.type != 7)
3315                 return false;
3316         if (!ss.s)
3317                 return false;
3318         if (ss.dpl != ss_rpl) /* DPL != RPL */
3319                 return false;
3320         if (!ss.present)
3321                 return false;
3322
3323         return true;
3324 }
3325
3326 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3327 {
3328         struct kvm_segment var;
3329         unsigned int rpl;
3330
3331         vmx_get_segment(vcpu, &var, seg);
3332         rpl = var.selector & SEGMENT_RPL_MASK;
3333
3334         if (var.unusable)
3335                 return true;
3336         if (!var.s)
3337                 return false;
3338         if (!var.present)
3339                 return false;
3340         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
3341                 if (var.dpl < rpl) /* DPL < RPL */
3342                         return false;
3343         }
3344
3345         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3346          * rights flags
3347          */
3348         return true;
3349 }
3350
3351 static bool tr_valid(struct kvm_vcpu *vcpu)
3352 {
3353         struct kvm_segment tr;
3354
3355         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3356
3357         if (tr.unusable)
3358                 return false;
3359         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
3360                 return false;
3361         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3362                 return false;
3363         if (!tr.present)
3364                 return false;
3365
3366         return true;
3367 }
3368
3369 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3370 {
3371         struct kvm_segment ldtr;
3372
3373         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3374
3375         if (ldtr.unusable)
3376                 return true;
3377         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
3378                 return false;
3379         if (ldtr.type != 2)
3380                 return false;
3381         if (!ldtr.present)
3382                 return false;
3383
3384         return true;
3385 }
3386
3387 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3388 {
3389         struct kvm_segment cs, ss;
3390
3391         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3392         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3393
3394         return ((cs.selector & SEGMENT_RPL_MASK) ==
3395                  (ss.selector & SEGMENT_RPL_MASK));
3396 }
3397
3398 /*
3399  * Check if guest state is valid. Returns true if valid, false if
3400  * not.
3401  * We assume that registers are always usable
3402  */
3403 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3404 {
3405         if (enable_unrestricted_guest)
3406                 return true;
3407
3408         /* real mode guest state checks */
3409         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3410                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3411                         return false;
3412                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3413                         return false;
3414                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3415                         return false;
3416                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3417                         return false;
3418                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3419                         return false;
3420                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3421                         return false;
3422         } else {
3423         /* protected mode guest state checks */
3424                 if (!cs_ss_rpl_check(vcpu))
3425                         return false;
3426                 if (!code_segment_valid(vcpu))
3427                         return false;
3428                 if (!stack_segment_valid(vcpu))
3429                         return false;
3430                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3431                         return false;
3432                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3433                         return false;
3434                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3435                         return false;
3436                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3437                         return false;
3438                 if (!tr_valid(vcpu))
3439                         return false;
3440                 if (!ldtr_valid(vcpu))
3441                         return false;
3442         }
3443         /* TODO:
3444          * - Add checks on RIP
3445          * - Add checks on RFLAGS
3446          */
3447
3448         return true;
3449 }
3450
3451 static int init_rmode_tss(struct kvm *kvm)
3452 {
3453         gfn_t fn;
3454         u16 data = 0;
3455         int idx, r;
3456
3457         idx = srcu_read_lock(&kvm->srcu);
3458         fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
3459         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3460         if (r < 0)
3461                 goto out;
3462         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3463         r = kvm_write_guest_page(kvm, fn++, &data,
3464                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3465         if (r < 0)
3466                 goto out;
3467         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3468         if (r < 0)
3469                 goto out;
3470         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3471         if (r < 0)
3472                 goto out;
3473         data = ~0;
3474         r = kvm_write_guest_page(kvm, fn, &data,
3475                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3476                                  sizeof(u8));
3477 out:
3478         srcu_read_unlock(&kvm->srcu, idx);
3479         return r;
3480 }
3481
3482 static int init_rmode_identity_map(struct kvm *kvm)
3483 {
3484         struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
3485         int i, idx, r = 0;
3486         kvm_pfn_t identity_map_pfn;
3487         u32 tmp;
3488
3489         /* Protect kvm_vmx->ept_identity_pagetable_done. */
3490         mutex_lock(&kvm->slots_lock);
3491
3492         if (likely(kvm_vmx->ept_identity_pagetable_done))
3493                 goto out2;
3494
3495         if (!kvm_vmx->ept_identity_map_addr)
3496                 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3497         identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
3498
3499         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
3500                                     kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
3501         if (r < 0)
3502                 goto out2;
3503
3504         idx = srcu_read_lock(&kvm->srcu);
3505         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3506         if (r < 0)
3507                 goto out;
3508         /* Set up identity-mapping pagetable for EPT in real mode */
3509         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3510                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3511                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3512                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3513                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3514                 if (r < 0)
3515                         goto out;
3516         }
3517         kvm_vmx->ept_identity_pagetable_done = true;
3518
3519 out:
3520         srcu_read_unlock(&kvm->srcu, idx);
3521
3522 out2:
3523         mutex_unlock(&kvm->slots_lock);
3524         return r;
3525 }
3526
3527 static void seg_setup(int seg)
3528 {
3529         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3530         unsigned int ar;
3531
3532         vmcs_write16(sf->selector, 0);
3533         vmcs_writel(sf->base, 0);
3534         vmcs_write32(sf->limit, 0xffff);
3535         ar = 0x93;
3536         if (seg == VCPU_SREG_CS)
3537                 ar |= 0x08; /* code segment */
3538
3539         vmcs_write32(sf->ar_bytes, ar);
3540 }
3541
3542 static int alloc_apic_access_page(struct kvm *kvm)
3543 {
3544         struct page *page;
3545         int r = 0;
3546
3547         mutex_lock(&kvm->slots_lock);
3548         if (kvm->arch.apic_access_page_done)
3549                 goto out;
3550         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3551                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
3552         if (r)
3553                 goto out;
3554
3555         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
3556         if (is_error_page(page)) {
3557                 r = -EFAULT;
3558                 goto out;
3559         }
3560
3561         /*
3562          * Do not pin the page in memory, so that memory hot-unplug
3563          * is able to migrate it.
3564          */
3565         put_page(page);
3566         kvm->arch.apic_access_page_done = true;
3567 out:
3568         mutex_unlock(&kvm->slots_lock);
3569         return r;
3570 }
3571
3572 int allocate_vpid(void)
3573 {
3574         int vpid;
3575
3576         if (!enable_vpid)
3577                 return 0;
3578         spin_lock(&vmx_vpid_lock);
3579         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3580         if (vpid < VMX_NR_VPIDS)
3581                 __set_bit(vpid, vmx_vpid_bitmap);
3582         else
3583                 vpid = 0;
3584         spin_unlock(&vmx_vpid_lock);
3585         return vpid;
3586 }
3587
3588 void free_vpid(int vpid)
3589 {
3590         if (!enable_vpid || vpid == 0)
3591                 return;
3592         spin_lock(&vmx_vpid_lock);
3593         __clear_bit(vpid, vmx_vpid_bitmap);
3594         spin_unlock(&vmx_vpid_lock);
3595 }
3596
3597 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3598                                                           u32 msr, int type)
3599 {
3600         int f = sizeof(unsigned long);
3601
3602         if (!cpu_has_vmx_msr_bitmap())
3603                 return;
3604
3605         if (static_branch_unlikely(&enable_evmcs))
3606                 evmcs_touch_msr_bitmap();
3607
3608         /*
3609          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3610          * have the write-low and read-high bitmap offsets the wrong way round.
3611          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3612          */
3613         if (msr <= 0x1fff) {
3614                 if (type & MSR_TYPE_R)
3615                         /* read-low */
3616                         __clear_bit(msr, msr_bitmap + 0x000 / f);
3617
3618                 if (type & MSR_TYPE_W)
3619                         /* write-low */
3620                         __clear_bit(msr, msr_bitmap + 0x800 / f);
3621
3622         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3623                 msr &= 0x1fff;
3624                 if (type & MSR_TYPE_R)
3625                         /* read-high */
3626                         __clear_bit(msr, msr_bitmap + 0x400 / f);
3627
3628                 if (type & MSR_TYPE_W)
3629                         /* write-high */
3630                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
3631
3632         }
3633 }
3634
3635 static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3636                                                          u32 msr, int type)
3637 {
3638         int f = sizeof(unsigned long);
3639
3640         if (!cpu_has_vmx_msr_bitmap())
3641                 return;
3642
3643         if (static_branch_unlikely(&enable_evmcs))
3644                 evmcs_touch_msr_bitmap();
3645
3646         /*
3647          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3648          * have the write-low and read-high bitmap offsets the wrong way round.
3649          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3650          */
3651         if (msr <= 0x1fff) {
3652                 if (type & MSR_TYPE_R)
3653                         /* read-low */
3654                         __set_bit(msr, msr_bitmap + 0x000 / f);
3655
3656                 if (type & MSR_TYPE_W)
3657                         /* write-low */
3658                         __set_bit(msr, msr_bitmap + 0x800 / f);
3659
3660         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3661                 msr &= 0x1fff;
3662                 if (type & MSR_TYPE_R)
3663                         /* read-high */
3664                         __set_bit(msr, msr_bitmap + 0x400 / f);
3665
3666                 if (type & MSR_TYPE_W)
3667                         /* write-high */
3668                         __set_bit(msr, msr_bitmap + 0xc00 / f);
3669
3670         }
3671 }
3672
3673 static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
3674                                                       u32 msr, int type, bool value)
3675 {
3676         if (value)
3677                 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
3678         else
3679                 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
3680 }
3681
3682 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
3683 {
3684         u8 mode = 0;
3685
3686         if (cpu_has_secondary_exec_ctrls() &&
3687             (secondary_exec_controls_get(to_vmx(vcpu)) &
3688              SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3689                 mode |= MSR_BITMAP_MODE_X2APIC;
3690                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3691                         mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3692         }
3693
3694         return mode;
3695 }
3696
3697 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
3698                                          u8 mode)
3699 {
3700         int msr;
3701
3702         for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3703                 unsigned word = msr / BITS_PER_LONG;
3704                 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3705                 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
3706         }
3707
3708         if (mode & MSR_BITMAP_MODE_X2APIC) {
3709                 /*
3710                  * TPR reads and writes can be virtualized even if virtual interrupt
3711                  * delivery is not in use.
3712                  */
3713                 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
3714                 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3715                         vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
3716                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3717                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3718                 }
3719         }
3720 }
3721
3722 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
3723 {
3724         struct vcpu_vmx *vmx = to_vmx(vcpu);
3725         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3726         u8 mode = vmx_msr_bitmap_mode(vcpu);
3727         u8 changed = mode ^ vmx->msr_bitmap_mode;
3728
3729         if (!changed)
3730                 return;
3731
3732         if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
3733                 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
3734
3735         vmx->msr_bitmap_mode = mode;
3736 }
3737
3738 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx)
3739 {
3740         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3741         bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3742         u32 i;
3743
3744         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS,
3745                                                         MSR_TYPE_RW, flag);
3746         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE,
3747                                                         MSR_TYPE_RW, flag);
3748         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK,
3749                                                         MSR_TYPE_RW, flag);
3750         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH,
3751                                                         MSR_TYPE_RW, flag);
3752         for (i = 0; i < vmx->pt_desc.addr_range; i++) {
3753                 vmx_set_intercept_for_msr(msr_bitmap,
3754                         MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3755                 vmx_set_intercept_for_msr(msr_bitmap,
3756                         MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3757         }
3758 }
3759
3760 static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu)
3761 {
3762         return enable_apicv;
3763 }
3764
3765 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3766 {
3767         struct vcpu_vmx *vmx = to_vmx(vcpu);
3768         void *vapic_page;
3769         u32 vppr;
3770         int rvi;
3771
3772         if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3773                 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
3774                 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
3775                 return false;
3776
3777         rvi = vmx_get_rvi();
3778
3779         vapic_page = vmx->nested.virtual_apic_map.hva;
3780         vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
3781
3782         return ((rvi & 0xf0) > (vppr & 0xf0));
3783 }
3784
3785 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3786                                                      bool nested)
3787 {
3788 #ifdef CONFIG_SMP
3789         int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3790
3791         if (vcpu->mode == IN_GUEST_MODE) {
3792                 /*
3793                  * The vector of interrupt to be delivered to vcpu had
3794                  * been set in PIR before this function.
3795                  *
3796                  * Following cases will be reached in this block, and
3797                  * we always send a notification event in all cases as
3798                  * explained below.
3799                  *
3800                  * Case 1: vcpu keeps in non-root mode. Sending a
3801                  * notification event posts the interrupt to vcpu.
3802                  *
3803                  * Case 2: vcpu exits to root mode and is still
3804                  * runnable. PIR will be synced to vIRR before the
3805                  * next vcpu entry. Sending a notification event in
3806                  * this case has no effect, as vcpu is not in root
3807                  * mode.
3808                  *
3809                  * Case 3: vcpu exits to root mode and is blocked.
3810                  * vcpu_block() has already synced PIR to vIRR and
3811                  * never blocks vcpu if vIRR is not cleared. Therefore,
3812                  * a blocked vcpu here does not wait for any requested
3813                  * interrupts in PIR, and sending a notification event
3814                  * which has no effect is safe here.
3815                  */
3816
3817                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
3818                 return true;
3819         }
3820 #endif
3821         return false;
3822 }
3823
3824 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3825                                                 int vector)
3826 {
3827         struct vcpu_vmx *vmx = to_vmx(vcpu);
3828
3829         if (is_guest_mode(vcpu) &&
3830             vector == vmx->nested.posted_intr_nv) {
3831                 /*
3832                  * If a posted intr is not recognized by hardware,
3833                  * we will accomplish it in the next vmentry.
3834                  */
3835                 vmx->nested.pi_pending = true;
3836                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3837                 /* the PIR and ON have been set by L1. */
3838                 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3839                         kvm_vcpu_kick(vcpu);
3840                 return 0;
3841         }
3842         return -1;
3843 }
3844 /*
3845  * Send interrupt to vcpu via posted interrupt way.
3846  * 1. If target vcpu is running(non-root mode), send posted interrupt
3847  * notification to vcpu and hardware will sync PIR to vIRR atomically.
3848  * 2. If target vcpu isn't running(root mode), kick it to pick up the
3849  * interrupt from PIR in next vmentry.
3850  */
3851 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3852 {
3853         struct vcpu_vmx *vmx = to_vmx(vcpu);
3854         int r;
3855
3856         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3857         if (!r)
3858                 return;
3859
3860         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
3861                 return;
3862
3863         /* If a previous notification has sent the IPI, nothing to do.  */
3864         if (pi_test_and_set_on(&vmx->pi_desc))
3865                 return;
3866
3867         if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
3868                 kvm_vcpu_kick(vcpu);
3869 }
3870
3871 /*
3872  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3873  * will not change in the lifetime of the guest.
3874  * Note that host-state that does change is set elsewhere. E.g., host-state
3875  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3876  */
3877 void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
3878 {
3879         u32 low32, high32;
3880         unsigned long tmpl;
3881         unsigned long cr0, cr3, cr4;
3882
3883         cr0 = read_cr0();
3884         WARN_ON(cr0 & X86_CR0_TS);
3885         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
3886
3887         /*
3888          * Save the most likely value for this task's CR3 in the VMCS.
3889          * We can't use __get_current_cr3_fast() because we're not atomic.
3890          */
3891         cr3 = __read_cr3();
3892         vmcs_writel(HOST_CR3, cr3);             /* 22.2.3  FIXME: shadow tables */
3893         vmx->loaded_vmcs->host_state.cr3 = cr3;
3894
3895         /* Save the most likely value for this task's CR4 in the VMCS. */
3896         cr4 = cr4_read_shadow();
3897         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
3898         vmx->loaded_vmcs->host_state.cr4 = cr4;
3899
3900         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
3901 #ifdef CONFIG_X86_64
3902         /*
3903          * Load null selectors, so we can avoid reloading them in
3904          * vmx_prepare_switch_to_host(), in case userspace uses
3905          * the null selectors too (the expected case).
3906          */
3907         vmcs_write16(HOST_DS_SELECTOR, 0);
3908         vmcs_write16(HOST_ES_SELECTOR, 0);
3909 #else
3910         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3911         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3912 #endif
3913         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3914         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
3915
3916         vmcs_writel(HOST_IDTR_BASE, host_idt_base);   /* 22.2.4 */
3917
3918         vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
3919
3920         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3921         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3922         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3923         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
3924
3925         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3926                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3927                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3928         }
3929
3930         if (cpu_has_load_ia32_efer())
3931                 vmcs_write64(HOST_IA32_EFER, host_efer);
3932 }
3933
3934 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3935 {
3936         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3937         if (enable_ept)
3938                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3939         if (is_guest_mode(&vmx->vcpu))
3940                 vmx->vcpu.arch.cr4_guest_owned_bits &=
3941                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3942         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3943 }
3944
3945 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
3946 {
3947         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
3948
3949         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
3950                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
3951
3952         if (!enable_vnmi)
3953                 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
3954
3955         if (!enable_preemption_timer)
3956                 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3957
3958         return pin_based_exec_ctrl;
3959 }
3960
3961 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
3962 {
3963         struct vcpu_vmx *vmx = to_vmx(vcpu);
3964
3965         pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
3966         if (cpu_has_secondary_exec_ctrls()) {
3967                 if (kvm_vcpu_apicv_active(vcpu))
3968                         secondary_exec_controls_setbit(vmx,
3969                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
3970                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3971                 else
3972                         secondary_exec_controls_clearbit(vmx,
3973                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3974                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3975         }
3976
3977         if (cpu_has_vmx_msr_bitmap())
3978                 vmx_update_msr_bitmap(vcpu);
3979 }
3980
3981 u32 vmx_exec_control(struct vcpu_vmx *vmx)
3982 {
3983         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3984
3985         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
3986                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
3987
3988         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
3989                 exec_control &= ~CPU_BASED_TPR_SHADOW;
3990 #ifdef CONFIG_X86_64
3991                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3992                                 CPU_BASED_CR8_LOAD_EXITING;
3993 #endif
3994         }
3995         if (!enable_ept)
3996                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3997                                 CPU_BASED_CR3_LOAD_EXITING  |
3998                                 CPU_BASED_INVLPG_EXITING;
3999         if (kvm_mwait_in_guest(vmx->vcpu.kvm))
4000                 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
4001                                 CPU_BASED_MONITOR_EXITING);
4002         if (kvm_hlt_in_guest(vmx->vcpu.kvm))
4003                 exec_control &= ~CPU_BASED_HLT_EXITING;
4004         return exec_control;
4005 }
4006
4007
4008 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
4009 {
4010         struct kvm_vcpu *vcpu = &vmx->vcpu;
4011
4012         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4013
4014         if (pt_mode == PT_MODE_SYSTEM)
4015                 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
4016         if (!cpu_need_virtualize_apic_accesses(vcpu))
4017                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4018         if (vmx->vpid == 0)
4019                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4020         if (!enable_ept) {
4021                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4022                 enable_unrestricted_guest = 0;
4023         }
4024         if (!enable_unrestricted_guest)
4025                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4026         if (kvm_pause_in_guest(vmx->vcpu.kvm))
4027                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4028         if (!kvm_vcpu_apicv_active(vcpu))
4029                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4030                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4031         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4032
4033         /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
4034          * in vmx_set_cr4.  */
4035         exec_control &= ~SECONDARY_EXEC_DESC;
4036
4037         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4038            (handle_vmptrld).
4039            We can NOT enable shadow_vmcs here because we don't have yet
4040            a current VMCS12
4041         */
4042         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4043
4044         if (!enable_pml)
4045                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4046
4047         if (vmx_xsaves_supported()) {
4048                 /* Exposing XSAVES only when XSAVE is exposed */
4049                 bool xsaves_enabled =
4050                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4051                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
4052
4053                 if (!xsaves_enabled)
4054                         exec_control &= ~SECONDARY_EXEC_XSAVES;
4055
4056                 if (nested) {
4057                         if (xsaves_enabled)
4058                                 vmx->nested.msrs.secondary_ctls_high |=
4059                                         SECONDARY_EXEC_XSAVES;
4060                         else
4061                                 vmx->nested.msrs.secondary_ctls_high &=
4062                                         ~SECONDARY_EXEC_XSAVES;
4063                 }
4064         }
4065
4066         if (vmx_rdtscp_supported()) {
4067                 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
4068                 if (!rdtscp_enabled)
4069                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
4070
4071                 if (nested) {
4072                         if (rdtscp_enabled)
4073                                 vmx->nested.msrs.secondary_ctls_high |=
4074                                         SECONDARY_EXEC_RDTSCP;
4075                         else
4076                                 vmx->nested.msrs.secondary_ctls_high &=
4077                                         ~SECONDARY_EXEC_RDTSCP;
4078                 }
4079         }
4080
4081         if (vmx_invpcid_supported()) {
4082                 /* Exposing INVPCID only when PCID is exposed */
4083                 bool invpcid_enabled =
4084                         guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
4085                         guest_cpuid_has(vcpu, X86_FEATURE_PCID);
4086
4087                 if (!invpcid_enabled) {
4088                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4089                         guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
4090                 }
4091
4092                 if (nested) {
4093                         if (invpcid_enabled)
4094                                 vmx->nested.msrs.secondary_ctls_high |=
4095                                         SECONDARY_EXEC_ENABLE_INVPCID;
4096                         else
4097                                 vmx->nested.msrs.secondary_ctls_high &=
4098                                         ~SECONDARY_EXEC_ENABLE_INVPCID;
4099                 }
4100         }
4101
4102         if (vmx_rdrand_supported()) {
4103                 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
4104                 if (rdrand_enabled)
4105                         exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
4106
4107                 if (nested) {
4108                         if (rdrand_enabled)
4109                                 vmx->nested.msrs.secondary_ctls_high |=
4110                                         SECONDARY_EXEC_RDRAND_EXITING;
4111                         else
4112                                 vmx->nested.msrs.secondary_ctls_high &=
4113                                         ~SECONDARY_EXEC_RDRAND_EXITING;
4114                 }
4115         }
4116
4117         if (vmx_rdseed_supported()) {
4118                 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
4119                 if (rdseed_enabled)
4120                         exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
4121
4122                 if (nested) {
4123                         if (rdseed_enabled)
4124                                 vmx->nested.msrs.secondary_ctls_high |=
4125                                         SECONDARY_EXEC_RDSEED_EXITING;
4126                         else
4127                                 vmx->nested.msrs.secondary_ctls_high &=
4128                                         ~SECONDARY_EXEC_RDSEED_EXITING;
4129                 }
4130         }
4131
4132         if (vmx_waitpkg_supported()) {
4133                 bool waitpkg_enabled =
4134                         guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG);
4135
4136                 if (!waitpkg_enabled)
4137                         exec_control &= ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4138
4139                 if (nested) {
4140                         if (waitpkg_enabled)
4141                                 vmx->nested.msrs.secondary_ctls_high |=
4142                                         SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4143                         else
4144                                 vmx->nested.msrs.secondary_ctls_high &=
4145                                         ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4146                 }
4147         }
4148
4149         vmx->secondary_exec_control = exec_control;
4150 }
4151
4152 static void ept_set_mmio_spte_mask(void)
4153 {
4154         /*
4155          * EPT Misconfigurations can be generated if the value of bits 2:0
4156          * of an EPT paging-structure entry is 110b (write/execute).
4157          */
4158         kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
4159                                    VMX_EPT_MISCONFIG_WX_VALUE, 0);
4160 }
4161
4162 #define VMX_XSS_EXIT_BITMAP 0
4163
4164 /*
4165  * Sets up the vmcs for emulated real mode.
4166  */
4167 static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
4168 {
4169         int i;
4170
4171         if (nested)
4172                 nested_vmx_vcpu_setup();
4173
4174         if (cpu_has_vmx_msr_bitmap())
4175                 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
4176
4177         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4178
4179         /* Control */
4180         pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4181         vmx->hv_deadline_tsc = -1;
4182
4183         exec_controls_set(vmx, vmx_exec_control(vmx));
4184
4185         if (cpu_has_secondary_exec_ctrls()) {
4186                 vmx_compute_secondary_exec_control(vmx);
4187                 secondary_exec_controls_set(vmx, vmx->secondary_exec_control);
4188         }
4189
4190         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4191                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4192                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4193                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4194                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4195
4196                 vmcs_write16(GUEST_INTR_STATUS, 0);
4197
4198                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4199                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4200         }
4201
4202         if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4203                 vmcs_write32(PLE_GAP, ple_gap);
4204                 vmx->ple_window = ple_window;
4205                 vmx->ple_window_dirty = true;
4206         }
4207
4208         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4209         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4210         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4211
4212         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4213         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4214         vmx_set_constant_host_state(vmx);
4215         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4216         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4217
4218         if (cpu_has_vmx_vmfunc())
4219                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4220
4221         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4222         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4223         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
4224         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4225         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
4226
4227         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4228                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4229
4230         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4231                 u32 index = vmx_msr_index[i];
4232                 u32 data_low, data_high;
4233                 int j = vmx->nmsrs;
4234
4235                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4236                         continue;
4237                 if (wrmsr_safe(index, data_low, data_high) < 0)
4238                         continue;
4239                 vmx->guest_msrs[j].index = i;
4240                 vmx->guest_msrs[j].data = 0;
4241                 vmx->guest_msrs[j].mask = -1ull;
4242                 ++vmx->nmsrs;
4243         }
4244
4245         vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
4246
4247         /* 22.2.1, 20.8.1 */
4248         vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
4249
4250         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
4251         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
4252
4253         set_cr4_guest_host_mask(vmx);
4254
4255         if (vmx_xsaves_supported())
4256                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4257
4258         if (enable_pml) {
4259                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4260                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4261         }
4262
4263         if (cpu_has_vmx_encls_vmexit())
4264                 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
4265
4266         if (pt_mode == PT_MODE_HOST_GUEST) {
4267                 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4268                 /* Bit[6~0] are forced to 1, writes are ignored. */
4269                 vmx->pt_desc.guest.output_mask = 0x7F;
4270                 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4271         }
4272 }
4273
4274 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4275 {
4276         struct vcpu_vmx *vmx = to_vmx(vcpu);
4277         struct msr_data apic_base_msr;
4278         u64 cr0;
4279
4280         vmx->rmode.vm86_active = 0;
4281         vmx->spec_ctrl = 0;
4282
4283         vmx->msr_ia32_umwait_control = 0;
4284
4285         vcpu->arch.microcode_version = 0x100000000ULL;
4286         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4287         vmx->hv_deadline_tsc = -1;
4288         kvm_set_cr8(vcpu, 0);
4289
4290         if (!init_event) {
4291                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4292                                      MSR_IA32_APICBASE_ENABLE;
4293                 if (kvm_vcpu_is_reset_bsp(vcpu))
4294                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4295                 apic_base_msr.host_initiated = true;
4296                 kvm_set_apic_base(vcpu, &apic_base_msr);
4297         }
4298
4299         vmx_segment_cache_clear(vmx);
4300
4301         seg_setup(VCPU_SREG_CS);
4302         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4303         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4304
4305         seg_setup(VCPU_SREG_DS);
4306         seg_setup(VCPU_SREG_ES);
4307         seg_setup(VCPU_SREG_FS);
4308         seg_setup(VCPU_SREG_GS);
4309         seg_setup(VCPU_SREG_SS);
4310
4311         vmcs_write16(GUEST_TR_SELECTOR, 0);
4312         vmcs_writel(GUEST_TR_BASE, 0);
4313         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4314         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4315
4316         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4317         vmcs_writel(GUEST_LDTR_BASE, 0);
4318         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4319         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4320
4321         if (!init_event) {
4322                 vmcs_write32(GUEST_SYSENTER_CS, 0);
4323                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4324                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4325                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4326         }
4327
4328         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
4329         kvm_rip_write(vcpu, 0xfff0);
4330
4331         vmcs_writel(GUEST_GDTR_BASE, 0);
4332         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4333
4334         vmcs_writel(GUEST_IDTR_BASE, 0);
4335         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4336
4337         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4338         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4339         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4340         if (kvm_mpx_supported())
4341                 vmcs_write64(GUEST_BNDCFGS, 0);
4342
4343         setup_msrs(vmx);
4344
4345         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4346
4347         if (cpu_has_vmx_tpr_shadow() && !init_event) {
4348                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4349                 if (cpu_need_tpr_shadow(vcpu))
4350                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4351                                      __pa(vcpu->arch.apic->regs));
4352                 vmcs_write32(TPR_THRESHOLD, 0);
4353         }
4354
4355         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4356
4357         if (vmx->vpid != 0)
4358                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4359
4360         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4361         vmx->vcpu.arch.cr0 = cr0;
4362         vmx_set_cr0(vcpu, cr0); /* enter rmode */
4363         vmx_set_cr4(vcpu, 0);
4364         vmx_set_efer(vcpu, 0);
4365
4366         update_exception_bitmap(vcpu);
4367
4368         vpid_sync_context(vmx->vpid);
4369         if (init_event)
4370                 vmx_clear_hlt(vcpu);
4371 }
4372
4373 static void enable_irq_window(struct kvm_vcpu *vcpu)
4374 {
4375         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_INTR_PENDING);
4376 }
4377
4378 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4379 {
4380         if (!enable_vnmi ||
4381             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4382                 enable_irq_window(vcpu);
4383                 return;
4384         }
4385
4386         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_NMI_PENDING);
4387 }
4388
4389 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4390 {
4391         struct vcpu_vmx *vmx = to_vmx(vcpu);
4392         uint32_t intr;
4393         int irq = vcpu->arch.interrupt.nr;
4394
4395         trace_kvm_inj_virq(irq);
4396
4397         ++vcpu->stat.irq_injections;
4398         if (vmx->rmode.vm86_active) {
4399                 int inc_eip = 0;
4400                 if (vcpu->arch.interrupt.soft)
4401                         inc_eip = vcpu->arch.event_exit_inst_len;
4402                 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
4403                 return;
4404         }
4405         intr = irq | INTR_INFO_VALID_MASK;
4406         if (vcpu->arch.interrupt.soft) {
4407                 intr |= INTR_TYPE_SOFT_INTR;
4408                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4409                              vmx->vcpu.arch.event_exit_inst_len);
4410         } else
4411                 intr |= INTR_TYPE_EXT_INTR;
4412         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4413
4414         vmx_clear_hlt(vcpu);
4415 }
4416
4417 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4418 {
4419         struct vcpu_vmx *vmx = to_vmx(vcpu);
4420
4421         if (!enable_vnmi) {
4422                 /*
4423                  * Tracking the NMI-blocked state in software is built upon
4424                  * finding the next open IRQ window. This, in turn, depends on
4425                  * well-behaving guests: They have to keep IRQs disabled at
4426                  * least as long as the NMI handler runs. Otherwise we may
4427                  * cause NMI nesting, maybe breaking the guest. But as this is
4428                  * highly unlikely, we can live with the residual risk.
4429                  */
4430                 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4431                 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4432         }
4433
4434         ++vcpu->stat.nmi_injections;
4435         vmx->loaded_vmcs->nmi_known_unmasked = false;
4436
4437         if (vmx->rmode.vm86_active) {
4438                 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
4439                 return;
4440         }
4441
4442         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4443                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4444
4445         vmx_clear_hlt(vcpu);
4446 }
4447
4448 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4449 {
4450         struct vcpu_vmx *vmx = to_vmx(vcpu);
4451         bool masked;
4452
4453         if (!enable_vnmi)
4454                 return vmx->loaded_vmcs->soft_vnmi_blocked;
4455         if (vmx->loaded_vmcs->nmi_known_unmasked)
4456                 return false;
4457         masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4458         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4459         return masked;
4460 }
4461
4462 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4463 {
4464         struct vcpu_vmx *vmx = to_vmx(vcpu);
4465
4466         if (!enable_vnmi) {
4467                 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4468                         vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4469                         vmx->loaded_vmcs->vnmi_blocked_time = 0;
4470                 }
4471         } else {
4472                 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4473                 if (masked)
4474                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4475                                       GUEST_INTR_STATE_NMI);
4476                 else
4477                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4478                                         GUEST_INTR_STATE_NMI);
4479         }
4480 }
4481
4482 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4483 {
4484         if (to_vmx(vcpu)->nested.nested_run_pending)
4485                 return 0;
4486
4487         if (!enable_vnmi &&
4488             to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4489                 return 0;
4490
4491         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4492                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4493                    | GUEST_INTR_STATE_NMI));
4494 }
4495
4496 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4497 {
4498         return (!to_vmx(vcpu)->nested.nested_run_pending &&
4499                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4500                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4501                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4502 }
4503
4504 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4505 {
4506         int ret;
4507
4508         if (enable_unrestricted_guest)
4509                 return 0;
4510
4511         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4512                                     PAGE_SIZE * 3);
4513         if (ret)
4514                 return ret;
4515         to_kvm_vmx(kvm)->tss_addr = addr;
4516         return init_rmode_tss(kvm);
4517 }
4518
4519 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4520 {
4521         to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
4522         return 0;
4523 }
4524
4525 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4526 {
4527         switch (vec) {
4528         case BP_VECTOR:
4529                 /*
4530                  * Update instruction length as we may reinject the exception
4531                  * from user space while in guest debugging mode.
4532                  */
4533                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4534                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4535                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4536                         return false;
4537                 /* fall through */
4538         case DB_VECTOR:
4539                 if (vcpu->guest_debug &
4540                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4541                         return false;
4542                 /* fall through */
4543         case DE_VECTOR:
4544         case OF_VECTOR:
4545         case BR_VECTOR:
4546         case UD_VECTOR:
4547         case DF_VECTOR:
4548         case SS_VECTOR:
4549         case GP_VECTOR:
4550         case MF_VECTOR:
4551                 return true;
4552         break;
4553         }
4554         return false;
4555 }
4556
4557 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4558                                   int vec, u32 err_code)
4559 {
4560         /*
4561          * Instruction with address size override prefix opcode 0x67
4562          * Cause the #SS fault with 0 error code in VM86 mode.
4563          */
4564         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4565                 if (kvm_emulate_instruction(vcpu, 0)) {
4566                         if (vcpu->arch.halt_request) {
4567                                 vcpu->arch.halt_request = 0;
4568                                 return kvm_vcpu_halt(vcpu);
4569                         }
4570                         return 1;
4571                 }
4572                 return 0;
4573         }
4574
4575         /*
4576          * Forward all other exceptions that are valid in real mode.
4577          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4578          *        the required debugging infrastructure rework.
4579          */
4580         kvm_queue_exception(vcpu, vec);
4581         return 1;
4582 }
4583
4584 /*
4585  * Trigger machine check on the host. We assume all the MSRs are already set up
4586  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4587  * We pass a fake environment to the machine check handler because we want
4588  * the guest to be always treated like user space, no matter what context
4589  * it used internally.
4590  */
4591 static void kvm_machine_check(void)
4592 {
4593 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4594         struct pt_regs regs = {
4595                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4596                 .flags = X86_EFLAGS_IF,
4597         };
4598
4599         do_machine_check(&regs, 0);
4600 #endif
4601 }
4602
4603 static int handle_machine_check(struct kvm_vcpu *vcpu)
4604 {
4605         /* handled by vmx_vcpu_run() */
4606         return 1;
4607 }
4608
4609 static int handle_exception_nmi(struct kvm_vcpu *vcpu)
4610 {
4611         struct vcpu_vmx *vmx = to_vmx(vcpu);
4612         struct kvm_run *kvm_run = vcpu->run;
4613         u32 intr_info, ex_no, error_code;
4614         unsigned long cr2, rip, dr6;
4615         u32 vect_info;
4616
4617         vect_info = vmx->idt_vectoring_info;
4618         intr_info = vmx->exit_intr_info;
4619
4620         if (is_machine_check(intr_info) || is_nmi(intr_info))
4621                 return 1; /* handled by handle_exception_nmi_irqoff() */
4622
4623         if (is_invalid_opcode(intr_info))
4624                 return handle_ud(vcpu);
4625
4626         error_code = 0;
4627         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4628                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4629
4630         if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4631                 WARN_ON_ONCE(!enable_vmware_backdoor);
4632
4633                 /*
4634                  * VMware backdoor emulation on #GP interception only handles
4635                  * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
4636                  * error code on #GP.
4637                  */
4638                 if (error_code) {
4639                         kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4640                         return 1;
4641                 }
4642                 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
4643         }
4644
4645         /*
4646          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4647          * MMIO, it is better to report an internal error.
4648          * See the comments in vmx_handle_exit.
4649          */
4650         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4651             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4652                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4653                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4654                 vcpu->run->internal.ndata = 3;
4655                 vcpu->run->internal.data[0] = vect_info;
4656                 vcpu->run->internal.data[1] = intr_info;
4657                 vcpu->run->internal.data[2] = error_code;
4658                 return 0;
4659         }
4660
4661         if (is_page_fault(intr_info)) {
4662                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4663                 /* EPT won't cause page fault directly */
4664                 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
4665                 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
4666         }
4667
4668         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4669
4670         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4671                 return handle_rmode_exception(vcpu, ex_no, error_code);
4672
4673         switch (ex_no) {
4674         case AC_VECTOR:
4675                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4676                 return 1;
4677         case DB_VECTOR:
4678                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4679                 if (!(vcpu->guest_debug &
4680                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4681                         vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4682                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
4683                         if (is_icebp(intr_info))
4684                                 WARN_ON(!skip_emulated_instruction(vcpu));
4685
4686                         kvm_queue_exception(vcpu, DB_VECTOR);
4687                         return 1;
4688                 }
4689                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4690                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4691                 /* fall through */
4692         case BP_VECTOR:
4693                 /*
4694                  * Update instruction length as we may reinject #BP from
4695                  * user space while in guest debugging mode. Reading it for
4696                  * #DB as well causes no harm, it is not used in that case.
4697                  */
4698                 vmx->vcpu.arch.event_exit_inst_len =
4699                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4700                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4701                 rip = kvm_rip_read(vcpu);
4702                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4703                 kvm_run->debug.arch.exception = ex_no;
4704                 break;
4705         default:
4706                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4707                 kvm_run->ex.exception = ex_no;
4708                 kvm_run->ex.error_code = error_code;
4709                 break;
4710         }
4711         return 0;
4712 }
4713
4714 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4715 {
4716         ++vcpu->stat.irq_exits;
4717         return 1;
4718 }
4719
4720 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4721 {
4722         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4723         vcpu->mmio_needed = 0;
4724         return 0;
4725 }
4726
4727 static int handle_io(struct kvm_vcpu *vcpu)
4728 {
4729         unsigned long exit_qualification;
4730         int size, in, string;
4731         unsigned port;
4732
4733         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4734         string = (exit_qualification & 16) != 0;
4735
4736         ++vcpu->stat.io_exits;
4737
4738         if (string)
4739                 return kvm_emulate_instruction(vcpu, 0);
4740
4741         port = exit_qualification >> 16;
4742         size = (exit_qualification & 7) + 1;
4743         in = (exit_qualification & 8) != 0;
4744
4745         return kvm_fast_pio(vcpu, size, port, in);
4746 }
4747
4748 static void
4749 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4750 {
4751         /*
4752          * Patch in the VMCALL instruction:
4753          */
4754         hypercall[0] = 0x0f;
4755         hypercall[1] = 0x01;
4756         hypercall[2] = 0xc1;
4757 }
4758
4759 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4760 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4761 {
4762         if (is_guest_mode(vcpu)) {
4763                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4764                 unsigned long orig_val = val;
4765
4766                 /*
4767                  * We get here when L2 changed cr0 in a way that did not change
4768                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4769                  * but did change L0 shadowed bits. So we first calculate the
4770                  * effective cr0 value that L1 would like to write into the
4771                  * hardware. It consists of the L2-owned bits from the new
4772                  * value combined with the L1-owned bits from L1's guest_cr0.
4773                  */
4774                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4775                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4776
4777                 if (!nested_guest_cr0_valid(vcpu, val))
4778                         return 1;
4779
4780                 if (kvm_set_cr0(vcpu, val))
4781                         return 1;
4782                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4783                 return 0;
4784         } else {
4785                 if (to_vmx(vcpu)->nested.vmxon &&
4786                     !nested_host_cr0_valid(vcpu, val))
4787                         return 1;
4788
4789                 return kvm_set_cr0(vcpu, val);
4790         }
4791 }
4792
4793 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4794 {
4795         if (is_guest_mode(vcpu)) {
4796                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4797                 unsigned long orig_val = val;
4798
4799                 /* analogously to handle_set_cr0 */
4800                 val = (val & ~vmcs12->cr4_guest_host_mask) |
4801                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4802                 if (kvm_set_cr4(vcpu, val))
4803                         return 1;
4804                 vmcs_writel(CR4_READ_SHADOW, orig_val);
4805                 return 0;
4806         } else
4807                 return kvm_set_cr4(vcpu, val);
4808 }
4809
4810 static int handle_desc(struct kvm_vcpu *vcpu)
4811 {
4812         WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
4813         return kvm_emulate_instruction(vcpu, 0);
4814 }
4815
4816 static int handle_cr(struct kvm_vcpu *vcpu)
4817 {
4818         unsigned long exit_qualification, val;
4819         int cr;
4820         int reg;
4821         int err;
4822         int ret;
4823
4824         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4825         cr = exit_qualification & 15;
4826         reg = (exit_qualification >> 8) & 15;
4827         switch ((exit_qualification >> 4) & 3) {
4828         case 0: /* mov to cr */
4829                 val = kvm_register_readl(vcpu, reg);
4830                 trace_kvm_cr_write(cr, val);
4831                 switch (cr) {
4832                 case 0:
4833                         err = handle_set_cr0(vcpu, val);
4834                         return kvm_complete_insn_gp(vcpu, err);
4835                 case 3:
4836                         WARN_ON_ONCE(enable_unrestricted_guest);
4837                         err = kvm_set_cr3(vcpu, val);
4838                         return kvm_complete_insn_gp(vcpu, err);
4839                 case 4:
4840                         err = handle_set_cr4(vcpu, val);
4841                         return kvm_complete_insn_gp(vcpu, err);
4842                 case 8: {
4843                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4844                                 u8 cr8 = (u8)val;
4845                                 err = kvm_set_cr8(vcpu, cr8);
4846                                 ret = kvm_complete_insn_gp(vcpu, err);
4847                                 if (lapic_in_kernel(vcpu))
4848                                         return ret;
4849                                 if (cr8_prev <= cr8)
4850                                         return ret;
4851                                 /*
4852                                  * TODO: we might be squashing a
4853                                  * KVM_GUESTDBG_SINGLESTEP-triggered
4854                                  * KVM_EXIT_DEBUG here.
4855                                  */
4856                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4857                                 return 0;
4858                         }
4859                 }
4860                 break;
4861         case 2: /* clts */
4862                 WARN_ONCE(1, "Guest should always own CR0.TS");
4863                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4864                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4865                 return kvm_skip_emulated_instruction(vcpu);
4866         case 1: /*mov from cr*/
4867                 switch (cr) {
4868                 case 3:
4869                         WARN_ON_ONCE(enable_unrestricted_guest);
4870                         val = kvm_read_cr3(vcpu);
4871                         kvm_register_write(vcpu, reg, val);
4872                         trace_kvm_cr_read(cr, val);
4873                         return kvm_skip_emulated_instruction(vcpu);
4874                 case 8:
4875                         val = kvm_get_cr8(vcpu);
4876                         kvm_register_write(vcpu, reg, val);
4877                         trace_kvm_cr_read(cr, val);
4878                         return kvm_skip_emulated_instruction(vcpu);
4879                 }
4880                 break;
4881         case 3: /* lmsw */
4882                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4883                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4884                 kvm_lmsw(vcpu, val);
4885
4886                 return kvm_skip_emulated_instruction(vcpu);
4887         default:
4888                 break;
4889         }
4890         vcpu->run->exit_reason = 0;
4891         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4892                (int)(exit_qualification >> 4) & 3, cr);
4893         return 0;
4894 }
4895
4896 static int handle_dr(struct kvm_vcpu *vcpu)
4897 {
4898         unsigned long exit_qualification;
4899         int dr, dr7, reg;
4900
4901         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4902         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4903
4904         /* First, if DR does not exist, trigger UD */
4905         if (!kvm_require_dr(vcpu, dr))
4906                 return 1;
4907
4908         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4909         if (!kvm_require_cpl(vcpu, 0))
4910                 return 1;
4911         dr7 = vmcs_readl(GUEST_DR7);
4912         if (dr7 & DR7_GD) {
4913                 /*
4914                  * As the vm-exit takes precedence over the debug trap, we
4915                  * need to emulate the latter, either for the host or the
4916                  * guest debugging itself.
4917                  */
4918                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4919                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4920                         vcpu->run->debug.arch.dr7 = dr7;
4921                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
4922                         vcpu->run->debug.arch.exception = DB_VECTOR;
4923                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4924                         return 0;
4925                 } else {
4926                         vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4927                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
4928                         kvm_queue_exception(vcpu, DB_VECTOR);
4929                         return 1;
4930                 }
4931         }
4932
4933         if (vcpu->guest_debug == 0) {
4934                 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
4935
4936                 /*
4937                  * No more DR vmexits; force a reload of the debug registers
4938                  * and reenter on this instruction.  The next vmexit will
4939                  * retrieve the full state of the debug registers.
4940                  */
4941                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4942                 return 1;
4943         }
4944
4945         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4946         if (exit_qualification & TYPE_MOV_FROM_DR) {
4947                 unsigned long val;
4948
4949                 if (kvm_get_dr(vcpu, dr, &val))
4950                         return 1;
4951                 kvm_register_write(vcpu, reg, val);
4952         } else
4953                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4954                         return 1;
4955
4956         return kvm_skip_emulated_instruction(vcpu);
4957 }
4958
4959 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
4960 {
4961         return vcpu->arch.dr6;
4962 }
4963
4964 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
4965 {
4966 }
4967
4968 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
4969 {
4970         get_debugreg(vcpu->arch.db[0], 0);
4971         get_debugreg(vcpu->arch.db[1], 1);
4972         get_debugreg(vcpu->arch.db[2], 2);
4973         get_debugreg(vcpu->arch.db[3], 3);
4974         get_debugreg(vcpu->arch.dr6, 6);
4975         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
4976
4977         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
4978         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
4979 }
4980
4981 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4982 {
4983         vmcs_writel(GUEST_DR7, val);
4984 }
4985
4986 static int handle_cpuid(struct kvm_vcpu *vcpu)
4987 {
4988         return kvm_emulate_cpuid(vcpu);
4989 }
4990
4991 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4992 {
4993         return kvm_emulate_rdmsr(vcpu);
4994 }
4995
4996 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4997 {
4998         return kvm_emulate_wrmsr(vcpu);
4999 }
5000
5001 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5002 {
5003         kvm_apic_update_ppr(vcpu);
5004         return 1;
5005 }
5006
5007 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5008 {
5009         exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_INTR_PENDING);
5010
5011         kvm_make_request(KVM_REQ_EVENT, vcpu);
5012
5013         ++vcpu->stat.irq_window_exits;
5014         return 1;
5015 }
5016
5017 static int handle_halt(struct kvm_vcpu *vcpu)
5018 {
5019         return kvm_emulate_halt(vcpu);
5020 }
5021
5022 static int handle_vmcall(struct kvm_vcpu *vcpu)
5023 {
5024         return kvm_emulate_hypercall(vcpu);
5025 }
5026
5027 static int handle_invd(struct kvm_vcpu *vcpu)
5028 {
5029         return kvm_emulate_instruction(vcpu, 0);
5030 }
5031
5032 static int handle_invlpg(struct kvm_vcpu *vcpu)
5033 {
5034         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5035
5036         kvm_mmu_invlpg(vcpu, exit_qualification);
5037         return kvm_skip_emulated_instruction(vcpu);
5038 }
5039
5040 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5041 {
5042         int err;
5043
5044         err = kvm_rdpmc(vcpu);
5045         return kvm_complete_insn_gp(vcpu, err);
5046 }
5047
5048 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5049 {
5050         return kvm_emulate_wbinvd(vcpu);
5051 }
5052
5053 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5054 {
5055         u64 new_bv = kvm_read_edx_eax(vcpu);
5056         u32 index = kvm_rcx_read(vcpu);
5057
5058         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5059                 return kvm_skip_emulated_instruction(vcpu);
5060         return 1;
5061 }
5062
5063 static int handle_apic_access(struct kvm_vcpu *vcpu)
5064 {
5065         if (likely(fasteoi)) {
5066                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5067                 int access_type, offset;
5068
5069                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5070                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5071                 /*
5072                  * Sane guest uses MOV to write EOI, with written value
5073                  * not cared. So make a short-circuit here by avoiding
5074                  * heavy instruction emulation.
5075                  */
5076                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5077                     (offset == APIC_EOI)) {
5078                         kvm_lapic_set_eoi(vcpu);
5079                         return kvm_skip_emulated_instruction(vcpu);
5080                 }
5081         }
5082         return kvm_emulate_instruction(vcpu, 0);
5083 }
5084
5085 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5086 {
5087         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5088         int vector = exit_qualification & 0xff;
5089
5090         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5091         kvm_apic_set_eoi_accelerated(vcpu, vector);
5092         return 1;
5093 }
5094
5095 static int handle_apic_write(struct kvm_vcpu *vcpu)
5096 {
5097         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5098         u32 offset = exit_qualification & 0xfff;
5099
5100         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5101         kvm_apic_write_nodecode(vcpu, offset);
5102         return 1;
5103 }
5104
5105 static int handle_task_switch(struct kvm_vcpu *vcpu)
5106 {
5107         struct vcpu_vmx *vmx = to_vmx(vcpu);
5108         unsigned long exit_qualification;
5109         bool has_error_code = false;
5110         u32 error_code = 0;
5111         u16 tss_selector;
5112         int reason, type, idt_v, idt_index;
5113
5114         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5115         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5116         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5117
5118         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5119
5120         reason = (u32)exit_qualification >> 30;
5121         if (reason == TASK_SWITCH_GATE && idt_v) {
5122                 switch (type) {
5123                 case INTR_TYPE_NMI_INTR:
5124                         vcpu->arch.nmi_injected = false;
5125                         vmx_set_nmi_mask(vcpu, true);
5126                         break;
5127                 case INTR_TYPE_EXT_INTR:
5128                 case INTR_TYPE_SOFT_INTR:
5129                         kvm_clear_interrupt_queue(vcpu);
5130                         break;
5131                 case INTR_TYPE_HARD_EXCEPTION:
5132                         if (vmx->idt_vectoring_info &
5133                             VECTORING_INFO_DELIVER_CODE_MASK) {
5134                                 has_error_code = true;
5135                                 error_code =
5136                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5137                         }
5138                         /* fall through */
5139                 case INTR_TYPE_SOFT_EXCEPTION:
5140                         kvm_clear_exception_queue(vcpu);
5141                         break;
5142                 default:
5143                         break;
5144                 }
5145         }
5146         tss_selector = exit_qualification;
5147
5148         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5149                        type != INTR_TYPE_EXT_INTR &&
5150                        type != INTR_TYPE_NMI_INTR))
5151                 WARN_ON(!skip_emulated_instruction(vcpu));
5152
5153         /*
5154          * TODO: What about debug traps on tss switch?
5155          *       Are we supposed to inject them and update dr6?
5156          */
5157         return kvm_task_switch(vcpu, tss_selector,
5158                                type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
5159                                reason, has_error_code, error_code);
5160 }
5161
5162 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5163 {
5164         unsigned long exit_qualification;
5165         gpa_t gpa;
5166         u64 error_code;
5167
5168         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5169
5170         /*
5171          * EPT violation happened while executing iret from NMI,
5172          * "blocked by NMI" bit has to be set before next VM entry.
5173          * There are errata that may cause this bit to not be set:
5174          * AAK134, BY25.
5175          */
5176         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5177                         enable_vnmi &&
5178                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5179                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5180
5181         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5182         trace_kvm_page_fault(gpa, exit_qualification);
5183
5184         /* Is it a read fault? */
5185         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
5186                      ? PFERR_USER_MASK : 0;
5187         /* Is it a write fault? */
5188         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
5189                       ? PFERR_WRITE_MASK : 0;
5190         /* Is it a fetch fault? */
5191         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
5192                       ? PFERR_FETCH_MASK : 0;
5193         /* ept page table entry is present? */
5194         error_code |= (exit_qualification &
5195                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5196                         EPT_VIOLATION_EXECUTABLE))
5197                       ? PFERR_PRESENT_MASK : 0;
5198
5199         error_code |= (exit_qualification & 0x100) != 0 ?
5200                PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
5201
5202         vcpu->arch.exit_qualification = exit_qualification;
5203         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5204 }
5205
5206 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5207 {
5208         gpa_t gpa;
5209
5210         /*
5211          * A nested guest cannot optimize MMIO vmexits, because we have an
5212          * nGPA here instead of the required GPA.
5213          */
5214         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5215         if (!is_guest_mode(vcpu) &&
5216             !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5217                 trace_kvm_fast_mmio(gpa);
5218                 return kvm_skip_emulated_instruction(vcpu);
5219         }
5220
5221         return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
5222 }
5223
5224 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5225 {
5226         WARN_ON_ONCE(!enable_vnmi);
5227         exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_NMI_PENDING);
5228         ++vcpu->stat.nmi_window_exits;
5229         kvm_make_request(KVM_REQ_EVENT, vcpu);
5230
5231         return 1;
5232 }
5233
5234 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5235 {
5236         struct vcpu_vmx *vmx = to_vmx(vcpu);
5237         bool intr_window_requested;
5238         unsigned count = 130;
5239
5240         /*
5241          * We should never reach the point where we are emulating L2
5242          * due to invalid guest state as that means we incorrectly
5243          * allowed a nested VMEntry with an invalid vmcs12.
5244          */
5245         WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
5246
5247         intr_window_requested = exec_controls_get(vmx) &
5248                                 CPU_BASED_VIRTUAL_INTR_PENDING;
5249
5250         while (vmx->emulation_required && count-- != 0) {
5251                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5252                         return handle_interrupt_window(&vmx->vcpu);
5253
5254                 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
5255                         return 1;
5256
5257                 if (!kvm_emulate_instruction(vcpu, 0))
5258                         return 0;
5259
5260                 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5261                     vcpu->arch.exception.pending) {
5262                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5263                         vcpu->run->internal.suberror =
5264                                                 KVM_INTERNAL_ERROR_EMULATION;
5265                         vcpu->run->internal.ndata = 0;
5266                         return 0;
5267                 }
5268
5269                 if (vcpu->arch.halt_request) {
5270                         vcpu->arch.halt_request = 0;
5271                         return kvm_vcpu_halt(vcpu);
5272                 }
5273
5274                 /*
5275                  * Note, return 1 and not 0, vcpu_run() is responsible for
5276                  * morphing the pending signal into the proper return code.
5277                  */
5278                 if (signal_pending(current))
5279                         return 1;
5280
5281                 if (need_resched())
5282                         schedule();
5283         }
5284
5285         return 1;
5286 }
5287
5288 static void grow_ple_window(struct kvm_vcpu *vcpu)
5289 {
5290         struct vcpu_vmx *vmx = to_vmx(vcpu);
5291         unsigned int old = vmx->ple_window;
5292
5293         vmx->ple_window = __grow_ple_window(old, ple_window,
5294                                             ple_window_grow,
5295                                             ple_window_max);
5296
5297         if (vmx->ple_window != old) {
5298                 vmx->ple_window_dirty = true;
5299                 trace_kvm_ple_window_update(vcpu->vcpu_id,
5300                                             vmx->ple_window, old);
5301         }
5302 }
5303
5304 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5305 {
5306         struct vcpu_vmx *vmx = to_vmx(vcpu);
5307         unsigned int old = vmx->ple_window;
5308
5309         vmx->ple_window = __shrink_ple_window(old, ple_window,
5310                                               ple_window_shrink,
5311                                               ple_window);
5312
5313         if (vmx->ple_window != old) {
5314                 vmx->ple_window_dirty = true;
5315                 trace_kvm_ple_window_update(vcpu->vcpu_id,
5316                                             vmx->ple_window, old);
5317         }
5318 }
5319
5320 /*
5321  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
5322  */
5323 static void wakeup_handler(void)
5324 {
5325         struct kvm_vcpu *vcpu;
5326         int cpu = smp_processor_id();
5327
5328         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5329         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
5330                         blocked_vcpu_list) {
5331                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
5332
5333                 if (pi_test_on(pi_desc) == 1)
5334                         kvm_vcpu_kick(vcpu);
5335         }
5336         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5337 }
5338
5339 static void vmx_enable_tdp(void)
5340 {
5341         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
5342                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
5343                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
5344                 0ull, VMX_EPT_EXECUTABLE_MASK,
5345                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
5346                 VMX_EPT_RWX_MASK, 0ull);
5347
5348         ept_set_mmio_spte_mask();
5349         kvm_enable_tdp();
5350 }
5351
5352 /*
5353  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5354  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5355  */
5356 static int handle_pause(struct kvm_vcpu *vcpu)
5357 {
5358         if (!kvm_pause_in_guest(vcpu->kvm))
5359                 grow_ple_window(vcpu);
5360
5361         /*
5362          * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5363          * VM-execution control is ignored if CPL > 0. OTOH, KVM
5364          * never set PAUSE_EXITING and just set PLE if supported,
5365          * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5366          */
5367         kvm_vcpu_on_spin(vcpu, true);
5368         return kvm_skip_emulated_instruction(vcpu);
5369 }
5370
5371 static int handle_nop(struct kvm_vcpu *vcpu)
5372 {
5373         return kvm_skip_emulated_instruction(vcpu);
5374 }
5375
5376 static int handle_mwait(struct kvm_vcpu *vcpu)
5377 {
5378         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5379         return handle_nop(vcpu);
5380 }
5381
5382 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5383 {
5384         kvm_queue_exception(vcpu, UD_VECTOR);
5385         return 1;
5386 }
5387
5388 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5389 {
5390         return 1;
5391 }
5392
5393 static int handle_monitor(struct kvm_vcpu *vcpu)
5394 {
5395         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5396         return handle_nop(vcpu);
5397 }
5398
5399 static int handle_invpcid(struct kvm_vcpu *vcpu)
5400 {
5401         u32 vmx_instruction_info;
5402         unsigned long type;
5403         bool pcid_enabled;
5404         gva_t gva;
5405         struct x86_exception e;
5406         unsigned i;
5407         unsigned long roots_to_free = 0;
5408         struct {
5409                 u64 pcid;
5410                 u64 gla;
5411         } operand;
5412
5413         if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
5414                 kvm_queue_exception(vcpu, UD_VECTOR);
5415                 return 1;
5416         }
5417
5418         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5419         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5420
5421         if (type > 3) {
5422                 kvm_inject_gp(vcpu, 0);
5423                 return 1;
5424         }
5425
5426         /* According to the Intel instruction reference, the memory operand
5427          * is read even if it isn't needed (e.g., for type==all)
5428          */
5429         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5430                                 vmx_instruction_info, false,
5431                                 sizeof(operand), &gva))
5432                 return 1;
5433
5434         if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
5435                 kvm_inject_page_fault(vcpu, &e);
5436                 return 1;
5437         }
5438
5439         if (operand.pcid >> 12 != 0) {
5440                 kvm_inject_gp(vcpu, 0);
5441                 return 1;
5442         }
5443
5444         pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
5445
5446         switch (type) {
5447         case INVPCID_TYPE_INDIV_ADDR:
5448                 if ((!pcid_enabled && (operand.pcid != 0)) ||
5449                     is_noncanonical_address(operand.gla, vcpu)) {
5450                         kvm_inject_gp(vcpu, 0);
5451                         return 1;
5452                 }
5453                 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
5454                 return kvm_skip_emulated_instruction(vcpu);
5455
5456         case INVPCID_TYPE_SINGLE_CTXT:
5457                 if (!pcid_enabled && (operand.pcid != 0)) {
5458                         kvm_inject_gp(vcpu, 0);
5459                         return 1;
5460                 }
5461
5462                 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
5463                         kvm_mmu_sync_roots(vcpu);
5464                         kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
5465                 }
5466
5467                 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5468                         if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3)
5469                             == operand.pcid)
5470                                 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
5471
5472                 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
5473                 /*
5474                  * If neither the current cr3 nor any of the prev_roots use the
5475                  * given PCID, then nothing needs to be done here because a
5476                  * resync will happen anyway before switching to any other CR3.
5477                  */
5478
5479                 return kvm_skip_emulated_instruction(vcpu);
5480
5481         case INVPCID_TYPE_ALL_NON_GLOBAL:
5482                 /*
5483                  * Currently, KVM doesn't mark global entries in the shadow
5484                  * page tables, so a non-global flush just degenerates to a
5485                  * global flush. If needed, we could optimize this later by
5486                  * keeping track of global entries in shadow page tables.
5487                  */
5488
5489                 /* fall-through */
5490         case INVPCID_TYPE_ALL_INCL_GLOBAL:
5491                 kvm_mmu_unload(vcpu);
5492                 return kvm_skip_emulated_instruction(vcpu);
5493
5494         default:
5495                 BUG(); /* We have already checked above that type <= 3 */
5496         }
5497 }
5498
5499 static int handle_pml_full(struct kvm_vcpu *vcpu)
5500 {
5501         unsigned long exit_qualification;
5502
5503         trace_kvm_pml_full(vcpu->vcpu_id);
5504
5505         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5506
5507         /*
5508          * PML buffer FULL happened while executing iret from NMI,
5509          * "blocked by NMI" bit has to be set before next VM entry.
5510          */
5511         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5512                         enable_vnmi &&
5513                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5514                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5515                                 GUEST_INTR_STATE_NMI);
5516
5517         /*
5518          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5519          * here.., and there's no userspace involvement needed for PML.
5520          */
5521         return 1;
5522 }
5523
5524 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
5525 {
5526         struct vcpu_vmx *vmx = to_vmx(vcpu);
5527
5528         if (!vmx->req_immediate_exit &&
5529             !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled))
5530                 kvm_lapic_expired_hv_timer(vcpu);
5531
5532         return 1;
5533 }
5534
5535 /*
5536  * When nested=0, all VMX instruction VM Exits filter here.  The handlers
5537  * are overwritten by nested_vmx_setup() when nested=1.
5538  */
5539 static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
5540 {
5541         kvm_queue_exception(vcpu, UD_VECTOR);
5542         return 1;
5543 }
5544
5545 static int handle_encls(struct kvm_vcpu *vcpu)
5546 {
5547         /*
5548          * SGX virtualization is not yet supported.  There is no software
5549          * enable bit for SGX, so we have to trap ENCLS and inject a #UD
5550          * to prevent the guest from executing ENCLS.
5551          */
5552         kvm_queue_exception(vcpu, UD_VECTOR);
5553         return 1;
5554 }
5555
5556 /*
5557  * The exit handlers return 1 if the exit was handled fully and guest execution
5558  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5559  * to be done to userspace and return 0.
5560  */
5561 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5562         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception_nmi,
5563         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5564         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5565         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5566         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5567         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5568         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5569         [EXIT_REASON_CPUID]                   = handle_cpuid,
5570         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
5571         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
5572         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
5573         [EXIT_REASON_HLT]                     = handle_halt,
5574         [EXIT_REASON_INVD]                    = handle_invd,
5575         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5576         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
5577         [EXIT_REASON_VMCALL]                  = handle_vmcall,
5578         [EXIT_REASON_VMCLEAR]                 = handle_vmx_instruction,
5579         [EXIT_REASON_VMLAUNCH]                = handle_vmx_instruction,
5580         [EXIT_REASON_VMPTRLD]                 = handle_vmx_instruction,
5581         [EXIT_REASON_VMPTRST]                 = handle_vmx_instruction,
5582         [EXIT_REASON_VMREAD]                  = handle_vmx_instruction,
5583         [EXIT_REASON_VMRESUME]                = handle_vmx_instruction,
5584         [EXIT_REASON_VMWRITE]                 = handle_vmx_instruction,
5585         [EXIT_REASON_VMOFF]                   = handle_vmx_instruction,
5586         [EXIT_REASON_VMON]                    = handle_vmx_instruction,
5587         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5588         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5589         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
5590         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
5591         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
5592         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
5593         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5594         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5595         [EXIT_REASON_GDTR_IDTR]               = handle_desc,
5596         [EXIT_REASON_LDTR_TR]                 = handle_desc,
5597         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5598         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5599         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5600         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
5601         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
5602         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
5603         [EXIT_REASON_INVEPT]                  = handle_vmx_instruction,
5604         [EXIT_REASON_INVVPID]                 = handle_vmx_instruction,
5605         [EXIT_REASON_RDRAND]                  = handle_invalid_op,
5606         [EXIT_REASON_RDSEED]                  = handle_invalid_op,
5607         [EXIT_REASON_PML_FULL]                = handle_pml_full,
5608         [EXIT_REASON_INVPCID]                 = handle_invpcid,
5609         [EXIT_REASON_VMFUNC]                  = handle_vmx_instruction,
5610         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
5611         [EXIT_REASON_ENCLS]                   = handle_encls,
5612 };
5613
5614 static const int kvm_vmx_max_exit_handlers =
5615         ARRAY_SIZE(kvm_vmx_exit_handlers);
5616
5617 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5618 {
5619         *info1 = vmcs_readl(EXIT_QUALIFICATION);
5620         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5621 }
5622
5623 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
5624 {
5625         if (vmx->pml_pg) {
5626                 __free_page(vmx->pml_pg);
5627                 vmx->pml_pg = NULL;
5628         }
5629 }
5630
5631 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
5632 {
5633         struct vcpu_vmx *vmx = to_vmx(vcpu);
5634         u64 *pml_buf;
5635         u16 pml_idx;
5636
5637         pml_idx = vmcs_read16(GUEST_PML_INDEX);
5638
5639         /* Do nothing if PML buffer is empty */
5640         if (pml_idx == (PML_ENTITY_NUM - 1))
5641                 return;
5642
5643         /* PML index always points to next available PML buffer entity */
5644         if (pml_idx >= PML_ENTITY_NUM)
5645                 pml_idx = 0;
5646         else
5647                 pml_idx++;
5648
5649         pml_buf = page_address(vmx->pml_pg);
5650         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5651                 u64 gpa;
5652
5653                 gpa = pml_buf[pml_idx];
5654                 WARN_ON(gpa & (PAGE_SIZE - 1));
5655                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5656         }
5657
5658         /* reset PML index */
5659         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5660 }
5661
5662 /*
5663  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
5664  * Called before reporting dirty_bitmap to userspace.
5665  */
5666 static void kvm_flush_pml_buffers(struct kvm *kvm)
5667 {
5668         int i;
5669         struct kvm_vcpu *vcpu;
5670         /*
5671          * We only need to kick vcpu out of guest mode here, as PML buffer
5672          * is flushed at beginning of all VMEXITs, and it's obvious that only
5673          * vcpus running in guest are possible to have unflushed GPAs in PML
5674          * buffer.
5675          */
5676         kvm_for_each_vcpu(i, vcpu, kvm)
5677                 kvm_vcpu_kick(vcpu);
5678 }
5679
5680 static void vmx_dump_sel(char *name, uint32_t sel)
5681 {
5682         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5683                name, vmcs_read16(sel),
5684                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5685                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5686                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
5687 }
5688
5689 static void vmx_dump_dtsel(char *name, uint32_t limit)
5690 {
5691         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
5692                name, vmcs_read32(limit),
5693                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
5694 }
5695
5696 void dump_vmcs(void)
5697 {
5698         u32 vmentry_ctl, vmexit_ctl;
5699         u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5700         unsigned long cr4;
5701         u64 efer;
5702         int i, n;
5703
5704         if (!dump_invalid_vmcs) {
5705                 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5706                 return;
5707         }
5708
5709         vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5710         vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5711         cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5712         pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5713         cr4 = vmcs_readl(GUEST_CR4);
5714         efer = vmcs_read64(GUEST_IA32_EFER);
5715         secondary_exec_control = 0;
5716         if (cpu_has_secondary_exec_ctrls())
5717                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5718
5719         pr_err("*** Guest State ***\n");
5720         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5721                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5722                vmcs_readl(CR0_GUEST_HOST_MASK));
5723         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5724                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5725         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5726         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
5727             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
5728         {
5729                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
5730                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5731                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
5732                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
5733         }
5734         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
5735                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5736         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
5737                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5738         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5739                vmcs_readl(GUEST_SYSENTER_ESP),
5740                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5741         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
5742         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
5743         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
5744         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
5745         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
5746         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
5747         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5748         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5749         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5750         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
5751         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
5752             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
5753                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
5754                        efer, vmcs_read64(GUEST_IA32_PAT));
5755         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
5756                vmcs_read64(GUEST_IA32_DEBUGCTL),
5757                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5758         if (cpu_has_load_perf_global_ctrl() &&
5759             vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5760                 pr_err("PerfGlobCtl = 0x%016llx\n",
5761                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5762         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5763                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5764         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
5765                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5766                vmcs_read32(GUEST_ACTIVITY_STATE));
5767         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5768                 pr_err("InterruptStatus = %04x\n",
5769                        vmcs_read16(GUEST_INTR_STATUS));
5770
5771         pr_err("*** Host State ***\n");
5772         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
5773                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5774         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5775                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5776                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5777                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5778                vmcs_read16(HOST_TR_SELECTOR));
5779         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5780                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5781                vmcs_readl(HOST_TR_BASE));
5782         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5783                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5784         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5785                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5786                vmcs_readl(HOST_CR4));
5787         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5788                vmcs_readl(HOST_IA32_SYSENTER_ESP),
5789                vmcs_read32(HOST_IA32_SYSENTER_CS),
5790                vmcs_readl(HOST_IA32_SYSENTER_EIP));
5791         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
5792                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
5793                        vmcs_read64(HOST_IA32_EFER),
5794                        vmcs_read64(HOST_IA32_PAT));
5795         if (cpu_has_load_perf_global_ctrl() &&
5796             vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5797                 pr_err("PerfGlobCtl = 0x%016llx\n",
5798                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
5799
5800         pr_err("*** Control State ***\n");
5801         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5802                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5803         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5804         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5805                vmcs_read32(EXCEPTION_BITMAP),
5806                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5807                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5808         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5809                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5810                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5811                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5812         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5813                vmcs_read32(VM_EXIT_INTR_INFO),
5814                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5815                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5816         pr_err("        reason=%08x qualification=%016lx\n",
5817                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5818         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5819                vmcs_read32(IDT_VECTORING_INFO_FIELD),
5820                vmcs_read32(IDT_VECTORING_ERROR_CODE));
5821         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5822         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5823                 pr_err("TSC Multiplier = 0x%016llx\n",
5824                        vmcs_read64(TSC_MULTIPLIER));
5825         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5826                 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5827                         u16 status = vmcs_read16(GUEST_INTR_STATUS);
5828                         pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5829                 }
5830                 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
5831                 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5832                         pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
5833                 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
5834         }
5835         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5836                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5837         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5838                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5839         n = vmcs_read32(CR3_TARGET_COUNT);
5840         for (i = 0; i + 1 < n; i += 4)
5841                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
5842                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
5843                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
5844         if (i < n)
5845                 pr_err("CR3 target%u=%016lx\n",
5846                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
5847         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5848                 pr_err("PLE Gap=%08x Window=%08x\n",
5849                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5850         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5851                 pr_err("Virtual processor ID = 0x%04x\n",
5852                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
5853 }
5854
5855 /*
5856  * The guest has exited.  See if we can fix it or if we need userspace
5857  * assistance.
5858  */
5859 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5860 {
5861         struct vcpu_vmx *vmx = to_vmx(vcpu);
5862         u32 exit_reason = vmx->exit_reason;
5863         u32 vectoring_info = vmx->idt_vectoring_info;
5864
5865         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
5866
5867         /*
5868          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5869          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5870          * querying dirty_bitmap, we only need to kick all vcpus out of guest
5871          * mode as if vcpus is in root mode, the PML buffer must has been
5872          * flushed already.
5873          */
5874         if (enable_pml)
5875                 vmx_flush_pml_buffer(vcpu);
5876
5877         /* If guest state is invalid, start emulating */
5878         if (vmx->emulation_required)
5879                 return handle_invalid_guest_state(vcpu);
5880
5881         if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
5882                 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
5883
5884         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5885                 dump_vmcs();
5886                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5887                 vcpu->run->fail_entry.hardware_entry_failure_reason
5888                         = exit_reason;
5889                 return 0;
5890         }
5891
5892         if (unlikely(vmx->fail)) {
5893                 dump_vmcs();
5894                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5895                 vcpu->run->fail_entry.hardware_entry_failure_reason
5896                         = vmcs_read32(VM_INSTRUCTION_ERROR);
5897                 return 0;
5898         }
5899
5900         /*
5901          * Note:
5902          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5903          * delivery event since it indicates guest is accessing MMIO.
5904          * The vm-exit can be triggered again after return to guest that
5905          * will cause infinite loop.
5906          */
5907         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5908                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5909                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
5910                         exit_reason != EXIT_REASON_PML_FULL &&
5911                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
5912                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5913                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5914                 vcpu->run->internal.ndata = 3;
5915                 vcpu->run->internal.data[0] = vectoring_info;
5916                 vcpu->run->internal.data[1] = exit_reason;
5917                 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5918                 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
5919                         vcpu->run->internal.ndata++;
5920                         vcpu->run->internal.data[3] =
5921                                 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5922                 }
5923                 return 0;
5924         }
5925
5926         if (unlikely(!enable_vnmi &&
5927                      vmx->loaded_vmcs->soft_vnmi_blocked)) {
5928                 if (vmx_interrupt_allowed(vcpu)) {
5929                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5930                 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5931                            vcpu->arch.nmi_pending) {
5932                         /*
5933                          * This CPU don't support us in finding the end of an
5934                          * NMI-blocked window if the guest runs with IRQs
5935                          * disabled. So we pull the trigger after 1 s of
5936                          * futile waiting, but inform the user about this.
5937                          */
5938                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5939                                "state on VCPU %d after 1 s timeout\n",
5940                                __func__, vcpu->vcpu_id);
5941                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5942                 }
5943         }
5944
5945         if (exit_reason < kvm_vmx_max_exit_handlers
5946             && kvm_vmx_exit_handlers[exit_reason])
5947                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5948         else {
5949                 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
5950                                 exit_reason);
5951                 dump_vmcs();
5952                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5953                 vcpu->run->internal.suberror =
5954                         KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
5955                 vcpu->run->internal.ndata = 1;
5956                 vcpu->run->internal.data[0] = exit_reason;
5957                 return 0;
5958         }
5959 }
5960
5961 /*
5962  * Software based L1D cache flush which is used when microcode providing
5963  * the cache control MSR is not loaded.
5964  *
5965  * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
5966  * flush it is required to read in 64 KiB because the replacement algorithm
5967  * is not exactly LRU. This could be sized at runtime via topology
5968  * information but as all relevant affected CPUs have 32KiB L1D cache size
5969  * there is no point in doing so.
5970  */
5971 static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
5972 {
5973         int size = PAGE_SIZE << L1D_CACHE_ORDER;
5974
5975         /*
5976          * This code is only executed when the the flush mode is 'cond' or
5977          * 'always'
5978          */
5979         if (static_branch_likely(&vmx_l1d_flush_cond)) {
5980                 bool flush_l1d;
5981
5982                 /*
5983                  * Clear the per-vcpu flush bit, it gets set again
5984                  * either from vcpu_run() or from one of the unsafe
5985                  * VMEXIT handlers.
5986                  */
5987                 flush_l1d = vcpu->arch.l1tf_flush_l1d;
5988                 vcpu->arch.l1tf_flush_l1d = false;
5989
5990                 /*
5991                  * Clear the per-cpu flush bit, it gets set again from
5992                  * the interrupt handlers.
5993                  */
5994                 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
5995                 kvm_clear_cpu_l1tf_flush_l1d();
5996
5997                 if (!flush_l1d)
5998                         return;
5999         }
6000
6001         vcpu->stat.l1d_flush++;
6002
6003         if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
6004                 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
6005                 return;
6006         }
6007
6008         asm volatile(
6009                 /* First ensure the pages are in the TLB */
6010                 "xorl   %%eax, %%eax\n"
6011                 ".Lpopulate_tlb:\n\t"
6012                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6013                 "addl   $4096, %%eax\n\t"
6014                 "cmpl   %%eax, %[size]\n\t"
6015                 "jne    .Lpopulate_tlb\n\t"
6016                 "xorl   %%eax, %%eax\n\t"
6017                 "cpuid\n\t"
6018                 /* Now fill the cache */
6019                 "xorl   %%eax, %%eax\n"
6020                 ".Lfill_cache:\n"
6021                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6022                 "addl   $64, %%eax\n\t"
6023                 "cmpl   %%eax, %[size]\n\t"
6024                 "jne    .Lfill_cache\n\t"
6025                 "lfence\n"
6026                 :: [flush_pages] "r" (vmx_l1d_flush_pages),
6027                     [size] "r" (size)
6028                 : "eax", "ebx", "ecx", "edx");
6029 }
6030
6031 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6032 {
6033         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6034
6035         if (is_guest_mode(vcpu) &&
6036                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
6037                 return;
6038
6039         if (irr == -1 || tpr < irr) {
6040                 vmcs_write32(TPR_THRESHOLD, 0);
6041                 return;
6042         }
6043
6044         vmcs_write32(TPR_THRESHOLD, irr);
6045 }
6046
6047 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
6048 {
6049         struct vcpu_vmx *vmx = to_vmx(vcpu);
6050         u32 sec_exec_control;
6051
6052         if (!lapic_in_kernel(vcpu))
6053                 return;
6054
6055         if (!flexpriority_enabled &&
6056             !cpu_has_vmx_virtualize_x2apic_mode())
6057                 return;
6058
6059         /* Postpone execution until vmcs01 is the current VMCS. */
6060         if (is_guest_mode(vcpu)) {
6061                 vmx->nested.change_vmcs01_virtual_apic_mode = true;
6062                 return;
6063         }
6064
6065         sec_exec_control = secondary_exec_controls_get(vmx);
6066         sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6067                               SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
6068
6069         switch (kvm_get_apic_mode(vcpu)) {
6070         case LAPIC_MODE_INVALID:
6071                 WARN_ONCE(true, "Invalid local APIC state");
6072         case LAPIC_MODE_DISABLED:
6073                 break;
6074         case LAPIC_MODE_XAPIC:
6075                 if (flexpriority_enabled) {
6076                         sec_exec_control |=
6077                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6078                         vmx_flush_tlb(vcpu, true);
6079                 }
6080                 break;
6081         case LAPIC_MODE_X2APIC:
6082                 if (cpu_has_vmx_virtualize_x2apic_mode())
6083                         sec_exec_control |=
6084                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6085                 break;
6086         }
6087         secondary_exec_controls_set(vmx, sec_exec_control);
6088
6089         vmx_update_msr_bitmap(vcpu);
6090 }
6091
6092 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
6093 {
6094         if (!is_guest_mode(vcpu)) {
6095                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
6096                 vmx_flush_tlb(vcpu, true);
6097         }
6098 }
6099
6100 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6101 {
6102         u16 status;
6103         u8 old;
6104
6105         if (max_isr == -1)
6106                 max_isr = 0;
6107
6108         status = vmcs_read16(GUEST_INTR_STATUS);
6109         old = status >> 8;
6110         if (max_isr != old) {
6111                 status &= 0xff;
6112                 status |= max_isr << 8;
6113                 vmcs_write16(GUEST_INTR_STATUS, status);
6114         }
6115 }
6116
6117 static void vmx_set_rvi(int vector)
6118 {
6119         u16 status;
6120         u8 old;
6121
6122         if (vector == -1)
6123                 vector = 0;
6124
6125         status = vmcs_read16(GUEST_INTR_STATUS);
6126         old = (u8)status & 0xff;
6127         if ((u8)vector != old) {
6128                 status &= ~0xff;
6129                 status |= (u8)vector;
6130                 vmcs_write16(GUEST_INTR_STATUS, status);
6131         }
6132 }
6133
6134 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6135 {
6136         /*
6137          * When running L2, updating RVI is only relevant when
6138          * vmcs12 virtual-interrupt-delivery enabled.
6139          * However, it can be enabled only when L1 also
6140          * intercepts external-interrupts and in that case
6141          * we should not update vmcs02 RVI but instead intercept
6142          * interrupt. Therefore, do nothing when running L2.
6143          */
6144         if (!is_guest_mode(vcpu))
6145                 vmx_set_rvi(max_irr);
6146 }
6147
6148 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6149 {
6150         struct vcpu_vmx *vmx = to_vmx(vcpu);
6151         int max_irr;
6152         bool max_irr_updated;
6153
6154         WARN_ON(!vcpu->arch.apicv_active);
6155         if (pi_test_on(&vmx->pi_desc)) {
6156                 pi_clear_on(&vmx->pi_desc);
6157                 /*
6158                  * IOMMU can write to PID.ON, so the barrier matters even on UP.
6159                  * But on x86 this is just a compiler barrier anyway.
6160                  */
6161                 smp_mb__after_atomic();
6162                 max_irr_updated =
6163                         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
6164
6165                 /*
6166                  * If we are running L2 and L1 has a new pending interrupt
6167                  * which can be injected, we should re-evaluate
6168                  * what should be done with this new L1 interrupt.
6169                  * If L1 intercepts external-interrupts, we should
6170                  * exit from L2 to L1. Otherwise, interrupt should be
6171                  * delivered directly to L2.
6172                  */
6173                 if (is_guest_mode(vcpu) && max_irr_updated) {
6174                         if (nested_exit_on_intr(vcpu))
6175                                 kvm_vcpu_exiting_guest_mode(vcpu);
6176                         else
6177                                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6178                 }
6179         } else {
6180                 max_irr = kvm_lapic_find_highest_irr(vcpu);
6181         }
6182         vmx_hwapic_irr_update(vcpu, max_irr);
6183         return max_irr;
6184 }
6185
6186 static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
6187 {
6188         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6189
6190         return pi_test_on(pi_desc) ||
6191                 (pi_test_sn(pi_desc) && !pi_is_pir_empty(pi_desc));
6192 }
6193
6194 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6195 {
6196         if (!kvm_vcpu_apicv_active(vcpu))
6197                 return;
6198
6199         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6200         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6201         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6202         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6203 }
6204
6205 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
6206 {
6207         struct vcpu_vmx *vmx = to_vmx(vcpu);
6208
6209         pi_clear_on(&vmx->pi_desc);
6210         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6211 }
6212
6213 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
6214 {
6215         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6216
6217         /* if exit due to PF check for async PF */
6218         if (is_page_fault(vmx->exit_intr_info))
6219                 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
6220
6221         /* Handle machine checks before interrupts are enabled */
6222         if (is_machine_check(vmx->exit_intr_info))
6223                 kvm_machine_check();
6224
6225         /* We need to handle NMIs before interrupts are enabled */
6226         if (is_nmi(vmx->exit_intr_info)) {
6227                 kvm_before_interrupt(&vmx->vcpu);
6228                 asm("int $2");
6229                 kvm_after_interrupt(&vmx->vcpu);
6230         }
6231 }
6232
6233 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
6234 {
6235         unsigned int vector;
6236         unsigned long entry;
6237 #ifdef CONFIG_X86_64
6238         unsigned long tmp;
6239 #endif
6240         gate_desc *desc;
6241         u32 intr_info;
6242
6243         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6244         if (WARN_ONCE(!is_external_intr(intr_info),
6245             "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6246                 return;
6247
6248         vector = intr_info & INTR_INFO_VECTOR_MASK;
6249         desc = (gate_desc *)host_idt_base + vector;
6250         entry = gate_offset(desc);
6251
6252         kvm_before_interrupt(vcpu);
6253
6254         asm volatile(
6255 #ifdef CONFIG_X86_64
6256                 "mov %%" _ASM_SP ", %[sp]\n\t"
6257                 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6258                 "push $%c[ss]\n\t"
6259                 "push %[sp]\n\t"
6260 #endif
6261                 "pushf\n\t"
6262                 __ASM_SIZE(push) " $%c[cs]\n\t"
6263                 CALL_NOSPEC
6264                 :
6265 #ifdef CONFIG_X86_64
6266                 [sp]"=&r"(tmp),
6267 #endif
6268                 ASM_CALL_CONSTRAINT
6269                 :
6270                 THUNK_TARGET(entry),
6271                 [ss]"i"(__KERNEL_DS),
6272                 [cs]"i"(__KERNEL_CS)
6273         );
6274
6275         kvm_after_interrupt(vcpu);
6276 }
6277 STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff);
6278
6279 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu)
6280 {
6281         struct vcpu_vmx *vmx = to_vmx(vcpu);
6282
6283         if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
6284                 handle_external_interrupt_irqoff(vcpu);
6285         else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)
6286                 handle_exception_nmi_irqoff(vmx);
6287 }
6288
6289 static bool vmx_has_emulated_msr(int index)
6290 {
6291         switch (index) {
6292         case MSR_IA32_SMBASE:
6293                 /*
6294                  * We cannot do SMM unless we can run the guest in big
6295                  * real mode.
6296                  */
6297                 return enable_unrestricted_guest || emulate_invalid_guest_state;
6298         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6299                 return nested;
6300         case MSR_AMD64_VIRT_SPEC_CTRL:
6301                 /* This is AMD only.  */
6302                 return false;
6303         default:
6304                 return true;
6305         }
6306 }
6307
6308 static bool vmx_pt_supported(void)
6309 {
6310         return pt_mode == PT_MODE_HOST_GUEST;
6311 }
6312
6313 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6314 {
6315         u32 exit_intr_info;
6316         bool unblock_nmi;
6317         u8 vector;
6318         bool idtv_info_valid;
6319
6320         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6321
6322         if (enable_vnmi) {
6323                 if (vmx->loaded_vmcs->nmi_known_unmasked)
6324                         return;
6325                 /*
6326                  * Can't use vmx->exit_intr_info since we're not sure what
6327                  * the exit reason is.
6328                  */
6329                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6330                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6331                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6332                 /*
6333                  * SDM 3: 27.7.1.2 (September 2008)
6334                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6335                  * a guest IRET fault.
6336                  * SDM 3: 23.2.2 (September 2008)
6337                  * Bit 12 is undefined in any of the following cases:
6338                  *  If the VM exit sets the valid bit in the IDT-vectoring
6339                  *   information field.
6340                  *  If the VM exit is due to a double fault.
6341                  */
6342                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6343                     vector != DF_VECTOR && !idtv_info_valid)
6344                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6345                                       GUEST_INTR_STATE_NMI);
6346                 else
6347                         vmx->loaded_vmcs->nmi_known_unmasked =
6348                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6349                                   & GUEST_INTR_STATE_NMI);
6350         } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6351                 vmx->loaded_vmcs->vnmi_blocked_time +=
6352                         ktime_to_ns(ktime_sub(ktime_get(),
6353                                               vmx->loaded_vmcs->entry_time));
6354 }
6355
6356 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6357                                       u32 idt_vectoring_info,
6358                                       int instr_len_field,
6359                                       int error_code_field)
6360 {
6361         u8 vector;
6362         int type;
6363         bool idtv_info_valid;
6364
6365         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6366
6367         vcpu->arch.nmi_injected = false;
6368         kvm_clear_exception_queue(vcpu);
6369         kvm_clear_interrupt_queue(vcpu);
6370
6371         if (!idtv_info_valid)
6372                 return;
6373
6374         kvm_make_request(KVM_REQ_EVENT, vcpu);
6375
6376         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6377         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6378
6379         switch (type) {
6380         case INTR_TYPE_NMI_INTR:
6381                 vcpu->arch.nmi_injected = true;
6382                 /*
6383                  * SDM 3: 27.7.1.2 (September 2008)
6384                  * Clear bit "block by NMI" before VM entry if a NMI
6385                  * delivery faulted.
6386                  */
6387                 vmx_set_nmi_mask(vcpu, false);
6388                 break;
6389         case INTR_TYPE_SOFT_EXCEPTION:
6390                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6391                 /* fall through */
6392         case INTR_TYPE_HARD_EXCEPTION:
6393                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6394                         u32 err = vmcs_read32(error_code_field);
6395                         kvm_requeue_exception_e(vcpu, vector, err);
6396                 } else
6397                         kvm_requeue_exception(vcpu, vector);
6398                 break;
6399         case INTR_TYPE_SOFT_INTR:
6400                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6401                 /* fall through */
6402         case INTR_TYPE_EXT_INTR:
6403                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6404                 break;
6405         default:
6406                 break;
6407         }
6408 }
6409
6410 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6411 {
6412         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6413                                   VM_EXIT_INSTRUCTION_LEN,
6414                                   IDT_VECTORING_ERROR_CODE);
6415 }
6416
6417 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6418 {
6419         __vmx_complete_interrupts(vcpu,
6420                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6421                                   VM_ENTRY_INSTRUCTION_LEN,
6422                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6423
6424         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6425 }
6426
6427 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6428 {
6429         int i, nr_msrs;
6430         struct perf_guest_switch_msr *msrs;
6431
6432         msrs = perf_guest_get_msrs(&nr_msrs);
6433
6434         if (!msrs)
6435                 return;
6436
6437         for (i = 0; i < nr_msrs; i++)
6438                 if (msrs[i].host == msrs[i].guest)
6439                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6440                 else
6441                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6442                                         msrs[i].host, false);
6443 }
6444
6445 static void atomic_switch_umwait_control_msr(struct vcpu_vmx *vmx)
6446 {
6447         u32 host_umwait_control;
6448
6449         if (!vmx_has_waitpkg(vmx))
6450                 return;
6451
6452         host_umwait_control = get_umwait_control_msr();
6453
6454         if (vmx->msr_ia32_umwait_control != host_umwait_control)
6455                 add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL,
6456                         vmx->msr_ia32_umwait_control,
6457                         host_umwait_control, false);
6458         else
6459                 clear_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL);
6460 }
6461
6462 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
6463 {
6464         struct vcpu_vmx *vmx = to_vmx(vcpu);
6465         u64 tscl;
6466         u32 delta_tsc;
6467
6468         if (vmx->req_immediate_exit) {
6469                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6470                 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6471         } else if (vmx->hv_deadline_tsc != -1) {
6472                 tscl = rdtsc();
6473                 if (vmx->hv_deadline_tsc > tscl)
6474                         /* set_hv_timer ensures the delta fits in 32-bits */
6475                         delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6476                                 cpu_preemption_timer_multi);
6477                 else
6478                         delta_tsc = 0;
6479
6480                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6481                 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6482         } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6483                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6484                 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
6485         }
6486 }
6487
6488 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
6489 {
6490         if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6491                 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6492                 vmcs_writel(HOST_RSP, host_rsp);
6493         }
6494 }
6495
6496 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched);
6497
6498 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6499 {
6500         struct vcpu_vmx *vmx = to_vmx(vcpu);
6501         unsigned long cr3, cr4;
6502
6503         /* Record the guest's net vcpu time for enforced NMI injections. */
6504         if (unlikely(!enable_vnmi &&
6505                      vmx->loaded_vmcs->soft_vnmi_blocked))
6506                 vmx->loaded_vmcs->entry_time = ktime_get();
6507
6508         /* Don't enter VMX if guest state is invalid, let the exit handler
6509            start emulation until we arrive back to a valid state */
6510         if (vmx->emulation_required)
6511                 return;
6512
6513         if (vmx->ple_window_dirty) {
6514                 vmx->ple_window_dirty = false;
6515                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6516         }
6517
6518         if (vmx->nested.need_vmcs12_to_shadow_sync)
6519                 nested_sync_vmcs12_to_shadow(vcpu);
6520
6521         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6522                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6523         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6524                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6525
6526         cr3 = __get_current_cr3_fast();
6527         if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6528                 vmcs_writel(HOST_CR3, cr3);
6529                 vmx->loaded_vmcs->host_state.cr3 = cr3;
6530         }
6531
6532         cr4 = cr4_read_shadow();
6533         if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6534                 vmcs_writel(HOST_CR4, cr4);
6535                 vmx->loaded_vmcs->host_state.cr4 = cr4;
6536         }
6537
6538         /* When single-stepping over STI and MOV SS, we must clear the
6539          * corresponding interruptibility bits in the guest state. Otherwise
6540          * vmentry fails as it then expects bit 14 (BS) in pending debug
6541          * exceptions being set, but that's not correct for the guest debugging
6542          * case. */
6543         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6544                 vmx_set_interrupt_shadow(vcpu, 0);
6545
6546         kvm_load_guest_xcr0(vcpu);
6547
6548         if (static_cpu_has(X86_FEATURE_PKU) &&
6549             kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
6550             vcpu->arch.pkru != vmx->host_pkru)
6551                 __write_pkru(vcpu->arch.pkru);
6552
6553         pt_guest_enter(vmx);
6554
6555         atomic_switch_perf_msrs(vmx);
6556         atomic_switch_umwait_control_msr(vmx);
6557
6558         if (enable_preemption_timer)
6559                 vmx_update_hv_timer(vcpu);
6560
6561         if (lapic_in_kernel(vcpu) &&
6562                 vcpu->arch.apic->lapic_timer.timer_advance_ns)
6563                 kvm_wait_lapic_expire(vcpu);
6564
6565         /*
6566          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6567          * it's non-zero. Since vmentry is serialising on affected CPUs, there
6568          * is no need to worry about the conditional branch over the wrmsr
6569          * being speculatively taken.
6570          */
6571         x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6572
6573         /* L1D Flush includes CPU buffer clear to mitigate MDS */
6574         if (static_branch_unlikely(&vmx_l1d_should_flush))
6575                 vmx_l1d_flush(vcpu);
6576         else if (static_branch_unlikely(&mds_user_clear))
6577                 mds_clear_cpu_buffers();
6578
6579         if (vcpu->arch.cr2 != read_cr2())
6580                 write_cr2(vcpu->arch.cr2);
6581
6582         vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6583                                    vmx->loaded_vmcs->launched);
6584
6585         vcpu->arch.cr2 = read_cr2();
6586
6587         /*
6588          * We do not use IBRS in the kernel. If this vCPU has used the
6589          * SPEC_CTRL MSR it may have left it on; save the value and
6590          * turn it off. This is much more efficient than blindly adding
6591          * it to the atomic save/restore list. Especially as the former
6592          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6593          *
6594          * For non-nested case:
6595          * If the L01 MSR bitmap does not intercept the MSR, then we need to
6596          * save it.
6597          *
6598          * For nested case:
6599          * If the L02 MSR bitmap does not intercept the MSR, then we need to
6600          * save it.
6601          */
6602         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6603                 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
6604
6605         x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
6606
6607         /* All fields are clean at this point */
6608         if (static_branch_unlikely(&enable_evmcs))
6609                 current_evmcs->hv_clean_fields |=
6610                         HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
6611
6612         if (static_branch_unlikely(&enable_evmcs))
6613                 current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index;
6614
6615         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6616         if (vmx->host_debugctlmsr)
6617                 update_debugctlmsr(vmx->host_debugctlmsr);
6618
6619 #ifndef CONFIG_X86_64
6620         /*
6621          * The sysexit path does not restore ds/es, so we must set them to
6622          * a reasonable value ourselves.
6623          *
6624          * We can't defer this to vmx_prepare_switch_to_host() since that
6625          * function may be executed in interrupt context, which saves and
6626          * restore segments around it, nullifying its effect.
6627          */
6628         loadsegment(ds, __USER_DS);
6629         loadsegment(es, __USER_DS);
6630 #endif
6631
6632         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6633                                   | (1 << VCPU_EXREG_RFLAGS)
6634                                   | (1 << VCPU_EXREG_PDPTR)
6635                                   | (1 << VCPU_EXREG_SEGMENTS)
6636                                   | (1 << VCPU_EXREG_CR3));
6637         vcpu->arch.regs_dirty = 0;
6638
6639         pt_guest_exit(vmx);
6640
6641         /*
6642          * eager fpu is enabled if PKEY is supported and CR4 is switched
6643          * back on host, so it is safe to read guest PKRU from current
6644          * XSAVE.
6645          */
6646         if (static_cpu_has(X86_FEATURE_PKU) &&
6647             kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
6648                 vcpu->arch.pkru = rdpkru();
6649                 if (vcpu->arch.pkru != vmx->host_pkru)
6650                         __write_pkru(vmx->host_pkru);
6651         }
6652
6653         kvm_put_guest_xcr0(vcpu);
6654
6655         vmx->nested.nested_run_pending = 0;
6656         vmx->idt_vectoring_info = 0;
6657
6658         vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
6659         if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
6660                 kvm_machine_check();
6661
6662         if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6663                 return;
6664
6665         vmx->loaded_vmcs->launched = 1;
6666         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6667
6668         vmx_recover_nmi_blocking(vmx);
6669         vmx_complete_interrupts(vmx);
6670 }
6671
6672 static struct kvm *vmx_vm_alloc(void)
6673 {
6674         struct kvm_vmx *kvm_vmx = __vmalloc(sizeof(struct kvm_vmx),
6675                                             GFP_KERNEL_ACCOUNT | __GFP_ZERO,
6676                                             PAGE_KERNEL);
6677         return &kvm_vmx->kvm;
6678 }
6679
6680 static void vmx_vm_free(struct kvm *kvm)
6681 {
6682         kfree(kvm->arch.hyperv.hv_pa_pg);
6683         vfree(to_kvm_vmx(kvm));
6684 }
6685
6686 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6687 {
6688         struct vcpu_vmx *vmx = to_vmx(vcpu);
6689
6690         if (enable_pml)
6691                 vmx_destroy_pml_buffer(vmx);
6692         free_vpid(vmx->vpid);
6693         nested_vmx_free_vcpu(vcpu);
6694         free_loaded_vmcs(vmx->loaded_vmcs);
6695         kfree(vmx->guest_msrs);
6696         kvm_vcpu_uninit(vcpu);
6697         kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu);
6698         kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
6699         kmem_cache_free(kvm_vcpu_cache, vmx);
6700 }
6701
6702 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6703 {
6704         int err;
6705         struct vcpu_vmx *vmx;
6706         unsigned long *msr_bitmap;
6707         int cpu;
6708
6709         BUILD_BUG_ON_MSG(offsetof(struct vcpu_vmx, vcpu) != 0,
6710                 "struct kvm_vcpu must be at offset 0 for arch usercopy region");
6711
6712         vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL_ACCOUNT);
6713         if (!vmx)
6714                 return ERR_PTR(-ENOMEM);
6715
6716         vmx->vcpu.arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
6717                         GFP_KERNEL_ACCOUNT);
6718         if (!vmx->vcpu.arch.user_fpu) {
6719                 printk(KERN_ERR "kvm: failed to allocate kvm userspace's fpu\n");
6720                 err = -ENOMEM;
6721                 goto free_partial_vcpu;
6722         }
6723
6724         vmx->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
6725                         GFP_KERNEL_ACCOUNT);
6726         if (!vmx->vcpu.arch.guest_fpu) {
6727                 printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n");
6728                 err = -ENOMEM;
6729                 goto free_user_fpu;
6730         }
6731
6732         vmx->vpid = allocate_vpid();
6733
6734         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6735         if (err)
6736                 goto free_vcpu;
6737
6738         err = -ENOMEM;
6739
6740         /*
6741          * If PML is turned on, failure on enabling PML just results in failure
6742          * of creating the vcpu, therefore we can simplify PML logic (by
6743          * avoiding dealing with cases, such as enabling PML partially on vcpus
6744          * for the guest, etc.
6745          */
6746         if (enable_pml) {
6747                 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
6748                 if (!vmx->pml_pg)
6749                         goto uninit_vcpu;
6750         }
6751
6752         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL_ACCOUNT);
6753         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
6754                      > PAGE_SIZE);
6755
6756         if (!vmx->guest_msrs)
6757                 goto free_pml;
6758
6759         err = alloc_loaded_vmcs(&vmx->vmcs01);
6760         if (err < 0)
6761                 goto free_msrs;
6762
6763         msr_bitmap = vmx->vmcs01.msr_bitmap;
6764         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
6765         vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
6766         vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
6767         vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6768         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6769         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6770         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
6771         if (kvm_cstate_in_guest(kvm)) {
6772                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R);
6773                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6774                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6775                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6776         }
6777         vmx->msr_bitmap_mode = 0;
6778
6779         vmx->loaded_vmcs = &vmx->vmcs01;
6780         cpu = get_cpu();
6781         vmx_vcpu_load(&vmx->vcpu, cpu);
6782         vmx->vcpu.cpu = cpu;
6783         vmx_vcpu_setup(vmx);
6784         vmx_vcpu_put(&vmx->vcpu);
6785         put_cpu();
6786         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
6787                 err = alloc_apic_access_page(kvm);
6788                 if (err)
6789                         goto free_vmcs;
6790         }
6791
6792         if (enable_ept && !enable_unrestricted_guest) {
6793                 err = init_rmode_identity_map(kvm);
6794                 if (err)
6795                         goto free_vmcs;
6796         }
6797
6798         if (nested)
6799                 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
6800                                            vmx_capability.ept,
6801                                            kvm_vcpu_apicv_active(&vmx->vcpu));
6802         else
6803                 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
6804
6805         vmx->nested.posted_intr_nv = -1;
6806         vmx->nested.current_vmptr = -1ull;
6807
6808         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
6809
6810         /*
6811          * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
6812          * or POSTED_INTR_WAKEUP_VECTOR.
6813          */
6814         vmx->pi_desc.nv = POSTED_INTR_VECTOR;
6815         vmx->pi_desc.sn = 1;
6816
6817         vmx->ept_pointer = INVALID_PAGE;
6818
6819         return &vmx->vcpu;
6820
6821 free_vmcs:
6822         free_loaded_vmcs(vmx->loaded_vmcs);
6823 free_msrs:
6824         kfree(vmx->guest_msrs);
6825 free_pml:
6826         vmx_destroy_pml_buffer(vmx);
6827 uninit_vcpu:
6828         kvm_vcpu_uninit(&vmx->vcpu);
6829 free_vcpu:
6830         free_vpid(vmx->vpid);
6831         kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
6832 free_user_fpu:
6833         kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu);
6834 free_partial_vcpu:
6835         kmem_cache_free(kvm_vcpu_cache, vmx);
6836         return ERR_PTR(err);
6837 }
6838
6839 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6840 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6841
6842 static int vmx_vm_init(struct kvm *kvm)
6843 {
6844         spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
6845
6846         if (!ple_gap)
6847                 kvm->arch.pause_in_guest = true;
6848
6849         if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6850                 switch (l1tf_mitigation) {
6851                 case L1TF_MITIGATION_OFF:
6852                 case L1TF_MITIGATION_FLUSH_NOWARN:
6853                         /* 'I explicitly don't care' is set */
6854                         break;
6855                 case L1TF_MITIGATION_FLUSH:
6856                 case L1TF_MITIGATION_FLUSH_NOSMT:
6857                 case L1TF_MITIGATION_FULL:
6858                         /*
6859                          * Warn upon starting the first VM in a potentially
6860                          * insecure environment.
6861                          */
6862                         if (sched_smt_active())
6863                                 pr_warn_once(L1TF_MSG_SMT);
6864                         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6865                                 pr_warn_once(L1TF_MSG_L1D);
6866                         break;
6867                 case L1TF_MITIGATION_FULL_FORCE:
6868                         /* Flush is enforced */
6869                         break;
6870                 }
6871         }
6872         return 0;
6873 }
6874
6875 static int __init vmx_check_processor_compat(void)
6876 {
6877         struct vmcs_config vmcs_conf;
6878         struct vmx_capability vmx_cap;
6879
6880         if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
6881                 return -EIO;
6882         if (nested)
6883                 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept,
6884                                            enable_apicv);
6885         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6886                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6887                                 smp_processor_id());
6888                 return -EIO;
6889         }
6890         return 0;
6891 }
6892
6893 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6894 {
6895         u8 cache;
6896         u64 ipat = 0;
6897
6898         /* For VT-d and EPT combination
6899          * 1. MMIO: always map as UC
6900          * 2. EPT with VT-d:
6901          *   a. VT-d without snooping control feature: can't guarantee the
6902          *      result, try to trust guest.
6903          *   b. VT-d with snooping control feature: snooping control feature of
6904          *      VT-d engine can guarantee the cache correctness. Just set it
6905          *      to WB to keep consistent with host. So the same as item 3.
6906          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6907          *    consistent with host MTRR
6908          */
6909         if (is_mmio) {
6910                 cache = MTRR_TYPE_UNCACHABLE;
6911                 goto exit;
6912         }
6913
6914         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
6915                 ipat = VMX_EPT_IPAT_BIT;
6916                 cache = MTRR_TYPE_WRBACK;
6917                 goto exit;
6918         }
6919
6920         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
6921                 ipat = VMX_EPT_IPAT_BIT;
6922                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
6923                         cache = MTRR_TYPE_WRBACK;
6924                 else
6925                         cache = MTRR_TYPE_UNCACHABLE;
6926                 goto exit;
6927         }
6928
6929         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
6930
6931 exit:
6932         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
6933 }
6934
6935 static int vmx_get_lpage_level(void)
6936 {
6937         if (enable_ept && !cpu_has_vmx_ept_1g_page())
6938                 return PT_DIRECTORY_LEVEL;
6939         else
6940                 /* For shadow and EPT supported 1GB page */
6941                 return PT_PDPE_LEVEL;
6942 }
6943
6944 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx)
6945 {
6946         /*
6947          * These bits in the secondary execution controls field
6948          * are dynamic, the others are mostly based on the hypervisor
6949          * architecture and the guest's CPUID.  Do not touch the
6950          * dynamic bits.
6951          */
6952         u32 mask =
6953                 SECONDARY_EXEC_SHADOW_VMCS |
6954                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
6955                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6956                 SECONDARY_EXEC_DESC;
6957
6958         u32 new_ctl = vmx->secondary_exec_control;
6959         u32 cur_ctl = secondary_exec_controls_get(vmx);
6960
6961         secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
6962 }
6963
6964 /*
6965  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
6966  * (indicating "allowed-1") if they are supported in the guest's CPUID.
6967  */
6968 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
6969 {
6970         struct vcpu_vmx *vmx = to_vmx(vcpu);
6971         struct kvm_cpuid_entry2 *entry;
6972
6973         vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
6974         vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
6975
6976 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
6977         if (entry && (entry->_reg & (_cpuid_mask)))                     \
6978                 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask);     \
6979 } while (0)
6980
6981         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
6982         cr4_fixed1_update(X86_CR4_VME,        edx, bit(X86_FEATURE_VME));
6983         cr4_fixed1_update(X86_CR4_PVI,        edx, bit(X86_FEATURE_VME));
6984         cr4_fixed1_update(X86_CR4_TSD,        edx, bit(X86_FEATURE_TSC));
6985         cr4_fixed1_update(X86_CR4_DE,         edx, bit(X86_FEATURE_DE));
6986         cr4_fixed1_update(X86_CR4_PSE,        edx, bit(X86_FEATURE_PSE));
6987         cr4_fixed1_update(X86_CR4_PAE,        edx, bit(X86_FEATURE_PAE));
6988         cr4_fixed1_update(X86_CR4_MCE,        edx, bit(X86_FEATURE_MCE));
6989         cr4_fixed1_update(X86_CR4_PGE,        edx, bit(X86_FEATURE_PGE));
6990         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, bit(X86_FEATURE_FXSR));
6991         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
6992         cr4_fixed1_update(X86_CR4_VMXE,       ecx, bit(X86_FEATURE_VMX));
6993         cr4_fixed1_update(X86_CR4_SMXE,       ecx, bit(X86_FEATURE_SMX));
6994         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, bit(X86_FEATURE_PCID));
6995         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, bit(X86_FEATURE_XSAVE));
6996
6997         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6998         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, bit(X86_FEATURE_FSGSBASE));
6999         cr4_fixed1_update(X86_CR4_SMEP,       ebx, bit(X86_FEATURE_SMEP));
7000         cr4_fixed1_update(X86_CR4_SMAP,       ebx, bit(X86_FEATURE_SMAP));
7001         cr4_fixed1_update(X86_CR4_PKE,        ecx, bit(X86_FEATURE_PKU));
7002         cr4_fixed1_update(X86_CR4_UMIP,       ecx, bit(X86_FEATURE_UMIP));
7003
7004 #undef cr4_fixed1_update
7005 }
7006
7007 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
7008 {
7009         struct vcpu_vmx *vmx = to_vmx(vcpu);
7010
7011         if (kvm_mpx_supported()) {
7012                 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
7013
7014                 if (mpx_enabled) {
7015                         vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
7016                         vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
7017                 } else {
7018                         vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
7019                         vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
7020                 }
7021         }
7022 }
7023
7024 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
7025 {
7026         struct vcpu_vmx *vmx = to_vmx(vcpu);
7027         struct kvm_cpuid_entry2 *best = NULL;
7028         int i;
7029
7030         for (i = 0; i < PT_CPUID_LEAVES; i++) {
7031                 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
7032                 if (!best)
7033                         return;
7034                 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
7035                 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
7036                 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
7037                 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
7038         }
7039
7040         /* Get the number of configurable Address Ranges for filtering */
7041         vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
7042                                                 PT_CAP_num_address_ranges);
7043
7044         /* Initialize and clear the no dependency bits */
7045         vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
7046                         RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
7047
7048         /*
7049          * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
7050          * will inject an #GP
7051          */
7052         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
7053                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
7054
7055         /*
7056          * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
7057          * PSBFreq can be set
7058          */
7059         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
7060                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
7061                                 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
7062
7063         /*
7064          * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
7065          * MTCFreq can be set
7066          */
7067         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
7068                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
7069                                 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
7070
7071         /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
7072         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
7073                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
7074                                                         RTIT_CTL_PTW_EN);
7075
7076         /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7077         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
7078                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
7079
7080         /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7081         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
7082                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
7083
7084         /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */
7085         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
7086                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
7087
7088         /* unmask address range configure area */
7089         for (i = 0; i < vmx->pt_desc.addr_range; i++)
7090                 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
7091 }
7092
7093 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7094 {
7095         struct vcpu_vmx *vmx = to_vmx(vcpu);
7096
7097         if (cpu_has_secondary_exec_ctrls()) {
7098                 vmx_compute_secondary_exec_control(vmx);
7099                 vmcs_set_secondary_exec_control(vmx);
7100         }
7101
7102         if (nested_vmx_allowed(vcpu))
7103                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7104                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7105         else
7106                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7107                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7108
7109         if (nested_vmx_allowed(vcpu)) {
7110                 nested_vmx_cr_fixed1_bits_update(vcpu);
7111                 nested_vmx_entry_exit_ctls_update(vcpu);
7112         }
7113
7114         if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7115                         guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7116                 update_intel_pt_cfg(vcpu);
7117 }
7118
7119 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7120 {
7121         if (func == 1 && nested)
7122                 entry->ecx |= bit(X86_FEATURE_VMX);
7123 }
7124
7125 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
7126 {
7127         to_vmx(vcpu)->req_immediate_exit = true;
7128 }
7129
7130 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7131                                struct x86_instruction_info *info,
7132                                enum x86_intercept_stage stage)
7133 {
7134         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7135         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7136
7137         /*
7138          * RDPID causes #UD if disabled through secondary execution controls.
7139          * Because it is marked as EmulateOnUD, we need to intercept it here.
7140          */
7141         if (info->intercept == x86_intercept_rdtscp &&
7142             !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
7143                 ctxt->exception.vector = UD_VECTOR;
7144                 ctxt->exception.error_code_valid = false;
7145                 return X86EMUL_PROPAGATE_FAULT;
7146         }
7147
7148         /* TODO: check more intercepts... */
7149         return X86EMUL_CONTINUE;
7150 }
7151
7152 #ifdef CONFIG_X86_64
7153 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7154 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7155                                   u64 divisor, u64 *result)
7156 {
7157         u64 low = a << shift, high = a >> (64 - shift);
7158
7159         /* To avoid the overflow on divq */
7160         if (high >= divisor)
7161                 return 1;
7162
7163         /* Low hold the result, high hold rem which is discarded */
7164         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7165             "rm" (divisor), "0" (low), "1" (high));
7166         *result = low;
7167
7168         return 0;
7169 }
7170
7171 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7172                             bool *expired)
7173 {
7174         struct vcpu_vmx *vmx;
7175         u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
7176         struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
7177
7178         if (kvm_mwait_in_guest(vcpu->kvm) ||
7179                 kvm_can_post_timer_interrupt(vcpu))
7180                 return -EOPNOTSUPP;
7181
7182         vmx = to_vmx(vcpu);
7183         tscl = rdtsc();
7184         guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7185         delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
7186         lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7187                                                     ktimer->timer_advance_ns);
7188
7189         if (delta_tsc > lapic_timer_advance_cycles)
7190                 delta_tsc -= lapic_timer_advance_cycles;
7191         else
7192                 delta_tsc = 0;
7193
7194         /* Convert to host delta tsc if tsc scaling is enabled */
7195         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
7196             delta_tsc && u64_shl_div_u64(delta_tsc,
7197                                 kvm_tsc_scaling_ratio_frac_bits,
7198                                 vcpu->arch.tsc_scaling_ratio, &delta_tsc))
7199                 return -ERANGE;
7200
7201         /*
7202          * If the delta tsc can't fit in the 32 bit after the multi shift,
7203          * we can't use the preemption timer.
7204          * It's possible that it fits on later vmentries, but checking
7205          * on every vmentry is costly so we just use an hrtimer.
7206          */
7207         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7208                 return -ERANGE;
7209
7210         vmx->hv_deadline_tsc = tscl + delta_tsc;
7211         *expired = !delta_tsc;
7212         return 0;
7213 }
7214
7215 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7216 {
7217         to_vmx(vcpu)->hv_deadline_tsc = -1;
7218 }
7219 #endif
7220
7221 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
7222 {
7223         if (!kvm_pause_in_guest(vcpu->kvm))
7224                 shrink_ple_window(vcpu);
7225 }
7226
7227 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
7228                                      struct kvm_memory_slot *slot)
7229 {
7230         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
7231         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
7232 }
7233
7234 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
7235                                        struct kvm_memory_slot *slot)
7236 {
7237         kvm_mmu_slot_set_dirty(kvm, slot);
7238 }
7239
7240 static void vmx_flush_log_dirty(struct kvm *kvm)
7241 {
7242         kvm_flush_pml_buffers(kvm);
7243 }
7244
7245 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
7246 {
7247         struct vmcs12 *vmcs12;
7248         struct vcpu_vmx *vmx = to_vmx(vcpu);
7249         gpa_t gpa, dst;
7250
7251         if (is_guest_mode(vcpu)) {
7252                 WARN_ON_ONCE(vmx->nested.pml_full);
7253
7254                 /*
7255                  * Check if PML is enabled for the nested guest.
7256                  * Whether eptp bit 6 is set is already checked
7257                  * as part of A/D emulation.
7258                  */
7259                 vmcs12 = get_vmcs12(vcpu);
7260                 if (!nested_cpu_has_pml(vmcs12))
7261                         return 0;
7262
7263                 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
7264                         vmx->nested.pml_full = true;
7265                         return 1;
7266                 }
7267
7268                 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
7269                 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index;
7270
7271                 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa,
7272                                          offset_in_page(dst), sizeof(gpa)))
7273                         return 0;
7274
7275                 vmcs12->guest_pml_index--;
7276         }
7277
7278         return 0;
7279 }
7280
7281 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
7282                                            struct kvm_memory_slot *memslot,
7283                                            gfn_t offset, unsigned long mask)
7284 {
7285         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
7286 }
7287
7288 static void __pi_post_block(struct kvm_vcpu *vcpu)
7289 {
7290         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7291         struct pi_desc old, new;
7292         unsigned int dest;
7293
7294         do {
7295                 old.control = new.control = pi_desc->control;
7296                 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
7297                      "Wakeup handler not enabled while the VCPU is blocked\n");
7298
7299                 dest = cpu_physical_id(vcpu->cpu);
7300
7301                 if (x2apic_enabled())
7302                         new.ndst = dest;
7303                 else
7304                         new.ndst = (dest << 8) & 0xFF00;
7305
7306                 /* set 'NV' to 'notification vector' */
7307                 new.nv = POSTED_INTR_VECTOR;
7308         } while (cmpxchg64(&pi_desc->control, old.control,
7309                            new.control) != old.control);
7310
7311         if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
7312                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7313                 list_del(&vcpu->blocked_vcpu_list);
7314                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7315                 vcpu->pre_pcpu = -1;
7316         }
7317 }
7318
7319 /*
7320  * This routine does the following things for vCPU which is going
7321  * to be blocked if VT-d PI is enabled.
7322  * - Store the vCPU to the wakeup list, so when interrupts happen
7323  *   we can find the right vCPU to wake up.
7324  * - Change the Posted-interrupt descriptor as below:
7325  *      'NDST' <-- vcpu->pre_pcpu
7326  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
7327  * - If 'ON' is set during this process, which means at least one
7328  *   interrupt is posted for this vCPU, we cannot block it, in
7329  *   this case, return 1, otherwise, return 0.
7330  *
7331  */
7332 static int pi_pre_block(struct kvm_vcpu *vcpu)
7333 {
7334         unsigned int dest;
7335         struct pi_desc old, new;
7336         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7337
7338         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
7339                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
7340                 !kvm_vcpu_apicv_active(vcpu))
7341                 return 0;
7342
7343         WARN_ON(irqs_disabled());
7344         local_irq_disable();
7345         if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
7346                 vcpu->pre_pcpu = vcpu->cpu;
7347                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7348                 list_add_tail(&vcpu->blocked_vcpu_list,
7349                               &per_cpu(blocked_vcpu_on_cpu,
7350                                        vcpu->pre_pcpu));
7351                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7352         }
7353
7354         do {
7355                 old.control = new.control = pi_desc->control;
7356
7357                 WARN((pi_desc->sn == 1),
7358                      "Warning: SN field of posted-interrupts "
7359                      "is set before blocking\n");
7360
7361                 /*
7362                  * Since vCPU can be preempted during this process,
7363                  * vcpu->cpu could be different with pre_pcpu, we
7364                  * need to set pre_pcpu as the destination of wakeup
7365                  * notification event, then we can find the right vCPU
7366                  * to wakeup in wakeup handler if interrupts happen
7367                  * when the vCPU is in blocked state.
7368                  */
7369                 dest = cpu_physical_id(vcpu->pre_pcpu);
7370
7371                 if (x2apic_enabled())
7372                         new.ndst = dest;
7373                 else
7374                         new.ndst = (dest << 8) & 0xFF00;
7375
7376                 /* set 'NV' to 'wakeup vector' */
7377                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
7378         } while (cmpxchg64(&pi_desc->control, old.control,
7379                            new.control) != old.control);
7380
7381         /* We should not block the vCPU if an interrupt is posted for it.  */
7382         if (pi_test_on(pi_desc) == 1)
7383                 __pi_post_block(vcpu);
7384
7385         local_irq_enable();
7386         return (vcpu->pre_pcpu == -1);
7387 }
7388
7389 static int vmx_pre_block(struct kvm_vcpu *vcpu)
7390 {
7391         if (pi_pre_block(vcpu))
7392                 return 1;
7393
7394         if (kvm_lapic_hv_timer_in_use(vcpu))
7395                 kvm_lapic_switch_to_sw_timer(vcpu);
7396
7397         return 0;
7398 }
7399
7400 static void pi_post_block(struct kvm_vcpu *vcpu)
7401 {
7402         if (vcpu->pre_pcpu == -1)
7403                 return;
7404
7405         WARN_ON(irqs_disabled());
7406         local_irq_disable();
7407         __pi_post_block(vcpu);
7408         local_irq_enable();
7409 }
7410
7411 static void vmx_post_block(struct kvm_vcpu *vcpu)
7412 {
7413         if (kvm_x86_ops->set_hv_timer)
7414                 kvm_lapic_switch_to_hv_timer(vcpu);
7415
7416         pi_post_block(vcpu);
7417 }
7418
7419 /*
7420  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
7421  *
7422  * @kvm: kvm
7423  * @host_irq: host irq of the interrupt
7424  * @guest_irq: gsi of the interrupt
7425  * @set: set or unset PI
7426  * returns 0 on success, < 0 on failure
7427  */
7428 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
7429                               uint32_t guest_irq, bool set)
7430 {
7431         struct kvm_kernel_irq_routing_entry *e;
7432         struct kvm_irq_routing_table *irq_rt;
7433         struct kvm_lapic_irq irq;
7434         struct kvm_vcpu *vcpu;
7435         struct vcpu_data vcpu_info;
7436         int idx, ret = 0;
7437
7438         if (!kvm_arch_has_assigned_device(kvm) ||
7439                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7440                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
7441                 return 0;
7442
7443         idx = srcu_read_lock(&kvm->irq_srcu);
7444         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
7445         if (guest_irq >= irq_rt->nr_rt_entries ||
7446             hlist_empty(&irq_rt->map[guest_irq])) {
7447                 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
7448                              guest_irq, irq_rt->nr_rt_entries);
7449                 goto out;
7450         }
7451
7452         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
7453                 if (e->type != KVM_IRQ_ROUTING_MSI)
7454                         continue;
7455                 /*
7456                  * VT-d PI cannot support posting multicast/broadcast
7457                  * interrupts to a vCPU, we still use interrupt remapping
7458                  * for these kind of interrupts.
7459                  *
7460                  * For lowest-priority interrupts, we only support
7461                  * those with single CPU as the destination, e.g. user
7462                  * configures the interrupts via /proc/irq or uses
7463                  * irqbalance to make the interrupts single-CPU.
7464                  *
7465                  * We will support full lowest-priority interrupt later.
7466                  *
7467                  * In addition, we can only inject generic interrupts using
7468                  * the PI mechanism, refuse to route others through it.
7469                  */
7470
7471                 kvm_set_msi_irq(kvm, e, &irq);
7472                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) ||
7473                     !kvm_irq_is_postable(&irq)) {
7474                         /*
7475                          * Make sure the IRTE is in remapped mode if
7476                          * we don't handle it in posted mode.
7477                          */
7478                         ret = irq_set_vcpu_affinity(host_irq, NULL);
7479                         if (ret < 0) {
7480                                 printk(KERN_INFO
7481                                    "failed to back to remapped mode, irq: %u\n",
7482                                    host_irq);
7483                                 goto out;
7484                         }
7485
7486                         continue;
7487                 }
7488
7489                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
7490                 vcpu_info.vector = irq.vector;
7491
7492                 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
7493                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
7494
7495                 if (set)
7496                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
7497                 else
7498                         ret = irq_set_vcpu_affinity(host_irq, NULL);
7499
7500                 if (ret < 0) {
7501                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
7502                                         __func__);
7503                         goto out;
7504                 }
7505         }
7506
7507         ret = 0;
7508 out:
7509         srcu_read_unlock(&kvm->irq_srcu, idx);
7510         return ret;
7511 }
7512
7513 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7514 {
7515         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7516                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7517                         FEATURE_CONTROL_LMCE;
7518         else
7519                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7520                         ~FEATURE_CONTROL_LMCE;
7521 }
7522
7523 static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
7524 {
7525         /* we need a nested vmexit to enter SMM, postpone if run is pending */
7526         if (to_vmx(vcpu)->nested.nested_run_pending)
7527                 return 0;
7528         return 1;
7529 }
7530
7531 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7532 {
7533         struct vcpu_vmx *vmx = to_vmx(vcpu);
7534
7535         vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7536         if (vmx->nested.smm.guest_mode)
7537                 nested_vmx_vmexit(vcpu, -1, 0, 0);
7538
7539         vmx->nested.smm.vmxon = vmx->nested.vmxon;
7540         vmx->nested.vmxon = false;
7541         vmx_clear_hlt(vcpu);
7542         return 0;
7543 }
7544
7545 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
7546 {
7547         struct vcpu_vmx *vmx = to_vmx(vcpu);
7548         int ret;
7549
7550         if (vmx->nested.smm.vmxon) {
7551                 vmx->nested.vmxon = true;
7552                 vmx->nested.smm.vmxon = false;
7553         }
7554
7555         if (vmx->nested.smm.guest_mode) {
7556                 ret = nested_vmx_enter_non_root_mode(vcpu, false);
7557                 if (ret)
7558                         return ret;
7559
7560                 vmx->nested.smm.guest_mode = false;
7561         }
7562         return 0;
7563 }
7564
7565 static int enable_smi_window(struct kvm_vcpu *vcpu)
7566 {
7567         return 0;
7568 }
7569
7570 static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7571 {
7572         return false;
7573 }
7574
7575 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7576 {
7577         return to_vmx(vcpu)->nested.vmxon;
7578 }
7579
7580 static __init int hardware_setup(void)
7581 {
7582         unsigned long host_bndcfgs;
7583         struct desc_ptr dt;
7584         int r, i;
7585
7586         rdmsrl_safe(MSR_EFER, &host_efer);
7587
7588         store_idt(&dt);
7589         host_idt_base = dt.address;
7590
7591         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7592                 kvm_define_shared_msr(i, vmx_msr_index[i]);
7593
7594         if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7595                 return -EIO;
7596
7597         if (boot_cpu_has(X86_FEATURE_NX))
7598                 kvm_enable_efer_bits(EFER_NX);
7599
7600         if (boot_cpu_has(X86_FEATURE_MPX)) {
7601                 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7602                 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7603         }
7604
7605         if (boot_cpu_has(X86_FEATURE_XSAVES))
7606                 rdmsrl(MSR_IA32_XSS, host_xss);
7607
7608         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7609             !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7610                 enable_vpid = 0;
7611
7612         if (!cpu_has_vmx_ept() ||
7613             !cpu_has_vmx_ept_4levels() ||
7614             !cpu_has_vmx_ept_mt_wb() ||
7615             !cpu_has_vmx_invept_global())
7616                 enable_ept = 0;
7617
7618         if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7619                 enable_ept_ad_bits = 0;
7620
7621         if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7622                 enable_unrestricted_guest = 0;
7623
7624         if (!cpu_has_vmx_flexpriority())
7625                 flexpriority_enabled = 0;
7626
7627         if (!cpu_has_virtual_nmis())
7628                 enable_vnmi = 0;
7629
7630         /*
7631          * set_apic_access_page_addr() is used to reload apic access
7632          * page upon invalidation.  No need to do anything if not
7633          * using the APIC_ACCESS_ADDR VMCS field.
7634          */
7635         if (!flexpriority_enabled)
7636                 kvm_x86_ops->set_apic_access_page_addr = NULL;
7637
7638         if (!cpu_has_vmx_tpr_shadow())
7639                 kvm_x86_ops->update_cr8_intercept = NULL;
7640
7641         if (enable_ept && !cpu_has_vmx_ept_2m_page())
7642                 kvm_disable_largepages();
7643
7644 #if IS_ENABLED(CONFIG_HYPERV)
7645         if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7646             && enable_ept) {
7647                 kvm_x86_ops->tlb_remote_flush = hv_remote_flush_tlb;
7648                 kvm_x86_ops->tlb_remote_flush_with_range =
7649                                 hv_remote_flush_tlb_with_range;
7650         }
7651 #endif
7652
7653         if (!cpu_has_vmx_ple()) {
7654                 ple_gap = 0;
7655                 ple_window = 0;
7656                 ple_window_grow = 0;
7657                 ple_window_max = 0;
7658                 ple_window_shrink = 0;
7659         }
7660
7661         if (!cpu_has_vmx_apicv()) {
7662                 enable_apicv = 0;
7663                 kvm_x86_ops->sync_pir_to_irr = NULL;
7664         }
7665
7666         if (cpu_has_vmx_tsc_scaling()) {
7667                 kvm_has_tsc_control = true;
7668                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7669                 kvm_tsc_scaling_ratio_frac_bits = 48;
7670         }
7671
7672         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7673
7674         if (enable_ept)
7675                 vmx_enable_tdp();
7676         else
7677                 kvm_disable_tdp();
7678
7679         /*
7680          * Only enable PML when hardware supports PML feature, and both EPT
7681          * and EPT A/D bit features are enabled -- PML depends on them to work.
7682          */
7683         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7684                 enable_pml = 0;
7685
7686         if (!enable_pml) {
7687                 kvm_x86_ops->slot_enable_log_dirty = NULL;
7688                 kvm_x86_ops->slot_disable_log_dirty = NULL;
7689                 kvm_x86_ops->flush_log_dirty = NULL;
7690                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7691         }
7692
7693         if (!cpu_has_vmx_preemption_timer())
7694                 enable_preemption_timer = false;
7695
7696         if (enable_preemption_timer) {
7697                 u64 use_timer_freq = 5000ULL * 1000 * 1000;
7698                 u64 vmx_msr;
7699
7700                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7701                 cpu_preemption_timer_multi =
7702                         vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7703
7704                 if (tsc_khz)
7705                         use_timer_freq = (u64)tsc_khz * 1000;
7706                 use_timer_freq >>= cpu_preemption_timer_multi;
7707
7708                 /*
7709                  * KVM "disables" the preemption timer by setting it to its max
7710                  * value.  Don't use the timer if it might cause spurious exits
7711                  * at a rate faster than 0.1 Hz (of uninterrupted guest time).
7712                  */
7713                 if (use_timer_freq > 0xffffffffu / 10)
7714                         enable_preemption_timer = false;
7715         }
7716
7717         if (!enable_preemption_timer) {
7718                 kvm_x86_ops->set_hv_timer = NULL;
7719                 kvm_x86_ops->cancel_hv_timer = NULL;
7720                 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit;
7721         }
7722
7723         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
7724
7725         kvm_mce_cap_supported |= MCG_LMCE_P;
7726
7727         if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
7728                 return -EINVAL;
7729         if (!enable_ept || !cpu_has_vmx_intel_pt())
7730                 pt_mode = PT_MODE_SYSTEM;
7731
7732         if (nested) {
7733                 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
7734                                            vmx_capability.ept, enable_apicv);
7735
7736                 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
7737                 if (r)
7738                         return r;
7739         }
7740
7741         r = alloc_kvm_area();
7742         if (r)
7743                 nested_vmx_hardware_unsetup();
7744         return r;
7745 }
7746
7747 static __exit void hardware_unsetup(void)
7748 {
7749         if (nested)
7750                 nested_vmx_hardware_unsetup();
7751
7752         free_kvm_area();
7753 }
7754
7755 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
7756         .cpu_has_kvm_support = cpu_has_kvm_support,
7757         .disabled_by_bios = vmx_disabled_by_bios,
7758         .hardware_setup = hardware_setup,
7759         .hardware_unsetup = hardware_unsetup,
7760         .check_processor_compatibility = vmx_check_processor_compat,
7761         .hardware_enable = hardware_enable,
7762         .hardware_disable = hardware_disable,
7763         .cpu_has_accelerated_tpr = report_flexpriority,
7764         .has_emulated_msr = vmx_has_emulated_msr,
7765
7766         .vm_init = vmx_vm_init,
7767         .vm_alloc = vmx_vm_alloc,
7768         .vm_free = vmx_vm_free,
7769
7770         .vcpu_create = vmx_create_vcpu,
7771         .vcpu_free = vmx_free_vcpu,
7772         .vcpu_reset = vmx_vcpu_reset,
7773
7774         .prepare_guest_switch = vmx_prepare_switch_to_guest,
7775         .vcpu_load = vmx_vcpu_load,
7776         .vcpu_put = vmx_vcpu_put,
7777
7778         .update_bp_intercept = update_exception_bitmap,
7779         .get_msr_feature = vmx_get_msr_feature,
7780         .get_msr = vmx_get_msr,
7781         .set_msr = vmx_set_msr,
7782         .get_segment_base = vmx_get_segment_base,
7783         .get_segment = vmx_get_segment,
7784         .set_segment = vmx_set_segment,
7785         .get_cpl = vmx_get_cpl,
7786         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7787         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7788         .decache_cr3 = vmx_decache_cr3,
7789         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7790         .set_cr0 = vmx_set_cr0,
7791         .set_cr3 = vmx_set_cr3,
7792         .set_cr4 = vmx_set_cr4,
7793         .set_efer = vmx_set_efer,
7794         .get_idt = vmx_get_idt,
7795         .set_idt = vmx_set_idt,
7796         .get_gdt = vmx_get_gdt,
7797         .set_gdt = vmx_set_gdt,
7798         .get_dr6 = vmx_get_dr6,
7799         .set_dr6 = vmx_set_dr6,
7800         .set_dr7 = vmx_set_dr7,
7801         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
7802         .cache_reg = vmx_cache_reg,
7803         .get_rflags = vmx_get_rflags,
7804         .set_rflags = vmx_set_rflags,
7805
7806         .tlb_flush = vmx_flush_tlb,
7807         .tlb_flush_gva = vmx_flush_tlb_gva,
7808
7809         .run = vmx_vcpu_run,
7810         .handle_exit = vmx_handle_exit,
7811         .skip_emulated_instruction = skip_emulated_instruction,
7812         .set_interrupt_shadow = vmx_set_interrupt_shadow,
7813         .get_interrupt_shadow = vmx_get_interrupt_shadow,
7814         .patch_hypercall = vmx_patch_hypercall,
7815         .set_irq = vmx_inject_irq,
7816         .set_nmi = vmx_inject_nmi,
7817         .queue_exception = vmx_queue_exception,
7818         .cancel_injection = vmx_cancel_injection,
7819         .interrupt_allowed = vmx_interrupt_allowed,
7820         .nmi_allowed = vmx_nmi_allowed,
7821         .get_nmi_mask = vmx_get_nmi_mask,
7822         .set_nmi_mask = vmx_set_nmi_mask,
7823         .enable_nmi_window = enable_nmi_window,
7824         .enable_irq_window = enable_irq_window,
7825         .update_cr8_intercept = update_cr8_intercept,
7826         .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
7827         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
7828         .get_enable_apicv = vmx_get_enable_apicv,
7829         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
7830         .load_eoi_exitmap = vmx_load_eoi_exitmap,
7831         .apicv_post_state_restore = vmx_apicv_post_state_restore,
7832         .hwapic_irr_update = vmx_hwapic_irr_update,
7833         .hwapic_isr_update = vmx_hwapic_isr_update,
7834         .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
7835         .sync_pir_to_irr = vmx_sync_pir_to_irr,
7836         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
7837         .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt,
7838
7839         .set_tss_addr = vmx_set_tss_addr,
7840         .set_identity_map_addr = vmx_set_identity_map_addr,
7841         .get_tdp_level = get_ept_level,
7842         .get_mt_mask = vmx_get_mt_mask,
7843
7844         .get_exit_info = vmx_get_exit_info,
7845
7846         .get_lpage_level = vmx_get_lpage_level,
7847
7848         .cpuid_update = vmx_cpuid_update,
7849
7850         .rdtscp_supported = vmx_rdtscp_supported,
7851         .invpcid_supported = vmx_invpcid_supported,
7852
7853         .set_supported_cpuid = vmx_set_supported_cpuid,
7854
7855         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7856
7857         .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
7858         .write_l1_tsc_offset = vmx_write_l1_tsc_offset,
7859
7860         .set_tdp_cr3 = vmx_set_cr3,
7861
7862         .check_intercept = vmx_check_intercept,
7863         .handle_exit_irqoff = vmx_handle_exit_irqoff,
7864         .mpx_supported = vmx_mpx_supported,
7865         .xsaves_supported = vmx_xsaves_supported,
7866         .umip_emulated = vmx_umip_emulated,
7867         .pt_supported = vmx_pt_supported,
7868         .pku_supported = vmx_pku_supported,
7869
7870         .request_immediate_exit = vmx_request_immediate_exit,
7871
7872         .sched_in = vmx_sched_in,
7873
7874         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
7875         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
7876         .flush_log_dirty = vmx_flush_log_dirty,
7877         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
7878         .write_log_dirty = vmx_write_pml_buffer,
7879
7880         .pre_block = vmx_pre_block,
7881         .post_block = vmx_post_block,
7882
7883         .pmu_ops = &intel_pmu_ops,
7884
7885         .update_pi_irte = vmx_update_pi_irte,
7886
7887 #ifdef CONFIG_X86_64
7888         .set_hv_timer = vmx_set_hv_timer,
7889         .cancel_hv_timer = vmx_cancel_hv_timer,
7890 #endif
7891
7892         .setup_mce = vmx_setup_mce,
7893
7894         .smi_allowed = vmx_smi_allowed,
7895         .pre_enter_smm = vmx_pre_enter_smm,
7896         .pre_leave_smm = vmx_pre_leave_smm,
7897         .enable_smi_window = enable_smi_window,
7898
7899         .check_nested_events = NULL,
7900         .get_nested_state = NULL,
7901         .set_nested_state = NULL,
7902         .get_vmcs12_pages = NULL,
7903         .nested_enable_evmcs = NULL,
7904         .nested_get_evmcs_version = NULL,
7905         .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault,
7906         .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
7907 };
7908
7909 static void vmx_cleanup_l1d_flush(void)
7910 {
7911         if (vmx_l1d_flush_pages) {
7912                 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
7913                 vmx_l1d_flush_pages = NULL;
7914         }
7915         /* Restore state so sysfs ignores VMX */
7916         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
7917 }
7918
7919 static void vmx_exit(void)
7920 {
7921 #ifdef CONFIG_KEXEC_CORE
7922         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
7923         synchronize_rcu();
7924 #endif
7925
7926         kvm_exit();
7927
7928 #if IS_ENABLED(CONFIG_HYPERV)
7929         if (static_branch_unlikely(&enable_evmcs)) {
7930                 int cpu;
7931                 struct hv_vp_assist_page *vp_ap;
7932                 /*
7933                  * Reset everything to support using non-enlightened VMCS
7934                  * access later (e.g. when we reload the module with
7935                  * enlightened_vmcs=0)
7936                  */
7937                 for_each_online_cpu(cpu) {
7938                         vp_ap = hv_get_vp_assist_page(cpu);
7939
7940                         if (!vp_ap)
7941                                 continue;
7942
7943                         vp_ap->nested_control.features.directhypercall = 0;
7944                         vp_ap->current_nested_vmcs = 0;
7945                         vp_ap->enlighten_vmentry = 0;
7946                 }
7947
7948                 static_branch_disable(&enable_evmcs);
7949         }
7950 #endif
7951         vmx_cleanup_l1d_flush();
7952 }
7953 module_exit(vmx_exit);
7954
7955 static int __init vmx_init(void)
7956 {
7957         int r;
7958
7959 #if IS_ENABLED(CONFIG_HYPERV)
7960         /*
7961          * Enlightened VMCS usage should be recommended and the host needs
7962          * to support eVMCS v1 or above. We can also disable eVMCS support
7963          * with module parameter.
7964          */
7965         if (enlightened_vmcs &&
7966             ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
7967             (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
7968             KVM_EVMCS_VERSION) {
7969                 int cpu;
7970
7971                 /* Check that we have assist pages on all online CPUs */
7972                 for_each_online_cpu(cpu) {
7973                         if (!hv_get_vp_assist_page(cpu)) {
7974                                 enlightened_vmcs = false;
7975                                 break;
7976                         }
7977                 }
7978
7979                 if (enlightened_vmcs) {
7980                         pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
7981                         static_branch_enable(&enable_evmcs);
7982                 }
7983
7984                 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
7985                         vmx_x86_ops.enable_direct_tlbflush
7986                                 = hv_enable_direct_tlbflush;
7987
7988         } else {
7989                 enlightened_vmcs = false;
7990         }
7991 #endif
7992
7993         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7994                      __alignof__(struct vcpu_vmx), THIS_MODULE);
7995         if (r)
7996                 return r;
7997
7998         /*
7999          * Must be called after kvm_init() so enable_ept is properly set
8000          * up. Hand the parameter mitigation value in which was stored in
8001          * the pre module init parser. If no parameter was given, it will
8002          * contain 'auto' which will be turned into the default 'cond'
8003          * mitigation mode.
8004          */
8005         r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
8006         if (r) {
8007                 vmx_exit();
8008                 return r;
8009         }
8010
8011 #ifdef CONFIG_KEXEC_CORE
8012         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8013                            crash_vmclear_local_loaded_vmcss);
8014 #endif
8015         vmx_check_vmcs12_offsets();
8016
8017         return 0;
8018 }
8019 module_init(vmx_init);