1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
8 * Copyright (C) 2006 Qumranet, Inc.
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
16 #include <linux/frame.h>
17 #include <linux/highmem.h>
18 #include <linux/hrtimer.h>
19 #include <linux/kernel.h>
20 #include <linux/kvm_host.h>
21 #include <linux/module.h>
22 #include <linux/moduleparam.h>
23 #include <linux/mod_devicetable.h>
25 #include <linux/sched.h>
26 #include <linux/sched/smt.h>
27 #include <linux/slab.h>
28 #include <linux/tboot.h>
29 #include <linux/trace_events.h>
34 #include <asm/debugreg.h>
36 #include <asm/fpu/internal.h>
38 #include <asm/irq_remapping.h>
39 #include <asm/kexec.h>
40 #include <asm/perf_event.h>
42 #include <asm/mmu_context.h>
43 #include <asm/mshyperv.h>
44 #include <asm/spec-ctrl.h>
45 #include <asm/virtext.h>
48 #include "capabilities.h"
52 #include "kvm_cache_regs.h"
64 MODULE_AUTHOR("Qumranet");
65 MODULE_LICENSE("GPL");
67 static const struct x86_cpu_id vmx_cpu_id[] = {
68 X86_FEATURE_MATCH(X86_FEATURE_VMX),
71 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
73 bool __read_mostly enable_vpid = 1;
74 module_param_named(vpid, enable_vpid, bool, 0444);
76 static bool __read_mostly enable_vnmi = 1;
77 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
79 bool __read_mostly flexpriority_enabled = 1;
80 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
82 bool __read_mostly enable_ept = 1;
83 module_param_named(ept, enable_ept, bool, S_IRUGO);
85 bool __read_mostly enable_unrestricted_guest = 1;
86 module_param_named(unrestricted_guest,
87 enable_unrestricted_guest, bool, S_IRUGO);
89 bool __read_mostly enable_ept_ad_bits = 1;
90 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
92 static bool __read_mostly emulate_invalid_guest_state = true;
93 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
95 static bool __read_mostly fasteoi = 1;
96 module_param(fasteoi, bool, S_IRUGO);
98 static bool __read_mostly enable_apicv = 1;
99 module_param(enable_apicv, bool, S_IRUGO);
102 * If nested=1, nested virtualization is supported, i.e., guests may use
103 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
104 * use VMX instructions.
106 static bool __read_mostly nested = 1;
107 module_param(nested, bool, S_IRUGO);
109 static u64 __read_mostly host_xss;
111 bool __read_mostly enable_pml = 1;
112 module_param_named(pml, enable_pml, bool, S_IRUGO);
114 static bool __read_mostly dump_invalid_vmcs = 0;
115 module_param(dump_invalid_vmcs, bool, 0644);
117 #define MSR_BITMAP_MODE_X2APIC 1
118 #define MSR_BITMAP_MODE_X2APIC_APICV 2
120 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
122 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
123 static int __read_mostly cpu_preemption_timer_multi;
124 static bool __read_mostly enable_preemption_timer = 1;
126 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
129 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
130 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
131 #define KVM_VM_CR0_ALWAYS_ON \
132 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \
133 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
134 #define KVM_CR4_GUEST_OWNED_BITS \
135 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
136 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
138 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
139 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
140 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
142 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
144 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
145 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
146 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
147 RTIT_STATUS_BYTECNT))
149 #define MSR_IA32_RTIT_OUTPUT_BASE_MASK \
150 (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f)
153 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
154 * ple_gap: upper bound on the amount of time between two successive
155 * executions of PAUSE in a loop. Also indicate if ple enabled.
156 * According to test, this time is usually smaller than 128 cycles.
157 * ple_window: upper bound on the amount of time a guest is allowed to execute
158 * in a PAUSE loop. Tests indicate that most spinlocks are held for
159 * less than 2^12 cycles
160 * Time is measured based on a counter that runs at the same rate as the TSC,
161 * refer SDM volume 3b section 21.6.13 & 22.1.3.
163 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
164 module_param(ple_gap, uint, 0444);
166 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
167 module_param(ple_window, uint, 0444);
169 /* Default doubles per-vcpu window every exit. */
170 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
171 module_param(ple_window_grow, uint, 0444);
173 /* Default resets per-vcpu window every exit to ple_window. */
174 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
175 module_param(ple_window_shrink, uint, 0444);
177 /* Default is to compute the maximum so we can never overflow. */
178 static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
179 module_param(ple_window_max, uint, 0444);
181 /* Default is SYSTEM mode, 1 for host-guest mode */
182 int __read_mostly pt_mode = PT_MODE_SYSTEM;
183 module_param(pt_mode, int, S_IRUGO);
185 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
186 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
187 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
189 /* Storage for pre module init parameter parsing */
190 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
192 static const struct {
195 } vmentry_l1d_param[] = {
196 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true},
197 [VMENTER_L1D_FLUSH_NEVER] = {"never", true},
198 [VMENTER_L1D_FLUSH_COND] = {"cond", true},
199 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true},
200 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
201 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
204 #define L1D_CACHE_ORDER 4
205 static void *vmx_l1d_flush_pages;
207 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
212 if (!boot_cpu_has_bug(X86_BUG_L1TF)) {
213 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
218 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
222 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
225 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
226 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
227 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
232 /* If set to auto use the default l1tf mitigation method */
233 if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
234 switch (l1tf_mitigation) {
235 case L1TF_MITIGATION_OFF:
236 l1tf = VMENTER_L1D_FLUSH_NEVER;
238 case L1TF_MITIGATION_FLUSH_NOWARN:
239 case L1TF_MITIGATION_FLUSH:
240 case L1TF_MITIGATION_FLUSH_NOSMT:
241 l1tf = VMENTER_L1D_FLUSH_COND;
243 case L1TF_MITIGATION_FULL:
244 case L1TF_MITIGATION_FULL_FORCE:
245 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
248 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
249 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
252 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
253 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
255 * This allocation for vmx_l1d_flush_pages is not tied to a VM
256 * lifetime and so should not be charged to a memcg.
258 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
261 vmx_l1d_flush_pages = page_address(page);
264 * Initialize each page with a different pattern in
265 * order to protect against KSM in the nested
266 * virtualization case.
268 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
269 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
274 l1tf_vmx_mitigation = l1tf;
276 if (l1tf != VMENTER_L1D_FLUSH_NEVER)
277 static_branch_enable(&vmx_l1d_should_flush);
279 static_branch_disable(&vmx_l1d_should_flush);
281 if (l1tf == VMENTER_L1D_FLUSH_COND)
282 static_branch_enable(&vmx_l1d_flush_cond);
284 static_branch_disable(&vmx_l1d_flush_cond);
288 static int vmentry_l1d_flush_parse(const char *s)
293 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
294 if (vmentry_l1d_param[i].for_parse &&
295 sysfs_streq(s, vmentry_l1d_param[i].option))
302 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
306 l1tf = vmentry_l1d_flush_parse(s);
310 if (!boot_cpu_has(X86_BUG_L1TF))
314 * Has vmx_init() run already? If not then this is the pre init
315 * parameter parsing. In that case just store the value and let
316 * vmx_init() do the proper setup after enable_ept has been
319 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
320 vmentry_l1d_flush_param = l1tf;
324 mutex_lock(&vmx_l1d_flush_mutex);
325 ret = vmx_setup_l1d_flush(l1tf);
326 mutex_unlock(&vmx_l1d_flush_mutex);
330 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
332 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
333 return sprintf(s, "???\n");
335 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
338 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
339 .set = vmentry_l1d_flush_set,
340 .get = vmentry_l1d_flush_get,
342 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
344 static bool guest_state_valid(struct kvm_vcpu *vcpu);
345 static u32 vmx_segment_access_rights(struct kvm_segment *var);
346 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
349 void vmx_vmexit(void);
351 #define vmx_insn_failed(fmt...) \
354 pr_warn_ratelimited(fmt); \
357 asmlinkage void vmread_error(unsigned long field, bool fault)
360 kvm_spurious_fault();
362 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field);
365 noinline void vmwrite_error(unsigned long field, unsigned long value)
367 vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n",
368 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
371 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr)
373 vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr);
376 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr)
378 vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr);
381 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva)
383 vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n",
387 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa)
389 vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n",
393 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
394 DEFINE_PER_CPU(struct vmcs *, current_vmcs);
396 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
397 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
399 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
402 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
403 * can find which vCPU should be waken up.
405 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
406 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
408 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
409 static DEFINE_SPINLOCK(vmx_vpid_lock);
411 struct vmcs_config vmcs_config;
412 struct vmx_capability vmx_capability;
414 #define VMX_SEGMENT_FIELD(seg) \
415 [VCPU_SREG_##seg] = { \
416 .selector = GUEST_##seg##_SELECTOR, \
417 .base = GUEST_##seg##_BASE, \
418 .limit = GUEST_##seg##_LIMIT, \
419 .ar_bytes = GUEST_##seg##_AR_BYTES, \
422 static const struct kvm_vmx_segment_field {
427 } kvm_vmx_segment_fields[] = {
428 VMX_SEGMENT_FIELD(CS),
429 VMX_SEGMENT_FIELD(DS),
430 VMX_SEGMENT_FIELD(ES),
431 VMX_SEGMENT_FIELD(FS),
432 VMX_SEGMENT_FIELD(GS),
433 VMX_SEGMENT_FIELD(SS),
434 VMX_SEGMENT_FIELD(TR),
435 VMX_SEGMENT_FIELD(LDTR),
439 static unsigned long host_idt_base;
442 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
443 * will emulate SYSCALL in legacy mode if the vendor string in guest
444 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
445 * support this emulation, IA32_STAR must always be included in
446 * vmx_msr_index[], even in i386 builds.
448 const u32 vmx_msr_index[] = {
450 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
452 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
455 #if IS_ENABLED(CONFIG_HYPERV)
456 static bool __read_mostly enlightened_vmcs = true;
457 module_param(enlightened_vmcs, bool, 0444);
459 /* check_ept_pointer() should be under protection of ept_pointer_lock. */
460 static void check_ept_pointer_match(struct kvm *kvm)
462 struct kvm_vcpu *vcpu;
463 u64 tmp_eptp = INVALID_PAGE;
466 kvm_for_each_vcpu(i, vcpu, kvm) {
467 if (!VALID_PAGE(tmp_eptp)) {
468 tmp_eptp = to_vmx(vcpu)->ept_pointer;
469 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
470 to_kvm_vmx(kvm)->ept_pointers_match
471 = EPT_POINTERS_MISMATCH;
476 to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
479 static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush,
482 struct kvm_tlb_range *range = data;
484 return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn,
488 static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm,
489 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range)
491 u64 ept_pointer = to_vmx(vcpu)->ept_pointer;
494 * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address
495 * of the base of EPT PML4 table, strip off EPT configuration
499 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK,
500 kvm_fill_hv_flush_list_func, (void *)range);
502 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK);
505 static int hv_remote_flush_tlb_with_range(struct kvm *kvm,
506 struct kvm_tlb_range *range)
508 struct kvm_vcpu *vcpu;
511 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
513 if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
514 check_ept_pointer_match(kvm);
516 if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
517 kvm_for_each_vcpu(i, vcpu, kvm) {
518 /* If ept_pointer is invalid pointer, bypass flush request. */
519 if (VALID_PAGE(to_vmx(vcpu)->ept_pointer))
520 ret |= __hv_remote_flush_tlb_with_range(
524 ret = __hv_remote_flush_tlb_with_range(kvm,
525 kvm_get_vcpu(kvm, 0), range);
528 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
531 static int hv_remote_flush_tlb(struct kvm *kvm)
533 return hv_remote_flush_tlb_with_range(kvm, NULL);
536 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
538 struct hv_enlightened_vmcs *evmcs;
539 struct hv_partition_assist_pg **p_hv_pa_pg =
540 &vcpu->kvm->arch.hyperv.hv_pa_pg;
542 * Synthetic VM-Exit is not enabled in current code and so All
543 * evmcs in singe VM shares same assist page.
546 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL);
551 evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
553 evmcs->partition_assist_page =
555 evmcs->hv_vm_id = (unsigned long)vcpu->kvm;
556 evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
561 #endif /* IS_ENABLED(CONFIG_HYPERV) */
564 * Comment's format: document - errata name - stepping - processor name.
566 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
568 static u32 vmx_preemption_cpu_tfms[] = {
569 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
571 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
572 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
573 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
575 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
577 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
578 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
580 * 320767.pdf - AAP86 - B1 -
581 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
584 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
586 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
588 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
590 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
591 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
592 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
594 /* Xeon E3-1220 V2 */
598 static inline bool cpu_has_broken_vmx_preemption_timer(void)
600 u32 eax = cpuid_eax(0x00000001), i;
602 /* Clear the reserved bits */
603 eax &= ~(0x3U << 14 | 0xfU << 28);
604 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
605 if (eax == vmx_preemption_cpu_tfms[i])
611 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
613 return flexpriority_enabled && lapic_in_kernel(vcpu);
616 static inline bool report_flexpriority(void)
618 return flexpriority_enabled;
621 static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
625 for (i = 0; i < vmx->nmsrs; ++i)
626 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
631 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
635 i = __find_msr_index(vmx, msr);
637 return &vmx->guest_msrs[i];
641 void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
643 vmcs_clear(loaded_vmcs->vmcs);
644 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
645 vmcs_clear(loaded_vmcs->shadow_vmcs);
646 loaded_vmcs->cpu = -1;
647 loaded_vmcs->launched = 0;
650 #ifdef CONFIG_KEXEC_CORE
652 * This bitmap is used to indicate whether the vmclear
653 * operation is enabled on all cpus. All disabled by
656 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
658 static inline void crash_enable_local_vmclear(int cpu)
660 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
663 static inline void crash_disable_local_vmclear(int cpu)
665 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
668 static inline int crash_local_vmclear_enabled(int cpu)
670 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
673 static void crash_vmclear_local_loaded_vmcss(void)
675 int cpu = raw_smp_processor_id();
676 struct loaded_vmcs *v;
678 if (!crash_local_vmclear_enabled(cpu))
681 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
682 loaded_vmcss_on_cpu_link)
686 static inline void crash_enable_local_vmclear(int cpu) { }
687 static inline void crash_disable_local_vmclear(int cpu) { }
688 #endif /* CONFIG_KEXEC_CORE */
690 static void __loaded_vmcs_clear(void *arg)
692 struct loaded_vmcs *loaded_vmcs = arg;
693 int cpu = raw_smp_processor_id();
695 if (loaded_vmcs->cpu != cpu)
696 return; /* vcpu migration can race with cpu offline */
697 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
698 per_cpu(current_vmcs, cpu) = NULL;
699 crash_disable_local_vmclear(cpu);
700 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
703 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
704 * is before setting loaded_vmcs->vcpu to -1 which is done in
705 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
706 * then adds the vmcs into percpu list before it is deleted.
710 loaded_vmcs_init(loaded_vmcs);
711 crash_enable_local_vmclear(cpu);
714 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
716 int cpu = loaded_vmcs->cpu;
719 smp_call_function_single(cpu,
720 __loaded_vmcs_clear, loaded_vmcs, 1);
723 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
727 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
729 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
730 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
731 vmx->segment_cache.bitmask = 0;
733 ret = vmx->segment_cache.bitmask & mask;
734 vmx->segment_cache.bitmask |= mask;
738 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
740 u16 *p = &vmx->segment_cache.seg[seg].selector;
742 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
743 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
747 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
749 ulong *p = &vmx->segment_cache.seg[seg].base;
751 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
752 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
756 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
758 u32 *p = &vmx->segment_cache.seg[seg].limit;
760 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
761 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
765 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
767 u32 *p = &vmx->segment_cache.seg[seg].ar;
769 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
770 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
774 void update_exception_bitmap(struct kvm_vcpu *vcpu)
778 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
779 (1u << DB_VECTOR) | (1u << AC_VECTOR);
781 * Guest access to VMware backdoor ports could legitimately
782 * trigger #GP because of TSS I/O permission bitmap.
783 * We intercept those #GP and allow access to them anyway
786 if (enable_vmware_backdoor)
787 eb |= (1u << GP_VECTOR);
788 if ((vcpu->guest_debug &
789 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
790 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
791 eb |= 1u << BP_VECTOR;
792 if (to_vmx(vcpu)->rmode.vm86_active)
795 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
797 /* When we are running a nested L2 guest and L1 specified for it a
798 * certain exception bitmap, we must trap the same exceptions and pass
799 * them to L1. When running L2, we will only handle the exceptions
800 * specified above if L1 did not want them.
802 if (is_guest_mode(vcpu))
803 eb |= get_vmcs12(vcpu)->exception_bitmap;
805 vmcs_write32(EXCEPTION_BITMAP, eb);
809 * Check if MSR is intercepted for currently loaded MSR bitmap.
811 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
813 unsigned long *msr_bitmap;
814 int f = sizeof(unsigned long);
816 if (!cpu_has_vmx_msr_bitmap())
819 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
822 return !!test_bit(msr, msr_bitmap + 0x800 / f);
823 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
825 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
831 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
832 unsigned long entry, unsigned long exit)
834 vm_entry_controls_clearbit(vmx, entry);
835 vm_exit_controls_clearbit(vmx, exit);
838 static int find_msr(struct vmx_msrs *m, unsigned int msr)
842 for (i = 0; i < m->nr; ++i) {
843 if (m->val[i].index == msr)
849 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
852 struct msr_autoload *m = &vmx->msr_autoload;
856 if (cpu_has_load_ia32_efer()) {
857 clear_atomic_switch_msr_special(vmx,
858 VM_ENTRY_LOAD_IA32_EFER,
859 VM_EXIT_LOAD_IA32_EFER);
863 case MSR_CORE_PERF_GLOBAL_CTRL:
864 if (cpu_has_load_perf_global_ctrl()) {
865 clear_atomic_switch_msr_special(vmx,
866 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
867 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
872 i = find_msr(&m->guest, msr);
876 m->guest.val[i] = m->guest.val[m->guest.nr];
877 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
880 i = find_msr(&m->host, msr);
885 m->host.val[i] = m->host.val[m->host.nr];
886 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
889 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
890 unsigned long entry, unsigned long exit,
891 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
892 u64 guest_val, u64 host_val)
894 vmcs_write64(guest_val_vmcs, guest_val);
895 if (host_val_vmcs != HOST_IA32_EFER)
896 vmcs_write64(host_val_vmcs, host_val);
897 vm_entry_controls_setbit(vmx, entry);
898 vm_exit_controls_setbit(vmx, exit);
901 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
902 u64 guest_val, u64 host_val, bool entry_only)
905 struct msr_autoload *m = &vmx->msr_autoload;
909 if (cpu_has_load_ia32_efer()) {
910 add_atomic_switch_msr_special(vmx,
911 VM_ENTRY_LOAD_IA32_EFER,
912 VM_EXIT_LOAD_IA32_EFER,
915 guest_val, host_val);
919 case MSR_CORE_PERF_GLOBAL_CTRL:
920 if (cpu_has_load_perf_global_ctrl()) {
921 add_atomic_switch_msr_special(vmx,
922 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
923 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
924 GUEST_IA32_PERF_GLOBAL_CTRL,
925 HOST_IA32_PERF_GLOBAL_CTRL,
926 guest_val, host_val);
930 case MSR_IA32_PEBS_ENABLE:
931 /* PEBS needs a quiescent period after being disabled (to write
932 * a record). Disabling PEBS through VMX MSR swapping doesn't
933 * provide that period, so a CPU could write host's record into
936 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
939 i = find_msr(&m->guest, msr);
941 j = find_msr(&m->host, msr);
943 if ((i < 0 && m->guest.nr == NR_AUTOLOAD_MSRS) ||
944 (j < 0 && m->host.nr == NR_AUTOLOAD_MSRS)) {
945 printk_once(KERN_WARNING "Not enough msr switch entries. "
946 "Can't add msr %x\n", msr);
951 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
953 m->guest.val[i].index = msr;
954 m->guest.val[i].value = guest_val;
961 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
963 m->host.val[j].index = msr;
964 m->host.val[j].value = host_val;
967 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
969 u64 guest_efer = vmx->vcpu.arch.efer;
972 /* Shadow paging assumes NX to be available. */
974 guest_efer |= EFER_NX;
977 * LMA and LME handled by hardware; SCE meaningless outside long mode.
979 ignore_bits |= EFER_SCE;
981 ignore_bits |= EFER_LMA | EFER_LME;
982 /* SCE is meaningful only in long mode on Intel */
983 if (guest_efer & EFER_LMA)
984 ignore_bits &= ~(u64)EFER_SCE;
988 * On EPT, we can't emulate NX, so we must switch EFER atomically.
989 * On CPUs that support "load IA32_EFER", always switch EFER
990 * atomically, since it's faster than switching it manually.
992 if (cpu_has_load_ia32_efer() ||
993 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
994 if (!(guest_efer & EFER_LMA))
995 guest_efer &= ~EFER_LME;
996 if (guest_efer != host_efer)
997 add_atomic_switch_msr(vmx, MSR_EFER,
998 guest_efer, host_efer, false);
1000 clear_atomic_switch_msr(vmx, MSR_EFER);
1003 clear_atomic_switch_msr(vmx, MSR_EFER);
1005 guest_efer &= ~ignore_bits;
1006 guest_efer |= host_efer & ignore_bits;
1008 vmx->guest_msrs[efer_offset].data = guest_efer;
1009 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1015 #ifdef CONFIG_X86_32
1017 * On 32-bit kernels, VM exits still load the FS and GS bases from the
1018 * VMCS rather than the segment table. KVM uses this helper to figure
1019 * out the current bases to poke them into the VMCS before entry.
1021 static unsigned long segment_base(u16 selector)
1023 struct desc_struct *table;
1026 if (!(selector & ~SEGMENT_RPL_MASK))
1029 table = get_current_gdt_ro();
1031 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
1032 u16 ldt_selector = kvm_read_ldt();
1034 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
1037 table = (struct desc_struct *)segment_base(ldt_selector);
1039 v = get_desc_base(&table[selector >> 3]);
1044 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
1048 wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1049 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1050 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1051 wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1052 for (i = 0; i < addr_range; i++) {
1053 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1054 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1058 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
1062 rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1063 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1064 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1065 rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1066 for (i = 0; i < addr_range; i++) {
1067 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1068 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1072 static void pt_guest_enter(struct vcpu_vmx *vmx)
1074 if (pt_mode == PT_MODE_SYSTEM)
1078 * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1079 * Save host state before VM entry.
1081 rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1082 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1083 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1084 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1085 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1089 static void pt_guest_exit(struct vcpu_vmx *vmx)
1091 if (pt_mode == PT_MODE_SYSTEM)
1094 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1095 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1096 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1099 /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1100 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1103 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1104 unsigned long fs_base, unsigned long gs_base)
1106 if (unlikely(fs_sel != host->fs_sel)) {
1108 vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1110 vmcs_write16(HOST_FS_SELECTOR, 0);
1111 host->fs_sel = fs_sel;
1113 if (unlikely(gs_sel != host->gs_sel)) {
1115 vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1117 vmcs_write16(HOST_GS_SELECTOR, 0);
1118 host->gs_sel = gs_sel;
1120 if (unlikely(fs_base != host->fs_base)) {
1121 vmcs_writel(HOST_FS_BASE, fs_base);
1122 host->fs_base = fs_base;
1124 if (unlikely(gs_base != host->gs_base)) {
1125 vmcs_writel(HOST_GS_BASE, gs_base);
1126 host->gs_base = gs_base;
1130 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1132 struct vcpu_vmx *vmx = to_vmx(vcpu);
1133 struct vmcs_host_state *host_state;
1134 #ifdef CONFIG_X86_64
1135 int cpu = raw_smp_processor_id();
1137 unsigned long fs_base, gs_base;
1141 vmx->req_immediate_exit = false;
1144 * Note that guest MSRs to be saved/restored can also be changed
1145 * when guest state is loaded. This happens when guest transitions
1146 * to/from long-mode by setting MSR_EFER.LMA.
1148 if (!vmx->guest_msrs_ready) {
1149 vmx->guest_msrs_ready = true;
1150 for (i = 0; i < vmx->save_nmsrs; ++i)
1151 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1152 vmx->guest_msrs[i].data,
1153 vmx->guest_msrs[i].mask);
1156 if (vmx->guest_state_loaded)
1159 host_state = &vmx->loaded_vmcs->host_state;
1162 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1163 * allow segment selectors with cpl > 0 or ti == 1.
1165 host_state->ldt_sel = kvm_read_ldt();
1167 #ifdef CONFIG_X86_64
1168 savesegment(ds, host_state->ds_sel);
1169 savesegment(es, host_state->es_sel);
1171 gs_base = cpu_kernelmode_gs_base(cpu);
1172 if (likely(is_64bit_mm(current->mm))) {
1173 save_fsgs_for_kvm();
1174 fs_sel = current->thread.fsindex;
1175 gs_sel = current->thread.gsindex;
1176 fs_base = current->thread.fsbase;
1177 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
1179 savesegment(fs, fs_sel);
1180 savesegment(gs, gs_sel);
1181 fs_base = read_msr(MSR_FS_BASE);
1182 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
1185 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1187 savesegment(fs, fs_sel);
1188 savesegment(gs, gs_sel);
1189 fs_base = segment_base(fs_sel);
1190 gs_base = segment_base(gs_sel);
1193 vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
1194 vmx->guest_state_loaded = true;
1197 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
1199 struct vmcs_host_state *host_state;
1201 if (!vmx->guest_state_loaded)
1204 host_state = &vmx->loaded_vmcs->host_state;
1206 ++vmx->vcpu.stat.host_state_reload;
1208 #ifdef CONFIG_X86_64
1209 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1211 if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1212 kvm_load_ldt(host_state->ldt_sel);
1213 #ifdef CONFIG_X86_64
1214 load_gs_index(host_state->gs_sel);
1216 loadsegment(gs, host_state->gs_sel);
1219 if (host_state->fs_sel & 7)
1220 loadsegment(fs, host_state->fs_sel);
1221 #ifdef CONFIG_X86_64
1222 if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1223 loadsegment(ds, host_state->ds_sel);
1224 loadsegment(es, host_state->es_sel);
1227 invalidate_tss_limit();
1228 #ifdef CONFIG_X86_64
1229 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1231 load_fixmap_gdt(raw_smp_processor_id());
1232 vmx->guest_state_loaded = false;
1233 vmx->guest_msrs_ready = false;
1236 #ifdef CONFIG_X86_64
1237 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
1240 if (vmx->guest_state_loaded)
1241 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1243 return vmx->msr_guest_kernel_gs_base;
1246 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1249 if (vmx->guest_state_loaded)
1250 wrmsrl(MSR_KERNEL_GS_BASE, data);
1252 vmx->msr_guest_kernel_gs_base = data;
1256 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1258 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1259 struct pi_desc old, new;
1263 * In case of hot-plug or hot-unplug, we may have to undo
1264 * vmx_vcpu_pi_put even if there is no assigned device. And we
1265 * always keep PI.NDST up to date for simplicity: it makes the
1266 * code easier, and CPU migration is not a fast path.
1268 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
1272 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
1273 * PI.NDST: pi_post_block is the one expected to change PID.NDST and the
1274 * wakeup handler expects the vCPU to be on the blocked_vcpu_list that
1275 * matches PI.NDST. Otherwise, a vcpu may not be able to be woken up
1278 if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || vcpu->cpu == cpu) {
1279 pi_clear_sn(pi_desc);
1280 goto after_clear_sn;
1283 /* The full case. */
1285 old.control = new.control = pi_desc->control;
1287 dest = cpu_physical_id(cpu);
1289 if (x2apic_enabled())
1292 new.ndst = (dest << 8) & 0xFF00;
1295 } while (cmpxchg64(&pi_desc->control, old.control,
1296 new.control) != old.control);
1301 * Clear SN before reading the bitmap. The VT-d firmware
1302 * writes the bitmap and reads SN atomically (5.2.3 in the
1303 * spec), so it doesn't really have a memory barrier that
1304 * pairs with this, but we cannot do that and we need one.
1306 smp_mb__after_atomic();
1308 if (!pi_is_pir_empty(pi_desc))
1312 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu)
1314 struct vcpu_vmx *vmx = to_vmx(vcpu);
1315 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
1317 if (!already_loaded) {
1318 loaded_vmcs_clear(vmx->loaded_vmcs);
1319 local_irq_disable();
1320 crash_disable_local_vmclear(cpu);
1323 * Read loaded_vmcs->cpu should be before fetching
1324 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1325 * See the comments in __loaded_vmcs_clear().
1329 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1330 &per_cpu(loaded_vmcss_on_cpu, cpu));
1331 crash_enable_local_vmclear(cpu);
1335 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1336 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1337 vmcs_load(vmx->loaded_vmcs->vmcs);
1338 indirect_branch_prediction_barrier();
1341 if (!already_loaded) {
1342 void *gdt = get_current_gdt_ro();
1343 unsigned long sysenter_esp;
1345 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1348 * Linux uses per-cpu TSS and GDT, so set these when switching
1349 * processors. See 22.2.4.
1351 vmcs_writel(HOST_TR_BASE,
1352 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
1353 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
1356 * VM exits change the host TR limit to 0x67 after a VM
1357 * exit. This is okay, since 0x67 covers everything except
1358 * the IO bitmap and have have code to handle the IO bitmap
1359 * being lost after a VM exit.
1361 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
1363 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1364 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1366 vmx->loaded_vmcs->cpu = cpu;
1369 /* Setup TSC multiplier */
1370 if (kvm_has_tsc_control &&
1371 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
1372 decache_tsc_multiplier(vmx);
1376 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1377 * vcpu mutex is already taken.
1379 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1381 struct vcpu_vmx *vmx = to_vmx(vcpu);
1383 vmx_vcpu_load_vmcs(vcpu, cpu);
1385 vmx_vcpu_pi_load(vcpu, cpu);
1387 vmx->host_pkru = read_pkru();
1388 vmx->host_debugctlmsr = get_debugctlmsr();
1391 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
1393 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1395 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1396 !irq_remapping_cap(IRQ_POSTING_CAP) ||
1397 !kvm_vcpu_apicv_active(vcpu))
1400 /* Set SN when the vCPU is preempted */
1401 if (vcpu->preempted)
1405 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1407 vmx_vcpu_pi_put(vcpu);
1409 vmx_prepare_switch_to_host(to_vmx(vcpu));
1412 static bool emulation_required(struct kvm_vcpu *vcpu)
1414 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
1417 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1419 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1421 unsigned long rflags, save_rflags;
1423 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1424 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1425 rflags = vmcs_readl(GUEST_RFLAGS);
1426 if (to_vmx(vcpu)->rmode.vm86_active) {
1427 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1428 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1429 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1431 to_vmx(vcpu)->rflags = rflags;
1433 return to_vmx(vcpu)->rflags;
1436 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1438 unsigned long old_rflags = vmx_get_rflags(vcpu);
1440 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1441 to_vmx(vcpu)->rflags = rflags;
1442 if (to_vmx(vcpu)->rmode.vm86_active) {
1443 to_vmx(vcpu)->rmode.save_rflags = rflags;
1444 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1446 vmcs_writel(GUEST_RFLAGS, rflags);
1448 if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
1449 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
1452 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1454 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1457 if (interruptibility & GUEST_INTR_STATE_STI)
1458 ret |= KVM_X86_SHADOW_INT_STI;
1459 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1460 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1465 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1467 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1468 u32 interruptibility = interruptibility_old;
1470 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1472 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1473 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1474 else if (mask & KVM_X86_SHADOW_INT_STI)
1475 interruptibility |= GUEST_INTR_STATE_STI;
1477 if ((interruptibility != interruptibility_old))
1478 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1481 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1483 struct vcpu_vmx *vmx = to_vmx(vcpu);
1484 unsigned long value;
1487 * Any MSR write that attempts to change bits marked reserved will
1490 if (data & vmx->pt_desc.ctl_bitmask)
1494 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1495 * result in a #GP unless the same write also clears TraceEn.
1497 if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1498 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1502 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1503 * and FabricEn would cause #GP, if
1504 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1506 if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1507 !(data & RTIT_CTL_FABRIC_EN) &&
1508 !intel_pt_validate_cap(vmx->pt_desc.caps,
1509 PT_CAP_single_range_output))
1513 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1514 * utilize encodings marked reserved will casue a #GP fault.
1516 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1517 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1518 !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1519 RTIT_CTL_MTC_RANGE_OFFSET, &value))
1521 value = intel_pt_validate_cap(vmx->pt_desc.caps,
1522 PT_CAP_cycle_thresholds);
1523 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1524 !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1525 RTIT_CTL_CYC_THRESH_OFFSET, &value))
1527 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1528 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1529 !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1530 RTIT_CTL_PSB_FREQ_OFFSET, &value))
1534 * If ADDRx_CFG is reserved or the encodings is >2 will
1535 * cause a #GP fault.
1537 value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1538 if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
1540 value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1541 if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
1543 value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1544 if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
1546 value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1547 if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
1553 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
1558 * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
1559 * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
1560 * set when EPT misconfig occurs. In practice, real hardware updates
1561 * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
1562 * (namely Hyper-V) don't set it due to it being undefined behavior,
1563 * i.e. we end up advancing IP with some random value.
1565 if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
1566 to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) {
1567 rip = kvm_rip_read(vcpu);
1568 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1569 kvm_rip_write(vcpu, rip);
1571 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
1575 /* skipping an emulated instruction also counts */
1576 vmx_set_interrupt_shadow(vcpu, 0);
1581 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1584 * Ensure that we clear the HLT state in the VMCS. We don't need to
1585 * explicitly skip the instruction because if the HLT state is set,
1586 * then the instruction is already executing and RIP has already been
1589 if (kvm_hlt_in_guest(vcpu->kvm) &&
1590 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1591 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1594 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
1596 struct vcpu_vmx *vmx = to_vmx(vcpu);
1597 unsigned nr = vcpu->arch.exception.nr;
1598 bool has_error_code = vcpu->arch.exception.has_error_code;
1599 u32 error_code = vcpu->arch.exception.error_code;
1600 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1602 kvm_deliver_exception_payload(vcpu);
1604 if (has_error_code) {
1605 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1606 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1609 if (vmx->rmode.vm86_active) {
1611 if (kvm_exception_is_soft(nr))
1612 inc_eip = vcpu->arch.event_exit_inst_len;
1613 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
1617 WARN_ON_ONCE(vmx->emulation_required);
1619 if (kvm_exception_is_soft(nr)) {
1620 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1621 vmx->vcpu.arch.event_exit_inst_len);
1622 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1624 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1626 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1628 vmx_clear_hlt(vcpu);
1631 static bool vmx_rdtscp_supported(void)
1633 return cpu_has_vmx_rdtscp();
1636 static bool vmx_invpcid_supported(void)
1638 return cpu_has_vmx_invpcid();
1642 * Swap MSR entry in host/guest MSR entry array.
1644 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1646 struct shared_msr_entry tmp;
1648 tmp = vmx->guest_msrs[to];
1649 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1650 vmx->guest_msrs[from] = tmp;
1654 * Set up the vmcs to automatically save and restore system
1655 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1656 * mode, as fiddling with msrs is very expensive.
1658 static void setup_msrs(struct vcpu_vmx *vmx)
1660 int save_nmsrs, index;
1663 #ifdef CONFIG_X86_64
1665 * The SYSCALL MSRs are only needed on long mode guests, and only
1666 * when EFER.SCE is set.
1668 if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) {
1669 index = __find_msr_index(vmx, MSR_STAR);
1671 move_msr_up(vmx, index, save_nmsrs++);
1672 index = __find_msr_index(vmx, MSR_LSTAR);
1674 move_msr_up(vmx, index, save_nmsrs++);
1675 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1677 move_msr_up(vmx, index, save_nmsrs++);
1680 index = __find_msr_index(vmx, MSR_EFER);
1681 if (index >= 0 && update_transition_efer(vmx, index))
1682 move_msr_up(vmx, index, save_nmsrs++);
1683 index = __find_msr_index(vmx, MSR_TSC_AUX);
1684 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
1685 move_msr_up(vmx, index, save_nmsrs++);
1687 vmx->save_nmsrs = save_nmsrs;
1688 vmx->guest_msrs_ready = false;
1690 if (cpu_has_vmx_msr_bitmap())
1691 vmx_update_msr_bitmap(&vmx->vcpu);
1694 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1696 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1698 if (is_guest_mode(vcpu) &&
1699 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
1700 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
1702 return vcpu->arch.tsc_offset;
1705 static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1707 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1708 u64 g_tsc_offset = 0;
1711 * We're here if L1 chose not to trap WRMSR to TSC. According
1712 * to the spec, this should set L1's TSC; The offset that L1
1713 * set for L2 remains unchanged, and still needs to be added
1714 * to the newly set TSC to get L2's TSC.
1716 if (is_guest_mode(vcpu) &&
1717 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
1718 g_tsc_offset = vmcs12->tsc_offset;
1720 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1721 vcpu->arch.tsc_offset - g_tsc_offset,
1723 vmcs_write64(TSC_OFFSET, offset + g_tsc_offset);
1724 return offset + g_tsc_offset;
1728 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1729 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1730 * all guests if the "nested" module option is off, and can also be disabled
1731 * for a single guest by disabling its VMX cpuid bit.
1733 bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1735 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
1738 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1741 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
1743 return !(val & ~valid_bits);
1746 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
1748 switch (msr->index) {
1749 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1752 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1761 * Reads an msr value (of 'msr_index') into 'pdata'.
1762 * Returns 0 on success, non-0 otherwise.
1763 * Assumes vcpu_load() was already called.
1765 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1767 struct vcpu_vmx *vmx = to_vmx(vcpu);
1768 struct shared_msr_entry *msr;
1771 switch (msr_info->index) {
1772 #ifdef CONFIG_X86_64
1774 msr_info->data = vmcs_readl(GUEST_FS_BASE);
1777 msr_info->data = vmcs_readl(GUEST_GS_BASE);
1779 case MSR_KERNEL_GS_BASE:
1780 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
1784 return kvm_get_msr_common(vcpu, msr_info);
1785 case MSR_IA32_UMWAIT_CONTROL:
1786 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1789 msr_info->data = vmx->msr_ia32_umwait_control;
1791 case MSR_IA32_SPEC_CTRL:
1792 if (!msr_info->host_initiated &&
1793 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1796 msr_info->data = to_vmx(vcpu)->spec_ctrl;
1798 case MSR_IA32_SYSENTER_CS:
1799 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
1801 case MSR_IA32_SYSENTER_EIP:
1802 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
1804 case MSR_IA32_SYSENTER_ESP:
1805 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
1807 case MSR_IA32_BNDCFGS:
1808 if (!kvm_mpx_supported() ||
1809 (!msr_info->host_initiated &&
1810 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1812 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
1814 case MSR_IA32_MCG_EXT_CTL:
1815 if (!msr_info->host_initiated &&
1816 !(vmx->msr_ia32_feature_control &
1817 FEATURE_CONTROL_LMCE))
1819 msr_info->data = vcpu->arch.mcg_ext_ctl;
1821 case MSR_IA32_FEATURE_CONTROL:
1822 msr_info->data = vmx->msr_ia32_feature_control;
1824 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1825 if (!nested_vmx_allowed(vcpu))
1827 return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1830 if (!vmx_xsaves_supported() ||
1831 (!msr_info->host_initiated &&
1832 !(guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
1833 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))))
1835 msr_info->data = vcpu->arch.ia32_xss;
1837 case MSR_IA32_RTIT_CTL:
1838 if (pt_mode != PT_MODE_HOST_GUEST)
1840 msr_info->data = vmx->pt_desc.guest.ctl;
1842 case MSR_IA32_RTIT_STATUS:
1843 if (pt_mode != PT_MODE_HOST_GUEST)
1845 msr_info->data = vmx->pt_desc.guest.status;
1847 case MSR_IA32_RTIT_CR3_MATCH:
1848 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1849 !intel_pt_validate_cap(vmx->pt_desc.caps,
1850 PT_CAP_cr3_filtering))
1852 msr_info->data = vmx->pt_desc.guest.cr3_match;
1854 case MSR_IA32_RTIT_OUTPUT_BASE:
1855 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1856 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1857 PT_CAP_topa_output) &&
1858 !intel_pt_validate_cap(vmx->pt_desc.caps,
1859 PT_CAP_single_range_output)))
1861 msr_info->data = vmx->pt_desc.guest.output_base;
1863 case MSR_IA32_RTIT_OUTPUT_MASK:
1864 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1865 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1866 PT_CAP_topa_output) &&
1867 !intel_pt_validate_cap(vmx->pt_desc.caps,
1868 PT_CAP_single_range_output)))
1870 msr_info->data = vmx->pt_desc.guest.output_mask;
1872 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1873 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1874 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1875 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
1876 PT_CAP_num_address_ranges)))
1879 msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1881 msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1884 if (!msr_info->host_initiated &&
1885 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
1887 /* Else, falls through */
1889 msr = find_msr_entry(vmx, msr_info->index);
1891 msr_info->data = msr->data;
1894 return kvm_get_msr_common(vcpu, msr_info);
1901 * Writes msr value into into the appropriate "register".
1902 * Returns 0 on success, non-0 otherwise.
1903 * Assumes vcpu_load() was already called.
1905 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1907 struct vcpu_vmx *vmx = to_vmx(vcpu);
1908 struct shared_msr_entry *msr;
1910 u32 msr_index = msr_info->index;
1911 u64 data = msr_info->data;
1914 switch (msr_index) {
1916 ret = kvm_set_msr_common(vcpu, msr_info);
1918 #ifdef CONFIG_X86_64
1920 vmx_segment_cache_clear(vmx);
1921 vmcs_writel(GUEST_FS_BASE, data);
1924 vmx_segment_cache_clear(vmx);
1925 vmcs_writel(GUEST_GS_BASE, data);
1927 case MSR_KERNEL_GS_BASE:
1928 vmx_write_guest_kernel_gs_base(vmx, data);
1931 case MSR_IA32_SYSENTER_CS:
1932 if (is_guest_mode(vcpu))
1933 get_vmcs12(vcpu)->guest_sysenter_cs = data;
1934 vmcs_write32(GUEST_SYSENTER_CS, data);
1936 case MSR_IA32_SYSENTER_EIP:
1937 if (is_guest_mode(vcpu))
1938 get_vmcs12(vcpu)->guest_sysenter_eip = data;
1939 vmcs_writel(GUEST_SYSENTER_EIP, data);
1941 case MSR_IA32_SYSENTER_ESP:
1942 if (is_guest_mode(vcpu))
1943 get_vmcs12(vcpu)->guest_sysenter_esp = data;
1944 vmcs_writel(GUEST_SYSENTER_ESP, data);
1946 case MSR_IA32_DEBUGCTLMSR:
1947 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
1948 VM_EXIT_SAVE_DEBUG_CONTROLS)
1949 get_vmcs12(vcpu)->guest_ia32_debugctl = data;
1951 ret = kvm_set_msr_common(vcpu, msr_info);
1954 case MSR_IA32_BNDCFGS:
1955 if (!kvm_mpx_supported() ||
1956 (!msr_info->host_initiated &&
1957 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1959 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
1960 (data & MSR_IA32_BNDCFGS_RSVD))
1962 vmcs_write64(GUEST_BNDCFGS, data);
1964 case MSR_IA32_UMWAIT_CONTROL:
1965 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1968 /* The reserved bit 1 and non-32 bit [63:32] should be zero */
1969 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
1972 vmx->msr_ia32_umwait_control = data;
1974 case MSR_IA32_SPEC_CTRL:
1975 if (!msr_info->host_initiated &&
1976 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1979 /* The STIBP bit doesn't fault even if it's not advertised */
1980 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
1983 vmx->spec_ctrl = data;
1990 * When it's written (to non-zero) for the first time, pass
1994 * The handling of the MSR bitmap for L2 guests is done in
1995 * nested_vmx_merge_msr_bitmap. We should not touch the
1996 * vmcs02.msr_bitmap here since it gets completely overwritten
1997 * in the merging. We update the vmcs01 here for L1 as well
1998 * since it will end up touching the MSR anyway now.
2000 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
2004 case MSR_IA32_PRED_CMD:
2005 if (!msr_info->host_initiated &&
2006 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2009 if (data & ~PRED_CMD_IBPB)
2015 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2019 * When it's written (to non-zero) for the first time, pass
2023 * The handling of the MSR bitmap for L2 guests is done in
2024 * nested_vmx_merge_msr_bitmap. We should not touch the
2025 * vmcs02.msr_bitmap here since it gets completely overwritten
2028 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
2031 case MSR_IA32_CR_PAT:
2032 if (!kvm_pat_valid(data))
2035 if (is_guest_mode(vcpu) &&
2036 get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
2037 get_vmcs12(vcpu)->guest_ia32_pat = data;
2039 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2040 vmcs_write64(GUEST_IA32_PAT, data);
2041 vcpu->arch.pat = data;
2044 ret = kvm_set_msr_common(vcpu, msr_info);
2046 case MSR_IA32_TSC_ADJUST:
2047 ret = kvm_set_msr_common(vcpu, msr_info);
2049 case MSR_IA32_MCG_EXT_CTL:
2050 if ((!msr_info->host_initiated &&
2051 !(to_vmx(vcpu)->msr_ia32_feature_control &
2052 FEATURE_CONTROL_LMCE)) ||
2053 (data & ~MCG_EXT_CTL_LMCE_EN))
2055 vcpu->arch.mcg_ext_ctl = data;
2057 case MSR_IA32_FEATURE_CONTROL:
2058 if (!vmx_feature_control_msr_valid(vcpu, data) ||
2059 (to_vmx(vcpu)->msr_ia32_feature_control &
2060 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2062 vmx->msr_ia32_feature_control = data;
2063 if (msr_info->host_initiated && data == 0)
2064 vmx_leave_nested(vcpu);
2066 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2067 if (!msr_info->host_initiated)
2068 return 1; /* they are read-only */
2069 if (!nested_vmx_allowed(vcpu))
2071 return vmx_set_vmx_msr(vcpu, msr_index, data);
2073 if (!vmx_xsaves_supported() ||
2074 (!msr_info->host_initiated &&
2075 !(guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
2076 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))))
2079 * The only supported bit as of Skylake is bit 8, but
2080 * it is not supported on KVM.
2084 vcpu->arch.ia32_xss = data;
2085 if (vcpu->arch.ia32_xss != host_xss)
2086 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2087 vcpu->arch.ia32_xss, host_xss, false);
2089 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2091 case MSR_IA32_RTIT_CTL:
2092 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2093 vmx_rtit_ctl_check(vcpu, data) ||
2096 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
2097 vmx->pt_desc.guest.ctl = data;
2098 pt_update_intercept_for_msr(vmx);
2100 case MSR_IA32_RTIT_STATUS:
2101 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2102 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2103 (data & MSR_IA32_RTIT_STATUS_MASK))
2105 vmx->pt_desc.guest.status = data;
2107 case MSR_IA32_RTIT_CR3_MATCH:
2108 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2109 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2110 !intel_pt_validate_cap(vmx->pt_desc.caps,
2111 PT_CAP_cr3_filtering))
2113 vmx->pt_desc.guest.cr3_match = data;
2115 case MSR_IA32_RTIT_OUTPUT_BASE:
2116 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2117 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2118 (!intel_pt_validate_cap(vmx->pt_desc.caps,
2119 PT_CAP_topa_output) &&
2120 !intel_pt_validate_cap(vmx->pt_desc.caps,
2121 PT_CAP_single_range_output)) ||
2122 (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK))
2124 vmx->pt_desc.guest.output_base = data;
2126 case MSR_IA32_RTIT_OUTPUT_MASK:
2127 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2128 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2129 (!intel_pt_validate_cap(vmx->pt_desc.caps,
2130 PT_CAP_topa_output) &&
2131 !intel_pt_validate_cap(vmx->pt_desc.caps,
2132 PT_CAP_single_range_output)))
2134 vmx->pt_desc.guest.output_mask = data;
2136 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2137 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2138 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2139 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2140 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
2141 PT_CAP_num_address_ranges)))
2144 vmx->pt_desc.guest.addr_b[index / 2] = data;
2146 vmx->pt_desc.guest.addr_a[index / 2] = data;
2149 if (!msr_info->host_initiated &&
2150 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
2152 /* Check reserved bit, higher 32 bits should be zero */
2153 if ((data >> 32) != 0)
2155 /* Else, falls through */
2157 msr = find_msr_entry(vmx, msr_index);
2159 u64 old_msr_data = msr->data;
2161 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2163 ret = kvm_set_shared_msr(msr->index, msr->data,
2167 msr->data = old_msr_data;
2171 ret = kvm_set_msr_common(vcpu, msr_info);
2177 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2179 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2182 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2185 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2187 case VCPU_EXREG_PDPTR:
2189 ept_save_pdptrs(vcpu);
2196 static __init int cpu_has_kvm_support(void)
2198 return cpu_has_vmx();
2201 static __init int vmx_disabled_by_bios(void)
2205 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2206 if (msr & FEATURE_CONTROL_LOCKED) {
2207 /* launched w/ TXT and VMX disabled */
2208 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2211 /* launched w/o TXT and VMX only enabled w/ TXT */
2212 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2213 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2214 && !tboot_enabled()) {
2215 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2216 "activate TXT before enabling KVM\n");
2219 /* launched w/o TXT and VMX disabled */
2220 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2221 && !tboot_enabled())
2228 static void kvm_cpu_vmxon(u64 addr)
2230 cr4_set_bits(X86_CR4_VMXE);
2231 intel_pt_handle_vmx(1);
2233 asm volatile ("vmxon %0" : : "m"(addr));
2236 static int hardware_enable(void)
2238 int cpu = raw_smp_processor_id();
2239 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2242 if (cr4_read_shadow() & X86_CR4_VMXE)
2246 * This can happen if we hot-added a CPU but failed to allocate
2247 * VP assist page for it.
2249 if (static_branch_unlikely(&enable_evmcs) &&
2250 !hv_get_vp_assist_page(cpu))
2253 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2254 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
2255 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
2258 * Now we can enable the vmclear operation in kdump
2259 * since the loaded_vmcss_on_cpu list on this cpu
2260 * has been initialized.
2262 * Though the cpu is not in VMX operation now, there
2263 * is no problem to enable the vmclear operation
2264 * for the loaded_vmcss_on_cpu list is empty!
2266 crash_enable_local_vmclear(cpu);
2268 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2270 test_bits = FEATURE_CONTROL_LOCKED;
2271 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2272 if (tboot_enabled())
2273 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2275 if ((old & test_bits) != test_bits) {
2276 /* enable and lock */
2277 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2279 kvm_cpu_vmxon(phys_addr);
2286 static void vmclear_local_loaded_vmcss(void)
2288 int cpu = raw_smp_processor_id();
2289 struct loaded_vmcs *v, *n;
2291 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2292 loaded_vmcss_on_cpu_link)
2293 __loaded_vmcs_clear(v);
2297 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2300 static void kvm_cpu_vmxoff(void)
2302 asm volatile (__ex("vmxoff"));
2304 intel_pt_handle_vmx(0);
2305 cr4_clear_bits(X86_CR4_VMXE);
2308 static void hardware_disable(void)
2310 vmclear_local_loaded_vmcss();
2314 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2315 u32 msr, u32 *result)
2317 u32 vmx_msr_low, vmx_msr_high;
2318 u32 ctl = ctl_min | ctl_opt;
2320 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2322 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2323 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2325 /* Ensure minimum (required) set of control bits are supported. */
2333 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2334 struct vmx_capability *vmx_cap)
2336 u32 vmx_msr_low, vmx_msr_high;
2337 u32 min, opt, min2, opt2;
2338 u32 _pin_based_exec_control = 0;
2339 u32 _cpu_based_exec_control = 0;
2340 u32 _cpu_based_2nd_exec_control = 0;
2341 u32 _vmexit_control = 0;
2342 u32 _vmentry_control = 0;
2344 memset(vmcs_conf, 0, sizeof(*vmcs_conf));
2345 min = CPU_BASED_HLT_EXITING |
2346 #ifdef CONFIG_X86_64
2347 CPU_BASED_CR8_LOAD_EXITING |
2348 CPU_BASED_CR8_STORE_EXITING |
2350 CPU_BASED_CR3_LOAD_EXITING |
2351 CPU_BASED_CR3_STORE_EXITING |
2352 CPU_BASED_UNCOND_IO_EXITING |
2353 CPU_BASED_MOV_DR_EXITING |
2354 CPU_BASED_USE_TSC_OFFSETING |
2355 CPU_BASED_MWAIT_EXITING |
2356 CPU_BASED_MONITOR_EXITING |
2357 CPU_BASED_INVLPG_EXITING |
2358 CPU_BASED_RDPMC_EXITING;
2360 opt = CPU_BASED_TPR_SHADOW |
2361 CPU_BASED_USE_MSR_BITMAPS |
2362 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2363 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2364 &_cpu_based_exec_control) < 0)
2366 #ifdef CONFIG_X86_64
2367 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2368 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2369 ~CPU_BASED_CR8_STORE_EXITING;
2371 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2373 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2374 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2375 SECONDARY_EXEC_WBINVD_EXITING |
2376 SECONDARY_EXEC_ENABLE_VPID |
2377 SECONDARY_EXEC_ENABLE_EPT |
2378 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2379 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2380 SECONDARY_EXEC_DESC |
2381 SECONDARY_EXEC_RDTSCP |
2382 SECONDARY_EXEC_ENABLE_INVPCID |
2383 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2384 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2385 SECONDARY_EXEC_SHADOW_VMCS |
2386 SECONDARY_EXEC_XSAVES |
2387 SECONDARY_EXEC_RDSEED_EXITING |
2388 SECONDARY_EXEC_RDRAND_EXITING |
2389 SECONDARY_EXEC_ENABLE_PML |
2390 SECONDARY_EXEC_TSC_SCALING |
2391 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
2392 SECONDARY_EXEC_PT_USE_GPA |
2393 SECONDARY_EXEC_PT_CONCEAL_VMX |
2394 SECONDARY_EXEC_ENABLE_VMFUNC |
2395 SECONDARY_EXEC_ENCLS_EXITING;
2396 if (adjust_vmx_controls(min2, opt2,
2397 MSR_IA32_VMX_PROCBASED_CTLS2,
2398 &_cpu_based_2nd_exec_control) < 0)
2401 #ifndef CONFIG_X86_64
2402 if (!(_cpu_based_2nd_exec_control &
2403 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2404 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2407 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2408 _cpu_based_2nd_exec_control &= ~(
2409 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2410 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2411 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2413 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
2414 &vmx_cap->ept, &vmx_cap->vpid);
2416 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2417 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2419 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2420 CPU_BASED_CR3_STORE_EXITING |
2421 CPU_BASED_INVLPG_EXITING);
2422 } else if (vmx_cap->ept) {
2424 pr_warn_once("EPT CAP should not exist if not support "
2425 "1-setting enable EPT VM-execution control\n");
2427 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
2430 pr_warn_once("VPID CAP should not exist if not support "
2431 "1-setting enable VPID VM-execution control\n");
2434 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
2435 #ifdef CONFIG_X86_64
2436 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2438 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2439 VM_EXIT_LOAD_IA32_PAT |
2440 VM_EXIT_LOAD_IA32_EFER |
2441 VM_EXIT_CLEAR_BNDCFGS |
2442 VM_EXIT_PT_CONCEAL_PIP |
2443 VM_EXIT_CLEAR_IA32_RTIT_CTL;
2444 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2445 &_vmexit_control) < 0)
2448 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2449 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2450 PIN_BASED_VMX_PREEMPTION_TIMER;
2451 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2452 &_pin_based_exec_control) < 0)
2455 if (cpu_has_broken_vmx_preemption_timer())
2456 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2457 if (!(_cpu_based_2nd_exec_control &
2458 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
2459 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2461 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2462 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2463 VM_ENTRY_LOAD_IA32_PAT |
2464 VM_ENTRY_LOAD_IA32_EFER |
2465 VM_ENTRY_LOAD_BNDCFGS |
2466 VM_ENTRY_PT_CONCEAL_PIP |
2467 VM_ENTRY_LOAD_IA32_RTIT_CTL;
2468 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2469 &_vmentry_control) < 0)
2473 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2474 * can't be used due to an errata where VM Exit may incorrectly clear
2475 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the
2476 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2478 if (boot_cpu_data.x86 == 0x6) {
2479 switch (boot_cpu_data.x86_model) {
2480 case 26: /* AAK155 */
2481 case 30: /* AAP115 */
2482 case 37: /* AAT100 */
2483 case 44: /* BC86,AAY89,BD102 */
2485 _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
2486 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2487 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2488 "does not work properly. Using workaround\n");
2496 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2498 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2499 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2502 #ifdef CONFIG_X86_64
2503 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2504 if (vmx_msr_high & (1u<<16))
2508 /* Require Write-Back (WB) memory type for VMCS accesses. */
2509 if (((vmx_msr_high >> 18) & 15) != 6)
2512 vmcs_conf->size = vmx_msr_high & 0x1fff;
2513 vmcs_conf->order = get_order(vmcs_conf->size);
2514 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
2516 vmcs_conf->revision_id = vmx_msr_low;
2518 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2519 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2520 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2521 vmcs_conf->vmexit_ctrl = _vmexit_control;
2522 vmcs_conf->vmentry_ctrl = _vmentry_control;
2524 if (static_branch_unlikely(&enable_evmcs))
2525 evmcs_sanitize_exec_ctrls(vmcs_conf);
2530 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
2532 int node = cpu_to_node(cpu);
2536 pages = __alloc_pages_node(node, flags, vmcs_config.order);
2539 vmcs = page_address(pages);
2540 memset(vmcs, 0, vmcs_config.size);
2542 /* KVM supports Enlightened VMCS v1 only */
2543 if (static_branch_unlikely(&enable_evmcs))
2544 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2546 vmcs->hdr.revision_id = vmcs_config.revision_id;
2549 vmcs->hdr.shadow_vmcs = 1;
2553 void free_vmcs(struct vmcs *vmcs)
2555 free_pages((unsigned long)vmcs, vmcs_config.order);
2559 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2561 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2563 if (!loaded_vmcs->vmcs)
2565 loaded_vmcs_clear(loaded_vmcs);
2566 free_vmcs(loaded_vmcs->vmcs);
2567 loaded_vmcs->vmcs = NULL;
2568 if (loaded_vmcs->msr_bitmap)
2569 free_page((unsigned long)loaded_vmcs->msr_bitmap);
2570 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
2573 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2575 loaded_vmcs->vmcs = alloc_vmcs(false);
2576 if (!loaded_vmcs->vmcs)
2579 loaded_vmcs->shadow_vmcs = NULL;
2580 loaded_vmcs->hv_timer_soft_disabled = false;
2581 loaded_vmcs_init(loaded_vmcs);
2583 if (cpu_has_vmx_msr_bitmap()) {
2584 loaded_vmcs->msr_bitmap = (unsigned long *)
2585 __get_free_page(GFP_KERNEL_ACCOUNT);
2586 if (!loaded_vmcs->msr_bitmap)
2588 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
2590 if (IS_ENABLED(CONFIG_HYPERV) &&
2591 static_branch_unlikely(&enable_evmcs) &&
2592 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2593 struct hv_enlightened_vmcs *evmcs =
2594 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2596 evmcs->hv_enlightenments_control.msr_bitmap = 1;
2600 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2601 memset(&loaded_vmcs->controls_shadow, 0,
2602 sizeof(struct vmcs_controls_shadow));
2607 free_loaded_vmcs(loaded_vmcs);
2611 static void free_kvm_area(void)
2615 for_each_possible_cpu(cpu) {
2616 free_vmcs(per_cpu(vmxarea, cpu));
2617 per_cpu(vmxarea, cpu) = NULL;
2621 static __init int alloc_kvm_area(void)
2625 for_each_possible_cpu(cpu) {
2628 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
2635 * When eVMCS is enabled, alloc_vmcs_cpu() sets
2636 * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2637 * revision_id reported by MSR_IA32_VMX_BASIC.
2639 * However, even though not explicitly documented by
2640 * TLFS, VMXArea passed as VMXON argument should
2641 * still be marked with revision_id reported by
2644 if (static_branch_unlikely(&enable_evmcs))
2645 vmcs->hdr.revision_id = vmcs_config.revision_id;
2647 per_cpu(vmxarea, cpu) = vmcs;
2652 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2653 struct kvm_segment *save)
2655 if (!emulate_invalid_guest_state) {
2657 * CS and SS RPL should be equal during guest entry according
2658 * to VMX spec, but in reality it is not always so. Since vcpu
2659 * is in the middle of the transition from real mode to
2660 * protected mode it is safe to assume that RPL 0 is a good
2663 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2664 save->selector &= ~SEGMENT_RPL_MASK;
2665 save->dpl = save->selector & SEGMENT_RPL_MASK;
2668 vmx_set_segment(vcpu, save, seg);
2671 static void enter_pmode(struct kvm_vcpu *vcpu)
2673 unsigned long flags;
2674 struct vcpu_vmx *vmx = to_vmx(vcpu);
2677 * Update real mode segment cache. It may be not up-to-date if sement
2678 * register was written while vcpu was in a guest mode.
2680 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2681 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2682 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2683 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2684 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2685 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2687 vmx->rmode.vm86_active = 0;
2689 vmx_segment_cache_clear(vmx);
2691 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2693 flags = vmcs_readl(GUEST_RFLAGS);
2694 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2695 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2696 vmcs_writel(GUEST_RFLAGS, flags);
2698 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2699 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2701 update_exception_bitmap(vcpu);
2703 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2704 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2705 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2706 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2707 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2708 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2711 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2713 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2714 struct kvm_segment var = *save;
2717 if (seg == VCPU_SREG_CS)
2720 if (!emulate_invalid_guest_state) {
2721 var.selector = var.base >> 4;
2722 var.base = var.base & 0xffff0;
2732 if (save->base & 0xf)
2733 printk_once(KERN_WARNING "kvm: segment base is not "
2734 "paragraph aligned when entering "
2735 "protected mode (seg=%d)", seg);
2738 vmcs_write16(sf->selector, var.selector);
2739 vmcs_writel(sf->base, var.base);
2740 vmcs_write32(sf->limit, var.limit);
2741 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2744 static void enter_rmode(struct kvm_vcpu *vcpu)
2746 unsigned long flags;
2747 struct vcpu_vmx *vmx = to_vmx(vcpu);
2748 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
2750 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2751 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2752 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2753 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2754 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2755 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2756 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2758 vmx->rmode.vm86_active = 1;
2761 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2762 * vcpu. Warn the user that an update is overdue.
2764 if (!kvm_vmx->tss_addr)
2765 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2766 "called before entering vcpu\n");
2768 vmx_segment_cache_clear(vmx);
2770 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
2771 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2772 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2774 flags = vmcs_readl(GUEST_RFLAGS);
2775 vmx->rmode.save_rflags = flags;
2777 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2779 vmcs_writel(GUEST_RFLAGS, flags);
2780 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2781 update_exception_bitmap(vcpu);
2783 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2784 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2785 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2786 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2787 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2788 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2790 kvm_mmu_reset_context(vcpu);
2793 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2795 struct vcpu_vmx *vmx = to_vmx(vcpu);
2796 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2801 vcpu->arch.efer = efer;
2802 if (efer & EFER_LMA) {
2803 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2806 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2808 msr->data = efer & ~EFER_LME;
2813 #ifdef CONFIG_X86_64
2815 static void enter_lmode(struct kvm_vcpu *vcpu)
2819 vmx_segment_cache_clear(to_vmx(vcpu));
2821 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2822 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
2823 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2825 vmcs_write32(GUEST_TR_AR_BYTES,
2826 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2827 | VMX_AR_TYPE_BUSY_64_TSS);
2829 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2832 static void exit_lmode(struct kvm_vcpu *vcpu)
2834 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2835 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2840 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2842 int vpid = to_vmx(vcpu)->vpid;
2844 if (!vpid_sync_vcpu_addr(vpid, addr))
2845 vpid_sync_context(vpid);
2848 * If VPIDs are not supported or enabled, then the above is a no-op.
2849 * But we don't really need a TLB flush in that case anyway, because
2850 * each VM entry/exit includes an implicit flush when VPID is 0.
2854 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2856 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2858 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2859 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2862 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2864 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
2865 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2866 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2869 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2871 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2873 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2874 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2877 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2879 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2881 if (!test_bit(VCPU_EXREG_PDPTR,
2882 (unsigned long *)&vcpu->arch.regs_dirty))
2885 if (is_pae_paging(vcpu)) {
2886 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2887 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2888 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2889 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
2893 void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2895 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2897 if (is_pae_paging(vcpu)) {
2898 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2899 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2900 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2901 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2904 __set_bit(VCPU_EXREG_PDPTR,
2905 (unsigned long *)&vcpu->arch.regs_avail);
2906 __set_bit(VCPU_EXREG_PDPTR,
2907 (unsigned long *)&vcpu->arch.regs_dirty);
2910 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2912 struct kvm_vcpu *vcpu)
2914 struct vcpu_vmx *vmx = to_vmx(vcpu);
2916 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2917 vmx_decache_cr3(vcpu);
2918 if (!(cr0 & X86_CR0_PG)) {
2919 /* From paging/starting to nonpaging */
2920 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2921 CPU_BASED_CR3_STORE_EXITING);
2922 vcpu->arch.cr0 = cr0;
2923 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2924 } else if (!is_paging(vcpu)) {
2925 /* From nonpaging to paging */
2926 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2927 CPU_BASED_CR3_STORE_EXITING);
2928 vcpu->arch.cr0 = cr0;
2929 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2932 if (!(cr0 & X86_CR0_WP))
2933 *hw_cr0 &= ~X86_CR0_WP;
2936 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2938 struct vcpu_vmx *vmx = to_vmx(vcpu);
2939 unsigned long hw_cr0;
2941 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
2942 if (enable_unrestricted_guest)
2943 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2945 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
2947 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2950 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2954 #ifdef CONFIG_X86_64
2955 if (vcpu->arch.efer & EFER_LME) {
2956 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2958 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2963 if (enable_ept && !enable_unrestricted_guest)
2964 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2966 vmcs_writel(CR0_READ_SHADOW, cr0);
2967 vmcs_writel(GUEST_CR0, hw_cr0);
2968 vcpu->arch.cr0 = cr0;
2970 /* depends on vcpu->arch.cr0 to be set to a new value */
2971 vmx->emulation_required = emulation_required(vcpu);
2974 static int get_ept_level(struct kvm_vcpu *vcpu)
2976 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
2981 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
2983 u64 eptp = VMX_EPTP_MT_WB;
2985 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
2987 if (enable_ept_ad_bits &&
2988 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
2989 eptp |= VMX_EPTP_AD_ENABLE_BIT;
2990 eptp |= (root_hpa & PAGE_MASK);
2995 void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2997 struct kvm *kvm = vcpu->kvm;
2998 bool update_guest_cr3 = true;
2999 unsigned long guest_cr3;
3004 eptp = construct_eptp(vcpu, cr3);
3005 vmcs_write64(EPT_POINTER, eptp);
3007 if (kvm_x86_ops->tlb_remote_flush) {
3008 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3009 to_vmx(vcpu)->ept_pointer = eptp;
3010 to_kvm_vmx(kvm)->ept_pointers_match
3011 = EPT_POINTERS_CHECK;
3012 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3015 /* Loading vmcs02.GUEST_CR3 is handled by nested VM-Enter. */
3016 if (is_guest_mode(vcpu))
3017 update_guest_cr3 = false;
3018 else if (enable_unrestricted_guest || is_paging(vcpu))
3019 guest_cr3 = kvm_read_cr3(vcpu);
3021 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
3022 ept_load_pdptrs(vcpu);
3025 if (update_guest_cr3)
3026 vmcs_writel(GUEST_CR3, guest_cr3);
3029 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3031 struct vcpu_vmx *vmx = to_vmx(vcpu);
3033 * Pass through host's Machine Check Enable value to hw_cr4, which
3034 * is in force while we are in guest mode. Do not let guests control
3035 * this bit, even if host CR4.MCE == 0.
3037 unsigned long hw_cr4;
3039 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
3040 if (enable_unrestricted_guest)
3041 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
3042 else if (vmx->rmode.vm86_active)
3043 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
3045 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
3047 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
3048 if (cr4 & X86_CR4_UMIP) {
3049 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
3050 hw_cr4 &= ~X86_CR4_UMIP;
3051 } else if (!is_guest_mode(vcpu) ||
3052 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
3053 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
3057 if (cr4 & X86_CR4_VMXE) {
3059 * To use VMXON (and later other VMX instructions), a guest
3060 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3061 * So basically the check on whether to allow nested VMX
3062 * is here. We operate under the default treatment of SMM,
3063 * so VMX cannot be enabled under SMM.
3065 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
3069 if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
3072 vcpu->arch.cr4 = cr4;
3074 if (!enable_unrestricted_guest) {
3076 if (!is_paging(vcpu)) {
3077 hw_cr4 &= ~X86_CR4_PAE;
3078 hw_cr4 |= X86_CR4_PSE;
3079 } else if (!(cr4 & X86_CR4_PAE)) {
3080 hw_cr4 &= ~X86_CR4_PAE;
3085 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3086 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
3087 * to be manually disabled when guest switches to non-paging
3090 * If !enable_unrestricted_guest, the CPU is always running
3091 * with CR0.PG=1 and CR4 needs to be modified.
3092 * If enable_unrestricted_guest, the CPU automatically
3093 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3095 if (!is_paging(vcpu))
3096 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3099 vmcs_writel(CR4_READ_SHADOW, cr4);
3100 vmcs_writel(GUEST_CR4, hw_cr4);
3104 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3106 struct vcpu_vmx *vmx = to_vmx(vcpu);
3109 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3110 *var = vmx->rmode.segs[seg];
3111 if (seg == VCPU_SREG_TR
3112 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3114 var->base = vmx_read_guest_seg_base(vmx, seg);
3115 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3118 var->base = vmx_read_guest_seg_base(vmx, seg);
3119 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3120 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3121 ar = vmx_read_guest_seg_ar(vmx, seg);
3122 var->unusable = (ar >> 16) & 1;
3123 var->type = ar & 15;
3124 var->s = (ar >> 4) & 1;
3125 var->dpl = (ar >> 5) & 3;
3127 * Some userspaces do not preserve unusable property. Since usable
3128 * segment has to be present according to VMX spec we can use present
3129 * property to amend userspace bug by making unusable segment always
3130 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3131 * segment as unusable.
3133 var->present = !var->unusable;
3134 var->avl = (ar >> 12) & 1;
3135 var->l = (ar >> 13) & 1;
3136 var->db = (ar >> 14) & 1;
3137 var->g = (ar >> 15) & 1;
3140 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3142 struct kvm_segment s;
3144 if (to_vmx(vcpu)->rmode.vm86_active) {
3145 vmx_get_segment(vcpu, &s, seg);
3148 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3151 int vmx_get_cpl(struct kvm_vcpu *vcpu)
3153 struct vcpu_vmx *vmx = to_vmx(vcpu);
3155 if (unlikely(vmx->rmode.vm86_active))
3158 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3159 return VMX_AR_DPL(ar);
3163 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3167 if (var->unusable || !var->present)
3170 ar = var->type & 15;
3171 ar |= (var->s & 1) << 4;
3172 ar |= (var->dpl & 3) << 5;
3173 ar |= (var->present & 1) << 7;
3174 ar |= (var->avl & 1) << 12;
3175 ar |= (var->l & 1) << 13;
3176 ar |= (var->db & 1) << 14;
3177 ar |= (var->g & 1) << 15;
3183 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3185 struct vcpu_vmx *vmx = to_vmx(vcpu);
3186 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3188 vmx_segment_cache_clear(vmx);
3190 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3191 vmx->rmode.segs[seg] = *var;
3192 if (seg == VCPU_SREG_TR)
3193 vmcs_write16(sf->selector, var->selector);
3195 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3199 vmcs_writel(sf->base, var->base);
3200 vmcs_write32(sf->limit, var->limit);
3201 vmcs_write16(sf->selector, var->selector);
3204 * Fix the "Accessed" bit in AR field of segment registers for older
3206 * IA32 arch specifies that at the time of processor reset the
3207 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3208 * is setting it to 0 in the userland code. This causes invalid guest
3209 * state vmexit when "unrestricted guest" mode is turned on.
3210 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3211 * tree. Newer qemu binaries with that qemu fix would not need this
3214 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3215 var->type |= 0x1; /* Accessed */
3217 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3220 vmx->emulation_required = emulation_required(vcpu);
3223 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3225 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3227 *db = (ar >> 14) & 1;
3228 *l = (ar >> 13) & 1;
3231 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3233 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3234 dt->address = vmcs_readl(GUEST_IDTR_BASE);
3237 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3239 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3240 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3243 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3245 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3246 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3249 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3251 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3252 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3255 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3257 struct kvm_segment var;
3260 vmx_get_segment(vcpu, &var, seg);
3262 if (seg == VCPU_SREG_CS)
3264 ar = vmx_segment_access_rights(&var);
3266 if (var.base != (var.selector << 4))
3268 if (var.limit != 0xffff)
3276 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3278 struct kvm_segment cs;
3279 unsigned int cs_rpl;
3281 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3282 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3286 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3290 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3291 if (cs.dpl > cs_rpl)
3294 if (cs.dpl != cs_rpl)
3300 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3304 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3306 struct kvm_segment ss;
3307 unsigned int ss_rpl;
3309 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3310 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3314 if (ss.type != 3 && ss.type != 7)
3318 if (ss.dpl != ss_rpl) /* DPL != RPL */
3326 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3328 struct kvm_segment var;
3331 vmx_get_segment(vcpu, &var, seg);
3332 rpl = var.selector & SEGMENT_RPL_MASK;
3340 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
3341 if (var.dpl < rpl) /* DPL < RPL */
3345 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3351 static bool tr_valid(struct kvm_vcpu *vcpu)
3353 struct kvm_segment tr;
3355 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3359 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
3361 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3369 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3371 struct kvm_segment ldtr;
3373 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3377 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
3387 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3389 struct kvm_segment cs, ss;
3391 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3392 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3394 return ((cs.selector & SEGMENT_RPL_MASK) ==
3395 (ss.selector & SEGMENT_RPL_MASK));
3399 * Check if guest state is valid. Returns true if valid, false if
3401 * We assume that registers are always usable
3403 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3405 if (enable_unrestricted_guest)
3408 /* real mode guest state checks */
3409 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3410 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3412 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3414 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3416 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3418 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3420 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3423 /* protected mode guest state checks */
3424 if (!cs_ss_rpl_check(vcpu))
3426 if (!code_segment_valid(vcpu))
3428 if (!stack_segment_valid(vcpu))
3430 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3432 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3434 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3436 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3438 if (!tr_valid(vcpu))
3440 if (!ldtr_valid(vcpu))
3444 * - Add checks on RIP
3445 * - Add checks on RFLAGS
3451 static int init_rmode_tss(struct kvm *kvm)
3457 idx = srcu_read_lock(&kvm->srcu);
3458 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
3459 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3462 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3463 r = kvm_write_guest_page(kvm, fn++, &data,
3464 TSS_IOPB_BASE_OFFSET, sizeof(u16));
3467 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3470 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3474 r = kvm_write_guest_page(kvm, fn, &data,
3475 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3478 srcu_read_unlock(&kvm->srcu, idx);
3482 static int init_rmode_identity_map(struct kvm *kvm)
3484 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
3486 kvm_pfn_t identity_map_pfn;
3489 /* Protect kvm_vmx->ept_identity_pagetable_done. */
3490 mutex_lock(&kvm->slots_lock);
3492 if (likely(kvm_vmx->ept_identity_pagetable_done))
3495 if (!kvm_vmx->ept_identity_map_addr)
3496 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3497 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
3499 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
3500 kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
3504 idx = srcu_read_lock(&kvm->srcu);
3505 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3508 /* Set up identity-mapping pagetable for EPT in real mode */
3509 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3510 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3511 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3512 r = kvm_write_guest_page(kvm, identity_map_pfn,
3513 &tmp, i * sizeof(tmp), sizeof(tmp));
3517 kvm_vmx->ept_identity_pagetable_done = true;
3520 srcu_read_unlock(&kvm->srcu, idx);
3523 mutex_unlock(&kvm->slots_lock);
3527 static void seg_setup(int seg)
3529 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3532 vmcs_write16(sf->selector, 0);
3533 vmcs_writel(sf->base, 0);
3534 vmcs_write32(sf->limit, 0xffff);
3536 if (seg == VCPU_SREG_CS)
3537 ar |= 0x08; /* code segment */
3539 vmcs_write32(sf->ar_bytes, ar);
3542 static int alloc_apic_access_page(struct kvm *kvm)
3547 mutex_lock(&kvm->slots_lock);
3548 if (kvm->arch.apic_access_page_done)
3550 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3551 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
3555 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
3556 if (is_error_page(page)) {
3562 * Do not pin the page in memory, so that memory hot-unplug
3563 * is able to migrate it.
3566 kvm->arch.apic_access_page_done = true;
3568 mutex_unlock(&kvm->slots_lock);
3572 int allocate_vpid(void)
3578 spin_lock(&vmx_vpid_lock);
3579 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3580 if (vpid < VMX_NR_VPIDS)
3581 __set_bit(vpid, vmx_vpid_bitmap);
3584 spin_unlock(&vmx_vpid_lock);
3588 void free_vpid(int vpid)
3590 if (!enable_vpid || vpid == 0)
3592 spin_lock(&vmx_vpid_lock);
3593 __clear_bit(vpid, vmx_vpid_bitmap);
3594 spin_unlock(&vmx_vpid_lock);
3597 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3600 int f = sizeof(unsigned long);
3602 if (!cpu_has_vmx_msr_bitmap())
3605 if (static_branch_unlikely(&enable_evmcs))
3606 evmcs_touch_msr_bitmap();
3609 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3610 * have the write-low and read-high bitmap offsets the wrong way round.
3611 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3613 if (msr <= 0x1fff) {
3614 if (type & MSR_TYPE_R)
3616 __clear_bit(msr, msr_bitmap + 0x000 / f);
3618 if (type & MSR_TYPE_W)
3620 __clear_bit(msr, msr_bitmap + 0x800 / f);
3622 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3624 if (type & MSR_TYPE_R)
3626 __clear_bit(msr, msr_bitmap + 0x400 / f);
3628 if (type & MSR_TYPE_W)
3630 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3635 static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3638 int f = sizeof(unsigned long);
3640 if (!cpu_has_vmx_msr_bitmap())
3643 if (static_branch_unlikely(&enable_evmcs))
3644 evmcs_touch_msr_bitmap();
3647 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3648 * have the write-low and read-high bitmap offsets the wrong way round.
3649 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3651 if (msr <= 0x1fff) {
3652 if (type & MSR_TYPE_R)
3654 __set_bit(msr, msr_bitmap + 0x000 / f);
3656 if (type & MSR_TYPE_W)
3658 __set_bit(msr, msr_bitmap + 0x800 / f);
3660 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3662 if (type & MSR_TYPE_R)
3664 __set_bit(msr, msr_bitmap + 0x400 / f);
3666 if (type & MSR_TYPE_W)
3668 __set_bit(msr, msr_bitmap + 0xc00 / f);
3673 static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
3674 u32 msr, int type, bool value)
3677 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
3679 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
3682 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
3686 if (cpu_has_secondary_exec_ctrls() &&
3687 (secondary_exec_controls_get(to_vmx(vcpu)) &
3688 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3689 mode |= MSR_BITMAP_MODE_X2APIC;
3690 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3691 mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3697 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
3702 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3703 unsigned word = msr / BITS_PER_LONG;
3704 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3705 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
3708 if (mode & MSR_BITMAP_MODE_X2APIC) {
3710 * TPR reads and writes can be virtualized even if virtual interrupt
3711 * delivery is not in use.
3713 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
3714 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3715 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
3716 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3717 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3722 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
3724 struct vcpu_vmx *vmx = to_vmx(vcpu);
3725 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3726 u8 mode = vmx_msr_bitmap_mode(vcpu);
3727 u8 changed = mode ^ vmx->msr_bitmap_mode;
3732 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
3733 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
3735 vmx->msr_bitmap_mode = mode;
3738 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx)
3740 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3741 bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3744 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS,
3746 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE,
3748 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK,
3750 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH,
3752 for (i = 0; i < vmx->pt_desc.addr_range; i++) {
3753 vmx_set_intercept_for_msr(msr_bitmap,
3754 MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3755 vmx_set_intercept_for_msr(msr_bitmap,
3756 MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3760 static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu)
3762 return enable_apicv;
3765 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3767 struct vcpu_vmx *vmx = to_vmx(vcpu);
3772 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3773 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
3774 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
3777 rvi = vmx_get_rvi();
3779 vapic_page = vmx->nested.virtual_apic_map.hva;
3780 vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
3782 return ((rvi & 0xf0) > (vppr & 0xf0));
3785 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3789 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3791 if (vcpu->mode == IN_GUEST_MODE) {
3793 * The vector of interrupt to be delivered to vcpu had
3794 * been set in PIR before this function.
3796 * Following cases will be reached in this block, and
3797 * we always send a notification event in all cases as
3800 * Case 1: vcpu keeps in non-root mode. Sending a
3801 * notification event posts the interrupt to vcpu.
3803 * Case 2: vcpu exits to root mode and is still
3804 * runnable. PIR will be synced to vIRR before the
3805 * next vcpu entry. Sending a notification event in
3806 * this case has no effect, as vcpu is not in root
3809 * Case 3: vcpu exits to root mode and is blocked.
3810 * vcpu_block() has already synced PIR to vIRR and
3811 * never blocks vcpu if vIRR is not cleared. Therefore,
3812 * a blocked vcpu here does not wait for any requested
3813 * interrupts in PIR, and sending a notification event
3814 * which has no effect is safe here.
3817 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
3824 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3827 struct vcpu_vmx *vmx = to_vmx(vcpu);
3829 if (is_guest_mode(vcpu) &&
3830 vector == vmx->nested.posted_intr_nv) {
3832 * If a posted intr is not recognized by hardware,
3833 * we will accomplish it in the next vmentry.
3835 vmx->nested.pi_pending = true;
3836 kvm_make_request(KVM_REQ_EVENT, vcpu);
3837 /* the PIR and ON have been set by L1. */
3838 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3839 kvm_vcpu_kick(vcpu);
3845 * Send interrupt to vcpu via posted interrupt way.
3846 * 1. If target vcpu is running(non-root mode), send posted interrupt
3847 * notification to vcpu and hardware will sync PIR to vIRR atomically.
3848 * 2. If target vcpu isn't running(root mode), kick it to pick up the
3849 * interrupt from PIR in next vmentry.
3851 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3853 struct vcpu_vmx *vmx = to_vmx(vcpu);
3856 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3860 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
3863 /* If a previous notification has sent the IPI, nothing to do. */
3864 if (pi_test_and_set_on(&vmx->pi_desc))
3867 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
3868 kvm_vcpu_kick(vcpu);
3872 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3873 * will not change in the lifetime of the guest.
3874 * Note that host-state that does change is set elsewhere. E.g., host-state
3875 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3877 void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
3881 unsigned long cr0, cr3, cr4;
3884 WARN_ON(cr0 & X86_CR0_TS);
3885 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
3888 * Save the most likely value for this task's CR3 in the VMCS.
3889 * We can't use __get_current_cr3_fast() because we're not atomic.
3892 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
3893 vmx->loaded_vmcs->host_state.cr3 = cr3;
3895 /* Save the most likely value for this task's CR4 in the VMCS. */
3896 cr4 = cr4_read_shadow();
3897 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
3898 vmx->loaded_vmcs->host_state.cr4 = cr4;
3900 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
3901 #ifdef CONFIG_X86_64
3903 * Load null selectors, so we can avoid reloading them in
3904 * vmx_prepare_switch_to_host(), in case userspace uses
3905 * the null selectors too (the expected case).
3907 vmcs_write16(HOST_DS_SELECTOR, 0);
3908 vmcs_write16(HOST_ES_SELECTOR, 0);
3910 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3911 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3913 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3914 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3916 vmcs_writel(HOST_IDTR_BASE, host_idt_base); /* 22.2.4 */
3918 vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
3920 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3921 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3922 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3923 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3925 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3926 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3927 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3930 if (cpu_has_load_ia32_efer())
3931 vmcs_write64(HOST_IA32_EFER, host_efer);
3934 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3936 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3938 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3939 if (is_guest_mode(&vmx->vcpu))
3940 vmx->vcpu.arch.cr4_guest_owned_bits &=
3941 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3942 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3945 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
3947 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
3949 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
3950 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
3953 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
3955 if (!enable_preemption_timer)
3956 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3958 return pin_based_exec_ctrl;
3961 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
3963 struct vcpu_vmx *vmx = to_vmx(vcpu);
3965 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
3966 if (cpu_has_secondary_exec_ctrls()) {
3967 if (kvm_vcpu_apicv_active(vcpu))
3968 secondary_exec_controls_setbit(vmx,
3969 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3970 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3972 secondary_exec_controls_clearbit(vmx,
3973 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3974 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3977 if (cpu_has_vmx_msr_bitmap())
3978 vmx_update_msr_bitmap(vcpu);
3981 u32 vmx_exec_control(struct vcpu_vmx *vmx)
3983 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3985 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
3986 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
3988 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
3989 exec_control &= ~CPU_BASED_TPR_SHADOW;
3990 #ifdef CONFIG_X86_64
3991 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3992 CPU_BASED_CR8_LOAD_EXITING;
3996 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3997 CPU_BASED_CR3_LOAD_EXITING |
3998 CPU_BASED_INVLPG_EXITING;
3999 if (kvm_mwait_in_guest(vmx->vcpu.kvm))
4000 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
4001 CPU_BASED_MONITOR_EXITING);
4002 if (kvm_hlt_in_guest(vmx->vcpu.kvm))
4003 exec_control &= ~CPU_BASED_HLT_EXITING;
4004 return exec_control;
4008 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
4010 struct kvm_vcpu *vcpu = &vmx->vcpu;
4012 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4014 if (pt_mode == PT_MODE_SYSTEM)
4015 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
4016 if (!cpu_need_virtualize_apic_accesses(vcpu))
4017 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4019 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4021 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4022 enable_unrestricted_guest = 0;
4024 if (!enable_unrestricted_guest)
4025 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4026 if (kvm_pause_in_guest(vmx->vcpu.kvm))
4027 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4028 if (!kvm_vcpu_apicv_active(vcpu))
4029 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4030 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4031 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4033 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
4034 * in vmx_set_cr4. */
4035 exec_control &= ~SECONDARY_EXEC_DESC;
4037 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4039 We can NOT enable shadow_vmcs here because we don't have yet
4042 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4045 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4047 if (vmx_xsaves_supported()) {
4048 /* Exposing XSAVES only when XSAVE is exposed */
4049 bool xsaves_enabled =
4050 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4051 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
4053 if (!xsaves_enabled)
4054 exec_control &= ~SECONDARY_EXEC_XSAVES;
4058 vmx->nested.msrs.secondary_ctls_high |=
4059 SECONDARY_EXEC_XSAVES;
4061 vmx->nested.msrs.secondary_ctls_high &=
4062 ~SECONDARY_EXEC_XSAVES;
4066 if (vmx_rdtscp_supported()) {
4067 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
4068 if (!rdtscp_enabled)
4069 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4073 vmx->nested.msrs.secondary_ctls_high |=
4074 SECONDARY_EXEC_RDTSCP;
4076 vmx->nested.msrs.secondary_ctls_high &=
4077 ~SECONDARY_EXEC_RDTSCP;
4081 if (vmx_invpcid_supported()) {
4082 /* Exposing INVPCID only when PCID is exposed */
4083 bool invpcid_enabled =
4084 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
4085 guest_cpuid_has(vcpu, X86_FEATURE_PCID);
4087 if (!invpcid_enabled) {
4088 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4089 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
4093 if (invpcid_enabled)
4094 vmx->nested.msrs.secondary_ctls_high |=
4095 SECONDARY_EXEC_ENABLE_INVPCID;
4097 vmx->nested.msrs.secondary_ctls_high &=
4098 ~SECONDARY_EXEC_ENABLE_INVPCID;
4102 if (vmx_rdrand_supported()) {
4103 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
4105 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
4109 vmx->nested.msrs.secondary_ctls_high |=
4110 SECONDARY_EXEC_RDRAND_EXITING;
4112 vmx->nested.msrs.secondary_ctls_high &=
4113 ~SECONDARY_EXEC_RDRAND_EXITING;
4117 if (vmx_rdseed_supported()) {
4118 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
4120 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
4124 vmx->nested.msrs.secondary_ctls_high |=
4125 SECONDARY_EXEC_RDSEED_EXITING;
4127 vmx->nested.msrs.secondary_ctls_high &=
4128 ~SECONDARY_EXEC_RDSEED_EXITING;
4132 if (vmx_waitpkg_supported()) {
4133 bool waitpkg_enabled =
4134 guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG);
4136 if (!waitpkg_enabled)
4137 exec_control &= ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4140 if (waitpkg_enabled)
4141 vmx->nested.msrs.secondary_ctls_high |=
4142 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4144 vmx->nested.msrs.secondary_ctls_high &=
4145 ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4149 vmx->secondary_exec_control = exec_control;
4152 static void ept_set_mmio_spte_mask(void)
4155 * EPT Misconfigurations can be generated if the value of bits 2:0
4156 * of an EPT paging-structure entry is 110b (write/execute).
4158 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
4159 VMX_EPT_MISCONFIG_WX_VALUE, 0);
4162 #define VMX_XSS_EXIT_BITMAP 0
4165 * Sets up the vmcs for emulated real mode.
4167 static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
4172 nested_vmx_vcpu_setup();
4174 if (cpu_has_vmx_msr_bitmap())
4175 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
4177 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4180 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4181 vmx->hv_deadline_tsc = -1;
4183 exec_controls_set(vmx, vmx_exec_control(vmx));
4185 if (cpu_has_secondary_exec_ctrls()) {
4186 vmx_compute_secondary_exec_control(vmx);
4187 secondary_exec_controls_set(vmx, vmx->secondary_exec_control);
4190 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4191 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4192 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4193 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4194 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4196 vmcs_write16(GUEST_INTR_STATUS, 0);
4198 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4199 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4202 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4203 vmcs_write32(PLE_GAP, ple_gap);
4204 vmx->ple_window = ple_window;
4205 vmx->ple_window_dirty = true;
4208 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4209 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4210 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4212 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4213 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
4214 vmx_set_constant_host_state(vmx);
4215 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4216 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4218 if (cpu_has_vmx_vmfunc())
4219 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4221 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4222 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4223 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
4224 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4225 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
4227 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4228 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4230 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4231 u32 index = vmx_msr_index[i];
4232 u32 data_low, data_high;
4235 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4237 if (wrmsr_safe(index, data_low, data_high) < 0)
4239 vmx->guest_msrs[j].index = i;
4240 vmx->guest_msrs[j].data = 0;
4241 vmx->guest_msrs[j].mask = -1ull;
4245 vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
4247 /* 22.2.1, 20.8.1 */
4248 vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
4250 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
4251 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
4253 set_cr4_guest_host_mask(vmx);
4255 if (vmx_xsaves_supported())
4256 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4259 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4260 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4263 if (cpu_has_vmx_encls_vmexit())
4264 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
4266 if (pt_mode == PT_MODE_HOST_GUEST) {
4267 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4268 /* Bit[6~0] are forced to 1, writes are ignored. */
4269 vmx->pt_desc.guest.output_mask = 0x7F;
4270 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4274 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4276 struct vcpu_vmx *vmx = to_vmx(vcpu);
4277 struct msr_data apic_base_msr;
4280 vmx->rmode.vm86_active = 0;
4283 vmx->msr_ia32_umwait_control = 0;
4285 vcpu->arch.microcode_version = 0x100000000ULL;
4286 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4287 vmx->hv_deadline_tsc = -1;
4288 kvm_set_cr8(vcpu, 0);
4291 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4292 MSR_IA32_APICBASE_ENABLE;
4293 if (kvm_vcpu_is_reset_bsp(vcpu))
4294 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4295 apic_base_msr.host_initiated = true;
4296 kvm_set_apic_base(vcpu, &apic_base_msr);
4299 vmx_segment_cache_clear(vmx);
4301 seg_setup(VCPU_SREG_CS);
4302 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4303 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4305 seg_setup(VCPU_SREG_DS);
4306 seg_setup(VCPU_SREG_ES);
4307 seg_setup(VCPU_SREG_FS);
4308 seg_setup(VCPU_SREG_GS);
4309 seg_setup(VCPU_SREG_SS);
4311 vmcs_write16(GUEST_TR_SELECTOR, 0);
4312 vmcs_writel(GUEST_TR_BASE, 0);
4313 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4314 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4316 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4317 vmcs_writel(GUEST_LDTR_BASE, 0);
4318 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4319 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4322 vmcs_write32(GUEST_SYSENTER_CS, 0);
4323 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4324 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4325 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4328 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
4329 kvm_rip_write(vcpu, 0xfff0);
4331 vmcs_writel(GUEST_GDTR_BASE, 0);
4332 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4334 vmcs_writel(GUEST_IDTR_BASE, 0);
4335 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4337 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4338 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4339 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4340 if (kvm_mpx_supported())
4341 vmcs_write64(GUEST_BNDCFGS, 0);
4345 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4347 if (cpu_has_vmx_tpr_shadow() && !init_event) {
4348 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4349 if (cpu_need_tpr_shadow(vcpu))
4350 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4351 __pa(vcpu->arch.apic->regs));
4352 vmcs_write32(TPR_THRESHOLD, 0);
4355 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4358 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4360 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4361 vmx->vcpu.arch.cr0 = cr0;
4362 vmx_set_cr0(vcpu, cr0); /* enter rmode */
4363 vmx_set_cr4(vcpu, 0);
4364 vmx_set_efer(vcpu, 0);
4366 update_exception_bitmap(vcpu);
4368 vpid_sync_context(vmx->vpid);
4370 vmx_clear_hlt(vcpu);
4373 static void enable_irq_window(struct kvm_vcpu *vcpu)
4375 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_INTR_PENDING);
4378 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4381 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4382 enable_irq_window(vcpu);
4386 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_NMI_PENDING);
4389 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4391 struct vcpu_vmx *vmx = to_vmx(vcpu);
4393 int irq = vcpu->arch.interrupt.nr;
4395 trace_kvm_inj_virq(irq);
4397 ++vcpu->stat.irq_injections;
4398 if (vmx->rmode.vm86_active) {
4400 if (vcpu->arch.interrupt.soft)
4401 inc_eip = vcpu->arch.event_exit_inst_len;
4402 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
4405 intr = irq | INTR_INFO_VALID_MASK;
4406 if (vcpu->arch.interrupt.soft) {
4407 intr |= INTR_TYPE_SOFT_INTR;
4408 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4409 vmx->vcpu.arch.event_exit_inst_len);
4411 intr |= INTR_TYPE_EXT_INTR;
4412 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4414 vmx_clear_hlt(vcpu);
4417 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4419 struct vcpu_vmx *vmx = to_vmx(vcpu);
4423 * Tracking the NMI-blocked state in software is built upon
4424 * finding the next open IRQ window. This, in turn, depends on
4425 * well-behaving guests: They have to keep IRQs disabled at
4426 * least as long as the NMI handler runs. Otherwise we may
4427 * cause NMI nesting, maybe breaking the guest. But as this is
4428 * highly unlikely, we can live with the residual risk.
4430 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4431 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4434 ++vcpu->stat.nmi_injections;
4435 vmx->loaded_vmcs->nmi_known_unmasked = false;
4437 if (vmx->rmode.vm86_active) {
4438 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
4442 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4443 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4445 vmx_clear_hlt(vcpu);
4448 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4450 struct vcpu_vmx *vmx = to_vmx(vcpu);
4454 return vmx->loaded_vmcs->soft_vnmi_blocked;
4455 if (vmx->loaded_vmcs->nmi_known_unmasked)
4457 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4458 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4462 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4464 struct vcpu_vmx *vmx = to_vmx(vcpu);
4467 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4468 vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4469 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4472 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4474 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4475 GUEST_INTR_STATE_NMI);
4477 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4478 GUEST_INTR_STATE_NMI);
4482 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4484 if (to_vmx(vcpu)->nested.nested_run_pending)
4488 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4491 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4492 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4493 | GUEST_INTR_STATE_NMI));
4496 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4498 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4499 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4500 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4501 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4504 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4508 if (enable_unrestricted_guest)
4511 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4515 to_kvm_vmx(kvm)->tss_addr = addr;
4516 return init_rmode_tss(kvm);
4519 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4521 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
4525 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4530 * Update instruction length as we may reinject the exception
4531 * from user space while in guest debugging mode.
4533 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4534 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4535 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4539 if (vcpu->guest_debug &
4540 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4557 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4558 int vec, u32 err_code)
4561 * Instruction with address size override prefix opcode 0x67
4562 * Cause the #SS fault with 0 error code in VM86 mode.
4564 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4565 if (kvm_emulate_instruction(vcpu, 0)) {
4566 if (vcpu->arch.halt_request) {
4567 vcpu->arch.halt_request = 0;
4568 return kvm_vcpu_halt(vcpu);
4576 * Forward all other exceptions that are valid in real mode.
4577 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4578 * the required debugging infrastructure rework.
4580 kvm_queue_exception(vcpu, vec);
4585 * Trigger machine check on the host. We assume all the MSRs are already set up
4586 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4587 * We pass a fake environment to the machine check handler because we want
4588 * the guest to be always treated like user space, no matter what context
4589 * it used internally.
4591 static void kvm_machine_check(void)
4593 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4594 struct pt_regs regs = {
4595 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4596 .flags = X86_EFLAGS_IF,
4599 do_machine_check(®s, 0);
4603 static int handle_machine_check(struct kvm_vcpu *vcpu)
4605 /* handled by vmx_vcpu_run() */
4609 static int handle_exception_nmi(struct kvm_vcpu *vcpu)
4611 struct vcpu_vmx *vmx = to_vmx(vcpu);
4612 struct kvm_run *kvm_run = vcpu->run;
4613 u32 intr_info, ex_no, error_code;
4614 unsigned long cr2, rip, dr6;
4617 vect_info = vmx->idt_vectoring_info;
4618 intr_info = vmx->exit_intr_info;
4620 if (is_machine_check(intr_info) || is_nmi(intr_info))
4621 return 1; /* handled by handle_exception_nmi_irqoff() */
4623 if (is_invalid_opcode(intr_info))
4624 return handle_ud(vcpu);
4627 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4628 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4630 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4631 WARN_ON_ONCE(!enable_vmware_backdoor);
4634 * VMware backdoor emulation on #GP interception only handles
4635 * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
4636 * error code on #GP.
4639 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4642 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
4646 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4647 * MMIO, it is better to report an internal error.
4648 * See the comments in vmx_handle_exit.
4650 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4651 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4652 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4653 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4654 vcpu->run->internal.ndata = 3;
4655 vcpu->run->internal.data[0] = vect_info;
4656 vcpu->run->internal.data[1] = intr_info;
4657 vcpu->run->internal.data[2] = error_code;
4661 if (is_page_fault(intr_info)) {
4662 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4663 /* EPT won't cause page fault directly */
4664 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
4665 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
4668 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4670 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4671 return handle_rmode_exception(vcpu, ex_no, error_code);
4675 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4678 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4679 if (!(vcpu->guest_debug &
4680 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4681 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4682 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4683 if (is_icebp(intr_info))
4684 WARN_ON(!skip_emulated_instruction(vcpu));
4686 kvm_queue_exception(vcpu, DB_VECTOR);
4689 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4690 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4694 * Update instruction length as we may reinject #BP from
4695 * user space while in guest debugging mode. Reading it for
4696 * #DB as well causes no harm, it is not used in that case.
4698 vmx->vcpu.arch.event_exit_inst_len =
4699 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4700 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4701 rip = kvm_rip_read(vcpu);
4702 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4703 kvm_run->debug.arch.exception = ex_no;
4706 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4707 kvm_run->ex.exception = ex_no;
4708 kvm_run->ex.error_code = error_code;
4714 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4716 ++vcpu->stat.irq_exits;
4720 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4722 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4723 vcpu->mmio_needed = 0;
4727 static int handle_io(struct kvm_vcpu *vcpu)
4729 unsigned long exit_qualification;
4730 int size, in, string;
4733 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4734 string = (exit_qualification & 16) != 0;
4736 ++vcpu->stat.io_exits;
4739 return kvm_emulate_instruction(vcpu, 0);
4741 port = exit_qualification >> 16;
4742 size = (exit_qualification & 7) + 1;
4743 in = (exit_qualification & 8) != 0;
4745 return kvm_fast_pio(vcpu, size, port, in);
4749 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4752 * Patch in the VMCALL instruction:
4754 hypercall[0] = 0x0f;
4755 hypercall[1] = 0x01;
4756 hypercall[2] = 0xc1;
4759 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4760 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4762 if (is_guest_mode(vcpu)) {
4763 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4764 unsigned long orig_val = val;
4767 * We get here when L2 changed cr0 in a way that did not change
4768 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4769 * but did change L0 shadowed bits. So we first calculate the
4770 * effective cr0 value that L1 would like to write into the
4771 * hardware. It consists of the L2-owned bits from the new
4772 * value combined with the L1-owned bits from L1's guest_cr0.
4774 val = (val & ~vmcs12->cr0_guest_host_mask) |
4775 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4777 if (!nested_guest_cr0_valid(vcpu, val))
4780 if (kvm_set_cr0(vcpu, val))
4782 vmcs_writel(CR0_READ_SHADOW, orig_val);
4785 if (to_vmx(vcpu)->nested.vmxon &&
4786 !nested_host_cr0_valid(vcpu, val))
4789 return kvm_set_cr0(vcpu, val);
4793 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4795 if (is_guest_mode(vcpu)) {
4796 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4797 unsigned long orig_val = val;
4799 /* analogously to handle_set_cr0 */
4800 val = (val & ~vmcs12->cr4_guest_host_mask) |
4801 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4802 if (kvm_set_cr4(vcpu, val))
4804 vmcs_writel(CR4_READ_SHADOW, orig_val);
4807 return kvm_set_cr4(vcpu, val);
4810 static int handle_desc(struct kvm_vcpu *vcpu)
4812 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
4813 return kvm_emulate_instruction(vcpu, 0);
4816 static int handle_cr(struct kvm_vcpu *vcpu)
4818 unsigned long exit_qualification, val;
4824 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4825 cr = exit_qualification & 15;
4826 reg = (exit_qualification >> 8) & 15;
4827 switch ((exit_qualification >> 4) & 3) {
4828 case 0: /* mov to cr */
4829 val = kvm_register_readl(vcpu, reg);
4830 trace_kvm_cr_write(cr, val);
4833 err = handle_set_cr0(vcpu, val);
4834 return kvm_complete_insn_gp(vcpu, err);
4836 WARN_ON_ONCE(enable_unrestricted_guest);
4837 err = kvm_set_cr3(vcpu, val);
4838 return kvm_complete_insn_gp(vcpu, err);
4840 err = handle_set_cr4(vcpu, val);
4841 return kvm_complete_insn_gp(vcpu, err);
4843 u8 cr8_prev = kvm_get_cr8(vcpu);
4845 err = kvm_set_cr8(vcpu, cr8);
4846 ret = kvm_complete_insn_gp(vcpu, err);
4847 if (lapic_in_kernel(vcpu))
4849 if (cr8_prev <= cr8)
4852 * TODO: we might be squashing a
4853 * KVM_GUESTDBG_SINGLESTEP-triggered
4854 * KVM_EXIT_DEBUG here.
4856 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4862 WARN_ONCE(1, "Guest should always own CR0.TS");
4863 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4864 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4865 return kvm_skip_emulated_instruction(vcpu);
4866 case 1: /*mov from cr*/
4869 WARN_ON_ONCE(enable_unrestricted_guest);
4870 val = kvm_read_cr3(vcpu);
4871 kvm_register_write(vcpu, reg, val);
4872 trace_kvm_cr_read(cr, val);
4873 return kvm_skip_emulated_instruction(vcpu);
4875 val = kvm_get_cr8(vcpu);
4876 kvm_register_write(vcpu, reg, val);
4877 trace_kvm_cr_read(cr, val);
4878 return kvm_skip_emulated_instruction(vcpu);
4882 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4883 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4884 kvm_lmsw(vcpu, val);
4886 return kvm_skip_emulated_instruction(vcpu);
4890 vcpu->run->exit_reason = 0;
4891 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4892 (int)(exit_qualification >> 4) & 3, cr);
4896 static int handle_dr(struct kvm_vcpu *vcpu)
4898 unsigned long exit_qualification;
4901 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4902 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4904 /* First, if DR does not exist, trigger UD */
4905 if (!kvm_require_dr(vcpu, dr))
4908 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4909 if (!kvm_require_cpl(vcpu, 0))
4911 dr7 = vmcs_readl(GUEST_DR7);
4914 * As the vm-exit takes precedence over the debug trap, we
4915 * need to emulate the latter, either for the host or the
4916 * guest debugging itself.
4918 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4919 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4920 vcpu->run->debug.arch.dr7 = dr7;
4921 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
4922 vcpu->run->debug.arch.exception = DB_VECTOR;
4923 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4926 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4927 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
4928 kvm_queue_exception(vcpu, DB_VECTOR);
4933 if (vcpu->guest_debug == 0) {
4934 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
4937 * No more DR vmexits; force a reload of the debug registers
4938 * and reenter on this instruction. The next vmexit will
4939 * retrieve the full state of the debug registers.
4941 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4945 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4946 if (exit_qualification & TYPE_MOV_FROM_DR) {
4949 if (kvm_get_dr(vcpu, dr, &val))
4951 kvm_register_write(vcpu, reg, val);
4953 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4956 return kvm_skip_emulated_instruction(vcpu);
4959 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
4961 return vcpu->arch.dr6;
4964 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
4968 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
4970 get_debugreg(vcpu->arch.db[0], 0);
4971 get_debugreg(vcpu->arch.db[1], 1);
4972 get_debugreg(vcpu->arch.db[2], 2);
4973 get_debugreg(vcpu->arch.db[3], 3);
4974 get_debugreg(vcpu->arch.dr6, 6);
4975 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
4977 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
4978 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
4981 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4983 vmcs_writel(GUEST_DR7, val);
4986 static int handle_cpuid(struct kvm_vcpu *vcpu)
4988 return kvm_emulate_cpuid(vcpu);
4991 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4993 return kvm_emulate_rdmsr(vcpu);
4996 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4998 return kvm_emulate_wrmsr(vcpu);
5001 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5003 kvm_apic_update_ppr(vcpu);
5007 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5009 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_INTR_PENDING);
5011 kvm_make_request(KVM_REQ_EVENT, vcpu);
5013 ++vcpu->stat.irq_window_exits;
5017 static int handle_halt(struct kvm_vcpu *vcpu)
5019 return kvm_emulate_halt(vcpu);
5022 static int handle_vmcall(struct kvm_vcpu *vcpu)
5024 return kvm_emulate_hypercall(vcpu);
5027 static int handle_invd(struct kvm_vcpu *vcpu)
5029 return kvm_emulate_instruction(vcpu, 0);
5032 static int handle_invlpg(struct kvm_vcpu *vcpu)
5034 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5036 kvm_mmu_invlpg(vcpu, exit_qualification);
5037 return kvm_skip_emulated_instruction(vcpu);
5040 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5044 err = kvm_rdpmc(vcpu);
5045 return kvm_complete_insn_gp(vcpu, err);
5048 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5050 return kvm_emulate_wbinvd(vcpu);
5053 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5055 u64 new_bv = kvm_read_edx_eax(vcpu);
5056 u32 index = kvm_rcx_read(vcpu);
5058 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5059 return kvm_skip_emulated_instruction(vcpu);
5063 static int handle_apic_access(struct kvm_vcpu *vcpu)
5065 if (likely(fasteoi)) {
5066 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5067 int access_type, offset;
5069 access_type = exit_qualification & APIC_ACCESS_TYPE;
5070 offset = exit_qualification & APIC_ACCESS_OFFSET;
5072 * Sane guest uses MOV to write EOI, with written value
5073 * not cared. So make a short-circuit here by avoiding
5074 * heavy instruction emulation.
5076 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5077 (offset == APIC_EOI)) {
5078 kvm_lapic_set_eoi(vcpu);
5079 return kvm_skip_emulated_instruction(vcpu);
5082 return kvm_emulate_instruction(vcpu, 0);
5085 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5087 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5088 int vector = exit_qualification & 0xff;
5090 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5091 kvm_apic_set_eoi_accelerated(vcpu, vector);
5095 static int handle_apic_write(struct kvm_vcpu *vcpu)
5097 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5098 u32 offset = exit_qualification & 0xfff;
5100 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5101 kvm_apic_write_nodecode(vcpu, offset);
5105 static int handle_task_switch(struct kvm_vcpu *vcpu)
5107 struct vcpu_vmx *vmx = to_vmx(vcpu);
5108 unsigned long exit_qualification;
5109 bool has_error_code = false;
5112 int reason, type, idt_v, idt_index;
5114 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5115 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5116 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5118 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5120 reason = (u32)exit_qualification >> 30;
5121 if (reason == TASK_SWITCH_GATE && idt_v) {
5123 case INTR_TYPE_NMI_INTR:
5124 vcpu->arch.nmi_injected = false;
5125 vmx_set_nmi_mask(vcpu, true);
5127 case INTR_TYPE_EXT_INTR:
5128 case INTR_TYPE_SOFT_INTR:
5129 kvm_clear_interrupt_queue(vcpu);
5131 case INTR_TYPE_HARD_EXCEPTION:
5132 if (vmx->idt_vectoring_info &
5133 VECTORING_INFO_DELIVER_CODE_MASK) {
5134 has_error_code = true;
5136 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5139 case INTR_TYPE_SOFT_EXCEPTION:
5140 kvm_clear_exception_queue(vcpu);
5146 tss_selector = exit_qualification;
5148 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5149 type != INTR_TYPE_EXT_INTR &&
5150 type != INTR_TYPE_NMI_INTR))
5151 WARN_ON(!skip_emulated_instruction(vcpu));
5154 * TODO: What about debug traps on tss switch?
5155 * Are we supposed to inject them and update dr6?
5157 return kvm_task_switch(vcpu, tss_selector,
5158 type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
5159 reason, has_error_code, error_code);
5162 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5164 unsigned long exit_qualification;
5168 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5171 * EPT violation happened while executing iret from NMI,
5172 * "blocked by NMI" bit has to be set before next VM entry.
5173 * There are errata that may cause this bit to not be set:
5176 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5178 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5179 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5181 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5182 trace_kvm_page_fault(gpa, exit_qualification);
5184 /* Is it a read fault? */
5185 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
5186 ? PFERR_USER_MASK : 0;
5187 /* Is it a write fault? */
5188 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
5189 ? PFERR_WRITE_MASK : 0;
5190 /* Is it a fetch fault? */
5191 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
5192 ? PFERR_FETCH_MASK : 0;
5193 /* ept page table entry is present? */
5194 error_code |= (exit_qualification &
5195 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5196 EPT_VIOLATION_EXECUTABLE))
5197 ? PFERR_PRESENT_MASK : 0;
5199 error_code |= (exit_qualification & 0x100) != 0 ?
5200 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
5202 vcpu->arch.exit_qualification = exit_qualification;
5203 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5206 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5211 * A nested guest cannot optimize MMIO vmexits, because we have an
5212 * nGPA here instead of the required GPA.
5214 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5215 if (!is_guest_mode(vcpu) &&
5216 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5217 trace_kvm_fast_mmio(gpa);
5218 return kvm_skip_emulated_instruction(vcpu);
5221 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
5224 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5226 WARN_ON_ONCE(!enable_vnmi);
5227 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_NMI_PENDING);
5228 ++vcpu->stat.nmi_window_exits;
5229 kvm_make_request(KVM_REQ_EVENT, vcpu);
5234 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5236 struct vcpu_vmx *vmx = to_vmx(vcpu);
5237 bool intr_window_requested;
5238 unsigned count = 130;
5241 * We should never reach the point where we are emulating L2
5242 * due to invalid guest state as that means we incorrectly
5243 * allowed a nested VMEntry with an invalid vmcs12.
5245 WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
5247 intr_window_requested = exec_controls_get(vmx) &
5248 CPU_BASED_VIRTUAL_INTR_PENDING;
5250 while (vmx->emulation_required && count-- != 0) {
5251 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5252 return handle_interrupt_window(&vmx->vcpu);
5254 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
5257 if (!kvm_emulate_instruction(vcpu, 0))
5260 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5261 vcpu->arch.exception.pending) {
5262 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5263 vcpu->run->internal.suberror =
5264 KVM_INTERNAL_ERROR_EMULATION;
5265 vcpu->run->internal.ndata = 0;
5269 if (vcpu->arch.halt_request) {
5270 vcpu->arch.halt_request = 0;
5271 return kvm_vcpu_halt(vcpu);
5275 * Note, return 1 and not 0, vcpu_run() is responsible for
5276 * morphing the pending signal into the proper return code.
5278 if (signal_pending(current))
5288 static void grow_ple_window(struct kvm_vcpu *vcpu)
5290 struct vcpu_vmx *vmx = to_vmx(vcpu);
5291 unsigned int old = vmx->ple_window;
5293 vmx->ple_window = __grow_ple_window(old, ple_window,
5297 if (vmx->ple_window != old) {
5298 vmx->ple_window_dirty = true;
5299 trace_kvm_ple_window_update(vcpu->vcpu_id,
5300 vmx->ple_window, old);
5304 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5306 struct vcpu_vmx *vmx = to_vmx(vcpu);
5307 unsigned int old = vmx->ple_window;
5309 vmx->ple_window = __shrink_ple_window(old, ple_window,
5313 if (vmx->ple_window != old) {
5314 vmx->ple_window_dirty = true;
5315 trace_kvm_ple_window_update(vcpu->vcpu_id,
5316 vmx->ple_window, old);
5321 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
5323 static void wakeup_handler(void)
5325 struct kvm_vcpu *vcpu;
5326 int cpu = smp_processor_id();
5328 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5329 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
5330 blocked_vcpu_list) {
5331 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
5333 if (pi_test_on(pi_desc) == 1)
5334 kvm_vcpu_kick(vcpu);
5336 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5339 static void vmx_enable_tdp(void)
5341 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
5342 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
5343 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
5344 0ull, VMX_EPT_EXECUTABLE_MASK,
5345 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
5346 VMX_EPT_RWX_MASK, 0ull);
5348 ept_set_mmio_spte_mask();
5353 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5354 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5356 static int handle_pause(struct kvm_vcpu *vcpu)
5358 if (!kvm_pause_in_guest(vcpu->kvm))
5359 grow_ple_window(vcpu);
5362 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5363 * VM-execution control is ignored if CPL > 0. OTOH, KVM
5364 * never set PAUSE_EXITING and just set PLE if supported,
5365 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5367 kvm_vcpu_on_spin(vcpu, true);
5368 return kvm_skip_emulated_instruction(vcpu);
5371 static int handle_nop(struct kvm_vcpu *vcpu)
5373 return kvm_skip_emulated_instruction(vcpu);
5376 static int handle_mwait(struct kvm_vcpu *vcpu)
5378 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5379 return handle_nop(vcpu);
5382 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5384 kvm_queue_exception(vcpu, UD_VECTOR);
5388 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5393 static int handle_monitor(struct kvm_vcpu *vcpu)
5395 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5396 return handle_nop(vcpu);
5399 static int handle_invpcid(struct kvm_vcpu *vcpu)
5401 u32 vmx_instruction_info;
5405 struct x86_exception e;
5407 unsigned long roots_to_free = 0;
5413 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
5414 kvm_queue_exception(vcpu, UD_VECTOR);
5418 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5419 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5422 kvm_inject_gp(vcpu, 0);
5426 /* According to the Intel instruction reference, the memory operand
5427 * is read even if it isn't needed (e.g., for type==all)
5429 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5430 vmx_instruction_info, false,
5431 sizeof(operand), &gva))
5434 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
5435 kvm_inject_page_fault(vcpu, &e);
5439 if (operand.pcid >> 12 != 0) {
5440 kvm_inject_gp(vcpu, 0);
5444 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
5447 case INVPCID_TYPE_INDIV_ADDR:
5448 if ((!pcid_enabled && (operand.pcid != 0)) ||
5449 is_noncanonical_address(operand.gla, vcpu)) {
5450 kvm_inject_gp(vcpu, 0);
5453 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
5454 return kvm_skip_emulated_instruction(vcpu);
5456 case INVPCID_TYPE_SINGLE_CTXT:
5457 if (!pcid_enabled && (operand.pcid != 0)) {
5458 kvm_inject_gp(vcpu, 0);
5462 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
5463 kvm_mmu_sync_roots(vcpu);
5464 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
5467 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5468 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3)
5470 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
5472 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
5474 * If neither the current cr3 nor any of the prev_roots use the
5475 * given PCID, then nothing needs to be done here because a
5476 * resync will happen anyway before switching to any other CR3.
5479 return kvm_skip_emulated_instruction(vcpu);
5481 case INVPCID_TYPE_ALL_NON_GLOBAL:
5483 * Currently, KVM doesn't mark global entries in the shadow
5484 * page tables, so a non-global flush just degenerates to a
5485 * global flush. If needed, we could optimize this later by
5486 * keeping track of global entries in shadow page tables.
5490 case INVPCID_TYPE_ALL_INCL_GLOBAL:
5491 kvm_mmu_unload(vcpu);
5492 return kvm_skip_emulated_instruction(vcpu);
5495 BUG(); /* We have already checked above that type <= 3 */
5499 static int handle_pml_full(struct kvm_vcpu *vcpu)
5501 unsigned long exit_qualification;
5503 trace_kvm_pml_full(vcpu->vcpu_id);
5505 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5508 * PML buffer FULL happened while executing iret from NMI,
5509 * "blocked by NMI" bit has to be set before next VM entry.
5511 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5513 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5514 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5515 GUEST_INTR_STATE_NMI);
5518 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5519 * here.., and there's no userspace involvement needed for PML.
5524 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
5526 struct vcpu_vmx *vmx = to_vmx(vcpu);
5528 if (!vmx->req_immediate_exit &&
5529 !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled))
5530 kvm_lapic_expired_hv_timer(vcpu);
5536 * When nested=0, all VMX instruction VM Exits filter here. The handlers
5537 * are overwritten by nested_vmx_setup() when nested=1.
5539 static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
5541 kvm_queue_exception(vcpu, UD_VECTOR);
5545 static int handle_encls(struct kvm_vcpu *vcpu)
5548 * SGX virtualization is not yet supported. There is no software
5549 * enable bit for SGX, so we have to trap ENCLS and inject a #UD
5550 * to prevent the guest from executing ENCLS.
5552 kvm_queue_exception(vcpu, UD_VECTOR);
5557 * The exit handlers return 1 if the exit was handled fully and guest execution
5558 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5559 * to be done to userspace and return 0.
5561 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5562 [EXIT_REASON_EXCEPTION_NMI] = handle_exception_nmi,
5563 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
5564 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
5565 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
5566 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
5567 [EXIT_REASON_CR_ACCESS] = handle_cr,
5568 [EXIT_REASON_DR_ACCESS] = handle_dr,
5569 [EXIT_REASON_CPUID] = handle_cpuid,
5570 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5571 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5572 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5573 [EXIT_REASON_HLT] = handle_halt,
5574 [EXIT_REASON_INVD] = handle_invd,
5575 [EXIT_REASON_INVLPG] = handle_invlpg,
5576 [EXIT_REASON_RDPMC] = handle_rdpmc,
5577 [EXIT_REASON_VMCALL] = handle_vmcall,
5578 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction,
5579 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction,
5580 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction,
5581 [EXIT_REASON_VMPTRST] = handle_vmx_instruction,
5582 [EXIT_REASON_VMREAD] = handle_vmx_instruction,
5583 [EXIT_REASON_VMRESUME] = handle_vmx_instruction,
5584 [EXIT_REASON_VMWRITE] = handle_vmx_instruction,
5585 [EXIT_REASON_VMOFF] = handle_vmx_instruction,
5586 [EXIT_REASON_VMON] = handle_vmx_instruction,
5587 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5588 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
5589 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
5590 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
5591 [EXIT_REASON_WBINVD] = handle_wbinvd,
5592 [EXIT_REASON_XSETBV] = handle_xsetbv,
5593 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
5594 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
5595 [EXIT_REASON_GDTR_IDTR] = handle_desc,
5596 [EXIT_REASON_LDTR_TR] = handle_desc,
5597 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5598 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
5599 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
5600 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
5601 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
5602 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
5603 [EXIT_REASON_INVEPT] = handle_vmx_instruction,
5604 [EXIT_REASON_INVVPID] = handle_vmx_instruction,
5605 [EXIT_REASON_RDRAND] = handle_invalid_op,
5606 [EXIT_REASON_RDSEED] = handle_invalid_op,
5607 [EXIT_REASON_PML_FULL] = handle_pml_full,
5608 [EXIT_REASON_INVPCID] = handle_invpcid,
5609 [EXIT_REASON_VMFUNC] = handle_vmx_instruction,
5610 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
5611 [EXIT_REASON_ENCLS] = handle_encls,
5614 static const int kvm_vmx_max_exit_handlers =
5615 ARRAY_SIZE(kvm_vmx_exit_handlers);
5617 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5619 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5620 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5623 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
5626 __free_page(vmx->pml_pg);
5631 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
5633 struct vcpu_vmx *vmx = to_vmx(vcpu);
5637 pml_idx = vmcs_read16(GUEST_PML_INDEX);
5639 /* Do nothing if PML buffer is empty */
5640 if (pml_idx == (PML_ENTITY_NUM - 1))
5643 /* PML index always points to next available PML buffer entity */
5644 if (pml_idx >= PML_ENTITY_NUM)
5649 pml_buf = page_address(vmx->pml_pg);
5650 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5653 gpa = pml_buf[pml_idx];
5654 WARN_ON(gpa & (PAGE_SIZE - 1));
5655 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5658 /* reset PML index */
5659 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5663 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
5664 * Called before reporting dirty_bitmap to userspace.
5666 static void kvm_flush_pml_buffers(struct kvm *kvm)
5669 struct kvm_vcpu *vcpu;
5671 * We only need to kick vcpu out of guest mode here, as PML buffer
5672 * is flushed at beginning of all VMEXITs, and it's obvious that only
5673 * vcpus running in guest are possible to have unflushed GPAs in PML
5676 kvm_for_each_vcpu(i, vcpu, kvm)
5677 kvm_vcpu_kick(vcpu);
5680 static void vmx_dump_sel(char *name, uint32_t sel)
5682 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5683 name, vmcs_read16(sel),
5684 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5685 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5686 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
5689 static void vmx_dump_dtsel(char *name, uint32_t limit)
5691 pr_err("%s limit=0x%08x, base=0x%016lx\n",
5692 name, vmcs_read32(limit),
5693 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
5696 void dump_vmcs(void)
5698 u32 vmentry_ctl, vmexit_ctl;
5699 u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5704 if (!dump_invalid_vmcs) {
5705 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5709 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5710 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5711 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5712 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5713 cr4 = vmcs_readl(GUEST_CR4);
5714 efer = vmcs_read64(GUEST_IA32_EFER);
5715 secondary_exec_control = 0;
5716 if (cpu_has_secondary_exec_ctrls())
5717 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5719 pr_err("*** Guest State ***\n");
5720 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5721 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5722 vmcs_readl(CR0_GUEST_HOST_MASK));
5723 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5724 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5725 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5726 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
5727 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
5729 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
5730 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5731 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
5732 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
5734 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
5735 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5736 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
5737 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5738 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5739 vmcs_readl(GUEST_SYSENTER_ESP),
5740 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5741 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
5742 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
5743 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
5744 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
5745 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
5746 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
5747 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5748 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5749 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5750 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
5751 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
5752 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
5753 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5754 efer, vmcs_read64(GUEST_IA32_PAT));
5755 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
5756 vmcs_read64(GUEST_IA32_DEBUGCTL),
5757 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5758 if (cpu_has_load_perf_global_ctrl() &&
5759 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5760 pr_err("PerfGlobCtl = 0x%016llx\n",
5761 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5762 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5763 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5764 pr_err("Interruptibility = %08x ActivityState = %08x\n",
5765 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5766 vmcs_read32(GUEST_ACTIVITY_STATE));
5767 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5768 pr_err("InterruptStatus = %04x\n",
5769 vmcs_read16(GUEST_INTR_STATUS));
5771 pr_err("*** Host State ***\n");
5772 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
5773 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5774 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5775 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5776 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5777 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5778 vmcs_read16(HOST_TR_SELECTOR));
5779 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5780 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5781 vmcs_readl(HOST_TR_BASE));
5782 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5783 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5784 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5785 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5786 vmcs_readl(HOST_CR4));
5787 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5788 vmcs_readl(HOST_IA32_SYSENTER_ESP),
5789 vmcs_read32(HOST_IA32_SYSENTER_CS),
5790 vmcs_readl(HOST_IA32_SYSENTER_EIP));
5791 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
5792 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5793 vmcs_read64(HOST_IA32_EFER),
5794 vmcs_read64(HOST_IA32_PAT));
5795 if (cpu_has_load_perf_global_ctrl() &&
5796 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5797 pr_err("PerfGlobCtl = 0x%016llx\n",
5798 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
5800 pr_err("*** Control State ***\n");
5801 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5802 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5803 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5804 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5805 vmcs_read32(EXCEPTION_BITMAP),
5806 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5807 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5808 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5809 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5810 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5811 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5812 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5813 vmcs_read32(VM_EXIT_INTR_INFO),
5814 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5815 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5816 pr_err(" reason=%08x qualification=%016lx\n",
5817 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5818 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5819 vmcs_read32(IDT_VECTORING_INFO_FIELD),
5820 vmcs_read32(IDT_VECTORING_ERROR_CODE));
5821 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5822 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5823 pr_err("TSC Multiplier = 0x%016llx\n",
5824 vmcs_read64(TSC_MULTIPLIER));
5825 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5826 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5827 u16 status = vmcs_read16(GUEST_INTR_STATUS);
5828 pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5830 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
5831 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5832 pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
5833 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
5835 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5836 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5837 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5838 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5839 n = vmcs_read32(CR3_TARGET_COUNT);
5840 for (i = 0; i + 1 < n; i += 4)
5841 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
5842 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
5843 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
5845 pr_err("CR3 target%u=%016lx\n",
5846 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
5847 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5848 pr_err("PLE Gap=%08x Window=%08x\n",
5849 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5850 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5851 pr_err("Virtual processor ID = 0x%04x\n",
5852 vmcs_read16(VIRTUAL_PROCESSOR_ID));
5856 * The guest has exited. See if we can fix it or if we need userspace
5859 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5861 struct vcpu_vmx *vmx = to_vmx(vcpu);
5862 u32 exit_reason = vmx->exit_reason;
5863 u32 vectoring_info = vmx->idt_vectoring_info;
5865 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
5868 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5869 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5870 * querying dirty_bitmap, we only need to kick all vcpus out of guest
5871 * mode as if vcpus is in root mode, the PML buffer must has been
5875 vmx_flush_pml_buffer(vcpu);
5877 /* If guest state is invalid, start emulating */
5878 if (vmx->emulation_required)
5879 return handle_invalid_guest_state(vcpu);
5881 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
5882 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
5884 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5886 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5887 vcpu->run->fail_entry.hardware_entry_failure_reason
5892 if (unlikely(vmx->fail)) {
5894 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5895 vcpu->run->fail_entry.hardware_entry_failure_reason
5896 = vmcs_read32(VM_INSTRUCTION_ERROR);
5902 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5903 * delivery event since it indicates guest is accessing MMIO.
5904 * The vm-exit can be triggered again after return to guest that
5905 * will cause infinite loop.
5907 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5908 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5909 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5910 exit_reason != EXIT_REASON_PML_FULL &&
5911 exit_reason != EXIT_REASON_TASK_SWITCH)) {
5912 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5913 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5914 vcpu->run->internal.ndata = 3;
5915 vcpu->run->internal.data[0] = vectoring_info;
5916 vcpu->run->internal.data[1] = exit_reason;
5917 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5918 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
5919 vcpu->run->internal.ndata++;
5920 vcpu->run->internal.data[3] =
5921 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5926 if (unlikely(!enable_vnmi &&
5927 vmx->loaded_vmcs->soft_vnmi_blocked)) {
5928 if (vmx_interrupt_allowed(vcpu)) {
5929 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5930 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5931 vcpu->arch.nmi_pending) {
5933 * This CPU don't support us in finding the end of an
5934 * NMI-blocked window if the guest runs with IRQs
5935 * disabled. So we pull the trigger after 1 s of
5936 * futile waiting, but inform the user about this.
5938 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5939 "state on VCPU %d after 1 s timeout\n",
5940 __func__, vcpu->vcpu_id);
5941 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5945 if (exit_reason < kvm_vmx_max_exit_handlers
5946 && kvm_vmx_exit_handlers[exit_reason])
5947 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5949 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
5952 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5953 vcpu->run->internal.suberror =
5954 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
5955 vcpu->run->internal.ndata = 1;
5956 vcpu->run->internal.data[0] = exit_reason;
5962 * Software based L1D cache flush which is used when microcode providing
5963 * the cache control MSR is not loaded.
5965 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
5966 * flush it is required to read in 64 KiB because the replacement algorithm
5967 * is not exactly LRU. This could be sized at runtime via topology
5968 * information but as all relevant affected CPUs have 32KiB L1D cache size
5969 * there is no point in doing so.
5971 static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
5973 int size = PAGE_SIZE << L1D_CACHE_ORDER;
5976 * This code is only executed when the the flush mode is 'cond' or
5979 if (static_branch_likely(&vmx_l1d_flush_cond)) {
5983 * Clear the per-vcpu flush bit, it gets set again
5984 * either from vcpu_run() or from one of the unsafe
5987 flush_l1d = vcpu->arch.l1tf_flush_l1d;
5988 vcpu->arch.l1tf_flush_l1d = false;
5991 * Clear the per-cpu flush bit, it gets set again from
5992 * the interrupt handlers.
5994 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
5995 kvm_clear_cpu_l1tf_flush_l1d();
6001 vcpu->stat.l1d_flush++;
6003 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
6004 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
6009 /* First ensure the pages are in the TLB */
6010 "xorl %%eax, %%eax\n"
6011 ".Lpopulate_tlb:\n\t"
6012 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6013 "addl $4096, %%eax\n\t"
6014 "cmpl %%eax, %[size]\n\t"
6015 "jne .Lpopulate_tlb\n\t"
6016 "xorl %%eax, %%eax\n\t"
6018 /* Now fill the cache */
6019 "xorl %%eax, %%eax\n"
6021 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6022 "addl $64, %%eax\n\t"
6023 "cmpl %%eax, %[size]\n\t"
6024 "jne .Lfill_cache\n\t"
6026 :: [flush_pages] "r" (vmx_l1d_flush_pages),
6028 : "eax", "ebx", "ecx", "edx");
6031 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6033 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6035 if (is_guest_mode(vcpu) &&
6036 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
6039 if (irr == -1 || tpr < irr) {
6040 vmcs_write32(TPR_THRESHOLD, 0);
6044 vmcs_write32(TPR_THRESHOLD, irr);
6047 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
6049 struct vcpu_vmx *vmx = to_vmx(vcpu);
6050 u32 sec_exec_control;
6052 if (!lapic_in_kernel(vcpu))
6055 if (!flexpriority_enabled &&
6056 !cpu_has_vmx_virtualize_x2apic_mode())
6059 /* Postpone execution until vmcs01 is the current VMCS. */
6060 if (is_guest_mode(vcpu)) {
6061 vmx->nested.change_vmcs01_virtual_apic_mode = true;
6065 sec_exec_control = secondary_exec_controls_get(vmx);
6066 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6067 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
6069 switch (kvm_get_apic_mode(vcpu)) {
6070 case LAPIC_MODE_INVALID:
6071 WARN_ONCE(true, "Invalid local APIC state");
6072 case LAPIC_MODE_DISABLED:
6074 case LAPIC_MODE_XAPIC:
6075 if (flexpriority_enabled) {
6077 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6078 vmx_flush_tlb(vcpu, true);
6081 case LAPIC_MODE_X2APIC:
6082 if (cpu_has_vmx_virtualize_x2apic_mode())
6084 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6087 secondary_exec_controls_set(vmx, sec_exec_control);
6089 vmx_update_msr_bitmap(vcpu);
6092 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
6094 if (!is_guest_mode(vcpu)) {
6095 vmcs_write64(APIC_ACCESS_ADDR, hpa);
6096 vmx_flush_tlb(vcpu, true);
6100 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6108 status = vmcs_read16(GUEST_INTR_STATUS);
6110 if (max_isr != old) {
6112 status |= max_isr << 8;
6113 vmcs_write16(GUEST_INTR_STATUS, status);
6117 static void vmx_set_rvi(int vector)
6125 status = vmcs_read16(GUEST_INTR_STATUS);
6126 old = (u8)status & 0xff;
6127 if ((u8)vector != old) {
6129 status |= (u8)vector;
6130 vmcs_write16(GUEST_INTR_STATUS, status);
6134 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6137 * When running L2, updating RVI is only relevant when
6138 * vmcs12 virtual-interrupt-delivery enabled.
6139 * However, it can be enabled only when L1 also
6140 * intercepts external-interrupts and in that case
6141 * we should not update vmcs02 RVI but instead intercept
6142 * interrupt. Therefore, do nothing when running L2.
6144 if (!is_guest_mode(vcpu))
6145 vmx_set_rvi(max_irr);
6148 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6150 struct vcpu_vmx *vmx = to_vmx(vcpu);
6152 bool max_irr_updated;
6154 WARN_ON(!vcpu->arch.apicv_active);
6155 if (pi_test_on(&vmx->pi_desc)) {
6156 pi_clear_on(&vmx->pi_desc);
6158 * IOMMU can write to PID.ON, so the barrier matters even on UP.
6159 * But on x86 this is just a compiler barrier anyway.
6161 smp_mb__after_atomic();
6163 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
6166 * If we are running L2 and L1 has a new pending interrupt
6167 * which can be injected, we should re-evaluate
6168 * what should be done with this new L1 interrupt.
6169 * If L1 intercepts external-interrupts, we should
6170 * exit from L2 to L1. Otherwise, interrupt should be
6171 * delivered directly to L2.
6173 if (is_guest_mode(vcpu) && max_irr_updated) {
6174 if (nested_exit_on_intr(vcpu))
6175 kvm_vcpu_exiting_guest_mode(vcpu);
6177 kvm_make_request(KVM_REQ_EVENT, vcpu);
6180 max_irr = kvm_lapic_find_highest_irr(vcpu);
6182 vmx_hwapic_irr_update(vcpu, max_irr);
6186 static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
6188 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6190 return pi_test_on(pi_desc) ||
6191 (pi_test_sn(pi_desc) && !pi_is_pir_empty(pi_desc));
6194 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6196 if (!kvm_vcpu_apicv_active(vcpu))
6199 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6200 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6201 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6202 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6205 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
6207 struct vcpu_vmx *vmx = to_vmx(vcpu);
6209 pi_clear_on(&vmx->pi_desc);
6210 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6213 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
6215 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6217 /* if exit due to PF check for async PF */
6218 if (is_page_fault(vmx->exit_intr_info))
6219 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
6221 /* Handle machine checks before interrupts are enabled */
6222 if (is_machine_check(vmx->exit_intr_info))
6223 kvm_machine_check();
6225 /* We need to handle NMIs before interrupts are enabled */
6226 if (is_nmi(vmx->exit_intr_info)) {
6227 kvm_before_interrupt(&vmx->vcpu);
6229 kvm_after_interrupt(&vmx->vcpu);
6233 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
6235 unsigned int vector;
6236 unsigned long entry;
6237 #ifdef CONFIG_X86_64
6243 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6244 if (WARN_ONCE(!is_external_intr(intr_info),
6245 "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6248 vector = intr_info & INTR_INFO_VECTOR_MASK;
6249 desc = (gate_desc *)host_idt_base + vector;
6250 entry = gate_offset(desc);
6252 kvm_before_interrupt(vcpu);
6255 #ifdef CONFIG_X86_64
6256 "mov %%" _ASM_SP ", %[sp]\n\t"
6257 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6262 __ASM_SIZE(push) " $%c[cs]\n\t"
6265 #ifdef CONFIG_X86_64
6270 THUNK_TARGET(entry),
6271 [ss]"i"(__KERNEL_DS),
6272 [cs]"i"(__KERNEL_CS)
6275 kvm_after_interrupt(vcpu);
6277 STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff);
6279 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu)
6281 struct vcpu_vmx *vmx = to_vmx(vcpu);
6283 if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
6284 handle_external_interrupt_irqoff(vcpu);
6285 else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)
6286 handle_exception_nmi_irqoff(vmx);
6289 static bool vmx_has_emulated_msr(int index)
6292 case MSR_IA32_SMBASE:
6294 * We cannot do SMM unless we can run the guest in big
6297 return enable_unrestricted_guest || emulate_invalid_guest_state;
6298 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6300 case MSR_AMD64_VIRT_SPEC_CTRL:
6301 /* This is AMD only. */
6308 static bool vmx_pt_supported(void)
6310 return pt_mode == PT_MODE_HOST_GUEST;
6313 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6318 bool idtv_info_valid;
6320 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6323 if (vmx->loaded_vmcs->nmi_known_unmasked)
6326 * Can't use vmx->exit_intr_info since we're not sure what
6327 * the exit reason is.
6329 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6330 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6331 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6333 * SDM 3: 27.7.1.2 (September 2008)
6334 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6335 * a guest IRET fault.
6336 * SDM 3: 23.2.2 (September 2008)
6337 * Bit 12 is undefined in any of the following cases:
6338 * If the VM exit sets the valid bit in the IDT-vectoring
6339 * information field.
6340 * If the VM exit is due to a double fault.
6342 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6343 vector != DF_VECTOR && !idtv_info_valid)
6344 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6345 GUEST_INTR_STATE_NMI);
6347 vmx->loaded_vmcs->nmi_known_unmasked =
6348 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6349 & GUEST_INTR_STATE_NMI);
6350 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6351 vmx->loaded_vmcs->vnmi_blocked_time +=
6352 ktime_to_ns(ktime_sub(ktime_get(),
6353 vmx->loaded_vmcs->entry_time));
6356 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6357 u32 idt_vectoring_info,
6358 int instr_len_field,
6359 int error_code_field)
6363 bool idtv_info_valid;
6365 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6367 vcpu->arch.nmi_injected = false;
6368 kvm_clear_exception_queue(vcpu);
6369 kvm_clear_interrupt_queue(vcpu);
6371 if (!idtv_info_valid)
6374 kvm_make_request(KVM_REQ_EVENT, vcpu);
6376 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6377 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6380 case INTR_TYPE_NMI_INTR:
6381 vcpu->arch.nmi_injected = true;
6383 * SDM 3: 27.7.1.2 (September 2008)
6384 * Clear bit "block by NMI" before VM entry if a NMI
6387 vmx_set_nmi_mask(vcpu, false);
6389 case INTR_TYPE_SOFT_EXCEPTION:
6390 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6392 case INTR_TYPE_HARD_EXCEPTION:
6393 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6394 u32 err = vmcs_read32(error_code_field);
6395 kvm_requeue_exception_e(vcpu, vector, err);
6397 kvm_requeue_exception(vcpu, vector);
6399 case INTR_TYPE_SOFT_INTR:
6400 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6402 case INTR_TYPE_EXT_INTR:
6403 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6410 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6412 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6413 VM_EXIT_INSTRUCTION_LEN,
6414 IDT_VECTORING_ERROR_CODE);
6417 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6419 __vmx_complete_interrupts(vcpu,
6420 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6421 VM_ENTRY_INSTRUCTION_LEN,
6422 VM_ENTRY_EXCEPTION_ERROR_CODE);
6424 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6427 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6430 struct perf_guest_switch_msr *msrs;
6432 msrs = perf_guest_get_msrs(&nr_msrs);
6437 for (i = 0; i < nr_msrs; i++)
6438 if (msrs[i].host == msrs[i].guest)
6439 clear_atomic_switch_msr(vmx, msrs[i].msr);
6441 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6442 msrs[i].host, false);
6445 static void atomic_switch_umwait_control_msr(struct vcpu_vmx *vmx)
6447 u32 host_umwait_control;
6449 if (!vmx_has_waitpkg(vmx))
6452 host_umwait_control = get_umwait_control_msr();
6454 if (vmx->msr_ia32_umwait_control != host_umwait_control)
6455 add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL,
6456 vmx->msr_ia32_umwait_control,
6457 host_umwait_control, false);
6459 clear_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL);
6462 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
6464 struct vcpu_vmx *vmx = to_vmx(vcpu);
6468 if (vmx->req_immediate_exit) {
6469 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6470 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6471 } else if (vmx->hv_deadline_tsc != -1) {
6473 if (vmx->hv_deadline_tsc > tscl)
6474 /* set_hv_timer ensures the delta fits in 32-bits */
6475 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6476 cpu_preemption_timer_multi);
6480 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6481 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6482 } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6483 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6484 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
6488 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
6490 if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6491 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6492 vmcs_writel(HOST_RSP, host_rsp);
6496 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched);
6498 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6500 struct vcpu_vmx *vmx = to_vmx(vcpu);
6501 unsigned long cr3, cr4;
6503 /* Record the guest's net vcpu time for enforced NMI injections. */
6504 if (unlikely(!enable_vnmi &&
6505 vmx->loaded_vmcs->soft_vnmi_blocked))
6506 vmx->loaded_vmcs->entry_time = ktime_get();
6508 /* Don't enter VMX if guest state is invalid, let the exit handler
6509 start emulation until we arrive back to a valid state */
6510 if (vmx->emulation_required)
6513 if (vmx->ple_window_dirty) {
6514 vmx->ple_window_dirty = false;
6515 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6518 if (vmx->nested.need_vmcs12_to_shadow_sync)
6519 nested_sync_vmcs12_to_shadow(vcpu);
6521 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6522 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6523 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6524 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6526 cr3 = __get_current_cr3_fast();
6527 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6528 vmcs_writel(HOST_CR3, cr3);
6529 vmx->loaded_vmcs->host_state.cr3 = cr3;
6532 cr4 = cr4_read_shadow();
6533 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6534 vmcs_writel(HOST_CR4, cr4);
6535 vmx->loaded_vmcs->host_state.cr4 = cr4;
6538 /* When single-stepping over STI and MOV SS, we must clear the
6539 * corresponding interruptibility bits in the guest state. Otherwise
6540 * vmentry fails as it then expects bit 14 (BS) in pending debug
6541 * exceptions being set, but that's not correct for the guest debugging
6543 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6544 vmx_set_interrupt_shadow(vcpu, 0);
6546 kvm_load_guest_xcr0(vcpu);
6548 if (static_cpu_has(X86_FEATURE_PKU) &&
6549 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
6550 vcpu->arch.pkru != vmx->host_pkru)
6551 __write_pkru(vcpu->arch.pkru);
6553 pt_guest_enter(vmx);
6555 atomic_switch_perf_msrs(vmx);
6556 atomic_switch_umwait_control_msr(vmx);
6558 if (enable_preemption_timer)
6559 vmx_update_hv_timer(vcpu);
6561 if (lapic_in_kernel(vcpu) &&
6562 vcpu->arch.apic->lapic_timer.timer_advance_ns)
6563 kvm_wait_lapic_expire(vcpu);
6566 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6567 * it's non-zero. Since vmentry is serialising on affected CPUs, there
6568 * is no need to worry about the conditional branch over the wrmsr
6569 * being speculatively taken.
6571 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6573 /* L1D Flush includes CPU buffer clear to mitigate MDS */
6574 if (static_branch_unlikely(&vmx_l1d_should_flush))
6575 vmx_l1d_flush(vcpu);
6576 else if (static_branch_unlikely(&mds_user_clear))
6577 mds_clear_cpu_buffers();
6579 if (vcpu->arch.cr2 != read_cr2())
6580 write_cr2(vcpu->arch.cr2);
6582 vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6583 vmx->loaded_vmcs->launched);
6585 vcpu->arch.cr2 = read_cr2();
6588 * We do not use IBRS in the kernel. If this vCPU has used the
6589 * SPEC_CTRL MSR it may have left it on; save the value and
6590 * turn it off. This is much more efficient than blindly adding
6591 * it to the atomic save/restore list. Especially as the former
6592 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6594 * For non-nested case:
6595 * If the L01 MSR bitmap does not intercept the MSR, then we need to
6599 * If the L02 MSR bitmap does not intercept the MSR, then we need to
6602 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6603 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
6605 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
6607 /* All fields are clean at this point */
6608 if (static_branch_unlikely(&enable_evmcs))
6609 current_evmcs->hv_clean_fields |=
6610 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
6612 if (static_branch_unlikely(&enable_evmcs))
6613 current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index;
6615 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6616 if (vmx->host_debugctlmsr)
6617 update_debugctlmsr(vmx->host_debugctlmsr);
6619 #ifndef CONFIG_X86_64
6621 * The sysexit path does not restore ds/es, so we must set them to
6622 * a reasonable value ourselves.
6624 * We can't defer this to vmx_prepare_switch_to_host() since that
6625 * function may be executed in interrupt context, which saves and
6626 * restore segments around it, nullifying its effect.
6628 loadsegment(ds, __USER_DS);
6629 loadsegment(es, __USER_DS);
6632 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6633 | (1 << VCPU_EXREG_RFLAGS)
6634 | (1 << VCPU_EXREG_PDPTR)
6635 | (1 << VCPU_EXREG_SEGMENTS)
6636 | (1 << VCPU_EXREG_CR3));
6637 vcpu->arch.regs_dirty = 0;
6642 * eager fpu is enabled if PKEY is supported and CR4 is switched
6643 * back on host, so it is safe to read guest PKRU from current
6646 if (static_cpu_has(X86_FEATURE_PKU) &&
6647 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
6648 vcpu->arch.pkru = rdpkru();
6649 if (vcpu->arch.pkru != vmx->host_pkru)
6650 __write_pkru(vmx->host_pkru);
6653 kvm_put_guest_xcr0(vcpu);
6655 vmx->nested.nested_run_pending = 0;
6656 vmx->idt_vectoring_info = 0;
6658 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
6659 if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
6660 kvm_machine_check();
6662 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6665 vmx->loaded_vmcs->launched = 1;
6666 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6668 vmx_recover_nmi_blocking(vmx);
6669 vmx_complete_interrupts(vmx);
6672 static struct kvm *vmx_vm_alloc(void)
6674 struct kvm_vmx *kvm_vmx = __vmalloc(sizeof(struct kvm_vmx),
6675 GFP_KERNEL_ACCOUNT | __GFP_ZERO,
6677 return &kvm_vmx->kvm;
6680 static void vmx_vm_free(struct kvm *kvm)
6682 kfree(kvm->arch.hyperv.hv_pa_pg);
6683 vfree(to_kvm_vmx(kvm));
6686 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6688 struct vcpu_vmx *vmx = to_vmx(vcpu);
6691 vmx_destroy_pml_buffer(vmx);
6692 free_vpid(vmx->vpid);
6693 nested_vmx_free_vcpu(vcpu);
6694 free_loaded_vmcs(vmx->loaded_vmcs);
6695 kfree(vmx->guest_msrs);
6696 kvm_vcpu_uninit(vcpu);
6697 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu);
6698 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
6699 kmem_cache_free(kvm_vcpu_cache, vmx);
6702 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6705 struct vcpu_vmx *vmx;
6706 unsigned long *msr_bitmap;
6709 BUILD_BUG_ON_MSG(offsetof(struct vcpu_vmx, vcpu) != 0,
6710 "struct kvm_vcpu must be at offset 0 for arch usercopy region");
6712 vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL_ACCOUNT);
6714 return ERR_PTR(-ENOMEM);
6716 vmx->vcpu.arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
6717 GFP_KERNEL_ACCOUNT);
6718 if (!vmx->vcpu.arch.user_fpu) {
6719 printk(KERN_ERR "kvm: failed to allocate kvm userspace's fpu\n");
6721 goto free_partial_vcpu;
6724 vmx->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
6725 GFP_KERNEL_ACCOUNT);
6726 if (!vmx->vcpu.arch.guest_fpu) {
6727 printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n");
6732 vmx->vpid = allocate_vpid();
6734 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6741 * If PML is turned on, failure on enabling PML just results in failure
6742 * of creating the vcpu, therefore we can simplify PML logic (by
6743 * avoiding dealing with cases, such as enabling PML partially on vcpus
6744 * for the guest, etc.
6747 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
6752 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL_ACCOUNT);
6753 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
6756 if (!vmx->guest_msrs)
6759 err = alloc_loaded_vmcs(&vmx->vmcs01);
6763 msr_bitmap = vmx->vmcs01.msr_bitmap;
6764 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
6765 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
6766 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
6767 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6768 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6769 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6770 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
6771 if (kvm_cstate_in_guest(kvm)) {
6772 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R);
6773 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6774 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6775 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6777 vmx->msr_bitmap_mode = 0;
6779 vmx->loaded_vmcs = &vmx->vmcs01;
6781 vmx_vcpu_load(&vmx->vcpu, cpu);
6782 vmx->vcpu.cpu = cpu;
6783 vmx_vcpu_setup(vmx);
6784 vmx_vcpu_put(&vmx->vcpu);
6786 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
6787 err = alloc_apic_access_page(kvm);
6792 if (enable_ept && !enable_unrestricted_guest) {
6793 err = init_rmode_identity_map(kvm);
6799 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
6801 kvm_vcpu_apicv_active(&vmx->vcpu));
6803 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
6805 vmx->nested.posted_intr_nv = -1;
6806 vmx->nested.current_vmptr = -1ull;
6808 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
6811 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
6812 * or POSTED_INTR_WAKEUP_VECTOR.
6814 vmx->pi_desc.nv = POSTED_INTR_VECTOR;
6815 vmx->pi_desc.sn = 1;
6817 vmx->ept_pointer = INVALID_PAGE;
6822 free_loaded_vmcs(vmx->loaded_vmcs);
6824 kfree(vmx->guest_msrs);
6826 vmx_destroy_pml_buffer(vmx);
6828 kvm_vcpu_uninit(&vmx->vcpu);
6830 free_vpid(vmx->vpid);
6831 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
6833 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu);
6835 kmem_cache_free(kvm_vcpu_cache, vmx);
6836 return ERR_PTR(err);
6839 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6840 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6842 static int vmx_vm_init(struct kvm *kvm)
6844 spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
6847 kvm->arch.pause_in_guest = true;
6849 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6850 switch (l1tf_mitigation) {
6851 case L1TF_MITIGATION_OFF:
6852 case L1TF_MITIGATION_FLUSH_NOWARN:
6853 /* 'I explicitly don't care' is set */
6855 case L1TF_MITIGATION_FLUSH:
6856 case L1TF_MITIGATION_FLUSH_NOSMT:
6857 case L1TF_MITIGATION_FULL:
6859 * Warn upon starting the first VM in a potentially
6860 * insecure environment.
6862 if (sched_smt_active())
6863 pr_warn_once(L1TF_MSG_SMT);
6864 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6865 pr_warn_once(L1TF_MSG_L1D);
6867 case L1TF_MITIGATION_FULL_FORCE:
6868 /* Flush is enforced */
6875 static int __init vmx_check_processor_compat(void)
6877 struct vmcs_config vmcs_conf;
6878 struct vmx_capability vmx_cap;
6880 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
6883 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept,
6885 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6886 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6887 smp_processor_id());
6893 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6898 /* For VT-d and EPT combination
6899 * 1. MMIO: always map as UC
6901 * a. VT-d without snooping control feature: can't guarantee the
6902 * result, try to trust guest.
6903 * b. VT-d with snooping control feature: snooping control feature of
6904 * VT-d engine can guarantee the cache correctness. Just set it
6905 * to WB to keep consistent with host. So the same as item 3.
6906 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6907 * consistent with host MTRR
6910 cache = MTRR_TYPE_UNCACHABLE;
6914 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
6915 ipat = VMX_EPT_IPAT_BIT;
6916 cache = MTRR_TYPE_WRBACK;
6920 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
6921 ipat = VMX_EPT_IPAT_BIT;
6922 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
6923 cache = MTRR_TYPE_WRBACK;
6925 cache = MTRR_TYPE_UNCACHABLE;
6929 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
6932 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
6935 static int vmx_get_lpage_level(void)
6937 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6938 return PT_DIRECTORY_LEVEL;
6940 /* For shadow and EPT supported 1GB page */
6941 return PT_PDPE_LEVEL;
6944 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx)
6947 * These bits in the secondary execution controls field
6948 * are dynamic, the others are mostly based on the hypervisor
6949 * architecture and the guest's CPUID. Do not touch the
6953 SECONDARY_EXEC_SHADOW_VMCS |
6954 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
6955 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6956 SECONDARY_EXEC_DESC;
6958 u32 new_ctl = vmx->secondary_exec_control;
6959 u32 cur_ctl = secondary_exec_controls_get(vmx);
6961 secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
6965 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
6966 * (indicating "allowed-1") if they are supported in the guest's CPUID.
6968 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
6970 struct vcpu_vmx *vmx = to_vmx(vcpu);
6971 struct kvm_cpuid_entry2 *entry;
6973 vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
6974 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
6976 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
6977 if (entry && (entry->_reg & (_cpuid_mask))) \
6978 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \
6981 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
6982 cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME));
6983 cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME));
6984 cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC));
6985 cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE));
6986 cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE));
6987 cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE));
6988 cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE));
6989 cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE));
6990 cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR));
6991 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
6992 cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX));
6993 cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX));
6994 cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID));
6995 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE));
6997 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6998 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE));
6999 cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP));
7000 cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP));
7001 cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU));
7002 cr4_fixed1_update(X86_CR4_UMIP, ecx, bit(X86_FEATURE_UMIP));
7004 #undef cr4_fixed1_update
7007 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
7009 struct vcpu_vmx *vmx = to_vmx(vcpu);
7011 if (kvm_mpx_supported()) {
7012 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
7015 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
7016 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
7018 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
7019 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
7024 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
7026 struct vcpu_vmx *vmx = to_vmx(vcpu);
7027 struct kvm_cpuid_entry2 *best = NULL;
7030 for (i = 0; i < PT_CPUID_LEAVES; i++) {
7031 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
7034 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
7035 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
7036 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
7037 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
7040 /* Get the number of configurable Address Ranges for filtering */
7041 vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
7042 PT_CAP_num_address_ranges);
7044 /* Initialize and clear the no dependency bits */
7045 vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
7046 RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
7049 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
7050 * will inject an #GP
7052 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
7053 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
7056 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
7057 * PSBFreq can be set
7059 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
7060 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
7061 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
7064 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
7065 * MTCFreq can be set
7067 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
7068 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
7069 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
7071 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
7072 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
7073 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
7076 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7077 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
7078 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
7080 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7081 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
7082 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
7084 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */
7085 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
7086 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
7088 /* unmask address range configure area */
7089 for (i = 0; i < vmx->pt_desc.addr_range; i++)
7090 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
7093 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7095 struct vcpu_vmx *vmx = to_vmx(vcpu);
7097 if (cpu_has_secondary_exec_ctrls()) {
7098 vmx_compute_secondary_exec_control(vmx);
7099 vmcs_set_secondary_exec_control(vmx);
7102 if (nested_vmx_allowed(vcpu))
7103 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7104 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7106 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7107 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7109 if (nested_vmx_allowed(vcpu)) {
7110 nested_vmx_cr_fixed1_bits_update(vcpu);
7111 nested_vmx_entry_exit_ctls_update(vcpu);
7114 if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7115 guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7116 update_intel_pt_cfg(vcpu);
7119 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7121 if (func == 1 && nested)
7122 entry->ecx |= bit(X86_FEATURE_VMX);
7125 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
7127 to_vmx(vcpu)->req_immediate_exit = true;
7130 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7131 struct x86_instruction_info *info,
7132 enum x86_intercept_stage stage)
7134 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7135 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7138 * RDPID causes #UD if disabled through secondary execution controls.
7139 * Because it is marked as EmulateOnUD, we need to intercept it here.
7141 if (info->intercept == x86_intercept_rdtscp &&
7142 !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
7143 ctxt->exception.vector = UD_VECTOR;
7144 ctxt->exception.error_code_valid = false;
7145 return X86EMUL_PROPAGATE_FAULT;
7148 /* TODO: check more intercepts... */
7149 return X86EMUL_CONTINUE;
7152 #ifdef CONFIG_X86_64
7153 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7154 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7155 u64 divisor, u64 *result)
7157 u64 low = a << shift, high = a >> (64 - shift);
7159 /* To avoid the overflow on divq */
7160 if (high >= divisor)
7163 /* Low hold the result, high hold rem which is discarded */
7164 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7165 "rm" (divisor), "0" (low), "1" (high));
7171 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7174 struct vcpu_vmx *vmx;
7175 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
7176 struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
7178 if (kvm_mwait_in_guest(vcpu->kvm) ||
7179 kvm_can_post_timer_interrupt(vcpu))
7184 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7185 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
7186 lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7187 ktimer->timer_advance_ns);
7189 if (delta_tsc > lapic_timer_advance_cycles)
7190 delta_tsc -= lapic_timer_advance_cycles;
7194 /* Convert to host delta tsc if tsc scaling is enabled */
7195 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
7196 delta_tsc && u64_shl_div_u64(delta_tsc,
7197 kvm_tsc_scaling_ratio_frac_bits,
7198 vcpu->arch.tsc_scaling_ratio, &delta_tsc))
7202 * If the delta tsc can't fit in the 32 bit after the multi shift,
7203 * we can't use the preemption timer.
7204 * It's possible that it fits on later vmentries, but checking
7205 * on every vmentry is costly so we just use an hrtimer.
7207 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7210 vmx->hv_deadline_tsc = tscl + delta_tsc;
7211 *expired = !delta_tsc;
7215 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7217 to_vmx(vcpu)->hv_deadline_tsc = -1;
7221 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
7223 if (!kvm_pause_in_guest(vcpu->kvm))
7224 shrink_ple_window(vcpu);
7227 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
7228 struct kvm_memory_slot *slot)
7230 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
7231 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
7234 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
7235 struct kvm_memory_slot *slot)
7237 kvm_mmu_slot_set_dirty(kvm, slot);
7240 static void vmx_flush_log_dirty(struct kvm *kvm)
7242 kvm_flush_pml_buffers(kvm);
7245 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
7247 struct vmcs12 *vmcs12;
7248 struct vcpu_vmx *vmx = to_vmx(vcpu);
7251 if (is_guest_mode(vcpu)) {
7252 WARN_ON_ONCE(vmx->nested.pml_full);
7255 * Check if PML is enabled for the nested guest.
7256 * Whether eptp bit 6 is set is already checked
7257 * as part of A/D emulation.
7259 vmcs12 = get_vmcs12(vcpu);
7260 if (!nested_cpu_has_pml(vmcs12))
7263 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
7264 vmx->nested.pml_full = true;
7268 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
7269 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index;
7271 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa,
7272 offset_in_page(dst), sizeof(gpa)))
7275 vmcs12->guest_pml_index--;
7281 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
7282 struct kvm_memory_slot *memslot,
7283 gfn_t offset, unsigned long mask)
7285 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
7288 static void __pi_post_block(struct kvm_vcpu *vcpu)
7290 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7291 struct pi_desc old, new;
7295 old.control = new.control = pi_desc->control;
7296 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
7297 "Wakeup handler not enabled while the VCPU is blocked\n");
7299 dest = cpu_physical_id(vcpu->cpu);
7301 if (x2apic_enabled())
7304 new.ndst = (dest << 8) & 0xFF00;
7306 /* set 'NV' to 'notification vector' */
7307 new.nv = POSTED_INTR_VECTOR;
7308 } while (cmpxchg64(&pi_desc->control, old.control,
7309 new.control) != old.control);
7311 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
7312 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7313 list_del(&vcpu->blocked_vcpu_list);
7314 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7315 vcpu->pre_pcpu = -1;
7320 * This routine does the following things for vCPU which is going
7321 * to be blocked if VT-d PI is enabled.
7322 * - Store the vCPU to the wakeup list, so when interrupts happen
7323 * we can find the right vCPU to wake up.
7324 * - Change the Posted-interrupt descriptor as below:
7325 * 'NDST' <-- vcpu->pre_pcpu
7326 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
7327 * - If 'ON' is set during this process, which means at least one
7328 * interrupt is posted for this vCPU, we cannot block it, in
7329 * this case, return 1, otherwise, return 0.
7332 static int pi_pre_block(struct kvm_vcpu *vcpu)
7335 struct pi_desc old, new;
7336 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7338 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
7339 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7340 !kvm_vcpu_apicv_active(vcpu))
7343 WARN_ON(irqs_disabled());
7344 local_irq_disable();
7345 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
7346 vcpu->pre_pcpu = vcpu->cpu;
7347 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7348 list_add_tail(&vcpu->blocked_vcpu_list,
7349 &per_cpu(blocked_vcpu_on_cpu,
7351 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7355 old.control = new.control = pi_desc->control;
7357 WARN((pi_desc->sn == 1),
7358 "Warning: SN field of posted-interrupts "
7359 "is set before blocking\n");
7362 * Since vCPU can be preempted during this process,
7363 * vcpu->cpu could be different with pre_pcpu, we
7364 * need to set pre_pcpu as the destination of wakeup
7365 * notification event, then we can find the right vCPU
7366 * to wakeup in wakeup handler if interrupts happen
7367 * when the vCPU is in blocked state.
7369 dest = cpu_physical_id(vcpu->pre_pcpu);
7371 if (x2apic_enabled())
7374 new.ndst = (dest << 8) & 0xFF00;
7376 /* set 'NV' to 'wakeup vector' */
7377 new.nv = POSTED_INTR_WAKEUP_VECTOR;
7378 } while (cmpxchg64(&pi_desc->control, old.control,
7379 new.control) != old.control);
7381 /* We should not block the vCPU if an interrupt is posted for it. */
7382 if (pi_test_on(pi_desc) == 1)
7383 __pi_post_block(vcpu);
7386 return (vcpu->pre_pcpu == -1);
7389 static int vmx_pre_block(struct kvm_vcpu *vcpu)
7391 if (pi_pre_block(vcpu))
7394 if (kvm_lapic_hv_timer_in_use(vcpu))
7395 kvm_lapic_switch_to_sw_timer(vcpu);
7400 static void pi_post_block(struct kvm_vcpu *vcpu)
7402 if (vcpu->pre_pcpu == -1)
7405 WARN_ON(irqs_disabled());
7406 local_irq_disable();
7407 __pi_post_block(vcpu);
7411 static void vmx_post_block(struct kvm_vcpu *vcpu)
7413 if (kvm_x86_ops->set_hv_timer)
7414 kvm_lapic_switch_to_hv_timer(vcpu);
7416 pi_post_block(vcpu);
7420 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
7423 * @host_irq: host irq of the interrupt
7424 * @guest_irq: gsi of the interrupt
7425 * @set: set or unset PI
7426 * returns 0 on success, < 0 on failure
7428 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
7429 uint32_t guest_irq, bool set)
7431 struct kvm_kernel_irq_routing_entry *e;
7432 struct kvm_irq_routing_table *irq_rt;
7433 struct kvm_lapic_irq irq;
7434 struct kvm_vcpu *vcpu;
7435 struct vcpu_data vcpu_info;
7438 if (!kvm_arch_has_assigned_device(kvm) ||
7439 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7440 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
7443 idx = srcu_read_lock(&kvm->irq_srcu);
7444 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
7445 if (guest_irq >= irq_rt->nr_rt_entries ||
7446 hlist_empty(&irq_rt->map[guest_irq])) {
7447 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
7448 guest_irq, irq_rt->nr_rt_entries);
7452 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
7453 if (e->type != KVM_IRQ_ROUTING_MSI)
7456 * VT-d PI cannot support posting multicast/broadcast
7457 * interrupts to a vCPU, we still use interrupt remapping
7458 * for these kind of interrupts.
7460 * For lowest-priority interrupts, we only support
7461 * those with single CPU as the destination, e.g. user
7462 * configures the interrupts via /proc/irq or uses
7463 * irqbalance to make the interrupts single-CPU.
7465 * We will support full lowest-priority interrupt later.
7467 * In addition, we can only inject generic interrupts using
7468 * the PI mechanism, refuse to route others through it.
7471 kvm_set_msi_irq(kvm, e, &irq);
7472 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) ||
7473 !kvm_irq_is_postable(&irq)) {
7475 * Make sure the IRTE is in remapped mode if
7476 * we don't handle it in posted mode.
7478 ret = irq_set_vcpu_affinity(host_irq, NULL);
7481 "failed to back to remapped mode, irq: %u\n",
7489 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
7490 vcpu_info.vector = irq.vector;
7492 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
7493 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
7496 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
7498 ret = irq_set_vcpu_affinity(host_irq, NULL);
7501 printk(KERN_INFO "%s: failed to update PI IRTE\n",
7509 srcu_read_unlock(&kvm->irq_srcu, idx);
7513 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7515 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7516 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7517 FEATURE_CONTROL_LMCE;
7519 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7520 ~FEATURE_CONTROL_LMCE;
7523 static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
7525 /* we need a nested vmexit to enter SMM, postpone if run is pending */
7526 if (to_vmx(vcpu)->nested.nested_run_pending)
7531 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7533 struct vcpu_vmx *vmx = to_vmx(vcpu);
7535 vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7536 if (vmx->nested.smm.guest_mode)
7537 nested_vmx_vmexit(vcpu, -1, 0, 0);
7539 vmx->nested.smm.vmxon = vmx->nested.vmxon;
7540 vmx->nested.vmxon = false;
7541 vmx_clear_hlt(vcpu);
7545 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
7547 struct vcpu_vmx *vmx = to_vmx(vcpu);
7550 if (vmx->nested.smm.vmxon) {
7551 vmx->nested.vmxon = true;
7552 vmx->nested.smm.vmxon = false;
7555 if (vmx->nested.smm.guest_mode) {
7556 ret = nested_vmx_enter_non_root_mode(vcpu, false);
7560 vmx->nested.smm.guest_mode = false;
7565 static int enable_smi_window(struct kvm_vcpu *vcpu)
7570 static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7575 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7577 return to_vmx(vcpu)->nested.vmxon;
7580 static __init int hardware_setup(void)
7582 unsigned long host_bndcfgs;
7586 rdmsrl_safe(MSR_EFER, &host_efer);
7589 host_idt_base = dt.address;
7591 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7592 kvm_define_shared_msr(i, vmx_msr_index[i]);
7594 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7597 if (boot_cpu_has(X86_FEATURE_NX))
7598 kvm_enable_efer_bits(EFER_NX);
7600 if (boot_cpu_has(X86_FEATURE_MPX)) {
7601 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7602 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7605 if (boot_cpu_has(X86_FEATURE_XSAVES))
7606 rdmsrl(MSR_IA32_XSS, host_xss);
7608 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7609 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7612 if (!cpu_has_vmx_ept() ||
7613 !cpu_has_vmx_ept_4levels() ||
7614 !cpu_has_vmx_ept_mt_wb() ||
7615 !cpu_has_vmx_invept_global())
7618 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7619 enable_ept_ad_bits = 0;
7621 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7622 enable_unrestricted_guest = 0;
7624 if (!cpu_has_vmx_flexpriority())
7625 flexpriority_enabled = 0;
7627 if (!cpu_has_virtual_nmis())
7631 * set_apic_access_page_addr() is used to reload apic access
7632 * page upon invalidation. No need to do anything if not
7633 * using the APIC_ACCESS_ADDR VMCS field.
7635 if (!flexpriority_enabled)
7636 kvm_x86_ops->set_apic_access_page_addr = NULL;
7638 if (!cpu_has_vmx_tpr_shadow())
7639 kvm_x86_ops->update_cr8_intercept = NULL;
7641 if (enable_ept && !cpu_has_vmx_ept_2m_page())
7642 kvm_disable_largepages();
7644 #if IS_ENABLED(CONFIG_HYPERV)
7645 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7647 kvm_x86_ops->tlb_remote_flush = hv_remote_flush_tlb;
7648 kvm_x86_ops->tlb_remote_flush_with_range =
7649 hv_remote_flush_tlb_with_range;
7653 if (!cpu_has_vmx_ple()) {
7656 ple_window_grow = 0;
7658 ple_window_shrink = 0;
7661 if (!cpu_has_vmx_apicv()) {
7663 kvm_x86_ops->sync_pir_to_irr = NULL;
7666 if (cpu_has_vmx_tsc_scaling()) {
7667 kvm_has_tsc_control = true;
7668 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7669 kvm_tsc_scaling_ratio_frac_bits = 48;
7672 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7680 * Only enable PML when hardware supports PML feature, and both EPT
7681 * and EPT A/D bit features are enabled -- PML depends on them to work.
7683 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7687 kvm_x86_ops->slot_enable_log_dirty = NULL;
7688 kvm_x86_ops->slot_disable_log_dirty = NULL;
7689 kvm_x86_ops->flush_log_dirty = NULL;
7690 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7693 if (!cpu_has_vmx_preemption_timer())
7694 enable_preemption_timer = false;
7696 if (enable_preemption_timer) {
7697 u64 use_timer_freq = 5000ULL * 1000 * 1000;
7700 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7701 cpu_preemption_timer_multi =
7702 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7705 use_timer_freq = (u64)tsc_khz * 1000;
7706 use_timer_freq >>= cpu_preemption_timer_multi;
7709 * KVM "disables" the preemption timer by setting it to its max
7710 * value. Don't use the timer if it might cause spurious exits
7711 * at a rate faster than 0.1 Hz (of uninterrupted guest time).
7713 if (use_timer_freq > 0xffffffffu / 10)
7714 enable_preemption_timer = false;
7717 if (!enable_preemption_timer) {
7718 kvm_x86_ops->set_hv_timer = NULL;
7719 kvm_x86_ops->cancel_hv_timer = NULL;
7720 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit;
7723 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
7725 kvm_mce_cap_supported |= MCG_LMCE_P;
7727 if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
7729 if (!enable_ept || !cpu_has_vmx_intel_pt())
7730 pt_mode = PT_MODE_SYSTEM;
7733 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
7734 vmx_capability.ept, enable_apicv);
7736 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
7741 r = alloc_kvm_area();
7743 nested_vmx_hardware_unsetup();
7747 static __exit void hardware_unsetup(void)
7750 nested_vmx_hardware_unsetup();
7755 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
7756 .cpu_has_kvm_support = cpu_has_kvm_support,
7757 .disabled_by_bios = vmx_disabled_by_bios,
7758 .hardware_setup = hardware_setup,
7759 .hardware_unsetup = hardware_unsetup,
7760 .check_processor_compatibility = vmx_check_processor_compat,
7761 .hardware_enable = hardware_enable,
7762 .hardware_disable = hardware_disable,
7763 .cpu_has_accelerated_tpr = report_flexpriority,
7764 .has_emulated_msr = vmx_has_emulated_msr,
7766 .vm_init = vmx_vm_init,
7767 .vm_alloc = vmx_vm_alloc,
7768 .vm_free = vmx_vm_free,
7770 .vcpu_create = vmx_create_vcpu,
7771 .vcpu_free = vmx_free_vcpu,
7772 .vcpu_reset = vmx_vcpu_reset,
7774 .prepare_guest_switch = vmx_prepare_switch_to_guest,
7775 .vcpu_load = vmx_vcpu_load,
7776 .vcpu_put = vmx_vcpu_put,
7778 .update_bp_intercept = update_exception_bitmap,
7779 .get_msr_feature = vmx_get_msr_feature,
7780 .get_msr = vmx_get_msr,
7781 .set_msr = vmx_set_msr,
7782 .get_segment_base = vmx_get_segment_base,
7783 .get_segment = vmx_get_segment,
7784 .set_segment = vmx_set_segment,
7785 .get_cpl = vmx_get_cpl,
7786 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7787 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7788 .decache_cr3 = vmx_decache_cr3,
7789 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7790 .set_cr0 = vmx_set_cr0,
7791 .set_cr3 = vmx_set_cr3,
7792 .set_cr4 = vmx_set_cr4,
7793 .set_efer = vmx_set_efer,
7794 .get_idt = vmx_get_idt,
7795 .set_idt = vmx_set_idt,
7796 .get_gdt = vmx_get_gdt,
7797 .set_gdt = vmx_set_gdt,
7798 .get_dr6 = vmx_get_dr6,
7799 .set_dr6 = vmx_set_dr6,
7800 .set_dr7 = vmx_set_dr7,
7801 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
7802 .cache_reg = vmx_cache_reg,
7803 .get_rflags = vmx_get_rflags,
7804 .set_rflags = vmx_set_rflags,
7806 .tlb_flush = vmx_flush_tlb,
7807 .tlb_flush_gva = vmx_flush_tlb_gva,
7809 .run = vmx_vcpu_run,
7810 .handle_exit = vmx_handle_exit,
7811 .skip_emulated_instruction = skip_emulated_instruction,
7812 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7813 .get_interrupt_shadow = vmx_get_interrupt_shadow,
7814 .patch_hypercall = vmx_patch_hypercall,
7815 .set_irq = vmx_inject_irq,
7816 .set_nmi = vmx_inject_nmi,
7817 .queue_exception = vmx_queue_exception,
7818 .cancel_injection = vmx_cancel_injection,
7819 .interrupt_allowed = vmx_interrupt_allowed,
7820 .nmi_allowed = vmx_nmi_allowed,
7821 .get_nmi_mask = vmx_get_nmi_mask,
7822 .set_nmi_mask = vmx_set_nmi_mask,
7823 .enable_nmi_window = enable_nmi_window,
7824 .enable_irq_window = enable_irq_window,
7825 .update_cr8_intercept = update_cr8_intercept,
7826 .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
7827 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
7828 .get_enable_apicv = vmx_get_enable_apicv,
7829 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
7830 .load_eoi_exitmap = vmx_load_eoi_exitmap,
7831 .apicv_post_state_restore = vmx_apicv_post_state_restore,
7832 .hwapic_irr_update = vmx_hwapic_irr_update,
7833 .hwapic_isr_update = vmx_hwapic_isr_update,
7834 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
7835 .sync_pir_to_irr = vmx_sync_pir_to_irr,
7836 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
7837 .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt,
7839 .set_tss_addr = vmx_set_tss_addr,
7840 .set_identity_map_addr = vmx_set_identity_map_addr,
7841 .get_tdp_level = get_ept_level,
7842 .get_mt_mask = vmx_get_mt_mask,
7844 .get_exit_info = vmx_get_exit_info,
7846 .get_lpage_level = vmx_get_lpage_level,
7848 .cpuid_update = vmx_cpuid_update,
7850 .rdtscp_supported = vmx_rdtscp_supported,
7851 .invpcid_supported = vmx_invpcid_supported,
7853 .set_supported_cpuid = vmx_set_supported_cpuid,
7855 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7857 .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
7858 .write_l1_tsc_offset = vmx_write_l1_tsc_offset,
7860 .set_tdp_cr3 = vmx_set_cr3,
7862 .check_intercept = vmx_check_intercept,
7863 .handle_exit_irqoff = vmx_handle_exit_irqoff,
7864 .mpx_supported = vmx_mpx_supported,
7865 .xsaves_supported = vmx_xsaves_supported,
7866 .umip_emulated = vmx_umip_emulated,
7867 .pt_supported = vmx_pt_supported,
7869 .request_immediate_exit = vmx_request_immediate_exit,
7871 .sched_in = vmx_sched_in,
7873 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
7874 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
7875 .flush_log_dirty = vmx_flush_log_dirty,
7876 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
7877 .write_log_dirty = vmx_write_pml_buffer,
7879 .pre_block = vmx_pre_block,
7880 .post_block = vmx_post_block,
7882 .pmu_ops = &intel_pmu_ops,
7884 .update_pi_irte = vmx_update_pi_irte,
7886 #ifdef CONFIG_X86_64
7887 .set_hv_timer = vmx_set_hv_timer,
7888 .cancel_hv_timer = vmx_cancel_hv_timer,
7891 .setup_mce = vmx_setup_mce,
7893 .smi_allowed = vmx_smi_allowed,
7894 .pre_enter_smm = vmx_pre_enter_smm,
7895 .pre_leave_smm = vmx_pre_leave_smm,
7896 .enable_smi_window = enable_smi_window,
7898 .check_nested_events = NULL,
7899 .get_nested_state = NULL,
7900 .set_nested_state = NULL,
7901 .get_vmcs12_pages = NULL,
7902 .nested_enable_evmcs = NULL,
7903 .nested_get_evmcs_version = NULL,
7904 .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault,
7905 .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
7908 static void vmx_cleanup_l1d_flush(void)
7910 if (vmx_l1d_flush_pages) {
7911 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
7912 vmx_l1d_flush_pages = NULL;
7914 /* Restore state so sysfs ignores VMX */
7915 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
7918 static void vmx_exit(void)
7920 #ifdef CONFIG_KEXEC_CORE
7921 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
7927 #if IS_ENABLED(CONFIG_HYPERV)
7928 if (static_branch_unlikely(&enable_evmcs)) {
7930 struct hv_vp_assist_page *vp_ap;
7932 * Reset everything to support using non-enlightened VMCS
7933 * access later (e.g. when we reload the module with
7934 * enlightened_vmcs=0)
7936 for_each_online_cpu(cpu) {
7937 vp_ap = hv_get_vp_assist_page(cpu);
7942 vp_ap->nested_control.features.directhypercall = 0;
7943 vp_ap->current_nested_vmcs = 0;
7944 vp_ap->enlighten_vmentry = 0;
7947 static_branch_disable(&enable_evmcs);
7950 vmx_cleanup_l1d_flush();
7952 module_exit(vmx_exit);
7954 static int __init vmx_init(void)
7958 #if IS_ENABLED(CONFIG_HYPERV)
7960 * Enlightened VMCS usage should be recommended and the host needs
7961 * to support eVMCS v1 or above. We can also disable eVMCS support
7962 * with module parameter.
7964 if (enlightened_vmcs &&
7965 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
7966 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
7967 KVM_EVMCS_VERSION) {
7970 /* Check that we have assist pages on all online CPUs */
7971 for_each_online_cpu(cpu) {
7972 if (!hv_get_vp_assist_page(cpu)) {
7973 enlightened_vmcs = false;
7978 if (enlightened_vmcs) {
7979 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
7980 static_branch_enable(&enable_evmcs);
7983 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
7984 vmx_x86_ops.enable_direct_tlbflush
7985 = hv_enable_direct_tlbflush;
7988 enlightened_vmcs = false;
7992 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7993 __alignof__(struct vcpu_vmx), THIS_MODULE);
7998 * Must be called after kvm_init() so enable_ept is properly set
7999 * up. Hand the parameter mitigation value in which was stored in
8000 * the pre module init parser. If no parameter was given, it will
8001 * contain 'auto' which will be turned into the default 'cond'
8004 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
8010 #ifdef CONFIG_KEXEC_CORE
8011 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8012 crash_vmclear_local_loaded_vmcss);
8014 vmx_check_vmcs12_offsets();
8018 module_init(vmx_init);