arch/x86/kvm/vmx/vmx.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Kernel-based Virtual Machine driver for Linux
   4  *
   5  * This module enables machines with Intel VT-x extensions to run virtual
   6  * machines without emulation or binary translation.
   7  *
   8  * Copyright (C) 2006 Qumranet, Inc.
   9  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  10  *
  11  * Authors:
  12  *   Avi Kivity   <avi@qumranet.com>
  13  *   Yaniv Kamay  <yaniv@qumranet.com>
  14  */
  15
  16 #include <linux/frame.h>
  17 #include <linux/highmem.h>
  18 #include <linux/hrtimer.h>
  19 #include <linux/kernel.h>
  20 #include <linux/kvm_host.h>
  21 #include <linux/module.h>
  22 #include <linux/moduleparam.h>
  23 #include <linux/mod_devicetable.h>
  24 #include <linux/mm.h>
  25 #include <linux/sched.h>
  26 #include <linux/sched/smt.h>
  27 #include <linux/slab.h>
  28 #include <linux/tboot.h>
  29 #include <linux/trace_events.h>
  30
  31 #include <asm/apic.h>
  32 #include <asm/asm.h>
  33 #include <asm/cpu.h>
  34 #include <asm/debugreg.h>
  35 #include <asm/desc.h>
  36 #include <asm/fpu/internal.h>
  37 #include <asm/io.h>
  38 #include <asm/irq_remapping.h>
  39 #include <asm/kexec.h>
  40 #include <asm/perf_event.h>
  41 #include <asm/mce.h>
  42 #include <asm/mmu_context.h>
  43 #include <asm/mshyperv.h>
  44 #include <asm/spec-ctrl.h>
  45 #include <asm/virtext.h>
  46 #include <asm/vmx.h>
  47
  48 #include "capabilities.h"
  49 #include "cpuid.h"
  50 #include "evmcs.h"
  51 #include "irq.h"
  52 #include "kvm_cache_regs.h"
  53 #include "lapic.h"
  54 #include "mmu.h"
  55 #include "nested.h"
  56 #include "ops.h"
  57 #include "pmu.h"
  58 #include "trace.h"
  59 #include "vmcs.h"
  60 #include "vmcs12.h"
  61 #include "vmx.h"
  62 #include "x86.h"
  63
  64 MODULE_AUTHOR("Qumranet");
  65 MODULE_LICENSE("GPL");
  66
  67 static const struct x86_cpu_id vmx_cpu_id[] = {
  68         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  69         {}
  70 };
  71 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  72
  73 bool __read_mostly enable_vpid = 1;
  74 module_param_named(vpid, enable_vpid, bool, 0444);
  75
  76 static bool __read_mostly enable_vnmi = 1;
  77 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
  78
  79 bool __read_mostly flexpriority_enabled = 1;
  80 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  81
  82 bool __read_mostly enable_ept = 1;
  83 module_param_named(ept, enable_ept, bool, S_IRUGO);
  84
  85 bool __read_mostly enable_unrestricted_guest = 1;
  86 module_param_named(unrestricted_guest,
  87                         enable_unrestricted_guest, bool, S_IRUGO);
  88
  89 bool __read_mostly enable_ept_ad_bits = 1;
  90 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  91
  92 static bool __read_mostly emulate_invalid_guest_state = true;
  93 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  94
  95 static bool __read_mostly fasteoi = 1;
  96 module_param(fasteoi, bool, S_IRUGO);
  97
  98 static bool __read_mostly enable_apicv = 1;
  99 module_param(enable_apicv, bool, S_IRUGO);
 100
 101 /*
 102  * If nested=1, nested virtualization is supported, i.e., guests may use
 103  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 104  * use VMX instructions.
 105  */
 106 static bool __read_mostly nested = 1;
 107 module_param(nested, bool, S_IRUGO);
 108
 109 static u64 __read_mostly host_xss;
 110
 111 bool __read_mostly enable_pml = 1;
 112 module_param_named(pml, enable_pml, bool, S_IRUGO);
 113
 114 static bool __read_mostly dump_invalid_vmcs = 0;
 115 module_param(dump_invalid_vmcs, bool, 0644);
 116
 117 #define MSR_BITMAP_MODE_X2APIC          1
 118 #define MSR_BITMAP_MODE_X2APIC_APICV    2
 119
 120 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 121
 122 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 123 static int __read_mostly cpu_preemption_timer_multi;
 124 static bool __read_mostly enable_preemption_timer = 1;
 125 #ifdef CONFIG_X86_64
 126 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 127 #endif
 128
 129 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
 130 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
 131 #define KVM_VM_CR0_ALWAYS_ON                            \
 132         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST |      \
 133          X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
 134 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 135         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 136          | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
 137
 138 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
 139 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 140 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 141
 142 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 143
 144 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
 145         RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
 146         RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
 147         RTIT_STATUS_BYTECNT))
 148
 149 #define MSR_IA32_RTIT_OUTPUT_BASE_MASK \
 150         (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f)
 151
 152 /*
 153  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 154  * ple_gap:    upper bound on the amount of time between two successive
 155  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 156  *             According to test, this time is usually smaller than 128 cycles.
 157  * ple_window: upper bound on the amount of time a guest is allowed to execute
 158  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 159  *             less than 2^12 cycles
 160  * Time is measured based on a counter that runs at the same rate as the TSC,
 161  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 162  */
 163 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
 164 module_param(ple_gap, uint, 0444);
 165
 166 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 167 module_param(ple_window, uint, 0444);
 168
 169 /* Default doubles per-vcpu window every exit. */
 170 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 171 module_param(ple_window_grow, uint, 0444);
 172
 173 /* Default resets per-vcpu window every exit to ple_window. */
 174 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 175 module_param(ple_window_shrink, uint, 0444);
 176
 177 /* Default is to compute the maximum so we can never overflow. */
 178 static unsigned int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 179 module_param(ple_window_max, uint, 0444);
 180
 181 /* Default is SYSTEM mode, 1 for host-guest mode */
 182 int __read_mostly pt_mode = PT_MODE_SYSTEM;
 183 module_param(pt_mode, int, S_IRUGO);
 184
 185 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
 186 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
 187 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
 188
 189 /* Storage for pre module init parameter parsing */
 190 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
 191
 192 static const struct {
 193         const char *option;
 194         bool for_parse;
 195 } vmentry_l1d_param[] = {
 196         [VMENTER_L1D_FLUSH_AUTO]         = {"auto", true},
 197         [VMENTER_L1D_FLUSH_NEVER]        = {"never", true},
 198         [VMENTER_L1D_FLUSH_COND]         = {"cond", true},
 199         [VMENTER_L1D_FLUSH_ALWAYS]       = {"always", true},
 200         [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
 201         [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
 202 };
 203
 204 #define L1D_CACHE_ORDER 4
 205 static void *vmx_l1d_flush_pages;
 206
 207 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
 208 {
 209         struct page *page;
 210         unsigned int i;
 211
 212         if (!boot_cpu_has_bug(X86_BUG_L1TF)) {
 213                 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
 214                 return 0;
 215         }
 216
 217         if (!enable_ept) {
 218                 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
 219                 return 0;
 220         }
 221
 222         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
 223                 u64 msr;
 224
 225                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
 226                 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
 227                         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
 228                         return 0;
 229                 }
 230         }
 231
 232         /* If set to auto use the default l1tf mitigation method */
 233         if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
 234                 switch (l1tf_mitigation) {
 235                 case L1TF_MITIGATION_OFF:
 236                         l1tf = VMENTER_L1D_FLUSH_NEVER;
 237                         break;
 238                 case L1TF_MITIGATION_FLUSH_NOWARN:
 239                 case L1TF_MITIGATION_FLUSH:
 240                 case L1TF_MITIGATION_FLUSH_NOSMT:
 241                         l1tf = VMENTER_L1D_FLUSH_COND;
 242                         break;
 243                 case L1TF_MITIGATION_FULL:
 244                 case L1TF_MITIGATION_FULL_FORCE:
 245                         l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 246                         break;
 247                 }
 248         } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
 249                 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 250         }
 251
 252         if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
 253             !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
 254                 /*
 255                  * This allocation for vmx_l1d_flush_pages is not tied to a VM
 256                  * lifetime and so should not be charged to a memcg.
 257                  */
 258                 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
 259                 if (!page)
 260                         return -ENOMEM;
 261                 vmx_l1d_flush_pages = page_address(page);
 262
 263                 /*
 264                  * Initialize each page with a different pattern in
 265                  * order to protect against KSM in the nested
 266                  * virtualization case.
 267                  */
 268                 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
 269                         memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
 270                                PAGE_SIZE);
 271                 }
 272         }
 273
 274         l1tf_vmx_mitigation = l1tf;
 275
 276         if (l1tf != VMENTER_L1D_FLUSH_NEVER)
 277                 static_branch_enable(&vmx_l1d_should_flush);
 278         else
 279                 static_branch_disable(&vmx_l1d_should_flush);
 280
 281         if (l1tf == VMENTER_L1D_FLUSH_COND)
 282                 static_branch_enable(&vmx_l1d_flush_cond);
 283         else
 284                 static_branch_disable(&vmx_l1d_flush_cond);
 285         return 0;
 286 }
 287
 288 static int vmentry_l1d_flush_parse(const char *s)
 289 {
 290         unsigned int i;
 291
 292         if (s) {
 293                 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
 294                         if (vmentry_l1d_param[i].for_parse &&
 295                             sysfs_streq(s, vmentry_l1d_param[i].option))
 296                                 return i;
 297                 }
 298         }
 299         return -EINVAL;
 300 }
 301
 302 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
 303 {
 304         int l1tf, ret;
 305
 306         l1tf = vmentry_l1d_flush_parse(s);
 307         if (l1tf < 0)
 308                 return l1tf;
 309
 310         if (!boot_cpu_has(X86_BUG_L1TF))
 311                 return 0;
 312
 313         /*
 314          * Has vmx_init() run already? If not then this is the pre init
 315          * parameter parsing. In that case just store the value and let
 316          * vmx_init() do the proper setup after enable_ept has been
 317          * established.
 318          */
 319         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
 320                 vmentry_l1d_flush_param = l1tf;
 321                 return 0;
 322         }
 323
 324         mutex_lock(&vmx_l1d_flush_mutex);
 325         ret = vmx_setup_l1d_flush(l1tf);
 326         mutex_unlock(&vmx_l1d_flush_mutex);
 327         return ret;
 328 }
 329
 330 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
 331 {
 332         if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
 333                 return sprintf(s, "???\n");
 334
 335         return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
 336 }
 337
 338 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
 339         .set = vmentry_l1d_flush_set,
 340         .get = vmentry_l1d_flush_get,
 341 };
 342 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
 343
 344 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 345 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 346 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
 347                                                           u32 msr, int type);
 348
 349 void vmx_vmexit(void);
 350
 351 #define vmx_insn_failed(fmt...)         \
 352 do {                                    \
 353         WARN_ONCE(1, fmt);              \
 354         pr_warn_ratelimited(fmt);       \
 355 } while (0)
 356
 357 asmlinkage void vmread_error(unsigned long field, bool fault)
 358 {
 359         if (fault)
 360                 kvm_spurious_fault();
 361         else
 362                 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field);
 363 }
 364
 365 noinline void vmwrite_error(unsigned long field, unsigned long value)
 366 {
 367         vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n",
 368                         field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 369 }
 370
 371 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr)
 372 {
 373         vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr);
 374 }
 375
 376 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr)
 377 {
 378         vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr);
 379 }
 380
 381 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva)
 382 {
 383         vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n",
 384                         ext, vpid, gva);
 385 }
 386
 387 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa)
 388 {
 389         vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n",
 390                         ext, eptp, gpa);
 391 }
 392
 393 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 394 DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 395 /*
 396  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 397  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 398  */
 399 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 400
 401 /*
 402  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 403  * can find which vCPU should be waken up.
 404  */
 405 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 406 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 407
 408 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 409 static DEFINE_SPINLOCK(vmx_vpid_lock);
 410
 411 struct vmcs_config vmcs_config;
 412 struct vmx_capability vmx_capability;
 413
 414 #define VMX_SEGMENT_FIELD(seg)                                  \
 415         [VCPU_SREG_##seg] = {                                   \
 416                 .selector = GUEST_##seg##_SELECTOR,             \
 417                 .base = GUEST_##seg##_BASE,                     \
 418                 .limit = GUEST_##seg##_LIMIT,                   \
 419                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 420         }
 421
 422 static const struct kvm_vmx_segment_field {
 423         unsigned selector;
 424         unsigned base;
 425         unsigned limit;
 426         unsigned ar_bytes;
 427 } kvm_vmx_segment_fields[] = {
 428         VMX_SEGMENT_FIELD(CS),
 429         VMX_SEGMENT_FIELD(DS),
 430         VMX_SEGMENT_FIELD(ES),
 431         VMX_SEGMENT_FIELD(FS),
 432         VMX_SEGMENT_FIELD(GS),
 433         VMX_SEGMENT_FIELD(SS),
 434         VMX_SEGMENT_FIELD(TR),
 435         VMX_SEGMENT_FIELD(LDTR),
 436 };
 437
 438 u64 host_efer;
 439 static unsigned long host_idt_base;
 440
 441 /*
 442  * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
 443  * will emulate SYSCALL in legacy mode if the vendor string in guest
 444  * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
 445  * support this emulation, IA32_STAR must always be included in
 446  * vmx_msr_index[], even in i386 builds.
 447  */
 448 const u32 vmx_msr_index[] = {
 449 #ifdef CONFIG_X86_64
 450         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 451 #endif
 452         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 453 };
 454
 455 #if IS_ENABLED(CONFIG_HYPERV)
 456 static bool __read_mostly enlightened_vmcs = true;
 457 module_param(enlightened_vmcs, bool, 0444);
 458
 459 /* check_ept_pointer() should be under protection of ept_pointer_lock. */
 460 static void check_ept_pointer_match(struct kvm *kvm)
 461 {
 462         struct kvm_vcpu *vcpu;
 463         u64 tmp_eptp = INVALID_PAGE;
 464         int i;
 465
 466         kvm_for_each_vcpu(i, vcpu, kvm) {
 467                 if (!VALID_PAGE(tmp_eptp)) {
 468                         tmp_eptp = to_vmx(vcpu)->ept_pointer;
 469                 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
 470                         to_kvm_vmx(kvm)->ept_pointers_match
 471                                 = EPT_POINTERS_MISMATCH;
 472                         return;
 473                 }
 474         }
 475
 476         to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
 477 }
 478
 479 static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush,
 480                 void *data)
 481 {
 482         struct kvm_tlb_range *range = data;
 483
 484         return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn,
 485                         range->pages);
 486 }
 487
 488 static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm,
 489                 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range)
 490 {
 491         u64 ept_pointer = to_vmx(vcpu)->ept_pointer;
 492
 493         /*
 494          * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address
 495          * of the base of EPT PML4 table, strip off EPT configuration
 496          * information.
 497          */
 498         if (range)
 499                 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK,
 500                                 kvm_fill_hv_flush_list_func, (void *)range);
 501         else
 502                 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK);
 503 }
 504
 505 static int hv_remote_flush_tlb_with_range(struct kvm *kvm,
 506                 struct kvm_tlb_range *range)
 507 {
 508         struct kvm_vcpu *vcpu;
 509         int ret = 0, i;
 510
 511         spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
 512
 513         if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
 514                 check_ept_pointer_match(kvm);
 515
 516         if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
 517                 kvm_for_each_vcpu(i, vcpu, kvm) {
 518                         /* If ept_pointer is invalid pointer, bypass flush request. */
 519                         if (VALID_PAGE(to_vmx(vcpu)->ept_pointer))
 520                                 ret |= __hv_remote_flush_tlb_with_range(
 521                                         kvm, vcpu, range);
 522                 }
 523         } else {
 524                 ret = __hv_remote_flush_tlb_with_range(kvm,
 525                                 kvm_get_vcpu(kvm, 0), range);
 526         }
 527
 528         spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
 529         return ret;
 530 }
 531 static int hv_remote_flush_tlb(struct kvm *kvm)
 532 {
 533         return hv_remote_flush_tlb_with_range(kvm, NULL);
 534 }
 535
 536 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
 537 {
 538         struct hv_enlightened_vmcs *evmcs;
 539         struct hv_partition_assist_pg **p_hv_pa_pg =
 540                         &vcpu->kvm->arch.hyperv.hv_pa_pg;
 541         /*
 542          * Synthetic VM-Exit is not enabled in current code and so All
 543          * evmcs in singe VM shares same assist page.
 544          */
 545         if (!*p_hv_pa_pg)
 546                 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL);
 547
 548         if (!*p_hv_pa_pg)
 549                 return -ENOMEM;
 550
 551         evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
 552
 553         evmcs->partition_assist_page =
 554                 __pa(*p_hv_pa_pg);
 555         evmcs->hv_vm_id = (unsigned long)vcpu->kvm;
 556         evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
 557
 558         return 0;
 559 }
 560
 561 #endif /* IS_ENABLED(CONFIG_HYPERV) */
 562
 563 /*
 564  * Comment's format: document - errata name - stepping - processor name.
 565  * Refer from
 566  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
 567  */
 568 static u32 vmx_preemption_cpu_tfms[] = {
 569 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
 570 0x000206E6,
 571 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
 572 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
 573 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
 574 0x00020652,
 575 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
 576 0x00020655,
 577 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
 578 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
 579 /*
 580  * 320767.pdf - AAP86  - B1 -
 581  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
 582  */
 583 0x000106E5,
 584 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
 585 0x000106A0,
 586 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
 587 0x000106A1,
 588 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
 589 0x000106A4,
 590  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
 591  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
 592  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
 593 0x000106A5,
 594  /* Xeon E3-1220 V2 */
 595 0x000306A8,
 596 };
 597
 598 static inline bool cpu_has_broken_vmx_preemption_timer(void)
 599 {
 600         u32 eax = cpuid_eax(0x00000001), i;
 601
 602         /* Clear the reserved bits */
 603         eax &= ~(0x3U << 14 | 0xfU << 28);
 604         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
 605                 if (eax == vmx_preemption_cpu_tfms[i])
 606                         return true;
 607
 608         return false;
 609 }
 610
 611 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
 612 {
 613         return flexpriority_enabled && lapic_in_kernel(vcpu);
 614 }
 615
 616 static inline bool report_flexpriority(void)
 617 {
 618         return flexpriority_enabled;
 619 }
 620
 621 static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 622 {
 623         int i;
 624
 625         for (i = 0; i < vmx->nmsrs; ++i)
 626                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 627                         return i;
 628         return -1;
 629 }
 630
 631 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 632 {
 633         int i;
 634
 635         i = __find_msr_index(vmx, msr);
 636         if (i >= 0)
 637                 return &vmx->guest_msrs[i];
 638         return NULL;
 639 }
 640
 641 void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
 642 {
 643         vmcs_clear(loaded_vmcs->vmcs);
 644         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
 645                 vmcs_clear(loaded_vmcs->shadow_vmcs);
 646         loaded_vmcs->cpu = -1;
 647         loaded_vmcs->launched = 0;
 648 }
 649
 650 #ifdef CONFIG_KEXEC_CORE
 651 /*
 652  * This bitmap is used to indicate whether the vmclear
 653  * operation is enabled on all cpus. All disabled by
 654  * default.
 655  */
 656 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
 657
 658 static inline void crash_enable_local_vmclear(int cpu)
 659 {
 660         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
 661 }
 662
 663 static inline void crash_disable_local_vmclear(int cpu)
 664 {
 665         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
 666 }
 667
 668 static inline int crash_local_vmclear_enabled(int cpu)
 669 {
 670         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
 671 }
 672
 673 static void crash_vmclear_local_loaded_vmcss(void)
 674 {
 675         int cpu = raw_smp_processor_id();
 676         struct loaded_vmcs *v;
 677
 678         if (!crash_local_vmclear_enabled(cpu))
 679                 return;
 680
 681         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
 682                             loaded_vmcss_on_cpu_link)
 683                 vmcs_clear(v->vmcs);
 684 }
 685 #else
 686 static inline void crash_enable_local_vmclear(int cpu) { }
 687 static inline void crash_disable_local_vmclear(int cpu) { }
 688 #endif /* CONFIG_KEXEC_CORE */
 689
 690 static void __loaded_vmcs_clear(void *arg)
 691 {
 692         struct loaded_vmcs *loaded_vmcs = arg;
 693         int cpu = raw_smp_processor_id();
 694
 695         if (loaded_vmcs->cpu != cpu)
 696                 return; /* vcpu migration can race with cpu offline */
 697         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
 698                 per_cpu(current_vmcs, cpu) = NULL;
 699         crash_disable_local_vmclear(cpu);
 700         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
 701
 702         /*
 703          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
 704          * is before setting loaded_vmcs->vcpu to -1 which is done in
 705          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
 706          * then adds the vmcs into percpu list before it is deleted.
 707          */
 708         smp_wmb();
 709
 710         loaded_vmcs_init(loaded_vmcs);
 711         crash_enable_local_vmclear(cpu);
 712 }
 713
 714 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
 715 {
 716         int cpu = loaded_vmcs->cpu;
 717
 718         if (cpu != -1)
 719                 smp_call_function_single(cpu,
 720                          __loaded_vmcs_clear, loaded_vmcs, 1);
 721 }
 722
 723 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
 724                                        unsigned field)
 725 {
 726         bool ret;
 727         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
 728
 729         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
 730                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
 731                 vmx->segment_cache.bitmask = 0;
 732         }
 733         ret = vmx->segment_cache.bitmask & mask;
 734         vmx->segment_cache.bitmask |= mask;
 735         return ret;
 736 }
 737
 738 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
 739 {
 740         u16 *p = &vmx->segment_cache.seg[seg].selector;
 741
 742         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
 743                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
 744         return *p;
 745 }
 746
 747 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
 748 {
 749         ulong *p = &vmx->segment_cache.seg[seg].base;
 750
 751         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
 752                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
 753         return *p;
 754 }
 755
 756 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
 757 {
 758         u32 *p = &vmx->segment_cache.seg[seg].limit;
 759
 760         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
 761                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
 762         return *p;
 763 }
 764
 765 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
 766 {
 767         u32 *p = &vmx->segment_cache.seg[seg].ar;
 768
 769         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
 770                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
 771         return *p;
 772 }
 773
 774 void update_exception_bitmap(struct kvm_vcpu *vcpu)
 775 {
 776         u32 eb;
 777
 778         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
 779              (1u << DB_VECTOR) | (1u << AC_VECTOR);
 780         /*
 781          * Guest access to VMware backdoor ports could legitimately
 782          * trigger #GP because of TSS I/O permission bitmap.
 783          * We intercept those #GP and allow access to them anyway
 784          * as VMware does.
 785          */
 786         if (enable_vmware_backdoor)
 787                 eb |= (1u << GP_VECTOR);
 788         if ((vcpu->guest_debug &
 789              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
 790             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
 791                 eb |= 1u << BP_VECTOR;
 792         if (to_vmx(vcpu)->rmode.vm86_active)
 793                 eb = ~0;
 794         if (enable_ept)
 795                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 796
 797         /* When we are running a nested L2 guest and L1 specified for it a
 798          * certain exception bitmap, we must trap the same exceptions and pass
 799          * them to L1. When running L2, we will only handle the exceptions
 800          * specified above if L1 did not want them.
 801          */
 802         if (is_guest_mode(vcpu))
 803                 eb |= get_vmcs12(vcpu)->exception_bitmap;
 804
 805         vmcs_write32(EXCEPTION_BITMAP, eb);
 806 }
 807
 808 /*
 809  * Check if MSR is intercepted for currently loaded MSR bitmap.
 810  */
 811 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
 812 {
 813         unsigned long *msr_bitmap;
 814         int f = sizeof(unsigned long);
 815
 816         if (!cpu_has_vmx_msr_bitmap())
 817                 return true;
 818
 819         msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
 820
 821         if (msr <= 0x1fff) {
 822                 return !!test_bit(msr, msr_bitmap + 0x800 / f);
 823         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
 824                 msr &= 0x1fff;
 825                 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
 826         }
 827
 828         return true;
 829 }
 830
 831 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
 832                 unsigned long entry, unsigned long exit)
 833 {
 834         vm_entry_controls_clearbit(vmx, entry);
 835         vm_exit_controls_clearbit(vmx, exit);
 836 }
 837
 838 static int find_msr(struct vmx_msrs *m, unsigned int msr)
 839 {
 840         unsigned int i;
 841
 842         for (i = 0; i < m->nr; ++i) {
 843                 if (m->val[i].index == msr)
 844                         return i;
 845         }
 846         return -ENOENT;
 847 }
 848
 849 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
 850 {
 851         int i;
 852         struct msr_autoload *m = &vmx->msr_autoload;
 853
 854         switch (msr) {
 855         case MSR_EFER:
 856                 if (cpu_has_load_ia32_efer()) {
 857                         clear_atomic_switch_msr_special(vmx,
 858                                         VM_ENTRY_LOAD_IA32_EFER,
 859                                         VM_EXIT_LOAD_IA32_EFER);
 860                         return;
 861                 }
 862                 break;
 863         case MSR_CORE_PERF_GLOBAL_CTRL:
 864                 if (cpu_has_load_perf_global_ctrl()) {
 865                         clear_atomic_switch_msr_special(vmx,
 866                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
 867                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
 868                         return;
 869                 }
 870                 break;
 871         }
 872         i = find_msr(&m->guest, msr);
 873         if (i < 0)
 874                 goto skip_guest;
 875         --m->guest.nr;
 876         m->guest.val[i] = m->guest.val[m->guest.nr];
 877         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
 878
 879 skip_guest:
 880         i = find_msr(&m->host, msr);
 881         if (i < 0)
 882                 return;
 883
 884         --m->host.nr;
 885         m->host.val[i] = m->host.val[m->host.nr];
 886         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
 887 }
 888
 889 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
 890                 unsigned long entry, unsigned long exit,
 891                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
 892                 u64 guest_val, u64 host_val)
 893 {
 894         vmcs_write64(guest_val_vmcs, guest_val);
 895         if (host_val_vmcs != HOST_IA32_EFER)
 896                 vmcs_write64(host_val_vmcs, host_val);
 897         vm_entry_controls_setbit(vmx, entry);
 898         vm_exit_controls_setbit(vmx, exit);
 899 }
 900
 901 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
 902                                   u64 guest_val, u64 host_val, bool entry_only)
 903 {
 904         int i, j = 0;
 905         struct msr_autoload *m = &vmx->msr_autoload;
 906
 907         switch (msr) {
 908         case MSR_EFER:
 909                 if (cpu_has_load_ia32_efer()) {
 910                         add_atomic_switch_msr_special(vmx,
 911                                         VM_ENTRY_LOAD_IA32_EFER,
 912                                         VM_EXIT_LOAD_IA32_EFER,
 913                                         GUEST_IA32_EFER,
 914                                         HOST_IA32_EFER,
 915                                         guest_val, host_val);
 916                         return;
 917                 }
 918                 break;
 919         case MSR_CORE_PERF_GLOBAL_CTRL:
 920                 if (cpu_has_load_perf_global_ctrl()) {
 921                         add_atomic_switch_msr_special(vmx,
 922                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
 923                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
 924                                         GUEST_IA32_PERF_GLOBAL_CTRL,
 925                                         HOST_IA32_PERF_GLOBAL_CTRL,
 926                                         guest_val, host_val);
 927                         return;
 928                 }
 929                 break;
 930         case MSR_IA32_PEBS_ENABLE:
 931                 /* PEBS needs a quiescent period after being disabled (to write
 932                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
 933                  * provide that period, so a CPU could write host's record into
 934                  * guest's memory.
 935                  */
 936                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
 937         }
 938
 939         i = find_msr(&m->guest, msr);
 940         if (!entry_only)
 941                 j = find_msr(&m->host, msr);
 942
 943         if ((i < 0 && m->guest.nr == NR_AUTOLOAD_MSRS) ||
 944                 (j < 0 &&  m->host.nr == NR_AUTOLOAD_MSRS)) {
 945                 printk_once(KERN_WARNING "Not enough msr switch entries. "
 946                                 "Can't add msr %x\n", msr);
 947                 return;
 948         }
 949         if (i < 0) {
 950                 i = m->guest.nr++;
 951                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
 952         }
 953         m->guest.val[i].index = msr;
 954         m->guest.val[i].value = guest_val;
 955
 956         if (entry_only)
 957                 return;
 958
 959         if (j < 0) {
 960                 j = m->host.nr++;
 961                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
 962         }
 963         m->host.val[j].index = msr;
 964         m->host.val[j].value = host_val;
 965 }
 966
 967 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
 968 {
 969         u64 guest_efer = vmx->vcpu.arch.efer;
 970         u64 ignore_bits = 0;
 971
 972         /* Shadow paging assumes NX to be available.  */
 973         if (!enable_ept)
 974                 guest_efer |= EFER_NX;
 975
 976         /*
 977          * LMA and LME handled by hardware; SCE meaningless outside long mode.
 978          */
 979         ignore_bits |= EFER_SCE;
 980 #ifdef CONFIG_X86_64
 981         ignore_bits |= EFER_LMA | EFER_LME;
 982         /* SCE is meaningful only in long mode on Intel */
 983         if (guest_efer & EFER_LMA)
 984                 ignore_bits &= ~(u64)EFER_SCE;
 985 #endif
 986
 987         /*
 988          * On EPT, we can't emulate NX, so we must switch EFER atomically.
 989          * On CPUs that support "load IA32_EFER", always switch EFER
 990          * atomically, since it's faster than switching it manually.
 991          */
 992         if (cpu_has_load_ia32_efer() ||
 993             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
 994                 if (!(guest_efer & EFER_LMA))
 995                         guest_efer &= ~EFER_LME;
 996                 if (guest_efer != host_efer)
 997                         add_atomic_switch_msr(vmx, MSR_EFER,
 998                                               guest_efer, host_efer, false);
 999                 else
1000                         clear_atomic_switch_msr(vmx, MSR_EFER);
1001                 return false;
1002         } else {
1003                 clear_atomic_switch_msr(vmx, MSR_EFER);
1004
1005                 guest_efer &= ~ignore_bits;
1006                 guest_efer |= host_efer & ignore_bits;
1007
1008                 vmx->guest_msrs[efer_offset].data = guest_efer;
1009                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1010
1011                 return true;
1012         }
1013 }
1014
1015 #ifdef CONFIG_X86_32
1016 /*
1017  * On 32-bit kernels, VM exits still load the FS and GS bases from the
1018  * VMCS rather than the segment table.  KVM uses this helper to figure
1019  * out the current bases to poke them into the VMCS before entry.
1020  */
1021 static unsigned long segment_base(u16 selector)
1022 {
1023         struct desc_struct *table;
1024         unsigned long v;
1025
1026         if (!(selector & ~SEGMENT_RPL_MASK))
1027                 return 0;
1028
1029         table = get_current_gdt_ro();
1030
1031         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
1032                 u16 ldt_selector = kvm_read_ldt();
1033
1034                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
1035                         return 0;
1036
1037                 table = (struct desc_struct *)segment_base(ldt_selector);
1038         }
1039         v = get_desc_base(&table[selector >> 3]);
1040         return v;
1041 }
1042 #endif
1043
1044 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
1045 {
1046         u32 i;
1047
1048         wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1049         wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1050         wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1051         wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1052         for (i = 0; i < addr_range; i++) {
1053                 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1054                 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1055         }
1056 }
1057
1058 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
1059 {
1060         u32 i;
1061
1062         rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1063         rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1064         rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1065         rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1066         for (i = 0; i < addr_range; i++) {
1067                 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1068                 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1069         }
1070 }
1071
1072 static void pt_guest_enter(struct vcpu_vmx *vmx)
1073 {
1074         if (pt_mode == PT_MODE_SYSTEM)
1075                 return;
1076
1077         /*
1078          * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1079          * Save host state before VM entry.
1080          */
1081         rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1082         if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1083                 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1084                 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1085                 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1086         }
1087 }
1088
1089 static void pt_guest_exit(struct vcpu_vmx *vmx)
1090 {
1091         if (pt_mode == PT_MODE_SYSTEM)
1092                 return;
1093
1094         if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1095                 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1096                 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1097         }
1098
1099         /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1100         wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1101 }
1102
1103 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1104                         unsigned long fs_base, unsigned long gs_base)
1105 {
1106         if (unlikely(fs_sel != host->fs_sel)) {
1107                 if (!(fs_sel & 7))
1108                         vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1109                 else
1110                         vmcs_write16(HOST_FS_SELECTOR, 0);
1111                 host->fs_sel = fs_sel;
1112         }
1113         if (unlikely(gs_sel != host->gs_sel)) {
1114                 if (!(gs_sel & 7))
1115                         vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1116                 else
1117                         vmcs_write16(HOST_GS_SELECTOR, 0);
1118                 host->gs_sel = gs_sel;
1119         }
1120         if (unlikely(fs_base != host->fs_base)) {
1121                 vmcs_writel(HOST_FS_BASE, fs_base);
1122                 host->fs_base = fs_base;
1123         }
1124         if (unlikely(gs_base != host->gs_base)) {
1125                 vmcs_writel(HOST_GS_BASE, gs_base);
1126                 host->gs_base = gs_base;
1127         }
1128 }
1129
1130 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1131 {
1132         struct vcpu_vmx *vmx = to_vmx(vcpu);
1133         struct vmcs_host_state *host_state;
1134 #ifdef CONFIG_X86_64
1135         int cpu = raw_smp_processor_id();
1136 #endif
1137         unsigned long fs_base, gs_base;
1138         u16 fs_sel, gs_sel;
1139         int i;
1140
1141         vmx->req_immediate_exit = false;
1142
1143         /*
1144          * Note that guest MSRs to be saved/restored can also be changed
1145          * when guest state is loaded. This happens when guest transitions
1146          * to/from long-mode by setting MSR_EFER.LMA.
1147          */
1148         if (!vmx->guest_msrs_ready) {
1149                 vmx->guest_msrs_ready = true;
1150                 for (i = 0; i < vmx->save_nmsrs; ++i)
1151                         kvm_set_shared_msr(vmx->guest_msrs[i].index,
1152                                            vmx->guest_msrs[i].data,
1153                                            vmx->guest_msrs[i].mask);
1154
1155         }
1156         if (vmx->guest_state_loaded)
1157                 return;
1158
1159         host_state = &vmx->loaded_vmcs->host_state;
1160
1161         /*
1162          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1163          * allow segment selectors with cpl > 0 or ti == 1.
1164          */
1165         host_state->ldt_sel = kvm_read_ldt();
1166
1167 #ifdef CONFIG_X86_64
1168         savesegment(ds, host_state->ds_sel);
1169         savesegment(es, host_state->es_sel);
1170
1171         gs_base = cpu_kernelmode_gs_base(cpu);
1172         if (likely(is_64bit_mm(current->mm))) {
1173                 save_fsgs_for_kvm();
1174                 fs_sel = current->thread.fsindex;
1175                 gs_sel = current->thread.gsindex;
1176                 fs_base = current->thread.fsbase;
1177                 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
1178         } else {
1179                 savesegment(fs, fs_sel);
1180                 savesegment(gs, gs_sel);
1181                 fs_base = read_msr(MSR_FS_BASE);
1182                 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
1183         }
1184
1185         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1186 #else
1187         savesegment(fs, fs_sel);
1188         savesegment(gs, gs_sel);
1189         fs_base = segment_base(fs_sel);
1190         gs_base = segment_base(gs_sel);
1191 #endif
1192
1193         vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
1194         vmx->guest_state_loaded = true;
1195 }
1196
1197 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
1198 {
1199         struct vmcs_host_state *host_state;
1200
1201         if (!vmx->guest_state_loaded)
1202                 return;
1203
1204         host_state = &vmx->loaded_vmcs->host_state;
1205
1206         ++vmx->vcpu.stat.host_state_reload;
1207
1208 #ifdef CONFIG_X86_64
1209         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1210 #endif
1211         if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1212                 kvm_load_ldt(host_state->ldt_sel);
1213 #ifdef CONFIG_X86_64
1214                 load_gs_index(host_state->gs_sel);
1215 #else
1216                 loadsegment(gs, host_state->gs_sel);
1217 #endif
1218         }
1219         if (host_state->fs_sel & 7)
1220                 loadsegment(fs, host_state->fs_sel);
1221 #ifdef CONFIG_X86_64
1222         if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1223                 loadsegment(ds, host_state->ds_sel);
1224                 loadsegment(es, host_state->es_sel);
1225         }
1226 #endif
1227         invalidate_tss_limit();
1228 #ifdef CONFIG_X86_64
1229         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1230 #endif
1231         load_fixmap_gdt(raw_smp_processor_id());
1232         vmx->guest_state_loaded = false;
1233         vmx->guest_msrs_ready = false;
1234 }
1235
1236 #ifdef CONFIG_X86_64
1237 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
1238 {
1239         preempt_disable();
1240         if (vmx->guest_state_loaded)
1241                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1242         preempt_enable();
1243         return vmx->msr_guest_kernel_gs_base;
1244 }
1245
1246 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1247 {
1248         preempt_disable();
1249         if (vmx->guest_state_loaded)
1250                 wrmsrl(MSR_KERNEL_GS_BASE, data);
1251         preempt_enable();
1252         vmx->msr_guest_kernel_gs_base = data;
1253 }
1254 #endif
1255
1256 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1257 {
1258         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1259         struct pi_desc old, new;
1260         unsigned int dest;
1261
1262         /*
1263          * In case of hot-plug or hot-unplug, we may have to undo
1264          * vmx_vcpu_pi_put even if there is no assigned device.  And we
1265          * always keep PI.NDST up to date for simplicity: it makes the
1266          * code easier, and CPU migration is not a fast path.
1267          */
1268         if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
1269                 return;
1270
1271         /*
1272          * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
1273          * PI.NDST: pi_post_block is the one expected to change PID.NDST and the
1274          * wakeup handler expects the vCPU to be on the blocked_vcpu_list that
1275          * matches PI.NDST. Otherwise, a vcpu may not be able to be woken up
1276          * correctly.
1277          */
1278         if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || vcpu->cpu == cpu) {
1279                 pi_clear_sn(pi_desc);
1280                 goto after_clear_sn;
1281         }
1282
1283         /* The full case.  */
1284         do {
1285                 old.control = new.control = pi_desc->control;
1286
1287                 dest = cpu_physical_id(cpu);
1288
1289                 if (x2apic_enabled())
1290                         new.ndst = dest;
1291                 else
1292                         new.ndst = (dest << 8) & 0xFF00;
1293
1294                 new.sn = 0;
1295         } while (cmpxchg64(&pi_desc->control, old.control,
1296                            new.control) != old.control);
1297
1298 after_clear_sn:
1299
1300         /*
1301          * Clear SN before reading the bitmap.  The VT-d firmware
1302          * writes the bitmap and reads SN atomically (5.2.3 in the
1303          * spec), so it doesn't really have a memory barrier that
1304          * pairs with this, but we cannot do that and we need one.
1305          */
1306         smp_mb__after_atomic();
1307
1308         if (!pi_is_pir_empty(pi_desc))
1309                 pi_set_on(pi_desc);
1310 }
1311
1312 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu)
1313 {
1314         struct vcpu_vmx *vmx = to_vmx(vcpu);
1315         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
1316
1317         if (!already_loaded) {
1318                 loaded_vmcs_clear(vmx->loaded_vmcs);
1319                 local_irq_disable();
1320                 crash_disable_local_vmclear(cpu);
1321
1322                 /*
1323                  * Read loaded_vmcs->cpu should be before fetching
1324                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1325                  * See the comments in __loaded_vmcs_clear().
1326                  */
1327                 smp_rmb();
1328
1329                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1330                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1331                 crash_enable_local_vmclear(cpu);
1332                 local_irq_enable();
1333         }
1334
1335         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1336                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1337                 vmcs_load(vmx->loaded_vmcs->vmcs);
1338                 indirect_branch_prediction_barrier();
1339         }
1340
1341         if (!already_loaded) {
1342                 void *gdt = get_current_gdt_ro();
1343                 unsigned long sysenter_esp;
1344
1345                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1346
1347                 /*
1348                  * Linux uses per-cpu TSS and GDT, so set these when switching
1349                  * processors.  See 22.2.4.
1350                  */
1351                 vmcs_writel(HOST_TR_BASE,
1352                             (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
1353                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
1354
1355                 /*
1356                  * VM exits change the host TR limit to 0x67 after a VM
1357                  * exit.  This is okay, since 0x67 covers everything except
1358                  * the IO bitmap and have have code to handle the IO bitmap
1359                  * being lost after a VM exit.
1360                  */
1361                 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
1362
1363                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1364                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1365
1366                 vmx->loaded_vmcs->cpu = cpu;
1367         }
1368
1369         /* Setup TSC multiplier */
1370         if (kvm_has_tsc_control &&
1371             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
1372                 decache_tsc_multiplier(vmx);
1373 }
1374
1375 /*
1376  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1377  * vcpu mutex is already taken.
1378  */
1379 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1380 {
1381         struct vcpu_vmx *vmx = to_vmx(vcpu);
1382
1383         vmx_vcpu_load_vmcs(vcpu, cpu);
1384
1385         vmx_vcpu_pi_load(vcpu, cpu);
1386
1387         vmx->host_pkru = read_pkru();
1388         vmx->host_debugctlmsr = get_debugctlmsr();
1389 }
1390
1391 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
1392 {
1393         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1394
1395         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1396                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
1397                 !kvm_vcpu_apicv_active(vcpu))
1398                 return;
1399
1400         /* Set SN when the vCPU is preempted */
1401         if (vcpu->preempted)
1402                 pi_set_sn(pi_desc);
1403 }
1404
1405 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1406 {
1407         vmx_vcpu_pi_put(vcpu);
1408
1409         vmx_prepare_switch_to_host(to_vmx(vcpu));
1410 }
1411
1412 static bool emulation_required(struct kvm_vcpu *vcpu)
1413 {
1414         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
1415 }
1416
1417 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1418
1419 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1420 {
1421         unsigned long rflags, save_rflags;
1422
1423         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1424                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1425                 rflags = vmcs_readl(GUEST_RFLAGS);
1426                 if (to_vmx(vcpu)->rmode.vm86_active) {
1427                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1428                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1429                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1430                 }
1431                 to_vmx(vcpu)->rflags = rflags;
1432         }
1433         return to_vmx(vcpu)->rflags;
1434 }
1435
1436 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1437 {
1438         unsigned long old_rflags = vmx_get_rflags(vcpu);
1439
1440         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1441         to_vmx(vcpu)->rflags = rflags;
1442         if (to_vmx(vcpu)->rmode.vm86_active) {
1443                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1444                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1445         }
1446         vmcs_writel(GUEST_RFLAGS, rflags);
1447
1448         if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
1449                 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
1450 }
1451
1452 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1453 {
1454         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1455         int ret = 0;
1456
1457         if (interruptibility & GUEST_INTR_STATE_STI)
1458                 ret |= KVM_X86_SHADOW_INT_STI;
1459         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1460                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1461
1462         return ret;
1463 }
1464
1465 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1466 {
1467         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1468         u32 interruptibility = interruptibility_old;
1469
1470         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1471
1472         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1473                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1474         else if (mask & KVM_X86_SHADOW_INT_STI)
1475                 interruptibility |= GUEST_INTR_STATE_STI;
1476
1477         if ((interruptibility != interruptibility_old))
1478                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1479 }
1480
1481 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1482 {
1483         struct vcpu_vmx *vmx = to_vmx(vcpu);
1484         unsigned long value;
1485
1486         /*
1487          * Any MSR write that attempts to change bits marked reserved will
1488          * case a #GP fault.
1489          */
1490         if (data & vmx->pt_desc.ctl_bitmask)
1491                 return 1;
1492
1493         /*
1494          * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1495          * result in a #GP unless the same write also clears TraceEn.
1496          */
1497         if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1498                 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1499                 return 1;
1500
1501         /*
1502          * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1503          * and FabricEn would cause #GP, if
1504          * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1505          */
1506         if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1507                 !(data & RTIT_CTL_FABRIC_EN) &&
1508                 !intel_pt_validate_cap(vmx->pt_desc.caps,
1509                                         PT_CAP_single_range_output))
1510                 return 1;
1511
1512         /*
1513          * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1514          * utilize encodings marked reserved will casue a #GP fault.
1515          */
1516         value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1517         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1518                         !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1519                         RTIT_CTL_MTC_RANGE_OFFSET, &value))
1520                 return 1;
1521         value = intel_pt_validate_cap(vmx->pt_desc.caps,
1522                                                 PT_CAP_cycle_thresholds);
1523         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1524                         !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1525                         RTIT_CTL_CYC_THRESH_OFFSET, &value))
1526                 return 1;
1527         value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1528         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1529                         !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1530                         RTIT_CTL_PSB_FREQ_OFFSET, &value))
1531                 return 1;
1532
1533         /*
1534          * If ADDRx_CFG is reserved or the encodings is >2 will
1535          * cause a #GP fault.
1536          */
1537         value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1538         if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
1539                 return 1;
1540         value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1541         if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
1542                 return 1;
1543         value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1544         if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
1545                 return 1;
1546         value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1547         if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
1548                 return 1;
1549
1550         return 0;
1551 }
1552
1553 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
1554 {
1555         unsigned long rip;
1556
1557         /*
1558          * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
1559          * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
1560          * set when EPT misconfig occurs.  In practice, real hardware updates
1561          * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
1562          * (namely Hyper-V) don't set it due to it being undefined behavior,
1563          * i.e. we end up advancing IP with some random value.
1564          */
1565         if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
1566             to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) {
1567                 rip = kvm_rip_read(vcpu);
1568                 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1569                 kvm_rip_write(vcpu, rip);
1570         } else {
1571                 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
1572                         return 0;
1573         }
1574
1575         /* skipping an emulated instruction also counts */
1576         vmx_set_interrupt_shadow(vcpu, 0);
1577
1578         return 1;
1579 }
1580
1581 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1582 {
1583         /*
1584          * Ensure that we clear the HLT state in the VMCS.  We don't need to
1585          * explicitly skip the instruction because if the HLT state is set,
1586          * then the instruction is already executing and RIP has already been
1587          * advanced.
1588          */
1589         if (kvm_hlt_in_guest(vcpu->kvm) &&
1590                         vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1591                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1592 }
1593
1594 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
1595 {
1596         struct vcpu_vmx *vmx = to_vmx(vcpu);
1597         unsigned nr = vcpu->arch.exception.nr;
1598         bool has_error_code = vcpu->arch.exception.has_error_code;
1599         u32 error_code = vcpu->arch.exception.error_code;
1600         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1601
1602         kvm_deliver_exception_payload(vcpu);
1603
1604         if (has_error_code) {
1605                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1606                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1607         }
1608
1609         if (vmx->rmode.vm86_active) {
1610                 int inc_eip = 0;
1611                 if (kvm_exception_is_soft(nr))
1612                         inc_eip = vcpu->arch.event_exit_inst_len;
1613                 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
1614                 return;
1615         }
1616
1617         WARN_ON_ONCE(vmx->emulation_required);
1618
1619         if (kvm_exception_is_soft(nr)) {
1620                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1621                              vmx->vcpu.arch.event_exit_inst_len);
1622                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1623         } else
1624                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1625
1626         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1627
1628         vmx_clear_hlt(vcpu);
1629 }
1630
1631 static bool vmx_rdtscp_supported(void)
1632 {
1633         return cpu_has_vmx_rdtscp();
1634 }
1635
1636 static bool vmx_invpcid_supported(void)
1637 {
1638         return cpu_has_vmx_invpcid();
1639 }
1640
1641 /*
1642  * Swap MSR entry in host/guest MSR entry array.
1643  */
1644 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1645 {
1646         struct shared_msr_entry tmp;
1647
1648         tmp = vmx->guest_msrs[to];
1649         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1650         vmx->guest_msrs[from] = tmp;
1651 }
1652
1653 /*
1654  * Set up the vmcs to automatically save and restore system
1655  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1656  * mode, as fiddling with msrs is very expensive.
1657  */
1658 static void setup_msrs(struct vcpu_vmx *vmx)
1659 {
1660         int save_nmsrs, index;
1661
1662         save_nmsrs = 0;
1663 #ifdef CONFIG_X86_64
1664         /*
1665          * The SYSCALL MSRs are only needed on long mode guests, and only
1666          * when EFER.SCE is set.
1667          */
1668         if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) {
1669                 index = __find_msr_index(vmx, MSR_STAR);
1670                 if (index >= 0)
1671                         move_msr_up(vmx, index, save_nmsrs++);
1672                 index = __find_msr_index(vmx, MSR_LSTAR);
1673                 if (index >= 0)
1674                         move_msr_up(vmx, index, save_nmsrs++);
1675                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1676                 if (index >= 0)
1677                         move_msr_up(vmx, index, save_nmsrs++);
1678         }
1679 #endif
1680         index = __find_msr_index(vmx, MSR_EFER);
1681         if (index >= 0 && update_transition_efer(vmx, index))
1682                 move_msr_up(vmx, index, save_nmsrs++);
1683         index = __find_msr_index(vmx, MSR_TSC_AUX);
1684         if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
1685                 move_msr_up(vmx, index, save_nmsrs++);
1686
1687         vmx->save_nmsrs = save_nmsrs;
1688         vmx->guest_msrs_ready = false;
1689
1690         if (cpu_has_vmx_msr_bitmap())
1691                 vmx_update_msr_bitmap(&vmx->vcpu);
1692 }
1693
1694 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1695 {
1696         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1697
1698         if (is_guest_mode(vcpu) &&
1699             (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
1700                 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
1701
1702         return vcpu->arch.tsc_offset;
1703 }
1704
1705 static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1706 {
1707         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1708         u64 g_tsc_offset = 0;
1709
1710         /*
1711          * We're here if L1 chose not to trap WRMSR to TSC. According
1712          * to the spec, this should set L1's TSC; The offset that L1
1713          * set for L2 remains unchanged, and still needs to be added
1714          * to the newly set TSC to get L2's TSC.
1715          */
1716         if (is_guest_mode(vcpu) &&
1717             (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
1718                 g_tsc_offset = vmcs12->tsc_offset;
1719
1720         trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1721                                    vcpu->arch.tsc_offset - g_tsc_offset,
1722                                    offset);
1723         vmcs_write64(TSC_OFFSET, offset + g_tsc_offset);
1724         return offset + g_tsc_offset;
1725 }
1726
1727 /*
1728  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1729  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1730  * all guests if the "nested" module option is off, and can also be disabled
1731  * for a single guest by disabling its VMX cpuid bit.
1732  */
1733 bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1734 {
1735         return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
1736 }
1737
1738 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1739                                                  uint64_t val)
1740 {
1741         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
1742
1743         return !(val & ~valid_bits);
1744 }
1745
1746 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
1747 {
1748         switch (msr->index) {
1749         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1750                 if (!nested)
1751                         return 1;
1752                 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1753         default:
1754                 return 1;
1755         }
1756
1757         return 0;
1758 }
1759
1760 /*
1761  * Reads an msr value (of 'msr_index') into 'pdata'.
1762  * Returns 0 on success, non-0 otherwise.
1763  * Assumes vcpu_load() was already called.
1764  */
1765 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1766 {
1767         struct vcpu_vmx *vmx = to_vmx(vcpu);
1768         struct shared_msr_entry *msr;
1769         u32 index;
1770
1771         switch (msr_info->index) {
1772 #ifdef CONFIG_X86_64
1773         case MSR_FS_BASE:
1774                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
1775                 break;
1776         case MSR_GS_BASE:
1777                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
1778                 break;
1779         case MSR_KERNEL_GS_BASE:
1780                 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
1781                 break;
1782 #endif
1783         case MSR_EFER:
1784                 return kvm_get_msr_common(vcpu, msr_info);
1785         case MSR_IA32_UMWAIT_CONTROL:
1786                 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1787                         return 1;
1788
1789                 msr_info->data = vmx->msr_ia32_umwait_control;
1790                 break;
1791         case MSR_IA32_SPEC_CTRL:
1792                 if (!msr_info->host_initiated &&
1793                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1794                         return 1;
1795
1796                 msr_info->data = to_vmx(vcpu)->spec_ctrl;
1797                 break;
1798         case MSR_IA32_SYSENTER_CS:
1799                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
1800                 break;
1801         case MSR_IA32_SYSENTER_EIP:
1802                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
1803                 break;
1804         case MSR_IA32_SYSENTER_ESP:
1805                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
1806                 break;
1807         case MSR_IA32_BNDCFGS:
1808                 if (!kvm_mpx_supported() ||
1809                     (!msr_info->host_initiated &&
1810                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1811                         return 1;
1812                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
1813                 break;
1814         case MSR_IA32_MCG_EXT_CTL:
1815                 if (!msr_info->host_initiated &&
1816                     !(vmx->msr_ia32_feature_control &
1817                       FEATURE_CONTROL_LMCE))
1818                         return 1;
1819                 msr_info->data = vcpu->arch.mcg_ext_ctl;
1820                 break;
1821         case MSR_IA32_FEATURE_CONTROL:
1822                 msr_info->data = vmx->msr_ia32_feature_control;
1823                 break;
1824         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1825                 if (!nested_vmx_allowed(vcpu))
1826                         return 1;
1827                 return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1828                                        &msr_info->data);
1829         case MSR_IA32_XSS:
1830                 if (!vmx_xsaves_supported() ||
1831                     (!msr_info->host_initiated &&
1832                      !(guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
1833                        guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))))
1834                         return 1;
1835                 msr_info->data = vcpu->arch.ia32_xss;
1836                 break;
1837         case MSR_IA32_RTIT_CTL:
1838                 if (pt_mode != PT_MODE_HOST_GUEST)
1839                         return 1;
1840                 msr_info->data = vmx->pt_desc.guest.ctl;
1841                 break;
1842         case MSR_IA32_RTIT_STATUS:
1843                 if (pt_mode != PT_MODE_HOST_GUEST)
1844                         return 1;
1845                 msr_info->data = vmx->pt_desc.guest.status;
1846                 break;
1847         case MSR_IA32_RTIT_CR3_MATCH:
1848                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1849                         !intel_pt_validate_cap(vmx->pt_desc.caps,
1850                                                 PT_CAP_cr3_filtering))
1851                         return 1;
1852                 msr_info->data = vmx->pt_desc.guest.cr3_match;
1853                 break;
1854         case MSR_IA32_RTIT_OUTPUT_BASE:
1855                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1856                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1857                                         PT_CAP_topa_output) &&
1858                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1859                                         PT_CAP_single_range_output)))
1860                         return 1;
1861                 msr_info->data = vmx->pt_desc.guest.output_base;
1862                 break;
1863         case MSR_IA32_RTIT_OUTPUT_MASK:
1864                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1865                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1866                                         PT_CAP_topa_output) &&
1867                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1868                                         PT_CAP_single_range_output)))
1869                         return 1;
1870                 msr_info->data = vmx->pt_desc.guest.output_mask;
1871                 break;
1872         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1873                 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1874                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1875                         (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
1876                                         PT_CAP_num_address_ranges)))
1877                         return 1;
1878                 if (index % 2)
1879                         msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1880                 else
1881                         msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1882                 break;
1883         case MSR_TSC_AUX:
1884                 if (!msr_info->host_initiated &&
1885                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
1886                         return 1;
1887                 /* Else, falls through */
1888         default:
1889                 msr = find_msr_entry(vmx, msr_info->index);
1890                 if (msr) {
1891                         msr_info->data = msr->data;
1892                         break;
1893                 }
1894                 return kvm_get_msr_common(vcpu, msr_info);
1895         }
1896
1897         return 0;
1898 }
1899
1900 /*
1901  * Writes msr value into into the appropriate "register".
1902  * Returns 0 on success, non-0 otherwise.
1903  * Assumes vcpu_load() was already called.
1904  */
1905 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1906 {
1907         struct vcpu_vmx *vmx = to_vmx(vcpu);
1908         struct shared_msr_entry *msr;
1909         int ret = 0;
1910         u32 msr_index = msr_info->index;
1911         u64 data = msr_info->data;
1912         u32 index;
1913
1914         switch (msr_index) {
1915         case MSR_EFER:
1916                 ret = kvm_set_msr_common(vcpu, msr_info);
1917                 break;
1918 #ifdef CONFIG_X86_64
1919         case MSR_FS_BASE:
1920                 vmx_segment_cache_clear(vmx);
1921                 vmcs_writel(GUEST_FS_BASE, data);
1922                 break;
1923         case MSR_GS_BASE:
1924                 vmx_segment_cache_clear(vmx);
1925                 vmcs_writel(GUEST_GS_BASE, data);
1926                 break;
1927         case MSR_KERNEL_GS_BASE:
1928                 vmx_write_guest_kernel_gs_base(vmx, data);
1929                 break;
1930 #endif
1931         case MSR_IA32_SYSENTER_CS:
1932                 if (is_guest_mode(vcpu))
1933                         get_vmcs12(vcpu)->guest_sysenter_cs = data;
1934                 vmcs_write32(GUEST_SYSENTER_CS, data);
1935                 break;
1936         case MSR_IA32_SYSENTER_EIP:
1937                 if (is_guest_mode(vcpu))
1938                         get_vmcs12(vcpu)->guest_sysenter_eip = data;
1939                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1940                 break;
1941         case MSR_IA32_SYSENTER_ESP:
1942                 if (is_guest_mode(vcpu))
1943                         get_vmcs12(vcpu)->guest_sysenter_esp = data;
1944                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1945                 break;
1946         case MSR_IA32_DEBUGCTLMSR:
1947                 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
1948                                                 VM_EXIT_SAVE_DEBUG_CONTROLS)
1949                         get_vmcs12(vcpu)->guest_ia32_debugctl = data;
1950
1951                 ret = kvm_set_msr_common(vcpu, msr_info);
1952                 break;
1953
1954         case MSR_IA32_BNDCFGS:
1955                 if (!kvm_mpx_supported() ||
1956                     (!msr_info->host_initiated &&
1957                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1958                         return 1;
1959                 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
1960                     (data & MSR_IA32_BNDCFGS_RSVD))
1961                         return 1;
1962                 vmcs_write64(GUEST_BNDCFGS, data);
1963                 break;
1964         case MSR_IA32_UMWAIT_CONTROL:
1965                 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1966                         return 1;
1967
1968                 /* The reserved bit 1 and non-32 bit [63:32] should be zero */
1969                 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
1970                         return 1;
1971
1972                 vmx->msr_ia32_umwait_control = data;
1973                 break;
1974         case MSR_IA32_SPEC_CTRL:
1975                 if (!msr_info->host_initiated &&
1976                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1977                         return 1;
1978
1979                 /* The STIBP bit doesn't fault even if it's not advertised */
1980                 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
1981                         return 1;
1982
1983                 vmx->spec_ctrl = data;
1984
1985                 if (!data)
1986                         break;
1987
1988                 /*
1989                  * For non-nested:
1990                  * When it's written (to non-zero) for the first time, pass
1991                  * it through.
1992                  *
1993                  * For nested:
1994                  * The handling of the MSR bitmap for L2 guests is done in
1995                  * nested_vmx_merge_msr_bitmap. We should not touch the
1996                  * vmcs02.msr_bitmap here since it gets completely overwritten
1997                  * in the merging. We update the vmcs01 here for L1 as well
1998                  * since it will end up touching the MSR anyway now.
1999                  */
2000                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
2001                                               MSR_IA32_SPEC_CTRL,
2002                                               MSR_TYPE_RW);
2003                 break;
2004         case MSR_IA32_PRED_CMD:
2005                 if (!msr_info->host_initiated &&
2006                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2007                         return 1;
2008
2009                 if (data & ~PRED_CMD_IBPB)
2010                         return 1;
2011
2012                 if (!data)
2013                         break;
2014
2015                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2016
2017                 /*
2018                  * For non-nested:
2019                  * When it's written (to non-zero) for the first time, pass
2020                  * it through.
2021                  *
2022                  * For nested:
2023                  * The handling of the MSR bitmap for L2 guests is done in
2024                  * nested_vmx_merge_msr_bitmap. We should not touch the
2025                  * vmcs02.msr_bitmap here since it gets completely overwritten
2026                  * in the merging.
2027                  */
2028                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
2029                                               MSR_TYPE_W);
2030                 break;
2031         case MSR_IA32_CR_PAT:
2032                 if (!kvm_pat_valid(data))
2033                         return 1;
2034
2035                 if (is_guest_mode(vcpu) &&
2036                     get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
2037                         get_vmcs12(vcpu)->guest_ia32_pat = data;
2038
2039                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2040                         vmcs_write64(GUEST_IA32_PAT, data);
2041                         vcpu->arch.pat = data;
2042                         break;
2043                 }
2044                 ret = kvm_set_msr_common(vcpu, msr_info);
2045                 break;
2046         case MSR_IA32_TSC_ADJUST:
2047                 ret = kvm_set_msr_common(vcpu, msr_info);
2048                 break;
2049         case MSR_IA32_MCG_EXT_CTL:
2050                 if ((!msr_info->host_initiated &&
2051                      !(to_vmx(vcpu)->msr_ia32_feature_control &
2052                        FEATURE_CONTROL_LMCE)) ||
2053                     (data & ~MCG_EXT_CTL_LMCE_EN))
2054                         return 1;
2055                 vcpu->arch.mcg_ext_ctl = data;
2056                 break;
2057         case MSR_IA32_FEATURE_CONTROL:
2058                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
2059                     (to_vmx(vcpu)->msr_ia32_feature_control &
2060                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2061                         return 1;
2062                 vmx->msr_ia32_feature_control = data;
2063                 if (msr_info->host_initiated && data == 0)
2064                         vmx_leave_nested(vcpu);
2065                 break;
2066         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2067                 if (!msr_info->host_initiated)
2068                         return 1; /* they are read-only */
2069                 if (!nested_vmx_allowed(vcpu))
2070                         return 1;
2071                 return vmx_set_vmx_msr(vcpu, msr_index, data);
2072         case MSR_IA32_XSS:
2073                 if (!vmx_xsaves_supported() ||
2074                     (!msr_info->host_initiated &&
2075                      !(guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
2076                        guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))))
2077                         return 1;
2078                 /*
2079                  * The only supported bit as of Skylake is bit 8, but
2080                  * it is not supported on KVM.
2081                  */
2082                 if (data != 0)
2083                         return 1;
2084                 vcpu->arch.ia32_xss = data;
2085                 if (vcpu->arch.ia32_xss != host_xss)
2086                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2087                                 vcpu->arch.ia32_xss, host_xss, false);
2088                 else
2089                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2090                 break;
2091         case MSR_IA32_RTIT_CTL:
2092                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2093                         vmx_rtit_ctl_check(vcpu, data) ||
2094                         vmx->nested.vmxon)
2095                         return 1;
2096                 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
2097                 vmx->pt_desc.guest.ctl = data;
2098                 pt_update_intercept_for_msr(vmx);
2099                 break;
2100         case MSR_IA32_RTIT_STATUS:
2101                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2102                         (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2103                         (data & MSR_IA32_RTIT_STATUS_MASK))
2104                         return 1;
2105                 vmx->pt_desc.guest.status = data;
2106                 break;
2107         case MSR_IA32_RTIT_CR3_MATCH:
2108                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2109                         (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2110                         !intel_pt_validate_cap(vmx->pt_desc.caps,
2111                                                 PT_CAP_cr3_filtering))
2112                         return 1;
2113                 vmx->pt_desc.guest.cr3_match = data;
2114                 break;
2115         case MSR_IA32_RTIT_OUTPUT_BASE:
2116                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2117                         (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2118                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
2119                                         PT_CAP_topa_output) &&
2120                          !intel_pt_validate_cap(vmx->pt_desc.caps,
2121                                         PT_CAP_single_range_output)) ||
2122                         (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK))
2123                         return 1;
2124                 vmx->pt_desc.guest.output_base = data;
2125                 break;
2126         case MSR_IA32_RTIT_OUTPUT_MASK:
2127                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2128                         (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2129                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
2130                                         PT_CAP_topa_output) &&
2131                          !intel_pt_validate_cap(vmx->pt_desc.caps,
2132                                         PT_CAP_single_range_output)))
2133                         return 1;
2134                 vmx->pt_desc.guest.output_mask = data;
2135                 break;
2136         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2137                 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2138                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2139                         (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2140                         (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
2141                                         PT_CAP_num_address_ranges)))
2142                         return 1;
2143                 if (is_noncanonical_address(data, vcpu))
2144                         return 1;
2145                 if (index % 2)
2146                         vmx->pt_desc.guest.addr_b[index / 2] = data;
2147                 else
2148                         vmx->pt_desc.guest.addr_a[index / 2] = data;
2149                 break;
2150         case MSR_TSC_AUX:
2151                 if (!msr_info->host_initiated &&
2152                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
2153                         return 1;
2154                 /* Check reserved bit, higher 32 bits should be zero */
2155                 if ((data >> 32) != 0)
2156                         return 1;
2157                 /* Else, falls through */
2158         default:
2159                 msr = find_msr_entry(vmx, msr_index);
2160                 if (msr) {
2161                         u64 old_msr_data = msr->data;
2162                         msr->data = data;
2163                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2164                                 preempt_disable();
2165                                 ret = kvm_set_shared_msr(msr->index, msr->data,
2166                                                          msr->mask);
2167                                 preempt_enable();
2168                                 if (ret)
2169                                         msr->data = old_msr_data;
2170                         }
2171                         break;
2172                 }
2173                 ret = kvm_set_msr_common(vcpu, msr_info);
2174         }
2175
2176         return ret;
2177 }
2178
2179 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2180 {
2181         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2182         switch (reg) {
2183         case VCPU_REGS_RSP:
2184                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2185                 break;
2186         case VCPU_REGS_RIP:
2187                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2188                 break;
2189         case VCPU_EXREG_PDPTR:
2190                 if (enable_ept)
2191                         ept_save_pdptrs(vcpu);
2192                 break;
2193         default:
2194                 break;
2195         }
2196 }
2197
2198 static __init int cpu_has_kvm_support(void)
2199 {
2200         return cpu_has_vmx();
2201 }
2202
2203 static __init int vmx_disabled_by_bios(void)
2204 {
2205         u64 msr;
2206
2207         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2208         if (msr & FEATURE_CONTROL_LOCKED) {
2209                 /* launched w/ TXT and VMX disabled */
2210                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2211                         && tboot_enabled())
2212                         return 1;
2213                 /* launched w/o TXT and VMX only enabled w/ TXT */
2214                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2215                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2216                         && !tboot_enabled()) {
2217                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2218                                 "activate TXT before enabling KVM\n");
2219                         return 1;
2220                 }
2221                 /* launched w/o TXT and VMX disabled */
2222                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2223                         && !tboot_enabled())
2224                         return 1;
2225         }
2226
2227         return 0;
2228 }
2229
2230 static void kvm_cpu_vmxon(u64 addr)
2231 {
2232         cr4_set_bits(X86_CR4_VMXE);
2233         intel_pt_handle_vmx(1);
2234
2235         asm volatile ("vmxon %0" : : "m"(addr));
2236 }
2237
2238 static int hardware_enable(void)
2239 {
2240         int cpu = raw_smp_processor_id();
2241         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2242         u64 old, test_bits;
2243
2244         if (cr4_read_shadow() & X86_CR4_VMXE)
2245                 return -EBUSY;
2246
2247         /*
2248          * This can happen if we hot-added a CPU but failed to allocate
2249          * VP assist page for it.
2250          */
2251         if (static_branch_unlikely(&enable_evmcs) &&
2252             !hv_get_vp_assist_page(cpu))
2253                 return -EFAULT;
2254
2255         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2256         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
2257         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
2258
2259         /*
2260          * Now we can enable the vmclear operation in kdump
2261          * since the loaded_vmcss_on_cpu list on this cpu
2262          * has been initialized.
2263          *
2264          * Though the cpu is not in VMX operation now, there
2265          * is no problem to enable the vmclear operation
2266          * for the loaded_vmcss_on_cpu list is empty!
2267          */
2268         crash_enable_local_vmclear(cpu);
2269
2270         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2271
2272         test_bits = FEATURE_CONTROL_LOCKED;
2273         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2274         if (tboot_enabled())
2275                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2276
2277         if ((old & test_bits) != test_bits) {
2278                 /* enable and lock */
2279                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2280         }
2281         kvm_cpu_vmxon(phys_addr);
2282         if (enable_ept)
2283                 ept_sync_global();
2284
2285         return 0;
2286 }
2287
2288 static void vmclear_local_loaded_vmcss(void)
2289 {
2290         int cpu = raw_smp_processor_id();
2291         struct loaded_vmcs *v, *n;
2292
2293         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2294                                  loaded_vmcss_on_cpu_link)
2295                 __loaded_vmcs_clear(v);
2296 }
2297
2298
2299 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2300  * tricks.
2301  */
2302 static void kvm_cpu_vmxoff(void)
2303 {
2304         asm volatile (__ex("vmxoff"));
2305
2306         intel_pt_handle_vmx(0);
2307         cr4_clear_bits(X86_CR4_VMXE);
2308 }
2309
2310 static void hardware_disable(void)
2311 {
2312         vmclear_local_loaded_vmcss();
2313         kvm_cpu_vmxoff();
2314 }
2315
2316 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2317                                       u32 msr, u32 *result)
2318 {
2319         u32 vmx_msr_low, vmx_msr_high;
2320         u32 ctl = ctl_min | ctl_opt;
2321
2322         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2323
2324         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2325         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2326
2327         /* Ensure minimum (required) set of control bits are supported. */
2328         if (ctl_min & ~ctl)
2329                 return -EIO;
2330
2331         *result = ctl;
2332         return 0;
2333 }
2334
2335 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2336                                     struct vmx_capability *vmx_cap)
2337 {
2338         u32 vmx_msr_low, vmx_msr_high;
2339         u32 min, opt, min2, opt2;
2340         u32 _pin_based_exec_control = 0;
2341         u32 _cpu_based_exec_control = 0;
2342         u32 _cpu_based_2nd_exec_control = 0;
2343         u32 _vmexit_control = 0;
2344         u32 _vmentry_control = 0;
2345
2346         memset(vmcs_conf, 0, sizeof(*vmcs_conf));
2347         min = CPU_BASED_HLT_EXITING |
2348 #ifdef CONFIG_X86_64
2349               CPU_BASED_CR8_LOAD_EXITING |
2350               CPU_BASED_CR8_STORE_EXITING |
2351 #endif
2352               CPU_BASED_CR3_LOAD_EXITING |
2353               CPU_BASED_CR3_STORE_EXITING |
2354               CPU_BASED_UNCOND_IO_EXITING |
2355               CPU_BASED_MOV_DR_EXITING |
2356               CPU_BASED_USE_TSC_OFFSETING |
2357               CPU_BASED_MWAIT_EXITING |
2358               CPU_BASED_MONITOR_EXITING |
2359               CPU_BASED_INVLPG_EXITING |
2360               CPU_BASED_RDPMC_EXITING;
2361
2362         opt = CPU_BASED_TPR_SHADOW |
2363               CPU_BASED_USE_MSR_BITMAPS |
2364               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2365         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2366                                 &_cpu_based_exec_control) < 0)
2367                 return -EIO;
2368 #ifdef CONFIG_X86_64
2369         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2370                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2371                                            ~CPU_BASED_CR8_STORE_EXITING;
2372 #endif
2373         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2374                 min2 = 0;
2375                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2376                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2377                         SECONDARY_EXEC_WBINVD_EXITING |
2378                         SECONDARY_EXEC_ENABLE_VPID |
2379                         SECONDARY_EXEC_ENABLE_EPT |
2380                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2381                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2382                         SECONDARY_EXEC_DESC |
2383                         SECONDARY_EXEC_RDTSCP |
2384                         SECONDARY_EXEC_ENABLE_INVPCID |
2385                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2386                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2387                         SECONDARY_EXEC_SHADOW_VMCS |
2388                         SECONDARY_EXEC_XSAVES |
2389                         SECONDARY_EXEC_RDSEED_EXITING |
2390                         SECONDARY_EXEC_RDRAND_EXITING |
2391                         SECONDARY_EXEC_ENABLE_PML |
2392                         SECONDARY_EXEC_TSC_SCALING |
2393                         SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
2394                         SECONDARY_EXEC_PT_USE_GPA |
2395                         SECONDARY_EXEC_PT_CONCEAL_VMX |
2396                         SECONDARY_EXEC_ENABLE_VMFUNC |
2397                         SECONDARY_EXEC_ENCLS_EXITING;
2398                 if (adjust_vmx_controls(min2, opt2,
2399                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2400                                         &_cpu_based_2nd_exec_control) < 0)
2401                         return -EIO;
2402         }
2403 #ifndef CONFIG_X86_64
2404         if (!(_cpu_based_2nd_exec_control &
2405                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2406                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2407 #endif
2408
2409         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2410                 _cpu_based_2nd_exec_control &= ~(
2411                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2412                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2413                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2414
2415         rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
2416                 &vmx_cap->ept, &vmx_cap->vpid);
2417
2418         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2419                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2420                    enabled */
2421                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2422                                              CPU_BASED_CR3_STORE_EXITING |
2423                                              CPU_BASED_INVLPG_EXITING);
2424         } else if (vmx_cap->ept) {
2425                 vmx_cap->ept = 0;
2426                 pr_warn_once("EPT CAP should not exist if not support "
2427                                 "1-setting enable EPT VM-execution control\n");
2428         }
2429         if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
2430                 vmx_cap->vpid) {
2431                 vmx_cap->vpid = 0;
2432                 pr_warn_once("VPID CAP should not exist if not support "
2433                                 "1-setting enable VPID VM-execution control\n");
2434         }
2435
2436         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
2437 #ifdef CONFIG_X86_64
2438         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2439 #endif
2440         opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2441               VM_EXIT_LOAD_IA32_PAT |
2442               VM_EXIT_LOAD_IA32_EFER |
2443               VM_EXIT_CLEAR_BNDCFGS |
2444               VM_EXIT_PT_CONCEAL_PIP |
2445               VM_EXIT_CLEAR_IA32_RTIT_CTL;
2446         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2447                                 &_vmexit_control) < 0)
2448                 return -EIO;
2449
2450         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2451         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2452                  PIN_BASED_VMX_PREEMPTION_TIMER;
2453         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2454                                 &_pin_based_exec_control) < 0)
2455                 return -EIO;
2456
2457         if (cpu_has_broken_vmx_preemption_timer())
2458                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2459         if (!(_cpu_based_2nd_exec_control &
2460                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
2461                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2462
2463         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2464         opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2465               VM_ENTRY_LOAD_IA32_PAT |
2466               VM_ENTRY_LOAD_IA32_EFER |
2467               VM_ENTRY_LOAD_BNDCFGS |
2468               VM_ENTRY_PT_CONCEAL_PIP |
2469               VM_ENTRY_LOAD_IA32_RTIT_CTL;
2470         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2471                                 &_vmentry_control) < 0)
2472                 return -EIO;
2473
2474         /*
2475          * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2476          * can't be used due to an errata where VM Exit may incorrectly clear
2477          * IA32_PERF_GLOBAL_CTRL[34:32].  Workaround the errata by using the
2478          * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2479          */
2480         if (boot_cpu_data.x86 == 0x6) {
2481                 switch (boot_cpu_data.x86_model) {
2482                 case 26: /* AAK155 */
2483                 case 30: /* AAP115 */
2484                 case 37: /* AAT100 */
2485                 case 44: /* BC86,AAY89,BD102 */
2486                 case 46: /* BA97 */
2487                         _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
2488                         _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2489                         pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2490                                         "does not work properly. Using workaround\n");
2491                         break;
2492                 default:
2493                         break;
2494                 }
2495         }
2496
2497
2498         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2499
2500         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2501         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2502                 return -EIO;
2503
2504 #ifdef CONFIG_X86_64
2505         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2506         if (vmx_msr_high & (1u<<16))
2507                 return -EIO;
2508 #endif
2509
2510         /* Require Write-Back (WB) memory type for VMCS accesses. */
2511         if (((vmx_msr_high >> 18) & 15) != 6)
2512                 return -EIO;
2513
2514         vmcs_conf->size = vmx_msr_high & 0x1fff;
2515         vmcs_conf->order = get_order(vmcs_conf->size);
2516         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
2517
2518         vmcs_conf->revision_id = vmx_msr_low;
2519
2520         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2521         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2522         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2523         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2524         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2525
2526         if (static_branch_unlikely(&enable_evmcs))
2527                 evmcs_sanitize_exec_ctrls(vmcs_conf);
2528
2529         return 0;
2530 }
2531
2532 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
2533 {
2534         int node = cpu_to_node(cpu);
2535         struct page *pages;
2536         struct vmcs *vmcs;
2537
2538         pages = __alloc_pages_node(node, flags, vmcs_config.order);
2539         if (!pages)
2540                 return NULL;
2541         vmcs = page_address(pages);
2542         memset(vmcs, 0, vmcs_config.size);
2543
2544         /* KVM supports Enlightened VMCS v1 only */
2545         if (static_branch_unlikely(&enable_evmcs))
2546                 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2547         else
2548                 vmcs->hdr.revision_id = vmcs_config.revision_id;
2549
2550         if (shadow)
2551                 vmcs->hdr.shadow_vmcs = 1;
2552         return vmcs;
2553 }
2554
2555 void free_vmcs(struct vmcs *vmcs)
2556 {
2557         free_pages((unsigned long)vmcs, vmcs_config.order);
2558 }
2559
2560 /*
2561  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2562  */
2563 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2564 {
2565         if (!loaded_vmcs->vmcs)
2566                 return;
2567         loaded_vmcs_clear(loaded_vmcs);
2568         free_vmcs(loaded_vmcs->vmcs);
2569         loaded_vmcs->vmcs = NULL;
2570         if (loaded_vmcs->msr_bitmap)
2571                 free_page((unsigned long)loaded_vmcs->msr_bitmap);
2572         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
2573 }
2574
2575 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2576 {
2577         loaded_vmcs->vmcs = alloc_vmcs(false);
2578         if (!loaded_vmcs->vmcs)
2579                 return -ENOMEM;
2580
2581         loaded_vmcs->shadow_vmcs = NULL;
2582         loaded_vmcs->hv_timer_soft_disabled = false;
2583         loaded_vmcs_init(loaded_vmcs);
2584
2585         if (cpu_has_vmx_msr_bitmap()) {
2586                 loaded_vmcs->msr_bitmap = (unsigned long *)
2587                                 __get_free_page(GFP_KERNEL_ACCOUNT);
2588                 if (!loaded_vmcs->msr_bitmap)
2589                         goto out_vmcs;
2590                 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
2591
2592                 if (IS_ENABLED(CONFIG_HYPERV) &&
2593                     static_branch_unlikely(&enable_evmcs) &&
2594                     (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2595                         struct hv_enlightened_vmcs *evmcs =
2596                                 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2597
2598                         evmcs->hv_enlightenments_control.msr_bitmap = 1;
2599                 }
2600         }
2601
2602         memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2603         memset(&loaded_vmcs->controls_shadow, 0,
2604                 sizeof(struct vmcs_controls_shadow));
2605
2606         return 0;
2607
2608 out_vmcs:
2609         free_loaded_vmcs(loaded_vmcs);
2610         return -ENOMEM;
2611 }
2612
2613 static void free_kvm_area(void)
2614 {
2615         int cpu;
2616
2617         for_each_possible_cpu(cpu) {
2618                 free_vmcs(per_cpu(vmxarea, cpu));
2619                 per_cpu(vmxarea, cpu) = NULL;
2620         }
2621 }
2622
2623 static __init int alloc_kvm_area(void)
2624 {
2625         int cpu;
2626
2627         for_each_possible_cpu(cpu) {
2628                 struct vmcs *vmcs;
2629
2630                 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
2631                 if (!vmcs) {
2632                         free_kvm_area();
2633                         return -ENOMEM;
2634                 }
2635
2636                 /*
2637                  * When eVMCS is enabled, alloc_vmcs_cpu() sets
2638                  * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2639                  * revision_id reported by MSR_IA32_VMX_BASIC.
2640                  *
2641                  * However, even though not explicitly documented by
2642                  * TLFS, VMXArea passed as VMXON argument should
2643                  * still be marked with revision_id reported by
2644                  * physical CPU.
2645                  */
2646                 if (static_branch_unlikely(&enable_evmcs))
2647                         vmcs->hdr.revision_id = vmcs_config.revision_id;
2648
2649                 per_cpu(vmxarea, cpu) = vmcs;
2650         }
2651         return 0;
2652 }
2653
2654 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2655                 struct kvm_segment *save)
2656 {
2657         if (!emulate_invalid_guest_state) {
2658                 /*
2659                  * CS and SS RPL should be equal during guest entry according
2660                  * to VMX spec, but in reality it is not always so. Since vcpu
2661                  * is in the middle of the transition from real mode to
2662                  * protected mode it is safe to assume that RPL 0 is a good
2663                  * default value.
2664                  */
2665                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2666                         save->selector &= ~SEGMENT_RPL_MASK;
2667                 save->dpl = save->selector & SEGMENT_RPL_MASK;
2668                 save->s = 1;
2669         }
2670         vmx_set_segment(vcpu, save, seg);
2671 }
2672
2673 static void enter_pmode(struct kvm_vcpu *vcpu)
2674 {
2675         unsigned long flags;
2676         struct vcpu_vmx *vmx = to_vmx(vcpu);
2677
2678         /*
2679          * Update real mode segment cache. It may be not up-to-date if sement
2680          * register was written while vcpu was in a guest mode.
2681          */
2682         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2683         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2684         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2685         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2686         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2687         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2688
2689         vmx->rmode.vm86_active = 0;
2690
2691         vmx_segment_cache_clear(vmx);
2692
2693         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2694
2695         flags = vmcs_readl(GUEST_RFLAGS);
2696         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2697         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2698         vmcs_writel(GUEST_RFLAGS, flags);
2699
2700         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2701                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2702
2703         update_exception_bitmap(vcpu);
2704
2705         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2706         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2707         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2708         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2709         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2710         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2711 }
2712
2713 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2714 {
2715         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2716         struct kvm_segment var = *save;
2717
2718         var.dpl = 0x3;
2719         if (seg == VCPU_SREG_CS)
2720                 var.type = 0x3;
2721
2722         if (!emulate_invalid_guest_state) {
2723                 var.selector = var.base >> 4;
2724                 var.base = var.base & 0xffff0;
2725                 var.limit = 0xffff;
2726                 var.g = 0;
2727                 var.db = 0;
2728                 var.present = 1;
2729                 var.s = 1;
2730                 var.l = 0;
2731                 var.unusable = 0;
2732                 var.type = 0x3;
2733                 var.avl = 0;
2734                 if (save->base & 0xf)
2735                         printk_once(KERN_WARNING "kvm: segment base is not "
2736                                         "paragraph aligned when entering "
2737                                         "protected mode (seg=%d)", seg);
2738         }
2739
2740         vmcs_write16(sf->selector, var.selector);
2741         vmcs_writel(sf->base, var.base);
2742         vmcs_write32(sf->limit, var.limit);
2743         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2744 }
2745
2746 static void enter_rmode(struct kvm_vcpu *vcpu)
2747 {
2748         unsigned long flags;
2749         struct vcpu_vmx *vmx = to_vmx(vcpu);
2750         struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
2751
2752         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2753         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2754         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2755         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2756         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2757         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2758         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2759
2760         vmx->rmode.vm86_active = 1;
2761
2762         /*
2763          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2764          * vcpu. Warn the user that an update is overdue.
2765          */
2766         if (!kvm_vmx->tss_addr)
2767                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2768                              "called before entering vcpu\n");
2769
2770         vmx_segment_cache_clear(vmx);
2771
2772         vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
2773         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2774         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2775
2776         flags = vmcs_readl(GUEST_RFLAGS);
2777         vmx->rmode.save_rflags = flags;
2778
2779         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2780
2781         vmcs_writel(GUEST_RFLAGS, flags);
2782         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2783         update_exception_bitmap(vcpu);
2784
2785         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2786         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2787         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2788         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2789         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2790         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2791
2792         kvm_mmu_reset_context(vcpu);
2793 }
2794
2795 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2796 {
2797         struct vcpu_vmx *vmx = to_vmx(vcpu);
2798         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2799
2800         if (!msr)
2801                 return;
2802
2803         vcpu->arch.efer = efer;
2804         if (efer & EFER_LMA) {
2805                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2806                 msr->data = efer;
2807         } else {
2808                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2809
2810                 msr->data = efer & ~EFER_LME;
2811         }
2812         setup_msrs(vmx);
2813 }
2814
2815 #ifdef CONFIG_X86_64
2816
2817 static void enter_lmode(struct kvm_vcpu *vcpu)
2818 {
2819         u32 guest_tr_ar;
2820
2821         vmx_segment_cache_clear(to_vmx(vcpu));
2822
2823         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2824         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
2825                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2826                                      __func__);
2827                 vmcs_write32(GUEST_TR_AR_BYTES,
2828                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2829                              | VMX_AR_TYPE_BUSY_64_TSS);
2830         }
2831         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2832 }
2833
2834 static void exit_lmode(struct kvm_vcpu *vcpu)
2835 {
2836         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2837         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2838 }
2839
2840 #endif
2841
2842 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2843 {
2844         int vpid = to_vmx(vcpu)->vpid;
2845
2846         if (!vpid_sync_vcpu_addr(vpid, addr))
2847                 vpid_sync_context(vpid);
2848
2849         /*
2850          * If VPIDs are not supported or enabled, then the above is a no-op.
2851          * But we don't really need a TLB flush in that case anyway, because
2852          * each VM entry/exit includes an implicit flush when VPID is 0.
2853          */
2854 }
2855
2856 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2857 {
2858         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2859
2860         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2861         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2862 }
2863
2864 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2865 {
2866         if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
2867                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2868         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2869 }
2870
2871 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2872 {
2873         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2874
2875         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2876         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2877 }
2878
2879 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2880 {
2881         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2882
2883         if (!test_bit(VCPU_EXREG_PDPTR,
2884                       (unsigned long *)&vcpu->arch.regs_dirty))
2885                 return;
2886
2887         if (is_pae_paging(vcpu)) {
2888                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2889                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2890                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2891                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
2892         }
2893 }
2894
2895 void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2896 {
2897         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2898
2899         if (is_pae_paging(vcpu)) {
2900                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2901                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2902                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2903                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2904         }
2905
2906         __set_bit(VCPU_EXREG_PDPTR,
2907                   (unsigned long *)&vcpu->arch.regs_avail);
2908         __set_bit(VCPU_EXREG_PDPTR,
2909                   (unsigned long *)&vcpu->arch.regs_dirty);
2910 }
2911
2912 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2913                                         unsigned long cr0,
2914                                         struct kvm_vcpu *vcpu)
2915 {
2916         struct vcpu_vmx *vmx = to_vmx(vcpu);
2917
2918         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2919                 vmx_decache_cr3(vcpu);
2920         if (!(cr0 & X86_CR0_PG)) {
2921                 /* From paging/starting to nonpaging */
2922                 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2923                                           CPU_BASED_CR3_STORE_EXITING);
2924                 vcpu->arch.cr0 = cr0;
2925                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2926         } else if (!is_paging(vcpu)) {
2927                 /* From nonpaging to paging */
2928                 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2929                                             CPU_BASED_CR3_STORE_EXITING);
2930                 vcpu->arch.cr0 = cr0;
2931                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2932         }
2933
2934         if (!(cr0 & X86_CR0_WP))
2935                 *hw_cr0 &= ~X86_CR0_WP;
2936 }
2937
2938 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2939 {
2940         struct vcpu_vmx *vmx = to_vmx(vcpu);
2941         unsigned long hw_cr0;
2942
2943         hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
2944         if (enable_unrestricted_guest)
2945                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2946         else {
2947                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
2948
2949                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2950                         enter_pmode(vcpu);
2951
2952                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2953                         enter_rmode(vcpu);
2954         }
2955
2956 #ifdef CONFIG_X86_64
2957         if (vcpu->arch.efer & EFER_LME) {
2958                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2959                         enter_lmode(vcpu);
2960                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2961                         exit_lmode(vcpu);
2962         }
2963 #endif
2964
2965         if (enable_ept && !enable_unrestricted_guest)
2966                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2967
2968         vmcs_writel(CR0_READ_SHADOW, cr0);
2969         vmcs_writel(GUEST_CR0, hw_cr0);
2970         vcpu->arch.cr0 = cr0;
2971
2972         /* depends on vcpu->arch.cr0 to be set to a new value */
2973         vmx->emulation_required = emulation_required(vcpu);
2974 }
2975
2976 static int get_ept_level(struct kvm_vcpu *vcpu)
2977 {
2978         if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
2979                 return 5;
2980         return 4;
2981 }
2982
2983 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
2984 {
2985         u64 eptp = VMX_EPTP_MT_WB;
2986
2987         eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
2988
2989         if (enable_ept_ad_bits &&
2990             (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
2991                 eptp |= VMX_EPTP_AD_ENABLE_BIT;
2992         eptp |= (root_hpa & PAGE_MASK);
2993
2994         return eptp;
2995 }
2996
2997 void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2998 {
2999         struct kvm *kvm = vcpu->kvm;
3000         bool update_guest_cr3 = true;
3001         unsigned long guest_cr3;
3002         u64 eptp;
3003
3004         guest_cr3 = cr3;
3005         if (enable_ept) {
3006                 eptp = construct_eptp(vcpu, cr3);
3007                 vmcs_write64(EPT_POINTER, eptp);
3008
3009                 if (kvm_x86_ops->tlb_remote_flush) {
3010                         spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3011                         to_vmx(vcpu)->ept_pointer = eptp;
3012                         to_kvm_vmx(kvm)->ept_pointers_match
3013                                 = EPT_POINTERS_CHECK;
3014                         spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3015                 }
3016
3017                 /* Loading vmcs02.GUEST_CR3 is handled by nested VM-Enter. */
3018                 if (is_guest_mode(vcpu))
3019                         update_guest_cr3 = false;
3020                 else if (enable_unrestricted_guest || is_paging(vcpu))
3021                         guest_cr3 = kvm_read_cr3(vcpu);
3022                 else
3023                         guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
3024                 ept_load_pdptrs(vcpu);
3025         }
3026
3027         if (update_guest_cr3)
3028                 vmcs_writel(GUEST_CR3, guest_cr3);
3029 }
3030
3031 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3032 {
3033         struct vcpu_vmx *vmx = to_vmx(vcpu);
3034         /*
3035          * Pass through host's Machine Check Enable value to hw_cr4, which
3036          * is in force while we are in guest mode.  Do not let guests control
3037          * this bit, even if host CR4.MCE == 0.
3038          */
3039         unsigned long hw_cr4;
3040
3041         hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
3042         if (enable_unrestricted_guest)
3043                 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
3044         else if (vmx->rmode.vm86_active)
3045                 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
3046         else
3047                 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
3048
3049         if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
3050                 if (cr4 & X86_CR4_UMIP) {
3051                         secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
3052                         hw_cr4 &= ~X86_CR4_UMIP;
3053                 } else if (!is_guest_mode(vcpu) ||
3054                         !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
3055                         secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
3056                 }
3057         }
3058
3059         if (cr4 & X86_CR4_VMXE) {
3060                 /*
3061                  * To use VMXON (and later other VMX instructions), a guest
3062                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3063                  * So basically the check on whether to allow nested VMX
3064                  * is here.  We operate under the default treatment of SMM,
3065                  * so VMX cannot be enabled under SMM.
3066                  */
3067                 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
3068                         return 1;
3069         }
3070
3071         if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
3072                 return 1;
3073
3074         vcpu->arch.cr4 = cr4;
3075
3076         if (!enable_unrestricted_guest) {
3077                 if (enable_ept) {
3078                         if (!is_paging(vcpu)) {
3079                                 hw_cr4 &= ~X86_CR4_PAE;
3080                                 hw_cr4 |= X86_CR4_PSE;
3081                         } else if (!(cr4 & X86_CR4_PAE)) {
3082                                 hw_cr4 &= ~X86_CR4_PAE;
3083                         }
3084                 }
3085
3086                 /*
3087                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3088                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
3089                  * to be manually disabled when guest switches to non-paging
3090                  * mode.
3091                  *
3092                  * If !enable_unrestricted_guest, the CPU is always running
3093                  * with CR0.PG=1 and CR4 needs to be modified.
3094                  * If enable_unrestricted_guest, the CPU automatically
3095                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3096                  */
3097                 if (!is_paging(vcpu))
3098                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3099         }
3100
3101         vmcs_writel(CR4_READ_SHADOW, cr4);
3102         vmcs_writel(GUEST_CR4, hw_cr4);
3103         return 0;
3104 }
3105
3106 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3107 {
3108         struct vcpu_vmx *vmx = to_vmx(vcpu);
3109         u32 ar;
3110
3111         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3112                 *var = vmx->rmode.segs[seg];
3113                 if (seg == VCPU_SREG_TR
3114                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3115                         return;
3116                 var->base = vmx_read_guest_seg_base(vmx, seg);
3117                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3118                 return;
3119         }
3120         var->base = vmx_read_guest_seg_base(vmx, seg);
3121         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3122         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3123         ar = vmx_read_guest_seg_ar(vmx, seg);
3124         var->unusable = (ar >> 16) & 1;
3125         var->type = ar & 15;
3126         var->s = (ar >> 4) & 1;
3127         var->dpl = (ar >> 5) & 3;
3128         /*
3129          * Some userspaces do not preserve unusable property. Since usable
3130          * segment has to be present according to VMX spec we can use present
3131          * property to amend userspace bug by making unusable segment always
3132          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3133          * segment as unusable.
3134          */
3135         var->present = !var->unusable;
3136         var->avl = (ar >> 12) & 1;
3137         var->l = (ar >> 13) & 1;
3138         var->db = (ar >> 14) & 1;
3139         var->g = (ar >> 15) & 1;
3140 }
3141
3142 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3143 {
3144         struct kvm_segment s;
3145
3146         if (to_vmx(vcpu)->rmode.vm86_active) {
3147                 vmx_get_segment(vcpu, &s, seg);
3148                 return s.base;
3149         }
3150         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3151 }
3152
3153 int vmx_get_cpl(struct kvm_vcpu *vcpu)
3154 {
3155         struct vcpu_vmx *vmx = to_vmx(vcpu);
3156
3157         if (unlikely(vmx->rmode.vm86_active))
3158                 return 0;
3159         else {
3160                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3161                 return VMX_AR_DPL(ar);
3162         }
3163 }
3164
3165 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3166 {
3167         u32 ar;
3168
3169         if (var->unusable || !var->present)
3170                 ar = 1 << 16;
3171         else {
3172                 ar = var->type & 15;
3173                 ar |= (var->s & 1) << 4;
3174                 ar |= (var->dpl & 3) << 5;
3175                 ar |= (var->present & 1) << 7;
3176                 ar |= (var->avl & 1) << 12;
3177                 ar |= (var->l & 1) << 13;
3178                 ar |= (var->db & 1) << 14;
3179                 ar |= (var->g & 1) << 15;
3180         }
3181
3182         return ar;
3183 }
3184
3185 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3186 {
3187         struct vcpu_vmx *vmx = to_vmx(vcpu);
3188         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3189
3190         vmx_segment_cache_clear(vmx);
3191
3192         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3193                 vmx->rmode.segs[seg] = *var;
3194                 if (seg == VCPU_SREG_TR)
3195                         vmcs_write16(sf->selector, var->selector);
3196                 else if (var->s)
3197                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3198                 goto out;
3199         }
3200
3201         vmcs_writel(sf->base, var->base);
3202         vmcs_write32(sf->limit, var->limit);
3203         vmcs_write16(sf->selector, var->selector);
3204
3205         /*
3206          *   Fix the "Accessed" bit in AR field of segment registers for older
3207          * qemu binaries.
3208          *   IA32 arch specifies that at the time of processor reset the
3209          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3210          * is setting it to 0 in the userland code. This causes invalid guest
3211          * state vmexit when "unrestricted guest" mode is turned on.
3212          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3213          * tree. Newer qemu binaries with that qemu fix would not need this
3214          * kvm hack.
3215          */
3216         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3217                 var->type |= 0x1; /* Accessed */
3218
3219         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3220
3221 out:
3222         vmx->emulation_required = emulation_required(vcpu);
3223 }
3224
3225 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3226 {
3227         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3228
3229         *db = (ar >> 14) & 1;
3230         *l = (ar >> 13) & 1;
3231 }
3232
3233 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3234 {
3235         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3236         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3237 }
3238
3239 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3240 {
3241         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3242         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3243 }
3244
3245 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3246 {
3247         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3248         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3249 }
3250
3251 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3252 {
3253         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3254         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3255 }
3256
3257 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3258 {
3259         struct kvm_segment var;
3260         u32 ar;
3261
3262         vmx_get_segment(vcpu, &var, seg);
3263         var.dpl = 0x3;
3264         if (seg == VCPU_SREG_CS)
3265                 var.type = 0x3;
3266         ar = vmx_segment_access_rights(&var);
3267
3268         if (var.base != (var.selector << 4))
3269                 return false;
3270         if (var.limit != 0xffff)
3271                 return false;
3272         if (ar != 0xf3)
3273                 return false;
3274
3275         return true;
3276 }
3277
3278 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3279 {
3280         struct kvm_segment cs;
3281         unsigned int cs_rpl;
3282
3283         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3284         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3285
3286         if (cs.unusable)
3287                 return false;
3288         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3289                 return false;
3290         if (!cs.s)
3291                 return false;
3292         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3293                 if (cs.dpl > cs_rpl)
3294                         return false;
3295         } else {
3296                 if (cs.dpl != cs_rpl)
3297                         return false;
3298         }
3299         if (!cs.present)
3300                 return false;
3301
3302         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3303         return true;
3304 }
3305
3306 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3307 {
3308         struct kvm_segment ss;
3309         unsigned int ss_rpl;
3310
3311         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3312         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3313
3314         if (ss.unusable)
3315                 return true;
3316         if (ss.type != 3 && ss.type != 7)
3317                 return false;
3318         if (!ss.s)
3319                 return false;
3320         if (ss.dpl != ss_rpl) /* DPL != RPL */
3321                 return false;
3322         if (!ss.present)
3323                 return false;
3324
3325         return true;
3326 }
3327
3328 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3329 {
3330         struct kvm_segment var;
3331         unsigned int rpl;
3332
3333         vmx_get_segment(vcpu, &var, seg);
3334         rpl = var.selector & SEGMENT_RPL_MASK;
3335
3336         if (var.unusable)
3337                 return true;
3338         if (!var.s)
3339                 return false;
3340         if (!var.present)
3341                 return false;
3342         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
3343                 if (var.dpl < rpl) /* DPL < RPL */
3344                         return false;
3345         }
3346
3347         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3348          * rights flags
3349          */
3350         return true;
3351 }
3352
3353 static bool tr_valid(struct kvm_vcpu *vcpu)
3354 {
3355         struct kvm_segment tr;
3356
3357         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3358
3359         if (tr.unusable)
3360                 return false;
3361         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
3362                 return false;
3363         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3364                 return false;
3365         if (!tr.present)
3366                 return false;
3367
3368         return true;
3369 }
3370
3371 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3372 {
3373         struct kvm_segment ldtr;
3374
3375         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3376
3377         if (ldtr.unusable)
3378                 return true;
3379         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
3380                 return false;
3381         if (ldtr.type != 2)
3382                 return false;
3383         if (!ldtr.present)
3384                 return false;
3385
3386         return true;
3387 }
3388
3389 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3390 {
3391         struct kvm_segment cs, ss;
3392
3393         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3394         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3395
3396         return ((cs.selector & SEGMENT_RPL_MASK) ==
3397                  (ss.selector & SEGMENT_RPL_MASK));
3398 }
3399
3400 /*
3401  * Check if guest state is valid. Returns true if valid, false if
3402  * not.
3403  * We assume that registers are always usable
3404  */
3405 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3406 {
3407         if (enable_unrestricted_guest)
3408                 return true;
3409
3410         /* real mode guest state checks */
3411         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3412                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3413                         return false;
3414                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3415                         return false;
3416                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3417                         return false;
3418                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3419                         return false;
3420                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3421                         return false;
3422                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3423                         return false;
3424         } else {
3425         /* protected mode guest state checks */
3426                 if (!cs_ss_rpl_check(vcpu))
3427                         return false;
3428                 if (!code_segment_valid(vcpu))
3429                         return false;
3430                 if (!stack_segment_valid(vcpu))
3431                         return false;
3432                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3433                         return false;
3434                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3435                         return false;
3436                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3437                         return false;
3438                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3439                         return false;
3440                 if (!tr_valid(vcpu))
3441                         return false;
3442                 if (!ldtr_valid(vcpu))
3443                         return false;
3444         }
3445         /* TODO:
3446          * - Add checks on RIP
3447          * - Add checks on RFLAGS
3448          */
3449
3450         return true;
3451 }
3452
3453 static int init_rmode_tss(struct kvm *kvm)
3454 {
3455         gfn_t fn;
3456         u16 data = 0;
3457         int idx, r;
3458
3459         idx = srcu_read_lock(&kvm->srcu);
3460         fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
3461         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3462         if (r < 0)
3463                 goto out;
3464         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3465         r = kvm_write_guest_page(kvm, fn++, &data,
3466                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3467         if (r < 0)
3468                 goto out;
3469         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3470         if (r < 0)
3471                 goto out;
3472         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3473         if (r < 0)
3474                 goto out;
3475         data = ~0;
3476         r = kvm_write_guest_page(kvm, fn, &data,
3477                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3478                                  sizeof(u8));
3479 out:
3480         srcu_read_unlock(&kvm->srcu, idx);
3481         return r;
3482 }
3483
3484 static int init_rmode_identity_map(struct kvm *kvm)
3485 {
3486         struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
3487         int i, idx, r = 0;
3488         kvm_pfn_t identity_map_pfn;
3489         u32 tmp;
3490
3491         /* Protect kvm_vmx->ept_identity_pagetable_done. */
3492         mutex_lock(&kvm->slots_lock);
3493
3494         if (likely(kvm_vmx->ept_identity_pagetable_done))
3495                 goto out2;
3496
3497         if (!kvm_vmx->ept_identity_map_addr)
3498                 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3499         identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
3500
3501         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
3502                                     kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
3503         if (r < 0)
3504                 goto out2;
3505
3506         idx = srcu_read_lock(&kvm->srcu);
3507         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3508         if (r < 0)
3509                 goto out;
3510         /* Set up identity-mapping pagetable for EPT in real mode */
3511         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3512                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3513                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3514                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3515                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3516                 if (r < 0)
3517                         goto out;
3518         }
3519         kvm_vmx->ept_identity_pagetable_done = true;
3520
3521 out:
3522         srcu_read_unlock(&kvm->srcu, idx);
3523
3524 out2:
3525         mutex_unlock(&kvm->slots_lock);
3526         return r;
3527 }
3528
3529 static void seg_setup(int seg)
3530 {
3531         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3532         unsigned int ar;
3533
3534         vmcs_write16(sf->selector, 0);
3535         vmcs_writel(sf->base, 0);
3536         vmcs_write32(sf->limit, 0xffff);
3537         ar = 0x93;
3538         if (seg == VCPU_SREG_CS)
3539                 ar |= 0x08; /* code segment */
3540
3541         vmcs_write32(sf->ar_bytes, ar);
3542 }
3543
3544 static int alloc_apic_access_page(struct kvm *kvm)
3545 {
3546         struct page *page;
3547         int r = 0;
3548
3549         mutex_lock(&kvm->slots_lock);
3550         if (kvm->arch.apic_access_page_done)
3551                 goto out;
3552         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3553                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
3554         if (r)
3555                 goto out;
3556
3557         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
3558         if (is_error_page(page)) {
3559                 r = -EFAULT;
3560                 goto out;
3561         }
3562
3563         /*
3564          * Do not pin the page in memory, so that memory hot-unplug
3565          * is able to migrate it.
3566          */
3567         put_page(page);
3568         kvm->arch.apic_access_page_done = true;
3569 out:
3570         mutex_unlock(&kvm->slots_lock);
3571         return r;
3572 }
3573
3574 int allocate_vpid(void)
3575 {
3576         int vpid;
3577
3578         if (!enable_vpid)
3579                 return 0;
3580         spin_lock(&vmx_vpid_lock);
3581         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3582         if (vpid < VMX_NR_VPIDS)
3583                 __set_bit(vpid, vmx_vpid_bitmap);
3584         else
3585                 vpid = 0;
3586         spin_unlock(&vmx_vpid_lock);
3587         return vpid;
3588 }
3589
3590 void free_vpid(int vpid)
3591 {
3592         if (!enable_vpid || vpid == 0)
3593                 return;
3594         spin_lock(&vmx_vpid_lock);
3595         __clear_bit(vpid, vmx_vpid_bitmap);
3596         spin_unlock(&vmx_vpid_lock);
3597 }
3598
3599 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3600                                                           u32 msr, int type)
3601 {
3602         int f = sizeof(unsigned long);
3603
3604         if (!cpu_has_vmx_msr_bitmap())
3605                 return;
3606
3607         if (static_branch_unlikely(&enable_evmcs))
3608                 evmcs_touch_msr_bitmap();
3609
3610         /*
3611          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3612          * have the write-low and read-high bitmap offsets the wrong way round.
3613          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3614          */
3615         if (msr <= 0x1fff) {
3616                 if (type & MSR_TYPE_R)
3617                         /* read-low */
3618                         __clear_bit(msr, msr_bitmap + 0x000 / f);
3619
3620                 if (type & MSR_TYPE_W)
3621                         /* write-low */
3622                         __clear_bit(msr, msr_bitmap + 0x800 / f);
3623
3624         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3625                 msr &= 0x1fff;
3626                 if (type & MSR_TYPE_R)
3627                         /* read-high */
3628                         __clear_bit(msr, msr_bitmap + 0x400 / f);
3629
3630                 if (type & MSR_TYPE_W)
3631                         /* write-high */
3632                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
3633
3634         }
3635 }
3636
3637 static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3638                                                          u32 msr, int type)
3639 {
3640         int f = sizeof(unsigned long);
3641
3642         if (!cpu_has_vmx_msr_bitmap())
3643                 return;
3644
3645         if (static_branch_unlikely(&enable_evmcs))
3646                 evmcs_touch_msr_bitmap();
3647
3648         /*
3649          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3650          * have the write-low and read-high bitmap offsets the wrong way round.
3651          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3652          */
3653         if (msr <= 0x1fff) {
3654                 if (type & MSR_TYPE_R)
3655                         /* read-low */
3656                         __set_bit(msr, msr_bitmap + 0x000 / f);
3657
3658                 if (type & MSR_TYPE_W)
3659                         /* write-low */
3660                         __set_bit(msr, msr_bitmap + 0x800 / f);
3661
3662         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3663                 msr &= 0x1fff;
3664                 if (type & MSR_TYPE_R)
3665                         /* read-high */
3666                         __set_bit(msr, msr_bitmap + 0x400 / f);
3667
3668                 if (type & MSR_TYPE_W)
3669                         /* write-high */
3670                         __set_bit(msr, msr_bitmap + 0xc00 / f);
3671
3672         }
3673 }
3674
3675 static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
3676                                                       u32 msr, int type, bool value)
3677 {
3678         if (value)
3679                 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
3680         else
3681                 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
3682 }
3683
3684 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
3685 {
3686         u8 mode = 0;
3687
3688         if (cpu_has_secondary_exec_ctrls() &&
3689             (secondary_exec_controls_get(to_vmx(vcpu)) &
3690              SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3691                 mode |= MSR_BITMAP_MODE_X2APIC;
3692                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3693                         mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3694         }
3695
3696         return mode;
3697 }
3698
3699 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
3700                                          u8 mode)
3701 {
3702         int msr;
3703
3704         for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3705                 unsigned word = msr / BITS_PER_LONG;
3706                 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3707                 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
3708         }
3709
3710         if (mode & MSR_BITMAP_MODE_X2APIC) {
3711                 /*
3712                  * TPR reads and writes can be virtualized even if virtual interrupt
3713                  * delivery is not in use.
3714                  */
3715                 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
3716                 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3717                         vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
3718                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3719                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3720                 }
3721         }
3722 }
3723
3724 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
3725 {
3726         struct vcpu_vmx *vmx = to_vmx(vcpu);
3727         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3728         u8 mode = vmx_msr_bitmap_mode(vcpu);
3729         u8 changed = mode ^ vmx->msr_bitmap_mode;
3730
3731         if (!changed)
3732                 return;
3733
3734         if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
3735                 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
3736
3737         vmx->msr_bitmap_mode = mode;
3738 }
3739
3740 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx)
3741 {
3742         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3743         bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3744         u32 i;
3745
3746         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS,
3747                                                         MSR_TYPE_RW, flag);
3748         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE,
3749                                                         MSR_TYPE_RW, flag);
3750         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK,
3751                                                         MSR_TYPE_RW, flag);
3752         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH,
3753                                                         MSR_TYPE_RW, flag);
3754         for (i = 0; i < vmx->pt_desc.addr_range; i++) {
3755                 vmx_set_intercept_for_msr(msr_bitmap,
3756                         MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3757                 vmx_set_intercept_for_msr(msr_bitmap,
3758                         MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3759         }
3760 }
3761
3762 static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu)
3763 {
3764         return enable_apicv;
3765 }
3766
3767 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3768 {
3769         struct vcpu_vmx *vmx = to_vmx(vcpu);
3770         void *vapic_page;
3771         u32 vppr;
3772         int rvi;
3773
3774         if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3775                 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
3776                 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
3777                 return false;
3778
3779         rvi = vmx_get_rvi();
3780
3781         vapic_page = vmx->nested.virtual_apic_map.hva;
3782         vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
3783
3784         return ((rvi & 0xf0) > (vppr & 0xf0));
3785 }
3786
3787 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3788                                                      bool nested)
3789 {
3790 #ifdef CONFIG_SMP
3791         int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3792
3793         if (vcpu->mode == IN_GUEST_MODE) {
3794                 /*
3795                  * The vector of interrupt to be delivered to vcpu had
3796                  * been set in PIR before this function.
3797                  *
3798                  * Following cases will be reached in this block, and
3799                  * we always send a notification event in all cases as
3800                  * explained below.
3801                  *
3802                  * Case 1: vcpu keeps in non-root mode. Sending a
3803                  * notification event posts the interrupt to vcpu.
3804                  *
3805                  * Case 2: vcpu exits to root mode and is still
3806                  * runnable. PIR will be synced to vIRR before the
3807                  * next vcpu entry. Sending a notification event in
3808                  * this case has no effect, as vcpu is not in root
3809                  * mode.
3810                  *
3811                  * Case 3: vcpu exits to root mode and is blocked.
3812                  * vcpu_block() has already synced PIR to vIRR and
3813                  * never blocks vcpu if vIRR is not cleared. Therefore,
3814                  * a blocked vcpu here does not wait for any requested
3815                  * interrupts in PIR, and sending a notification event
3816                  * which has no effect is safe here.
3817                  */
3818
3819                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
3820                 return true;
3821         }
3822 #endif
3823         return false;
3824 }
3825
3826 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3827                                                 int vector)
3828 {
3829         struct vcpu_vmx *vmx = to_vmx(vcpu);
3830
3831         if (is_guest_mode(vcpu) &&
3832             vector == vmx->nested.posted_intr_nv) {
3833                 /*
3834                  * If a posted intr is not recognized by hardware,
3835                  * we will accomplish it in the next vmentry.
3836                  */
3837                 vmx->nested.pi_pending = true;
3838                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3839                 /* the PIR and ON have been set by L1. */
3840                 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3841                         kvm_vcpu_kick(vcpu);
3842                 return 0;
3843         }
3844         return -1;
3845 }
3846 /*
3847  * Send interrupt to vcpu via posted interrupt way.
3848  * 1. If target vcpu is running(non-root mode), send posted interrupt
3849  * notification to vcpu and hardware will sync PIR to vIRR atomically.
3850  * 2. If target vcpu isn't running(root mode), kick it to pick up the
3851  * interrupt from PIR in next vmentry.
3852  */
3853 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3854 {
3855         struct vcpu_vmx *vmx = to_vmx(vcpu);
3856         int r;
3857
3858         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3859         if (!r)
3860                 return;
3861
3862         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
3863                 return;
3864
3865         /* If a previous notification has sent the IPI, nothing to do.  */
3866         if (pi_test_and_set_on(&vmx->pi_desc))
3867                 return;
3868
3869         if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
3870                 kvm_vcpu_kick(vcpu);
3871 }
3872
3873 /*
3874  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3875  * will not change in the lifetime of the guest.
3876  * Note that host-state that does change is set elsewhere. E.g., host-state
3877  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3878  */
3879 void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
3880 {
3881         u32 low32, high32;
3882         unsigned long tmpl;
3883         unsigned long cr0, cr3, cr4;
3884
3885         cr0 = read_cr0();
3886         WARN_ON(cr0 & X86_CR0_TS);
3887         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
3888
3889         /*
3890          * Save the most likely value for this task's CR3 in the VMCS.
3891          * We can't use __get_current_cr3_fast() because we're not atomic.
3892          */
3893         cr3 = __read_cr3();
3894         vmcs_writel(HOST_CR3, cr3);             /* 22.2.3  FIXME: shadow tables */
3895         vmx->loaded_vmcs->host_state.cr3 = cr3;
3896
3897         /* Save the most likely value for this task's CR4 in the VMCS. */
3898         cr4 = cr4_read_shadow();
3899         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
3900         vmx->loaded_vmcs->host_state.cr4 = cr4;
3901
3902         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
3903 #ifdef CONFIG_X86_64
3904         /*
3905          * Load null selectors, so we can avoid reloading them in
3906          * vmx_prepare_switch_to_host(), in case userspace uses
3907          * the null selectors too (the expected case).
3908          */
3909         vmcs_write16(HOST_DS_SELECTOR, 0);
3910         vmcs_write16(HOST_ES_SELECTOR, 0);
3911 #else
3912         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3913         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3914 #endif
3915         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3916         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
3917
3918         vmcs_writel(HOST_IDTR_BASE, host_idt_base);   /* 22.2.4 */
3919
3920         vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
3921
3922         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3923         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3924         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3925         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
3926
3927         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3928                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3929                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3930         }
3931
3932         if (cpu_has_load_ia32_efer())
3933                 vmcs_write64(HOST_IA32_EFER, host_efer);
3934 }
3935
3936 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3937 {
3938         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3939         if (enable_ept)
3940                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3941         if (is_guest_mode(&vmx->vcpu))
3942                 vmx->vcpu.arch.cr4_guest_owned_bits &=
3943                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3944         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3945 }
3946
3947 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
3948 {
3949         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
3950
3951         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
3952                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
3953
3954         if (!enable_vnmi)
3955                 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
3956
3957         if (!enable_preemption_timer)
3958                 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3959
3960         return pin_based_exec_ctrl;
3961 }
3962
3963 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
3964 {
3965         struct vcpu_vmx *vmx = to_vmx(vcpu);
3966
3967         pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
3968         if (cpu_has_secondary_exec_ctrls()) {
3969                 if (kvm_vcpu_apicv_active(vcpu))
3970                         secondary_exec_controls_setbit(vmx,
3971                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
3972                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3973                 else
3974                         secondary_exec_controls_clearbit(vmx,
3975                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3976                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3977         }
3978
3979         if (cpu_has_vmx_msr_bitmap())
3980                 vmx_update_msr_bitmap(vcpu);
3981 }
3982
3983 u32 vmx_exec_control(struct vcpu_vmx *vmx)
3984 {
3985         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3986
3987         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
3988                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
3989
3990         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
3991                 exec_control &= ~CPU_BASED_TPR_SHADOW;
3992 #ifdef CONFIG_X86_64
3993                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3994                                 CPU_BASED_CR8_LOAD_EXITING;
3995 #endif
3996         }
3997         if (!enable_ept)
3998                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3999                                 CPU_BASED_CR3_LOAD_EXITING  |
4000                                 CPU_BASED_INVLPG_EXITING;
4001         if (kvm_mwait_in_guest(vmx->vcpu.kvm))
4002                 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
4003                                 CPU_BASED_MONITOR_EXITING);
4004         if (kvm_hlt_in_guest(vmx->vcpu.kvm))
4005                 exec_control &= ~CPU_BASED_HLT_EXITING;
4006         return exec_control;
4007 }
4008
4009
4010 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
4011 {
4012         struct kvm_vcpu *vcpu = &vmx->vcpu;
4013
4014         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4015
4016         if (pt_mode == PT_MODE_SYSTEM)
4017                 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
4018         if (!cpu_need_virtualize_apic_accesses(vcpu))
4019                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4020         if (vmx->vpid == 0)
4021                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4022         if (!enable_ept) {
4023                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4024                 enable_unrestricted_guest = 0;
4025         }
4026         if (!enable_unrestricted_guest)
4027                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4028         if (kvm_pause_in_guest(vmx->vcpu.kvm))
4029                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4030         if (!kvm_vcpu_apicv_active(vcpu))
4031                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4032                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4033         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4034
4035         /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
4036          * in vmx_set_cr4.  */
4037         exec_control &= ~SECONDARY_EXEC_DESC;
4038
4039         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4040            (handle_vmptrld).
4041            We can NOT enable shadow_vmcs here because we don't have yet
4042            a current VMCS12
4043         */
4044         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4045
4046         if (!enable_pml)
4047                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4048
4049         if (vmx_xsaves_supported()) {
4050                 /* Exposing XSAVES only when XSAVE is exposed */
4051                 bool xsaves_enabled =
4052                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4053                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
4054
4055                 if (!xsaves_enabled)
4056                         exec_control &= ~SECONDARY_EXEC_XSAVES;
4057
4058                 if (nested) {
4059                         if (xsaves_enabled)
4060                                 vmx->nested.msrs.secondary_ctls_high |=
4061                                         SECONDARY_EXEC_XSAVES;
4062                         else
4063                                 vmx->nested.msrs.secondary_ctls_high &=
4064                                         ~SECONDARY_EXEC_XSAVES;
4065                 }
4066         }
4067
4068         if (vmx_rdtscp_supported()) {
4069                 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
4070                 if (!rdtscp_enabled)
4071                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
4072
4073                 if (nested) {
4074                         if (rdtscp_enabled)
4075                                 vmx->nested.msrs.secondary_ctls_high |=
4076                                         SECONDARY_EXEC_RDTSCP;
4077                         else
4078                                 vmx->nested.msrs.secondary_ctls_high &=
4079                                         ~SECONDARY_EXEC_RDTSCP;
4080                 }
4081         }
4082
4083         if (vmx_invpcid_supported()) {
4084                 /* Exposing INVPCID only when PCID is exposed */
4085                 bool invpcid_enabled =
4086                         guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
4087                         guest_cpuid_has(vcpu, X86_FEATURE_PCID);
4088
4089                 if (!invpcid_enabled) {
4090                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4091                         guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
4092                 }
4093
4094                 if (nested) {
4095                         if (invpcid_enabled)
4096                                 vmx->nested.msrs.secondary_ctls_high |=
4097                                         SECONDARY_EXEC_ENABLE_INVPCID;
4098                         else
4099                                 vmx->nested.msrs.secondary_ctls_high &=
4100                                         ~SECONDARY_EXEC_ENABLE_INVPCID;
4101                 }
4102         }
4103
4104         if (vmx_rdrand_supported()) {
4105                 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
4106                 if (rdrand_enabled)
4107                         exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
4108
4109                 if (nested) {
4110                         if (rdrand_enabled)
4111                                 vmx->nested.msrs.secondary_ctls_high |=
4112                                         SECONDARY_EXEC_RDRAND_EXITING;
4113                         else
4114                                 vmx->nested.msrs.secondary_ctls_high &=
4115                                         ~SECONDARY_EXEC_RDRAND_EXITING;
4116                 }
4117         }
4118
4119         if (vmx_rdseed_supported()) {
4120                 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
4121                 if (rdseed_enabled)
4122                         exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
4123
4124                 if (nested) {
4125                         if (rdseed_enabled)
4126                                 vmx->nested.msrs.secondary_ctls_high |=
4127                                         SECONDARY_EXEC_RDSEED_EXITING;
4128                         else
4129                                 vmx->nested.msrs.secondary_ctls_high &=
4130                                         ~SECONDARY_EXEC_RDSEED_EXITING;
4131                 }
4132         }
4133
4134         if (vmx_waitpkg_supported()) {
4135                 bool waitpkg_enabled =
4136                         guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG);
4137
4138                 if (!waitpkg_enabled)
4139                         exec_control &= ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4140
4141                 if (nested) {
4142                         if (waitpkg_enabled)
4143                                 vmx->nested.msrs.secondary_ctls_high |=
4144                                         SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4145                         else
4146                                 vmx->nested.msrs.secondary_ctls_high &=
4147                                         ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4148                 }
4149         }
4150
4151         vmx->secondary_exec_control = exec_control;
4152 }
4153
4154 static void ept_set_mmio_spte_mask(void)
4155 {
4156         /*
4157          * EPT Misconfigurations can be generated if the value of bits 2:0
4158          * of an EPT paging-structure entry is 110b (write/execute).
4159          */
4160         kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
4161                                    VMX_EPT_MISCONFIG_WX_VALUE, 0);
4162 }
4163
4164 #define VMX_XSS_EXIT_BITMAP 0
4165
4166 /*
4167  * Sets up the vmcs for emulated real mode.
4168  */
4169 static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
4170 {
4171         int i;
4172
4173         if (nested)
4174                 nested_vmx_vcpu_setup();
4175
4176         if (cpu_has_vmx_msr_bitmap())
4177                 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
4178
4179         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4180
4181         /* Control */
4182         pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4183         vmx->hv_deadline_tsc = -1;
4184
4185         exec_controls_set(vmx, vmx_exec_control(vmx));
4186
4187         if (cpu_has_secondary_exec_ctrls()) {
4188                 vmx_compute_secondary_exec_control(vmx);
4189                 secondary_exec_controls_set(vmx, vmx->secondary_exec_control);
4190         }
4191
4192         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4193                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4194                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4195                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4196                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4197
4198                 vmcs_write16(GUEST_INTR_STATUS, 0);
4199
4200                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4201                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4202         }
4203
4204         if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4205                 vmcs_write32(PLE_GAP, ple_gap);
4206                 vmx->ple_window = ple_window;
4207                 vmx->ple_window_dirty = true;
4208         }
4209
4210         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4211         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4212         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4213
4214         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4215         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4216         vmx_set_constant_host_state(vmx);
4217         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4218         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4219
4220         if (cpu_has_vmx_vmfunc())
4221                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4222
4223         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4224         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4225         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
4226         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4227         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
4228
4229         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4230                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4231
4232         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4233                 u32 index = vmx_msr_index[i];
4234                 u32 data_low, data_high;
4235                 int j = vmx->nmsrs;
4236
4237                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4238                         continue;
4239                 if (wrmsr_safe(index, data_low, data_high) < 0)
4240                         continue;
4241                 vmx->guest_msrs[j].index = i;
4242                 vmx->guest_msrs[j].data = 0;
4243                 vmx->guest_msrs[j].mask = -1ull;
4244                 ++vmx->nmsrs;
4245         }
4246
4247         vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
4248
4249         /* 22.2.1, 20.8.1 */
4250         vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
4251
4252         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
4253         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
4254
4255         set_cr4_guest_host_mask(vmx);
4256
4257         if (vmx_xsaves_supported())
4258                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4259
4260         if (enable_pml) {
4261                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4262                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4263         }
4264
4265         if (cpu_has_vmx_encls_vmexit())
4266                 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
4267
4268         if (pt_mode == PT_MODE_HOST_GUEST) {
4269                 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4270                 /* Bit[6~0] are forced to 1, writes are ignored. */
4271                 vmx->pt_desc.guest.output_mask = 0x7F;
4272                 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4273         }
4274 }
4275
4276 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4277 {
4278         struct vcpu_vmx *vmx = to_vmx(vcpu);
4279         struct msr_data apic_base_msr;
4280         u64 cr0;
4281
4282         vmx->rmode.vm86_active = 0;
4283         vmx->spec_ctrl = 0;
4284
4285         vmx->msr_ia32_umwait_control = 0;
4286
4287         vcpu->arch.microcode_version = 0x100000000ULL;
4288         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4289         vmx->hv_deadline_tsc = -1;
4290         kvm_set_cr8(vcpu, 0);
4291
4292         if (!init_event) {
4293                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4294                                      MSR_IA32_APICBASE_ENABLE;
4295                 if (kvm_vcpu_is_reset_bsp(vcpu))
4296                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4297                 apic_base_msr.host_initiated = true;
4298                 kvm_set_apic_base(vcpu, &apic_base_msr);
4299         }
4300
4301         vmx_segment_cache_clear(vmx);
4302
4303         seg_setup(VCPU_SREG_CS);
4304         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4305         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4306
4307         seg_setup(VCPU_SREG_DS);
4308         seg_setup(VCPU_SREG_ES);
4309         seg_setup(VCPU_SREG_FS);
4310         seg_setup(VCPU_SREG_GS);
4311         seg_setup(VCPU_SREG_SS);
4312
4313         vmcs_write16(GUEST_TR_SELECTOR, 0);
4314         vmcs_writel(GUEST_TR_BASE, 0);
4315         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4316         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4317
4318         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4319         vmcs_writel(GUEST_LDTR_BASE, 0);
4320         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4321         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4322
4323         if (!init_event) {
4324                 vmcs_write32(GUEST_SYSENTER_CS, 0);
4325                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4326                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4327                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4328         }
4329
4330         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
4331         kvm_rip_write(vcpu, 0xfff0);
4332
4333         vmcs_writel(GUEST_GDTR_BASE, 0);
4334         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4335
4336         vmcs_writel(GUEST_IDTR_BASE, 0);
4337         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4338
4339         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4340         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4341         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4342         if (kvm_mpx_supported())
4343                 vmcs_write64(GUEST_BNDCFGS, 0);
4344
4345         setup_msrs(vmx);
4346
4347         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4348
4349         if (cpu_has_vmx_tpr_shadow() && !init_event) {
4350                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4351                 if (cpu_need_tpr_shadow(vcpu))
4352                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4353                                      __pa(vcpu->arch.apic->regs));
4354                 vmcs_write32(TPR_THRESHOLD, 0);
4355         }
4356
4357         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4358
4359         if (vmx->vpid != 0)
4360                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4361
4362         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4363         vmx->vcpu.arch.cr0 = cr0;
4364         vmx_set_cr0(vcpu, cr0); /* enter rmode */
4365         vmx_set_cr4(vcpu, 0);
4366         vmx_set_efer(vcpu, 0);
4367
4368         update_exception_bitmap(vcpu);
4369
4370         vpid_sync_context(vmx->vpid);
4371         if (init_event)
4372                 vmx_clear_hlt(vcpu);
4373 }
4374
4375 static void enable_irq_window(struct kvm_vcpu *vcpu)
4376 {
4377         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_INTR_PENDING);
4378 }
4379
4380 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4381 {
4382         if (!enable_vnmi ||
4383             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4384                 enable_irq_window(vcpu);
4385                 return;
4386         }
4387
4388         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_NMI_PENDING);
4389 }
4390
4391 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4392 {
4393         struct vcpu_vmx *vmx = to_vmx(vcpu);
4394         uint32_t intr;
4395         int irq = vcpu->arch.interrupt.nr;
4396
4397         trace_kvm_inj_virq(irq);
4398
4399         ++vcpu->stat.irq_injections;
4400         if (vmx->rmode.vm86_active) {
4401                 int inc_eip = 0;
4402                 if (vcpu->arch.interrupt.soft)
4403                         inc_eip = vcpu->arch.event_exit_inst_len;
4404                 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
4405                 return;
4406         }
4407         intr = irq | INTR_INFO_VALID_MASK;
4408         if (vcpu->arch.interrupt.soft) {
4409                 intr |= INTR_TYPE_SOFT_INTR;
4410                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4411                              vmx->vcpu.arch.event_exit_inst_len);
4412         } else
4413                 intr |= INTR_TYPE_EXT_INTR;
4414         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4415
4416         vmx_clear_hlt(vcpu);
4417 }
4418
4419 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4420 {
4421         struct vcpu_vmx *vmx = to_vmx(vcpu);
4422
4423         if (!enable_vnmi) {
4424                 /*
4425                  * Tracking the NMI-blocked state in software is built upon
4426                  * finding the next open IRQ window. This, in turn, depends on
4427                  * well-behaving guests: They have to keep IRQs disabled at
4428                  * least as long as the NMI handler runs. Otherwise we may
4429                  * cause NMI nesting, maybe breaking the guest. But as this is
4430                  * highly unlikely, we can live with the residual risk.
4431                  */
4432                 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4433                 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4434         }
4435
4436         ++vcpu->stat.nmi_injections;
4437         vmx->loaded_vmcs->nmi_known_unmasked = false;
4438
4439         if (vmx->rmode.vm86_active) {
4440                 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
4441                 return;
4442         }
4443
4444         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4445                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4446
4447         vmx_clear_hlt(vcpu);
4448 }
4449
4450 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4451 {
4452         struct vcpu_vmx *vmx = to_vmx(vcpu);
4453         bool masked;
4454
4455         if (!enable_vnmi)
4456                 return vmx->loaded_vmcs->soft_vnmi_blocked;
4457         if (vmx->loaded_vmcs->nmi_known_unmasked)
4458                 return false;
4459         masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4460         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4461         return masked;
4462 }
4463
4464 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4465 {
4466         struct vcpu_vmx *vmx = to_vmx(vcpu);
4467
4468         if (!enable_vnmi) {
4469                 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4470                         vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4471                         vmx->loaded_vmcs->vnmi_blocked_time = 0;
4472                 }
4473         } else {
4474                 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4475                 if (masked)
4476                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4477                                       GUEST_INTR_STATE_NMI);
4478                 else
4479                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4480                                         GUEST_INTR_STATE_NMI);
4481         }
4482 }
4483
4484 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4485 {
4486         if (to_vmx(vcpu)->nested.nested_run_pending)
4487                 return 0;
4488
4489         if (!enable_vnmi &&
4490             to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4491                 return 0;
4492
4493         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4494                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4495                    | GUEST_INTR_STATE_NMI));
4496 }
4497
4498 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4499 {
4500         return (!to_vmx(vcpu)->nested.nested_run_pending &&
4501                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4502                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4503                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4504 }
4505
4506 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4507 {
4508         int ret;
4509
4510         if (enable_unrestricted_guest)
4511                 return 0;
4512
4513         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4514                                     PAGE_SIZE * 3);
4515         if (ret)
4516                 return ret;
4517         to_kvm_vmx(kvm)->tss_addr = addr;
4518         return init_rmode_tss(kvm);
4519 }
4520
4521 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4522 {
4523         to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
4524         return 0;
4525 }
4526
4527 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4528 {
4529         switch (vec) {
4530         case BP_VECTOR:
4531                 /*
4532                  * Update instruction length as we may reinject the exception
4533                  * from user space while in guest debugging mode.
4534                  */
4535                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4536                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4537                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4538                         return false;
4539                 /* fall through */
4540         case DB_VECTOR:
4541                 if (vcpu->guest_debug &
4542                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4543                         return false;
4544                 /* fall through */
4545         case DE_VECTOR:
4546         case OF_VECTOR:
4547         case BR_VECTOR:
4548         case UD_VECTOR:
4549         case DF_VECTOR:
4550         case SS_VECTOR:
4551         case GP_VECTOR:
4552         case MF_VECTOR:
4553                 return true;
4554         break;
4555         }
4556         return false;
4557 }
4558
4559 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4560                                   int vec, u32 err_code)
4561 {
4562         /*
4563          * Instruction with address size override prefix opcode 0x67
4564          * Cause the #SS fault with 0 error code in VM86 mode.
4565          */
4566         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4567                 if (kvm_emulate_instruction(vcpu, 0)) {
4568                         if (vcpu->arch.halt_request) {
4569                                 vcpu->arch.halt_request = 0;
4570                                 return kvm_vcpu_halt(vcpu);
4571                         }
4572                         return 1;
4573                 }
4574                 return 0;
4575         }
4576
4577         /*
4578          * Forward all other exceptions that are valid in real mode.
4579          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4580          *        the required debugging infrastructure rework.
4581          */
4582         kvm_queue_exception(vcpu, vec);
4583         return 1;
4584 }
4585
4586 /*
4587  * Trigger machine check on the host. We assume all the MSRs are already set up
4588  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4589  * We pass a fake environment to the machine check handler because we want
4590  * the guest to be always treated like user space, no matter what context
4591  * it used internally.
4592  */
4593 static void kvm_machine_check(void)
4594 {
4595 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4596         struct pt_regs regs = {
4597                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4598                 .flags = X86_EFLAGS_IF,
4599         };
4600
4601         do_machine_check(&regs, 0);
4602 #endif
4603 }
4604
4605 static int handle_machine_check(struct kvm_vcpu *vcpu)
4606 {
4607         /* handled by vmx_vcpu_run() */
4608         return 1;
4609 }
4610
4611 static int handle_exception_nmi(struct kvm_vcpu *vcpu)
4612 {
4613         struct vcpu_vmx *vmx = to_vmx(vcpu);
4614         struct kvm_run *kvm_run = vcpu->run;
4615         u32 intr_info, ex_no, error_code;
4616         unsigned long cr2, rip, dr6;
4617         u32 vect_info;
4618
4619         vect_info = vmx->idt_vectoring_info;
4620         intr_info = vmx->exit_intr_info;
4621
4622         if (is_machine_check(intr_info) || is_nmi(intr_info))
4623                 return 1; /* handled by handle_exception_nmi_irqoff() */
4624
4625         if (is_invalid_opcode(intr_info))
4626                 return handle_ud(vcpu);
4627
4628         error_code = 0;
4629         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4630                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4631
4632         if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4633                 WARN_ON_ONCE(!enable_vmware_backdoor);
4634
4635                 /*
4636                  * VMware backdoor emulation on #GP interception only handles
4637                  * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
4638                  * error code on #GP.
4639                  */
4640                 if (error_code) {
4641                         kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4642                         return 1;
4643                 }
4644                 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
4645         }
4646
4647         /*
4648          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4649          * MMIO, it is better to report an internal error.
4650          * See the comments in vmx_handle_exit.
4651          */
4652         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4653             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4654                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4655                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4656                 vcpu->run->internal.ndata = 3;
4657                 vcpu->run->internal.data[0] = vect_info;
4658                 vcpu->run->internal.data[1] = intr_info;
4659                 vcpu->run->internal.data[2] = error_code;
4660                 return 0;
4661         }
4662
4663         if (is_page_fault(intr_info)) {
4664                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4665                 /* EPT won't cause page fault directly */
4666                 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
4667                 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
4668         }
4669
4670         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4671
4672         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4673                 return handle_rmode_exception(vcpu, ex_no, error_code);
4674
4675         switch (ex_no) {
4676         case AC_VECTOR:
4677                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4678                 return 1;
4679         case DB_VECTOR:
4680                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4681                 if (!(vcpu->guest_debug &
4682                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4683                         vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4684                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
4685                         if (is_icebp(intr_info))
4686                                 WARN_ON(!skip_emulated_instruction(vcpu));
4687
4688                         kvm_queue_exception(vcpu, DB_VECTOR);
4689                         return 1;
4690                 }
4691                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4692                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4693                 /* fall through */
4694         case BP_VECTOR:
4695                 /*
4696                  * Update instruction length as we may reinject #BP from
4697                  * user space while in guest debugging mode. Reading it for
4698                  * #DB as well causes no harm, it is not used in that case.
4699                  */
4700                 vmx->vcpu.arch.event_exit_inst_len =
4701                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4702                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4703                 rip = kvm_rip_read(vcpu);
4704                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4705                 kvm_run->debug.arch.exception = ex_no;
4706                 break;
4707         default:
4708                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4709                 kvm_run->ex.exception = ex_no;
4710                 kvm_run->ex.error_code = error_code;
4711                 break;
4712         }
4713         return 0;
4714 }
4715
4716 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4717 {
4718         ++vcpu->stat.irq_exits;
4719         return 1;
4720 }
4721
4722 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4723 {
4724         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4725         vcpu->mmio_needed = 0;
4726         return 0;
4727 }
4728
4729 static int handle_io(struct kvm_vcpu *vcpu)
4730 {
4731         unsigned long exit_qualification;
4732         int size, in, string;
4733         unsigned port;
4734
4735         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4736         string = (exit_qualification & 16) != 0;
4737
4738         ++vcpu->stat.io_exits;
4739
4740         if (string)
4741                 return kvm_emulate_instruction(vcpu, 0);
4742
4743         port = exit_qualification >> 16;
4744         size = (exit_qualification & 7) + 1;
4745         in = (exit_qualification & 8) != 0;
4746
4747         return kvm_fast_pio(vcpu, size, port, in);
4748 }
4749
4750 static void
4751 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4752 {
4753         /*
4754          * Patch in the VMCALL instruction:
4755          */
4756         hypercall[0] = 0x0f;
4757         hypercall[1] = 0x01;
4758         hypercall[2] = 0xc1;
4759 }
4760
4761 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4762 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4763 {
4764         if (is_guest_mode(vcpu)) {
4765                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4766                 unsigned long orig_val = val;
4767
4768                 /*
4769                  * We get here when L2 changed cr0 in a way that did not change
4770                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4771                  * but did change L0 shadowed bits. So we first calculate the
4772                  * effective cr0 value that L1 would like to write into the
4773                  * hardware. It consists of the L2-owned bits from the new
4774                  * value combined with the L1-owned bits from L1's guest_cr0.
4775                  */
4776                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4777                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4778
4779                 if (!nested_guest_cr0_valid(vcpu, val))
4780                         return 1;
4781
4782                 if (kvm_set_cr0(vcpu, val))
4783                         return 1;
4784                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4785                 return 0;
4786         } else {
4787                 if (to_vmx(vcpu)->nested.vmxon &&
4788                     !nested_host_cr0_valid(vcpu, val))
4789                         return 1;
4790
4791                 return kvm_set_cr0(vcpu, val);
4792         }
4793 }
4794
4795 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4796 {
4797         if (is_guest_mode(vcpu)) {
4798                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4799                 unsigned long orig_val = val;
4800
4801                 /* analogously to handle_set_cr0 */
4802                 val = (val & ~vmcs12->cr4_guest_host_mask) |
4803                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4804                 if (kvm_set_cr4(vcpu, val))
4805                         return 1;
4806                 vmcs_writel(CR4_READ_SHADOW, orig_val);
4807                 return 0;
4808         } else
4809                 return kvm_set_cr4(vcpu, val);
4810 }
4811
4812 static int handle_desc(struct kvm_vcpu *vcpu)
4813 {
4814         WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
4815         return kvm_emulate_instruction(vcpu, 0);
4816 }
4817
4818 static int handle_cr(struct kvm_vcpu *vcpu)
4819 {
4820         unsigned long exit_qualification, val;
4821         int cr;
4822         int reg;
4823         int err;
4824         int ret;
4825
4826         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4827         cr = exit_qualification & 15;
4828         reg = (exit_qualification >> 8) & 15;
4829         switch ((exit_qualification >> 4) & 3) {
4830         case 0: /* mov to cr */
4831                 val = kvm_register_readl(vcpu, reg);
4832                 trace_kvm_cr_write(cr, val);
4833                 switch (cr) {
4834                 case 0:
4835                         err = handle_set_cr0(vcpu, val);
4836                         return kvm_complete_insn_gp(vcpu, err);
4837                 case 3:
4838                         WARN_ON_ONCE(enable_unrestricted_guest);
4839                         err = kvm_set_cr3(vcpu, val);
4840                         return kvm_complete_insn_gp(vcpu, err);
4841                 case 4:
4842                         err = handle_set_cr4(vcpu, val);
4843                         return kvm_complete_insn_gp(vcpu, err);
4844                 case 8: {
4845                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4846                                 u8 cr8 = (u8)val;
4847                                 err = kvm_set_cr8(vcpu, cr8);
4848                                 ret = kvm_complete_insn_gp(vcpu, err);
4849                                 if (lapic_in_kernel(vcpu))
4850                                         return ret;
4851                                 if (cr8_prev <= cr8)
4852                                         return ret;
4853                                 /*
4854                                  * TODO: we might be squashing a
4855                                  * KVM_GUESTDBG_SINGLESTEP-triggered
4856                                  * KVM_EXIT_DEBUG here.
4857                                  */
4858                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4859                                 return 0;
4860                         }
4861                 }
4862                 break;
4863         case 2: /* clts */
4864                 WARN_ONCE(1, "Guest should always own CR0.TS");
4865                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4866                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4867                 return kvm_skip_emulated_instruction(vcpu);
4868         case 1: /*mov from cr*/
4869                 switch (cr) {
4870                 case 3:
4871                         WARN_ON_ONCE(enable_unrestricted_guest);
4872                         val = kvm_read_cr3(vcpu);
4873                         kvm_register_write(vcpu, reg, val);
4874                         trace_kvm_cr_read(cr, val);
4875                         return kvm_skip_emulated_instruction(vcpu);
4876                 case 8:
4877                         val = kvm_get_cr8(vcpu);
4878                         kvm_register_write(vcpu, reg, val);
4879                         trace_kvm_cr_read(cr, val);
4880                         return kvm_skip_emulated_instruction(vcpu);
4881                 }
4882                 break;
4883         case 3: /* lmsw */
4884                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4885                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4886                 kvm_lmsw(vcpu, val);
4887
4888                 return kvm_skip_emulated_instruction(vcpu);
4889         default:
4890                 break;
4891         }
4892         vcpu->run->exit_reason = 0;
4893         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4894                (int)(exit_qualification >> 4) & 3, cr);
4895         return 0;
4896 }
4897
4898 static int handle_dr(struct kvm_vcpu *vcpu)
4899 {
4900         unsigned long exit_qualification;
4901         int dr, dr7, reg;
4902
4903         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4904         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4905
4906         /* First, if DR does not exist, trigger UD */
4907         if (!kvm_require_dr(vcpu, dr))
4908                 return 1;
4909
4910         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4911         if (!kvm_require_cpl(vcpu, 0))
4912                 return 1;
4913         dr7 = vmcs_readl(GUEST_DR7);
4914         if (dr7 & DR7_GD) {
4915                 /*
4916                  * As the vm-exit takes precedence over the debug trap, we
4917                  * need to emulate the latter, either for the host or the
4918                  * guest debugging itself.
4919                  */
4920                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4921                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4922                         vcpu->run->debug.arch.dr7 = dr7;
4923                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
4924                         vcpu->run->debug.arch.exception = DB_VECTOR;
4925                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4926                         return 0;
4927                 } else {
4928                         vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4929                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
4930                         kvm_queue_exception(vcpu, DB_VECTOR);
4931                         return 1;
4932                 }
4933         }
4934
4935         if (vcpu->guest_debug == 0) {
4936                 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
4937
4938                 /*
4939                  * No more DR vmexits; force a reload of the debug registers
4940                  * and reenter on this instruction.  The next vmexit will
4941                  * retrieve the full state of the debug registers.
4942                  */
4943                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4944                 return 1;
4945         }
4946
4947         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4948         if (exit_qualification & TYPE_MOV_FROM_DR) {
4949                 unsigned long val;
4950
4951                 if (kvm_get_dr(vcpu, dr, &val))
4952                         return 1;
4953                 kvm_register_write(vcpu, reg, val);
4954         } else
4955                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4956                         return 1;
4957
4958         return kvm_skip_emulated_instruction(vcpu);
4959 }
4960
4961 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
4962 {
4963         return vcpu->arch.dr6;
4964 }
4965
4966 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
4967 {
4968 }
4969
4970 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
4971 {
4972         get_debugreg(vcpu->arch.db[0], 0);
4973         get_debugreg(vcpu->arch.db[1], 1);
4974         get_debugreg(vcpu->arch.db[2], 2);
4975         get_debugreg(vcpu->arch.db[3], 3);
4976         get_debugreg(vcpu->arch.dr6, 6);
4977         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
4978
4979         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
4980         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
4981 }
4982
4983 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4984 {
4985         vmcs_writel(GUEST_DR7, val);
4986 }
4987
4988 static int handle_cpuid(struct kvm_vcpu *vcpu)
4989 {
4990         return kvm_emulate_cpuid(vcpu);
4991 }
4992
4993 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4994 {
4995         return kvm_emulate_rdmsr(vcpu);
4996 }
4997
4998 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4999 {
5000         return kvm_emulate_wrmsr(vcpu);
5001 }
5002
5003 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5004 {
5005         kvm_apic_update_ppr(vcpu);
5006         return 1;
5007 }
5008
5009 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5010 {
5011         exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_INTR_PENDING);
5012
5013         kvm_make_request(KVM_REQ_EVENT, vcpu);
5014
5015         ++vcpu->stat.irq_window_exits;
5016         return 1;
5017 }
5018
5019 static int handle_halt(struct kvm_vcpu *vcpu)
5020 {
5021         return kvm_emulate_halt(vcpu);
5022 }
5023
5024 static int handle_vmcall(struct kvm_vcpu *vcpu)
5025 {
5026         return kvm_emulate_hypercall(vcpu);
5027 }
5028
5029 static int handle_invd(struct kvm_vcpu *vcpu)
5030 {
5031         return kvm_emulate_instruction(vcpu, 0);
5032 }
5033
5034 static int handle_invlpg(struct kvm_vcpu *vcpu)
5035 {
5036         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5037
5038         kvm_mmu_invlpg(vcpu, exit_qualification);
5039         return kvm_skip_emulated_instruction(vcpu);
5040 }
5041
5042 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5043 {
5044         int err;
5045
5046         err = kvm_rdpmc(vcpu);
5047         return kvm_complete_insn_gp(vcpu, err);
5048 }
5049
5050 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5051 {
5052         return kvm_emulate_wbinvd(vcpu);
5053 }
5054
5055 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5056 {
5057         u64 new_bv = kvm_read_edx_eax(vcpu);
5058         u32 index = kvm_rcx_read(vcpu);
5059
5060         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5061                 return kvm_skip_emulated_instruction(vcpu);
5062         return 1;
5063 }
5064
5065 static int handle_apic_access(struct kvm_vcpu *vcpu)
5066 {
5067         if (likely(fasteoi)) {
5068                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5069                 int access_type, offset;
5070
5071                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5072                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5073                 /*
5074                  * Sane guest uses MOV to write EOI, with written value
5075                  * not cared. So make a short-circuit here by avoiding
5076                  * heavy instruction emulation.
5077                  */
5078                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5079                     (offset == APIC_EOI)) {
5080                         kvm_lapic_set_eoi(vcpu);
5081                         return kvm_skip_emulated_instruction(vcpu);
5082                 }
5083         }
5084         return kvm_emulate_instruction(vcpu, 0);
5085 }
5086
5087 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5088 {
5089         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5090         int vector = exit_qualification & 0xff;
5091
5092         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5093         kvm_apic_set_eoi_accelerated(vcpu, vector);
5094         return 1;
5095 }
5096
5097 static int handle_apic_write(struct kvm_vcpu *vcpu)
5098 {
5099         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5100         u32 offset = exit_qualification & 0xfff;
5101
5102         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5103         kvm_apic_write_nodecode(vcpu, offset);
5104         return 1;
5105 }
5106
5107 static int handle_task_switch(struct kvm_vcpu *vcpu)
5108 {
5109         struct vcpu_vmx *vmx = to_vmx(vcpu);
5110         unsigned long exit_qualification;
5111         bool has_error_code = false;
5112         u32 error_code = 0;
5113         u16 tss_selector;
5114         int reason, type, idt_v, idt_index;
5115
5116         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5117         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5118         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5119
5120         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5121
5122         reason = (u32)exit_qualification >> 30;
5123         if (reason == TASK_SWITCH_GATE && idt_v) {
5124                 switch (type) {
5125                 case INTR_TYPE_NMI_INTR:
5126                         vcpu->arch.nmi_injected = false;
5127                         vmx_set_nmi_mask(vcpu, true);
5128                         break;
5129                 case INTR_TYPE_EXT_INTR:
5130                 case INTR_TYPE_SOFT_INTR:
5131                         kvm_clear_interrupt_queue(vcpu);
5132                         break;
5133                 case INTR_TYPE_HARD_EXCEPTION:
5134                         if (vmx->idt_vectoring_info &
5135                             VECTORING_INFO_DELIVER_CODE_MASK) {
5136                                 has_error_code = true;
5137                                 error_code =
5138                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5139                         }
5140                         /* fall through */
5141                 case INTR_TYPE_SOFT_EXCEPTION:
5142                         kvm_clear_exception_queue(vcpu);
5143                         break;
5144                 default:
5145                         break;
5146                 }
5147         }
5148         tss_selector = exit_qualification;
5149
5150         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5151                        type != INTR_TYPE_EXT_INTR &&
5152                        type != INTR_TYPE_NMI_INTR))
5153                 WARN_ON(!skip_emulated_instruction(vcpu));
5154
5155         /*
5156          * TODO: What about debug traps on tss switch?
5157          *       Are we supposed to inject them and update dr6?
5158          */
5159         return kvm_task_switch(vcpu, tss_selector,
5160                                type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
5161                                reason, has_error_code, error_code);
5162 }
5163
5164 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5165 {
5166         unsigned long exit_qualification;
5167         gpa_t gpa;
5168         u64 error_code;
5169
5170         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5171
5172         /*
5173          * EPT violation happened while executing iret from NMI,
5174          * "blocked by NMI" bit has to be set before next VM entry.
5175          * There are errata that may cause this bit to not be set:
5176          * AAK134, BY25.
5177          */
5178         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5179                         enable_vnmi &&
5180                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5181                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5182
5183         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5184         trace_kvm_page_fault(gpa, exit_qualification);
5185
5186         /* Is it a read fault? */
5187         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
5188                      ? PFERR_USER_MASK : 0;
5189         /* Is it a write fault? */
5190         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
5191                       ? PFERR_WRITE_MASK : 0;
5192         /* Is it a fetch fault? */
5193         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
5194                       ? PFERR_FETCH_MASK : 0;
5195         /* ept page table entry is present? */
5196         error_code |= (exit_qualification &
5197                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5198                         EPT_VIOLATION_EXECUTABLE))
5199                       ? PFERR_PRESENT_MASK : 0;
5200
5201         error_code |= (exit_qualification & 0x100) != 0 ?
5202                PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
5203
5204         vcpu->arch.exit_qualification = exit_qualification;
5205         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5206 }
5207
5208 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5209 {
5210         gpa_t gpa;
5211
5212         /*
5213          * A nested guest cannot optimize MMIO vmexits, because we have an
5214          * nGPA here instead of the required GPA.
5215          */
5216         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5217         if (!is_guest_mode(vcpu) &&
5218             !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5219                 trace_kvm_fast_mmio(gpa);
5220                 return kvm_skip_emulated_instruction(vcpu);
5221         }
5222
5223         return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
5224 }
5225
5226 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5227 {
5228         WARN_ON_ONCE(!enable_vnmi);
5229         exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_NMI_PENDING);
5230         ++vcpu->stat.nmi_window_exits;
5231         kvm_make_request(KVM_REQ_EVENT, vcpu);
5232
5233         return 1;
5234 }
5235
5236 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5237 {
5238         struct vcpu_vmx *vmx = to_vmx(vcpu);
5239         bool intr_window_requested;
5240         unsigned count = 130;
5241
5242         /*
5243          * We should never reach the point where we are emulating L2
5244          * due to invalid guest state as that means we incorrectly
5245          * allowed a nested VMEntry with an invalid vmcs12.
5246          */
5247         WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
5248
5249         intr_window_requested = exec_controls_get(vmx) &
5250                                 CPU_BASED_VIRTUAL_INTR_PENDING;
5251
5252         while (vmx->emulation_required && count-- != 0) {
5253                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5254                         return handle_interrupt_window(&vmx->vcpu);
5255
5256                 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
5257                         return 1;
5258
5259                 if (!kvm_emulate_instruction(vcpu, 0))
5260                         return 0;
5261
5262                 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5263                     vcpu->arch.exception.pending) {
5264                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5265                         vcpu->run->internal.suberror =
5266                                                 KVM_INTERNAL_ERROR_EMULATION;
5267                         vcpu->run->internal.ndata = 0;
5268                         return 0;
5269                 }
5270
5271                 if (vcpu->arch.halt_request) {
5272                         vcpu->arch.halt_request = 0;
5273                         return kvm_vcpu_halt(vcpu);
5274                 }
5275
5276                 /*
5277                  * Note, return 1 and not 0, vcpu_run() is responsible for
5278                  * morphing the pending signal into the proper return code.
5279                  */
5280                 if (signal_pending(current))
5281                         return 1;
5282
5283                 if (need_resched())
5284                         schedule();
5285         }
5286
5287         return 1;
5288 }
5289
5290 static void grow_ple_window(struct kvm_vcpu *vcpu)
5291 {
5292         struct vcpu_vmx *vmx = to_vmx(vcpu);
5293         unsigned int old = vmx->ple_window;
5294
5295         vmx->ple_window = __grow_ple_window(old, ple_window,
5296                                             ple_window_grow,
5297                                             ple_window_max);
5298
5299         if (vmx->ple_window != old) {
5300                 vmx->ple_window_dirty = true;
5301                 trace_kvm_ple_window_update(vcpu->vcpu_id,
5302                                             vmx->ple_window, old);
5303         }
5304 }
5305
5306 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5307 {
5308         struct vcpu_vmx *vmx = to_vmx(vcpu);
5309         unsigned int old = vmx->ple_window;
5310
5311         vmx->ple_window = __shrink_ple_window(old, ple_window,
5312                                               ple_window_shrink,
5313                                               ple_window);
5314
5315         if (vmx->ple_window != old) {
5316                 vmx->ple_window_dirty = true;
5317                 trace_kvm_ple_window_update(vcpu->vcpu_id,
5318                                             vmx->ple_window, old);
5319         }
5320 }
5321
5322 /*
5323  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
5324  */
5325 static void wakeup_handler(void)
5326 {
5327         struct kvm_vcpu *vcpu;
5328         int cpu = smp_processor_id();
5329
5330         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5331         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
5332                         blocked_vcpu_list) {
5333                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
5334
5335                 if (pi_test_on(pi_desc) == 1)
5336                         kvm_vcpu_kick(vcpu);
5337         }
5338         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5339 }
5340
5341 static void vmx_enable_tdp(void)
5342 {
5343         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
5344                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
5345                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
5346                 0ull, VMX_EPT_EXECUTABLE_MASK,
5347                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
5348                 VMX_EPT_RWX_MASK, 0ull);
5349
5350         ept_set_mmio_spte_mask();
5351         kvm_enable_tdp();
5352 }
5353
5354 /*
5355  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5356  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5357  */
5358 static int handle_pause(struct kvm_vcpu *vcpu)
5359 {
5360         if (!kvm_pause_in_guest(vcpu->kvm))
5361                 grow_ple_window(vcpu);
5362
5363         /*
5364          * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5365          * VM-execution control is ignored if CPL > 0. OTOH, KVM
5366          * never set PAUSE_EXITING and just set PLE if supported,
5367          * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5368          */
5369         kvm_vcpu_on_spin(vcpu, true);
5370         return kvm_skip_emulated_instruction(vcpu);
5371 }
5372
5373 static int handle_nop(struct kvm_vcpu *vcpu)
5374 {
5375         return kvm_skip_emulated_instruction(vcpu);
5376 }
5377
5378 static int handle_mwait(struct kvm_vcpu *vcpu)
5379 {
5380         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5381         return handle_nop(vcpu);
5382 }
5383
5384 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5385 {
5386         kvm_queue_exception(vcpu, UD_VECTOR);
5387         return 1;
5388 }
5389
5390 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5391 {
5392         return 1;
5393 }
5394
5395 static int handle_monitor(struct kvm_vcpu *vcpu)
5396 {
5397         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5398         return handle_nop(vcpu);
5399 }
5400
5401 static int handle_invpcid(struct kvm_vcpu *vcpu)
5402 {
5403         u32 vmx_instruction_info;
5404         unsigned long type;
5405         bool pcid_enabled;
5406         gva_t gva;
5407         struct x86_exception e;
5408         unsigned i;
5409         unsigned long roots_to_free = 0;
5410         struct {
5411                 u64 pcid;
5412                 u64 gla;
5413         } operand;
5414
5415         if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
5416                 kvm_queue_exception(vcpu, UD_VECTOR);
5417                 return 1;
5418         }
5419
5420         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5421         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5422
5423         if (type > 3) {
5424                 kvm_inject_gp(vcpu, 0);
5425                 return 1;
5426         }
5427
5428         /* According to the Intel instruction reference, the memory operand
5429          * is read even if it isn't needed (e.g., for type==all)
5430          */
5431         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5432                                 vmx_instruction_info, false,
5433                                 sizeof(operand), &gva))
5434                 return 1;
5435
5436         if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
5437                 kvm_inject_page_fault(vcpu, &e);
5438                 return 1;
5439         }
5440
5441         if (operand.pcid >> 12 != 0) {
5442                 kvm_inject_gp(vcpu, 0);
5443                 return 1;
5444         }
5445
5446         pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
5447
5448         switch (type) {
5449         case INVPCID_TYPE_INDIV_ADDR:
5450                 if ((!pcid_enabled && (operand.pcid != 0)) ||
5451                     is_noncanonical_address(operand.gla, vcpu)) {
5452                         kvm_inject_gp(vcpu, 0);
5453                         return 1;
5454                 }
5455                 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
5456                 return kvm_skip_emulated_instruction(vcpu);
5457
5458         case INVPCID_TYPE_SINGLE_CTXT:
5459                 if (!pcid_enabled && (operand.pcid != 0)) {
5460                         kvm_inject_gp(vcpu, 0);
5461                         return 1;
5462                 }
5463
5464                 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
5465                         kvm_mmu_sync_roots(vcpu);
5466                         kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
5467                 }
5468
5469                 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5470                         if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3)
5471                             == operand.pcid)
5472                                 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
5473
5474                 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
5475                 /*
5476                  * If neither the current cr3 nor any of the prev_roots use the
5477                  * given PCID, then nothing needs to be done here because a
5478                  * resync will happen anyway before switching to any other CR3.
5479                  */
5480
5481                 return kvm_skip_emulated_instruction(vcpu);
5482
5483         case INVPCID_TYPE_ALL_NON_GLOBAL:
5484                 /*
5485                  * Currently, KVM doesn't mark global entries in the shadow
5486                  * page tables, so a non-global flush just degenerates to a
5487                  * global flush. If needed, we could optimize this later by
5488                  * keeping track of global entries in shadow page tables.
5489                  */
5490
5491                 /* fall-through */
5492         case INVPCID_TYPE_ALL_INCL_GLOBAL:
5493                 kvm_mmu_unload(vcpu);
5494                 return kvm_skip_emulated_instruction(vcpu);
5495
5496         default:
5497                 BUG(); /* We have already checked above that type <= 3 */
5498         }
5499 }
5500
5501 static int handle_pml_full(struct kvm_vcpu *vcpu)
5502 {
5503         unsigned long exit_qualification;
5504
5505         trace_kvm_pml_full(vcpu->vcpu_id);
5506
5507         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5508
5509         /*
5510          * PML buffer FULL happened while executing iret from NMI,
5511          * "blocked by NMI" bit has to be set before next VM entry.
5512          */
5513         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5514                         enable_vnmi &&
5515                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5516                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5517                                 GUEST_INTR_STATE_NMI);
5518
5519         /*
5520          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5521          * here.., and there's no userspace involvement needed for PML.
5522          */
5523         return 1;
5524 }
5525
5526 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
5527 {
5528         struct vcpu_vmx *vmx = to_vmx(vcpu);
5529
5530         if (!vmx->req_immediate_exit &&
5531             !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled))
5532                 kvm_lapic_expired_hv_timer(vcpu);
5533
5534         return 1;
5535 }
5536
5537 /*
5538  * When nested=0, all VMX instruction VM Exits filter here.  The handlers
5539  * are overwritten by nested_vmx_setup() when nested=1.
5540  */
5541 static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
5542 {
5543         kvm_queue_exception(vcpu, UD_VECTOR);
5544         return 1;
5545 }
5546
5547 static int handle_encls(struct kvm_vcpu *vcpu)
5548 {
5549         /*
5550          * SGX virtualization is not yet supported.  There is no software
5551          * enable bit for SGX, so we have to trap ENCLS and inject a #UD
5552          * to prevent the guest from executing ENCLS.
5553          */
5554         kvm_queue_exception(vcpu, UD_VECTOR);
5555         return 1;
5556 }
5557
5558 /*
5559  * The exit handlers return 1 if the exit was handled fully and guest execution
5560  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5561  * to be done to userspace and return 0.
5562  */
5563 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5564         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception_nmi,
5565         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5566         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5567         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5568         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5569         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5570         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5571         [EXIT_REASON_CPUID]                   = handle_cpuid,
5572         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
5573         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
5574         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
5575         [EXIT_REASON_HLT]                     = handle_halt,
5576         [EXIT_REASON_INVD]                    = handle_invd,
5577         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5578         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
5579         [EXIT_REASON_VMCALL]                  = handle_vmcall,
5580         [EXIT_REASON_VMCLEAR]                 = handle_vmx_instruction,
5581         [EXIT_REASON_VMLAUNCH]                = handle_vmx_instruction,
5582         [EXIT_REASON_VMPTRLD]                 = handle_vmx_instruction,
5583         [EXIT_REASON_VMPTRST]                 = handle_vmx_instruction,
5584         [EXIT_REASON_VMREAD]                  = handle_vmx_instruction,
5585         [EXIT_REASON_VMRESUME]                = handle_vmx_instruction,
5586         [EXIT_REASON_VMWRITE]                 = handle_vmx_instruction,
5587         [EXIT_REASON_VMOFF]                   = handle_vmx_instruction,
5588         [EXIT_REASON_VMON]                    = handle_vmx_instruction,
5589         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5590         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5591         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
5592         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
5593         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
5594         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
5595         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5596         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5597         [EXIT_REASON_GDTR_IDTR]               = handle_desc,
5598         [EXIT_REASON_LDTR_TR]                 = handle_desc,
5599         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5600         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5601         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5602         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
5603         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
5604         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
5605         [EXIT_REASON_INVEPT]                  = handle_vmx_instruction,
5606         [EXIT_REASON_INVVPID]                 = handle_vmx_instruction,
5607         [EXIT_REASON_RDRAND]                  = handle_invalid_op,
5608         [EXIT_REASON_RDSEED]                  = handle_invalid_op,
5609         [EXIT_REASON_PML_FULL]                = handle_pml_full,
5610         [EXIT_REASON_INVPCID]                 = handle_invpcid,
5611         [EXIT_REASON_VMFUNC]                  = handle_vmx_instruction,
5612         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
5613         [EXIT_REASON_ENCLS]                   = handle_encls,
5614 };
5615
5616 static const int kvm_vmx_max_exit_handlers =
5617         ARRAY_SIZE(kvm_vmx_exit_handlers);
5618
5619 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5620 {
5621         *info1 = vmcs_readl(EXIT_QUALIFICATION);
5622         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5623 }
5624
5625 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
5626 {
5627         if (vmx->pml_pg) {
5628                 __free_page(vmx->pml_pg);
5629                 vmx->pml_pg = NULL;
5630         }
5631 }
5632
5633 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
5634 {
5635         struct vcpu_vmx *vmx = to_vmx(vcpu);
5636         u64 *pml_buf;
5637         u16 pml_idx;
5638
5639         pml_idx = vmcs_read16(GUEST_PML_INDEX);
5640
5641         /* Do nothing if PML buffer is empty */
5642         if (pml_idx == (PML_ENTITY_NUM - 1))
5643                 return;
5644
5645         /* PML index always points to next available PML buffer entity */
5646         if (pml_idx >= PML_ENTITY_NUM)
5647                 pml_idx = 0;
5648         else
5649                 pml_idx++;
5650
5651         pml_buf = page_address(vmx->pml_pg);
5652         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5653                 u64 gpa;
5654
5655                 gpa = pml_buf[pml_idx];
5656                 WARN_ON(gpa & (PAGE_SIZE - 1));
5657                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5658         }
5659
5660         /* reset PML index */
5661         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5662 }
5663
5664 /*
5665  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
5666  * Called before reporting dirty_bitmap to userspace.
5667  */
5668 static void kvm_flush_pml_buffers(struct kvm *kvm)
5669 {
5670         int i;
5671         struct kvm_vcpu *vcpu;
5672         /*
5673          * We only need to kick vcpu out of guest mode here, as PML buffer
5674          * is flushed at beginning of all VMEXITs, and it's obvious that only
5675          * vcpus running in guest are possible to have unflushed GPAs in PML
5676          * buffer.
5677          */
5678         kvm_for_each_vcpu(i, vcpu, kvm)
5679                 kvm_vcpu_kick(vcpu);
5680 }
5681
5682 static void vmx_dump_sel(char *name, uint32_t sel)
5683 {
5684         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5685                name, vmcs_read16(sel),
5686                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5687                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5688                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
5689 }
5690
5691 static void vmx_dump_dtsel(char *name, uint32_t limit)
5692 {
5693         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
5694                name, vmcs_read32(limit),
5695                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
5696 }
5697
5698 void dump_vmcs(void)
5699 {
5700         u32 vmentry_ctl, vmexit_ctl;
5701         u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5702         unsigned long cr4;
5703         u64 efer;
5704         int i, n;
5705
5706         if (!dump_invalid_vmcs) {
5707                 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5708                 return;
5709         }
5710
5711         vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5712         vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5713         cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5714         pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5715         cr4 = vmcs_readl(GUEST_CR4);
5716         efer = vmcs_read64(GUEST_IA32_EFER);
5717         secondary_exec_control = 0;
5718         if (cpu_has_secondary_exec_ctrls())
5719                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5720
5721         pr_err("*** Guest State ***\n");
5722         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5723                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5724                vmcs_readl(CR0_GUEST_HOST_MASK));
5725         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5726                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5727         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5728         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
5729             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
5730         {
5731                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
5732                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5733                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
5734                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
5735         }
5736         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
5737                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5738         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
5739                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5740         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5741                vmcs_readl(GUEST_SYSENTER_ESP),
5742                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5743         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
5744         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
5745         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
5746         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
5747         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
5748         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
5749         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5750         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5751         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5752         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
5753         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
5754             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
5755                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
5756                        efer, vmcs_read64(GUEST_IA32_PAT));
5757         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
5758                vmcs_read64(GUEST_IA32_DEBUGCTL),
5759                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5760         if (cpu_has_load_perf_global_ctrl() &&
5761             vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5762                 pr_err("PerfGlobCtl = 0x%016llx\n",
5763                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5764         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5765                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5766         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
5767                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5768                vmcs_read32(GUEST_ACTIVITY_STATE));
5769         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5770                 pr_err("InterruptStatus = %04x\n",
5771                        vmcs_read16(GUEST_INTR_STATUS));
5772
5773         pr_err("*** Host State ***\n");
5774         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
5775                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5776         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5777                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5778                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5779                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5780                vmcs_read16(HOST_TR_SELECTOR));
5781         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5782                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5783                vmcs_readl(HOST_TR_BASE));
5784         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5785                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5786         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5787                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5788                vmcs_readl(HOST_CR4));
5789         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5790                vmcs_readl(HOST_IA32_SYSENTER_ESP),
5791                vmcs_read32(HOST_IA32_SYSENTER_CS),
5792                vmcs_readl(HOST_IA32_SYSENTER_EIP));
5793         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
5794                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
5795                        vmcs_read64(HOST_IA32_EFER),
5796                        vmcs_read64(HOST_IA32_PAT));
5797         if (cpu_has_load_perf_global_ctrl() &&
5798             vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5799                 pr_err("PerfGlobCtl = 0x%016llx\n",
5800                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
5801
5802         pr_err("*** Control State ***\n");
5803         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5804                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5805         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5806         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5807                vmcs_read32(EXCEPTION_BITMAP),
5808                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5809                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5810         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5811                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5812                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5813                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5814         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5815                vmcs_read32(VM_EXIT_INTR_INFO),
5816                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5817                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5818         pr_err("        reason=%08x qualification=%016lx\n",
5819                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5820         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5821                vmcs_read32(IDT_VECTORING_INFO_FIELD),
5822                vmcs_read32(IDT_VECTORING_ERROR_CODE));
5823         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5824         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5825                 pr_err("TSC Multiplier = 0x%016llx\n",
5826                        vmcs_read64(TSC_MULTIPLIER));
5827         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5828                 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5829                         u16 status = vmcs_read16(GUEST_INTR_STATUS);
5830                         pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5831                 }
5832                 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
5833                 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5834                         pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
5835                 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
5836         }
5837         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5838                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5839         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5840                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5841         n = vmcs_read32(CR3_TARGET_COUNT);
5842         for (i = 0; i + 1 < n; i += 4)
5843                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
5844                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
5845                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
5846         if (i < n)
5847                 pr_err("CR3 target%u=%016lx\n",
5848                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
5849         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5850                 pr_err("PLE Gap=%08x Window=%08x\n",
5851                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5852         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5853                 pr_err("Virtual processor ID = 0x%04x\n",
5854                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
5855 }
5856
5857 /*
5858  * The guest has exited.  See if we can fix it or if we need userspace
5859  * assistance.
5860  */
5861 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5862 {
5863         struct vcpu_vmx *vmx = to_vmx(vcpu);
5864         u32 exit_reason = vmx->exit_reason;
5865         u32 vectoring_info = vmx->idt_vectoring_info;
5866
5867         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
5868
5869         /*
5870          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5871          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5872          * querying dirty_bitmap, we only need to kick all vcpus out of guest
5873          * mode as if vcpus is in root mode, the PML buffer must has been
5874          * flushed already.
5875          */
5876         if (enable_pml)
5877                 vmx_flush_pml_buffer(vcpu);
5878
5879         /* If guest state is invalid, start emulating */
5880         if (vmx->emulation_required)
5881                 return handle_invalid_guest_state(vcpu);
5882
5883         if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
5884                 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
5885
5886         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5887                 dump_vmcs();
5888                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5889                 vcpu->run->fail_entry.hardware_entry_failure_reason
5890                         = exit_reason;
5891                 return 0;
5892         }
5893
5894         if (unlikely(vmx->fail)) {
5895                 dump_vmcs();
5896                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5897                 vcpu->run->fail_entry.hardware_entry_failure_reason
5898                         = vmcs_read32(VM_INSTRUCTION_ERROR);
5899                 return 0;
5900         }
5901
5902         /*
5903          * Note:
5904          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5905          * delivery event since it indicates guest is accessing MMIO.
5906          * The vm-exit can be triggered again after return to guest that
5907          * will cause infinite loop.
5908          */
5909         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5910                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5911                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
5912                         exit_reason != EXIT_REASON_PML_FULL &&
5913                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
5914                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5915                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5916                 vcpu->run->internal.ndata = 3;
5917                 vcpu->run->internal.data[0] = vectoring_info;
5918                 vcpu->run->internal.data[1] = exit_reason;
5919                 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5920                 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
5921                         vcpu->run->internal.ndata++;
5922                         vcpu->run->internal.data[3] =
5923                                 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5924                 }
5925                 return 0;
5926         }
5927
5928         if (unlikely(!enable_vnmi &&
5929                      vmx->loaded_vmcs->soft_vnmi_blocked)) {
5930                 if (vmx_interrupt_allowed(vcpu)) {
5931                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5932                 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5933                            vcpu->arch.nmi_pending) {
5934                         /*
5935                          * This CPU don't support us in finding the end of an
5936                          * NMI-blocked window if the guest runs with IRQs
5937                          * disabled. So we pull the trigger after 1 s of
5938                          * futile waiting, but inform the user about this.
5939                          */
5940                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5941                                "state on VCPU %d after 1 s timeout\n",
5942                                __func__, vcpu->vcpu_id);
5943                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5944                 }
5945         }
5946
5947         if (exit_reason < kvm_vmx_max_exit_handlers
5948             && kvm_vmx_exit_handlers[exit_reason])
5949                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5950         else {
5951                 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
5952                                 exit_reason);
5953                 dump_vmcs();
5954                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5955                 vcpu->run->internal.suberror =
5956                         KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
5957                 vcpu->run->internal.ndata = 1;
5958                 vcpu->run->internal.data[0] = exit_reason;
5959                 return 0;
5960         }
5961 }
5962
5963 /*
5964  * Software based L1D cache flush which is used when microcode providing
5965  * the cache control MSR is not loaded.
5966  *
5967  * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
5968  * flush it is required to read in 64 KiB because the replacement algorithm
5969  * is not exactly LRU. This could be sized at runtime via topology
5970  * information but as all relevant affected CPUs have 32KiB L1D cache size
5971  * there is no point in doing so.
5972  */
5973 static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
5974 {
5975         int size = PAGE_SIZE << L1D_CACHE_ORDER;
5976
5977         /*
5978          * This code is only executed when the the flush mode is 'cond' or
5979          * 'always'
5980          */
5981         if (static_branch_likely(&vmx_l1d_flush_cond)) {
5982                 bool flush_l1d;
5983
5984                 /*
5985                  * Clear the per-vcpu flush bit, it gets set again
5986                  * either from vcpu_run() or from one of the unsafe
5987                  * VMEXIT handlers.
5988                  */
5989                 flush_l1d = vcpu->arch.l1tf_flush_l1d;
5990                 vcpu->arch.l1tf_flush_l1d = false;
5991
5992                 /*
5993                  * Clear the per-cpu flush bit, it gets set again from
5994                  * the interrupt handlers.
5995                  */
5996                 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
5997                 kvm_clear_cpu_l1tf_flush_l1d();
5998
5999                 if (!flush_l1d)
6000                         return;
6001         }
6002
6003         vcpu->stat.l1d_flush++;
6004
6005         if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
6006                 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
6007                 return;
6008         }
6009
6010         asm volatile(
6011                 /* First ensure the pages are in the TLB */
6012                 "xorl   %%eax, %%eax\n"
6013                 ".Lpopulate_tlb:\n\t"
6014                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6015                 "addl   $4096, %%eax\n\t"
6016                 "cmpl   %%eax, %[size]\n\t"
6017                 "jne    .Lpopulate_tlb\n\t"
6018                 "xorl   %%eax, %%eax\n\t"
6019                 "cpuid\n\t"
6020                 /* Now fill the cache */
6021                 "xorl   %%eax, %%eax\n"
6022                 ".Lfill_cache:\n"
6023                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6024                 "addl   $64, %%eax\n\t"
6025                 "cmpl   %%eax, %[size]\n\t"
6026                 "jne    .Lfill_cache\n\t"
6027                 "lfence\n"
6028                 :: [flush_pages] "r" (vmx_l1d_flush_pages),
6029                     [size] "r" (size)
6030                 : "eax", "ebx", "ecx", "edx");
6031 }
6032
6033 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6034 {
6035         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6036
6037         if (is_guest_mode(vcpu) &&
6038                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
6039                 return;
6040
6041         if (irr == -1 || tpr < irr) {
6042                 vmcs_write32(TPR_THRESHOLD, 0);
6043                 return;
6044         }
6045
6046         vmcs_write32(TPR_THRESHOLD, irr);
6047 }
6048
6049 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
6050 {
6051         struct vcpu_vmx *vmx = to_vmx(vcpu);
6052         u32 sec_exec_control;
6053
6054         if (!lapic_in_kernel(vcpu))
6055                 return;
6056
6057         if (!flexpriority_enabled &&
6058             !cpu_has_vmx_virtualize_x2apic_mode())
6059                 return;
6060
6061         /* Postpone execution until vmcs01 is the current VMCS. */
6062         if (is_guest_mode(vcpu)) {
6063                 vmx->nested.change_vmcs01_virtual_apic_mode = true;
6064                 return;
6065         }
6066
6067         sec_exec_control = secondary_exec_controls_get(vmx);
6068         sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6069                               SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
6070
6071         switch (kvm_get_apic_mode(vcpu)) {
6072         case LAPIC_MODE_INVALID:
6073                 WARN_ONCE(true, "Invalid local APIC state");
6074         case LAPIC_MODE_DISABLED:
6075                 break;
6076         case LAPIC_MODE_XAPIC:
6077                 if (flexpriority_enabled) {
6078                         sec_exec_control |=
6079                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6080                         vmx_flush_tlb(vcpu, true);
6081                 }
6082                 break;
6083         case LAPIC_MODE_X2APIC:
6084                 if (cpu_has_vmx_virtualize_x2apic_mode())
6085                         sec_exec_control |=
6086                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6087                 break;
6088         }
6089         secondary_exec_controls_set(vmx, sec_exec_control);
6090
6091         vmx_update_msr_bitmap(vcpu);
6092 }
6093
6094 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
6095 {
6096         if (!is_guest_mode(vcpu)) {
6097                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
6098                 vmx_flush_tlb(vcpu, true);
6099         }
6100 }
6101
6102 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6103 {
6104         u16 status;
6105         u8 old;
6106
6107         if (max_isr == -1)
6108                 max_isr = 0;
6109
6110         status = vmcs_read16(GUEST_INTR_STATUS);
6111         old = status >> 8;
6112         if (max_isr != old) {
6113                 status &= 0xff;
6114                 status |= max_isr << 8;
6115                 vmcs_write16(GUEST_INTR_STATUS, status);
6116         }
6117 }
6118
6119 static void vmx_set_rvi(int vector)
6120 {
6121         u16 status;
6122         u8 old;
6123
6124         if (vector == -1)
6125                 vector = 0;
6126
6127         status = vmcs_read16(GUEST_INTR_STATUS);
6128         old = (u8)status & 0xff;
6129         if ((u8)vector != old) {
6130                 status &= ~0xff;
6131                 status |= (u8)vector;
6132                 vmcs_write16(GUEST_INTR_STATUS, status);
6133         }
6134 }
6135
6136 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6137 {
6138         /*
6139          * When running L2, updating RVI is only relevant when
6140          * vmcs12 virtual-interrupt-delivery enabled.
6141          * However, it can be enabled only when L1 also
6142          * intercepts external-interrupts and in that case
6143          * we should not update vmcs02 RVI but instead intercept
6144          * interrupt. Therefore, do nothing when running L2.
6145          */
6146         if (!is_guest_mode(vcpu))
6147                 vmx_set_rvi(max_irr);
6148 }
6149
6150 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6151 {
6152         struct vcpu_vmx *vmx = to_vmx(vcpu);
6153         int max_irr;
6154         bool max_irr_updated;
6155
6156         WARN_ON(!vcpu->arch.apicv_active);
6157         if (pi_test_on(&vmx->pi_desc)) {
6158                 pi_clear_on(&vmx->pi_desc);
6159                 /*
6160                  * IOMMU can write to PID.ON, so the barrier matters even on UP.
6161                  * But on x86 this is just a compiler barrier anyway.
6162                  */
6163                 smp_mb__after_atomic();
6164                 max_irr_updated =
6165                         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
6166
6167                 /*
6168                  * If we are running L2 and L1 has a new pending interrupt
6169                  * which can be injected, we should re-evaluate
6170                  * what should be done with this new L1 interrupt.
6171                  * If L1 intercepts external-interrupts, we should
6172                  * exit from L2 to L1. Otherwise, interrupt should be
6173                  * delivered directly to L2.
6174                  */
6175                 if (is_guest_mode(vcpu) && max_irr_updated) {
6176                         if (nested_exit_on_intr(vcpu))
6177                                 kvm_vcpu_exiting_guest_mode(vcpu);
6178                         else
6179                                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6180                 }
6181         } else {
6182                 max_irr = kvm_lapic_find_highest_irr(vcpu);
6183         }
6184         vmx_hwapic_irr_update(vcpu, max_irr);
6185         return max_irr;
6186 }
6187
6188 static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
6189 {
6190         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6191
6192         return pi_test_on(pi_desc) ||
6193                 (pi_test_sn(pi_desc) && !pi_is_pir_empty(pi_desc));
6194 }
6195
6196 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6197 {
6198         if (!kvm_vcpu_apicv_active(vcpu))
6199                 return;
6200
6201         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6202         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6203         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6204         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6205 }
6206
6207 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
6208 {
6209         struct vcpu_vmx *vmx = to_vmx(vcpu);
6210
6211         pi_clear_on(&vmx->pi_desc);
6212         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6213 }
6214
6215 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
6216 {
6217         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6218
6219         /* if exit due to PF check for async PF */
6220         if (is_page_fault(vmx->exit_intr_info))
6221                 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
6222
6223         /* Handle machine checks before interrupts are enabled */
6224         if (is_machine_check(vmx->exit_intr_info))
6225                 kvm_machine_check();
6226
6227         /* We need to handle NMIs before interrupts are enabled */
6228         if (is_nmi(vmx->exit_intr_info)) {
6229                 kvm_before_interrupt(&vmx->vcpu);
6230                 asm("int $2");
6231                 kvm_after_interrupt(&vmx->vcpu);
6232         }
6233 }
6234
6235 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
6236 {
6237         unsigned int vector;
6238         unsigned long entry;
6239 #ifdef CONFIG_X86_64
6240         unsigned long tmp;
6241 #endif
6242         gate_desc *desc;
6243         u32 intr_info;
6244
6245         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6246         if (WARN_ONCE(!is_external_intr(intr_info),
6247             "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6248                 return;
6249
6250         vector = intr_info & INTR_INFO_VECTOR_MASK;
6251         desc = (gate_desc *)host_idt_base + vector;
6252         entry = gate_offset(desc);
6253
6254         kvm_before_interrupt(vcpu);
6255
6256         asm volatile(
6257 #ifdef CONFIG_X86_64
6258                 "mov %%" _ASM_SP ", %[sp]\n\t"
6259                 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6260                 "push $%c[ss]\n\t"
6261                 "push %[sp]\n\t"
6262 #endif
6263                 "pushf\n\t"
6264                 __ASM_SIZE(push) " $%c[cs]\n\t"
6265                 CALL_NOSPEC
6266                 :
6267 #ifdef CONFIG_X86_64
6268                 [sp]"=&r"(tmp),
6269 #endif
6270                 ASM_CALL_CONSTRAINT
6271                 :
6272                 THUNK_TARGET(entry),
6273                 [ss]"i"(__KERNEL_DS),
6274                 [cs]"i"(__KERNEL_CS)
6275         );
6276
6277         kvm_after_interrupt(vcpu);
6278 }
6279 STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff);
6280
6281 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu)
6282 {
6283         struct vcpu_vmx *vmx = to_vmx(vcpu);
6284
6285         if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
6286                 handle_external_interrupt_irqoff(vcpu);
6287         else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)
6288                 handle_exception_nmi_irqoff(vmx);
6289 }
6290
6291 static bool vmx_has_emulated_msr(int index)
6292 {
6293         switch (index) {
6294         case MSR_IA32_SMBASE:
6295                 /*
6296                  * We cannot do SMM unless we can run the guest in big
6297                  * real mode.
6298                  */
6299                 return enable_unrestricted_guest || emulate_invalid_guest_state;
6300         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6301                 return nested;
6302         case MSR_AMD64_VIRT_SPEC_CTRL:
6303                 /* This is AMD only.  */
6304                 return false;
6305         default:
6306                 return true;
6307         }
6308 }
6309
6310 static bool vmx_pt_supported(void)
6311 {
6312         return pt_mode == PT_MODE_HOST_GUEST;
6313 }
6314
6315 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6316 {
6317         u32 exit_intr_info;
6318         bool unblock_nmi;
6319         u8 vector;
6320         bool idtv_info_valid;
6321
6322         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6323
6324         if (enable_vnmi) {
6325                 if (vmx->loaded_vmcs->nmi_known_unmasked)
6326                         return;
6327                 /*
6328                  * Can't use vmx->exit_intr_info since we're not sure what
6329                  * the exit reason is.
6330                  */
6331                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6332                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6333                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6334                 /*
6335                  * SDM 3: 27.7.1.2 (September 2008)
6336                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6337                  * a guest IRET fault.
6338                  * SDM 3: 23.2.2 (September 2008)
6339                  * Bit 12 is undefined in any of the following cases:
6340                  *  If the VM exit sets the valid bit in the IDT-vectoring
6341                  *   information field.
6342                  *  If the VM exit is due to a double fault.
6343                  */
6344                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6345                     vector != DF_VECTOR && !idtv_info_valid)
6346                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6347                                       GUEST_INTR_STATE_NMI);
6348                 else
6349                         vmx->loaded_vmcs->nmi_known_unmasked =
6350                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6351                                   & GUEST_INTR_STATE_NMI);
6352         } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6353                 vmx->loaded_vmcs->vnmi_blocked_time +=
6354                         ktime_to_ns(ktime_sub(ktime_get(),
6355                                               vmx->loaded_vmcs->entry_time));
6356 }
6357
6358 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6359                                       u32 idt_vectoring_info,
6360                                       int instr_len_field,
6361                                       int error_code_field)
6362 {
6363         u8 vector;
6364         int type;
6365         bool idtv_info_valid;
6366
6367         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6368
6369         vcpu->arch.nmi_injected = false;
6370         kvm_clear_exception_queue(vcpu);
6371         kvm_clear_interrupt_queue(vcpu);
6372
6373         if (!idtv_info_valid)
6374                 return;
6375
6376         kvm_make_request(KVM_REQ_EVENT, vcpu);
6377
6378         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6379         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6380
6381         switch (type) {
6382         case INTR_TYPE_NMI_INTR:
6383                 vcpu->arch.nmi_injected = true;
6384                 /*
6385                  * SDM 3: 27.7.1.2 (September 2008)
6386                  * Clear bit "block by NMI" before VM entry if a NMI
6387                  * delivery faulted.
6388                  */
6389                 vmx_set_nmi_mask(vcpu, false);
6390                 break;
6391         case INTR_TYPE_SOFT_EXCEPTION:
6392                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6393                 /* fall through */
6394         case INTR_TYPE_HARD_EXCEPTION:
6395                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6396                         u32 err = vmcs_read32(error_code_field);
6397                         kvm_requeue_exception_e(vcpu, vector, err);
6398                 } else
6399                         kvm_requeue_exception(vcpu, vector);
6400                 break;
6401         case INTR_TYPE_SOFT_INTR:
6402                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6403                 /* fall through */
6404         case INTR_TYPE_EXT_INTR:
6405                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6406                 break;
6407         default:
6408                 break;
6409         }
6410 }
6411
6412 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6413 {
6414         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6415                                   VM_EXIT_INSTRUCTION_LEN,
6416                                   IDT_VECTORING_ERROR_CODE);
6417 }
6418
6419 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6420 {
6421         __vmx_complete_interrupts(vcpu,
6422                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6423                                   VM_ENTRY_INSTRUCTION_LEN,
6424                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6425
6426         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6427 }
6428
6429 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6430 {
6431         int i, nr_msrs;
6432         struct perf_guest_switch_msr *msrs;
6433
6434         msrs = perf_guest_get_msrs(&nr_msrs);
6435
6436         if (!msrs)
6437                 return;
6438
6439         for (i = 0; i < nr_msrs; i++)
6440                 if (msrs[i].host == msrs[i].guest)
6441                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6442                 else
6443                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6444                                         msrs[i].host, false);
6445 }
6446
6447 static void atomic_switch_umwait_control_msr(struct vcpu_vmx *vmx)
6448 {
6449         u32 host_umwait_control;
6450
6451         if (!vmx_has_waitpkg(vmx))
6452                 return;
6453
6454         host_umwait_control = get_umwait_control_msr();
6455
6456         if (vmx->msr_ia32_umwait_control != host_umwait_control)
6457                 add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL,
6458                         vmx->msr_ia32_umwait_control,
6459                         host_umwait_control, false);
6460         else
6461                 clear_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL);
6462 }
6463
6464 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
6465 {
6466         struct vcpu_vmx *vmx = to_vmx(vcpu);
6467         u64 tscl;
6468         u32 delta_tsc;
6469
6470         if (vmx->req_immediate_exit) {
6471                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6472                 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6473         } else if (vmx->hv_deadline_tsc != -1) {
6474                 tscl = rdtsc();
6475                 if (vmx->hv_deadline_tsc > tscl)
6476                         /* set_hv_timer ensures the delta fits in 32-bits */
6477                         delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6478                                 cpu_preemption_timer_multi);
6479                 else
6480                         delta_tsc = 0;
6481
6482                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6483                 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6484         } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6485                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6486                 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
6487         }
6488 }
6489
6490 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
6491 {
6492         if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6493                 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6494                 vmcs_writel(HOST_RSP, host_rsp);
6495         }
6496 }
6497
6498 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched);
6499
6500 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6501 {
6502         struct vcpu_vmx *vmx = to_vmx(vcpu);
6503         unsigned long cr3, cr4;
6504
6505         /* Record the guest's net vcpu time for enforced NMI injections. */
6506         if (unlikely(!enable_vnmi &&
6507                      vmx->loaded_vmcs->soft_vnmi_blocked))
6508                 vmx->loaded_vmcs->entry_time = ktime_get();
6509
6510         /* Don't enter VMX if guest state is invalid, let the exit handler
6511            start emulation until we arrive back to a valid state */
6512         if (vmx->emulation_required)
6513                 return;
6514
6515         if (vmx->ple_window_dirty) {
6516                 vmx->ple_window_dirty = false;
6517                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6518         }
6519
6520         if (vmx->nested.need_vmcs12_to_shadow_sync)
6521                 nested_sync_vmcs12_to_shadow(vcpu);
6522
6523         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6524                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6525         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6526                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6527
6528         cr3 = __get_current_cr3_fast();
6529         if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6530                 vmcs_writel(HOST_CR3, cr3);
6531                 vmx->loaded_vmcs->host_state.cr3 = cr3;
6532         }
6533
6534         cr4 = cr4_read_shadow();
6535         if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6536                 vmcs_writel(HOST_CR4, cr4);
6537                 vmx->loaded_vmcs->host_state.cr4 = cr4;
6538         }
6539
6540         /* When single-stepping over STI and MOV SS, we must clear the
6541          * corresponding interruptibility bits in the guest state. Otherwise
6542          * vmentry fails as it then expects bit 14 (BS) in pending debug
6543          * exceptions being set, but that's not correct for the guest debugging
6544          * case. */
6545         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6546                 vmx_set_interrupt_shadow(vcpu, 0);
6547
6548         kvm_load_guest_xcr0(vcpu);
6549
6550         if (static_cpu_has(X86_FEATURE_PKU) &&
6551             kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
6552             vcpu->arch.pkru != vmx->host_pkru)
6553                 __write_pkru(vcpu->arch.pkru);
6554
6555         pt_guest_enter(vmx);
6556
6557         atomic_switch_perf_msrs(vmx);
6558         atomic_switch_umwait_control_msr(vmx);
6559
6560         if (enable_preemption_timer)
6561                 vmx_update_hv_timer(vcpu);
6562
6563         if (lapic_in_kernel(vcpu) &&
6564                 vcpu->arch.apic->lapic_timer.timer_advance_ns)
6565                 kvm_wait_lapic_expire(vcpu);
6566
6567         /*
6568          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6569          * it's non-zero. Since vmentry is serialising on affected CPUs, there
6570          * is no need to worry about the conditional branch over the wrmsr
6571          * being speculatively taken.
6572          */
6573         x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6574
6575         /* L1D Flush includes CPU buffer clear to mitigate MDS */
6576         if (static_branch_unlikely(&vmx_l1d_should_flush))
6577                 vmx_l1d_flush(vcpu);
6578         else if (static_branch_unlikely(&mds_user_clear))
6579                 mds_clear_cpu_buffers();
6580
6581         if (vcpu->arch.cr2 != read_cr2())
6582                 write_cr2(vcpu->arch.cr2);
6583
6584         vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6585                                    vmx->loaded_vmcs->launched);
6586
6587         vcpu->arch.cr2 = read_cr2();
6588
6589         /*
6590          * We do not use IBRS in the kernel. If this vCPU has used the
6591          * SPEC_CTRL MSR it may have left it on; save the value and
6592          * turn it off. This is much more efficient than blindly adding
6593          * it to the atomic save/restore list. Especially as the former
6594          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6595          *
6596          * For non-nested case:
6597          * If the L01 MSR bitmap does not intercept the MSR, then we need to
6598          * save it.
6599          *
6600          * For nested case:
6601          * If the L02 MSR bitmap does not intercept the MSR, then we need to
6602          * save it.
6603          */
6604         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6605                 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
6606
6607         x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
6608
6609         /* All fields are clean at this point */
6610         if (static_branch_unlikely(&enable_evmcs))
6611                 current_evmcs->hv_clean_fields |=
6612                         HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
6613
6614         if (static_branch_unlikely(&enable_evmcs))
6615                 current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index;
6616
6617         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6618         if (vmx->host_debugctlmsr)
6619                 update_debugctlmsr(vmx->host_debugctlmsr);
6620
6621 #ifndef CONFIG_X86_64
6622         /*
6623          * The sysexit path does not restore ds/es, so we must set them to
6624          * a reasonable value ourselves.
6625          *
6626          * We can't defer this to vmx_prepare_switch_to_host() since that
6627          * function may be executed in interrupt context, which saves and
6628          * restore segments around it, nullifying its effect.
6629          */
6630         loadsegment(ds, __USER_DS);
6631         loadsegment(es, __USER_DS);
6632 #endif
6633
6634         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6635                                   | (1 << VCPU_EXREG_RFLAGS)
6636                                   | (1 << VCPU_EXREG_PDPTR)
6637                                   | (1 << VCPU_EXREG_SEGMENTS)
6638                                   | (1 << VCPU_EXREG_CR3));
6639         vcpu->arch.regs_dirty = 0;
6640
6641         pt_guest_exit(vmx);
6642
6643         /*
6644          * eager fpu is enabled if PKEY is supported and CR4 is switched
6645          * back on host, so it is safe to read guest PKRU from current
6646          * XSAVE.
6647          */
6648         if (static_cpu_has(X86_FEATURE_PKU) &&
6649             kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
6650                 vcpu->arch.pkru = rdpkru();
6651                 if (vcpu->arch.pkru != vmx->host_pkru)
6652                         __write_pkru(vmx->host_pkru);
6653         }
6654
6655         kvm_put_guest_xcr0(vcpu);
6656
6657         vmx->nested.nested_run_pending = 0;
6658         vmx->idt_vectoring_info = 0;
6659
6660         vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
6661         if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
6662                 kvm_machine_check();
6663
6664         if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6665                 return;
6666
6667         vmx->loaded_vmcs->launched = 1;
6668         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6669
6670         vmx_recover_nmi_blocking(vmx);
6671         vmx_complete_interrupts(vmx);
6672 }
6673
6674 static struct kvm *vmx_vm_alloc(void)
6675 {
6676         struct kvm_vmx *kvm_vmx = __vmalloc(sizeof(struct kvm_vmx),
6677                                             GFP_KERNEL_ACCOUNT | __GFP_ZERO,
6678                                             PAGE_KERNEL);
6679         return &kvm_vmx->kvm;
6680 }
6681
6682 static void vmx_vm_free(struct kvm *kvm)
6683 {
6684         kfree(kvm->arch.hyperv.hv_pa_pg);
6685         vfree(to_kvm_vmx(kvm));
6686 }
6687
6688 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6689 {
6690         struct vcpu_vmx *vmx = to_vmx(vcpu);
6691
6692         if (enable_pml)
6693                 vmx_destroy_pml_buffer(vmx);
6694         free_vpid(vmx->vpid);
6695         nested_vmx_free_vcpu(vcpu);
6696         free_loaded_vmcs(vmx->loaded_vmcs);
6697         kfree(vmx->guest_msrs);
6698         kvm_vcpu_uninit(vcpu);
6699         kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu);
6700         kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
6701         kmem_cache_free(kvm_vcpu_cache, vmx);
6702 }
6703
6704 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6705 {
6706         int err;
6707         struct vcpu_vmx *vmx;
6708         unsigned long *msr_bitmap;
6709         int cpu;
6710
6711         BUILD_BUG_ON_MSG(offsetof(struct vcpu_vmx, vcpu) != 0,
6712                 "struct kvm_vcpu must be at offset 0 for arch usercopy region");
6713
6714         vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL_ACCOUNT);
6715         if (!vmx)
6716                 return ERR_PTR(-ENOMEM);
6717
6718         vmx->vcpu.arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
6719                         GFP_KERNEL_ACCOUNT);
6720         if (!vmx->vcpu.arch.user_fpu) {
6721                 printk(KERN_ERR "kvm: failed to allocate kvm userspace's fpu\n");
6722                 err = -ENOMEM;
6723                 goto free_partial_vcpu;
6724         }
6725
6726         vmx->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
6727                         GFP_KERNEL_ACCOUNT);
6728         if (!vmx->vcpu.arch.guest_fpu) {
6729                 printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n");
6730                 err = -ENOMEM;
6731                 goto free_user_fpu;
6732         }
6733
6734         vmx->vpid = allocate_vpid();
6735
6736         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6737         if (err)
6738                 goto free_vcpu;
6739
6740         err = -ENOMEM;
6741
6742         /*
6743          * If PML is turned on, failure on enabling PML just results in failure
6744          * of creating the vcpu, therefore we can simplify PML logic (by
6745          * avoiding dealing with cases, such as enabling PML partially on vcpus
6746          * for the guest, etc.
6747          */
6748         if (enable_pml) {
6749                 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
6750                 if (!vmx->pml_pg)
6751                         goto uninit_vcpu;
6752         }
6753
6754         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL_ACCOUNT);
6755         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
6756                      > PAGE_SIZE);
6757
6758         if (!vmx->guest_msrs)
6759                 goto free_pml;
6760
6761         err = alloc_loaded_vmcs(&vmx->vmcs01);
6762         if (err < 0)
6763                 goto free_msrs;
6764
6765         msr_bitmap = vmx->vmcs01.msr_bitmap;
6766         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
6767         vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
6768         vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
6769         vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6770         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6771         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6772         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
6773         if (kvm_cstate_in_guest(kvm)) {
6774                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R);
6775                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6776                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6777                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6778         }
6779         vmx->msr_bitmap_mode = 0;
6780
6781         vmx->loaded_vmcs = &vmx->vmcs01;
6782         cpu = get_cpu();
6783         vmx_vcpu_load(&vmx->vcpu, cpu);
6784         vmx->vcpu.cpu = cpu;
6785         vmx_vcpu_setup(vmx);
6786         vmx_vcpu_put(&vmx->vcpu);
6787         put_cpu();
6788         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
6789                 err = alloc_apic_access_page(kvm);
6790                 if (err)
6791                         goto free_vmcs;
6792         }
6793
6794         if (enable_ept && !enable_unrestricted_guest) {
6795                 err = init_rmode_identity_map(kvm);
6796                 if (err)
6797                         goto free_vmcs;
6798         }
6799
6800         if (nested)
6801                 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
6802                                            vmx_capability.ept,
6803                                            kvm_vcpu_apicv_active(&vmx->vcpu));
6804         else
6805                 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
6806
6807         vmx->nested.posted_intr_nv = -1;
6808         vmx->nested.current_vmptr = -1ull;
6809
6810         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
6811
6812         /*
6813          * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
6814          * or POSTED_INTR_WAKEUP_VECTOR.
6815          */
6816         vmx->pi_desc.nv = POSTED_INTR_VECTOR;
6817         vmx->pi_desc.sn = 1;
6818
6819         vmx->ept_pointer = INVALID_PAGE;
6820
6821         return &vmx->vcpu;
6822
6823 free_vmcs:
6824         free_loaded_vmcs(vmx->loaded_vmcs);
6825 free_msrs:
6826         kfree(vmx->guest_msrs);
6827 free_pml:
6828         vmx_destroy_pml_buffer(vmx);
6829 uninit_vcpu:
6830         kvm_vcpu_uninit(&vmx->vcpu);
6831 free_vcpu:
6832         free_vpid(vmx->vpid);
6833         kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
6834 free_user_fpu:
6835         kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu);
6836 free_partial_vcpu:
6837         kmem_cache_free(kvm_vcpu_cache, vmx);
6838         return ERR_PTR(err);
6839 }
6840
6841 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6842 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6843
6844 static int vmx_vm_init(struct kvm *kvm)
6845 {
6846         spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
6847
6848         if (!ple_gap)
6849                 kvm->arch.pause_in_guest = true;
6850
6851         if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6852                 switch (l1tf_mitigation) {
6853                 case L1TF_MITIGATION_OFF:
6854                 case L1TF_MITIGATION_FLUSH_NOWARN:
6855                         /* 'I explicitly don't care' is set */
6856                         break;
6857                 case L1TF_MITIGATION_FLUSH:
6858                 case L1TF_MITIGATION_FLUSH_NOSMT:
6859                 case L1TF_MITIGATION_FULL:
6860                         /*
6861                          * Warn upon starting the first VM in a potentially
6862                          * insecure environment.
6863                          */
6864                         if (sched_smt_active())
6865                                 pr_warn_once(L1TF_MSG_SMT);
6866                         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6867                                 pr_warn_once(L1TF_MSG_L1D);
6868                         break;
6869                 case L1TF_MITIGATION_FULL_FORCE:
6870                         /* Flush is enforced */
6871                         break;
6872                 }
6873         }
6874         return 0;
6875 }
6876
6877 static int __init vmx_check_processor_compat(void)
6878 {
6879         struct vmcs_config vmcs_conf;
6880         struct vmx_capability vmx_cap;
6881
6882         if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
6883                 return -EIO;
6884         if (nested)
6885                 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept,
6886                                            enable_apicv);
6887         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6888                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6889                                 smp_processor_id());
6890                 return -EIO;
6891         }
6892         return 0;
6893 }
6894
6895 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6896 {
6897         u8 cache;
6898         u64 ipat = 0;
6899
6900         /* For VT-d and EPT combination
6901          * 1. MMIO: always map as UC
6902          * 2. EPT with VT-d:
6903          *   a. VT-d without snooping control feature: can't guarantee the
6904          *      result, try to trust guest.
6905          *   b. VT-d with snooping control feature: snooping control feature of
6906          *      VT-d engine can guarantee the cache correctness. Just set it
6907          *      to WB to keep consistent with host. So the same as item 3.
6908          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6909          *    consistent with host MTRR
6910          */
6911         if (is_mmio) {
6912                 cache = MTRR_TYPE_UNCACHABLE;
6913                 goto exit;
6914         }
6915
6916         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
6917                 ipat = VMX_EPT_IPAT_BIT;
6918                 cache = MTRR_TYPE_WRBACK;
6919                 goto exit;
6920         }
6921
6922         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
6923                 ipat = VMX_EPT_IPAT_BIT;
6924                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
6925                         cache = MTRR_TYPE_WRBACK;
6926                 else
6927                         cache = MTRR_TYPE_UNCACHABLE;
6928                 goto exit;
6929         }
6930
6931         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
6932
6933 exit:
6934         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
6935 }
6936
6937 static int vmx_get_lpage_level(void)
6938 {
6939         if (enable_ept && !cpu_has_vmx_ept_1g_page())
6940                 return PT_DIRECTORY_LEVEL;
6941         else
6942                 /* For shadow and EPT supported 1GB page */
6943                 return PT_PDPE_LEVEL;
6944 }
6945
6946 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx)
6947 {
6948         /*
6949          * These bits in the secondary execution controls field
6950          * are dynamic, the others are mostly based on the hypervisor
6951          * architecture and the guest's CPUID.  Do not touch the
6952          * dynamic bits.
6953          */
6954         u32 mask =
6955                 SECONDARY_EXEC_SHADOW_VMCS |
6956                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
6957                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6958                 SECONDARY_EXEC_DESC;
6959
6960         u32 new_ctl = vmx->secondary_exec_control;
6961         u32 cur_ctl = secondary_exec_controls_get(vmx);
6962
6963         secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
6964 }
6965
6966 /*
6967  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
6968  * (indicating "allowed-1") if they are supported in the guest's CPUID.
6969  */
6970 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
6971 {
6972         struct vcpu_vmx *vmx = to_vmx(vcpu);
6973         struct kvm_cpuid_entry2 *entry;
6974
6975         vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
6976         vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
6977
6978 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
6979         if (entry && (entry->_reg & (_cpuid_mask)))                     \
6980                 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask);     \
6981 } while (0)
6982
6983         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
6984         cr4_fixed1_update(X86_CR4_VME,        edx, bit(X86_FEATURE_VME));
6985         cr4_fixed1_update(X86_CR4_PVI,        edx, bit(X86_FEATURE_VME));
6986         cr4_fixed1_update(X86_CR4_TSD,        edx, bit(X86_FEATURE_TSC));
6987         cr4_fixed1_update(X86_CR4_DE,         edx, bit(X86_FEATURE_DE));
6988         cr4_fixed1_update(X86_CR4_PSE,        edx, bit(X86_FEATURE_PSE));
6989         cr4_fixed1_update(X86_CR4_PAE,        edx, bit(X86_FEATURE_PAE));
6990         cr4_fixed1_update(X86_CR4_MCE,        edx, bit(X86_FEATURE_MCE));
6991         cr4_fixed1_update(X86_CR4_PGE,        edx, bit(X86_FEATURE_PGE));
6992         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, bit(X86_FEATURE_FXSR));
6993         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
6994         cr4_fixed1_update(X86_CR4_VMXE,       ecx, bit(X86_FEATURE_VMX));
6995         cr4_fixed1_update(X86_CR4_SMXE,       ecx, bit(X86_FEATURE_SMX));
6996         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, bit(X86_FEATURE_PCID));
6997         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, bit(X86_FEATURE_XSAVE));
6998
6999         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7000         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, bit(X86_FEATURE_FSGSBASE));
7001         cr4_fixed1_update(X86_CR4_SMEP,       ebx, bit(X86_FEATURE_SMEP));
7002         cr4_fixed1_update(X86_CR4_SMAP,       ebx, bit(X86_FEATURE_SMAP));
7003         cr4_fixed1_update(X86_CR4_PKE,        ecx, bit(X86_FEATURE_PKU));
7004         cr4_fixed1_update(X86_CR4_UMIP,       ecx, bit(X86_FEATURE_UMIP));
7005
7006 #undef cr4_fixed1_update
7007 }
7008
7009 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
7010 {
7011         struct vcpu_vmx *vmx = to_vmx(vcpu);
7012
7013         if (kvm_mpx_supported()) {
7014                 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
7015
7016                 if (mpx_enabled) {
7017                         vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
7018                         vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
7019                 } else {
7020                         vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
7021                         vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
7022                 }
7023         }
7024 }
7025
7026 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
7027 {
7028         struct vcpu_vmx *vmx = to_vmx(vcpu);
7029         struct kvm_cpuid_entry2 *best = NULL;
7030         int i;
7031
7032         for (i = 0; i < PT_CPUID_LEAVES; i++) {
7033                 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
7034                 if (!best)
7035                         return;
7036                 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
7037                 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
7038                 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
7039                 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
7040         }
7041
7042         /* Get the number of configurable Address Ranges for filtering */
7043         vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
7044                                                 PT_CAP_num_address_ranges);
7045
7046         /* Initialize and clear the no dependency bits */
7047         vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
7048                         RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
7049
7050         /*
7051          * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
7052          * will inject an #GP
7053          */
7054         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
7055                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
7056
7057         /*
7058          * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
7059          * PSBFreq can be set
7060          */
7061         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
7062                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
7063                                 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
7064
7065         /*
7066          * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
7067          * MTCFreq can be set
7068          */
7069         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
7070                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
7071                                 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
7072
7073         /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
7074         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
7075                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
7076                                                         RTIT_CTL_PTW_EN);
7077
7078         /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7079         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
7080                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
7081
7082         /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7083         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
7084                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
7085
7086         /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */
7087         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
7088                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
7089
7090         /* unmask address range configure area */
7091         for (i = 0; i < vmx->pt_desc.addr_range; i++)
7092                 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
7093 }
7094
7095 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7096 {
7097         struct vcpu_vmx *vmx = to_vmx(vcpu);
7098
7099         if (cpu_has_secondary_exec_ctrls()) {
7100                 vmx_compute_secondary_exec_control(vmx);
7101                 vmcs_set_secondary_exec_control(vmx);
7102         }
7103
7104         if (nested_vmx_allowed(vcpu))
7105                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7106                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7107         else
7108                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7109                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7110
7111         if (nested_vmx_allowed(vcpu)) {
7112                 nested_vmx_cr_fixed1_bits_update(vcpu);
7113                 nested_vmx_entry_exit_ctls_update(vcpu);
7114         }
7115
7116         if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7117                         guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7118                 update_intel_pt_cfg(vcpu);
7119 }
7120
7121 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7122 {
7123         if (func == 1 && nested)
7124                 entry->ecx |= bit(X86_FEATURE_VMX);
7125 }
7126
7127 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
7128 {
7129         to_vmx(vcpu)->req_immediate_exit = true;
7130 }
7131
7132 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7133                                struct x86_instruction_info *info,
7134                                enum x86_intercept_stage stage)
7135 {
7136         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7137         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7138
7139         /*
7140          * RDPID causes #UD if disabled through secondary execution controls.
7141          * Because it is marked as EmulateOnUD, we need to intercept it here.
7142          */
7143         if (info->intercept == x86_intercept_rdtscp &&
7144             !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
7145                 ctxt->exception.vector = UD_VECTOR;
7146                 ctxt->exception.error_code_valid = false;
7147                 return X86EMUL_PROPAGATE_FAULT;
7148         }
7149
7150         /* TODO: check more intercepts... */
7151         return X86EMUL_CONTINUE;
7152 }
7153
7154 #ifdef CONFIG_X86_64
7155 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7156 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7157                                   u64 divisor, u64 *result)
7158 {
7159         u64 low = a << shift, high = a >> (64 - shift);
7160
7161         /* To avoid the overflow on divq */
7162         if (high >= divisor)
7163                 return 1;
7164
7165         /* Low hold the result, high hold rem which is discarded */
7166         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7167             "rm" (divisor), "0" (low), "1" (high));
7168         *result = low;
7169
7170         return 0;
7171 }
7172
7173 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7174                             bool *expired)
7175 {
7176         struct vcpu_vmx *vmx;
7177         u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
7178         struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
7179
7180         if (kvm_mwait_in_guest(vcpu->kvm) ||
7181                 kvm_can_post_timer_interrupt(vcpu))
7182                 return -EOPNOTSUPP;
7183
7184         vmx = to_vmx(vcpu);
7185         tscl = rdtsc();
7186         guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7187         delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
7188         lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7189                                                     ktimer->timer_advance_ns);
7190
7191         if (delta_tsc > lapic_timer_advance_cycles)
7192                 delta_tsc -= lapic_timer_advance_cycles;
7193         else
7194                 delta_tsc = 0;
7195
7196         /* Convert to host delta tsc if tsc scaling is enabled */
7197         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
7198             delta_tsc && u64_shl_div_u64(delta_tsc,
7199                                 kvm_tsc_scaling_ratio_frac_bits,
7200                                 vcpu->arch.tsc_scaling_ratio, &delta_tsc))
7201                 return -ERANGE;
7202
7203         /*
7204          * If the delta tsc can't fit in the 32 bit after the multi shift,
7205          * we can't use the preemption timer.
7206          * It's possible that it fits on later vmentries, but checking
7207          * on every vmentry is costly so we just use an hrtimer.
7208          */
7209         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7210                 return -ERANGE;
7211
7212         vmx->hv_deadline_tsc = tscl + delta_tsc;
7213         *expired = !delta_tsc;
7214         return 0;
7215 }
7216
7217 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7218 {
7219         to_vmx(vcpu)->hv_deadline_tsc = -1;
7220 }
7221 #endif
7222
7223 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
7224 {
7225         if (!kvm_pause_in_guest(vcpu->kvm))
7226                 shrink_ple_window(vcpu);
7227 }
7228
7229 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
7230                                      struct kvm_memory_slot *slot)
7231 {
7232         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
7233         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
7234 }
7235
7236 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
7237                                        struct kvm_memory_slot *slot)
7238 {
7239         kvm_mmu_slot_set_dirty(kvm, slot);
7240 }
7241
7242 static void vmx_flush_log_dirty(struct kvm *kvm)
7243 {
7244         kvm_flush_pml_buffers(kvm);
7245 }
7246
7247 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
7248 {
7249         struct vmcs12 *vmcs12;
7250         struct vcpu_vmx *vmx = to_vmx(vcpu);
7251         gpa_t gpa, dst;
7252
7253         if (is_guest_mode(vcpu)) {
7254                 WARN_ON_ONCE(vmx->nested.pml_full);
7255
7256                 /*
7257                  * Check if PML is enabled for the nested guest.
7258                  * Whether eptp bit 6 is set is already checked
7259                  * as part of A/D emulation.
7260                  */
7261                 vmcs12 = get_vmcs12(vcpu);
7262                 if (!nested_cpu_has_pml(vmcs12))
7263                         return 0;
7264
7265                 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
7266                         vmx->nested.pml_full = true;
7267                         return 1;
7268                 }
7269
7270                 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
7271                 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index;
7272
7273                 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa,
7274                                          offset_in_page(dst), sizeof(gpa)))
7275                         return 0;
7276
7277                 vmcs12->guest_pml_index--;
7278         }
7279
7280         return 0;
7281 }
7282
7283 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
7284                                            struct kvm_memory_slot *memslot,
7285                                            gfn_t offset, unsigned long mask)
7286 {
7287         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
7288 }
7289
7290 static void __pi_post_block(struct kvm_vcpu *vcpu)
7291 {
7292         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7293         struct pi_desc old, new;
7294         unsigned int dest;
7295
7296         do {
7297                 old.control = new.control = pi_desc->control;
7298                 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
7299                      "Wakeup handler not enabled while the VCPU is blocked\n");
7300
7301                 dest = cpu_physical_id(vcpu->cpu);
7302
7303                 if (x2apic_enabled())
7304                         new.ndst = dest;
7305                 else
7306                         new.ndst = (dest << 8) & 0xFF00;
7307
7308                 /* set 'NV' to 'notification vector' */
7309                 new.nv = POSTED_INTR_VECTOR;
7310         } while (cmpxchg64(&pi_desc->control, old.control,
7311                            new.control) != old.control);
7312
7313         if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
7314                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7315                 list_del(&vcpu->blocked_vcpu_list);
7316                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7317                 vcpu->pre_pcpu = -1;
7318         }
7319 }
7320
7321 /*
7322  * This routine does the following things for vCPU which is going
7323  * to be blocked if VT-d PI is enabled.
7324  * - Store the vCPU to the wakeup list, so when interrupts happen
7325  *   we can find the right vCPU to wake up.
7326  * - Change the Posted-interrupt descriptor as below:
7327  *      'NDST' <-- vcpu->pre_pcpu
7328  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
7329  * - If 'ON' is set during this process, which means at least one
7330  *   interrupt is posted for this vCPU, we cannot block it, in
7331  *   this case, return 1, otherwise, return 0.
7332  *
7333  */
7334 static int pi_pre_block(struct kvm_vcpu *vcpu)
7335 {
7336         unsigned int dest;
7337         struct pi_desc old, new;
7338         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7339
7340         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
7341                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
7342                 !kvm_vcpu_apicv_active(vcpu))
7343                 return 0;
7344
7345         WARN_ON(irqs_disabled());
7346         local_irq_disable();
7347         if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
7348                 vcpu->pre_pcpu = vcpu->cpu;
7349                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7350                 list_add_tail(&vcpu->blocked_vcpu_list,
7351                               &per_cpu(blocked_vcpu_on_cpu,
7352                                        vcpu->pre_pcpu));
7353                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7354         }
7355
7356         do {
7357                 old.control = new.control = pi_desc->control;
7358
7359                 WARN((pi_desc->sn == 1),
7360                      "Warning: SN field of posted-interrupts "
7361                      "is set before blocking\n");
7362
7363                 /*
7364                  * Since vCPU can be preempted during this process,
7365                  * vcpu->cpu could be different with pre_pcpu, we
7366                  * need to set pre_pcpu as the destination of wakeup
7367                  * notification event, then we can find the right vCPU
7368                  * to wakeup in wakeup handler if interrupts happen
7369                  * when the vCPU is in blocked state.
7370                  */
7371                 dest = cpu_physical_id(vcpu->pre_pcpu);
7372
7373                 if (x2apic_enabled())
7374                         new.ndst = dest;
7375                 else
7376                         new.ndst = (dest << 8) & 0xFF00;
7377
7378                 /* set 'NV' to 'wakeup vector' */
7379                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
7380         } while (cmpxchg64(&pi_desc->control, old.control,
7381                            new.control) != old.control);
7382
7383         /* We should not block the vCPU if an interrupt is posted for it.  */
7384         if (pi_test_on(pi_desc) == 1)
7385                 __pi_post_block(vcpu);
7386
7387         local_irq_enable();
7388         return (vcpu->pre_pcpu == -1);
7389 }
7390
7391 static int vmx_pre_block(struct kvm_vcpu *vcpu)
7392 {
7393         if (pi_pre_block(vcpu))
7394                 return 1;
7395
7396         if (kvm_lapic_hv_timer_in_use(vcpu))
7397                 kvm_lapic_switch_to_sw_timer(vcpu);
7398
7399         return 0;
7400 }
7401
7402 static void pi_post_block(struct kvm_vcpu *vcpu)
7403 {
7404         if (vcpu->pre_pcpu == -1)
7405                 return;
7406
7407         WARN_ON(irqs_disabled());
7408         local_irq_disable();
7409         __pi_post_block(vcpu);
7410         local_irq_enable();
7411 }
7412
7413 static void vmx_post_block(struct kvm_vcpu *vcpu)
7414 {
7415         if (kvm_x86_ops->set_hv_timer)
7416                 kvm_lapic_switch_to_hv_timer(vcpu);
7417
7418         pi_post_block(vcpu);
7419 }
7420
7421 /*
7422  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
7423  *
7424  * @kvm: kvm
7425  * @host_irq: host irq of the interrupt
7426  * @guest_irq: gsi of the interrupt
7427  * @set: set or unset PI
7428  * returns 0 on success, < 0 on failure
7429  */
7430 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
7431                               uint32_t guest_irq, bool set)
7432 {
7433         struct kvm_kernel_irq_routing_entry *e;
7434         struct kvm_irq_routing_table *irq_rt;
7435         struct kvm_lapic_irq irq;
7436         struct kvm_vcpu *vcpu;
7437         struct vcpu_data vcpu_info;
7438         int idx, ret = 0;
7439
7440         if (!kvm_arch_has_assigned_device(kvm) ||
7441                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7442                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
7443                 return 0;
7444
7445         idx = srcu_read_lock(&kvm->irq_srcu);
7446         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
7447         if (guest_irq >= irq_rt->nr_rt_entries ||
7448             hlist_empty(&irq_rt->map[guest_irq])) {
7449                 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
7450                              guest_irq, irq_rt->nr_rt_entries);
7451                 goto out;
7452         }
7453
7454         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
7455                 if (e->type != KVM_IRQ_ROUTING_MSI)
7456                         continue;
7457                 /*
7458                  * VT-d PI cannot support posting multicast/broadcast
7459                  * interrupts to a vCPU, we still use interrupt remapping
7460                  * for these kind of interrupts.
7461                  *
7462                  * For lowest-priority interrupts, we only support
7463                  * those with single CPU as the destination, e.g. user
7464                  * configures the interrupts via /proc/irq or uses
7465                  * irqbalance to make the interrupts single-CPU.
7466                  *
7467                  * We will support full lowest-priority interrupt later.
7468                  *
7469                  * In addition, we can only inject generic interrupts using
7470                  * the PI mechanism, refuse to route others through it.
7471                  */
7472
7473                 kvm_set_msi_irq(kvm, e, &irq);
7474                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) ||
7475                     !kvm_irq_is_postable(&irq)) {
7476                         /*
7477                          * Make sure the IRTE is in remapped mode if
7478                          * we don't handle it in posted mode.
7479                          */
7480                         ret = irq_set_vcpu_affinity(host_irq, NULL);
7481                         if (ret < 0) {
7482                                 printk(KERN_INFO
7483                                    "failed to back to remapped mode, irq: %u\n",
7484                                    host_irq);
7485                                 goto out;
7486                         }
7487
7488                         continue;
7489                 }
7490
7491                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
7492                 vcpu_info.vector = irq.vector;
7493
7494                 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
7495                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
7496
7497                 if (set)
7498                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
7499                 else
7500                         ret = irq_set_vcpu_affinity(host_irq, NULL);
7501
7502                 if (ret < 0) {
7503                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
7504                                         __func__);
7505                         goto out;
7506                 }
7507         }
7508
7509         ret = 0;
7510 out:
7511         srcu_read_unlock(&kvm->irq_srcu, idx);
7512         return ret;
7513 }
7514
7515 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7516 {
7517         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7518                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7519                         FEATURE_CONTROL_LMCE;
7520         else
7521                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7522                         ~FEATURE_CONTROL_LMCE;
7523 }
7524
7525 static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
7526 {
7527         /* we need a nested vmexit to enter SMM, postpone if run is pending */
7528         if (to_vmx(vcpu)->nested.nested_run_pending)
7529                 return 0;
7530         return 1;
7531 }
7532
7533 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7534 {
7535         struct vcpu_vmx *vmx = to_vmx(vcpu);
7536
7537         vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7538         if (vmx->nested.smm.guest_mode)
7539                 nested_vmx_vmexit(vcpu, -1, 0, 0);
7540
7541         vmx->nested.smm.vmxon = vmx->nested.vmxon;
7542         vmx->nested.vmxon = false;
7543         vmx_clear_hlt(vcpu);
7544         return 0;
7545 }
7546
7547 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
7548 {
7549         struct vcpu_vmx *vmx = to_vmx(vcpu);
7550         int ret;
7551
7552         if (vmx->nested.smm.vmxon) {
7553                 vmx->nested.vmxon = true;
7554                 vmx->nested.smm.vmxon = false;
7555         }
7556
7557         if (vmx->nested.smm.guest_mode) {
7558                 ret = nested_vmx_enter_non_root_mode(vcpu, false);
7559                 if (ret)
7560                         return ret;
7561
7562                 vmx->nested.smm.guest_mode = false;
7563         }
7564         return 0;
7565 }
7566
7567 static int enable_smi_window(struct kvm_vcpu *vcpu)
7568 {
7569         return 0;
7570 }
7571
7572 static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7573 {
7574         return false;
7575 }
7576
7577 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7578 {
7579         return to_vmx(vcpu)->nested.vmxon;
7580 }
7581
7582 static __init int hardware_setup(void)
7583 {
7584         unsigned long host_bndcfgs;
7585         struct desc_ptr dt;
7586         int r, i;
7587
7588         rdmsrl_safe(MSR_EFER, &host_efer);
7589
7590         store_idt(&dt);
7591         host_idt_base = dt.address;
7592
7593         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7594                 kvm_define_shared_msr(i, vmx_msr_index[i]);
7595
7596         if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7597                 return -EIO;
7598
7599         if (boot_cpu_has(X86_FEATURE_NX))
7600                 kvm_enable_efer_bits(EFER_NX);
7601
7602         if (boot_cpu_has(X86_FEATURE_MPX)) {
7603                 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7604                 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7605         }
7606
7607         if (boot_cpu_has(X86_FEATURE_XSAVES))
7608                 rdmsrl(MSR_IA32_XSS, host_xss);
7609
7610         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7611             !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7612                 enable_vpid = 0;
7613
7614         if (!cpu_has_vmx_ept() ||
7615             !cpu_has_vmx_ept_4levels() ||
7616             !cpu_has_vmx_ept_mt_wb() ||
7617             !cpu_has_vmx_invept_global())
7618                 enable_ept = 0;
7619
7620         if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7621                 enable_ept_ad_bits = 0;
7622
7623         if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7624                 enable_unrestricted_guest = 0;
7625
7626         if (!cpu_has_vmx_flexpriority())
7627                 flexpriority_enabled = 0;
7628
7629         if (!cpu_has_virtual_nmis())
7630                 enable_vnmi = 0;
7631
7632         /*
7633          * set_apic_access_page_addr() is used to reload apic access
7634          * page upon invalidation.  No need to do anything if not
7635          * using the APIC_ACCESS_ADDR VMCS field.
7636          */
7637         if (!flexpriority_enabled)
7638                 kvm_x86_ops->set_apic_access_page_addr = NULL;
7639
7640         if (!cpu_has_vmx_tpr_shadow())
7641                 kvm_x86_ops->update_cr8_intercept = NULL;
7642
7643         if (enable_ept && !cpu_has_vmx_ept_2m_page())
7644                 kvm_disable_largepages();
7645
7646 #if IS_ENABLED(CONFIG_HYPERV)
7647         if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7648             && enable_ept) {
7649                 kvm_x86_ops->tlb_remote_flush = hv_remote_flush_tlb;
7650                 kvm_x86_ops->tlb_remote_flush_with_range =
7651                                 hv_remote_flush_tlb_with_range;
7652         }
7653 #endif
7654
7655         if (!cpu_has_vmx_ple()) {
7656                 ple_gap = 0;
7657                 ple_window = 0;
7658                 ple_window_grow = 0;
7659                 ple_window_max = 0;
7660                 ple_window_shrink = 0;
7661         }
7662
7663         if (!cpu_has_vmx_apicv()) {
7664                 enable_apicv = 0;
7665                 kvm_x86_ops->sync_pir_to_irr = NULL;
7666         }
7667
7668         if (cpu_has_vmx_tsc_scaling()) {
7669                 kvm_has_tsc_control = true;
7670                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7671                 kvm_tsc_scaling_ratio_frac_bits = 48;
7672         }
7673
7674         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7675
7676         if (enable_ept)
7677                 vmx_enable_tdp();
7678         else
7679                 kvm_disable_tdp();
7680
7681         /*
7682          * Only enable PML when hardware supports PML feature, and both EPT
7683          * and EPT A/D bit features are enabled -- PML depends on them to work.
7684          */
7685         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7686                 enable_pml = 0;
7687
7688         if (!enable_pml) {
7689                 kvm_x86_ops->slot_enable_log_dirty = NULL;
7690                 kvm_x86_ops->slot_disable_log_dirty = NULL;
7691                 kvm_x86_ops->flush_log_dirty = NULL;
7692                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7693         }
7694
7695         if (!cpu_has_vmx_preemption_timer())
7696                 enable_preemption_timer = false;
7697
7698         if (enable_preemption_timer) {
7699                 u64 use_timer_freq = 5000ULL * 1000 * 1000;
7700                 u64 vmx_msr;
7701
7702                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7703                 cpu_preemption_timer_multi =
7704                         vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7705
7706                 if (tsc_khz)
7707                         use_timer_freq = (u64)tsc_khz * 1000;
7708                 use_timer_freq >>= cpu_preemption_timer_multi;
7709
7710                 /*
7711                  * KVM "disables" the preemption timer by setting it to its max
7712                  * value.  Don't use the timer if it might cause spurious exits
7713                  * at a rate faster than 0.1 Hz (of uninterrupted guest time).
7714                  */
7715                 if (use_timer_freq > 0xffffffffu / 10)
7716                         enable_preemption_timer = false;
7717         }
7718
7719         if (!enable_preemption_timer) {
7720                 kvm_x86_ops->set_hv_timer = NULL;
7721                 kvm_x86_ops->cancel_hv_timer = NULL;
7722                 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit;
7723         }
7724
7725         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
7726
7727         kvm_mce_cap_supported |= MCG_LMCE_P;
7728
7729         if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
7730                 return -EINVAL;
7731         if (!enable_ept || !cpu_has_vmx_intel_pt())
7732                 pt_mode = PT_MODE_SYSTEM;
7733
7734         if (nested) {
7735                 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
7736                                            vmx_capability.ept, enable_apicv);
7737
7738                 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
7739                 if (r)
7740                         return r;
7741         }
7742
7743         r = alloc_kvm_area();
7744         if (r)
7745                 nested_vmx_hardware_unsetup();
7746         return r;
7747 }
7748
7749 static __exit void hardware_unsetup(void)
7750 {
7751         if (nested)
7752                 nested_vmx_hardware_unsetup();
7753
7754         free_kvm_area();
7755 }
7756
7757 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
7758         .cpu_has_kvm_support = cpu_has_kvm_support,
7759         .disabled_by_bios = vmx_disabled_by_bios,
7760         .hardware_setup = hardware_setup,
7761         .hardware_unsetup = hardware_unsetup,
7762         .check_processor_compatibility = vmx_check_processor_compat,
7763         .hardware_enable = hardware_enable,
7764         .hardware_disable = hardware_disable,
7765         .cpu_has_accelerated_tpr = report_flexpriority,
7766         .has_emulated_msr = vmx_has_emulated_msr,
7767
7768         .vm_init = vmx_vm_init,
7769         .vm_alloc = vmx_vm_alloc,
7770         .vm_free = vmx_vm_free,
7771
7772         .vcpu_create = vmx_create_vcpu,
7773         .vcpu_free = vmx_free_vcpu,
7774         .vcpu_reset = vmx_vcpu_reset,
7775
7776         .prepare_guest_switch = vmx_prepare_switch_to_guest,
7777         .vcpu_load = vmx_vcpu_load,
7778         .vcpu_put = vmx_vcpu_put,
7779
7780         .update_bp_intercept = update_exception_bitmap,
7781         .get_msr_feature = vmx_get_msr_feature,
7782         .get_msr = vmx_get_msr,
7783         .set_msr = vmx_set_msr,
7784         .get_segment_base = vmx_get_segment_base,
7785         .get_segment = vmx_get_segment,
7786         .set_segment = vmx_set_segment,
7787         .get_cpl = vmx_get_cpl,
7788         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7789         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7790         .decache_cr3 = vmx_decache_cr3,
7791         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7792         .set_cr0 = vmx_set_cr0,
7793         .set_cr3 = vmx_set_cr3,
7794         .set_cr4 = vmx_set_cr4,
7795         .set_efer = vmx_set_efer,
7796         .get_idt = vmx_get_idt,
7797         .set_idt = vmx_set_idt,
7798         .get_gdt = vmx_get_gdt,
7799         .set_gdt = vmx_set_gdt,
7800         .get_dr6 = vmx_get_dr6,
7801         .set_dr6 = vmx_set_dr6,
7802         .set_dr7 = vmx_set_dr7,
7803         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
7804         .cache_reg = vmx_cache_reg,
7805         .get_rflags = vmx_get_rflags,
7806         .set_rflags = vmx_set_rflags,
7807
7808         .tlb_flush = vmx_flush_tlb,
7809         .tlb_flush_gva = vmx_flush_tlb_gva,
7810
7811         .run = vmx_vcpu_run,
7812         .handle_exit = vmx_handle_exit,
7813         .skip_emulated_instruction = skip_emulated_instruction,
7814         .set_interrupt_shadow = vmx_set_interrupt_shadow,
7815         .get_interrupt_shadow = vmx_get_interrupt_shadow,
7816         .patch_hypercall = vmx_patch_hypercall,
7817         .set_irq = vmx_inject_irq,
7818         .set_nmi = vmx_inject_nmi,
7819         .queue_exception = vmx_queue_exception,
7820         .cancel_injection = vmx_cancel_injection,
7821         .interrupt_allowed = vmx_interrupt_allowed,
7822         .nmi_allowed = vmx_nmi_allowed,
7823         .get_nmi_mask = vmx_get_nmi_mask,
7824         .set_nmi_mask = vmx_set_nmi_mask,
7825         .enable_nmi_window = enable_nmi_window,
7826         .enable_irq_window = enable_irq_window,
7827         .update_cr8_intercept = update_cr8_intercept,
7828         .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
7829         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
7830         .get_enable_apicv = vmx_get_enable_apicv,
7831         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
7832         .load_eoi_exitmap = vmx_load_eoi_exitmap,
7833         .apicv_post_state_restore = vmx_apicv_post_state_restore,
7834         .hwapic_irr_update = vmx_hwapic_irr_update,
7835         .hwapic_isr_update = vmx_hwapic_isr_update,
7836         .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
7837         .sync_pir_to_irr = vmx_sync_pir_to_irr,
7838         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
7839         .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt,
7840
7841         .set_tss_addr = vmx_set_tss_addr,
7842         .set_identity_map_addr = vmx_set_identity_map_addr,
7843         .get_tdp_level = get_ept_level,
7844         .get_mt_mask = vmx_get_mt_mask,
7845
7846         .get_exit_info = vmx_get_exit_info,
7847
7848         .get_lpage_level = vmx_get_lpage_level,
7849
7850         .cpuid_update = vmx_cpuid_update,
7851
7852         .rdtscp_supported = vmx_rdtscp_supported,
7853         .invpcid_supported = vmx_invpcid_supported,
7854
7855         .set_supported_cpuid = vmx_set_supported_cpuid,
7856
7857         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7858
7859         .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
7860         .write_l1_tsc_offset = vmx_write_l1_tsc_offset,
7861
7862         .set_tdp_cr3 = vmx_set_cr3,
7863
7864         .check_intercept = vmx_check_intercept,
7865         .handle_exit_irqoff = vmx_handle_exit_irqoff,
7866         .mpx_supported = vmx_mpx_supported,
7867         .xsaves_supported = vmx_xsaves_supported,
7868         .umip_emulated = vmx_umip_emulated,
7869         .pt_supported = vmx_pt_supported,
7870         .pku_supported = vmx_pku_supported,
7871
7872         .request_immediate_exit = vmx_request_immediate_exit,
7873
7874         .sched_in = vmx_sched_in,
7875
7876         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
7877         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
7878         .flush_log_dirty = vmx_flush_log_dirty,
7879         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
7880         .write_log_dirty = vmx_write_pml_buffer,
7881
7882         .pre_block = vmx_pre_block,
7883         .post_block = vmx_post_block,
7884
7885         .pmu_ops = &intel_pmu_ops,
7886
7887         .update_pi_irte = vmx_update_pi_irte,
7888
7889 #ifdef CONFIG_X86_64
7890         .set_hv_timer = vmx_set_hv_timer,
7891         .cancel_hv_timer = vmx_cancel_hv_timer,
7892 #endif
7893
7894         .setup_mce = vmx_setup_mce,
7895
7896         .smi_allowed = vmx_smi_allowed,
7897         .pre_enter_smm = vmx_pre_enter_smm,
7898         .pre_leave_smm = vmx_pre_leave_smm,
7899         .enable_smi_window = enable_smi_window,
7900
7901         .check_nested_events = NULL,
7902         .get_nested_state = NULL,
7903         .set_nested_state = NULL,
7904         .get_vmcs12_pages = NULL,
7905         .nested_enable_evmcs = NULL,
7906         .nested_get_evmcs_version = NULL,
7907         .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault,
7908         .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
7909 };
7910
7911 static void vmx_cleanup_l1d_flush(void)
7912 {
7913         if (vmx_l1d_flush_pages) {
7914                 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
7915                 vmx_l1d_flush_pages = NULL;
7916         }
7917         /* Restore state so sysfs ignores VMX */
7918         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
7919 }
7920
7921 static void vmx_exit(void)
7922 {
7923 #ifdef CONFIG_KEXEC_CORE
7924         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
7925         synchronize_rcu();
7926 #endif
7927
7928         kvm_exit();
7929
7930 #if IS_ENABLED(CONFIG_HYPERV)
7931         if (static_branch_unlikely(&enable_evmcs)) {
7932                 int cpu;
7933                 struct hv_vp_assist_page *vp_ap;
7934                 /*
7935                  * Reset everything to support using non-enlightened VMCS
7936                  * access later (e.g. when we reload the module with
7937                  * enlightened_vmcs=0)
7938                  */
7939                 for_each_online_cpu(cpu) {
7940                         vp_ap = hv_get_vp_assist_page(cpu);
7941
7942                         if (!vp_ap)
7943                                 continue;
7944
7945                         vp_ap->nested_control.features.directhypercall = 0;
7946                         vp_ap->current_nested_vmcs = 0;
7947                         vp_ap->enlighten_vmentry = 0;
7948                 }
7949
7950                 static_branch_disable(&enable_evmcs);
7951         }
7952 #endif
7953         vmx_cleanup_l1d_flush();
7954 }
7955 module_exit(vmx_exit);
7956
7957 static int __init vmx_init(void)
7958 {
7959         int r;
7960
7961 #if IS_ENABLED(CONFIG_HYPERV)
7962         /*
7963          * Enlightened VMCS usage should be recommended and the host needs
7964          * to support eVMCS v1 or above. We can also disable eVMCS support
7965          * with module parameter.
7966          */
7967         if (enlightened_vmcs &&
7968             ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
7969             (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
7970             KVM_EVMCS_VERSION) {
7971                 int cpu;
7972
7973                 /* Check that we have assist pages on all online CPUs */
7974                 for_each_online_cpu(cpu) {
7975                         if (!hv_get_vp_assist_page(cpu)) {
7976                                 enlightened_vmcs = false;
7977                                 break;
7978                         }
7979                 }
7980
7981                 if (enlightened_vmcs) {
7982                         pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
7983                         static_branch_enable(&enable_evmcs);
7984                 }
7985
7986                 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
7987                         vmx_x86_ops.enable_direct_tlbflush
7988                                 = hv_enable_direct_tlbflush;
7989
7990         } else {
7991                 enlightened_vmcs = false;
7992         }
7993 #endif
7994
7995         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7996                      __alignof__(struct vcpu_vmx), THIS_MODULE);
7997         if (r)
7998                 return r;
7999
8000         /*
8001          * Must be called after kvm_init() so enable_ept is properly set
8002          * up. Hand the parameter mitigation value in which was stored in
8003          * the pre module init parser. If no parameter was given, it will
8004          * contain 'auto' which will be turned into the default 'cond'
8005          * mitigation mode.
8006          */
8007         r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
8008         if (r) {
8009                 vmx_exit();
8010                 return r;
8011         }
8012
8013 #ifdef CONFIG_KEXEC_CORE
8014         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8015                            crash_vmclear_local_loaded_vmcss);
8016 #endif
8017         vmx_check_vmcs12_offsets();
8018
8019         return 0;
8020 }
8021 module_init(vmx_init);