arch/x86/kvm/vmx/vmx.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Kernel-based Virtual Machine driver for Linux
   4  *
   5  * This module enables machines with Intel VT-x extensions to run virtual
   6  * machines without emulation or binary translation.
   7  *
   8  * Copyright (C) 2006 Qumranet, Inc.
   9  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  10  *
  11  * Authors:
  12  *   Avi Kivity   <avi@qumranet.com>
  13  *   Yaniv Kamay  <yaniv@qumranet.com>
  14  */
  15
  16 #include <linux/frame.h>
  17 #include <linux/highmem.h>
  18 #include <linux/hrtimer.h>
  19 #include <linux/kernel.h>
  20 #include <linux/kvm_host.h>
  21 #include <linux/module.h>
  22 #include <linux/moduleparam.h>
  23 #include <linux/mod_devicetable.h>
  24 #include <linux/mm.h>
  25 #include <linux/sched.h>
  26 #include <linux/sched/smt.h>
  27 #include <linux/slab.h>
  28 #include <linux/tboot.h>
  29 #include <linux/trace_events.h>
  30
  31 #include <asm/apic.h>
  32 #include <asm/asm.h>
  33 #include <asm/cpu.h>
  34 #include <asm/debugreg.h>
  35 #include <asm/desc.h>
  36 #include <asm/fpu/internal.h>
  37 #include <asm/io.h>
  38 #include <asm/irq_remapping.h>
  39 #include <asm/kexec.h>
  40 #include <asm/perf_event.h>
  41 #include <asm/mce.h>
  42 #include <asm/mmu_context.h>
  43 #include <asm/mshyperv.h>
  44 #include <asm/spec-ctrl.h>
  45 #include <asm/virtext.h>
  46 #include <asm/vmx.h>
  47
  48 #include "capabilities.h"
  49 #include "cpuid.h"
  50 #include "evmcs.h"
  51 #include "irq.h"
  52 #include "kvm_cache_regs.h"
  53 #include "lapic.h"
  54 #include "mmu.h"
  55 #include "nested.h"
  56 #include "ops.h"
  57 #include "pmu.h"
  58 #include "trace.h"
  59 #include "vmcs.h"
  60 #include "vmcs12.h"
  61 #include "vmx.h"
  62 #include "x86.h"
  63
  64 MODULE_AUTHOR("Qumranet");
  65 MODULE_LICENSE("GPL");
  66
  67 #ifdef MODULE
  68 static const struct x86_cpu_id vmx_cpu_id[] = {
  69         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  70         {}
  71 };
  72 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  73 #endif
  74
  75 bool __read_mostly enable_vpid = 1;
  76 module_param_named(vpid, enable_vpid, bool, 0444);
  77
  78 static bool __read_mostly enable_vnmi = 1;
  79 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
  80
  81 bool __read_mostly flexpriority_enabled = 1;
  82 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  83
  84 bool __read_mostly enable_ept = 1;
  85 module_param_named(ept, enable_ept, bool, S_IRUGO);
  86
  87 bool __read_mostly enable_unrestricted_guest = 1;
  88 module_param_named(unrestricted_guest,
  89                         enable_unrestricted_guest, bool, S_IRUGO);
  90
  91 bool __read_mostly enable_ept_ad_bits = 1;
  92 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  93
  94 static bool __read_mostly emulate_invalid_guest_state = true;
  95 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  96
  97 static bool __read_mostly fasteoi = 1;
  98 module_param(fasteoi, bool, S_IRUGO);
  99
 100 bool __read_mostly enable_apicv = 1;
 101 module_param(enable_apicv, bool, S_IRUGO);
 102
 103 /*
 104  * If nested=1, nested virtualization is supported, i.e., guests may use
 105  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 106  * use VMX instructions.
 107  */
 108 static bool __read_mostly nested = 1;
 109 module_param(nested, bool, S_IRUGO);
 110
 111 bool __read_mostly enable_pml = 1;
 112 module_param_named(pml, enable_pml, bool, S_IRUGO);
 113
 114 static bool __read_mostly dump_invalid_vmcs = 0;
 115 module_param(dump_invalid_vmcs, bool, 0644);
 116
 117 #define MSR_BITMAP_MODE_X2APIC          1
 118 #define MSR_BITMAP_MODE_X2APIC_APICV    2
 119
 120 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 121
 122 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 123 static int __read_mostly cpu_preemption_timer_multi;
 124 static bool __read_mostly enable_preemption_timer = 1;
 125 #ifdef CONFIG_X86_64
 126 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 127 #endif
 128
 129 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
 130 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
 131 #define KVM_VM_CR0_ALWAYS_ON                            \
 132         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST |      \
 133          X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
 134 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 135         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 136          | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
 137
 138 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
 139 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 140 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 141
 142 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 143
 144 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
 145         RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
 146         RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
 147         RTIT_STATUS_BYTECNT))
 148
 149 #define MSR_IA32_RTIT_OUTPUT_BASE_MASK \
 150         (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f)
 151
 152 /*
 153  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 154  * ple_gap:    upper bound on the amount of time between two successive
 155  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 156  *             According to test, this time is usually smaller than 128 cycles.
 157  * ple_window: upper bound on the amount of time a guest is allowed to execute
 158  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 159  *             less than 2^12 cycles
 160  * Time is measured based on a counter that runs at the same rate as the TSC,
 161  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 162  */
 163 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
 164 module_param(ple_gap, uint, 0444);
 165
 166 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 167 module_param(ple_window, uint, 0444);
 168
 169 /* Default doubles per-vcpu window every exit. */
 170 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 171 module_param(ple_window_grow, uint, 0444);
 172
 173 /* Default resets per-vcpu window every exit to ple_window. */
 174 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 175 module_param(ple_window_shrink, uint, 0444);
 176
 177 /* Default is to compute the maximum so we can never overflow. */
 178 static unsigned int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 179 module_param(ple_window_max, uint, 0444);
 180
 181 /* Default is SYSTEM mode, 1 for host-guest mode */
 182 int __read_mostly pt_mode = PT_MODE_SYSTEM;
 183 module_param(pt_mode, int, S_IRUGO);
 184
 185 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
 186 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
 187 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
 188
 189 /* Storage for pre module init parameter parsing */
 190 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
 191
 192 static const struct {
 193         const char *option;
 194         bool for_parse;
 195 } vmentry_l1d_param[] = {
 196         [VMENTER_L1D_FLUSH_AUTO]         = {"auto", true},
 197         [VMENTER_L1D_FLUSH_NEVER]        = {"never", true},
 198         [VMENTER_L1D_FLUSH_COND]         = {"cond", true},
 199         [VMENTER_L1D_FLUSH_ALWAYS]       = {"always", true},
 200         [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
 201         [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
 202 };
 203
 204 #define L1D_CACHE_ORDER 4
 205 static void *vmx_l1d_flush_pages;
 206
 207 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
 208 {
 209         struct page *page;
 210         unsigned int i;
 211
 212         if (!boot_cpu_has_bug(X86_BUG_L1TF)) {
 213                 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
 214                 return 0;
 215         }
 216
 217         if (!enable_ept) {
 218                 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
 219                 return 0;
 220         }
 221
 222         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
 223                 u64 msr;
 224
 225                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
 226                 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
 227                         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
 228                         return 0;
 229                 }
 230         }
 231
 232         /* If set to auto use the default l1tf mitigation method */
 233         if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
 234                 switch (l1tf_mitigation) {
 235                 case L1TF_MITIGATION_OFF:
 236                         l1tf = VMENTER_L1D_FLUSH_NEVER;
 237                         break;
 238                 case L1TF_MITIGATION_FLUSH_NOWARN:
 239                 case L1TF_MITIGATION_FLUSH:
 240                 case L1TF_MITIGATION_FLUSH_NOSMT:
 241                         l1tf = VMENTER_L1D_FLUSH_COND;
 242                         break;
 243                 case L1TF_MITIGATION_FULL:
 244                 case L1TF_MITIGATION_FULL_FORCE:
 245                         l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 246                         break;
 247                 }
 248         } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
 249                 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 250         }
 251
 252         if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
 253             !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
 254                 /*
 255                  * This allocation for vmx_l1d_flush_pages is not tied to a VM
 256                  * lifetime and so should not be charged to a memcg.
 257                  */
 258                 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
 259                 if (!page)
 260                         return -ENOMEM;
 261                 vmx_l1d_flush_pages = page_address(page);
 262
 263                 /*
 264                  * Initialize each page with a different pattern in
 265                  * order to protect against KSM in the nested
 266                  * virtualization case.
 267                  */
 268                 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
 269                         memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
 270                                PAGE_SIZE);
 271                 }
 272         }
 273
 274         l1tf_vmx_mitigation = l1tf;
 275
 276         if (l1tf != VMENTER_L1D_FLUSH_NEVER)
 277                 static_branch_enable(&vmx_l1d_should_flush);
 278         else
 279                 static_branch_disable(&vmx_l1d_should_flush);
 280
 281         if (l1tf == VMENTER_L1D_FLUSH_COND)
 282                 static_branch_enable(&vmx_l1d_flush_cond);
 283         else
 284                 static_branch_disable(&vmx_l1d_flush_cond);
 285         return 0;
 286 }
 287
 288 static int vmentry_l1d_flush_parse(const char *s)
 289 {
 290         unsigned int i;
 291
 292         if (s) {
 293                 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
 294                         if (vmentry_l1d_param[i].for_parse &&
 295                             sysfs_streq(s, vmentry_l1d_param[i].option))
 296                                 return i;
 297                 }
 298         }
 299         return -EINVAL;
 300 }
 301
 302 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
 303 {
 304         int l1tf, ret;
 305
 306         l1tf = vmentry_l1d_flush_parse(s);
 307         if (l1tf < 0)
 308                 return l1tf;
 309
 310         if (!boot_cpu_has(X86_BUG_L1TF))
 311                 return 0;
 312
 313         /*
 314          * Has vmx_init() run already? If not then this is the pre init
 315          * parameter parsing. In that case just store the value and let
 316          * vmx_init() do the proper setup after enable_ept has been
 317          * established.
 318          */
 319         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
 320                 vmentry_l1d_flush_param = l1tf;
 321                 return 0;
 322         }
 323
 324         mutex_lock(&vmx_l1d_flush_mutex);
 325         ret = vmx_setup_l1d_flush(l1tf);
 326         mutex_unlock(&vmx_l1d_flush_mutex);
 327         return ret;
 328 }
 329
 330 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
 331 {
 332         if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
 333                 return sprintf(s, "???\n");
 334
 335         return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
 336 }
 337
 338 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
 339         .set = vmentry_l1d_flush_set,
 340         .get = vmentry_l1d_flush_get,
 341 };
 342 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
 343
 344 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 345 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 346 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
 347                                                           u32 msr, int type);
 348
 349 void vmx_vmexit(void);
 350
 351 #define vmx_insn_failed(fmt...)         \
 352 do {                                    \
 353         WARN_ONCE(1, fmt);              \
 354         pr_warn_ratelimited(fmt);       \
 355 } while (0)
 356
 357 asmlinkage void vmread_error(unsigned long field, bool fault)
 358 {
 359         if (fault)
 360                 kvm_spurious_fault();
 361         else
 362                 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field);
 363 }
 364
 365 noinline void vmwrite_error(unsigned long field, unsigned long value)
 366 {
 367         vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n",
 368                         field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 369 }
 370
 371 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr)
 372 {
 373         vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr);
 374 }
 375
 376 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr)
 377 {
 378         vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr);
 379 }
 380
 381 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva)
 382 {
 383         vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n",
 384                         ext, vpid, gva);
 385 }
 386
 387 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa)
 388 {
 389         vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n",
 390                         ext, eptp, gpa);
 391 }
 392
 393 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 394 DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 395 /*
 396  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 397  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 398  */
 399 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 400
 401 /*
 402  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 403  * can find which vCPU should be waken up.
 404  */
 405 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 406 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 407
 408 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 409 static DEFINE_SPINLOCK(vmx_vpid_lock);
 410
 411 struct vmcs_config vmcs_config;
 412 struct vmx_capability vmx_capability;
 413
 414 #define VMX_SEGMENT_FIELD(seg)                                  \
 415         [VCPU_SREG_##seg] = {                                   \
 416                 .selector = GUEST_##seg##_SELECTOR,             \
 417                 .base = GUEST_##seg##_BASE,                     \
 418                 .limit = GUEST_##seg##_LIMIT,                   \
 419                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 420         }
 421
 422 static const struct kvm_vmx_segment_field {
 423         unsigned selector;
 424         unsigned base;
 425         unsigned limit;
 426         unsigned ar_bytes;
 427 } kvm_vmx_segment_fields[] = {
 428         VMX_SEGMENT_FIELD(CS),
 429         VMX_SEGMENT_FIELD(DS),
 430         VMX_SEGMENT_FIELD(ES),
 431         VMX_SEGMENT_FIELD(FS),
 432         VMX_SEGMENT_FIELD(GS),
 433         VMX_SEGMENT_FIELD(SS),
 434         VMX_SEGMENT_FIELD(TR),
 435         VMX_SEGMENT_FIELD(LDTR),
 436 };
 437
 438 static unsigned long host_idt_base;
 439
 440 /*
 441  * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
 442  * will emulate SYSCALL in legacy mode if the vendor string in guest
 443  * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
 444  * support this emulation, IA32_STAR must always be included in
 445  * vmx_msr_index[], even in i386 builds.
 446  */
 447 const u32 vmx_msr_index[] = {
 448 #ifdef CONFIG_X86_64
 449         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 450 #endif
 451         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 452         MSR_IA32_TSX_CTRL,
 453 };
 454
 455 #if IS_ENABLED(CONFIG_HYPERV)
 456 static bool __read_mostly enlightened_vmcs = true;
 457 module_param(enlightened_vmcs, bool, 0444);
 458
 459 /* check_ept_pointer() should be under protection of ept_pointer_lock. */
 460 static void check_ept_pointer_match(struct kvm *kvm)
 461 {
 462         struct kvm_vcpu *vcpu;
 463         u64 tmp_eptp = INVALID_PAGE;
 464         int i;
 465
 466         kvm_for_each_vcpu(i, vcpu, kvm) {
 467                 if (!VALID_PAGE(tmp_eptp)) {
 468                         tmp_eptp = to_vmx(vcpu)->ept_pointer;
 469                 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
 470                         to_kvm_vmx(kvm)->ept_pointers_match
 471                                 = EPT_POINTERS_MISMATCH;
 472                         return;
 473                 }
 474         }
 475
 476         to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
 477 }
 478
 479 static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush,
 480                 void *data)
 481 {
 482         struct kvm_tlb_range *range = data;
 483
 484         return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn,
 485                         range->pages);
 486 }
 487
 488 static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm,
 489                 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range)
 490 {
 491         u64 ept_pointer = to_vmx(vcpu)->ept_pointer;
 492
 493         /*
 494          * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address
 495          * of the base of EPT PML4 table, strip off EPT configuration
 496          * information.
 497          */
 498         if (range)
 499                 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK,
 500                                 kvm_fill_hv_flush_list_func, (void *)range);
 501         else
 502                 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK);
 503 }
 504
 505 static int hv_remote_flush_tlb_with_range(struct kvm *kvm,
 506                 struct kvm_tlb_range *range)
 507 {
 508         struct kvm_vcpu *vcpu;
 509         int ret = 0, i;
 510
 511         spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
 512
 513         if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
 514                 check_ept_pointer_match(kvm);
 515
 516         if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
 517                 kvm_for_each_vcpu(i, vcpu, kvm) {
 518                         /* If ept_pointer is invalid pointer, bypass flush request. */
 519                         if (VALID_PAGE(to_vmx(vcpu)->ept_pointer))
 520                                 ret |= __hv_remote_flush_tlb_with_range(
 521                                         kvm, vcpu, range);
 522                 }
 523         } else {
 524                 ret = __hv_remote_flush_tlb_with_range(kvm,
 525                                 kvm_get_vcpu(kvm, 0), range);
 526         }
 527
 528         spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
 529         return ret;
 530 }
 531 static int hv_remote_flush_tlb(struct kvm *kvm)
 532 {
 533         return hv_remote_flush_tlb_with_range(kvm, NULL);
 534 }
 535
 536 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
 537 {
 538         struct hv_enlightened_vmcs *evmcs;
 539         struct hv_partition_assist_pg **p_hv_pa_pg =
 540                         &vcpu->kvm->arch.hyperv.hv_pa_pg;
 541         /*
 542          * Synthetic VM-Exit is not enabled in current code and so All
 543          * evmcs in singe VM shares same assist page.
 544          */
 545         if (!*p_hv_pa_pg)
 546                 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL);
 547
 548         if (!*p_hv_pa_pg)
 549                 return -ENOMEM;
 550
 551         evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
 552
 553         evmcs->partition_assist_page =
 554                 __pa(*p_hv_pa_pg);
 555         evmcs->hv_vm_id = (unsigned long)vcpu->kvm;
 556         evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
 557
 558         return 0;
 559 }
 560
 561 #endif /* IS_ENABLED(CONFIG_HYPERV) */
 562
 563 /*
 564  * Comment's format: document - errata name - stepping - processor name.
 565  * Refer from
 566  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
 567  */
 568 static u32 vmx_preemption_cpu_tfms[] = {
 569 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
 570 0x000206E6,
 571 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
 572 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
 573 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
 574 0x00020652,
 575 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
 576 0x00020655,
 577 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
 578 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
 579 /*
 580  * 320767.pdf - AAP86  - B1 -
 581  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
 582  */
 583 0x000106E5,
 584 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
 585 0x000106A0,
 586 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
 587 0x000106A1,
 588 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
 589 0x000106A4,
 590  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
 591  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
 592  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
 593 0x000106A5,
 594  /* Xeon E3-1220 V2 */
 595 0x000306A8,
 596 };
 597
 598 static inline bool cpu_has_broken_vmx_preemption_timer(void)
 599 {
 600         u32 eax = cpuid_eax(0x00000001), i;
 601
 602         /* Clear the reserved bits */
 603         eax &= ~(0x3U << 14 | 0xfU << 28);
 604         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
 605                 if (eax == vmx_preemption_cpu_tfms[i])
 606                         return true;
 607
 608         return false;
 609 }
 610
 611 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
 612 {
 613         return flexpriority_enabled && lapic_in_kernel(vcpu);
 614 }
 615
 616 static inline bool report_flexpriority(void)
 617 {
 618         return flexpriority_enabled;
 619 }
 620
 621 static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 622 {
 623         int i;
 624
 625         for (i = 0; i < vmx->nmsrs; ++i)
 626                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 627                         return i;
 628         return -1;
 629 }
 630
 631 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 632 {
 633         int i;
 634
 635         i = __find_msr_index(vmx, msr);
 636         if (i >= 0)
 637                 return &vmx->guest_msrs[i];
 638         return NULL;
 639 }
 640
 641 static int vmx_set_guest_msr(struct vcpu_vmx *vmx, struct shared_msr_entry *msr, u64 data)
 642 {
 643         int ret = 0;
 644
 645         u64 old_msr_data = msr->data;
 646         msr->data = data;
 647         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
 648                 preempt_disable();
 649                 ret = kvm_set_shared_msr(msr->index, msr->data,
 650                                          msr->mask);
 651                 preempt_enable();
 652                 if (ret)
 653                         msr->data = old_msr_data;
 654         }
 655         return ret;
 656 }
 657
 658 #ifdef CONFIG_KEXEC_CORE
 659 static void crash_vmclear_local_loaded_vmcss(void)
 660 {
 661         int cpu = raw_smp_processor_id();
 662         struct loaded_vmcs *v;
 663
 664         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
 665                             loaded_vmcss_on_cpu_link)
 666                 vmcs_clear(v->vmcs);
 667 }
 668 #endif /* CONFIG_KEXEC_CORE */
 669
 670 static void __loaded_vmcs_clear(void *arg)
 671 {
 672         struct loaded_vmcs *loaded_vmcs = arg;
 673         int cpu = raw_smp_processor_id();
 674
 675         if (loaded_vmcs->cpu != cpu)
 676                 return; /* vcpu migration can race with cpu offline */
 677         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
 678                 per_cpu(current_vmcs, cpu) = NULL;
 679
 680         vmcs_clear(loaded_vmcs->vmcs);
 681         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
 682                 vmcs_clear(loaded_vmcs->shadow_vmcs);
 683
 684         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
 685
 686         /*
 687          * Ensure all writes to loaded_vmcs, including deleting it from its
 688          * current percpu list, complete before setting loaded_vmcs->vcpu to
 689          * -1, otherwise a different cpu can see vcpu == -1 first and add
 690          * loaded_vmcs to its percpu list before it's deleted from this cpu's
 691          * list. Pairs with the smp_rmb() in vmx_vcpu_load_vmcs().
 692          */
 693         smp_wmb();
 694
 695         loaded_vmcs->cpu = -1;
 696         loaded_vmcs->launched = 0;
 697 }
 698
 699 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
 700 {
 701         int cpu = loaded_vmcs->cpu;
 702
 703         if (cpu != -1)
 704                 smp_call_function_single(cpu,
 705                          __loaded_vmcs_clear, loaded_vmcs, 1);
 706 }
 707
 708 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
 709                                        unsigned field)
 710 {
 711         bool ret;
 712         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
 713
 714         if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) {
 715                 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS);
 716                 vmx->segment_cache.bitmask = 0;
 717         }
 718         ret = vmx->segment_cache.bitmask & mask;
 719         vmx->segment_cache.bitmask |= mask;
 720         return ret;
 721 }
 722
 723 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
 724 {
 725         u16 *p = &vmx->segment_cache.seg[seg].selector;
 726
 727         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
 728                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
 729         return *p;
 730 }
 731
 732 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
 733 {
 734         ulong *p = &vmx->segment_cache.seg[seg].base;
 735
 736         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
 737                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
 738         return *p;
 739 }
 740
 741 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
 742 {
 743         u32 *p = &vmx->segment_cache.seg[seg].limit;
 744
 745         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
 746                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
 747         return *p;
 748 }
 749
 750 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
 751 {
 752         u32 *p = &vmx->segment_cache.seg[seg].ar;
 753
 754         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
 755                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
 756         return *p;
 757 }
 758
 759 void update_exception_bitmap(struct kvm_vcpu *vcpu)
 760 {
 761         u32 eb;
 762
 763         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
 764              (1u << DB_VECTOR) | (1u << AC_VECTOR);
 765         /*
 766          * Guest access to VMware backdoor ports could legitimately
 767          * trigger #GP because of TSS I/O permission bitmap.
 768          * We intercept those #GP and allow access to them anyway
 769          * as VMware does.
 770          */
 771         if (enable_vmware_backdoor)
 772                 eb |= (1u << GP_VECTOR);
 773         if ((vcpu->guest_debug &
 774              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
 775             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
 776                 eb |= 1u << BP_VECTOR;
 777         if (to_vmx(vcpu)->rmode.vm86_active)
 778                 eb = ~0;
 779         if (enable_ept)
 780                 eb &= ~(1u << PF_VECTOR);
 781
 782         /* When we are running a nested L2 guest and L1 specified for it a
 783          * certain exception bitmap, we must trap the same exceptions and pass
 784          * them to L1. When running L2, we will only handle the exceptions
 785          * specified above if L1 did not want them.
 786          */
 787         if (is_guest_mode(vcpu))
 788                 eb |= get_vmcs12(vcpu)->exception_bitmap;
 789
 790         vmcs_write32(EXCEPTION_BITMAP, eb);
 791 }
 792
 793 /*
 794  * Check if MSR is intercepted for currently loaded MSR bitmap.
 795  */
 796 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
 797 {
 798         unsigned long *msr_bitmap;
 799         int f = sizeof(unsigned long);
 800
 801         if (!cpu_has_vmx_msr_bitmap())
 802                 return true;
 803
 804         msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
 805
 806         if (msr <= 0x1fff) {
 807                 return !!test_bit(msr, msr_bitmap + 0x800 / f);
 808         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
 809                 msr &= 0x1fff;
 810                 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
 811         }
 812
 813         return true;
 814 }
 815
 816 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
 817                 unsigned long entry, unsigned long exit)
 818 {
 819         vm_entry_controls_clearbit(vmx, entry);
 820         vm_exit_controls_clearbit(vmx, exit);
 821 }
 822
 823 int vmx_find_msr_index(struct vmx_msrs *m, u32 msr)
 824 {
 825         unsigned int i;
 826
 827         for (i = 0; i < m->nr; ++i) {
 828                 if (m->val[i].index == msr)
 829                         return i;
 830         }
 831         return -ENOENT;
 832 }
 833
 834 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
 835 {
 836         int i;
 837         struct msr_autoload *m = &vmx->msr_autoload;
 838
 839         switch (msr) {
 840         case MSR_EFER:
 841                 if (cpu_has_load_ia32_efer()) {
 842                         clear_atomic_switch_msr_special(vmx,
 843                                         VM_ENTRY_LOAD_IA32_EFER,
 844                                         VM_EXIT_LOAD_IA32_EFER);
 845                         return;
 846                 }
 847                 break;
 848         case MSR_CORE_PERF_GLOBAL_CTRL:
 849                 if (cpu_has_load_perf_global_ctrl()) {
 850                         clear_atomic_switch_msr_special(vmx,
 851                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
 852                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
 853                         return;
 854                 }
 855                 break;
 856         }
 857         i = vmx_find_msr_index(&m->guest, msr);
 858         if (i < 0)
 859                 goto skip_guest;
 860         --m->guest.nr;
 861         m->guest.val[i] = m->guest.val[m->guest.nr];
 862         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
 863
 864 skip_guest:
 865         i = vmx_find_msr_index(&m->host, msr);
 866         if (i < 0)
 867                 return;
 868
 869         --m->host.nr;
 870         m->host.val[i] = m->host.val[m->host.nr];
 871         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
 872 }
 873
 874 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
 875                 unsigned long entry, unsigned long exit,
 876                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
 877                 u64 guest_val, u64 host_val)
 878 {
 879         vmcs_write64(guest_val_vmcs, guest_val);
 880         if (host_val_vmcs != HOST_IA32_EFER)
 881                 vmcs_write64(host_val_vmcs, host_val);
 882         vm_entry_controls_setbit(vmx, entry);
 883         vm_exit_controls_setbit(vmx, exit);
 884 }
 885
 886 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
 887                                   u64 guest_val, u64 host_val, bool entry_only)
 888 {
 889         int i, j = 0;
 890         struct msr_autoload *m = &vmx->msr_autoload;
 891
 892         switch (msr) {
 893         case MSR_EFER:
 894                 if (cpu_has_load_ia32_efer()) {
 895                         add_atomic_switch_msr_special(vmx,
 896                                         VM_ENTRY_LOAD_IA32_EFER,
 897                                         VM_EXIT_LOAD_IA32_EFER,
 898                                         GUEST_IA32_EFER,
 899                                         HOST_IA32_EFER,
 900                                         guest_val, host_val);
 901                         return;
 902                 }
 903                 break;
 904         case MSR_CORE_PERF_GLOBAL_CTRL:
 905                 if (cpu_has_load_perf_global_ctrl()) {
 906                         add_atomic_switch_msr_special(vmx,
 907                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
 908                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
 909                                         GUEST_IA32_PERF_GLOBAL_CTRL,
 910                                         HOST_IA32_PERF_GLOBAL_CTRL,
 911                                         guest_val, host_val);
 912                         return;
 913                 }
 914                 break;
 915         case MSR_IA32_PEBS_ENABLE:
 916                 /* PEBS needs a quiescent period after being disabled (to write
 917                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
 918                  * provide that period, so a CPU could write host's record into
 919                  * guest's memory.
 920                  */
 921                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
 922         }
 923
 924         i = vmx_find_msr_index(&m->guest, msr);
 925         if (!entry_only)
 926                 j = vmx_find_msr_index(&m->host, msr);
 927
 928         if ((i < 0 && m->guest.nr == NR_LOADSTORE_MSRS) ||
 929                 (j < 0 &&  m->host.nr == NR_LOADSTORE_MSRS)) {
 930                 printk_once(KERN_WARNING "Not enough msr switch entries. "
 931                                 "Can't add msr %x\n", msr);
 932                 return;
 933         }
 934         if (i < 0) {
 935                 i = m->guest.nr++;
 936                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
 937         }
 938         m->guest.val[i].index = msr;
 939         m->guest.val[i].value = guest_val;
 940
 941         if (entry_only)
 942                 return;
 943
 944         if (j < 0) {
 945                 j = m->host.nr++;
 946                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
 947         }
 948         m->host.val[j].index = msr;
 949         m->host.val[j].value = host_val;
 950 }
 951
 952 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
 953 {
 954         u64 guest_efer = vmx->vcpu.arch.efer;
 955         u64 ignore_bits = 0;
 956
 957         /* Shadow paging assumes NX to be available.  */
 958         if (!enable_ept)
 959                 guest_efer |= EFER_NX;
 960
 961         /*
 962          * LMA and LME handled by hardware; SCE meaningless outside long mode.
 963          */
 964         ignore_bits |= EFER_SCE;
 965 #ifdef CONFIG_X86_64
 966         ignore_bits |= EFER_LMA | EFER_LME;
 967         /* SCE is meaningful only in long mode on Intel */
 968         if (guest_efer & EFER_LMA)
 969                 ignore_bits &= ~(u64)EFER_SCE;
 970 #endif
 971
 972         /*
 973          * On EPT, we can't emulate NX, so we must switch EFER atomically.
 974          * On CPUs that support "load IA32_EFER", always switch EFER
 975          * atomically, since it's faster than switching it manually.
 976          */
 977         if (cpu_has_load_ia32_efer() ||
 978             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
 979                 if (!(guest_efer & EFER_LMA))
 980                         guest_efer &= ~EFER_LME;
 981                 if (guest_efer != host_efer)
 982                         add_atomic_switch_msr(vmx, MSR_EFER,
 983                                               guest_efer, host_efer, false);
 984                 else
 985                         clear_atomic_switch_msr(vmx, MSR_EFER);
 986                 return false;
 987         } else {
 988                 clear_atomic_switch_msr(vmx, MSR_EFER);
 989
 990                 guest_efer &= ~ignore_bits;
 991                 guest_efer |= host_efer & ignore_bits;
 992
 993                 vmx->guest_msrs[efer_offset].data = guest_efer;
 994                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
 995
 996                 return true;
 997         }
 998 }
 999
1000 #ifdef CONFIG_X86_32
1001 /*
1002  * On 32-bit kernels, VM exits still load the FS and GS bases from the
1003  * VMCS rather than the segment table.  KVM uses this helper to figure
1004  * out the current bases to poke them into the VMCS before entry.
1005  */
1006 static unsigned long segment_base(u16 selector)
1007 {
1008         struct desc_struct *table;
1009         unsigned long v;
1010
1011         if (!(selector & ~SEGMENT_RPL_MASK))
1012                 return 0;
1013
1014         table = get_current_gdt_ro();
1015
1016         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
1017                 u16 ldt_selector = kvm_read_ldt();
1018
1019                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
1020                         return 0;
1021
1022                 table = (struct desc_struct *)segment_base(ldt_selector);
1023         }
1024         v = get_desc_base(&table[selector >> 3]);
1025         return v;
1026 }
1027 #endif
1028
1029 static inline bool pt_can_write_msr(struct vcpu_vmx *vmx)
1030 {
1031         return vmx_pt_mode_is_host_guest() &&
1032                !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
1033 }
1034
1035 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
1036 {
1037         u32 i;
1038
1039         wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1040         wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1041         wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1042         wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1043         for (i = 0; i < addr_range; i++) {
1044                 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1045                 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1046         }
1047 }
1048
1049 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
1050 {
1051         u32 i;
1052
1053         rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1054         rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1055         rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1056         rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1057         for (i = 0; i < addr_range; i++) {
1058                 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1059                 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1060         }
1061 }
1062
1063 static void pt_guest_enter(struct vcpu_vmx *vmx)
1064 {
1065         if (vmx_pt_mode_is_system())
1066                 return;
1067
1068         /*
1069          * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1070          * Save host state before VM entry.
1071          */
1072         rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1073         if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1074                 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1075                 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1076                 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1077         }
1078 }
1079
1080 static void pt_guest_exit(struct vcpu_vmx *vmx)
1081 {
1082         if (vmx_pt_mode_is_system())
1083                 return;
1084
1085         if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1086                 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1087                 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1088         }
1089
1090         /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1091         wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1092 }
1093
1094 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1095                         unsigned long fs_base, unsigned long gs_base)
1096 {
1097         if (unlikely(fs_sel != host->fs_sel)) {
1098                 if (!(fs_sel & 7))
1099                         vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1100                 else
1101                         vmcs_write16(HOST_FS_SELECTOR, 0);
1102                 host->fs_sel = fs_sel;
1103         }
1104         if (unlikely(gs_sel != host->gs_sel)) {
1105                 if (!(gs_sel & 7))
1106                         vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1107                 else
1108                         vmcs_write16(HOST_GS_SELECTOR, 0);
1109                 host->gs_sel = gs_sel;
1110         }
1111         if (unlikely(fs_base != host->fs_base)) {
1112                 vmcs_writel(HOST_FS_BASE, fs_base);
1113                 host->fs_base = fs_base;
1114         }
1115         if (unlikely(gs_base != host->gs_base)) {
1116                 vmcs_writel(HOST_GS_BASE, gs_base);
1117                 host->gs_base = gs_base;
1118         }
1119 }
1120
1121 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1122 {
1123         struct vcpu_vmx *vmx = to_vmx(vcpu);
1124         struct vmcs_host_state *host_state;
1125 #ifdef CONFIG_X86_64
1126         int cpu = raw_smp_processor_id();
1127 #endif
1128         unsigned long fs_base, gs_base;
1129         u16 fs_sel, gs_sel;
1130         int i;
1131
1132         vmx->req_immediate_exit = false;
1133
1134         /*
1135          * Note that guest MSRs to be saved/restored can also be changed
1136          * when guest state is loaded. This happens when guest transitions
1137          * to/from long-mode by setting MSR_EFER.LMA.
1138          */
1139         if (!vmx->guest_msrs_ready) {
1140                 vmx->guest_msrs_ready = true;
1141                 for (i = 0; i < vmx->save_nmsrs; ++i)
1142                         kvm_set_shared_msr(vmx->guest_msrs[i].index,
1143                                            vmx->guest_msrs[i].data,
1144                                            vmx->guest_msrs[i].mask);
1145
1146         }
1147
1148         if (vmx->nested.need_vmcs12_to_shadow_sync)
1149                 nested_sync_vmcs12_to_shadow(vcpu);
1150
1151         if (vmx->guest_state_loaded)
1152                 return;
1153
1154         host_state = &vmx->loaded_vmcs->host_state;
1155
1156         /*
1157          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1158          * allow segment selectors with cpl > 0 or ti == 1.
1159          */
1160         host_state->ldt_sel = kvm_read_ldt();
1161
1162 #ifdef CONFIG_X86_64
1163         savesegment(ds, host_state->ds_sel);
1164         savesegment(es, host_state->es_sel);
1165
1166         gs_base = cpu_kernelmode_gs_base(cpu);
1167         if (likely(is_64bit_mm(current->mm))) {
1168                 save_fsgs_for_kvm();
1169                 fs_sel = current->thread.fsindex;
1170                 gs_sel = current->thread.gsindex;
1171                 fs_base = current->thread.fsbase;
1172                 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
1173         } else {
1174                 savesegment(fs, fs_sel);
1175                 savesegment(gs, gs_sel);
1176                 fs_base = read_msr(MSR_FS_BASE);
1177                 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
1178         }
1179
1180         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1181 #else
1182         savesegment(fs, fs_sel);
1183         savesegment(gs, gs_sel);
1184         fs_base = segment_base(fs_sel);
1185         gs_base = segment_base(gs_sel);
1186 #endif
1187
1188         vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
1189         vmx->guest_state_loaded = true;
1190 }
1191
1192 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
1193 {
1194         struct vmcs_host_state *host_state;
1195
1196         if (!vmx->guest_state_loaded)
1197                 return;
1198
1199         host_state = &vmx->loaded_vmcs->host_state;
1200
1201         ++vmx->vcpu.stat.host_state_reload;
1202
1203 #ifdef CONFIG_X86_64
1204         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1205 #endif
1206         if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1207                 kvm_load_ldt(host_state->ldt_sel);
1208 #ifdef CONFIG_X86_64
1209                 load_gs_index(host_state->gs_sel);
1210 #else
1211                 loadsegment(gs, host_state->gs_sel);
1212 #endif
1213         }
1214         if (host_state->fs_sel & 7)
1215                 loadsegment(fs, host_state->fs_sel);
1216 #ifdef CONFIG_X86_64
1217         if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1218                 loadsegment(ds, host_state->ds_sel);
1219                 loadsegment(es, host_state->es_sel);
1220         }
1221 #endif
1222         invalidate_tss_limit();
1223 #ifdef CONFIG_X86_64
1224         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1225 #endif
1226         load_fixmap_gdt(raw_smp_processor_id());
1227         vmx->guest_state_loaded = false;
1228         vmx->guest_msrs_ready = false;
1229 }
1230
1231 #ifdef CONFIG_X86_64
1232 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
1233 {
1234         preempt_disable();
1235         if (vmx->guest_state_loaded)
1236                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1237         preempt_enable();
1238         return vmx->msr_guest_kernel_gs_base;
1239 }
1240
1241 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1242 {
1243         preempt_disable();
1244         if (vmx->guest_state_loaded)
1245                 wrmsrl(MSR_KERNEL_GS_BASE, data);
1246         preempt_enable();
1247         vmx->msr_guest_kernel_gs_base = data;
1248 }
1249 #endif
1250
1251 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1252 {
1253         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1254         struct pi_desc old, new;
1255         unsigned int dest;
1256
1257         /*
1258          * In case of hot-plug or hot-unplug, we may have to undo
1259          * vmx_vcpu_pi_put even if there is no assigned device.  And we
1260          * always keep PI.NDST up to date for simplicity: it makes the
1261          * code easier, and CPU migration is not a fast path.
1262          */
1263         if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
1264                 return;
1265
1266         /*
1267          * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
1268          * PI.NDST: pi_post_block is the one expected to change PID.NDST and the
1269          * wakeup handler expects the vCPU to be on the blocked_vcpu_list that
1270          * matches PI.NDST. Otherwise, a vcpu may not be able to be woken up
1271          * correctly.
1272          */
1273         if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || vcpu->cpu == cpu) {
1274                 pi_clear_sn(pi_desc);
1275                 goto after_clear_sn;
1276         }
1277
1278         /* The full case.  */
1279         do {
1280                 old.control = new.control = pi_desc->control;
1281
1282                 dest = cpu_physical_id(cpu);
1283
1284                 if (x2apic_enabled())
1285                         new.ndst = dest;
1286                 else
1287                         new.ndst = (dest << 8) & 0xFF00;
1288
1289                 new.sn = 0;
1290         } while (cmpxchg64(&pi_desc->control, old.control,
1291                            new.control) != old.control);
1292
1293 after_clear_sn:
1294
1295         /*
1296          * Clear SN before reading the bitmap.  The VT-d firmware
1297          * writes the bitmap and reads SN atomically (5.2.3 in the
1298          * spec), so it doesn't really have a memory barrier that
1299          * pairs with this, but we cannot do that and we need one.
1300          */
1301         smp_mb__after_atomic();
1302
1303         if (!pi_is_pir_empty(pi_desc))
1304                 pi_set_on(pi_desc);
1305 }
1306
1307 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu)
1308 {
1309         struct vcpu_vmx *vmx = to_vmx(vcpu);
1310         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
1311
1312         if (!already_loaded) {
1313                 loaded_vmcs_clear(vmx->loaded_vmcs);
1314                 local_irq_disable();
1315
1316                 /*
1317                  * Ensure loaded_vmcs->cpu is read before adding loaded_vmcs to
1318                  * this cpu's percpu list, otherwise it may not yet be deleted
1319                  * from its previous cpu's percpu list.  Pairs with the
1320                  * smb_wmb() in __loaded_vmcs_clear().
1321                  */
1322                 smp_rmb();
1323
1324                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1325                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1326                 local_irq_enable();
1327         }
1328
1329         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1330                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1331                 vmcs_load(vmx->loaded_vmcs->vmcs);
1332                 indirect_branch_prediction_barrier();
1333         }
1334
1335         if (!already_loaded) {
1336                 void *gdt = get_current_gdt_ro();
1337                 unsigned long sysenter_esp;
1338
1339                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1340
1341                 /*
1342                  * Linux uses per-cpu TSS and GDT, so set these when switching
1343                  * processors.  See 22.2.4.
1344                  */
1345                 vmcs_writel(HOST_TR_BASE,
1346                             (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
1347                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
1348
1349                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1350                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1351
1352                 vmx->loaded_vmcs->cpu = cpu;
1353         }
1354
1355         /* Setup TSC multiplier */
1356         if (kvm_has_tsc_control &&
1357             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
1358                 decache_tsc_multiplier(vmx);
1359 }
1360
1361 /*
1362  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1363  * vcpu mutex is already taken.
1364  */
1365 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1366 {
1367         struct vcpu_vmx *vmx = to_vmx(vcpu);
1368
1369         vmx_vcpu_load_vmcs(vcpu, cpu);
1370
1371         vmx_vcpu_pi_load(vcpu, cpu);
1372
1373         vmx->host_pkru = read_pkru();
1374         vmx->host_debugctlmsr = get_debugctlmsr();
1375 }
1376
1377 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
1378 {
1379         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1380
1381         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1382                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
1383                 !kvm_vcpu_apicv_active(vcpu))
1384                 return;
1385
1386         /* Set SN when the vCPU is preempted */
1387         if (vcpu->preempted)
1388                 pi_set_sn(pi_desc);
1389 }
1390
1391 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1392 {
1393         vmx_vcpu_pi_put(vcpu);
1394
1395         vmx_prepare_switch_to_host(to_vmx(vcpu));
1396 }
1397
1398 static bool emulation_required(struct kvm_vcpu *vcpu)
1399 {
1400         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
1401 }
1402
1403 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1404 {
1405         struct vcpu_vmx *vmx = to_vmx(vcpu);
1406         unsigned long rflags, save_rflags;
1407
1408         if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) {
1409                 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1410                 rflags = vmcs_readl(GUEST_RFLAGS);
1411                 if (vmx->rmode.vm86_active) {
1412                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1413                         save_rflags = vmx->rmode.save_rflags;
1414                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1415                 }
1416                 vmx->rflags = rflags;
1417         }
1418         return vmx->rflags;
1419 }
1420
1421 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1422 {
1423         struct vcpu_vmx *vmx = to_vmx(vcpu);
1424         unsigned long old_rflags;
1425
1426         if (enable_unrestricted_guest) {
1427                 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1428                 vmx->rflags = rflags;
1429                 vmcs_writel(GUEST_RFLAGS, rflags);
1430                 return;
1431         }
1432
1433         old_rflags = vmx_get_rflags(vcpu);
1434         vmx->rflags = rflags;
1435         if (vmx->rmode.vm86_active) {
1436                 vmx->rmode.save_rflags = rflags;
1437                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1438         }
1439         vmcs_writel(GUEST_RFLAGS, rflags);
1440
1441         if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM)
1442                 vmx->emulation_required = emulation_required(vcpu);
1443 }
1444
1445 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1446 {
1447         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1448         int ret = 0;
1449
1450         if (interruptibility & GUEST_INTR_STATE_STI)
1451                 ret |= KVM_X86_SHADOW_INT_STI;
1452         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1453                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1454
1455         return ret;
1456 }
1457
1458 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1459 {
1460         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1461         u32 interruptibility = interruptibility_old;
1462
1463         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1464
1465         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1466                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1467         else if (mask & KVM_X86_SHADOW_INT_STI)
1468                 interruptibility |= GUEST_INTR_STATE_STI;
1469
1470         if ((interruptibility != interruptibility_old))
1471                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1472 }
1473
1474 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1475 {
1476         struct vcpu_vmx *vmx = to_vmx(vcpu);
1477         unsigned long value;
1478
1479         /*
1480          * Any MSR write that attempts to change bits marked reserved will
1481          * case a #GP fault.
1482          */
1483         if (data & vmx->pt_desc.ctl_bitmask)
1484                 return 1;
1485
1486         /*
1487          * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1488          * result in a #GP unless the same write also clears TraceEn.
1489          */
1490         if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1491                 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1492                 return 1;
1493
1494         /*
1495          * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1496          * and FabricEn would cause #GP, if
1497          * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1498          */
1499         if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1500                 !(data & RTIT_CTL_FABRIC_EN) &&
1501                 !intel_pt_validate_cap(vmx->pt_desc.caps,
1502                                         PT_CAP_single_range_output))
1503                 return 1;
1504
1505         /*
1506          * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1507          * utilize encodings marked reserved will casue a #GP fault.
1508          */
1509         value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1510         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1511                         !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1512                         RTIT_CTL_MTC_RANGE_OFFSET, &value))
1513                 return 1;
1514         value = intel_pt_validate_cap(vmx->pt_desc.caps,
1515                                                 PT_CAP_cycle_thresholds);
1516         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1517                         !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1518                         RTIT_CTL_CYC_THRESH_OFFSET, &value))
1519                 return 1;
1520         value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1521         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1522                         !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1523                         RTIT_CTL_PSB_FREQ_OFFSET, &value))
1524                 return 1;
1525
1526         /*
1527          * If ADDRx_CFG is reserved or the encodings is >2 will
1528          * cause a #GP fault.
1529          */
1530         value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1531         if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
1532                 return 1;
1533         value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1534         if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
1535                 return 1;
1536         value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1537         if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
1538                 return 1;
1539         value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1540         if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
1541                 return 1;
1542
1543         return 0;
1544 }
1545
1546 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
1547 {
1548         unsigned long rip;
1549
1550         /*
1551          * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
1552          * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
1553          * set when EPT misconfig occurs.  In practice, real hardware updates
1554          * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
1555          * (namely Hyper-V) don't set it due to it being undefined behavior,
1556          * i.e. we end up advancing IP with some random value.
1557          */
1558         if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
1559             to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) {
1560                 rip = kvm_rip_read(vcpu);
1561                 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1562                 kvm_rip_write(vcpu, rip);
1563         } else {
1564                 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
1565                         return 0;
1566         }
1567
1568         /* skipping an emulated instruction also counts */
1569         vmx_set_interrupt_shadow(vcpu, 0);
1570
1571         return 1;
1572 }
1573
1574
1575 /*
1576  * Recognizes a pending MTF VM-exit and records the nested state for later
1577  * delivery.
1578  */
1579 static void vmx_update_emulated_instruction(struct kvm_vcpu *vcpu)
1580 {
1581         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1582         struct vcpu_vmx *vmx = to_vmx(vcpu);
1583
1584         if (!is_guest_mode(vcpu))
1585                 return;
1586
1587         /*
1588          * Per the SDM, MTF takes priority over debug-trap exceptions besides
1589          * T-bit traps. As instruction emulation is completed (i.e. at the
1590          * instruction boundary), any #DB exception pending delivery must be a
1591          * debug-trap. Record the pending MTF state to be delivered in
1592          * vmx_check_nested_events().
1593          */
1594         if (nested_cpu_has_mtf(vmcs12) &&
1595             (!vcpu->arch.exception.pending ||
1596              vcpu->arch.exception.nr == DB_VECTOR))
1597                 vmx->nested.mtf_pending = true;
1598         else
1599                 vmx->nested.mtf_pending = false;
1600 }
1601
1602 static int vmx_skip_emulated_instruction(struct kvm_vcpu *vcpu)
1603 {
1604         vmx_update_emulated_instruction(vcpu);
1605         return skip_emulated_instruction(vcpu);
1606 }
1607
1608 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1609 {
1610         /*
1611          * Ensure that we clear the HLT state in the VMCS.  We don't need to
1612          * explicitly skip the instruction because if the HLT state is set,
1613          * then the instruction is already executing and RIP has already been
1614          * advanced.
1615          */
1616         if (kvm_hlt_in_guest(vcpu->kvm) &&
1617                         vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1618                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1619 }
1620
1621 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
1622 {
1623         struct vcpu_vmx *vmx = to_vmx(vcpu);
1624         unsigned nr = vcpu->arch.exception.nr;
1625         bool has_error_code = vcpu->arch.exception.has_error_code;
1626         u32 error_code = vcpu->arch.exception.error_code;
1627         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1628
1629         kvm_deliver_exception_payload(vcpu);
1630
1631         if (has_error_code) {
1632                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1633                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1634         }
1635
1636         if (vmx->rmode.vm86_active) {
1637                 int inc_eip = 0;
1638                 if (kvm_exception_is_soft(nr))
1639                         inc_eip = vcpu->arch.event_exit_inst_len;
1640                 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
1641                 return;
1642         }
1643
1644         WARN_ON_ONCE(vmx->emulation_required);
1645
1646         if (kvm_exception_is_soft(nr)) {
1647                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1648                              vmx->vcpu.arch.event_exit_inst_len);
1649                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1650         } else
1651                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1652
1653         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1654
1655         vmx_clear_hlt(vcpu);
1656 }
1657
1658 /*
1659  * Swap MSR entry in host/guest MSR entry array.
1660  */
1661 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1662 {
1663         struct shared_msr_entry tmp;
1664
1665         tmp = vmx->guest_msrs[to];
1666         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1667         vmx->guest_msrs[from] = tmp;
1668 }
1669
1670 /*
1671  * Set up the vmcs to automatically save and restore system
1672  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1673  * mode, as fiddling with msrs is very expensive.
1674  */
1675 static void setup_msrs(struct vcpu_vmx *vmx)
1676 {
1677         int save_nmsrs, index;
1678
1679         save_nmsrs = 0;
1680 #ifdef CONFIG_X86_64
1681         /*
1682          * The SYSCALL MSRs are only needed on long mode guests, and only
1683          * when EFER.SCE is set.
1684          */
1685         if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) {
1686                 index = __find_msr_index(vmx, MSR_STAR);
1687                 if (index >= 0)
1688                         move_msr_up(vmx, index, save_nmsrs++);
1689                 index = __find_msr_index(vmx, MSR_LSTAR);
1690                 if (index >= 0)
1691                         move_msr_up(vmx, index, save_nmsrs++);
1692                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1693                 if (index >= 0)
1694                         move_msr_up(vmx, index, save_nmsrs++);
1695         }
1696 #endif
1697         index = __find_msr_index(vmx, MSR_EFER);
1698         if (index >= 0 && update_transition_efer(vmx, index))
1699                 move_msr_up(vmx, index, save_nmsrs++);
1700         index = __find_msr_index(vmx, MSR_TSC_AUX);
1701         if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
1702                 move_msr_up(vmx, index, save_nmsrs++);
1703         index = __find_msr_index(vmx, MSR_IA32_TSX_CTRL);
1704         if (index >= 0)
1705                 move_msr_up(vmx, index, save_nmsrs++);
1706
1707         vmx->save_nmsrs = save_nmsrs;
1708         vmx->guest_msrs_ready = false;
1709
1710         if (cpu_has_vmx_msr_bitmap())
1711                 vmx_update_msr_bitmap(&vmx->vcpu);
1712 }
1713
1714 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1715 {
1716         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1717
1718         if (is_guest_mode(vcpu) &&
1719             (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING))
1720                 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
1721
1722         return vcpu->arch.tsc_offset;
1723 }
1724
1725 static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1726 {
1727         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1728         u64 g_tsc_offset = 0;
1729
1730         /*
1731          * We're here if L1 chose not to trap WRMSR to TSC. According
1732          * to the spec, this should set L1's TSC; The offset that L1
1733          * set for L2 remains unchanged, and still needs to be added
1734          * to the newly set TSC to get L2's TSC.
1735          */
1736         if (is_guest_mode(vcpu) &&
1737             (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING))
1738                 g_tsc_offset = vmcs12->tsc_offset;
1739
1740         trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1741                                    vcpu->arch.tsc_offset - g_tsc_offset,
1742                                    offset);
1743         vmcs_write64(TSC_OFFSET, offset + g_tsc_offset);
1744         return offset + g_tsc_offset;
1745 }
1746
1747 /*
1748  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1749  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1750  * all guests if the "nested" module option is off, and can also be disabled
1751  * for a single guest by disabling its VMX cpuid bit.
1752  */
1753 bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1754 {
1755         return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
1756 }
1757
1758 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1759                                                  uint64_t val)
1760 {
1761         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
1762
1763         return !(val & ~valid_bits);
1764 }
1765
1766 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
1767 {
1768         switch (msr->index) {
1769         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1770                 if (!nested)
1771                         return 1;
1772                 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1773         default:
1774                 return 1;
1775         }
1776 }
1777
1778 /*
1779  * Reads an msr value (of 'msr_index') into 'pdata'.
1780  * Returns 0 on success, non-0 otherwise.
1781  * Assumes vcpu_load() was already called.
1782  */
1783 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1784 {
1785         struct vcpu_vmx *vmx = to_vmx(vcpu);
1786         struct shared_msr_entry *msr;
1787         u32 index;
1788
1789         switch (msr_info->index) {
1790 #ifdef CONFIG_X86_64
1791         case MSR_FS_BASE:
1792                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
1793                 break;
1794         case MSR_GS_BASE:
1795                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
1796                 break;
1797         case MSR_KERNEL_GS_BASE:
1798                 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
1799                 break;
1800 #endif
1801         case MSR_EFER:
1802                 return kvm_get_msr_common(vcpu, msr_info);
1803         case MSR_IA32_TSX_CTRL:
1804                 if (!msr_info->host_initiated &&
1805                     !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
1806                         return 1;
1807                 goto find_shared_msr;
1808         case MSR_IA32_UMWAIT_CONTROL:
1809                 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1810                         return 1;
1811
1812                 msr_info->data = vmx->msr_ia32_umwait_control;
1813                 break;
1814         case MSR_IA32_SPEC_CTRL:
1815                 if (!msr_info->host_initiated &&
1816                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1817                         return 1;
1818
1819                 msr_info->data = to_vmx(vcpu)->spec_ctrl;
1820                 break;
1821         case MSR_IA32_SYSENTER_CS:
1822                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
1823                 break;
1824         case MSR_IA32_SYSENTER_EIP:
1825                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
1826                 break;
1827         case MSR_IA32_SYSENTER_ESP:
1828                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
1829                 break;
1830         case MSR_IA32_BNDCFGS:
1831                 if (!kvm_mpx_supported() ||
1832                     (!msr_info->host_initiated &&
1833                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1834                         return 1;
1835                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
1836                 break;
1837         case MSR_IA32_MCG_EXT_CTL:
1838                 if (!msr_info->host_initiated &&
1839                     !(vmx->msr_ia32_feature_control &
1840                       FEAT_CTL_LMCE_ENABLED))
1841                         return 1;
1842                 msr_info->data = vcpu->arch.mcg_ext_ctl;
1843                 break;
1844         case MSR_IA32_FEAT_CTL:
1845                 msr_info->data = vmx->msr_ia32_feature_control;
1846                 break;
1847         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1848                 if (!nested_vmx_allowed(vcpu))
1849                         return 1;
1850                 if (vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1851                                     &msr_info->data))
1852                         return 1;
1853                 /*
1854                  * Enlightened VMCS v1 doesn't have certain fields, but buggy
1855                  * Hyper-V versions are still trying to use corresponding
1856                  * features when they are exposed. Filter out the essential
1857                  * minimum.
1858                  */
1859                 if (!msr_info->host_initiated &&
1860                     vmx->nested.enlightened_vmcs_enabled)
1861                         nested_evmcs_filter_control_msr(msr_info->index,
1862                                                         &msr_info->data);
1863                 break;
1864         case MSR_IA32_RTIT_CTL:
1865                 if (!vmx_pt_mode_is_host_guest())
1866                         return 1;
1867                 msr_info->data = vmx->pt_desc.guest.ctl;
1868                 break;
1869         case MSR_IA32_RTIT_STATUS:
1870                 if (!vmx_pt_mode_is_host_guest())
1871                         return 1;
1872                 msr_info->data = vmx->pt_desc.guest.status;
1873                 break;
1874         case MSR_IA32_RTIT_CR3_MATCH:
1875                 if (!vmx_pt_mode_is_host_guest() ||
1876                         !intel_pt_validate_cap(vmx->pt_desc.caps,
1877                                                 PT_CAP_cr3_filtering))
1878                         return 1;
1879                 msr_info->data = vmx->pt_desc.guest.cr3_match;
1880                 break;
1881         case MSR_IA32_RTIT_OUTPUT_BASE:
1882                 if (!vmx_pt_mode_is_host_guest() ||
1883                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1884                                         PT_CAP_topa_output) &&
1885                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1886                                         PT_CAP_single_range_output)))
1887                         return 1;
1888                 msr_info->data = vmx->pt_desc.guest.output_base;
1889                 break;
1890         case MSR_IA32_RTIT_OUTPUT_MASK:
1891                 if (!vmx_pt_mode_is_host_guest() ||
1892                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1893                                         PT_CAP_topa_output) &&
1894                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1895                                         PT_CAP_single_range_output)))
1896                         return 1;
1897                 msr_info->data = vmx->pt_desc.guest.output_mask;
1898                 break;
1899         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1900                 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1901                 if (!vmx_pt_mode_is_host_guest() ||
1902                         (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
1903                                         PT_CAP_num_address_ranges)))
1904                         return 1;
1905                 if (index % 2)
1906                         msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1907                 else
1908                         msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1909                 break;
1910         case MSR_TSC_AUX:
1911                 if (!msr_info->host_initiated &&
1912                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
1913                         return 1;
1914                 goto find_shared_msr;
1915         default:
1916         find_shared_msr:
1917                 msr = find_msr_entry(vmx, msr_info->index);
1918                 if (msr) {
1919                         msr_info->data = msr->data;
1920                         break;
1921                 }
1922                 return kvm_get_msr_common(vcpu, msr_info);
1923         }
1924
1925         return 0;
1926 }
1927
1928 /*
1929  * Writes msr value into the appropriate "register".
1930  * Returns 0 on success, non-0 otherwise.
1931  * Assumes vcpu_load() was already called.
1932  */
1933 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1934 {
1935         struct vcpu_vmx *vmx = to_vmx(vcpu);
1936         struct shared_msr_entry *msr;
1937         int ret = 0;
1938         u32 msr_index = msr_info->index;
1939         u64 data = msr_info->data;
1940         u32 index;
1941
1942         switch (msr_index) {
1943         case MSR_EFER:
1944                 ret = kvm_set_msr_common(vcpu, msr_info);
1945                 break;
1946 #ifdef CONFIG_X86_64
1947         case MSR_FS_BASE:
1948                 vmx_segment_cache_clear(vmx);
1949                 vmcs_writel(GUEST_FS_BASE, data);
1950                 break;
1951         case MSR_GS_BASE:
1952                 vmx_segment_cache_clear(vmx);
1953                 vmcs_writel(GUEST_GS_BASE, data);
1954                 break;
1955         case MSR_KERNEL_GS_BASE:
1956                 vmx_write_guest_kernel_gs_base(vmx, data);
1957                 break;
1958 #endif
1959         case MSR_IA32_SYSENTER_CS:
1960                 if (is_guest_mode(vcpu))
1961                         get_vmcs12(vcpu)->guest_sysenter_cs = data;
1962                 vmcs_write32(GUEST_SYSENTER_CS, data);
1963                 break;
1964         case MSR_IA32_SYSENTER_EIP:
1965                 if (is_guest_mode(vcpu))
1966                         get_vmcs12(vcpu)->guest_sysenter_eip = data;
1967                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1968                 break;
1969         case MSR_IA32_SYSENTER_ESP:
1970                 if (is_guest_mode(vcpu))
1971                         get_vmcs12(vcpu)->guest_sysenter_esp = data;
1972                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1973                 break;
1974         case MSR_IA32_DEBUGCTLMSR:
1975                 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
1976                                                 VM_EXIT_SAVE_DEBUG_CONTROLS)
1977                         get_vmcs12(vcpu)->guest_ia32_debugctl = data;
1978
1979                 ret = kvm_set_msr_common(vcpu, msr_info);
1980                 break;
1981
1982         case MSR_IA32_BNDCFGS:
1983                 if (!kvm_mpx_supported() ||
1984                     (!msr_info->host_initiated &&
1985                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1986                         return 1;
1987                 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
1988                     (data & MSR_IA32_BNDCFGS_RSVD))
1989                         return 1;
1990                 vmcs_write64(GUEST_BNDCFGS, data);
1991                 break;
1992         case MSR_IA32_UMWAIT_CONTROL:
1993                 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1994                         return 1;
1995
1996                 /* The reserved bit 1 and non-32 bit [63:32] should be zero */
1997                 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
1998                         return 1;
1999
2000                 vmx->msr_ia32_umwait_control = data;
2001                 break;
2002         case MSR_IA32_SPEC_CTRL:
2003                 if (!msr_info->host_initiated &&
2004                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2005                         return 1;
2006
2007                 if (data & ~kvm_spec_ctrl_valid_bits(vcpu))
2008                         return 1;
2009
2010                 vmx->spec_ctrl = data;
2011                 if (!data)
2012                         break;
2013
2014                 /*
2015                  * For non-nested:
2016                  * When it's written (to non-zero) for the first time, pass
2017                  * it through.
2018                  *
2019                  * For nested:
2020                  * The handling of the MSR bitmap for L2 guests is done in
2021                  * nested_vmx_prepare_msr_bitmap. We should not touch the
2022                  * vmcs02.msr_bitmap here since it gets completely overwritten
2023                  * in the merging. We update the vmcs01 here for L1 as well
2024                  * since it will end up touching the MSR anyway now.
2025                  */
2026                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
2027                                               MSR_IA32_SPEC_CTRL,
2028                                               MSR_TYPE_RW);
2029                 break;
2030         case MSR_IA32_TSX_CTRL:
2031                 if (!msr_info->host_initiated &&
2032                     !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
2033                         return 1;
2034                 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR))
2035                         return 1;
2036                 goto find_shared_msr;
2037         case MSR_IA32_PRED_CMD:
2038                 if (!msr_info->host_initiated &&
2039                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2040                         return 1;
2041
2042                 if (data & ~PRED_CMD_IBPB)
2043                         return 1;
2044                 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL))
2045                         return 1;
2046                 if (!data)
2047                         break;
2048
2049                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2050
2051                 /*
2052                  * For non-nested:
2053                  * When it's written (to non-zero) for the first time, pass
2054                  * it through.
2055                  *
2056                  * For nested:
2057                  * The handling of the MSR bitmap for L2 guests is done in
2058                  * nested_vmx_prepare_msr_bitmap. We should not touch the
2059                  * vmcs02.msr_bitmap here since it gets completely overwritten
2060                  * in the merging.
2061                  */
2062                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
2063                                               MSR_TYPE_W);
2064                 break;
2065         case MSR_IA32_CR_PAT:
2066                 if (!kvm_pat_valid(data))
2067                         return 1;
2068
2069                 if (is_guest_mode(vcpu) &&
2070                     get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
2071                         get_vmcs12(vcpu)->guest_ia32_pat = data;
2072
2073                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2074                         vmcs_write64(GUEST_IA32_PAT, data);
2075                         vcpu->arch.pat = data;
2076                         break;
2077                 }
2078                 ret = kvm_set_msr_common(vcpu, msr_info);
2079                 break;
2080         case MSR_IA32_TSC_ADJUST:
2081                 ret = kvm_set_msr_common(vcpu, msr_info);
2082                 break;
2083         case MSR_IA32_MCG_EXT_CTL:
2084                 if ((!msr_info->host_initiated &&
2085                      !(to_vmx(vcpu)->msr_ia32_feature_control &
2086                        FEAT_CTL_LMCE_ENABLED)) ||
2087                     (data & ~MCG_EXT_CTL_LMCE_EN))
2088                         return 1;
2089                 vcpu->arch.mcg_ext_ctl = data;
2090                 break;
2091         case MSR_IA32_FEAT_CTL:
2092                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
2093                     (to_vmx(vcpu)->msr_ia32_feature_control &
2094                      FEAT_CTL_LOCKED && !msr_info->host_initiated))
2095                         return 1;
2096                 vmx->msr_ia32_feature_control = data;
2097                 if (msr_info->host_initiated && data == 0)
2098                         vmx_leave_nested(vcpu);
2099                 break;
2100         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2101                 if (!msr_info->host_initiated)
2102                         return 1; /* they are read-only */
2103                 if (!nested_vmx_allowed(vcpu))
2104                         return 1;
2105                 return vmx_set_vmx_msr(vcpu, msr_index, data);
2106         case MSR_IA32_RTIT_CTL:
2107                 if (!vmx_pt_mode_is_host_guest() ||
2108                         vmx_rtit_ctl_check(vcpu, data) ||
2109                         vmx->nested.vmxon)
2110                         return 1;
2111                 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
2112                 vmx->pt_desc.guest.ctl = data;
2113                 pt_update_intercept_for_msr(vmx);
2114                 break;
2115         case MSR_IA32_RTIT_STATUS:
2116                 if (!pt_can_write_msr(vmx))
2117                         return 1;
2118                 if (data & MSR_IA32_RTIT_STATUS_MASK)
2119                         return 1;
2120                 vmx->pt_desc.guest.status = data;
2121                 break;
2122         case MSR_IA32_RTIT_CR3_MATCH:
2123                 if (!pt_can_write_msr(vmx))
2124                         return 1;
2125                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2126                                            PT_CAP_cr3_filtering))
2127                         return 1;
2128                 vmx->pt_desc.guest.cr3_match = data;
2129                 break;
2130         case MSR_IA32_RTIT_OUTPUT_BASE:
2131                 if (!pt_can_write_msr(vmx))
2132                         return 1;
2133                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2134                                            PT_CAP_topa_output) &&
2135                     !intel_pt_validate_cap(vmx->pt_desc.caps,
2136                                            PT_CAP_single_range_output))
2137                         return 1;
2138                 if (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK)
2139                         return 1;
2140                 vmx->pt_desc.guest.output_base = data;
2141                 break;
2142         case MSR_IA32_RTIT_OUTPUT_MASK:
2143                 if (!pt_can_write_msr(vmx))
2144                         return 1;
2145                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2146                                            PT_CAP_topa_output) &&
2147                     !intel_pt_validate_cap(vmx->pt_desc.caps,
2148                                            PT_CAP_single_range_output))
2149                         return 1;
2150                 vmx->pt_desc.guest.output_mask = data;
2151                 break;
2152         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2153                 if (!pt_can_write_msr(vmx))
2154                         return 1;
2155                 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2156                 if (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
2157                                                        PT_CAP_num_address_ranges))
2158                         return 1;
2159                 if (is_noncanonical_address(data, vcpu))
2160                         return 1;
2161                 if (index % 2)
2162                         vmx->pt_desc.guest.addr_b[index / 2] = data;
2163                 else
2164                         vmx->pt_desc.guest.addr_a[index / 2] = data;
2165                 break;
2166         case MSR_TSC_AUX:
2167                 if (!msr_info->host_initiated &&
2168                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
2169                         return 1;
2170                 /* Check reserved bit, higher 32 bits should be zero */
2171                 if ((data >> 32) != 0)
2172                         return 1;
2173                 goto find_shared_msr;
2174
2175         default:
2176         find_shared_msr:
2177                 msr = find_msr_entry(vmx, msr_index);
2178                 if (msr)
2179                         ret = vmx_set_guest_msr(vmx, msr, data);
2180                 else
2181                         ret = kvm_set_msr_common(vcpu, msr_info);
2182         }
2183
2184         return ret;
2185 }
2186
2187 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2188 {
2189         kvm_register_mark_available(vcpu, reg);
2190
2191         switch (reg) {
2192         case VCPU_REGS_RSP:
2193                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2194                 break;
2195         case VCPU_REGS_RIP:
2196                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2197                 break;
2198         case VCPU_EXREG_PDPTR:
2199                 if (enable_ept)
2200                         ept_save_pdptrs(vcpu);
2201                 break;
2202         case VCPU_EXREG_CR3:
2203                 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
2204                         vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2205                 break;
2206         default:
2207                 WARN_ON_ONCE(1);
2208                 break;
2209         }
2210 }
2211
2212 static __init int cpu_has_kvm_support(void)
2213 {
2214         return cpu_has_vmx();
2215 }
2216
2217 static __init int vmx_disabled_by_bios(void)
2218 {
2219         return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
2220                !boot_cpu_has(X86_FEATURE_VMX);
2221 }
2222
2223 static int kvm_cpu_vmxon(u64 vmxon_pointer)
2224 {
2225         u64 msr;
2226
2227         cr4_set_bits(X86_CR4_VMXE);
2228         intel_pt_handle_vmx(1);
2229
2230         asm_volatile_goto("1: vmxon %[vmxon_pointer]\n\t"
2231                           _ASM_EXTABLE(1b, %l[fault])
2232                           : : [vmxon_pointer] "m"(vmxon_pointer)
2233                           : : fault);
2234         return 0;
2235
2236 fault:
2237         WARN_ONCE(1, "VMXON faulted, MSR_IA32_FEAT_CTL (0x3a) = 0x%llx\n",
2238                   rdmsrl_safe(MSR_IA32_FEAT_CTL, &msr) ? 0xdeadbeef : msr);
2239         intel_pt_handle_vmx(0);
2240         cr4_clear_bits(X86_CR4_VMXE);
2241
2242         return -EFAULT;
2243 }
2244
2245 static int hardware_enable(void)
2246 {
2247         int cpu = raw_smp_processor_id();
2248         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2249         int r;
2250
2251         if (cr4_read_shadow() & X86_CR4_VMXE)
2252                 return -EBUSY;
2253
2254         /*
2255          * This can happen if we hot-added a CPU but failed to allocate
2256          * VP assist page for it.
2257          */
2258         if (static_branch_unlikely(&enable_evmcs) &&
2259             !hv_get_vp_assist_page(cpu))
2260                 return -EFAULT;
2261
2262         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2263         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
2264         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
2265
2266         r = kvm_cpu_vmxon(phys_addr);
2267         if (r)
2268                 return r;
2269
2270         if (enable_ept)
2271                 ept_sync_global();
2272
2273         return 0;
2274 }
2275
2276 static void vmclear_local_loaded_vmcss(void)
2277 {
2278         int cpu = raw_smp_processor_id();
2279         struct loaded_vmcs *v, *n;
2280
2281         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2282                                  loaded_vmcss_on_cpu_link)
2283                 __loaded_vmcs_clear(v);
2284 }
2285
2286
2287 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2288  * tricks.
2289  */
2290 static void kvm_cpu_vmxoff(void)
2291 {
2292         asm volatile (__ex("vmxoff"));
2293
2294         intel_pt_handle_vmx(0);
2295         cr4_clear_bits(X86_CR4_VMXE);
2296 }
2297
2298 static void hardware_disable(void)
2299 {
2300         vmclear_local_loaded_vmcss();
2301         kvm_cpu_vmxoff();
2302 }
2303
2304 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2305                                       u32 msr, u32 *result)
2306 {
2307         u32 vmx_msr_low, vmx_msr_high;
2308         u32 ctl = ctl_min | ctl_opt;
2309
2310         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2311
2312         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2313         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2314
2315         /* Ensure minimum (required) set of control bits are supported. */
2316         if (ctl_min & ~ctl)
2317                 return -EIO;
2318
2319         *result = ctl;
2320         return 0;
2321 }
2322
2323 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2324                                     struct vmx_capability *vmx_cap)
2325 {
2326         u32 vmx_msr_low, vmx_msr_high;
2327         u32 min, opt, min2, opt2;
2328         u32 _pin_based_exec_control = 0;
2329         u32 _cpu_based_exec_control = 0;
2330         u32 _cpu_based_2nd_exec_control = 0;
2331         u32 _vmexit_control = 0;
2332         u32 _vmentry_control = 0;
2333
2334         memset(vmcs_conf, 0, sizeof(*vmcs_conf));
2335         min = CPU_BASED_HLT_EXITING |
2336 #ifdef CONFIG_X86_64
2337               CPU_BASED_CR8_LOAD_EXITING |
2338               CPU_BASED_CR8_STORE_EXITING |
2339 #endif
2340               CPU_BASED_CR3_LOAD_EXITING |
2341               CPU_BASED_CR3_STORE_EXITING |
2342               CPU_BASED_UNCOND_IO_EXITING |
2343               CPU_BASED_MOV_DR_EXITING |
2344               CPU_BASED_USE_TSC_OFFSETTING |
2345               CPU_BASED_MWAIT_EXITING |
2346               CPU_BASED_MONITOR_EXITING |
2347               CPU_BASED_INVLPG_EXITING |
2348               CPU_BASED_RDPMC_EXITING;
2349
2350         opt = CPU_BASED_TPR_SHADOW |
2351               CPU_BASED_USE_MSR_BITMAPS |
2352               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2353         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2354                                 &_cpu_based_exec_control) < 0)
2355                 return -EIO;
2356 #ifdef CONFIG_X86_64
2357         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2358                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2359                                            ~CPU_BASED_CR8_STORE_EXITING;
2360 #endif
2361         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2362                 min2 = 0;
2363                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2364                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2365                         SECONDARY_EXEC_WBINVD_EXITING |
2366                         SECONDARY_EXEC_ENABLE_VPID |
2367                         SECONDARY_EXEC_ENABLE_EPT |
2368                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2369                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2370                         SECONDARY_EXEC_DESC |
2371                         SECONDARY_EXEC_RDTSCP |
2372                         SECONDARY_EXEC_ENABLE_INVPCID |
2373                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2374                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2375                         SECONDARY_EXEC_SHADOW_VMCS |
2376                         SECONDARY_EXEC_XSAVES |
2377                         SECONDARY_EXEC_RDSEED_EXITING |
2378                         SECONDARY_EXEC_RDRAND_EXITING |
2379                         SECONDARY_EXEC_ENABLE_PML |
2380                         SECONDARY_EXEC_TSC_SCALING |
2381                         SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
2382                         SECONDARY_EXEC_PT_USE_GPA |
2383                         SECONDARY_EXEC_PT_CONCEAL_VMX |
2384                         SECONDARY_EXEC_ENABLE_VMFUNC |
2385                         SECONDARY_EXEC_ENCLS_EXITING;
2386                 if (adjust_vmx_controls(min2, opt2,
2387                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2388                                         &_cpu_based_2nd_exec_control) < 0)
2389                         return -EIO;
2390         }
2391 #ifndef CONFIG_X86_64
2392         if (!(_cpu_based_2nd_exec_control &
2393                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2394                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2395 #endif
2396
2397         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2398                 _cpu_based_2nd_exec_control &= ~(
2399                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2400                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2401                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2402
2403         rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
2404                 &vmx_cap->ept, &vmx_cap->vpid);
2405
2406         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2407                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2408                    enabled */
2409                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2410                                              CPU_BASED_CR3_STORE_EXITING |
2411                                              CPU_BASED_INVLPG_EXITING);
2412         } else if (vmx_cap->ept) {
2413                 vmx_cap->ept = 0;
2414                 pr_warn_once("EPT CAP should not exist if not support "
2415                                 "1-setting enable EPT VM-execution control\n");
2416         }
2417         if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
2418                 vmx_cap->vpid) {
2419                 vmx_cap->vpid = 0;
2420                 pr_warn_once("VPID CAP should not exist if not support "
2421                                 "1-setting enable VPID VM-execution control\n");
2422         }
2423
2424         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
2425 #ifdef CONFIG_X86_64
2426         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2427 #endif
2428         opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2429               VM_EXIT_LOAD_IA32_PAT |
2430               VM_EXIT_LOAD_IA32_EFER |
2431               VM_EXIT_CLEAR_BNDCFGS |
2432               VM_EXIT_PT_CONCEAL_PIP |
2433               VM_EXIT_CLEAR_IA32_RTIT_CTL;
2434         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2435                                 &_vmexit_control) < 0)
2436                 return -EIO;
2437
2438         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2439         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2440                  PIN_BASED_VMX_PREEMPTION_TIMER;
2441         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2442                                 &_pin_based_exec_control) < 0)
2443                 return -EIO;
2444
2445         if (cpu_has_broken_vmx_preemption_timer())
2446                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2447         if (!(_cpu_based_2nd_exec_control &
2448                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
2449                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2450
2451         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2452         opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2453               VM_ENTRY_LOAD_IA32_PAT |
2454               VM_ENTRY_LOAD_IA32_EFER |
2455               VM_ENTRY_LOAD_BNDCFGS |
2456               VM_ENTRY_PT_CONCEAL_PIP |
2457               VM_ENTRY_LOAD_IA32_RTIT_CTL;
2458         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2459                                 &_vmentry_control) < 0)
2460                 return -EIO;
2461
2462         /*
2463          * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2464          * can't be used due to an errata where VM Exit may incorrectly clear
2465          * IA32_PERF_GLOBAL_CTRL[34:32].  Workaround the errata by using the
2466          * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2467          */
2468         if (boot_cpu_data.x86 == 0x6) {
2469                 switch (boot_cpu_data.x86_model) {
2470                 case 26: /* AAK155 */
2471                 case 30: /* AAP115 */
2472                 case 37: /* AAT100 */
2473                 case 44: /* BC86,AAY89,BD102 */
2474                 case 46: /* BA97 */
2475                         _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
2476                         _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2477                         pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2478                                         "does not work properly. Using workaround\n");
2479                         break;
2480                 default:
2481                         break;
2482                 }
2483         }
2484
2485
2486         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2487
2488         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2489         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2490                 return -EIO;
2491
2492 #ifdef CONFIG_X86_64
2493         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2494         if (vmx_msr_high & (1u<<16))
2495                 return -EIO;
2496 #endif
2497
2498         /* Require Write-Back (WB) memory type for VMCS accesses. */
2499         if (((vmx_msr_high >> 18) & 15) != 6)
2500                 return -EIO;
2501
2502         vmcs_conf->size = vmx_msr_high & 0x1fff;
2503         vmcs_conf->order = get_order(vmcs_conf->size);
2504         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
2505
2506         vmcs_conf->revision_id = vmx_msr_low;
2507
2508         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2509         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2510         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2511         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2512         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2513
2514         if (static_branch_unlikely(&enable_evmcs))
2515                 evmcs_sanitize_exec_ctrls(vmcs_conf);
2516
2517         return 0;
2518 }
2519
2520 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
2521 {
2522         int node = cpu_to_node(cpu);
2523         struct page *pages;
2524         struct vmcs *vmcs;
2525
2526         pages = __alloc_pages_node(node, flags, vmcs_config.order);
2527         if (!pages)
2528                 return NULL;
2529         vmcs = page_address(pages);
2530         memset(vmcs, 0, vmcs_config.size);
2531
2532         /* KVM supports Enlightened VMCS v1 only */
2533         if (static_branch_unlikely(&enable_evmcs))
2534                 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2535         else
2536                 vmcs->hdr.revision_id = vmcs_config.revision_id;
2537
2538         if (shadow)
2539                 vmcs->hdr.shadow_vmcs = 1;
2540         return vmcs;
2541 }
2542
2543 void free_vmcs(struct vmcs *vmcs)
2544 {
2545         free_pages((unsigned long)vmcs, vmcs_config.order);
2546 }
2547
2548 /*
2549  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2550  */
2551 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2552 {
2553         if (!loaded_vmcs->vmcs)
2554                 return;
2555         loaded_vmcs_clear(loaded_vmcs);
2556         free_vmcs(loaded_vmcs->vmcs);
2557         loaded_vmcs->vmcs = NULL;
2558         if (loaded_vmcs->msr_bitmap)
2559                 free_page((unsigned long)loaded_vmcs->msr_bitmap);
2560         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
2561 }
2562
2563 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2564 {
2565         loaded_vmcs->vmcs = alloc_vmcs(false);
2566         if (!loaded_vmcs->vmcs)
2567                 return -ENOMEM;
2568
2569         vmcs_clear(loaded_vmcs->vmcs);
2570
2571         loaded_vmcs->shadow_vmcs = NULL;
2572         loaded_vmcs->hv_timer_soft_disabled = false;
2573         loaded_vmcs->cpu = -1;
2574         loaded_vmcs->launched = 0;
2575
2576         if (cpu_has_vmx_msr_bitmap()) {
2577                 loaded_vmcs->msr_bitmap = (unsigned long *)
2578                                 __get_free_page(GFP_KERNEL_ACCOUNT);
2579                 if (!loaded_vmcs->msr_bitmap)
2580                         goto out_vmcs;
2581                 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
2582
2583                 if (IS_ENABLED(CONFIG_HYPERV) &&
2584                     static_branch_unlikely(&enable_evmcs) &&
2585                     (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2586                         struct hv_enlightened_vmcs *evmcs =
2587                                 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2588
2589                         evmcs->hv_enlightenments_control.msr_bitmap = 1;
2590                 }
2591         }
2592
2593         memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2594         memset(&loaded_vmcs->controls_shadow, 0,
2595                 sizeof(struct vmcs_controls_shadow));
2596
2597         return 0;
2598
2599 out_vmcs:
2600         free_loaded_vmcs(loaded_vmcs);
2601         return -ENOMEM;
2602 }
2603
2604 static void free_kvm_area(void)
2605 {
2606         int cpu;
2607
2608         for_each_possible_cpu(cpu) {
2609                 free_vmcs(per_cpu(vmxarea, cpu));
2610                 per_cpu(vmxarea, cpu) = NULL;
2611         }
2612 }
2613
2614 static __init int alloc_kvm_area(void)
2615 {
2616         int cpu;
2617
2618         for_each_possible_cpu(cpu) {
2619                 struct vmcs *vmcs;
2620
2621                 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
2622                 if (!vmcs) {
2623                         free_kvm_area();
2624                         return -ENOMEM;
2625                 }
2626
2627                 /*
2628                  * When eVMCS is enabled, alloc_vmcs_cpu() sets
2629                  * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2630                  * revision_id reported by MSR_IA32_VMX_BASIC.
2631                  *
2632                  * However, even though not explicitly documented by
2633                  * TLFS, VMXArea passed as VMXON argument should
2634                  * still be marked with revision_id reported by
2635                  * physical CPU.
2636                  */
2637                 if (static_branch_unlikely(&enable_evmcs))
2638                         vmcs->hdr.revision_id = vmcs_config.revision_id;
2639
2640                 per_cpu(vmxarea, cpu) = vmcs;
2641         }
2642         return 0;
2643 }
2644
2645 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2646                 struct kvm_segment *save)
2647 {
2648         if (!emulate_invalid_guest_state) {
2649                 /*
2650                  * CS and SS RPL should be equal during guest entry according
2651                  * to VMX spec, but in reality it is not always so. Since vcpu
2652                  * is in the middle of the transition from real mode to
2653                  * protected mode it is safe to assume that RPL 0 is a good
2654                  * default value.
2655                  */
2656                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2657                         save->selector &= ~SEGMENT_RPL_MASK;
2658                 save->dpl = save->selector & SEGMENT_RPL_MASK;
2659                 save->s = 1;
2660         }
2661         vmx_set_segment(vcpu, save, seg);
2662 }
2663
2664 static void enter_pmode(struct kvm_vcpu *vcpu)
2665 {
2666         unsigned long flags;
2667         struct vcpu_vmx *vmx = to_vmx(vcpu);
2668
2669         /*
2670          * Update real mode segment cache. It may be not up-to-date if sement
2671          * register was written while vcpu was in a guest mode.
2672          */
2673         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2674         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2675         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2676         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2677         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2678         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2679
2680         vmx->rmode.vm86_active = 0;
2681
2682         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2683
2684         flags = vmcs_readl(GUEST_RFLAGS);
2685         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2686         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2687         vmcs_writel(GUEST_RFLAGS, flags);
2688
2689         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2690                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2691
2692         update_exception_bitmap(vcpu);
2693
2694         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2695         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2696         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2697         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2698         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2699         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2700 }
2701
2702 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2703 {
2704         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2705         struct kvm_segment var = *save;
2706
2707         var.dpl = 0x3;
2708         if (seg == VCPU_SREG_CS)
2709                 var.type = 0x3;
2710
2711         if (!emulate_invalid_guest_state) {
2712                 var.selector = var.base >> 4;
2713                 var.base = var.base & 0xffff0;
2714                 var.limit = 0xffff;
2715                 var.g = 0;
2716                 var.db = 0;
2717                 var.present = 1;
2718                 var.s = 1;
2719                 var.l = 0;
2720                 var.unusable = 0;
2721                 var.type = 0x3;
2722                 var.avl = 0;
2723                 if (save->base & 0xf)
2724                         printk_once(KERN_WARNING "kvm: segment base is not "
2725                                         "paragraph aligned when entering "
2726                                         "protected mode (seg=%d)", seg);
2727         }
2728
2729         vmcs_write16(sf->selector, var.selector);
2730         vmcs_writel(sf->base, var.base);
2731         vmcs_write32(sf->limit, var.limit);
2732         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2733 }
2734
2735 static void enter_rmode(struct kvm_vcpu *vcpu)
2736 {
2737         unsigned long flags;
2738         struct vcpu_vmx *vmx = to_vmx(vcpu);
2739         struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
2740
2741         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2742         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2743         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2744         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2745         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2746         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2747         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2748
2749         vmx->rmode.vm86_active = 1;
2750
2751         /*
2752          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2753          * vcpu. Warn the user that an update is overdue.
2754          */
2755         if (!kvm_vmx->tss_addr)
2756                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2757                              "called before entering vcpu\n");
2758
2759         vmx_segment_cache_clear(vmx);
2760
2761         vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
2762         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2763         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2764
2765         flags = vmcs_readl(GUEST_RFLAGS);
2766         vmx->rmode.save_rflags = flags;
2767
2768         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2769
2770         vmcs_writel(GUEST_RFLAGS, flags);
2771         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2772         update_exception_bitmap(vcpu);
2773
2774         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2775         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2776         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2777         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2778         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2779         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2780
2781         kvm_mmu_reset_context(vcpu);
2782 }
2783
2784 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2785 {
2786         struct vcpu_vmx *vmx = to_vmx(vcpu);
2787         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2788
2789         if (!msr)
2790                 return;
2791
2792         vcpu->arch.efer = efer;
2793         if (efer & EFER_LMA) {
2794                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2795                 msr->data = efer;
2796         } else {
2797                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2798
2799                 msr->data = efer & ~EFER_LME;
2800         }
2801         setup_msrs(vmx);
2802 }
2803
2804 #ifdef CONFIG_X86_64
2805
2806 static void enter_lmode(struct kvm_vcpu *vcpu)
2807 {
2808         u32 guest_tr_ar;
2809
2810         vmx_segment_cache_clear(to_vmx(vcpu));
2811
2812         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2813         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
2814                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2815                                      __func__);
2816                 vmcs_write32(GUEST_TR_AR_BYTES,
2817                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2818                              | VMX_AR_TYPE_BUSY_64_TSS);
2819         }
2820         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2821 }
2822
2823 static void exit_lmode(struct kvm_vcpu *vcpu)
2824 {
2825         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2826         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2827 }
2828
2829 #endif
2830
2831 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2832 {
2833         int vpid = to_vmx(vcpu)->vpid;
2834
2835         if (!vpid_sync_vcpu_addr(vpid, addr))
2836                 vpid_sync_context(vpid);
2837
2838         /*
2839          * If VPIDs are not supported or enabled, then the above is a no-op.
2840          * But we don't really need a TLB flush in that case anyway, because
2841          * each VM entry/exit includes an implicit flush when VPID is 0.
2842          */
2843 }
2844
2845 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2846 {
2847         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2848
2849         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2850         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2851 }
2852
2853 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2854 {
2855         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2856
2857         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2858         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2859 }
2860
2861 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2862 {
2863         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2864
2865         if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR))
2866                 return;
2867
2868         if (is_pae_paging(vcpu)) {
2869                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2870                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2871                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2872                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
2873         }
2874 }
2875
2876 void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2877 {
2878         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2879
2880         if (is_pae_paging(vcpu)) {
2881                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2882                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2883                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2884                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2885         }
2886
2887         kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
2888 }
2889
2890 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2891                                         unsigned long cr0,
2892                                         struct kvm_vcpu *vcpu)
2893 {
2894         struct vcpu_vmx *vmx = to_vmx(vcpu);
2895
2896         if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3))
2897                 vmx_cache_reg(vcpu, VCPU_EXREG_CR3);
2898         if (!(cr0 & X86_CR0_PG)) {
2899                 /* From paging/starting to nonpaging */
2900                 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2901                                           CPU_BASED_CR3_STORE_EXITING);
2902                 vcpu->arch.cr0 = cr0;
2903                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2904         } else if (!is_paging(vcpu)) {
2905                 /* From nonpaging to paging */
2906                 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2907                                             CPU_BASED_CR3_STORE_EXITING);
2908                 vcpu->arch.cr0 = cr0;
2909                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2910         }
2911
2912         if (!(cr0 & X86_CR0_WP))
2913                 *hw_cr0 &= ~X86_CR0_WP;
2914 }
2915
2916 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2917 {
2918         struct vcpu_vmx *vmx = to_vmx(vcpu);
2919         unsigned long hw_cr0;
2920
2921         hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
2922         if (enable_unrestricted_guest)
2923                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2924         else {
2925                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
2926
2927                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2928                         enter_pmode(vcpu);
2929
2930                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2931                         enter_rmode(vcpu);
2932         }
2933
2934 #ifdef CONFIG_X86_64
2935         if (vcpu->arch.efer & EFER_LME) {
2936                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2937                         enter_lmode(vcpu);
2938                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2939                         exit_lmode(vcpu);
2940         }
2941 #endif
2942
2943         if (enable_ept && !enable_unrestricted_guest)
2944                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2945
2946         vmcs_writel(CR0_READ_SHADOW, cr0);
2947         vmcs_writel(GUEST_CR0, hw_cr0);
2948         vcpu->arch.cr0 = cr0;
2949
2950         /* depends on vcpu->arch.cr0 to be set to a new value */
2951         vmx->emulation_required = emulation_required(vcpu);
2952 }
2953
2954 static int get_ept_level(struct kvm_vcpu *vcpu)
2955 {
2956         if (is_guest_mode(vcpu) && nested_cpu_has_ept(get_vmcs12(vcpu)))
2957                 return vmx_eptp_page_walk_level(nested_ept_get_eptp(vcpu));
2958         if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
2959                 return 5;
2960         return 4;
2961 }
2962
2963 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
2964 {
2965         u64 eptp = VMX_EPTP_MT_WB;
2966
2967         eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
2968
2969         if (enable_ept_ad_bits &&
2970             (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
2971                 eptp |= VMX_EPTP_AD_ENABLE_BIT;
2972         eptp |= (root_hpa & PAGE_MASK);
2973
2974         return eptp;
2975 }
2976
2977 void vmx_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long cr3)
2978 {
2979         struct kvm *kvm = vcpu->kvm;
2980         bool update_guest_cr3 = true;
2981         unsigned long guest_cr3;
2982         u64 eptp;
2983
2984         guest_cr3 = cr3;
2985         if (enable_ept) {
2986                 eptp = construct_eptp(vcpu, cr3);
2987                 vmcs_write64(EPT_POINTER, eptp);
2988
2989                 if (kvm_x86_ops->tlb_remote_flush) {
2990                         spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
2991                         to_vmx(vcpu)->ept_pointer = eptp;
2992                         to_kvm_vmx(kvm)->ept_pointers_match
2993                                 = EPT_POINTERS_CHECK;
2994                         spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
2995                 }
2996
2997                 /* Loading vmcs02.GUEST_CR3 is handled by nested VM-Enter. */
2998                 if (is_guest_mode(vcpu))
2999                         update_guest_cr3 = false;
3000                 else if (!enable_unrestricted_guest && !is_paging(vcpu))
3001                         guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
3002                 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3003                         guest_cr3 = vcpu->arch.cr3;
3004                 else /* vmcs01.GUEST_CR3 is already up-to-date. */
3005                         update_guest_cr3 = false;
3006                 ept_load_pdptrs(vcpu);
3007         }
3008
3009         if (update_guest_cr3)
3010                 vmcs_writel(GUEST_CR3, guest_cr3);
3011 }
3012
3013 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3014 {
3015         struct vcpu_vmx *vmx = to_vmx(vcpu);
3016         /*
3017          * Pass through host's Machine Check Enable value to hw_cr4, which
3018          * is in force while we are in guest mode.  Do not let guests control
3019          * this bit, even if host CR4.MCE == 0.
3020          */
3021         unsigned long hw_cr4;
3022
3023         hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
3024         if (enable_unrestricted_guest)
3025                 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
3026         else if (vmx->rmode.vm86_active)
3027                 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
3028         else
3029                 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
3030
3031         if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
3032                 if (cr4 & X86_CR4_UMIP) {
3033                         secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
3034                         hw_cr4 &= ~X86_CR4_UMIP;
3035                 } else if (!is_guest_mode(vcpu) ||
3036                         !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
3037                         secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
3038                 }
3039         }
3040
3041         if (cr4 & X86_CR4_VMXE) {
3042                 /*
3043                  * To use VMXON (and later other VMX instructions), a guest
3044                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3045                  * So basically the check on whether to allow nested VMX
3046                  * is here.  We operate under the default treatment of SMM,
3047                  * so VMX cannot be enabled under SMM.
3048                  */
3049                 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
3050                         return 1;
3051         }
3052
3053         if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
3054                 return 1;
3055
3056         vcpu->arch.cr4 = cr4;
3057
3058         if (!enable_unrestricted_guest) {
3059                 if (enable_ept) {
3060                         if (!is_paging(vcpu)) {
3061                                 hw_cr4 &= ~X86_CR4_PAE;
3062                                 hw_cr4 |= X86_CR4_PSE;
3063                         } else if (!(cr4 & X86_CR4_PAE)) {
3064                                 hw_cr4 &= ~X86_CR4_PAE;
3065                         }
3066                 }
3067
3068                 /*
3069                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3070                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
3071                  * to be manually disabled when guest switches to non-paging
3072                  * mode.
3073                  *
3074                  * If !enable_unrestricted_guest, the CPU is always running
3075                  * with CR0.PG=1 and CR4 needs to be modified.
3076                  * If enable_unrestricted_guest, the CPU automatically
3077                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3078                  */
3079                 if (!is_paging(vcpu))
3080                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3081         }
3082
3083         vmcs_writel(CR4_READ_SHADOW, cr4);
3084         vmcs_writel(GUEST_CR4, hw_cr4);
3085         return 0;
3086 }
3087
3088 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3089 {
3090         struct vcpu_vmx *vmx = to_vmx(vcpu);
3091         u32 ar;
3092
3093         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3094                 *var = vmx->rmode.segs[seg];
3095                 if (seg == VCPU_SREG_TR
3096                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3097                         return;
3098                 var->base = vmx_read_guest_seg_base(vmx, seg);
3099                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3100                 return;
3101         }
3102         var->base = vmx_read_guest_seg_base(vmx, seg);
3103         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3104         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3105         ar = vmx_read_guest_seg_ar(vmx, seg);
3106         var->unusable = (ar >> 16) & 1;
3107         var->type = ar & 15;
3108         var->s = (ar >> 4) & 1;
3109         var->dpl = (ar >> 5) & 3;
3110         /*
3111          * Some userspaces do not preserve unusable property. Since usable
3112          * segment has to be present according to VMX spec we can use present
3113          * property to amend userspace bug by making unusable segment always
3114          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3115          * segment as unusable.
3116          */
3117         var->present = !var->unusable;
3118         var->avl = (ar >> 12) & 1;
3119         var->l = (ar >> 13) & 1;
3120         var->db = (ar >> 14) & 1;
3121         var->g = (ar >> 15) & 1;
3122 }
3123
3124 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3125 {
3126         struct kvm_segment s;
3127
3128         if (to_vmx(vcpu)->rmode.vm86_active) {
3129                 vmx_get_segment(vcpu, &s, seg);
3130                 return s.base;
3131         }
3132         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3133 }
3134
3135 int vmx_get_cpl(struct kvm_vcpu *vcpu)
3136 {
3137         struct vcpu_vmx *vmx = to_vmx(vcpu);
3138
3139         if (unlikely(vmx->rmode.vm86_active))
3140                 return 0;
3141         else {
3142                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3143                 return VMX_AR_DPL(ar);
3144         }
3145 }
3146
3147 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3148 {
3149         u32 ar;
3150
3151         if (var->unusable || !var->present)
3152                 ar = 1 << 16;
3153         else {
3154                 ar = var->type & 15;
3155                 ar |= (var->s & 1) << 4;
3156                 ar |= (var->dpl & 3) << 5;
3157                 ar |= (var->present & 1) << 7;
3158                 ar |= (var->avl & 1) << 12;
3159                 ar |= (var->l & 1) << 13;
3160                 ar |= (var->db & 1) << 14;
3161                 ar |= (var->g & 1) << 15;
3162         }
3163
3164         return ar;
3165 }
3166
3167 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3168 {
3169         struct vcpu_vmx *vmx = to_vmx(vcpu);
3170         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3171
3172         vmx_segment_cache_clear(vmx);
3173
3174         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3175                 vmx->rmode.segs[seg] = *var;
3176                 if (seg == VCPU_SREG_TR)
3177                         vmcs_write16(sf->selector, var->selector);
3178                 else if (var->s)
3179                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3180                 goto out;
3181         }
3182
3183         vmcs_writel(sf->base, var->base);
3184         vmcs_write32(sf->limit, var->limit);
3185         vmcs_write16(sf->selector, var->selector);
3186
3187         /*
3188          *   Fix the "Accessed" bit in AR field of segment registers for older
3189          * qemu binaries.
3190          *   IA32 arch specifies that at the time of processor reset the
3191          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3192          * is setting it to 0 in the userland code. This causes invalid guest
3193          * state vmexit when "unrestricted guest" mode is turned on.
3194          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3195          * tree. Newer qemu binaries with that qemu fix would not need this
3196          * kvm hack.
3197          */
3198         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3199                 var->type |= 0x1; /* Accessed */
3200
3201         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3202
3203 out:
3204         vmx->emulation_required = emulation_required(vcpu);
3205 }
3206
3207 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3208 {
3209         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3210
3211         *db = (ar >> 14) & 1;
3212         *l = (ar >> 13) & 1;
3213 }
3214
3215 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3216 {
3217         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3218         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3219 }
3220
3221 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3222 {
3223         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3224         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3225 }
3226
3227 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3228 {
3229         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3230         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3231 }
3232
3233 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3234 {
3235         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3236         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3237 }
3238
3239 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3240 {
3241         struct kvm_segment var;
3242         u32 ar;
3243
3244         vmx_get_segment(vcpu, &var, seg);
3245         var.dpl = 0x3;
3246         if (seg == VCPU_SREG_CS)
3247                 var.type = 0x3;
3248         ar = vmx_segment_access_rights(&var);
3249
3250         if (var.base != (var.selector << 4))
3251                 return false;
3252         if (var.limit != 0xffff)
3253                 return false;
3254         if (ar != 0xf3)
3255                 return false;
3256
3257         return true;
3258 }
3259
3260 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3261 {
3262         struct kvm_segment cs;
3263         unsigned int cs_rpl;
3264
3265         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3266         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3267
3268         if (cs.unusable)
3269                 return false;
3270         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3271                 return false;
3272         if (!cs.s)
3273                 return false;
3274         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3275                 if (cs.dpl > cs_rpl)
3276                         return false;
3277         } else {
3278                 if (cs.dpl != cs_rpl)
3279                         return false;
3280         }
3281         if (!cs.present)
3282                 return false;
3283
3284         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3285         return true;
3286 }
3287
3288 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3289 {
3290         struct kvm_segment ss;
3291         unsigned int ss_rpl;
3292
3293         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3294         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3295
3296         if (ss.unusable)
3297                 return true;
3298         if (ss.type != 3 && ss.type != 7)
3299                 return false;
3300         if (!ss.s)
3301                 return false;
3302         if (ss.dpl != ss_rpl) /* DPL != RPL */
3303                 return false;
3304         if (!ss.present)
3305                 return false;
3306
3307         return true;
3308 }
3309
3310 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3311 {
3312         struct kvm_segment var;
3313         unsigned int rpl;
3314
3315         vmx_get_segment(vcpu, &var, seg);
3316         rpl = var.selector & SEGMENT_RPL_MASK;
3317
3318         if (var.unusable)
3319                 return true;
3320         if (!var.s)
3321                 return false;
3322         if (!var.present)
3323                 return false;
3324         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
3325                 if (var.dpl < rpl) /* DPL < RPL */
3326                         return false;
3327         }
3328
3329         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3330          * rights flags
3331          */
3332         return true;
3333 }
3334
3335 static bool tr_valid(struct kvm_vcpu *vcpu)
3336 {
3337         struct kvm_segment tr;
3338
3339         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3340
3341         if (tr.unusable)
3342                 return false;
3343         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
3344                 return false;
3345         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3346                 return false;
3347         if (!tr.present)
3348                 return false;
3349
3350         return true;
3351 }
3352
3353 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3354 {
3355         struct kvm_segment ldtr;
3356
3357         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3358
3359         if (ldtr.unusable)
3360                 return true;
3361         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
3362                 return false;
3363         if (ldtr.type != 2)
3364                 return false;
3365         if (!ldtr.present)
3366                 return false;
3367
3368         return true;
3369 }
3370
3371 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3372 {
3373         struct kvm_segment cs, ss;
3374
3375         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3376         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3377
3378         return ((cs.selector & SEGMENT_RPL_MASK) ==
3379                  (ss.selector & SEGMENT_RPL_MASK));
3380 }
3381
3382 /*
3383  * Check if guest state is valid. Returns true if valid, false if
3384  * not.
3385  * We assume that registers are always usable
3386  */
3387 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3388 {
3389         if (enable_unrestricted_guest)
3390                 return true;
3391
3392         /* real mode guest state checks */
3393         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3394                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3395                         return false;
3396                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3397                         return false;
3398                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3399                         return false;
3400                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3401                         return false;
3402                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3403                         return false;
3404                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3405                         return false;
3406         } else {
3407         /* protected mode guest state checks */
3408                 if (!cs_ss_rpl_check(vcpu))
3409                         return false;
3410                 if (!code_segment_valid(vcpu))
3411                         return false;
3412                 if (!stack_segment_valid(vcpu))
3413                         return false;
3414                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3415                         return false;
3416                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3417                         return false;
3418                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3419                         return false;
3420                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3421                         return false;
3422                 if (!tr_valid(vcpu))
3423                         return false;
3424                 if (!ldtr_valid(vcpu))
3425                         return false;
3426         }
3427         /* TODO:
3428          * - Add checks on RIP
3429          * - Add checks on RFLAGS
3430          */
3431
3432         return true;
3433 }
3434
3435 static int init_rmode_tss(struct kvm *kvm)
3436 {
3437         gfn_t fn;
3438         u16 data = 0;
3439         int idx, r;
3440
3441         idx = srcu_read_lock(&kvm->srcu);
3442         fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
3443         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3444         if (r < 0)
3445                 goto out;
3446         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3447         r = kvm_write_guest_page(kvm, fn++, &data,
3448                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3449         if (r < 0)
3450                 goto out;
3451         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3452         if (r < 0)
3453                 goto out;
3454         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3455         if (r < 0)
3456                 goto out;
3457         data = ~0;
3458         r = kvm_write_guest_page(kvm, fn, &data,
3459                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3460                                  sizeof(u8));
3461 out:
3462         srcu_read_unlock(&kvm->srcu, idx);
3463         return r;
3464 }
3465
3466 static int init_rmode_identity_map(struct kvm *kvm)
3467 {
3468         struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
3469         int i, r = 0;
3470         kvm_pfn_t identity_map_pfn;
3471         u32 tmp;
3472
3473         /* Protect kvm_vmx->ept_identity_pagetable_done. */
3474         mutex_lock(&kvm->slots_lock);
3475
3476         if (likely(kvm_vmx->ept_identity_pagetable_done))
3477                 goto out;
3478
3479         if (!kvm_vmx->ept_identity_map_addr)
3480                 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3481         identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
3482
3483         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
3484                                     kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
3485         if (r < 0)
3486                 goto out;
3487
3488         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3489         if (r < 0)
3490                 goto out;
3491         /* Set up identity-mapping pagetable for EPT in real mode */
3492         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3493                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3494                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3495                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3496                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3497                 if (r < 0)
3498                         goto out;
3499         }
3500         kvm_vmx->ept_identity_pagetable_done = true;
3501
3502 out:
3503         mutex_unlock(&kvm->slots_lock);
3504         return r;
3505 }
3506
3507 static void seg_setup(int seg)
3508 {
3509         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3510         unsigned int ar;
3511
3512         vmcs_write16(sf->selector, 0);
3513         vmcs_writel(sf->base, 0);
3514         vmcs_write32(sf->limit, 0xffff);
3515         ar = 0x93;
3516         if (seg == VCPU_SREG_CS)
3517                 ar |= 0x08; /* code segment */
3518
3519         vmcs_write32(sf->ar_bytes, ar);
3520 }
3521
3522 static int alloc_apic_access_page(struct kvm *kvm)
3523 {
3524         struct page *page;
3525         int r = 0;
3526
3527         mutex_lock(&kvm->slots_lock);
3528         if (kvm->arch.apic_access_page_done)
3529                 goto out;
3530         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3531                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
3532         if (r)
3533                 goto out;
3534
3535         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
3536         if (is_error_page(page)) {
3537                 r = -EFAULT;
3538                 goto out;
3539         }
3540
3541         /*
3542          * Do not pin the page in memory, so that memory hot-unplug
3543          * is able to migrate it.
3544          */
3545         put_page(page);
3546         kvm->arch.apic_access_page_done = true;
3547 out:
3548         mutex_unlock(&kvm->slots_lock);
3549         return r;
3550 }
3551
3552 int allocate_vpid(void)
3553 {
3554         int vpid;
3555
3556         if (!enable_vpid)
3557                 return 0;
3558         spin_lock(&vmx_vpid_lock);
3559         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3560         if (vpid < VMX_NR_VPIDS)
3561                 __set_bit(vpid, vmx_vpid_bitmap);
3562         else
3563                 vpid = 0;
3564         spin_unlock(&vmx_vpid_lock);
3565         return vpid;
3566 }
3567
3568 void free_vpid(int vpid)
3569 {
3570         if (!enable_vpid || vpid == 0)
3571                 return;
3572         spin_lock(&vmx_vpid_lock);
3573         __clear_bit(vpid, vmx_vpid_bitmap);
3574         spin_unlock(&vmx_vpid_lock);
3575 }
3576
3577 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3578                                                           u32 msr, int type)
3579 {
3580         int f = sizeof(unsigned long);
3581
3582         if (!cpu_has_vmx_msr_bitmap())
3583                 return;
3584
3585         if (static_branch_unlikely(&enable_evmcs))
3586                 evmcs_touch_msr_bitmap();
3587
3588         /*
3589          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3590          * have the write-low and read-high bitmap offsets the wrong way round.
3591          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3592          */
3593         if (msr <= 0x1fff) {
3594                 if (type & MSR_TYPE_R)
3595                         /* read-low */
3596                         __clear_bit(msr, msr_bitmap + 0x000 / f);
3597
3598                 if (type & MSR_TYPE_W)
3599                         /* write-low */
3600                         __clear_bit(msr, msr_bitmap + 0x800 / f);
3601
3602         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3603                 msr &= 0x1fff;
3604                 if (type & MSR_TYPE_R)
3605                         /* read-high */
3606                         __clear_bit(msr, msr_bitmap + 0x400 / f);
3607
3608                 if (type & MSR_TYPE_W)
3609                         /* write-high */
3610                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
3611
3612         }
3613 }
3614
3615 static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3616                                                          u32 msr, int type)
3617 {
3618         int f = sizeof(unsigned long);
3619
3620         if (!cpu_has_vmx_msr_bitmap())
3621                 return;
3622
3623         if (static_branch_unlikely(&enable_evmcs))
3624                 evmcs_touch_msr_bitmap();
3625
3626         /*
3627          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3628          * have the write-low and read-high bitmap offsets the wrong way round.
3629          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3630          */
3631         if (msr <= 0x1fff) {
3632                 if (type & MSR_TYPE_R)
3633                         /* read-low */
3634                         __set_bit(msr, msr_bitmap + 0x000 / f);
3635
3636                 if (type & MSR_TYPE_W)
3637                         /* write-low */
3638                         __set_bit(msr, msr_bitmap + 0x800 / f);
3639
3640         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3641                 msr &= 0x1fff;
3642                 if (type & MSR_TYPE_R)
3643                         /* read-high */
3644                         __set_bit(msr, msr_bitmap + 0x400 / f);
3645
3646                 if (type & MSR_TYPE_W)
3647                         /* write-high */
3648                         __set_bit(msr, msr_bitmap + 0xc00 / f);
3649
3650         }
3651 }
3652
3653 static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
3654                                                       u32 msr, int type, bool value)
3655 {
3656         if (value)
3657                 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
3658         else
3659                 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
3660 }
3661
3662 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
3663 {
3664         u8 mode = 0;
3665
3666         if (cpu_has_secondary_exec_ctrls() &&
3667             (secondary_exec_controls_get(to_vmx(vcpu)) &
3668              SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3669                 mode |= MSR_BITMAP_MODE_X2APIC;
3670                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3671                         mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3672         }
3673
3674         return mode;
3675 }
3676
3677 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
3678                                          u8 mode)
3679 {
3680         int msr;
3681
3682         for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3683                 unsigned word = msr / BITS_PER_LONG;
3684                 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3685                 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
3686         }
3687
3688         if (mode & MSR_BITMAP_MODE_X2APIC) {
3689                 /*
3690                  * TPR reads and writes can be virtualized even if virtual interrupt
3691                  * delivery is not in use.
3692                  */
3693                 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
3694                 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3695                         vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
3696                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3697                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3698                 }
3699         }
3700 }
3701
3702 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
3703 {
3704         struct vcpu_vmx *vmx = to_vmx(vcpu);
3705         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3706         u8 mode = vmx_msr_bitmap_mode(vcpu);
3707         u8 changed = mode ^ vmx->msr_bitmap_mode;
3708
3709         if (!changed)
3710                 return;
3711
3712         if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
3713                 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
3714
3715         vmx->msr_bitmap_mode = mode;
3716 }
3717
3718 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx)
3719 {
3720         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3721         bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3722         u32 i;
3723
3724         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS,
3725                                                         MSR_TYPE_RW, flag);
3726         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE,
3727                                                         MSR_TYPE_RW, flag);
3728         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK,
3729                                                         MSR_TYPE_RW, flag);
3730         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH,
3731                                                         MSR_TYPE_RW, flag);
3732         for (i = 0; i < vmx->pt_desc.addr_range; i++) {
3733                 vmx_set_intercept_for_msr(msr_bitmap,
3734                         MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3735                 vmx_set_intercept_for_msr(msr_bitmap,
3736                         MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3737         }
3738 }
3739
3740 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3741 {
3742         struct vcpu_vmx *vmx = to_vmx(vcpu);
3743         void *vapic_page;
3744         u32 vppr;
3745         int rvi;
3746
3747         if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3748                 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
3749                 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
3750                 return false;
3751
3752         rvi = vmx_get_rvi();
3753
3754         vapic_page = vmx->nested.virtual_apic_map.hva;
3755         vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
3756
3757         return ((rvi & 0xf0) > (vppr & 0xf0));
3758 }
3759
3760 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3761                                                      bool nested)
3762 {
3763 #ifdef CONFIG_SMP
3764         int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3765
3766         if (vcpu->mode == IN_GUEST_MODE) {
3767                 /*
3768                  * The vector of interrupt to be delivered to vcpu had
3769                  * been set in PIR before this function.
3770                  *
3771                  * Following cases will be reached in this block, and
3772                  * we always send a notification event in all cases as
3773                  * explained below.
3774                  *
3775                  * Case 1: vcpu keeps in non-root mode. Sending a
3776                  * notification event posts the interrupt to vcpu.
3777                  *
3778                  * Case 2: vcpu exits to root mode and is still
3779                  * runnable. PIR will be synced to vIRR before the
3780                  * next vcpu entry. Sending a notification event in
3781                  * this case has no effect, as vcpu is not in root
3782                  * mode.
3783                  *
3784                  * Case 3: vcpu exits to root mode and is blocked.
3785                  * vcpu_block() has already synced PIR to vIRR and
3786                  * never blocks vcpu if vIRR is not cleared. Therefore,
3787                  * a blocked vcpu here does not wait for any requested
3788                  * interrupts in PIR, and sending a notification event
3789                  * which has no effect is safe here.
3790                  */
3791
3792                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
3793                 return true;
3794         }
3795 #endif
3796         return false;
3797 }
3798
3799 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3800                                                 int vector)
3801 {
3802         struct vcpu_vmx *vmx = to_vmx(vcpu);
3803
3804         if (is_guest_mode(vcpu) &&
3805             vector == vmx->nested.posted_intr_nv) {
3806                 /*
3807                  * If a posted intr is not recognized by hardware,
3808                  * we will accomplish it in the next vmentry.
3809                  */
3810                 vmx->nested.pi_pending = true;
3811                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3812                 /* the PIR and ON have been set by L1. */
3813                 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3814                         kvm_vcpu_kick(vcpu);
3815                 return 0;
3816         }
3817         return -1;
3818 }
3819 /*
3820  * Send interrupt to vcpu via posted interrupt way.
3821  * 1. If target vcpu is running(non-root mode), send posted interrupt
3822  * notification to vcpu and hardware will sync PIR to vIRR atomically.
3823  * 2. If target vcpu isn't running(root mode), kick it to pick up the
3824  * interrupt from PIR in next vmentry.
3825  */
3826 static int vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3827 {
3828         struct vcpu_vmx *vmx = to_vmx(vcpu);
3829         int r;
3830
3831         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3832         if (!r)
3833                 return 0;
3834
3835         if (!vcpu->arch.apicv_active)
3836                 return -1;
3837
3838         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
3839                 return 0;
3840
3841         /* If a previous notification has sent the IPI, nothing to do.  */
3842         if (pi_test_and_set_on(&vmx->pi_desc))
3843                 return 0;
3844
3845         if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
3846                 kvm_vcpu_kick(vcpu);
3847
3848         return 0;
3849 }
3850
3851 /*
3852  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3853  * will not change in the lifetime of the guest.
3854  * Note that host-state that does change is set elsewhere. E.g., host-state
3855  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3856  */
3857 void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
3858 {
3859         u32 low32, high32;
3860         unsigned long tmpl;
3861         unsigned long cr0, cr3, cr4;
3862
3863         cr0 = read_cr0();
3864         WARN_ON(cr0 & X86_CR0_TS);
3865         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
3866
3867         /*
3868          * Save the most likely value for this task's CR3 in the VMCS.
3869          * We can't use __get_current_cr3_fast() because we're not atomic.
3870          */
3871         cr3 = __read_cr3();
3872         vmcs_writel(HOST_CR3, cr3);             /* 22.2.3  FIXME: shadow tables */
3873         vmx->loaded_vmcs->host_state.cr3 = cr3;
3874
3875         /* Save the most likely value for this task's CR4 in the VMCS. */
3876         cr4 = cr4_read_shadow();
3877         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
3878         vmx->loaded_vmcs->host_state.cr4 = cr4;
3879
3880         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
3881 #ifdef CONFIG_X86_64
3882         /*
3883          * Load null selectors, so we can avoid reloading them in
3884          * vmx_prepare_switch_to_host(), in case userspace uses
3885          * the null selectors too (the expected case).
3886          */
3887         vmcs_write16(HOST_DS_SELECTOR, 0);
3888         vmcs_write16(HOST_ES_SELECTOR, 0);
3889 #else
3890         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3891         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3892 #endif
3893         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3894         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
3895
3896         vmcs_writel(HOST_IDTR_BASE, host_idt_base);   /* 22.2.4 */
3897
3898         vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
3899
3900         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3901         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3902         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3903         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
3904
3905         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3906                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3907                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3908         }
3909
3910         if (cpu_has_load_ia32_efer())
3911                 vmcs_write64(HOST_IA32_EFER, host_efer);
3912 }
3913
3914 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3915 {
3916         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3917         if (enable_ept)
3918                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3919         if (is_guest_mode(&vmx->vcpu))
3920                 vmx->vcpu.arch.cr4_guest_owned_bits &=
3921                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3922         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3923 }
3924
3925 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
3926 {
3927         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
3928
3929         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
3930                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
3931
3932         if (!enable_vnmi)
3933                 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
3934
3935         if (!enable_preemption_timer)
3936                 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3937
3938         return pin_based_exec_ctrl;
3939 }
3940
3941 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
3942 {
3943         struct vcpu_vmx *vmx = to_vmx(vcpu);
3944
3945         pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
3946         if (cpu_has_secondary_exec_ctrls()) {
3947                 if (kvm_vcpu_apicv_active(vcpu))
3948                         secondary_exec_controls_setbit(vmx,
3949                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
3950                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3951                 else
3952                         secondary_exec_controls_clearbit(vmx,
3953                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3954                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3955         }
3956
3957         if (cpu_has_vmx_msr_bitmap())
3958                 vmx_update_msr_bitmap(vcpu);
3959 }
3960
3961 u32 vmx_exec_control(struct vcpu_vmx *vmx)
3962 {
3963         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3964
3965         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
3966                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
3967
3968         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
3969                 exec_control &= ~CPU_BASED_TPR_SHADOW;
3970 #ifdef CONFIG_X86_64
3971                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3972                                 CPU_BASED_CR8_LOAD_EXITING;
3973 #endif
3974         }
3975         if (!enable_ept)
3976                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3977                                 CPU_BASED_CR3_LOAD_EXITING  |
3978                                 CPU_BASED_INVLPG_EXITING;
3979         if (kvm_mwait_in_guest(vmx->vcpu.kvm))
3980                 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
3981                                 CPU_BASED_MONITOR_EXITING);
3982         if (kvm_hlt_in_guest(vmx->vcpu.kvm))
3983                 exec_control &= ~CPU_BASED_HLT_EXITING;
3984         return exec_control;
3985 }
3986
3987
3988 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
3989 {
3990         struct kvm_vcpu *vcpu = &vmx->vcpu;
3991
3992         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3993
3994         if (vmx_pt_mode_is_system())
3995                 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
3996         if (!cpu_need_virtualize_apic_accesses(vcpu))
3997                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3998         if (vmx->vpid == 0)
3999                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4000         if (!enable_ept) {
4001                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4002                 enable_unrestricted_guest = 0;
4003         }
4004         if (!enable_unrestricted_guest)
4005                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4006         if (kvm_pause_in_guest(vmx->vcpu.kvm))
4007                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4008         if (!kvm_vcpu_apicv_active(vcpu))
4009                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4010                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4011         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4012
4013         /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
4014          * in vmx_set_cr4.  */
4015         exec_control &= ~SECONDARY_EXEC_DESC;
4016
4017         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4018            (handle_vmptrld).
4019            We can NOT enable shadow_vmcs here because we don't have yet
4020            a current VMCS12
4021         */
4022         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4023
4024         if (!enable_pml)
4025                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4026
4027         if (vmx_xsaves_supported()) {
4028                 /* Exposing XSAVES only when XSAVE is exposed */
4029                 bool xsaves_enabled =
4030                         boot_cpu_has(X86_FEATURE_XSAVE) &&
4031                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4032                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
4033
4034                 vcpu->arch.xsaves_enabled = xsaves_enabled;
4035
4036                 if (!xsaves_enabled)
4037                         exec_control &= ~SECONDARY_EXEC_XSAVES;
4038
4039                 if (nested) {
4040                         if (xsaves_enabled)
4041                                 vmx->nested.msrs.secondary_ctls_high |=
4042                                         SECONDARY_EXEC_XSAVES;
4043                         else
4044                                 vmx->nested.msrs.secondary_ctls_high &=
4045                                         ~SECONDARY_EXEC_XSAVES;
4046                 }
4047         }
4048
4049         if (cpu_has_vmx_rdtscp()) {
4050                 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
4051                 if (!rdtscp_enabled)
4052                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
4053
4054                 if (nested) {
4055                         if (rdtscp_enabled)
4056                                 vmx->nested.msrs.secondary_ctls_high |=
4057                                         SECONDARY_EXEC_RDTSCP;
4058                         else
4059                                 vmx->nested.msrs.secondary_ctls_high &=
4060                                         ~SECONDARY_EXEC_RDTSCP;
4061                 }
4062         }
4063
4064         if (cpu_has_vmx_invpcid()) {
4065                 /* Exposing INVPCID only when PCID is exposed */
4066                 bool invpcid_enabled =
4067                         guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
4068                         guest_cpuid_has(vcpu, X86_FEATURE_PCID);
4069
4070                 if (!invpcid_enabled) {
4071                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4072                         guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
4073                 }
4074
4075                 if (nested) {
4076                         if (invpcid_enabled)
4077                                 vmx->nested.msrs.secondary_ctls_high |=
4078                                         SECONDARY_EXEC_ENABLE_INVPCID;
4079                         else
4080                                 vmx->nested.msrs.secondary_ctls_high &=
4081                                         ~SECONDARY_EXEC_ENABLE_INVPCID;
4082                 }
4083         }
4084
4085         if (vmx_rdrand_supported()) {
4086                 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
4087                 if (rdrand_enabled)
4088                         exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
4089
4090                 if (nested) {
4091                         if (rdrand_enabled)
4092                                 vmx->nested.msrs.secondary_ctls_high |=
4093                                         SECONDARY_EXEC_RDRAND_EXITING;
4094                         else
4095                                 vmx->nested.msrs.secondary_ctls_high &=
4096                                         ~SECONDARY_EXEC_RDRAND_EXITING;
4097                 }
4098         }
4099
4100         if (vmx_rdseed_supported()) {
4101                 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
4102                 if (rdseed_enabled)
4103                         exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
4104
4105                 if (nested) {
4106                         if (rdseed_enabled)
4107                                 vmx->nested.msrs.secondary_ctls_high |=
4108                                         SECONDARY_EXEC_RDSEED_EXITING;
4109                         else
4110                                 vmx->nested.msrs.secondary_ctls_high &=
4111                                         ~SECONDARY_EXEC_RDSEED_EXITING;
4112                 }
4113         }
4114
4115         if (vmx_waitpkg_supported()) {
4116                 bool waitpkg_enabled =
4117                         guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG);
4118
4119                 if (!waitpkg_enabled)
4120                         exec_control &= ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4121
4122                 if (nested) {
4123                         if (waitpkg_enabled)
4124                                 vmx->nested.msrs.secondary_ctls_high |=
4125                                         SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4126                         else
4127                                 vmx->nested.msrs.secondary_ctls_high &=
4128                                         ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4129                 }
4130         }
4131
4132         vmx->secondary_exec_control = exec_control;
4133 }
4134
4135 static void ept_set_mmio_spte_mask(void)
4136 {
4137         /*
4138          * EPT Misconfigurations can be generated if the value of bits 2:0
4139          * of an EPT paging-structure entry is 110b (write/execute).
4140          */
4141         kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
4142                                    VMX_EPT_MISCONFIG_WX_VALUE, 0);
4143 }
4144
4145 #define VMX_XSS_EXIT_BITMAP 0
4146
4147 /*
4148  * Noting that the initialization of Guest-state Area of VMCS is in
4149  * vmx_vcpu_reset().
4150  */
4151 static void init_vmcs(struct vcpu_vmx *vmx)
4152 {
4153         if (nested)
4154                 nested_vmx_set_vmcs_shadowing_bitmap();
4155
4156         if (cpu_has_vmx_msr_bitmap())
4157                 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
4158
4159         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4160
4161         /* Control */
4162         pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4163
4164         exec_controls_set(vmx, vmx_exec_control(vmx));
4165
4166         if (cpu_has_secondary_exec_ctrls()) {
4167                 vmx_compute_secondary_exec_control(vmx);
4168                 secondary_exec_controls_set(vmx, vmx->secondary_exec_control);
4169         }
4170
4171         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4172                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4173                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4174                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4175                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4176
4177                 vmcs_write16(GUEST_INTR_STATUS, 0);
4178
4179                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4180                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4181         }
4182
4183         if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4184                 vmcs_write32(PLE_GAP, ple_gap);
4185                 vmx->ple_window = ple_window;
4186                 vmx->ple_window_dirty = true;
4187         }
4188
4189         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4190         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4191         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4192
4193         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4194         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4195         vmx_set_constant_host_state(vmx);
4196         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4197         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4198
4199         if (cpu_has_vmx_vmfunc())
4200                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4201
4202         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4203         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4204         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
4205         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4206         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
4207
4208         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4209                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4210
4211         vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
4212
4213         /* 22.2.1, 20.8.1 */
4214         vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
4215
4216         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
4217         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
4218
4219         set_cr4_guest_host_mask(vmx);
4220
4221         if (vmx->vpid != 0)
4222                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4223
4224         if (vmx_xsaves_supported())
4225                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4226
4227         if (enable_pml) {
4228                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4229                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4230         }
4231
4232         if (cpu_has_vmx_encls_vmexit())
4233                 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
4234
4235         if (vmx_pt_mode_is_host_guest()) {
4236                 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4237                 /* Bit[6~0] are forced to 1, writes are ignored. */
4238                 vmx->pt_desc.guest.output_mask = 0x7F;
4239                 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4240         }
4241 }
4242
4243 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4244 {
4245         struct vcpu_vmx *vmx = to_vmx(vcpu);
4246         struct msr_data apic_base_msr;
4247         u64 cr0;
4248
4249         vmx->rmode.vm86_active = 0;
4250         vmx->spec_ctrl = 0;
4251
4252         vmx->msr_ia32_umwait_control = 0;
4253
4254         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4255         vmx->hv_deadline_tsc = -1;
4256         kvm_set_cr8(vcpu, 0);
4257
4258         if (!init_event) {
4259                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4260                                      MSR_IA32_APICBASE_ENABLE;
4261                 if (kvm_vcpu_is_reset_bsp(vcpu))
4262                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4263                 apic_base_msr.host_initiated = true;
4264                 kvm_set_apic_base(vcpu, &apic_base_msr);
4265         }
4266
4267         vmx_segment_cache_clear(vmx);
4268
4269         seg_setup(VCPU_SREG_CS);
4270         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4271         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4272
4273         seg_setup(VCPU_SREG_DS);
4274         seg_setup(VCPU_SREG_ES);
4275         seg_setup(VCPU_SREG_FS);
4276         seg_setup(VCPU_SREG_GS);
4277         seg_setup(VCPU_SREG_SS);
4278
4279         vmcs_write16(GUEST_TR_SELECTOR, 0);
4280         vmcs_writel(GUEST_TR_BASE, 0);
4281         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4282         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4283
4284         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4285         vmcs_writel(GUEST_LDTR_BASE, 0);
4286         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4287         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4288
4289         if (!init_event) {
4290                 vmcs_write32(GUEST_SYSENTER_CS, 0);
4291                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4292                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4293                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4294         }
4295
4296         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
4297         kvm_rip_write(vcpu, 0xfff0);
4298
4299         vmcs_writel(GUEST_GDTR_BASE, 0);
4300         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4301
4302         vmcs_writel(GUEST_IDTR_BASE, 0);
4303         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4304
4305         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4306         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4307         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4308         if (kvm_mpx_supported())
4309                 vmcs_write64(GUEST_BNDCFGS, 0);
4310
4311         setup_msrs(vmx);
4312
4313         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4314
4315         if (cpu_has_vmx_tpr_shadow() && !init_event) {
4316                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4317                 if (cpu_need_tpr_shadow(vcpu))
4318                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4319                                      __pa(vcpu->arch.apic->regs));
4320                 vmcs_write32(TPR_THRESHOLD, 0);
4321         }
4322
4323         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4324
4325         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4326         vmx->vcpu.arch.cr0 = cr0;
4327         vmx_set_cr0(vcpu, cr0); /* enter rmode */
4328         vmx_set_cr4(vcpu, 0);
4329         vmx_set_efer(vcpu, 0);
4330
4331         update_exception_bitmap(vcpu);
4332
4333         vpid_sync_context(vmx->vpid);
4334         if (init_event)
4335                 vmx_clear_hlt(vcpu);
4336 }
4337
4338 static void enable_irq_window(struct kvm_vcpu *vcpu)
4339 {
4340         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
4341 }
4342
4343 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4344 {
4345         if (!enable_vnmi ||
4346             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4347                 enable_irq_window(vcpu);
4348                 return;
4349         }
4350
4351         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
4352 }
4353
4354 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4355 {
4356         struct vcpu_vmx *vmx = to_vmx(vcpu);
4357         uint32_t intr;
4358         int irq = vcpu->arch.interrupt.nr;
4359
4360         trace_kvm_inj_virq(irq);
4361
4362         ++vcpu->stat.irq_injections;
4363         if (vmx->rmode.vm86_active) {
4364                 int inc_eip = 0;
4365                 if (vcpu->arch.interrupt.soft)
4366                         inc_eip = vcpu->arch.event_exit_inst_len;
4367                 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
4368                 return;
4369         }
4370         intr = irq | INTR_INFO_VALID_MASK;
4371         if (vcpu->arch.interrupt.soft) {
4372                 intr |= INTR_TYPE_SOFT_INTR;
4373                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4374                              vmx->vcpu.arch.event_exit_inst_len);
4375         } else
4376                 intr |= INTR_TYPE_EXT_INTR;
4377         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4378
4379         vmx_clear_hlt(vcpu);
4380 }
4381
4382 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4383 {
4384         struct vcpu_vmx *vmx = to_vmx(vcpu);
4385
4386         if (!enable_vnmi) {
4387                 /*
4388                  * Tracking the NMI-blocked state in software is built upon
4389                  * finding the next open IRQ window. This, in turn, depends on
4390                  * well-behaving guests: They have to keep IRQs disabled at
4391                  * least as long as the NMI handler runs. Otherwise we may
4392                  * cause NMI nesting, maybe breaking the guest. But as this is
4393                  * highly unlikely, we can live with the residual risk.
4394                  */
4395                 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4396                 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4397         }
4398
4399         ++vcpu->stat.nmi_injections;
4400         vmx->loaded_vmcs->nmi_known_unmasked = false;
4401
4402         if (vmx->rmode.vm86_active) {
4403                 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
4404                 return;
4405         }
4406
4407         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4408                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4409
4410         vmx_clear_hlt(vcpu);
4411 }
4412
4413 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4414 {
4415         struct vcpu_vmx *vmx = to_vmx(vcpu);
4416         bool masked;
4417
4418         if (!enable_vnmi)
4419                 return vmx->loaded_vmcs->soft_vnmi_blocked;
4420         if (vmx->loaded_vmcs->nmi_known_unmasked)
4421                 return false;
4422         masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4423         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4424         return masked;
4425 }
4426
4427 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4428 {
4429         struct vcpu_vmx *vmx = to_vmx(vcpu);
4430
4431         if (!enable_vnmi) {
4432                 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4433                         vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4434                         vmx->loaded_vmcs->vnmi_blocked_time = 0;
4435                 }
4436         } else {
4437                 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4438                 if (masked)
4439                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4440                                       GUEST_INTR_STATE_NMI);
4441                 else
4442                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4443                                         GUEST_INTR_STATE_NMI);
4444         }
4445 }
4446
4447 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4448 {
4449         if (to_vmx(vcpu)->nested.nested_run_pending)
4450                 return 0;
4451
4452         if (!enable_vnmi &&
4453             to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4454                 return 0;
4455
4456         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4457                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4458                    | GUEST_INTR_STATE_NMI));
4459 }
4460
4461 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4462 {
4463         if (to_vmx(vcpu)->nested.nested_run_pending)
4464                 return false;
4465
4466         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4467                 return true;
4468
4469         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4470                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4471                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4472 }
4473
4474 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4475 {
4476         int ret;
4477
4478         if (enable_unrestricted_guest)
4479                 return 0;
4480
4481         mutex_lock(&kvm->slots_lock);
4482         ret = __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4483                                       PAGE_SIZE * 3);
4484         mutex_unlock(&kvm->slots_lock);
4485
4486         if (ret)
4487                 return ret;
4488         to_kvm_vmx(kvm)->tss_addr = addr;
4489         return init_rmode_tss(kvm);
4490 }
4491
4492 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4493 {
4494         to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
4495         return 0;
4496 }
4497
4498 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4499 {
4500         switch (vec) {
4501         case BP_VECTOR:
4502                 /*
4503                  * Update instruction length as we may reinject the exception
4504                  * from user space while in guest debugging mode.
4505                  */
4506                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4507                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4508                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4509                         return false;
4510                 /* fall through */
4511         case DB_VECTOR:
4512                 if (vcpu->guest_debug &
4513                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4514                         return false;
4515                 /* fall through */
4516         case DE_VECTOR:
4517         case OF_VECTOR:
4518         case BR_VECTOR:
4519         case UD_VECTOR:
4520         case DF_VECTOR:
4521         case SS_VECTOR:
4522         case GP_VECTOR:
4523         case MF_VECTOR:
4524                 return true;
4525         }
4526         return false;
4527 }
4528
4529 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4530                                   int vec, u32 err_code)
4531 {
4532         /*
4533          * Instruction with address size override prefix opcode 0x67
4534          * Cause the #SS fault with 0 error code in VM86 mode.
4535          */
4536         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4537                 if (kvm_emulate_instruction(vcpu, 0)) {
4538                         if (vcpu->arch.halt_request) {
4539                                 vcpu->arch.halt_request = 0;
4540                                 return kvm_vcpu_halt(vcpu);
4541                         }
4542                         return 1;
4543                 }
4544                 return 0;
4545         }
4546
4547         /*
4548          * Forward all other exceptions that are valid in real mode.
4549          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4550          *        the required debugging infrastructure rework.
4551          */
4552         kvm_queue_exception(vcpu, vec);
4553         return 1;
4554 }
4555
4556 /*
4557  * Trigger machine check on the host. We assume all the MSRs are already set up
4558  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4559  * We pass a fake environment to the machine check handler because we want
4560  * the guest to be always treated like user space, no matter what context
4561  * it used internally.
4562  */
4563 static void kvm_machine_check(void)
4564 {
4565 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4566         struct pt_regs regs = {
4567                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4568                 .flags = X86_EFLAGS_IF,
4569         };
4570
4571         do_machine_check(&regs, 0);
4572 #endif
4573 }
4574
4575 static int handle_machine_check(struct kvm_vcpu *vcpu)
4576 {
4577         /* handled by vmx_vcpu_run() */
4578         return 1;
4579 }
4580
4581 static int handle_exception_nmi(struct kvm_vcpu *vcpu)
4582 {
4583         struct vcpu_vmx *vmx = to_vmx(vcpu);
4584         struct kvm_run *kvm_run = vcpu->run;
4585         u32 intr_info, ex_no, error_code;
4586         unsigned long cr2, rip, dr6;
4587         u32 vect_info;
4588
4589         vect_info = vmx->idt_vectoring_info;
4590         intr_info = vmx->exit_intr_info;
4591
4592         if (is_machine_check(intr_info) || is_nmi(intr_info))
4593                 return 1; /* handled by handle_exception_nmi_irqoff() */
4594
4595         if (is_invalid_opcode(intr_info))
4596                 return handle_ud(vcpu);
4597
4598         error_code = 0;
4599         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4600                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4601
4602         if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4603                 WARN_ON_ONCE(!enable_vmware_backdoor);
4604
4605                 /*
4606                  * VMware backdoor emulation on #GP interception only handles
4607                  * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
4608                  * error code on #GP.
4609                  */
4610                 if (error_code) {
4611                         kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4612                         return 1;
4613                 }
4614                 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
4615         }
4616
4617         /*
4618          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4619          * MMIO, it is better to report an internal error.
4620          * See the comments in vmx_handle_exit.
4621          */
4622         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4623             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4624                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4625                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4626                 vcpu->run->internal.ndata = 3;
4627                 vcpu->run->internal.data[0] = vect_info;
4628                 vcpu->run->internal.data[1] = intr_info;
4629                 vcpu->run->internal.data[2] = error_code;
4630                 return 0;
4631         }
4632
4633         if (is_page_fault(intr_info)) {
4634                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4635                 /* EPT won't cause page fault directly */
4636                 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
4637                 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
4638         }
4639
4640         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4641
4642         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4643                 return handle_rmode_exception(vcpu, ex_no, error_code);
4644
4645         switch (ex_no) {
4646         case AC_VECTOR:
4647                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4648                 return 1;
4649         case DB_VECTOR:
4650                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4651                 if (!(vcpu->guest_debug &
4652                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4653                         vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4654                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
4655                         if (is_icebp(intr_info))
4656                                 WARN_ON(!skip_emulated_instruction(vcpu));
4657
4658                         kvm_queue_exception(vcpu, DB_VECTOR);
4659                         return 1;
4660                 }
4661                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4662                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4663                 /* fall through */
4664         case BP_VECTOR:
4665                 /*
4666                  * Update instruction length as we may reinject #BP from
4667                  * user space while in guest debugging mode. Reading it for
4668                  * #DB as well causes no harm, it is not used in that case.
4669                  */
4670                 vmx->vcpu.arch.event_exit_inst_len =
4671                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4672                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4673                 rip = kvm_rip_read(vcpu);
4674                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4675                 kvm_run->debug.arch.exception = ex_no;
4676                 break;
4677         default:
4678                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4679                 kvm_run->ex.exception = ex_no;
4680                 kvm_run->ex.error_code = error_code;
4681                 break;
4682         }
4683         return 0;
4684 }
4685
4686 static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu)
4687 {
4688         ++vcpu->stat.irq_exits;
4689         return 1;
4690 }
4691
4692 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4693 {
4694         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4695         vcpu->mmio_needed = 0;
4696         return 0;
4697 }
4698
4699 static int handle_io(struct kvm_vcpu *vcpu)
4700 {
4701         unsigned long exit_qualification;
4702         int size, in, string;
4703         unsigned port;
4704
4705         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4706         string = (exit_qualification & 16) != 0;
4707
4708         ++vcpu->stat.io_exits;
4709
4710         if (string)
4711                 return kvm_emulate_instruction(vcpu, 0);
4712
4713         port = exit_qualification >> 16;
4714         size = (exit_qualification & 7) + 1;
4715         in = (exit_qualification & 8) != 0;
4716
4717         return kvm_fast_pio(vcpu, size, port, in);
4718 }
4719
4720 static void
4721 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4722 {
4723         /*
4724          * Patch in the VMCALL instruction:
4725          */
4726         hypercall[0] = 0x0f;
4727         hypercall[1] = 0x01;
4728         hypercall[2] = 0xc1;
4729 }
4730
4731 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4732 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4733 {
4734         if (is_guest_mode(vcpu)) {
4735                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4736                 unsigned long orig_val = val;
4737
4738                 /*
4739                  * We get here when L2 changed cr0 in a way that did not change
4740                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4741                  * but did change L0 shadowed bits. So we first calculate the
4742                  * effective cr0 value that L1 would like to write into the
4743                  * hardware. It consists of the L2-owned bits from the new
4744                  * value combined with the L1-owned bits from L1's guest_cr0.
4745                  */
4746                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4747                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4748
4749                 if (!nested_guest_cr0_valid(vcpu, val))
4750                         return 1;
4751
4752                 if (kvm_set_cr0(vcpu, val))
4753                         return 1;
4754                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4755                 return 0;
4756         } else {
4757                 if (to_vmx(vcpu)->nested.vmxon &&
4758                     !nested_host_cr0_valid(vcpu, val))
4759                         return 1;
4760
4761                 return kvm_set_cr0(vcpu, val);
4762         }
4763 }
4764
4765 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4766 {
4767         if (is_guest_mode(vcpu)) {
4768                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4769                 unsigned long orig_val = val;
4770
4771                 /* analogously to handle_set_cr0 */
4772                 val = (val & ~vmcs12->cr4_guest_host_mask) |
4773                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4774                 if (kvm_set_cr4(vcpu, val))
4775                         return 1;
4776                 vmcs_writel(CR4_READ_SHADOW, orig_val);
4777                 return 0;
4778         } else
4779                 return kvm_set_cr4(vcpu, val);
4780 }
4781
4782 static int handle_desc(struct kvm_vcpu *vcpu)
4783 {
4784         WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
4785         return kvm_emulate_instruction(vcpu, 0);
4786 }
4787
4788 static int handle_cr(struct kvm_vcpu *vcpu)
4789 {
4790         unsigned long exit_qualification, val;
4791         int cr;
4792         int reg;
4793         int err;
4794         int ret;
4795
4796         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4797         cr = exit_qualification & 15;
4798         reg = (exit_qualification >> 8) & 15;
4799         switch ((exit_qualification >> 4) & 3) {
4800         case 0: /* mov to cr */
4801                 val = kvm_register_readl(vcpu, reg);
4802                 trace_kvm_cr_write(cr, val);
4803                 switch (cr) {
4804                 case 0:
4805                         err = handle_set_cr0(vcpu, val);
4806                         return kvm_complete_insn_gp(vcpu, err);
4807                 case 3:
4808                         WARN_ON_ONCE(enable_unrestricted_guest);
4809                         err = kvm_set_cr3(vcpu, val);
4810                         return kvm_complete_insn_gp(vcpu, err);
4811                 case 4:
4812                         err = handle_set_cr4(vcpu, val);
4813                         return kvm_complete_insn_gp(vcpu, err);
4814                 case 8: {
4815                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4816                                 u8 cr8 = (u8)val;
4817                                 err = kvm_set_cr8(vcpu, cr8);
4818                                 ret = kvm_complete_insn_gp(vcpu, err);
4819                                 if (lapic_in_kernel(vcpu))
4820                                         return ret;
4821                                 if (cr8_prev <= cr8)
4822                                         return ret;
4823                                 /*
4824                                  * TODO: we might be squashing a
4825                                  * KVM_GUESTDBG_SINGLESTEP-triggered
4826                                  * KVM_EXIT_DEBUG here.
4827                                  */
4828                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4829                                 return 0;
4830                         }
4831                 }
4832                 break;
4833         case 2: /* clts */
4834                 WARN_ONCE(1, "Guest should always own CR0.TS");
4835                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4836                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4837                 return kvm_skip_emulated_instruction(vcpu);
4838         case 1: /*mov from cr*/
4839                 switch (cr) {
4840                 case 3:
4841                         WARN_ON_ONCE(enable_unrestricted_guest);
4842                         val = kvm_read_cr3(vcpu);
4843                         kvm_register_write(vcpu, reg, val);
4844                         trace_kvm_cr_read(cr, val);
4845                         return kvm_skip_emulated_instruction(vcpu);
4846                 case 8:
4847                         val = kvm_get_cr8(vcpu);
4848                         kvm_register_write(vcpu, reg, val);
4849                         trace_kvm_cr_read(cr, val);
4850                         return kvm_skip_emulated_instruction(vcpu);
4851                 }
4852                 break;
4853         case 3: /* lmsw */
4854                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4855                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4856                 kvm_lmsw(vcpu, val);
4857
4858                 return kvm_skip_emulated_instruction(vcpu);
4859         default:
4860                 break;
4861         }
4862         vcpu->run->exit_reason = 0;
4863         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4864                (int)(exit_qualification >> 4) & 3, cr);
4865         return 0;
4866 }
4867
4868 static int handle_dr(struct kvm_vcpu *vcpu)
4869 {
4870         unsigned long exit_qualification;
4871         int dr, dr7, reg;
4872
4873         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4874         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4875
4876         /* First, if DR does not exist, trigger UD */
4877         if (!kvm_require_dr(vcpu, dr))
4878                 return 1;
4879
4880         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4881         if (!kvm_require_cpl(vcpu, 0))
4882                 return 1;
4883         dr7 = vmcs_readl(GUEST_DR7);
4884         if (dr7 & DR7_GD) {
4885                 /*
4886                  * As the vm-exit takes precedence over the debug trap, we
4887                  * need to emulate the latter, either for the host or the
4888                  * guest debugging itself.
4889                  */
4890                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4891                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4892                         vcpu->run->debug.arch.dr7 = dr7;
4893                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
4894                         vcpu->run->debug.arch.exception = DB_VECTOR;
4895                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4896                         return 0;
4897                 } else {
4898                         vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4899                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
4900                         kvm_queue_exception(vcpu, DB_VECTOR);
4901                         return 1;
4902                 }
4903         }
4904
4905         if (vcpu->guest_debug == 0) {
4906                 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
4907
4908                 /*
4909                  * No more DR vmexits; force a reload of the debug registers
4910                  * and reenter on this instruction.  The next vmexit will
4911                  * retrieve the full state of the debug registers.
4912                  */
4913                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4914                 return 1;
4915         }
4916
4917         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4918         if (exit_qualification & TYPE_MOV_FROM_DR) {
4919                 unsigned long val;
4920
4921                 if (kvm_get_dr(vcpu, dr, &val))
4922                         return 1;
4923                 kvm_register_write(vcpu, reg, val);
4924         } else
4925                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4926                         return 1;
4927
4928         return kvm_skip_emulated_instruction(vcpu);
4929 }
4930
4931 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
4932 {
4933         return vcpu->arch.dr6;
4934 }
4935
4936 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
4937 {
4938 }
4939
4940 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
4941 {
4942         get_debugreg(vcpu->arch.db[0], 0);
4943         get_debugreg(vcpu->arch.db[1], 1);
4944         get_debugreg(vcpu->arch.db[2], 2);
4945         get_debugreg(vcpu->arch.db[3], 3);
4946         get_debugreg(vcpu->arch.dr6, 6);
4947         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
4948
4949         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
4950         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
4951 }
4952
4953 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4954 {
4955         vmcs_writel(GUEST_DR7, val);
4956 }
4957
4958 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4959 {
4960         kvm_apic_update_ppr(vcpu);
4961         return 1;
4962 }
4963
4964 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4965 {
4966         exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
4967
4968         kvm_make_request(KVM_REQ_EVENT, vcpu);
4969
4970         ++vcpu->stat.irq_window_exits;
4971         return 1;
4972 }
4973
4974 static int handle_vmcall(struct kvm_vcpu *vcpu)
4975 {
4976         return kvm_emulate_hypercall(vcpu);
4977 }
4978
4979 static int handle_invd(struct kvm_vcpu *vcpu)
4980 {
4981         return kvm_emulate_instruction(vcpu, 0);
4982 }
4983
4984 static int handle_invlpg(struct kvm_vcpu *vcpu)
4985 {
4986         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4987
4988         kvm_mmu_invlpg(vcpu, exit_qualification);
4989         return kvm_skip_emulated_instruction(vcpu);
4990 }
4991
4992 static int handle_rdpmc(struct kvm_vcpu *vcpu)
4993 {
4994         int err;
4995
4996         err = kvm_rdpmc(vcpu);
4997         return kvm_complete_insn_gp(vcpu, err);
4998 }
4999
5000 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5001 {
5002         return kvm_emulate_wbinvd(vcpu);
5003 }
5004
5005 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5006 {
5007         u64 new_bv = kvm_read_edx_eax(vcpu);
5008         u32 index = kvm_rcx_read(vcpu);
5009
5010         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5011                 return kvm_skip_emulated_instruction(vcpu);
5012         return 1;
5013 }
5014
5015 static int handle_apic_access(struct kvm_vcpu *vcpu)
5016 {
5017         if (likely(fasteoi)) {
5018                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5019                 int access_type, offset;
5020
5021                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5022                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5023                 /*
5024                  * Sane guest uses MOV to write EOI, with written value
5025                  * not cared. So make a short-circuit here by avoiding
5026                  * heavy instruction emulation.
5027                  */
5028                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5029                     (offset == APIC_EOI)) {
5030                         kvm_lapic_set_eoi(vcpu);
5031                         return kvm_skip_emulated_instruction(vcpu);
5032                 }
5033         }
5034         return kvm_emulate_instruction(vcpu, 0);
5035 }
5036
5037 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5038 {
5039         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5040         int vector = exit_qualification & 0xff;
5041
5042         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5043         kvm_apic_set_eoi_accelerated(vcpu, vector);
5044         return 1;
5045 }
5046
5047 static int handle_apic_write(struct kvm_vcpu *vcpu)
5048 {
5049         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5050         u32 offset = exit_qualification & 0xfff;
5051
5052         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5053         kvm_apic_write_nodecode(vcpu, offset);
5054         return 1;
5055 }
5056
5057 static int handle_task_switch(struct kvm_vcpu *vcpu)
5058 {
5059         struct vcpu_vmx *vmx = to_vmx(vcpu);
5060         unsigned long exit_qualification;
5061         bool has_error_code = false;
5062         u32 error_code = 0;
5063         u16 tss_selector;
5064         int reason, type, idt_v, idt_index;
5065
5066         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5067         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5068         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5069
5070         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5071
5072         reason = (u32)exit_qualification >> 30;
5073         if (reason == TASK_SWITCH_GATE && idt_v) {
5074                 switch (type) {
5075                 case INTR_TYPE_NMI_INTR:
5076                         vcpu->arch.nmi_injected = false;
5077                         vmx_set_nmi_mask(vcpu, true);
5078                         break;
5079                 case INTR_TYPE_EXT_INTR:
5080                 case INTR_TYPE_SOFT_INTR:
5081                         kvm_clear_interrupt_queue(vcpu);
5082                         break;
5083                 case INTR_TYPE_HARD_EXCEPTION:
5084                         if (vmx->idt_vectoring_info &
5085                             VECTORING_INFO_DELIVER_CODE_MASK) {
5086                                 has_error_code = true;
5087                                 error_code =
5088                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5089                         }
5090                         /* fall through */
5091                 case INTR_TYPE_SOFT_EXCEPTION:
5092                         kvm_clear_exception_queue(vcpu);
5093                         break;
5094                 default:
5095                         break;
5096                 }
5097         }
5098         tss_selector = exit_qualification;
5099
5100         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5101                        type != INTR_TYPE_EXT_INTR &&
5102                        type != INTR_TYPE_NMI_INTR))
5103                 WARN_ON(!skip_emulated_instruction(vcpu));
5104
5105         /*
5106          * TODO: What about debug traps on tss switch?
5107          *       Are we supposed to inject them and update dr6?
5108          */
5109         return kvm_task_switch(vcpu, tss_selector,
5110                                type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
5111                                reason, has_error_code, error_code);
5112 }
5113
5114 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5115 {
5116         unsigned long exit_qualification;
5117         gpa_t gpa;
5118         u64 error_code;
5119
5120         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5121
5122         /*
5123          * EPT violation happened while executing iret from NMI,
5124          * "blocked by NMI" bit has to be set before next VM entry.
5125          * There are errata that may cause this bit to not be set:
5126          * AAK134, BY25.
5127          */
5128         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5129                         enable_vnmi &&
5130                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5131                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5132
5133         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5134         trace_kvm_page_fault(gpa, exit_qualification);
5135
5136         /* Is it a read fault? */
5137         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
5138                      ? PFERR_USER_MASK : 0;
5139         /* Is it a write fault? */
5140         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
5141                       ? PFERR_WRITE_MASK : 0;
5142         /* Is it a fetch fault? */
5143         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
5144                       ? PFERR_FETCH_MASK : 0;
5145         /* ept page table entry is present? */
5146         error_code |= (exit_qualification &
5147                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5148                         EPT_VIOLATION_EXECUTABLE))
5149                       ? PFERR_PRESENT_MASK : 0;
5150
5151         error_code |= (exit_qualification & 0x100) != 0 ?
5152                PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
5153
5154         vcpu->arch.exit_qualification = exit_qualification;
5155         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5156 }
5157
5158 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5159 {
5160         gpa_t gpa;
5161
5162         /*
5163          * A nested guest cannot optimize MMIO vmexits, because we have an
5164          * nGPA here instead of the required GPA.
5165          */
5166         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5167         if (!is_guest_mode(vcpu) &&
5168             !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5169                 trace_kvm_fast_mmio(gpa);
5170                 return kvm_skip_emulated_instruction(vcpu);
5171         }
5172
5173         return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
5174 }
5175
5176 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5177 {
5178         WARN_ON_ONCE(!enable_vnmi);
5179         exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
5180         ++vcpu->stat.nmi_window_exits;
5181         kvm_make_request(KVM_REQ_EVENT, vcpu);
5182
5183         return 1;
5184 }
5185
5186 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5187 {
5188         struct vcpu_vmx *vmx = to_vmx(vcpu);
5189         bool intr_window_requested;
5190         unsigned count = 130;
5191
5192         /*
5193          * We should never reach the point where we are emulating L2
5194          * due to invalid guest state as that means we incorrectly
5195          * allowed a nested VMEntry with an invalid vmcs12.
5196          */
5197         WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
5198
5199         intr_window_requested = exec_controls_get(vmx) &
5200                                 CPU_BASED_INTR_WINDOW_EXITING;
5201
5202         while (vmx->emulation_required && count-- != 0) {
5203                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5204                         return handle_interrupt_window(&vmx->vcpu);
5205
5206                 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
5207                         return 1;
5208
5209                 if (!kvm_emulate_instruction(vcpu, 0))
5210                         return 0;
5211
5212                 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5213                     vcpu->arch.exception.pending) {
5214                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5215                         vcpu->run->internal.suberror =
5216                                                 KVM_INTERNAL_ERROR_EMULATION;
5217                         vcpu->run->internal.ndata = 0;
5218                         return 0;
5219                 }
5220
5221                 if (vcpu->arch.halt_request) {
5222                         vcpu->arch.halt_request = 0;
5223                         return kvm_vcpu_halt(vcpu);
5224                 }
5225
5226                 /*
5227                  * Note, return 1 and not 0, vcpu_run() is responsible for
5228                  * morphing the pending signal into the proper return code.
5229                  */
5230                 if (signal_pending(current))
5231                         return 1;
5232
5233                 if (need_resched())
5234                         schedule();
5235         }
5236
5237         return 1;
5238 }
5239
5240 static void grow_ple_window(struct kvm_vcpu *vcpu)
5241 {
5242         struct vcpu_vmx *vmx = to_vmx(vcpu);
5243         unsigned int old = vmx->ple_window;
5244
5245         vmx->ple_window = __grow_ple_window(old, ple_window,
5246                                             ple_window_grow,
5247                                             ple_window_max);
5248
5249         if (vmx->ple_window != old) {
5250                 vmx->ple_window_dirty = true;
5251                 trace_kvm_ple_window_update(vcpu->vcpu_id,
5252                                             vmx->ple_window, old);
5253         }
5254 }
5255
5256 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5257 {
5258         struct vcpu_vmx *vmx = to_vmx(vcpu);
5259         unsigned int old = vmx->ple_window;
5260
5261         vmx->ple_window = __shrink_ple_window(old, ple_window,
5262                                               ple_window_shrink,
5263                                               ple_window);
5264
5265         if (vmx->ple_window != old) {
5266                 vmx->ple_window_dirty = true;
5267                 trace_kvm_ple_window_update(vcpu->vcpu_id,
5268                                             vmx->ple_window, old);
5269         }
5270 }
5271
5272 /*
5273  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
5274  */
5275 static void wakeup_handler(void)
5276 {
5277         struct kvm_vcpu *vcpu;
5278         int cpu = smp_processor_id();
5279
5280         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5281         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
5282                         blocked_vcpu_list) {
5283                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
5284
5285                 if (pi_test_on(pi_desc) == 1)
5286                         kvm_vcpu_kick(vcpu);
5287         }
5288         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5289 }
5290
5291 static void vmx_enable_tdp(void)
5292 {
5293         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
5294                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
5295                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
5296                 0ull, VMX_EPT_EXECUTABLE_MASK,
5297                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
5298                 VMX_EPT_RWX_MASK, 0ull);
5299
5300         ept_set_mmio_spte_mask();
5301 }
5302
5303 /*
5304  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5305  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5306  */
5307 static int handle_pause(struct kvm_vcpu *vcpu)
5308 {
5309         if (!kvm_pause_in_guest(vcpu->kvm))
5310                 grow_ple_window(vcpu);
5311
5312         /*
5313          * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5314          * VM-execution control is ignored if CPL > 0. OTOH, KVM
5315          * never set PAUSE_EXITING and just set PLE if supported,
5316          * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5317          */
5318         kvm_vcpu_on_spin(vcpu, true);
5319         return kvm_skip_emulated_instruction(vcpu);
5320 }
5321
5322 static int handle_nop(struct kvm_vcpu *vcpu)
5323 {
5324         return kvm_skip_emulated_instruction(vcpu);
5325 }
5326
5327 static int handle_mwait(struct kvm_vcpu *vcpu)
5328 {
5329         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5330         return handle_nop(vcpu);
5331 }
5332
5333 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5334 {
5335         kvm_queue_exception(vcpu, UD_VECTOR);
5336         return 1;
5337 }
5338
5339 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5340 {
5341         return 1;
5342 }
5343
5344 static int handle_monitor(struct kvm_vcpu *vcpu)
5345 {
5346         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5347         return handle_nop(vcpu);
5348 }
5349
5350 static int handle_invpcid(struct kvm_vcpu *vcpu)
5351 {
5352         u32 vmx_instruction_info;
5353         unsigned long type;
5354         bool pcid_enabled;
5355         gva_t gva;
5356         struct x86_exception e;
5357         unsigned i;
5358         unsigned long roots_to_free = 0;
5359         struct {
5360                 u64 pcid;
5361                 u64 gla;
5362         } operand;
5363
5364         if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
5365                 kvm_queue_exception(vcpu, UD_VECTOR);
5366                 return 1;
5367         }
5368
5369         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5370         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5371
5372         if (type > 3) {
5373                 kvm_inject_gp(vcpu, 0);
5374                 return 1;
5375         }
5376
5377         /* According to the Intel instruction reference, the memory operand
5378          * is read even if it isn't needed (e.g., for type==all)
5379          */
5380         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5381                                 vmx_instruction_info, false,
5382                                 sizeof(operand), &gva))
5383                 return 1;
5384
5385         if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
5386                 kvm_inject_page_fault(vcpu, &e);
5387                 return 1;
5388         }
5389
5390         if (operand.pcid >> 12 != 0) {
5391                 kvm_inject_gp(vcpu, 0);
5392                 return 1;
5393         }
5394
5395         pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
5396
5397         switch (type) {
5398         case INVPCID_TYPE_INDIV_ADDR:
5399                 if ((!pcid_enabled && (operand.pcid != 0)) ||
5400                     is_noncanonical_address(operand.gla, vcpu)) {
5401                         kvm_inject_gp(vcpu, 0);
5402                         return 1;
5403                 }
5404                 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
5405                 return kvm_skip_emulated_instruction(vcpu);
5406
5407         case INVPCID_TYPE_SINGLE_CTXT:
5408                 if (!pcid_enabled && (operand.pcid != 0)) {
5409                         kvm_inject_gp(vcpu, 0);
5410                         return 1;
5411                 }
5412
5413                 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
5414                         kvm_mmu_sync_roots(vcpu);
5415                         kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
5416                 }
5417
5418                 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5419                         if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3)
5420                             == operand.pcid)
5421                                 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
5422
5423                 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
5424                 /*
5425                  * If neither the current cr3 nor any of the prev_roots use the
5426                  * given PCID, then nothing needs to be done here because a
5427                  * resync will happen anyway before switching to any other CR3.
5428                  */
5429
5430                 return kvm_skip_emulated_instruction(vcpu);
5431
5432         case INVPCID_TYPE_ALL_NON_GLOBAL:
5433                 /*
5434                  * Currently, KVM doesn't mark global entries in the shadow
5435                  * page tables, so a non-global flush just degenerates to a
5436                  * global flush. If needed, we could optimize this later by
5437                  * keeping track of global entries in shadow page tables.
5438                  */
5439
5440                 /* fall-through */
5441         case INVPCID_TYPE_ALL_INCL_GLOBAL:
5442                 kvm_mmu_unload(vcpu);
5443                 return kvm_skip_emulated_instruction(vcpu);
5444
5445         default:
5446                 BUG(); /* We have already checked above that type <= 3 */
5447         }
5448 }
5449
5450 static int handle_pml_full(struct kvm_vcpu *vcpu)
5451 {
5452         unsigned long exit_qualification;
5453
5454         trace_kvm_pml_full(vcpu->vcpu_id);
5455
5456         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5457
5458         /*
5459          * PML buffer FULL happened while executing iret from NMI,
5460          * "blocked by NMI" bit has to be set before next VM entry.
5461          */
5462         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5463                         enable_vnmi &&
5464                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5465                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5466                                 GUEST_INTR_STATE_NMI);
5467
5468         /*
5469          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5470          * here.., and there's no userspace involvement needed for PML.
5471          */
5472         return 1;
5473 }
5474
5475 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
5476 {
5477         struct vcpu_vmx *vmx = to_vmx(vcpu);
5478
5479         if (!vmx->req_immediate_exit &&
5480             !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled))
5481                 kvm_lapic_expired_hv_timer(vcpu);
5482
5483         return 1;
5484 }
5485
5486 /*
5487  * When nested=0, all VMX instruction VM Exits filter here.  The handlers
5488  * are overwritten by nested_vmx_setup() when nested=1.
5489  */
5490 static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
5491 {
5492         kvm_queue_exception(vcpu, UD_VECTOR);
5493         return 1;
5494 }
5495
5496 static int handle_encls(struct kvm_vcpu *vcpu)
5497 {
5498         /*
5499          * SGX virtualization is not yet supported.  There is no software
5500          * enable bit for SGX, so we have to trap ENCLS and inject a #UD
5501          * to prevent the guest from executing ENCLS.
5502          */
5503         kvm_queue_exception(vcpu, UD_VECTOR);
5504         return 1;
5505 }
5506
5507 /*
5508  * The exit handlers return 1 if the exit was handled fully and guest execution
5509  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5510  * to be done to userspace and return 0.
5511  */
5512 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5513         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception_nmi,
5514         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5515         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5516         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5517         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5518         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5519         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5520         [EXIT_REASON_CPUID]                   = kvm_emulate_cpuid,
5521         [EXIT_REASON_MSR_READ]                = kvm_emulate_rdmsr,
5522         [EXIT_REASON_MSR_WRITE]               = kvm_emulate_wrmsr,
5523         [EXIT_REASON_INTERRUPT_WINDOW]        = handle_interrupt_window,
5524         [EXIT_REASON_HLT]                     = kvm_emulate_halt,
5525         [EXIT_REASON_INVD]                    = handle_invd,
5526         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5527         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
5528         [EXIT_REASON_VMCALL]                  = handle_vmcall,
5529         [EXIT_REASON_VMCLEAR]                 = handle_vmx_instruction,
5530         [EXIT_REASON_VMLAUNCH]                = handle_vmx_instruction,
5531         [EXIT_REASON_VMPTRLD]                 = handle_vmx_instruction,
5532         [EXIT_REASON_VMPTRST]                 = handle_vmx_instruction,
5533         [EXIT_REASON_VMREAD]                  = handle_vmx_instruction,
5534         [EXIT_REASON_VMRESUME]                = handle_vmx_instruction,
5535         [EXIT_REASON_VMWRITE]                 = handle_vmx_instruction,
5536         [EXIT_REASON_VMOFF]                   = handle_vmx_instruction,
5537         [EXIT_REASON_VMON]                    = handle_vmx_instruction,
5538         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5539         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5540         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
5541         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
5542         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
5543         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
5544         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5545         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5546         [EXIT_REASON_GDTR_IDTR]               = handle_desc,
5547         [EXIT_REASON_LDTR_TR]                 = handle_desc,
5548         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5549         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5550         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5551         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
5552         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
5553         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
5554         [EXIT_REASON_INVEPT]                  = handle_vmx_instruction,
5555         [EXIT_REASON_INVVPID]                 = handle_vmx_instruction,
5556         [EXIT_REASON_RDRAND]                  = handle_invalid_op,
5557         [EXIT_REASON_RDSEED]                  = handle_invalid_op,
5558         [EXIT_REASON_PML_FULL]                = handle_pml_full,
5559         [EXIT_REASON_INVPCID]                 = handle_invpcid,
5560         [EXIT_REASON_VMFUNC]                  = handle_vmx_instruction,
5561         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
5562         [EXIT_REASON_ENCLS]                   = handle_encls,
5563 };
5564
5565 static const int kvm_vmx_max_exit_handlers =
5566         ARRAY_SIZE(kvm_vmx_exit_handlers);
5567
5568 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5569 {
5570         *info1 = vmcs_readl(EXIT_QUALIFICATION);
5571         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5572 }
5573
5574 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
5575 {
5576         if (vmx->pml_pg) {
5577                 __free_page(vmx->pml_pg);
5578                 vmx->pml_pg = NULL;
5579         }
5580 }
5581
5582 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
5583 {
5584         struct vcpu_vmx *vmx = to_vmx(vcpu);
5585         u64 *pml_buf;
5586         u16 pml_idx;
5587
5588         pml_idx = vmcs_read16(GUEST_PML_INDEX);
5589
5590         /* Do nothing if PML buffer is empty */
5591         if (pml_idx == (PML_ENTITY_NUM - 1))
5592                 return;
5593
5594         /* PML index always points to next available PML buffer entity */
5595         if (pml_idx >= PML_ENTITY_NUM)
5596                 pml_idx = 0;
5597         else
5598                 pml_idx++;
5599
5600         pml_buf = page_address(vmx->pml_pg);
5601         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5602                 u64 gpa;
5603
5604                 gpa = pml_buf[pml_idx];
5605                 WARN_ON(gpa & (PAGE_SIZE - 1));
5606                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5607         }
5608
5609         /* reset PML index */
5610         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5611 }
5612
5613 /*
5614  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
5615  * Called before reporting dirty_bitmap to userspace.
5616  */
5617 static void kvm_flush_pml_buffers(struct kvm *kvm)
5618 {
5619         int i;
5620         struct kvm_vcpu *vcpu;
5621         /*
5622          * We only need to kick vcpu out of guest mode here, as PML buffer
5623          * is flushed at beginning of all VMEXITs, and it's obvious that only
5624          * vcpus running in guest are possible to have unflushed GPAs in PML
5625          * buffer.
5626          */
5627         kvm_for_each_vcpu(i, vcpu, kvm)
5628                 kvm_vcpu_kick(vcpu);
5629 }
5630
5631 static void vmx_dump_sel(char *name, uint32_t sel)
5632 {
5633         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5634                name, vmcs_read16(sel),
5635                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5636                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5637                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
5638 }
5639
5640 static void vmx_dump_dtsel(char *name, uint32_t limit)
5641 {
5642         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
5643                name, vmcs_read32(limit),
5644                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
5645 }
5646
5647 void dump_vmcs(void)
5648 {
5649         u32 vmentry_ctl, vmexit_ctl;
5650         u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5651         unsigned long cr4;
5652         u64 efer;
5653         int i, n;
5654
5655         if (!dump_invalid_vmcs) {
5656                 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5657                 return;
5658         }
5659
5660         vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5661         vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5662         cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5663         pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5664         cr4 = vmcs_readl(GUEST_CR4);
5665         efer = vmcs_read64(GUEST_IA32_EFER);
5666         secondary_exec_control = 0;
5667         if (cpu_has_secondary_exec_ctrls())
5668                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5669
5670         pr_err("*** Guest State ***\n");
5671         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5672                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5673                vmcs_readl(CR0_GUEST_HOST_MASK));
5674         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5675                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5676         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5677         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
5678             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
5679         {
5680                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
5681                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5682                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
5683                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
5684         }
5685         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
5686                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5687         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
5688                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5689         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5690                vmcs_readl(GUEST_SYSENTER_ESP),
5691                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5692         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
5693         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
5694         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
5695         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
5696         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
5697         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
5698         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5699         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5700         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5701         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
5702         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
5703             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
5704                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
5705                        efer, vmcs_read64(GUEST_IA32_PAT));
5706         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
5707                vmcs_read64(GUEST_IA32_DEBUGCTL),
5708                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5709         if (cpu_has_load_perf_global_ctrl() &&
5710             vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5711                 pr_err("PerfGlobCtl = 0x%016llx\n",
5712                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5713         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5714                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5715         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
5716                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5717                vmcs_read32(GUEST_ACTIVITY_STATE));
5718         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5719                 pr_err("InterruptStatus = %04x\n",
5720                        vmcs_read16(GUEST_INTR_STATUS));
5721
5722         pr_err("*** Host State ***\n");
5723         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
5724                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5725         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5726                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5727                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5728                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5729                vmcs_read16(HOST_TR_SELECTOR));
5730         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5731                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5732                vmcs_readl(HOST_TR_BASE));
5733         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5734                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5735         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5736                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5737                vmcs_readl(HOST_CR4));
5738         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5739                vmcs_readl(HOST_IA32_SYSENTER_ESP),
5740                vmcs_read32(HOST_IA32_SYSENTER_CS),
5741                vmcs_readl(HOST_IA32_SYSENTER_EIP));
5742         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
5743                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
5744                        vmcs_read64(HOST_IA32_EFER),
5745                        vmcs_read64(HOST_IA32_PAT));
5746         if (cpu_has_load_perf_global_ctrl() &&
5747             vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5748                 pr_err("PerfGlobCtl = 0x%016llx\n",
5749                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
5750
5751         pr_err("*** Control State ***\n");
5752         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5753                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5754         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5755         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5756                vmcs_read32(EXCEPTION_BITMAP),
5757                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5758                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5759         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5760                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5761                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5762                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5763         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5764                vmcs_read32(VM_EXIT_INTR_INFO),
5765                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5766                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5767         pr_err("        reason=%08x qualification=%016lx\n",
5768                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5769         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5770                vmcs_read32(IDT_VECTORING_INFO_FIELD),
5771                vmcs_read32(IDT_VECTORING_ERROR_CODE));
5772         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5773         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5774                 pr_err("TSC Multiplier = 0x%016llx\n",
5775                        vmcs_read64(TSC_MULTIPLIER));
5776         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5777                 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5778                         u16 status = vmcs_read16(GUEST_INTR_STATUS);
5779                         pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5780                 }
5781                 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
5782                 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5783                         pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
5784                 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
5785         }
5786         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5787                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5788         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5789                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5790         n = vmcs_read32(CR3_TARGET_COUNT);
5791         for (i = 0; i + 1 < n; i += 4)
5792                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
5793                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
5794                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
5795         if (i < n)
5796                 pr_err("CR3 target%u=%016lx\n",
5797                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
5798         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5799                 pr_err("PLE Gap=%08x Window=%08x\n",
5800                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5801         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5802                 pr_err("Virtual processor ID = 0x%04x\n",
5803                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
5804 }
5805
5806 /*
5807  * The guest has exited.  See if we can fix it or if we need userspace
5808  * assistance.
5809  */
5810 static int vmx_handle_exit(struct kvm_vcpu *vcpu,
5811         enum exit_fastpath_completion exit_fastpath)
5812 {
5813         struct vcpu_vmx *vmx = to_vmx(vcpu);
5814         u32 exit_reason = vmx->exit_reason;
5815         u32 vectoring_info = vmx->idt_vectoring_info;
5816
5817         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
5818
5819         /*
5820          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5821          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5822          * querying dirty_bitmap, we only need to kick all vcpus out of guest
5823          * mode as if vcpus is in root mode, the PML buffer must has been
5824          * flushed already.
5825          */
5826         if (enable_pml)
5827                 vmx_flush_pml_buffer(vcpu);
5828
5829         /* If guest state is invalid, start emulating */
5830         if (vmx->emulation_required)
5831                 return handle_invalid_guest_state(vcpu);
5832
5833         if (is_guest_mode(vcpu)) {
5834                 /*
5835                  * The host physical addresses of some pages of guest memory
5836                  * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
5837                  * Page). The CPU may write to these pages via their host
5838                  * physical address while L2 is running, bypassing any
5839                  * address-translation-based dirty tracking (e.g. EPT write
5840                  * protection).
5841                  *
5842                  * Mark them dirty on every exit from L2 to prevent them from
5843                  * getting out of sync with dirty tracking.
5844                  */
5845                 nested_mark_vmcs12_pages_dirty(vcpu);
5846
5847                 if (nested_vmx_exit_reflected(vcpu, exit_reason))
5848                         return nested_vmx_reflect_vmexit(vcpu, exit_reason);
5849         }
5850
5851         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5852                 dump_vmcs();
5853                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5854                 vcpu->run->fail_entry.hardware_entry_failure_reason
5855                         = exit_reason;
5856                 return 0;
5857         }
5858
5859         if (unlikely(vmx->fail)) {
5860                 dump_vmcs();
5861                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5862                 vcpu->run->fail_entry.hardware_entry_failure_reason
5863                         = vmcs_read32(VM_INSTRUCTION_ERROR);
5864                 return 0;
5865         }
5866
5867         /*
5868          * Note:
5869          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5870          * delivery event since it indicates guest is accessing MMIO.
5871          * The vm-exit can be triggered again after return to guest that
5872          * will cause infinite loop.
5873          */
5874         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5875                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5876                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
5877                         exit_reason != EXIT_REASON_PML_FULL &&
5878                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
5879                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5880                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5881                 vcpu->run->internal.ndata = 3;
5882                 vcpu->run->internal.data[0] = vectoring_info;
5883                 vcpu->run->internal.data[1] = exit_reason;
5884                 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5885                 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
5886                         vcpu->run->internal.ndata++;
5887                         vcpu->run->internal.data[3] =
5888                                 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5889                 }
5890                 return 0;
5891         }
5892
5893         if (unlikely(!enable_vnmi &&
5894                      vmx->loaded_vmcs->soft_vnmi_blocked)) {
5895                 if (vmx_interrupt_allowed(vcpu)) {
5896                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5897                 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5898                            vcpu->arch.nmi_pending) {
5899                         /*
5900                          * This CPU don't support us in finding the end of an
5901                          * NMI-blocked window if the guest runs with IRQs
5902                          * disabled. So we pull the trigger after 1 s of
5903                          * futile waiting, but inform the user about this.
5904                          */
5905                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5906                                "state on VCPU %d after 1 s timeout\n",
5907                                __func__, vcpu->vcpu_id);
5908                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5909                 }
5910         }
5911
5912         if (exit_fastpath == EXIT_FASTPATH_SKIP_EMUL_INS) {
5913                 kvm_skip_emulated_instruction(vcpu);
5914                 return 1;
5915         }
5916
5917         if (exit_reason >= kvm_vmx_max_exit_handlers)
5918                 goto unexpected_vmexit;
5919 #ifdef CONFIG_RETPOLINE
5920         if (exit_reason == EXIT_REASON_MSR_WRITE)
5921                 return kvm_emulate_wrmsr(vcpu);
5922         else if (exit_reason == EXIT_REASON_PREEMPTION_TIMER)
5923                 return handle_preemption_timer(vcpu);
5924         else if (exit_reason == EXIT_REASON_INTERRUPT_WINDOW)
5925                 return handle_interrupt_window(vcpu);
5926         else if (exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
5927                 return handle_external_interrupt(vcpu);
5928         else if (exit_reason == EXIT_REASON_HLT)
5929                 return kvm_emulate_halt(vcpu);
5930         else if (exit_reason == EXIT_REASON_EPT_MISCONFIG)
5931                 return handle_ept_misconfig(vcpu);
5932 #endif
5933
5934         exit_reason = array_index_nospec(exit_reason,
5935                                          kvm_vmx_max_exit_handlers);
5936         if (!kvm_vmx_exit_handlers[exit_reason])
5937                 goto unexpected_vmexit;
5938
5939         return kvm_vmx_exit_handlers[exit_reason](vcpu);
5940
5941 unexpected_vmexit:
5942         vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n", exit_reason);
5943         dump_vmcs();
5944         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5945         vcpu->run->internal.suberror =
5946                         KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
5947         vcpu->run->internal.ndata = 1;
5948         vcpu->run->internal.data[0] = exit_reason;
5949         return 0;
5950 }
5951
5952 /*
5953  * Software based L1D cache flush which is used when microcode providing
5954  * the cache control MSR is not loaded.
5955  *
5956  * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
5957  * flush it is required to read in 64 KiB because the replacement algorithm
5958  * is not exactly LRU. This could be sized at runtime via topology
5959  * information but as all relevant affected CPUs have 32KiB L1D cache size
5960  * there is no point in doing so.
5961  */
5962 static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
5963 {
5964         int size = PAGE_SIZE << L1D_CACHE_ORDER;
5965
5966         /*
5967          * This code is only executed when the the flush mode is 'cond' or
5968          * 'always'
5969          */
5970         if (static_branch_likely(&vmx_l1d_flush_cond)) {
5971                 bool flush_l1d;
5972
5973                 /*
5974                  * Clear the per-vcpu flush bit, it gets set again
5975                  * either from vcpu_run() or from one of the unsafe
5976                  * VMEXIT handlers.
5977                  */
5978                 flush_l1d = vcpu->arch.l1tf_flush_l1d;
5979                 vcpu->arch.l1tf_flush_l1d = false;
5980
5981                 /*
5982                  * Clear the per-cpu flush bit, it gets set again from
5983                  * the interrupt handlers.
5984                  */
5985                 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
5986                 kvm_clear_cpu_l1tf_flush_l1d();
5987
5988                 if (!flush_l1d)
5989                         return;
5990         }
5991
5992         vcpu->stat.l1d_flush++;
5993
5994         if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
5995                 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
5996                 return;
5997         }
5998
5999         asm volatile(
6000                 /* First ensure the pages are in the TLB */
6001                 "xorl   %%eax, %%eax\n"
6002                 ".Lpopulate_tlb:\n\t"
6003                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6004                 "addl   $4096, %%eax\n\t"
6005                 "cmpl   %%eax, %[size]\n\t"
6006                 "jne    .Lpopulate_tlb\n\t"
6007                 "xorl   %%eax, %%eax\n\t"
6008                 "cpuid\n\t"
6009                 /* Now fill the cache */
6010                 "xorl   %%eax, %%eax\n"
6011                 ".Lfill_cache:\n"
6012                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6013                 "addl   $64, %%eax\n\t"
6014                 "cmpl   %%eax, %[size]\n\t"
6015                 "jne    .Lfill_cache\n\t"
6016                 "lfence\n"
6017                 :: [flush_pages] "r" (vmx_l1d_flush_pages),
6018                     [size] "r" (size)
6019                 : "eax", "ebx", "ecx", "edx");
6020 }
6021
6022 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6023 {
6024         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6025         int tpr_threshold;
6026
6027         if (is_guest_mode(vcpu) &&
6028                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
6029                 return;
6030
6031         tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr;
6032         if (is_guest_mode(vcpu))
6033                 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold;
6034         else
6035                 vmcs_write32(TPR_THRESHOLD, tpr_threshold);
6036 }
6037
6038 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
6039 {
6040         struct vcpu_vmx *vmx = to_vmx(vcpu);
6041         u32 sec_exec_control;
6042
6043         if (!lapic_in_kernel(vcpu))
6044                 return;
6045
6046         if (!flexpriority_enabled &&
6047             !cpu_has_vmx_virtualize_x2apic_mode())
6048                 return;
6049
6050         /* Postpone execution until vmcs01 is the current VMCS. */
6051         if (is_guest_mode(vcpu)) {
6052                 vmx->nested.change_vmcs01_virtual_apic_mode = true;
6053                 return;
6054         }
6055
6056         sec_exec_control = secondary_exec_controls_get(vmx);
6057         sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6058                               SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
6059
6060         switch (kvm_get_apic_mode(vcpu)) {
6061         case LAPIC_MODE_INVALID:
6062                 WARN_ONCE(true, "Invalid local APIC state");
6063         case LAPIC_MODE_DISABLED:
6064                 break;
6065         case LAPIC_MODE_XAPIC:
6066                 if (flexpriority_enabled) {
6067                         sec_exec_control |=
6068                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6069                         vmx_flush_tlb(vcpu, true);
6070                 }
6071                 break;
6072         case LAPIC_MODE_X2APIC:
6073                 if (cpu_has_vmx_virtualize_x2apic_mode())
6074                         sec_exec_control |=
6075                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6076                 break;
6077         }
6078         secondary_exec_controls_set(vmx, sec_exec_control);
6079
6080         vmx_update_msr_bitmap(vcpu);
6081 }
6082
6083 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
6084 {
6085         if (!is_guest_mode(vcpu)) {
6086                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
6087                 vmx_flush_tlb(vcpu, true);
6088         }
6089 }
6090
6091 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6092 {
6093         u16 status;
6094         u8 old;
6095
6096         if (max_isr == -1)
6097                 max_isr = 0;
6098
6099         status = vmcs_read16(GUEST_INTR_STATUS);
6100         old = status >> 8;
6101         if (max_isr != old) {
6102                 status &= 0xff;
6103                 status |= max_isr << 8;
6104                 vmcs_write16(GUEST_INTR_STATUS, status);
6105         }
6106 }
6107
6108 static void vmx_set_rvi(int vector)
6109 {
6110         u16 status;
6111         u8 old;
6112
6113         if (vector == -1)
6114                 vector = 0;
6115
6116         status = vmcs_read16(GUEST_INTR_STATUS);
6117         old = (u8)status & 0xff;
6118         if ((u8)vector != old) {
6119                 status &= ~0xff;
6120                 status |= (u8)vector;
6121                 vmcs_write16(GUEST_INTR_STATUS, status);
6122         }
6123 }
6124
6125 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6126 {
6127         /*
6128          * When running L2, updating RVI is only relevant when
6129          * vmcs12 virtual-interrupt-delivery enabled.
6130          * However, it can be enabled only when L1 also
6131          * intercepts external-interrupts and in that case
6132          * we should not update vmcs02 RVI but instead intercept
6133          * interrupt. Therefore, do nothing when running L2.
6134          */
6135         if (!is_guest_mode(vcpu))
6136                 vmx_set_rvi(max_irr);
6137 }
6138
6139 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6140 {
6141         struct vcpu_vmx *vmx = to_vmx(vcpu);
6142         int max_irr;
6143         bool max_irr_updated;
6144
6145         WARN_ON(!vcpu->arch.apicv_active);
6146         if (pi_test_on(&vmx->pi_desc)) {
6147                 pi_clear_on(&vmx->pi_desc);
6148                 /*
6149                  * IOMMU can write to PID.ON, so the barrier matters even on UP.
6150                  * But on x86 this is just a compiler barrier anyway.
6151                  */
6152                 smp_mb__after_atomic();
6153                 max_irr_updated =
6154                         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
6155
6156                 /*
6157                  * If we are running L2 and L1 has a new pending interrupt
6158                  * which can be injected, we should re-evaluate
6159                  * what should be done with this new L1 interrupt.
6160                  * If L1 intercepts external-interrupts, we should
6161                  * exit from L2 to L1. Otherwise, interrupt should be
6162                  * delivered directly to L2.
6163                  */
6164                 if (is_guest_mode(vcpu) && max_irr_updated) {
6165                         if (nested_exit_on_intr(vcpu))
6166                                 kvm_vcpu_exiting_guest_mode(vcpu);
6167                         else
6168                                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6169                 }
6170         } else {
6171                 max_irr = kvm_lapic_find_highest_irr(vcpu);
6172         }
6173         vmx_hwapic_irr_update(vcpu, max_irr);
6174         return max_irr;
6175 }
6176
6177 static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
6178 {
6179         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6180
6181         return pi_test_on(pi_desc) ||
6182                 (pi_test_sn(pi_desc) && !pi_is_pir_empty(pi_desc));
6183 }
6184
6185 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6186 {
6187         if (!kvm_vcpu_apicv_active(vcpu))
6188                 return;
6189
6190         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6191         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6192         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6193         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6194 }
6195
6196 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
6197 {
6198         struct vcpu_vmx *vmx = to_vmx(vcpu);
6199
6200         pi_clear_on(&vmx->pi_desc);
6201         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6202 }
6203
6204 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
6205 {
6206         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6207
6208         /* if exit due to PF check for async PF */
6209         if (is_page_fault(vmx->exit_intr_info)) {
6210                 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
6211         /* Handle machine checks before interrupts are enabled */
6212         } else if (is_machine_check(vmx->exit_intr_info)) {
6213                 kvm_machine_check();
6214         /* We need to handle NMIs before interrupts are enabled */
6215         } else if (is_nmi(vmx->exit_intr_info)) {
6216                 kvm_before_interrupt(&vmx->vcpu);
6217                 asm("int $2");
6218                 kvm_after_interrupt(&vmx->vcpu);
6219         }
6220 }
6221
6222 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
6223 {
6224         unsigned int vector;
6225         unsigned long entry;
6226 #ifdef CONFIG_X86_64
6227         unsigned long tmp;
6228 #endif
6229         gate_desc *desc;
6230         u32 intr_info;
6231
6232         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6233         if (WARN_ONCE(!is_external_intr(intr_info),
6234             "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6235                 return;
6236
6237         vector = intr_info & INTR_INFO_VECTOR_MASK;
6238         desc = (gate_desc *)host_idt_base + vector;
6239         entry = gate_offset(desc);
6240
6241         kvm_before_interrupt(vcpu);
6242
6243         asm volatile(
6244 #ifdef CONFIG_X86_64
6245                 "mov %%" _ASM_SP ", %[sp]\n\t"
6246                 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6247                 "push $%c[ss]\n\t"
6248                 "push %[sp]\n\t"
6249 #endif
6250                 "pushf\n\t"
6251                 __ASM_SIZE(push) " $%c[cs]\n\t"
6252                 CALL_NOSPEC
6253                 :
6254 #ifdef CONFIG_X86_64
6255                 [sp]"=&r"(tmp),
6256 #endif
6257                 ASM_CALL_CONSTRAINT
6258                 :
6259                 THUNK_TARGET(entry),
6260                 [ss]"i"(__KERNEL_DS),
6261                 [cs]"i"(__KERNEL_CS)
6262         );
6263
6264         kvm_after_interrupt(vcpu);
6265 }
6266 STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff);
6267
6268 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu,
6269         enum exit_fastpath_completion *exit_fastpath)
6270 {
6271         struct vcpu_vmx *vmx = to_vmx(vcpu);
6272
6273         if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
6274                 handle_external_interrupt_irqoff(vcpu);
6275         else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)
6276                 handle_exception_nmi_irqoff(vmx);
6277         else if (!is_guest_mode(vcpu) &&
6278                 vmx->exit_reason == EXIT_REASON_MSR_WRITE)
6279                 *exit_fastpath = handle_fastpath_set_msr_irqoff(vcpu);
6280 }
6281
6282 static bool vmx_has_emulated_msr(int index)
6283 {
6284         switch (index) {
6285         case MSR_IA32_SMBASE:
6286                 /*
6287                  * We cannot do SMM unless we can run the guest in big
6288                  * real mode.
6289                  */
6290                 return enable_unrestricted_guest || emulate_invalid_guest_state;
6291         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6292                 return nested;
6293         case MSR_AMD64_VIRT_SPEC_CTRL:
6294                 /* This is AMD only.  */
6295                 return false;
6296         default:
6297                 return true;
6298         }
6299 }
6300
6301 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6302 {
6303         u32 exit_intr_info;
6304         bool unblock_nmi;
6305         u8 vector;
6306         bool idtv_info_valid;
6307
6308         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6309
6310         if (enable_vnmi) {
6311                 if (vmx->loaded_vmcs->nmi_known_unmasked)
6312                         return;
6313                 /*
6314                  * Can't use vmx->exit_intr_info since we're not sure what
6315                  * the exit reason is.
6316                  */
6317                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6318                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6319                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6320                 /*
6321                  * SDM 3: 27.7.1.2 (September 2008)
6322                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6323                  * a guest IRET fault.
6324                  * SDM 3: 23.2.2 (September 2008)
6325                  * Bit 12 is undefined in any of the following cases:
6326                  *  If the VM exit sets the valid bit in the IDT-vectoring
6327                  *   information field.
6328                  *  If the VM exit is due to a double fault.
6329                  */
6330                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6331                     vector != DF_VECTOR && !idtv_info_valid)
6332                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6333                                       GUEST_INTR_STATE_NMI);
6334                 else
6335                         vmx->loaded_vmcs->nmi_known_unmasked =
6336                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6337                                   & GUEST_INTR_STATE_NMI);
6338         } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6339                 vmx->loaded_vmcs->vnmi_blocked_time +=
6340                         ktime_to_ns(ktime_sub(ktime_get(),
6341                                               vmx->loaded_vmcs->entry_time));
6342 }
6343
6344 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6345                                       u32 idt_vectoring_info,
6346                                       int instr_len_field,
6347                                       int error_code_field)
6348 {
6349         u8 vector;
6350         int type;
6351         bool idtv_info_valid;
6352
6353         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6354
6355         vcpu->arch.nmi_injected = false;
6356         kvm_clear_exception_queue(vcpu);
6357         kvm_clear_interrupt_queue(vcpu);
6358
6359         if (!idtv_info_valid)
6360                 return;
6361
6362         kvm_make_request(KVM_REQ_EVENT, vcpu);
6363
6364         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6365         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6366
6367         switch (type) {
6368         case INTR_TYPE_NMI_INTR:
6369                 vcpu->arch.nmi_injected = true;
6370                 /*
6371                  * SDM 3: 27.7.1.2 (September 2008)
6372                  * Clear bit "block by NMI" before VM entry if a NMI
6373                  * delivery faulted.
6374                  */
6375                 vmx_set_nmi_mask(vcpu, false);
6376                 break;
6377         case INTR_TYPE_SOFT_EXCEPTION:
6378                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6379                 /* fall through */
6380         case INTR_TYPE_HARD_EXCEPTION:
6381                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6382                         u32 err = vmcs_read32(error_code_field);
6383                         kvm_requeue_exception_e(vcpu, vector, err);
6384                 } else
6385                         kvm_requeue_exception(vcpu, vector);
6386                 break;
6387         case INTR_TYPE_SOFT_INTR:
6388                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6389                 /* fall through */
6390         case INTR_TYPE_EXT_INTR:
6391                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6392                 break;
6393         default:
6394                 break;
6395         }
6396 }
6397
6398 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6399 {
6400         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6401                                   VM_EXIT_INSTRUCTION_LEN,
6402                                   IDT_VECTORING_ERROR_CODE);
6403 }
6404
6405 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6406 {
6407         __vmx_complete_interrupts(vcpu,
6408                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6409                                   VM_ENTRY_INSTRUCTION_LEN,
6410                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6411
6412         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6413 }
6414
6415 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6416 {
6417         int i, nr_msrs;
6418         struct perf_guest_switch_msr *msrs;
6419
6420         msrs = perf_guest_get_msrs(&nr_msrs);
6421
6422         if (!msrs)
6423                 return;
6424
6425         for (i = 0; i < nr_msrs; i++)
6426                 if (msrs[i].host == msrs[i].guest)
6427                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6428                 else
6429                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6430                                         msrs[i].host, false);
6431 }
6432
6433 static void atomic_switch_umwait_control_msr(struct vcpu_vmx *vmx)
6434 {
6435         u32 host_umwait_control;
6436
6437         if (!vmx_has_waitpkg(vmx))
6438                 return;
6439
6440         host_umwait_control = get_umwait_control_msr();
6441
6442         if (vmx->msr_ia32_umwait_control != host_umwait_control)
6443                 add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL,
6444                         vmx->msr_ia32_umwait_control,
6445                         host_umwait_control, false);
6446         else
6447                 clear_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL);
6448 }
6449
6450 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
6451 {
6452         struct vcpu_vmx *vmx = to_vmx(vcpu);
6453         u64 tscl;
6454         u32 delta_tsc;
6455
6456         if (vmx->req_immediate_exit) {
6457                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6458                 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6459         } else if (vmx->hv_deadline_tsc != -1) {
6460                 tscl = rdtsc();
6461                 if (vmx->hv_deadline_tsc > tscl)
6462                         /* set_hv_timer ensures the delta fits in 32-bits */
6463                         delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6464                                 cpu_preemption_timer_multi);
6465                 else
6466                         delta_tsc = 0;
6467
6468                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6469                 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6470         } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6471                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6472                 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
6473         }
6474 }
6475
6476 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
6477 {
6478         if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6479                 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6480                 vmcs_writel(HOST_RSP, host_rsp);
6481         }
6482 }
6483
6484 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched);
6485
6486 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6487 {
6488         struct vcpu_vmx *vmx = to_vmx(vcpu);
6489         unsigned long cr3, cr4;
6490
6491         /* Record the guest's net vcpu time for enforced NMI injections. */
6492         if (unlikely(!enable_vnmi &&
6493                      vmx->loaded_vmcs->soft_vnmi_blocked))
6494                 vmx->loaded_vmcs->entry_time = ktime_get();
6495
6496         /* Don't enter VMX if guest state is invalid, let the exit handler
6497            start emulation until we arrive back to a valid state */
6498         if (vmx->emulation_required)
6499                 return;
6500
6501         if (vmx->ple_window_dirty) {
6502                 vmx->ple_window_dirty = false;
6503                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6504         }
6505
6506         /*
6507          * We did this in prepare_switch_to_guest, because it needs to
6508          * be within srcu_read_lock.
6509          */
6510         WARN_ON_ONCE(vmx->nested.need_vmcs12_to_shadow_sync);
6511
6512         if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP))
6513                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6514         if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP))
6515                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6516
6517         cr3 = __get_current_cr3_fast();
6518         if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6519                 vmcs_writel(HOST_CR3, cr3);
6520                 vmx->loaded_vmcs->host_state.cr3 = cr3;
6521         }
6522
6523         cr4 = cr4_read_shadow();
6524         if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6525                 vmcs_writel(HOST_CR4, cr4);
6526                 vmx->loaded_vmcs->host_state.cr4 = cr4;
6527         }
6528
6529         /* When single-stepping over STI and MOV SS, we must clear the
6530          * corresponding interruptibility bits in the guest state. Otherwise
6531          * vmentry fails as it then expects bit 14 (BS) in pending debug
6532          * exceptions being set, but that's not correct for the guest debugging
6533          * case. */
6534         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6535                 vmx_set_interrupt_shadow(vcpu, 0);
6536
6537         kvm_load_guest_xsave_state(vcpu);
6538
6539         if (static_cpu_has(X86_FEATURE_PKU) &&
6540             kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
6541             vcpu->arch.pkru != vmx->host_pkru)
6542                 __write_pkru(vcpu->arch.pkru);
6543
6544         pt_guest_enter(vmx);
6545
6546         if (vcpu_to_pmu(vcpu)->version)
6547                 atomic_switch_perf_msrs(vmx);
6548         atomic_switch_umwait_control_msr(vmx);
6549
6550         if (enable_preemption_timer)
6551                 vmx_update_hv_timer(vcpu);
6552
6553         if (lapic_in_kernel(vcpu) &&
6554                 vcpu->arch.apic->lapic_timer.timer_advance_ns)
6555                 kvm_wait_lapic_expire(vcpu);
6556
6557         /*
6558          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6559          * it's non-zero. Since vmentry is serialising on affected CPUs, there
6560          * is no need to worry about the conditional branch over the wrmsr
6561          * being speculatively taken.
6562          */
6563         x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6564
6565         /* L1D Flush includes CPU buffer clear to mitigate MDS */
6566         if (static_branch_unlikely(&vmx_l1d_should_flush))
6567                 vmx_l1d_flush(vcpu);
6568         else if (static_branch_unlikely(&mds_user_clear))
6569                 mds_clear_cpu_buffers();
6570
6571         if (vcpu->arch.cr2 != read_cr2())
6572                 write_cr2(vcpu->arch.cr2);
6573
6574         vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6575                                    vmx->loaded_vmcs->launched);
6576
6577         vcpu->arch.cr2 = read_cr2();
6578
6579         /*
6580          * We do not use IBRS in the kernel. If this vCPU has used the
6581          * SPEC_CTRL MSR it may have left it on; save the value and
6582          * turn it off. This is much more efficient than blindly adding
6583          * it to the atomic save/restore list. Especially as the former
6584          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6585          *
6586          * For non-nested case:
6587          * If the L01 MSR bitmap does not intercept the MSR, then we need to
6588          * save it.
6589          *
6590          * For nested case:
6591          * If the L02 MSR bitmap does not intercept the MSR, then we need to
6592          * save it.
6593          */
6594         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6595                 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
6596
6597         x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
6598
6599         /* All fields are clean at this point */
6600         if (static_branch_unlikely(&enable_evmcs))
6601                 current_evmcs->hv_clean_fields |=
6602                         HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
6603
6604         if (static_branch_unlikely(&enable_evmcs))
6605                 current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index;
6606
6607         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6608         if (vmx->host_debugctlmsr)
6609                 update_debugctlmsr(vmx->host_debugctlmsr);
6610
6611 #ifndef CONFIG_X86_64
6612         /*
6613          * The sysexit path does not restore ds/es, so we must set them to
6614          * a reasonable value ourselves.
6615          *
6616          * We can't defer this to vmx_prepare_switch_to_host() since that
6617          * function may be executed in interrupt context, which saves and
6618          * restore segments around it, nullifying its effect.
6619          */
6620         loadsegment(ds, __USER_DS);
6621         loadsegment(es, __USER_DS);
6622 #endif
6623
6624         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6625                                   | (1 << VCPU_EXREG_RFLAGS)
6626                                   | (1 << VCPU_EXREG_PDPTR)
6627                                   | (1 << VCPU_EXREG_SEGMENTS)
6628                                   | (1 << VCPU_EXREG_CR3));
6629         vcpu->arch.regs_dirty = 0;
6630
6631         pt_guest_exit(vmx);
6632
6633         /*
6634          * eager fpu is enabled if PKEY is supported and CR4 is switched
6635          * back on host, so it is safe to read guest PKRU from current
6636          * XSAVE.
6637          */
6638         if (static_cpu_has(X86_FEATURE_PKU) &&
6639             kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
6640                 vcpu->arch.pkru = rdpkru();
6641                 if (vcpu->arch.pkru != vmx->host_pkru)
6642                         __write_pkru(vmx->host_pkru);
6643         }
6644
6645         kvm_load_host_xsave_state(vcpu);
6646
6647         vmx->nested.nested_run_pending = 0;
6648         vmx->idt_vectoring_info = 0;
6649
6650         vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
6651         if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
6652                 kvm_machine_check();
6653
6654         if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6655                 return;
6656
6657         vmx->loaded_vmcs->launched = 1;
6658         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6659
6660         vmx_recover_nmi_blocking(vmx);
6661         vmx_complete_interrupts(vmx);
6662 }
6663
6664 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6665 {
6666         struct vcpu_vmx *vmx = to_vmx(vcpu);
6667
6668         if (enable_pml)
6669                 vmx_destroy_pml_buffer(vmx);
6670         free_vpid(vmx->vpid);
6671         nested_vmx_free_vcpu(vcpu);
6672         free_loaded_vmcs(vmx->loaded_vmcs);
6673 }
6674
6675 static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
6676 {
6677         struct vcpu_vmx *vmx;
6678         unsigned long *msr_bitmap;
6679         int i, cpu, err;
6680
6681         BUILD_BUG_ON(offsetof(struct vcpu_vmx, vcpu) != 0);
6682         vmx = to_vmx(vcpu);
6683
6684         err = -ENOMEM;
6685
6686         vmx->vpid = allocate_vpid();
6687
6688         /*
6689          * If PML is turned on, failure on enabling PML just results in failure
6690          * of creating the vcpu, therefore we can simplify PML logic (by
6691          * avoiding dealing with cases, such as enabling PML partially on vcpus
6692          * for the guest), etc.
6693          */
6694         if (enable_pml) {
6695                 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
6696                 if (!vmx->pml_pg)
6697                         goto free_vpid;
6698         }
6699
6700         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) != NR_SHARED_MSRS);
6701
6702         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6703                 u32 index = vmx_msr_index[i];
6704                 u32 data_low, data_high;
6705                 int j = vmx->nmsrs;
6706
6707                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
6708                         continue;
6709                 if (wrmsr_safe(index, data_low, data_high) < 0)
6710                         continue;
6711
6712                 vmx->guest_msrs[j].index = i;
6713                 vmx->guest_msrs[j].data = 0;
6714                 switch (index) {
6715                 case MSR_IA32_TSX_CTRL:
6716                         /*
6717                          * No need to pass TSX_CTRL_CPUID_CLEAR through, so
6718                          * let's avoid changing CPUID bits under the host
6719                          * kernel's feet.
6720                          */
6721                         vmx->guest_msrs[j].mask = ~(u64)TSX_CTRL_CPUID_CLEAR;
6722                         break;
6723                 default:
6724                         vmx->guest_msrs[j].mask = -1ull;
6725                         break;
6726                 }
6727                 ++vmx->nmsrs;
6728         }
6729
6730         err = alloc_loaded_vmcs(&vmx->vmcs01);
6731         if (err < 0)
6732                 goto free_pml;
6733
6734         msr_bitmap = vmx->vmcs01.msr_bitmap;
6735         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
6736         vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
6737         vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
6738         vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6739         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6740         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6741         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
6742         if (kvm_cstate_in_guest(vcpu->kvm)) {
6743                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R);
6744                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6745                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6746                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6747         }
6748         vmx->msr_bitmap_mode = 0;
6749
6750         vmx->loaded_vmcs = &vmx->vmcs01;
6751         cpu = get_cpu();
6752         vmx_vcpu_load(vcpu, cpu);
6753         vcpu->cpu = cpu;
6754         init_vmcs(vmx);
6755         vmx_vcpu_put(vcpu);
6756         put_cpu();
6757         if (cpu_need_virtualize_apic_accesses(vcpu)) {
6758                 err = alloc_apic_access_page(vcpu->kvm);
6759                 if (err)
6760                         goto free_vmcs;
6761         }
6762
6763         if (enable_ept && !enable_unrestricted_guest) {
6764                 err = init_rmode_identity_map(vcpu->kvm);
6765                 if (err)
6766                         goto free_vmcs;
6767         }
6768
6769         if (nested)
6770                 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
6771                                            vmx_capability.ept);
6772         else
6773                 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
6774
6775         vmx->nested.posted_intr_nv = -1;
6776         vmx->nested.current_vmptr = -1ull;
6777
6778         vcpu->arch.microcode_version = 0x100000000ULL;
6779         vmx->msr_ia32_feature_control_valid_bits = FEAT_CTL_LOCKED;
6780
6781         /*
6782          * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
6783          * or POSTED_INTR_WAKEUP_VECTOR.
6784          */
6785         vmx->pi_desc.nv = POSTED_INTR_VECTOR;
6786         vmx->pi_desc.sn = 1;
6787
6788         vmx->ept_pointer = INVALID_PAGE;
6789
6790         return 0;
6791
6792 free_vmcs:
6793         free_loaded_vmcs(vmx->loaded_vmcs);
6794 free_pml:
6795         vmx_destroy_pml_buffer(vmx);
6796 free_vpid:
6797         free_vpid(vmx->vpid);
6798         return err;
6799 }
6800
6801 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6802 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6803
6804 static int vmx_vm_init(struct kvm *kvm)
6805 {
6806         spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
6807
6808         if (!ple_gap)
6809                 kvm->arch.pause_in_guest = true;
6810
6811         if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6812                 switch (l1tf_mitigation) {
6813                 case L1TF_MITIGATION_OFF:
6814                 case L1TF_MITIGATION_FLUSH_NOWARN:
6815                         /* 'I explicitly don't care' is set */
6816                         break;
6817                 case L1TF_MITIGATION_FLUSH:
6818                 case L1TF_MITIGATION_FLUSH_NOSMT:
6819                 case L1TF_MITIGATION_FULL:
6820                         /*
6821                          * Warn upon starting the first VM in a potentially
6822                          * insecure environment.
6823                          */
6824                         if (sched_smt_active())
6825                                 pr_warn_once(L1TF_MSG_SMT);
6826                         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6827                                 pr_warn_once(L1TF_MSG_L1D);
6828                         break;
6829                 case L1TF_MITIGATION_FULL_FORCE:
6830                         /* Flush is enforced */
6831                         break;
6832                 }
6833         }
6834         kvm_apicv_init(kvm, enable_apicv);
6835         return 0;
6836 }
6837
6838 static int __init vmx_check_processor_compat(void)
6839 {
6840         struct vmcs_config vmcs_conf;
6841         struct vmx_capability vmx_cap;
6842
6843         if (!this_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
6844             !this_cpu_has(X86_FEATURE_VMX)) {
6845                 pr_err("kvm: VMX is disabled on CPU %d\n", smp_processor_id());
6846                 return -EIO;
6847         }
6848
6849         if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
6850                 return -EIO;
6851         if (nested)
6852                 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept);
6853         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6854                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6855                                 smp_processor_id());
6856                 return -EIO;
6857         }
6858         return 0;
6859 }
6860
6861 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6862 {
6863         u8 cache;
6864         u64 ipat = 0;
6865
6866         /* We wanted to honor guest CD/MTRR/PAT, but doing so could result in
6867          * memory aliases with conflicting memory types and sometimes MCEs.
6868          * We have to be careful as to what are honored and when.
6869          *
6870          * For MMIO, guest CD/MTRR are ignored.  The EPT memory type is set to
6871          * UC.  The effective memory type is UC or WC depending on guest PAT.
6872          * This was historically the source of MCEs and we want to be
6873          * conservative.
6874          *
6875          * When there is no need to deal with noncoherent DMA (e.g., no VT-d
6876          * or VT-d has snoop control), guest CD/MTRR/PAT are all ignored.  The
6877          * EPT memory type is set to WB.  The effective memory type is forced
6878          * WB.
6879          *
6880          * Otherwise, we trust guest.  Guest CD/MTRR/PAT are all honored.  The
6881          * EPT memory type is used to emulate guest CD/MTRR.
6882          */
6883
6884         if (is_mmio) {
6885                 cache = MTRR_TYPE_UNCACHABLE;
6886                 goto exit;
6887         }
6888
6889         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
6890                 ipat = VMX_EPT_IPAT_BIT;
6891                 cache = MTRR_TYPE_WRBACK;
6892                 goto exit;
6893         }
6894
6895         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
6896                 ipat = VMX_EPT_IPAT_BIT;
6897                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
6898                         cache = MTRR_TYPE_WRBACK;
6899                 else
6900                         cache = MTRR_TYPE_UNCACHABLE;
6901                 goto exit;
6902         }
6903
6904         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
6905
6906 exit:
6907         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
6908 }
6909
6910 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx)
6911 {
6912         /*
6913          * These bits in the secondary execution controls field
6914          * are dynamic, the others are mostly based on the hypervisor
6915          * architecture and the guest's CPUID.  Do not touch the
6916          * dynamic bits.
6917          */
6918         u32 mask =
6919                 SECONDARY_EXEC_SHADOW_VMCS |
6920                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
6921                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6922                 SECONDARY_EXEC_DESC;
6923
6924         u32 new_ctl = vmx->secondary_exec_control;
6925         u32 cur_ctl = secondary_exec_controls_get(vmx);
6926
6927         secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
6928 }
6929
6930 /*
6931  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
6932  * (indicating "allowed-1") if they are supported in the guest's CPUID.
6933  */
6934 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
6935 {
6936         struct vcpu_vmx *vmx = to_vmx(vcpu);
6937         struct kvm_cpuid_entry2 *entry;
6938
6939         vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
6940         vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
6941
6942 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
6943         if (entry && (entry->_reg & (_cpuid_mask)))                     \
6944                 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask);     \
6945 } while (0)
6946
6947         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
6948         cr4_fixed1_update(X86_CR4_VME,        edx, feature_bit(VME));
6949         cr4_fixed1_update(X86_CR4_PVI,        edx, feature_bit(VME));
6950         cr4_fixed1_update(X86_CR4_TSD,        edx, feature_bit(TSC));
6951         cr4_fixed1_update(X86_CR4_DE,         edx, feature_bit(DE));
6952         cr4_fixed1_update(X86_CR4_PSE,        edx, feature_bit(PSE));
6953         cr4_fixed1_update(X86_CR4_PAE,        edx, feature_bit(PAE));
6954         cr4_fixed1_update(X86_CR4_MCE,        edx, feature_bit(MCE));
6955         cr4_fixed1_update(X86_CR4_PGE,        edx, feature_bit(PGE));
6956         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, feature_bit(FXSR));
6957         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, feature_bit(XMM));
6958         cr4_fixed1_update(X86_CR4_VMXE,       ecx, feature_bit(VMX));
6959         cr4_fixed1_update(X86_CR4_SMXE,       ecx, feature_bit(SMX));
6960         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, feature_bit(PCID));
6961         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, feature_bit(XSAVE));
6962
6963         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6964         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, feature_bit(FSGSBASE));
6965         cr4_fixed1_update(X86_CR4_SMEP,       ebx, feature_bit(SMEP));
6966         cr4_fixed1_update(X86_CR4_SMAP,       ebx, feature_bit(SMAP));
6967         cr4_fixed1_update(X86_CR4_PKE,        ecx, feature_bit(PKU));
6968         cr4_fixed1_update(X86_CR4_UMIP,       ecx, feature_bit(UMIP));
6969         cr4_fixed1_update(X86_CR4_LA57,       ecx, feature_bit(LA57));
6970
6971 #undef cr4_fixed1_update
6972 }
6973
6974 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
6975 {
6976         struct vcpu_vmx *vmx = to_vmx(vcpu);
6977
6978         if (kvm_mpx_supported()) {
6979                 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
6980
6981                 if (mpx_enabled) {
6982                         vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
6983                         vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
6984                 } else {
6985                         vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
6986                         vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
6987                 }
6988         }
6989 }
6990
6991 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
6992 {
6993         struct vcpu_vmx *vmx = to_vmx(vcpu);
6994         struct kvm_cpuid_entry2 *best = NULL;
6995         int i;
6996
6997         for (i = 0; i < PT_CPUID_LEAVES; i++) {
6998                 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
6999                 if (!best)
7000                         return;
7001                 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
7002                 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
7003                 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
7004                 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
7005         }
7006
7007         /* Get the number of configurable Address Ranges for filtering */
7008         vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
7009                                                 PT_CAP_num_address_ranges);
7010
7011         /* Initialize and clear the no dependency bits */
7012         vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
7013                         RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
7014
7015         /*
7016          * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
7017          * will inject an #GP
7018          */
7019         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
7020                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
7021
7022         /*
7023          * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
7024          * PSBFreq can be set
7025          */
7026         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
7027                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
7028                                 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
7029
7030         /*
7031          * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
7032          * MTCFreq can be set
7033          */
7034         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
7035                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
7036                                 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
7037
7038         /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
7039         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
7040                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
7041                                                         RTIT_CTL_PTW_EN);
7042
7043         /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7044         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
7045                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
7046
7047         /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7048         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
7049                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
7050
7051         /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */
7052         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
7053                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
7054
7055         /* unmask address range configure area */
7056         for (i = 0; i < vmx->pt_desc.addr_range; i++)
7057                 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
7058 }
7059
7060 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7061 {
7062         struct vcpu_vmx *vmx = to_vmx(vcpu);
7063
7064         /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */
7065         vcpu->arch.xsaves_enabled = false;
7066
7067         if (cpu_has_secondary_exec_ctrls()) {
7068                 vmx_compute_secondary_exec_control(vmx);
7069                 vmcs_set_secondary_exec_control(vmx);
7070         }
7071
7072         if (nested_vmx_allowed(vcpu))
7073                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7074                         FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7075                         FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX;
7076         else
7077                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7078                         ~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7079                           FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX);
7080
7081         if (nested_vmx_allowed(vcpu)) {
7082                 nested_vmx_cr_fixed1_bits_update(vcpu);
7083                 nested_vmx_entry_exit_ctls_update(vcpu);
7084         }
7085
7086         if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7087                         guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7088                 update_intel_pt_cfg(vcpu);
7089
7090         if (boot_cpu_has(X86_FEATURE_RTM)) {
7091                 struct shared_msr_entry *msr;
7092                 msr = find_msr_entry(vmx, MSR_IA32_TSX_CTRL);
7093                 if (msr) {
7094                         bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM);
7095                         vmx_set_guest_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE);
7096                 }
7097         }
7098 }
7099
7100 static __init void vmx_set_cpu_caps(void)
7101 {
7102         kvm_set_cpu_caps();
7103
7104         /* CPUID 0x1 */
7105         if (nested)
7106                 kvm_cpu_cap_set(X86_FEATURE_VMX);
7107
7108         /* CPUID 0x7 */
7109         if (kvm_mpx_supported())
7110                 kvm_cpu_cap_check_and_set(X86_FEATURE_MPX);
7111         if (cpu_has_vmx_invpcid())
7112                 kvm_cpu_cap_check_and_set(X86_FEATURE_INVPCID);
7113         if (vmx_pt_mode_is_host_guest())
7114                 kvm_cpu_cap_check_and_set(X86_FEATURE_INTEL_PT);
7115
7116         /* PKU is not yet implemented for shadow paging. */
7117         if (enable_ept && boot_cpu_has(X86_FEATURE_OSPKE))
7118                 kvm_cpu_cap_check_and_set(X86_FEATURE_PKU);
7119
7120         if (vmx_umip_emulated())
7121                 kvm_cpu_cap_set(X86_FEATURE_UMIP);
7122
7123         /* CPUID 0xD.1 */
7124         supported_xss = 0;
7125         if (!vmx_xsaves_supported())
7126                 kvm_cpu_cap_clear(X86_FEATURE_XSAVES);
7127
7128         /* CPUID 0x80000001 */
7129         if (!cpu_has_vmx_rdtscp())
7130                 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP);
7131 }
7132
7133 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
7134 {
7135         to_vmx(vcpu)->req_immediate_exit = true;
7136 }
7137
7138 static int vmx_check_intercept_io(struct kvm_vcpu *vcpu,
7139                                   struct x86_instruction_info *info)
7140 {
7141         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7142         unsigned short port;
7143         bool intercept;
7144         int size;
7145
7146         if (info->intercept == x86_intercept_in ||
7147             info->intercept == x86_intercept_ins) {
7148                 port = info->src_val;
7149                 size = info->dst_bytes;
7150         } else {
7151                 port = info->dst_val;
7152                 size = info->src_bytes;
7153         }
7154
7155         /*
7156          * If the 'use IO bitmaps' VM-execution control is 0, IO instruction
7157          * VM-exits depend on the 'unconditional IO exiting' VM-execution
7158          * control.
7159          *
7160          * Otherwise, IO instruction VM-exits are controlled by the IO bitmaps.
7161          */
7162         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7163                 intercept = nested_cpu_has(vmcs12,
7164                                            CPU_BASED_UNCOND_IO_EXITING);
7165         else
7166                 intercept = nested_vmx_check_io_bitmaps(vcpu, port, size);
7167
7168         /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED.  */
7169         return intercept ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE;
7170 }
7171
7172 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7173                                struct x86_instruction_info *info,
7174                                enum x86_intercept_stage stage,
7175                                struct x86_exception *exception)
7176 {
7177         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7178
7179         switch (info->intercept) {
7180         /*
7181          * RDPID causes #UD if disabled through secondary execution controls.
7182          * Because it is marked as EmulateOnUD, we need to intercept it here.
7183          */
7184         case x86_intercept_rdtscp:
7185                 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
7186                         exception->vector = UD_VECTOR;
7187                         exception->error_code_valid = false;
7188                         return X86EMUL_PROPAGATE_FAULT;
7189                 }
7190                 break;
7191
7192         case x86_intercept_in:
7193         case x86_intercept_ins:
7194         case x86_intercept_out:
7195         case x86_intercept_outs:
7196                 return vmx_check_intercept_io(vcpu, info);
7197
7198         case x86_intercept_lgdt:
7199         case x86_intercept_lidt:
7200         case x86_intercept_lldt:
7201         case x86_intercept_ltr:
7202         case x86_intercept_sgdt:
7203         case x86_intercept_sidt:
7204         case x86_intercept_sldt:
7205         case x86_intercept_str:
7206                 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC))
7207                         return X86EMUL_CONTINUE;
7208
7209                 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED.  */
7210                 break;
7211
7212         /* TODO: check more intercepts... */
7213         default:
7214                 break;
7215         }
7216
7217         return X86EMUL_UNHANDLEABLE;
7218 }
7219
7220 #ifdef CONFIG_X86_64
7221 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7222 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7223                                   u64 divisor, u64 *result)
7224 {
7225         u64 low = a << shift, high = a >> (64 - shift);
7226
7227         /* To avoid the overflow on divq */
7228         if (high >= divisor)
7229                 return 1;
7230
7231         /* Low hold the result, high hold rem which is discarded */
7232         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7233             "rm" (divisor), "0" (low), "1" (high));
7234         *result = low;
7235
7236         return 0;
7237 }
7238
7239 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7240                             bool *expired)
7241 {
7242         struct vcpu_vmx *vmx;
7243         u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
7244         struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
7245
7246         if (kvm_mwait_in_guest(vcpu->kvm) ||
7247                 kvm_can_post_timer_interrupt(vcpu))
7248                 return -EOPNOTSUPP;
7249
7250         vmx = to_vmx(vcpu);
7251         tscl = rdtsc();
7252         guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7253         delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
7254         lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7255                                                     ktimer->timer_advance_ns);
7256
7257         if (delta_tsc > lapic_timer_advance_cycles)
7258                 delta_tsc -= lapic_timer_advance_cycles;
7259         else
7260                 delta_tsc = 0;
7261
7262         /* Convert to host delta tsc if tsc scaling is enabled */
7263         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
7264             delta_tsc && u64_shl_div_u64(delta_tsc,
7265                                 kvm_tsc_scaling_ratio_frac_bits,
7266                                 vcpu->arch.tsc_scaling_ratio, &delta_tsc))
7267                 return -ERANGE;
7268
7269         /*
7270          * If the delta tsc can't fit in the 32 bit after the multi shift,
7271          * we can't use the preemption timer.
7272          * It's possible that it fits on later vmentries, but checking
7273          * on every vmentry is costly so we just use an hrtimer.
7274          */
7275         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7276                 return -ERANGE;
7277
7278         vmx->hv_deadline_tsc = tscl + delta_tsc;
7279         *expired = !delta_tsc;
7280         return 0;
7281 }
7282
7283 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7284 {
7285         to_vmx(vcpu)->hv_deadline_tsc = -1;
7286 }
7287 #endif
7288
7289 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
7290 {
7291         if (!kvm_pause_in_guest(vcpu->kvm))
7292                 shrink_ple_window(vcpu);
7293 }
7294
7295 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
7296                                      struct kvm_memory_slot *slot)
7297 {
7298         if (!kvm_dirty_log_manual_protect_and_init_set(kvm))
7299                 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
7300         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
7301 }
7302
7303 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
7304                                        struct kvm_memory_slot *slot)
7305 {
7306         kvm_mmu_slot_set_dirty(kvm, slot);
7307 }
7308
7309 static void vmx_flush_log_dirty(struct kvm *kvm)
7310 {
7311         kvm_flush_pml_buffers(kvm);
7312 }
7313
7314 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
7315 {
7316         struct vmcs12 *vmcs12;
7317         struct vcpu_vmx *vmx = to_vmx(vcpu);
7318         gpa_t gpa, dst;
7319
7320         if (is_guest_mode(vcpu)) {
7321                 WARN_ON_ONCE(vmx->nested.pml_full);
7322
7323                 /*
7324                  * Check if PML is enabled for the nested guest.
7325                  * Whether eptp bit 6 is set is already checked
7326                  * as part of A/D emulation.
7327                  */
7328                 vmcs12 = get_vmcs12(vcpu);
7329                 if (!nested_cpu_has_pml(vmcs12))
7330                         return 0;
7331
7332                 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
7333                         vmx->nested.pml_full = true;
7334                         return 1;
7335                 }
7336
7337                 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
7338                 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index;
7339
7340                 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa,
7341                                          offset_in_page(dst), sizeof(gpa)))
7342                         return 0;
7343
7344                 vmcs12->guest_pml_index--;
7345         }
7346
7347         return 0;
7348 }
7349
7350 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
7351                                            struct kvm_memory_slot *memslot,
7352                                            gfn_t offset, unsigned long mask)
7353 {
7354         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
7355 }
7356
7357 static void __pi_post_block(struct kvm_vcpu *vcpu)
7358 {
7359         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7360         struct pi_desc old, new;
7361         unsigned int dest;
7362
7363         do {
7364                 old.control = new.control = pi_desc->control;
7365                 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
7366                      "Wakeup handler not enabled while the VCPU is blocked\n");
7367
7368                 dest = cpu_physical_id(vcpu->cpu);
7369
7370                 if (x2apic_enabled())
7371                         new.ndst = dest;
7372                 else
7373                         new.ndst = (dest << 8) & 0xFF00;
7374
7375                 /* set 'NV' to 'notification vector' */
7376                 new.nv = POSTED_INTR_VECTOR;
7377         } while (cmpxchg64(&pi_desc->control, old.control,
7378                            new.control) != old.control);
7379
7380         if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
7381                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7382                 list_del(&vcpu->blocked_vcpu_list);
7383                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7384                 vcpu->pre_pcpu = -1;
7385         }
7386 }
7387
7388 /*
7389  * This routine does the following things for vCPU which is going
7390  * to be blocked if VT-d PI is enabled.
7391  * - Store the vCPU to the wakeup list, so when interrupts happen
7392  *   we can find the right vCPU to wake up.
7393  * - Change the Posted-interrupt descriptor as below:
7394  *      'NDST' <-- vcpu->pre_pcpu
7395  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
7396  * - If 'ON' is set during this process, which means at least one
7397  *   interrupt is posted for this vCPU, we cannot block it, in
7398  *   this case, return 1, otherwise, return 0.
7399  *
7400  */
7401 static int pi_pre_block(struct kvm_vcpu *vcpu)
7402 {
7403         unsigned int dest;
7404         struct pi_desc old, new;
7405         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7406
7407         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
7408                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
7409                 !kvm_vcpu_apicv_active(vcpu))
7410                 return 0;
7411
7412         WARN_ON(irqs_disabled());
7413         local_irq_disable();
7414         if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
7415                 vcpu->pre_pcpu = vcpu->cpu;
7416                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7417                 list_add_tail(&vcpu->blocked_vcpu_list,
7418                               &per_cpu(blocked_vcpu_on_cpu,
7419                                        vcpu->pre_pcpu));
7420                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7421         }
7422
7423         do {
7424                 old.control = new.control = pi_desc->control;
7425
7426                 WARN((pi_desc->sn == 1),
7427                      "Warning: SN field of posted-interrupts "
7428                      "is set before blocking\n");
7429
7430                 /*
7431                  * Since vCPU can be preempted during this process,
7432                  * vcpu->cpu could be different with pre_pcpu, we
7433                  * need to set pre_pcpu as the destination of wakeup
7434                  * notification event, then we can find the right vCPU
7435                  * to wakeup in wakeup handler if interrupts happen
7436                  * when the vCPU is in blocked state.
7437                  */
7438                 dest = cpu_physical_id(vcpu->pre_pcpu);
7439
7440                 if (x2apic_enabled())
7441                         new.ndst = dest;
7442                 else
7443                         new.ndst = (dest << 8) & 0xFF00;
7444
7445                 /* set 'NV' to 'wakeup vector' */
7446                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
7447         } while (cmpxchg64(&pi_desc->control, old.control,
7448                            new.control) != old.control);
7449
7450         /* We should not block the vCPU if an interrupt is posted for it.  */
7451         if (pi_test_on(pi_desc) == 1)
7452                 __pi_post_block(vcpu);
7453
7454         local_irq_enable();
7455         return (vcpu->pre_pcpu == -1);
7456 }
7457
7458 static int vmx_pre_block(struct kvm_vcpu *vcpu)
7459 {
7460         if (pi_pre_block(vcpu))
7461                 return 1;
7462
7463         if (kvm_lapic_hv_timer_in_use(vcpu))
7464                 kvm_lapic_switch_to_sw_timer(vcpu);
7465
7466         return 0;
7467 }
7468
7469 static void pi_post_block(struct kvm_vcpu *vcpu)
7470 {
7471         if (vcpu->pre_pcpu == -1)
7472                 return;
7473
7474         WARN_ON(irqs_disabled());
7475         local_irq_disable();
7476         __pi_post_block(vcpu);
7477         local_irq_enable();
7478 }
7479
7480 static void vmx_post_block(struct kvm_vcpu *vcpu)
7481 {
7482         if (kvm_x86_ops->set_hv_timer)
7483                 kvm_lapic_switch_to_hv_timer(vcpu);
7484
7485         pi_post_block(vcpu);
7486 }
7487
7488 /*
7489  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
7490  *
7491  * @kvm: kvm
7492  * @host_irq: host irq of the interrupt
7493  * @guest_irq: gsi of the interrupt
7494  * @set: set or unset PI
7495  * returns 0 on success, < 0 on failure
7496  */
7497 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
7498                               uint32_t guest_irq, bool set)
7499 {
7500         struct kvm_kernel_irq_routing_entry *e;
7501         struct kvm_irq_routing_table *irq_rt;
7502         struct kvm_lapic_irq irq;
7503         struct kvm_vcpu *vcpu;
7504         struct vcpu_data vcpu_info;
7505         int idx, ret = 0;
7506
7507         if (!kvm_arch_has_assigned_device(kvm) ||
7508                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7509                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
7510                 return 0;
7511
7512         idx = srcu_read_lock(&kvm->irq_srcu);
7513         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
7514         if (guest_irq >= irq_rt->nr_rt_entries ||
7515             hlist_empty(&irq_rt->map[guest_irq])) {
7516                 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
7517                              guest_irq, irq_rt->nr_rt_entries);
7518                 goto out;
7519         }
7520
7521         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
7522                 if (e->type != KVM_IRQ_ROUTING_MSI)
7523                         continue;
7524                 /*
7525                  * VT-d PI cannot support posting multicast/broadcast
7526                  * interrupts to a vCPU, we still use interrupt remapping
7527                  * for these kind of interrupts.
7528                  *
7529                  * For lowest-priority interrupts, we only support
7530                  * those with single CPU as the destination, e.g. user
7531                  * configures the interrupts via /proc/irq or uses
7532                  * irqbalance to make the interrupts single-CPU.
7533                  *
7534                  * We will support full lowest-priority interrupt later.
7535                  *
7536                  * In addition, we can only inject generic interrupts using
7537                  * the PI mechanism, refuse to route others through it.
7538                  */
7539
7540                 kvm_set_msi_irq(kvm, e, &irq);
7541                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) ||
7542                     !kvm_irq_is_postable(&irq)) {
7543                         /*
7544                          * Make sure the IRTE is in remapped mode if
7545                          * we don't handle it in posted mode.
7546                          */
7547                         ret = irq_set_vcpu_affinity(host_irq, NULL);
7548                         if (ret < 0) {
7549                                 printk(KERN_INFO
7550                                    "failed to back to remapped mode, irq: %u\n",
7551                                    host_irq);
7552                                 goto out;
7553                         }
7554
7555                         continue;
7556                 }
7557
7558                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
7559                 vcpu_info.vector = irq.vector;
7560
7561                 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
7562                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
7563
7564                 if (set)
7565                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
7566                 else
7567                         ret = irq_set_vcpu_affinity(host_irq, NULL);
7568
7569                 if (ret < 0) {
7570                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
7571                                         __func__);
7572                         goto out;
7573                 }
7574         }
7575
7576         ret = 0;
7577 out:
7578         srcu_read_unlock(&kvm->irq_srcu, idx);
7579         return ret;
7580 }
7581
7582 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7583 {
7584         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7585                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7586                         FEAT_CTL_LMCE_ENABLED;
7587         else
7588                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7589                         ~FEAT_CTL_LMCE_ENABLED;
7590 }
7591
7592 static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
7593 {
7594         /* we need a nested vmexit to enter SMM, postpone if run is pending */
7595         if (to_vmx(vcpu)->nested.nested_run_pending)
7596                 return 0;
7597         return 1;
7598 }
7599
7600 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7601 {
7602         struct vcpu_vmx *vmx = to_vmx(vcpu);
7603
7604         vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7605         if (vmx->nested.smm.guest_mode)
7606                 nested_vmx_vmexit(vcpu, -1, 0, 0);
7607
7608         vmx->nested.smm.vmxon = vmx->nested.vmxon;
7609         vmx->nested.vmxon = false;
7610         vmx_clear_hlt(vcpu);
7611         return 0;
7612 }
7613
7614 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
7615 {
7616         struct vcpu_vmx *vmx = to_vmx(vcpu);
7617         int ret;
7618
7619         if (vmx->nested.smm.vmxon) {
7620                 vmx->nested.vmxon = true;
7621                 vmx->nested.smm.vmxon = false;
7622         }
7623
7624         if (vmx->nested.smm.guest_mode) {
7625                 ret = nested_vmx_enter_non_root_mode(vcpu, false);
7626                 if (ret)
7627                         return ret;
7628
7629                 vmx->nested.smm.guest_mode = false;
7630         }
7631         return 0;
7632 }
7633
7634 static int enable_smi_window(struct kvm_vcpu *vcpu)
7635 {
7636         return 0;
7637 }
7638
7639 static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7640 {
7641         return false;
7642 }
7643
7644 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7645 {
7646         return to_vmx(vcpu)->nested.vmxon;
7647 }
7648
7649 static __init int hardware_setup(void)
7650 {
7651         unsigned long host_bndcfgs;
7652         struct desc_ptr dt;
7653         int r, i, ept_lpage_level;
7654
7655         store_idt(&dt);
7656         host_idt_base = dt.address;
7657
7658         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7659                 kvm_define_shared_msr(i, vmx_msr_index[i]);
7660
7661         if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7662                 return -EIO;
7663
7664         if (boot_cpu_has(X86_FEATURE_NX))
7665                 kvm_enable_efer_bits(EFER_NX);
7666
7667         if (boot_cpu_has(X86_FEATURE_MPX)) {
7668                 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7669                 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7670         }
7671
7672         if (!cpu_has_vmx_mpx())
7673                 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS |
7674                                     XFEATURE_MASK_BNDCSR);
7675
7676         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7677             !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7678                 enable_vpid = 0;
7679
7680         if (!cpu_has_vmx_ept() ||
7681             !cpu_has_vmx_ept_4levels() ||
7682             !cpu_has_vmx_ept_mt_wb() ||
7683             !cpu_has_vmx_invept_global())
7684                 enable_ept = 0;
7685
7686         if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7687                 enable_ept_ad_bits = 0;
7688
7689         if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7690                 enable_unrestricted_guest = 0;
7691
7692         if (!cpu_has_vmx_flexpriority())
7693                 flexpriority_enabled = 0;
7694
7695         if (!cpu_has_virtual_nmis())
7696                 enable_vnmi = 0;
7697
7698         /*
7699          * set_apic_access_page_addr() is used to reload apic access
7700          * page upon invalidation.  No need to do anything if not
7701          * using the APIC_ACCESS_ADDR VMCS field.
7702          */
7703         if (!flexpriority_enabled)
7704                 kvm_x86_ops->set_apic_access_page_addr = NULL;
7705
7706         if (!cpu_has_vmx_tpr_shadow())
7707                 kvm_x86_ops->update_cr8_intercept = NULL;
7708
7709 #if IS_ENABLED(CONFIG_HYPERV)
7710         if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7711             && enable_ept) {
7712                 kvm_x86_ops->tlb_remote_flush = hv_remote_flush_tlb;
7713                 kvm_x86_ops->tlb_remote_flush_with_range =
7714                                 hv_remote_flush_tlb_with_range;
7715         }
7716 #endif
7717
7718         if (!cpu_has_vmx_ple()) {
7719                 ple_gap = 0;
7720                 ple_window = 0;
7721                 ple_window_grow = 0;
7722                 ple_window_max = 0;
7723                 ple_window_shrink = 0;
7724         }
7725
7726         if (!cpu_has_vmx_apicv()) {
7727                 enable_apicv = 0;
7728                 kvm_x86_ops->sync_pir_to_irr = NULL;
7729         }
7730
7731         if (cpu_has_vmx_tsc_scaling()) {
7732                 kvm_has_tsc_control = true;
7733                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7734                 kvm_tsc_scaling_ratio_frac_bits = 48;
7735         }
7736
7737         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7738
7739         if (enable_ept)
7740                 vmx_enable_tdp();
7741
7742         if (!enable_ept)
7743                 ept_lpage_level = 0;
7744         else if (cpu_has_vmx_ept_1g_page())
7745                 ept_lpage_level = PT_PDPE_LEVEL;
7746         else if (cpu_has_vmx_ept_2m_page())
7747                 ept_lpage_level = PT_DIRECTORY_LEVEL;
7748         else
7749                 ept_lpage_level = PT_PAGE_TABLE_LEVEL;
7750         kvm_configure_mmu(enable_ept, ept_lpage_level);
7751
7752         /*
7753          * Only enable PML when hardware supports PML feature, and both EPT
7754          * and EPT A/D bit features are enabled -- PML depends on them to work.
7755          */
7756         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7757                 enable_pml = 0;
7758
7759         if (!enable_pml) {
7760                 kvm_x86_ops->slot_enable_log_dirty = NULL;
7761                 kvm_x86_ops->slot_disable_log_dirty = NULL;
7762                 kvm_x86_ops->flush_log_dirty = NULL;
7763                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7764         }
7765
7766         if (!cpu_has_vmx_preemption_timer())
7767                 enable_preemption_timer = false;
7768
7769         if (enable_preemption_timer) {
7770                 u64 use_timer_freq = 5000ULL * 1000 * 1000;
7771                 u64 vmx_msr;
7772
7773                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7774                 cpu_preemption_timer_multi =
7775                         vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7776
7777                 if (tsc_khz)
7778                         use_timer_freq = (u64)tsc_khz * 1000;
7779                 use_timer_freq >>= cpu_preemption_timer_multi;
7780
7781                 /*
7782                  * KVM "disables" the preemption timer by setting it to its max
7783                  * value.  Don't use the timer if it might cause spurious exits
7784                  * at a rate faster than 0.1 Hz (of uninterrupted guest time).
7785                  */
7786                 if (use_timer_freq > 0xffffffffu / 10)
7787                         enable_preemption_timer = false;
7788         }
7789
7790         if (!enable_preemption_timer) {
7791                 kvm_x86_ops->set_hv_timer = NULL;
7792                 kvm_x86_ops->cancel_hv_timer = NULL;
7793                 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit;
7794         }
7795
7796         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
7797
7798         kvm_mce_cap_supported |= MCG_LMCE_P;
7799
7800         if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
7801                 return -EINVAL;
7802         if (!enable_ept || !cpu_has_vmx_intel_pt())
7803                 pt_mode = PT_MODE_SYSTEM;
7804
7805         if (nested) {
7806                 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
7807                                            vmx_capability.ept);
7808
7809                 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
7810                 if (r)
7811                         return r;
7812         }
7813
7814         vmx_set_cpu_caps();
7815
7816         r = alloc_kvm_area();
7817         if (r)
7818                 nested_vmx_hardware_unsetup();
7819         return r;
7820 }
7821
7822 static __exit void hardware_unsetup(void)
7823 {
7824         if (nested)
7825                 nested_vmx_hardware_unsetup();
7826
7827         free_kvm_area();
7828 }
7829
7830 static bool vmx_check_apicv_inhibit_reasons(ulong bit)
7831 {
7832         ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) |
7833                           BIT(APICV_INHIBIT_REASON_HYPERV);
7834
7835         return supported & BIT(bit);
7836 }
7837
7838 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
7839         .cpu_has_kvm_support = cpu_has_kvm_support,
7840         .disabled_by_bios = vmx_disabled_by_bios,
7841         .hardware_setup = hardware_setup,
7842         .hardware_unsetup = hardware_unsetup,
7843         .check_processor_compatibility = vmx_check_processor_compat,
7844         .hardware_enable = hardware_enable,
7845         .hardware_disable = hardware_disable,
7846         .cpu_has_accelerated_tpr = report_flexpriority,
7847         .has_emulated_msr = vmx_has_emulated_msr,
7848
7849         .vm_size = sizeof(struct kvm_vmx),
7850         .vm_init = vmx_vm_init,
7851
7852         .vcpu_create = vmx_create_vcpu,
7853         .vcpu_free = vmx_free_vcpu,
7854         .vcpu_reset = vmx_vcpu_reset,
7855
7856         .prepare_guest_switch = vmx_prepare_switch_to_guest,
7857         .vcpu_load = vmx_vcpu_load,
7858         .vcpu_put = vmx_vcpu_put,
7859
7860         .update_bp_intercept = update_exception_bitmap,
7861         .get_msr_feature = vmx_get_msr_feature,
7862         .get_msr = vmx_get_msr,
7863         .set_msr = vmx_set_msr,
7864         .get_segment_base = vmx_get_segment_base,
7865         .get_segment = vmx_get_segment,
7866         .set_segment = vmx_set_segment,
7867         .get_cpl = vmx_get_cpl,
7868         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7869         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7870         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7871         .set_cr0 = vmx_set_cr0,
7872         .set_cr4 = vmx_set_cr4,
7873         .set_efer = vmx_set_efer,
7874         .get_idt = vmx_get_idt,
7875         .set_idt = vmx_set_idt,
7876         .get_gdt = vmx_get_gdt,
7877         .set_gdt = vmx_set_gdt,
7878         .get_dr6 = vmx_get_dr6,
7879         .set_dr6 = vmx_set_dr6,
7880         .set_dr7 = vmx_set_dr7,
7881         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
7882         .cache_reg = vmx_cache_reg,
7883         .get_rflags = vmx_get_rflags,
7884         .set_rflags = vmx_set_rflags,
7885
7886         .tlb_flush = vmx_flush_tlb,
7887         .tlb_flush_gva = vmx_flush_tlb_gva,
7888
7889         .run = vmx_vcpu_run,
7890         .handle_exit = vmx_handle_exit,
7891         .skip_emulated_instruction = vmx_skip_emulated_instruction,
7892         .update_emulated_instruction = vmx_update_emulated_instruction,
7893         .set_interrupt_shadow = vmx_set_interrupt_shadow,
7894         .get_interrupt_shadow = vmx_get_interrupt_shadow,
7895         .patch_hypercall = vmx_patch_hypercall,
7896         .set_irq = vmx_inject_irq,
7897         .set_nmi = vmx_inject_nmi,
7898         .queue_exception = vmx_queue_exception,
7899         .cancel_injection = vmx_cancel_injection,
7900         .interrupt_allowed = vmx_interrupt_allowed,
7901         .nmi_allowed = vmx_nmi_allowed,
7902         .get_nmi_mask = vmx_get_nmi_mask,
7903         .set_nmi_mask = vmx_set_nmi_mask,
7904         .enable_nmi_window = enable_nmi_window,
7905         .enable_irq_window = enable_irq_window,
7906         .update_cr8_intercept = update_cr8_intercept,
7907         .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
7908         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
7909         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
7910         .load_eoi_exitmap = vmx_load_eoi_exitmap,
7911         .apicv_post_state_restore = vmx_apicv_post_state_restore,
7912         .check_apicv_inhibit_reasons = vmx_check_apicv_inhibit_reasons,
7913         .hwapic_irr_update = vmx_hwapic_irr_update,
7914         .hwapic_isr_update = vmx_hwapic_isr_update,
7915         .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
7916         .sync_pir_to_irr = vmx_sync_pir_to_irr,
7917         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
7918         .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt,
7919
7920         .set_tss_addr = vmx_set_tss_addr,
7921         .set_identity_map_addr = vmx_set_identity_map_addr,
7922         .get_tdp_level = get_ept_level,
7923         .get_mt_mask = vmx_get_mt_mask,
7924
7925         .get_exit_info = vmx_get_exit_info,
7926
7927         .cpuid_update = vmx_cpuid_update,
7928
7929         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7930
7931         .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
7932         .write_l1_tsc_offset = vmx_write_l1_tsc_offset,
7933
7934         .load_mmu_pgd = vmx_load_mmu_pgd,
7935
7936         .check_intercept = vmx_check_intercept,
7937         .handle_exit_irqoff = vmx_handle_exit_irqoff,
7938
7939         .request_immediate_exit = vmx_request_immediate_exit,
7940
7941         .sched_in = vmx_sched_in,
7942
7943         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
7944         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
7945         .flush_log_dirty = vmx_flush_log_dirty,
7946         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
7947         .write_log_dirty = vmx_write_pml_buffer,
7948
7949         .pre_block = vmx_pre_block,
7950         .post_block = vmx_post_block,
7951
7952         .pmu_ops = &intel_pmu_ops,
7953
7954         .update_pi_irte = vmx_update_pi_irte,
7955
7956 #ifdef CONFIG_X86_64
7957         .set_hv_timer = vmx_set_hv_timer,
7958         .cancel_hv_timer = vmx_cancel_hv_timer,
7959 #endif
7960
7961         .setup_mce = vmx_setup_mce,
7962
7963         .smi_allowed = vmx_smi_allowed,
7964         .pre_enter_smm = vmx_pre_enter_smm,
7965         .pre_leave_smm = vmx_pre_leave_smm,
7966         .enable_smi_window = enable_smi_window,
7967
7968         .check_nested_events = NULL,
7969         .get_nested_state = NULL,
7970         .set_nested_state = NULL,
7971         .get_vmcs12_pages = NULL,
7972         .nested_enable_evmcs = NULL,
7973         .nested_get_evmcs_version = NULL,
7974         .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault,
7975         .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
7976 };
7977
7978 static void vmx_cleanup_l1d_flush(void)
7979 {
7980         if (vmx_l1d_flush_pages) {
7981                 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
7982                 vmx_l1d_flush_pages = NULL;
7983         }
7984         /* Restore state so sysfs ignores VMX */
7985         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
7986 }
7987
7988 static void vmx_exit(void)
7989 {
7990 #ifdef CONFIG_KEXEC_CORE
7991         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
7992         synchronize_rcu();
7993 #endif
7994
7995         kvm_exit();
7996
7997 #if IS_ENABLED(CONFIG_HYPERV)
7998         if (static_branch_unlikely(&enable_evmcs)) {
7999                 int cpu;
8000                 struct hv_vp_assist_page *vp_ap;
8001                 /*
8002                  * Reset everything to support using non-enlightened VMCS
8003                  * access later (e.g. when we reload the module with
8004                  * enlightened_vmcs=0)
8005                  */
8006                 for_each_online_cpu(cpu) {
8007                         vp_ap = hv_get_vp_assist_page(cpu);
8008
8009                         if (!vp_ap)
8010                                 continue;
8011
8012                         vp_ap->nested_control.features.directhypercall = 0;
8013                         vp_ap->current_nested_vmcs = 0;
8014                         vp_ap->enlighten_vmentry = 0;
8015                 }
8016
8017                 static_branch_disable(&enable_evmcs);
8018         }
8019 #endif
8020         vmx_cleanup_l1d_flush();
8021 }
8022 module_exit(vmx_exit);
8023
8024 static int __init vmx_init(void)
8025 {
8026         int r;
8027
8028 #if IS_ENABLED(CONFIG_HYPERV)
8029         /*
8030          * Enlightened VMCS usage should be recommended and the host needs
8031          * to support eVMCS v1 or above. We can also disable eVMCS support
8032          * with module parameter.
8033          */
8034         if (enlightened_vmcs &&
8035             ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
8036             (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
8037             KVM_EVMCS_VERSION) {
8038                 int cpu;
8039
8040                 /* Check that we have assist pages on all online CPUs */
8041                 for_each_online_cpu(cpu) {
8042                         if (!hv_get_vp_assist_page(cpu)) {
8043                                 enlightened_vmcs = false;
8044                                 break;
8045                         }
8046                 }
8047
8048                 if (enlightened_vmcs) {
8049                         pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
8050                         static_branch_enable(&enable_evmcs);
8051                 }
8052
8053                 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
8054                         vmx_x86_ops.enable_direct_tlbflush
8055                                 = hv_enable_direct_tlbflush;
8056
8057         } else {
8058                 enlightened_vmcs = false;
8059         }
8060 #endif
8061
8062         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8063                      __alignof__(struct vcpu_vmx), THIS_MODULE);
8064         if (r)
8065                 return r;
8066
8067         /*
8068          * Must be called after kvm_init() so enable_ept is properly set
8069          * up. Hand the parameter mitigation value in which was stored in
8070          * the pre module init parser. If no parameter was given, it will
8071          * contain 'auto' which will be turned into the default 'cond'
8072          * mitigation mode.
8073          */
8074         r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
8075         if (r) {
8076                 vmx_exit();
8077                 return r;
8078         }
8079
8080 #ifdef CONFIG_KEXEC_CORE
8081         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8082                            crash_vmclear_local_loaded_vmcss);
8083 #endif
8084         vmx_check_vmcs12_offsets();
8085
8086         return 0;
8087 }
8088 module_init(vmx_init);