1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
8 * Copyright (C) 2006 Qumranet, Inc.
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
16 #include <linux/frame.h>
17 #include <linux/highmem.h>
18 #include <linux/hrtimer.h>
19 #include <linux/kernel.h>
20 #include <linux/kvm_host.h>
21 #include <linux/module.h>
22 #include <linux/moduleparam.h>
23 #include <linux/mod_devicetable.h>
25 #include <linux/sched.h>
26 #include <linux/sched/smt.h>
27 #include <linux/slab.h>
28 #include <linux/tboot.h>
29 #include <linux/trace_events.h>
34 #include <asm/debugreg.h>
36 #include <asm/fpu/internal.h>
38 #include <asm/irq_remapping.h>
39 #include <asm/kexec.h>
40 #include <asm/perf_event.h>
42 #include <asm/mmu_context.h>
43 #include <asm/mshyperv.h>
44 #include <asm/spec-ctrl.h>
45 #include <asm/virtext.h>
48 #include "capabilities.h"
52 #include "kvm_cache_regs.h"
64 MODULE_AUTHOR("Qumranet");
65 MODULE_LICENSE("GPL");
67 static const struct x86_cpu_id vmx_cpu_id[] = {
68 X86_FEATURE_MATCH(X86_FEATURE_VMX),
71 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
73 bool __read_mostly enable_vpid = 1;
74 module_param_named(vpid, enable_vpid, bool, 0444);
76 static bool __read_mostly enable_vnmi = 1;
77 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
79 bool __read_mostly flexpriority_enabled = 1;
80 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
82 bool __read_mostly enable_ept = 1;
83 module_param_named(ept, enable_ept, bool, S_IRUGO);
85 bool __read_mostly enable_unrestricted_guest = 1;
86 module_param_named(unrestricted_guest,
87 enable_unrestricted_guest, bool, S_IRUGO);
89 bool __read_mostly enable_ept_ad_bits = 1;
90 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
92 static bool __read_mostly emulate_invalid_guest_state = true;
93 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
95 static bool __read_mostly fasteoi = 1;
96 module_param(fasteoi, bool, S_IRUGO);
98 static bool __read_mostly enable_apicv = 1;
99 module_param(enable_apicv, bool, S_IRUGO);
102 * If nested=1, nested virtualization is supported, i.e., guests may use
103 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
104 * use VMX instructions.
106 static bool __read_mostly nested = 1;
107 module_param(nested, bool, S_IRUGO);
109 static u64 __read_mostly host_xss;
111 bool __read_mostly enable_pml = 1;
112 module_param_named(pml, enable_pml, bool, S_IRUGO);
114 static bool __read_mostly dump_invalid_vmcs = 0;
115 module_param(dump_invalid_vmcs, bool, 0644);
117 #define MSR_BITMAP_MODE_X2APIC 1
118 #define MSR_BITMAP_MODE_X2APIC_APICV 2
120 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
122 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
123 static int __read_mostly cpu_preemption_timer_multi;
124 static bool __read_mostly enable_preemption_timer = 1;
126 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
129 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
130 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
131 #define KVM_VM_CR0_ALWAYS_ON \
132 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \
133 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
134 #define KVM_CR4_GUEST_OWNED_BITS \
135 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
136 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
138 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
139 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
140 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
142 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
144 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
145 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
146 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
147 RTIT_STATUS_BYTECNT))
149 #define MSR_IA32_RTIT_OUTPUT_BASE_MASK \
150 (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f)
153 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
154 * ple_gap: upper bound on the amount of time between two successive
155 * executions of PAUSE in a loop. Also indicate if ple enabled.
156 * According to test, this time is usually smaller than 128 cycles.
157 * ple_window: upper bound on the amount of time a guest is allowed to execute
158 * in a PAUSE loop. Tests indicate that most spinlocks are held for
159 * less than 2^12 cycles
160 * Time is measured based on a counter that runs at the same rate as the TSC,
161 * refer SDM volume 3b section 21.6.13 & 22.1.3.
163 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
164 module_param(ple_gap, uint, 0444);
166 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
167 module_param(ple_window, uint, 0444);
169 /* Default doubles per-vcpu window every exit. */
170 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
171 module_param(ple_window_grow, uint, 0444);
173 /* Default resets per-vcpu window every exit to ple_window. */
174 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
175 module_param(ple_window_shrink, uint, 0444);
177 /* Default is to compute the maximum so we can never overflow. */
178 static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
179 module_param(ple_window_max, uint, 0444);
181 /* Default is SYSTEM mode, 1 for host-guest mode */
182 int __read_mostly pt_mode = PT_MODE_SYSTEM;
183 module_param(pt_mode, int, S_IRUGO);
185 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
186 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
187 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
189 /* Storage for pre module init parameter parsing */
190 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
192 static const struct {
195 } vmentry_l1d_param[] = {
196 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true},
197 [VMENTER_L1D_FLUSH_NEVER] = {"never", true},
198 [VMENTER_L1D_FLUSH_COND] = {"cond", true},
199 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true},
200 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
201 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
204 #define L1D_CACHE_ORDER 4
205 static void *vmx_l1d_flush_pages;
207 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
213 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
217 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
220 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
221 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
222 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
227 /* If set to auto use the default l1tf mitigation method */
228 if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
229 switch (l1tf_mitigation) {
230 case L1TF_MITIGATION_OFF:
231 l1tf = VMENTER_L1D_FLUSH_NEVER;
233 case L1TF_MITIGATION_FLUSH_NOWARN:
234 case L1TF_MITIGATION_FLUSH:
235 case L1TF_MITIGATION_FLUSH_NOSMT:
236 l1tf = VMENTER_L1D_FLUSH_COND;
238 case L1TF_MITIGATION_FULL:
239 case L1TF_MITIGATION_FULL_FORCE:
240 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
243 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
244 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
247 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
248 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
250 * This allocation for vmx_l1d_flush_pages is not tied to a VM
251 * lifetime and so should not be charged to a memcg.
253 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
256 vmx_l1d_flush_pages = page_address(page);
259 * Initialize each page with a different pattern in
260 * order to protect against KSM in the nested
261 * virtualization case.
263 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
264 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
269 l1tf_vmx_mitigation = l1tf;
271 if (l1tf != VMENTER_L1D_FLUSH_NEVER)
272 static_branch_enable(&vmx_l1d_should_flush);
274 static_branch_disable(&vmx_l1d_should_flush);
276 if (l1tf == VMENTER_L1D_FLUSH_COND)
277 static_branch_enable(&vmx_l1d_flush_cond);
279 static_branch_disable(&vmx_l1d_flush_cond);
283 static int vmentry_l1d_flush_parse(const char *s)
288 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
289 if (vmentry_l1d_param[i].for_parse &&
290 sysfs_streq(s, vmentry_l1d_param[i].option))
297 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
301 l1tf = vmentry_l1d_flush_parse(s);
305 if (!boot_cpu_has(X86_BUG_L1TF))
309 * Has vmx_init() run already? If not then this is the pre init
310 * parameter parsing. In that case just store the value and let
311 * vmx_init() do the proper setup after enable_ept has been
314 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
315 vmentry_l1d_flush_param = l1tf;
319 mutex_lock(&vmx_l1d_flush_mutex);
320 ret = vmx_setup_l1d_flush(l1tf);
321 mutex_unlock(&vmx_l1d_flush_mutex);
325 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
327 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
328 return sprintf(s, "???\n");
330 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
333 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
334 .set = vmentry_l1d_flush_set,
335 .get = vmentry_l1d_flush_get,
337 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
339 static bool guest_state_valid(struct kvm_vcpu *vcpu);
340 static u32 vmx_segment_access_rights(struct kvm_segment *var);
341 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
344 void vmx_vmexit(void);
346 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
347 DEFINE_PER_CPU(struct vmcs *, current_vmcs);
349 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
350 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
352 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
355 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
356 * can find which vCPU should be waken up.
358 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
359 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
361 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
362 static DEFINE_SPINLOCK(vmx_vpid_lock);
364 struct vmcs_config vmcs_config;
365 struct vmx_capability vmx_capability;
367 #define VMX_SEGMENT_FIELD(seg) \
368 [VCPU_SREG_##seg] = { \
369 .selector = GUEST_##seg##_SELECTOR, \
370 .base = GUEST_##seg##_BASE, \
371 .limit = GUEST_##seg##_LIMIT, \
372 .ar_bytes = GUEST_##seg##_AR_BYTES, \
375 static const struct kvm_vmx_segment_field {
380 } kvm_vmx_segment_fields[] = {
381 VMX_SEGMENT_FIELD(CS),
382 VMX_SEGMENT_FIELD(DS),
383 VMX_SEGMENT_FIELD(ES),
384 VMX_SEGMENT_FIELD(FS),
385 VMX_SEGMENT_FIELD(GS),
386 VMX_SEGMENT_FIELD(SS),
387 VMX_SEGMENT_FIELD(TR),
388 VMX_SEGMENT_FIELD(LDTR),
392 static unsigned long host_idt_base;
395 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
396 * will emulate SYSCALL in legacy mode if the vendor string in guest
397 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
398 * support this emulation, IA32_STAR must always be included in
399 * vmx_msr_index[], even in i386 builds.
401 const u32 vmx_msr_index[] = {
403 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
405 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
408 #if IS_ENABLED(CONFIG_HYPERV)
409 static bool __read_mostly enlightened_vmcs = true;
410 module_param(enlightened_vmcs, bool, 0444);
412 /* check_ept_pointer() should be under protection of ept_pointer_lock. */
413 static void check_ept_pointer_match(struct kvm *kvm)
415 struct kvm_vcpu *vcpu;
416 u64 tmp_eptp = INVALID_PAGE;
419 kvm_for_each_vcpu(i, vcpu, kvm) {
420 if (!VALID_PAGE(tmp_eptp)) {
421 tmp_eptp = to_vmx(vcpu)->ept_pointer;
422 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
423 to_kvm_vmx(kvm)->ept_pointers_match
424 = EPT_POINTERS_MISMATCH;
429 to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
432 static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush,
435 struct kvm_tlb_range *range = data;
437 return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn,
441 static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm,
442 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range)
444 u64 ept_pointer = to_vmx(vcpu)->ept_pointer;
447 * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address
448 * of the base of EPT PML4 table, strip off EPT configuration
452 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK,
453 kvm_fill_hv_flush_list_func, (void *)range);
455 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK);
458 static int hv_remote_flush_tlb_with_range(struct kvm *kvm,
459 struct kvm_tlb_range *range)
461 struct kvm_vcpu *vcpu;
464 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
466 if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
467 check_ept_pointer_match(kvm);
469 if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
470 kvm_for_each_vcpu(i, vcpu, kvm) {
471 /* If ept_pointer is invalid pointer, bypass flush request. */
472 if (VALID_PAGE(to_vmx(vcpu)->ept_pointer))
473 ret |= __hv_remote_flush_tlb_with_range(
477 ret = __hv_remote_flush_tlb_with_range(kvm,
478 kvm_get_vcpu(kvm, 0), range);
481 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
484 static int hv_remote_flush_tlb(struct kvm *kvm)
486 return hv_remote_flush_tlb_with_range(kvm, NULL);
489 #endif /* IS_ENABLED(CONFIG_HYPERV) */
492 * Comment's format: document - errata name - stepping - processor name.
494 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
496 static u32 vmx_preemption_cpu_tfms[] = {
497 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
499 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
500 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
501 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
503 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
505 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
506 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
508 * 320767.pdf - AAP86 - B1 -
509 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
512 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
514 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
516 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
518 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
519 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
520 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
522 /* Xeon E3-1220 V2 */
526 static inline bool cpu_has_broken_vmx_preemption_timer(void)
528 u32 eax = cpuid_eax(0x00000001), i;
530 /* Clear the reserved bits */
531 eax &= ~(0x3U << 14 | 0xfU << 28);
532 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
533 if (eax == vmx_preemption_cpu_tfms[i])
539 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
541 return flexpriority_enabled && lapic_in_kernel(vcpu);
544 static inline bool report_flexpriority(void)
546 return flexpriority_enabled;
549 static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
553 for (i = 0; i < vmx->nmsrs; ++i)
554 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
559 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
563 i = __find_msr_index(vmx, msr);
565 return &vmx->guest_msrs[i];
569 void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
571 vmcs_clear(loaded_vmcs->vmcs);
572 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
573 vmcs_clear(loaded_vmcs->shadow_vmcs);
574 loaded_vmcs->cpu = -1;
575 loaded_vmcs->launched = 0;
578 #ifdef CONFIG_KEXEC_CORE
580 * This bitmap is used to indicate whether the vmclear
581 * operation is enabled on all cpus. All disabled by
584 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
586 static inline void crash_enable_local_vmclear(int cpu)
588 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
591 static inline void crash_disable_local_vmclear(int cpu)
593 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
596 static inline int crash_local_vmclear_enabled(int cpu)
598 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
601 static void crash_vmclear_local_loaded_vmcss(void)
603 int cpu = raw_smp_processor_id();
604 struct loaded_vmcs *v;
606 if (!crash_local_vmclear_enabled(cpu))
609 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
610 loaded_vmcss_on_cpu_link)
614 static inline void crash_enable_local_vmclear(int cpu) { }
615 static inline void crash_disable_local_vmclear(int cpu) { }
616 #endif /* CONFIG_KEXEC_CORE */
618 static void __loaded_vmcs_clear(void *arg)
620 struct loaded_vmcs *loaded_vmcs = arg;
621 int cpu = raw_smp_processor_id();
623 if (loaded_vmcs->cpu != cpu)
624 return; /* vcpu migration can race with cpu offline */
625 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
626 per_cpu(current_vmcs, cpu) = NULL;
627 crash_disable_local_vmclear(cpu);
628 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
631 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
632 * is before setting loaded_vmcs->vcpu to -1 which is done in
633 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
634 * then adds the vmcs into percpu list before it is deleted.
638 loaded_vmcs_init(loaded_vmcs);
639 crash_enable_local_vmclear(cpu);
642 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
644 int cpu = loaded_vmcs->cpu;
647 smp_call_function_single(cpu,
648 __loaded_vmcs_clear, loaded_vmcs, 1);
651 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
655 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
657 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
658 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
659 vmx->segment_cache.bitmask = 0;
661 ret = vmx->segment_cache.bitmask & mask;
662 vmx->segment_cache.bitmask |= mask;
666 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
668 u16 *p = &vmx->segment_cache.seg[seg].selector;
670 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
671 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
675 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
677 ulong *p = &vmx->segment_cache.seg[seg].base;
679 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
680 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
684 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
686 u32 *p = &vmx->segment_cache.seg[seg].limit;
688 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
689 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
693 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
695 u32 *p = &vmx->segment_cache.seg[seg].ar;
697 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
698 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
702 void update_exception_bitmap(struct kvm_vcpu *vcpu)
706 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
707 (1u << DB_VECTOR) | (1u << AC_VECTOR);
709 * Guest access to VMware backdoor ports could legitimately
710 * trigger #GP because of TSS I/O permission bitmap.
711 * We intercept those #GP and allow access to them anyway
714 if (enable_vmware_backdoor)
715 eb |= (1u << GP_VECTOR);
716 if ((vcpu->guest_debug &
717 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
718 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
719 eb |= 1u << BP_VECTOR;
720 if (to_vmx(vcpu)->rmode.vm86_active)
723 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
725 /* When we are running a nested L2 guest and L1 specified for it a
726 * certain exception bitmap, we must trap the same exceptions and pass
727 * them to L1. When running L2, we will only handle the exceptions
728 * specified above if L1 did not want them.
730 if (is_guest_mode(vcpu))
731 eb |= get_vmcs12(vcpu)->exception_bitmap;
733 vmcs_write32(EXCEPTION_BITMAP, eb);
737 * Check if MSR is intercepted for currently loaded MSR bitmap.
739 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
741 unsigned long *msr_bitmap;
742 int f = sizeof(unsigned long);
744 if (!cpu_has_vmx_msr_bitmap())
747 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
750 return !!test_bit(msr, msr_bitmap + 0x800 / f);
751 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
753 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
759 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
760 unsigned long entry, unsigned long exit)
762 vm_entry_controls_clearbit(vmx, entry);
763 vm_exit_controls_clearbit(vmx, exit);
766 static int find_msr(struct vmx_msrs *m, unsigned int msr)
770 for (i = 0; i < m->nr; ++i) {
771 if (m->val[i].index == msr)
777 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
780 struct msr_autoload *m = &vmx->msr_autoload;
784 if (cpu_has_load_ia32_efer()) {
785 clear_atomic_switch_msr_special(vmx,
786 VM_ENTRY_LOAD_IA32_EFER,
787 VM_EXIT_LOAD_IA32_EFER);
791 case MSR_CORE_PERF_GLOBAL_CTRL:
792 if (cpu_has_load_perf_global_ctrl()) {
793 clear_atomic_switch_msr_special(vmx,
794 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
795 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
800 i = find_msr(&m->guest, msr);
804 m->guest.val[i] = m->guest.val[m->guest.nr];
805 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
808 i = find_msr(&m->host, msr);
813 m->host.val[i] = m->host.val[m->host.nr];
814 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
817 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
818 unsigned long entry, unsigned long exit,
819 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
820 u64 guest_val, u64 host_val)
822 vmcs_write64(guest_val_vmcs, guest_val);
823 if (host_val_vmcs != HOST_IA32_EFER)
824 vmcs_write64(host_val_vmcs, host_val);
825 vm_entry_controls_setbit(vmx, entry);
826 vm_exit_controls_setbit(vmx, exit);
829 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
830 u64 guest_val, u64 host_val, bool entry_only)
833 struct msr_autoload *m = &vmx->msr_autoload;
837 if (cpu_has_load_ia32_efer()) {
838 add_atomic_switch_msr_special(vmx,
839 VM_ENTRY_LOAD_IA32_EFER,
840 VM_EXIT_LOAD_IA32_EFER,
843 guest_val, host_val);
847 case MSR_CORE_PERF_GLOBAL_CTRL:
848 if (cpu_has_load_perf_global_ctrl()) {
849 add_atomic_switch_msr_special(vmx,
850 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
851 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
852 GUEST_IA32_PERF_GLOBAL_CTRL,
853 HOST_IA32_PERF_GLOBAL_CTRL,
854 guest_val, host_val);
858 case MSR_IA32_PEBS_ENABLE:
859 /* PEBS needs a quiescent period after being disabled (to write
860 * a record). Disabling PEBS through VMX MSR swapping doesn't
861 * provide that period, so a CPU could write host's record into
864 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
867 i = find_msr(&m->guest, msr);
869 j = find_msr(&m->host, msr);
871 if ((i < 0 && m->guest.nr == NR_AUTOLOAD_MSRS) ||
872 (j < 0 && m->host.nr == NR_AUTOLOAD_MSRS)) {
873 printk_once(KERN_WARNING "Not enough msr switch entries. "
874 "Can't add msr %x\n", msr);
879 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
881 m->guest.val[i].index = msr;
882 m->guest.val[i].value = guest_val;
889 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
891 m->host.val[j].index = msr;
892 m->host.val[j].value = host_val;
895 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
897 u64 guest_efer = vmx->vcpu.arch.efer;
902 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
903 * host CPUID is more efficient than testing guest CPUID
904 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
906 if (boot_cpu_has(X86_FEATURE_SMEP))
907 guest_efer |= EFER_NX;
908 else if (!(guest_efer & EFER_NX))
909 ignore_bits |= EFER_NX;
913 * LMA and LME handled by hardware; SCE meaningless outside long mode.
915 ignore_bits |= EFER_SCE;
917 ignore_bits |= EFER_LMA | EFER_LME;
918 /* SCE is meaningful only in long mode on Intel */
919 if (guest_efer & EFER_LMA)
920 ignore_bits &= ~(u64)EFER_SCE;
924 * On EPT, we can't emulate NX, so we must switch EFER atomically.
925 * On CPUs that support "load IA32_EFER", always switch EFER
926 * atomically, since it's faster than switching it manually.
928 if (cpu_has_load_ia32_efer() ||
929 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
930 if (!(guest_efer & EFER_LMA))
931 guest_efer &= ~EFER_LME;
932 if (guest_efer != host_efer)
933 add_atomic_switch_msr(vmx, MSR_EFER,
934 guest_efer, host_efer, false);
936 clear_atomic_switch_msr(vmx, MSR_EFER);
939 clear_atomic_switch_msr(vmx, MSR_EFER);
941 guest_efer &= ~ignore_bits;
942 guest_efer |= host_efer & ignore_bits;
944 vmx->guest_msrs[efer_offset].data = guest_efer;
945 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
953 * On 32-bit kernels, VM exits still load the FS and GS bases from the
954 * VMCS rather than the segment table. KVM uses this helper to figure
955 * out the current bases to poke them into the VMCS before entry.
957 static unsigned long segment_base(u16 selector)
959 struct desc_struct *table;
962 if (!(selector & ~SEGMENT_RPL_MASK))
965 table = get_current_gdt_ro();
967 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
968 u16 ldt_selector = kvm_read_ldt();
970 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
973 table = (struct desc_struct *)segment_base(ldt_selector);
975 v = get_desc_base(&table[selector >> 3]);
980 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
984 wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
985 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
986 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
987 wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
988 for (i = 0; i < addr_range; i++) {
989 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
990 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
994 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
998 rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
999 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1000 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1001 rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1002 for (i = 0; i < addr_range; i++) {
1003 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1004 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1008 static void pt_guest_enter(struct vcpu_vmx *vmx)
1010 if (pt_mode == PT_MODE_SYSTEM)
1014 * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1015 * Save host state before VM entry.
1017 rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1018 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1019 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1020 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1021 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1025 static void pt_guest_exit(struct vcpu_vmx *vmx)
1027 if (pt_mode == PT_MODE_SYSTEM)
1030 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1031 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1032 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1035 /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1036 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1039 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1040 unsigned long fs_base, unsigned long gs_base)
1042 if (unlikely(fs_sel != host->fs_sel)) {
1044 vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1046 vmcs_write16(HOST_FS_SELECTOR, 0);
1047 host->fs_sel = fs_sel;
1049 if (unlikely(gs_sel != host->gs_sel)) {
1051 vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1053 vmcs_write16(HOST_GS_SELECTOR, 0);
1054 host->gs_sel = gs_sel;
1056 if (unlikely(fs_base != host->fs_base)) {
1057 vmcs_writel(HOST_FS_BASE, fs_base);
1058 host->fs_base = fs_base;
1060 if (unlikely(gs_base != host->gs_base)) {
1061 vmcs_writel(HOST_GS_BASE, gs_base);
1062 host->gs_base = gs_base;
1066 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1068 struct vcpu_vmx *vmx = to_vmx(vcpu);
1069 struct vmcs_host_state *host_state;
1070 #ifdef CONFIG_X86_64
1071 int cpu = raw_smp_processor_id();
1073 unsigned long fs_base, gs_base;
1077 vmx->req_immediate_exit = false;
1080 * Note that guest MSRs to be saved/restored can also be changed
1081 * when guest state is loaded. This happens when guest transitions
1082 * to/from long-mode by setting MSR_EFER.LMA.
1084 if (!vmx->guest_msrs_ready) {
1085 vmx->guest_msrs_ready = true;
1086 for (i = 0; i < vmx->save_nmsrs; ++i)
1087 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1088 vmx->guest_msrs[i].data,
1089 vmx->guest_msrs[i].mask);
1092 if (vmx->guest_state_loaded)
1095 host_state = &vmx->loaded_vmcs->host_state;
1098 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1099 * allow segment selectors with cpl > 0 or ti == 1.
1101 host_state->ldt_sel = kvm_read_ldt();
1103 #ifdef CONFIG_X86_64
1104 savesegment(ds, host_state->ds_sel);
1105 savesegment(es, host_state->es_sel);
1107 gs_base = cpu_kernelmode_gs_base(cpu);
1108 if (likely(is_64bit_mm(current->mm))) {
1109 save_fsgs_for_kvm();
1110 fs_sel = current->thread.fsindex;
1111 gs_sel = current->thread.gsindex;
1112 fs_base = current->thread.fsbase;
1113 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
1115 savesegment(fs, fs_sel);
1116 savesegment(gs, gs_sel);
1117 fs_base = read_msr(MSR_FS_BASE);
1118 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
1121 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1123 savesegment(fs, fs_sel);
1124 savesegment(gs, gs_sel);
1125 fs_base = segment_base(fs_sel);
1126 gs_base = segment_base(gs_sel);
1129 vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
1130 vmx->guest_state_loaded = true;
1133 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
1135 struct vmcs_host_state *host_state;
1137 if (!vmx->guest_state_loaded)
1140 host_state = &vmx->loaded_vmcs->host_state;
1142 ++vmx->vcpu.stat.host_state_reload;
1144 #ifdef CONFIG_X86_64
1145 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1147 if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1148 kvm_load_ldt(host_state->ldt_sel);
1149 #ifdef CONFIG_X86_64
1150 load_gs_index(host_state->gs_sel);
1152 loadsegment(gs, host_state->gs_sel);
1155 if (host_state->fs_sel & 7)
1156 loadsegment(fs, host_state->fs_sel);
1157 #ifdef CONFIG_X86_64
1158 if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1159 loadsegment(ds, host_state->ds_sel);
1160 loadsegment(es, host_state->es_sel);
1163 invalidate_tss_limit();
1164 #ifdef CONFIG_X86_64
1165 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1167 load_fixmap_gdt(raw_smp_processor_id());
1168 vmx->guest_state_loaded = false;
1169 vmx->guest_msrs_ready = false;
1172 #ifdef CONFIG_X86_64
1173 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
1176 if (vmx->guest_state_loaded)
1177 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1179 return vmx->msr_guest_kernel_gs_base;
1182 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1185 if (vmx->guest_state_loaded)
1186 wrmsrl(MSR_KERNEL_GS_BASE, data);
1188 vmx->msr_guest_kernel_gs_base = data;
1192 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1194 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1195 struct pi_desc old, new;
1199 * In case of hot-plug or hot-unplug, we may have to undo
1200 * vmx_vcpu_pi_put even if there is no assigned device. And we
1201 * always keep PI.NDST up to date for simplicity: it makes the
1202 * code easier, and CPU migration is not a fast path.
1204 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
1207 /* The full case. */
1209 old.control = new.control = pi_desc->control;
1211 dest = cpu_physical_id(cpu);
1213 if (x2apic_enabled())
1216 new.ndst = (dest << 8) & 0xFF00;
1219 } while (cmpxchg64(&pi_desc->control, old.control,
1220 new.control) != old.control);
1223 * Clear SN before reading the bitmap. The VT-d firmware
1224 * writes the bitmap and reads SN atomically (5.2.3 in the
1225 * spec), so it doesn't really have a memory barrier that
1226 * pairs with this, but we cannot do that and we need one.
1228 smp_mb__after_atomic();
1230 if (!bitmap_empty((unsigned long *)pi_desc->pir, NR_VECTORS))
1234 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu)
1236 struct vcpu_vmx *vmx = to_vmx(vcpu);
1237 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
1239 if (!already_loaded) {
1240 loaded_vmcs_clear(vmx->loaded_vmcs);
1241 local_irq_disable();
1242 crash_disable_local_vmclear(cpu);
1245 * Read loaded_vmcs->cpu should be before fetching
1246 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1247 * See the comments in __loaded_vmcs_clear().
1251 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1252 &per_cpu(loaded_vmcss_on_cpu, cpu));
1253 crash_enable_local_vmclear(cpu);
1257 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1258 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1259 vmcs_load(vmx->loaded_vmcs->vmcs);
1260 indirect_branch_prediction_barrier();
1263 if (!already_loaded) {
1264 void *gdt = get_current_gdt_ro();
1265 unsigned long sysenter_esp;
1267 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1270 * Linux uses per-cpu TSS and GDT, so set these when switching
1271 * processors. See 22.2.4.
1273 vmcs_writel(HOST_TR_BASE,
1274 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
1275 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
1278 * VM exits change the host TR limit to 0x67 after a VM
1279 * exit. This is okay, since 0x67 covers everything except
1280 * the IO bitmap and have have code to handle the IO bitmap
1281 * being lost after a VM exit.
1283 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
1285 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1286 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1288 vmx->loaded_vmcs->cpu = cpu;
1291 /* Setup TSC multiplier */
1292 if (kvm_has_tsc_control &&
1293 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
1294 decache_tsc_multiplier(vmx);
1298 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1299 * vcpu mutex is already taken.
1301 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1303 struct vcpu_vmx *vmx = to_vmx(vcpu);
1305 vmx_vcpu_load_vmcs(vcpu, cpu);
1307 vmx_vcpu_pi_load(vcpu, cpu);
1309 vmx->host_pkru = read_pkru();
1310 vmx->host_debugctlmsr = get_debugctlmsr();
1313 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
1315 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1317 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1318 !irq_remapping_cap(IRQ_POSTING_CAP) ||
1319 !kvm_vcpu_apicv_active(vcpu))
1322 /* Set SN when the vCPU is preempted */
1323 if (vcpu->preempted)
1327 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1329 vmx_vcpu_pi_put(vcpu);
1331 vmx_prepare_switch_to_host(to_vmx(vcpu));
1334 static bool emulation_required(struct kvm_vcpu *vcpu)
1336 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
1339 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1341 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1343 unsigned long rflags, save_rflags;
1345 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1346 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1347 rflags = vmcs_readl(GUEST_RFLAGS);
1348 if (to_vmx(vcpu)->rmode.vm86_active) {
1349 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1350 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1351 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1353 to_vmx(vcpu)->rflags = rflags;
1355 return to_vmx(vcpu)->rflags;
1358 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1360 unsigned long old_rflags = vmx_get_rflags(vcpu);
1362 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1363 to_vmx(vcpu)->rflags = rflags;
1364 if (to_vmx(vcpu)->rmode.vm86_active) {
1365 to_vmx(vcpu)->rmode.save_rflags = rflags;
1366 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1368 vmcs_writel(GUEST_RFLAGS, rflags);
1370 if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
1371 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
1374 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1376 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1379 if (interruptibility & GUEST_INTR_STATE_STI)
1380 ret |= KVM_X86_SHADOW_INT_STI;
1381 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1382 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1387 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1389 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1390 u32 interruptibility = interruptibility_old;
1392 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1394 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1395 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1396 else if (mask & KVM_X86_SHADOW_INT_STI)
1397 interruptibility |= GUEST_INTR_STATE_STI;
1399 if ((interruptibility != interruptibility_old))
1400 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1403 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1405 struct vcpu_vmx *vmx = to_vmx(vcpu);
1406 unsigned long value;
1409 * Any MSR write that attempts to change bits marked reserved will
1412 if (data & vmx->pt_desc.ctl_bitmask)
1416 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1417 * result in a #GP unless the same write also clears TraceEn.
1419 if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1420 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1424 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1425 * and FabricEn would cause #GP, if
1426 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1428 if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1429 !(data & RTIT_CTL_FABRIC_EN) &&
1430 !intel_pt_validate_cap(vmx->pt_desc.caps,
1431 PT_CAP_single_range_output))
1435 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1436 * utilize encodings marked reserved will casue a #GP fault.
1438 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1439 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1440 !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1441 RTIT_CTL_MTC_RANGE_OFFSET, &value))
1443 value = intel_pt_validate_cap(vmx->pt_desc.caps,
1444 PT_CAP_cycle_thresholds);
1445 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1446 !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1447 RTIT_CTL_CYC_THRESH_OFFSET, &value))
1449 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1450 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1451 !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1452 RTIT_CTL_PSB_FREQ_OFFSET, &value))
1456 * If ADDRx_CFG is reserved or the encodings is >2 will
1457 * cause a #GP fault.
1459 value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1460 if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
1462 value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1463 if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
1465 value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1466 if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
1468 value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1469 if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
1476 * Returns an int to be compatible with SVM implementation (which can fail).
1477 * Do not use directly, use skip_emulated_instruction() instead.
1479 static int __skip_emulated_instruction(struct kvm_vcpu *vcpu)
1483 rip = kvm_rip_read(vcpu);
1484 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1485 kvm_rip_write(vcpu, rip);
1487 /* skipping an emulated instruction also counts */
1488 vmx_set_interrupt_shadow(vcpu, 0);
1490 return EMULATE_DONE;
1493 static inline void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1495 (void)__skip_emulated_instruction(vcpu);
1498 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1501 * Ensure that we clear the HLT state in the VMCS. We don't need to
1502 * explicitly skip the instruction because if the HLT state is set,
1503 * then the instruction is already executing and RIP has already been
1506 if (kvm_hlt_in_guest(vcpu->kvm) &&
1507 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1508 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1511 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
1513 struct vcpu_vmx *vmx = to_vmx(vcpu);
1514 unsigned nr = vcpu->arch.exception.nr;
1515 bool has_error_code = vcpu->arch.exception.has_error_code;
1516 u32 error_code = vcpu->arch.exception.error_code;
1517 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1519 kvm_deliver_exception_payload(vcpu);
1521 if (has_error_code) {
1522 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1523 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1526 if (vmx->rmode.vm86_active) {
1528 if (kvm_exception_is_soft(nr))
1529 inc_eip = vcpu->arch.event_exit_inst_len;
1530 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1531 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1535 WARN_ON_ONCE(vmx->emulation_required);
1537 if (kvm_exception_is_soft(nr)) {
1538 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1539 vmx->vcpu.arch.event_exit_inst_len);
1540 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1542 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1544 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1546 vmx_clear_hlt(vcpu);
1549 static bool vmx_rdtscp_supported(void)
1551 return cpu_has_vmx_rdtscp();
1554 static bool vmx_invpcid_supported(void)
1556 return cpu_has_vmx_invpcid();
1560 * Swap MSR entry in host/guest MSR entry array.
1562 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1564 struct shared_msr_entry tmp;
1566 tmp = vmx->guest_msrs[to];
1567 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1568 vmx->guest_msrs[from] = tmp;
1572 * Set up the vmcs to automatically save and restore system
1573 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1574 * mode, as fiddling with msrs is very expensive.
1576 static void setup_msrs(struct vcpu_vmx *vmx)
1578 int save_nmsrs, index;
1581 #ifdef CONFIG_X86_64
1583 * The SYSCALL MSRs are only needed on long mode guests, and only
1584 * when EFER.SCE is set.
1586 if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) {
1587 index = __find_msr_index(vmx, MSR_STAR);
1589 move_msr_up(vmx, index, save_nmsrs++);
1590 index = __find_msr_index(vmx, MSR_LSTAR);
1592 move_msr_up(vmx, index, save_nmsrs++);
1593 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1595 move_msr_up(vmx, index, save_nmsrs++);
1598 index = __find_msr_index(vmx, MSR_EFER);
1599 if (index >= 0 && update_transition_efer(vmx, index))
1600 move_msr_up(vmx, index, save_nmsrs++);
1601 index = __find_msr_index(vmx, MSR_TSC_AUX);
1602 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
1603 move_msr_up(vmx, index, save_nmsrs++);
1605 vmx->save_nmsrs = save_nmsrs;
1606 vmx->guest_msrs_ready = false;
1608 if (cpu_has_vmx_msr_bitmap())
1609 vmx_update_msr_bitmap(&vmx->vcpu);
1612 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1614 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1616 if (is_guest_mode(vcpu) &&
1617 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
1618 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
1620 return vcpu->arch.tsc_offset;
1623 static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1625 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1626 u64 g_tsc_offset = 0;
1629 * We're here if L1 chose not to trap WRMSR to TSC. According
1630 * to the spec, this should set L1's TSC; The offset that L1
1631 * set for L2 remains unchanged, and still needs to be added
1632 * to the newly set TSC to get L2's TSC.
1634 if (is_guest_mode(vcpu) &&
1635 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
1636 g_tsc_offset = vmcs12->tsc_offset;
1638 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1639 vcpu->arch.tsc_offset - g_tsc_offset,
1641 vmcs_write64(TSC_OFFSET, offset + g_tsc_offset);
1642 return offset + g_tsc_offset;
1646 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1647 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1648 * all guests if the "nested" module option is off, and can also be disabled
1649 * for a single guest by disabling its VMX cpuid bit.
1651 bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1653 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
1656 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1659 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
1661 return !(val & ~valid_bits);
1664 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
1666 switch (msr->index) {
1667 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1670 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1679 * Reads an msr value (of 'msr_index') into 'pdata'.
1680 * Returns 0 on success, non-0 otherwise.
1681 * Assumes vcpu_load() was already called.
1683 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1685 struct vcpu_vmx *vmx = to_vmx(vcpu);
1686 struct shared_msr_entry *msr;
1689 switch (msr_info->index) {
1690 #ifdef CONFIG_X86_64
1692 msr_info->data = vmcs_readl(GUEST_FS_BASE);
1695 msr_info->data = vmcs_readl(GUEST_GS_BASE);
1697 case MSR_KERNEL_GS_BASE:
1698 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
1702 return kvm_get_msr_common(vcpu, msr_info);
1703 case MSR_IA32_SPEC_CTRL:
1704 if (!msr_info->host_initiated &&
1705 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1708 msr_info->data = to_vmx(vcpu)->spec_ctrl;
1710 case MSR_IA32_SYSENTER_CS:
1711 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
1713 case MSR_IA32_SYSENTER_EIP:
1714 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
1716 case MSR_IA32_SYSENTER_ESP:
1717 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
1719 case MSR_IA32_BNDCFGS:
1720 if (!kvm_mpx_supported() ||
1721 (!msr_info->host_initiated &&
1722 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1724 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
1726 case MSR_IA32_MCG_EXT_CTL:
1727 if (!msr_info->host_initiated &&
1728 !(vmx->msr_ia32_feature_control &
1729 FEATURE_CONTROL_LMCE))
1731 msr_info->data = vcpu->arch.mcg_ext_ctl;
1733 case MSR_IA32_FEATURE_CONTROL:
1734 msr_info->data = vmx->msr_ia32_feature_control;
1736 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1737 if (!nested_vmx_allowed(vcpu))
1739 return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1742 if (!vmx_xsaves_supported() ||
1743 (!msr_info->host_initiated &&
1744 !(guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
1745 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))))
1747 msr_info->data = vcpu->arch.ia32_xss;
1749 case MSR_IA32_RTIT_CTL:
1750 if (pt_mode != PT_MODE_HOST_GUEST)
1752 msr_info->data = vmx->pt_desc.guest.ctl;
1754 case MSR_IA32_RTIT_STATUS:
1755 if (pt_mode != PT_MODE_HOST_GUEST)
1757 msr_info->data = vmx->pt_desc.guest.status;
1759 case MSR_IA32_RTIT_CR3_MATCH:
1760 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1761 !intel_pt_validate_cap(vmx->pt_desc.caps,
1762 PT_CAP_cr3_filtering))
1764 msr_info->data = vmx->pt_desc.guest.cr3_match;
1766 case MSR_IA32_RTIT_OUTPUT_BASE:
1767 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1768 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1769 PT_CAP_topa_output) &&
1770 !intel_pt_validate_cap(vmx->pt_desc.caps,
1771 PT_CAP_single_range_output)))
1773 msr_info->data = vmx->pt_desc.guest.output_base;
1775 case MSR_IA32_RTIT_OUTPUT_MASK:
1776 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1777 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1778 PT_CAP_topa_output) &&
1779 !intel_pt_validate_cap(vmx->pt_desc.caps,
1780 PT_CAP_single_range_output)))
1782 msr_info->data = vmx->pt_desc.guest.output_mask;
1784 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1785 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1786 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1787 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
1788 PT_CAP_num_address_ranges)))
1791 msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1793 msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1796 if (!msr_info->host_initiated &&
1797 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
1799 /* Else, falls through */
1801 msr = find_msr_entry(vmx, msr_info->index);
1803 msr_info->data = msr->data;
1806 return kvm_get_msr_common(vcpu, msr_info);
1813 * Writes msr value into into the appropriate "register".
1814 * Returns 0 on success, non-0 otherwise.
1815 * Assumes vcpu_load() was already called.
1817 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1819 struct vcpu_vmx *vmx = to_vmx(vcpu);
1820 struct shared_msr_entry *msr;
1822 u32 msr_index = msr_info->index;
1823 u64 data = msr_info->data;
1826 switch (msr_index) {
1828 ret = kvm_set_msr_common(vcpu, msr_info);
1830 #ifdef CONFIG_X86_64
1832 vmx_segment_cache_clear(vmx);
1833 vmcs_writel(GUEST_FS_BASE, data);
1836 vmx_segment_cache_clear(vmx);
1837 vmcs_writel(GUEST_GS_BASE, data);
1839 case MSR_KERNEL_GS_BASE:
1840 vmx_write_guest_kernel_gs_base(vmx, data);
1843 case MSR_IA32_SYSENTER_CS:
1844 if (is_guest_mode(vcpu))
1845 get_vmcs12(vcpu)->guest_sysenter_cs = data;
1846 vmcs_write32(GUEST_SYSENTER_CS, data);
1848 case MSR_IA32_SYSENTER_EIP:
1849 if (is_guest_mode(vcpu))
1850 get_vmcs12(vcpu)->guest_sysenter_eip = data;
1851 vmcs_writel(GUEST_SYSENTER_EIP, data);
1853 case MSR_IA32_SYSENTER_ESP:
1854 if (is_guest_mode(vcpu))
1855 get_vmcs12(vcpu)->guest_sysenter_esp = data;
1856 vmcs_writel(GUEST_SYSENTER_ESP, data);
1858 case MSR_IA32_DEBUGCTLMSR:
1859 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
1860 VM_EXIT_SAVE_DEBUG_CONTROLS)
1861 get_vmcs12(vcpu)->guest_ia32_debugctl = data;
1863 ret = kvm_set_msr_common(vcpu, msr_info);
1866 case MSR_IA32_BNDCFGS:
1867 if (!kvm_mpx_supported() ||
1868 (!msr_info->host_initiated &&
1869 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1871 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
1872 (data & MSR_IA32_BNDCFGS_RSVD))
1874 vmcs_write64(GUEST_BNDCFGS, data);
1876 case MSR_IA32_SPEC_CTRL:
1877 if (!msr_info->host_initiated &&
1878 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1881 /* The STIBP bit doesn't fault even if it's not advertised */
1882 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
1885 vmx->spec_ctrl = data;
1892 * When it's written (to non-zero) for the first time, pass
1896 * The handling of the MSR bitmap for L2 guests is done in
1897 * nested_vmx_merge_msr_bitmap. We should not touch the
1898 * vmcs02.msr_bitmap here since it gets completely overwritten
1899 * in the merging. We update the vmcs01 here for L1 as well
1900 * since it will end up touching the MSR anyway now.
1902 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
1906 case MSR_IA32_PRED_CMD:
1907 if (!msr_info->host_initiated &&
1908 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1911 if (data & ~PRED_CMD_IBPB)
1917 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
1921 * When it's written (to non-zero) for the first time, pass
1925 * The handling of the MSR bitmap for L2 guests is done in
1926 * nested_vmx_merge_msr_bitmap. We should not touch the
1927 * vmcs02.msr_bitmap here since it gets completely overwritten
1930 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
1933 case MSR_IA32_CR_PAT:
1934 if (!kvm_pat_valid(data))
1937 if (is_guest_mode(vcpu) &&
1938 get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
1939 get_vmcs12(vcpu)->guest_ia32_pat = data;
1941 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1942 vmcs_write64(GUEST_IA32_PAT, data);
1943 vcpu->arch.pat = data;
1946 ret = kvm_set_msr_common(vcpu, msr_info);
1948 case MSR_IA32_TSC_ADJUST:
1949 ret = kvm_set_msr_common(vcpu, msr_info);
1951 case MSR_IA32_MCG_EXT_CTL:
1952 if ((!msr_info->host_initiated &&
1953 !(to_vmx(vcpu)->msr_ia32_feature_control &
1954 FEATURE_CONTROL_LMCE)) ||
1955 (data & ~MCG_EXT_CTL_LMCE_EN))
1957 vcpu->arch.mcg_ext_ctl = data;
1959 case MSR_IA32_FEATURE_CONTROL:
1960 if (!vmx_feature_control_msr_valid(vcpu, data) ||
1961 (to_vmx(vcpu)->msr_ia32_feature_control &
1962 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
1964 vmx->msr_ia32_feature_control = data;
1965 if (msr_info->host_initiated && data == 0)
1966 vmx_leave_nested(vcpu);
1968 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1969 if (!msr_info->host_initiated)
1970 return 1; /* they are read-only */
1971 if (!nested_vmx_allowed(vcpu))
1973 return vmx_set_vmx_msr(vcpu, msr_index, data);
1975 if (!vmx_xsaves_supported() ||
1976 (!msr_info->host_initiated &&
1977 !(guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
1978 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))))
1981 * The only supported bit as of Skylake is bit 8, but
1982 * it is not supported on KVM.
1986 vcpu->arch.ia32_xss = data;
1987 if (vcpu->arch.ia32_xss != host_xss)
1988 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
1989 vcpu->arch.ia32_xss, host_xss, false);
1991 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
1993 case MSR_IA32_RTIT_CTL:
1994 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1995 vmx_rtit_ctl_check(vcpu, data) ||
1998 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
1999 vmx->pt_desc.guest.ctl = data;
2000 pt_update_intercept_for_msr(vmx);
2002 case MSR_IA32_RTIT_STATUS:
2003 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2004 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2005 (data & MSR_IA32_RTIT_STATUS_MASK))
2007 vmx->pt_desc.guest.status = data;
2009 case MSR_IA32_RTIT_CR3_MATCH:
2010 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2011 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2012 !intel_pt_validate_cap(vmx->pt_desc.caps,
2013 PT_CAP_cr3_filtering))
2015 vmx->pt_desc.guest.cr3_match = data;
2017 case MSR_IA32_RTIT_OUTPUT_BASE:
2018 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2019 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2020 (!intel_pt_validate_cap(vmx->pt_desc.caps,
2021 PT_CAP_topa_output) &&
2022 !intel_pt_validate_cap(vmx->pt_desc.caps,
2023 PT_CAP_single_range_output)) ||
2024 (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK))
2026 vmx->pt_desc.guest.output_base = data;
2028 case MSR_IA32_RTIT_OUTPUT_MASK:
2029 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2030 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2031 (!intel_pt_validate_cap(vmx->pt_desc.caps,
2032 PT_CAP_topa_output) &&
2033 !intel_pt_validate_cap(vmx->pt_desc.caps,
2034 PT_CAP_single_range_output)))
2036 vmx->pt_desc.guest.output_mask = data;
2038 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2039 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2040 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2041 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2042 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
2043 PT_CAP_num_address_ranges)))
2046 vmx->pt_desc.guest.addr_b[index / 2] = data;
2048 vmx->pt_desc.guest.addr_a[index / 2] = data;
2051 if (!msr_info->host_initiated &&
2052 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
2054 /* Check reserved bit, higher 32 bits should be zero */
2055 if ((data >> 32) != 0)
2057 /* Else, falls through */
2059 msr = find_msr_entry(vmx, msr_index);
2061 u64 old_msr_data = msr->data;
2063 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2065 ret = kvm_set_shared_msr(msr->index, msr->data,
2069 msr->data = old_msr_data;
2073 ret = kvm_set_msr_common(vcpu, msr_info);
2079 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2081 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2084 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2087 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2089 case VCPU_EXREG_PDPTR:
2091 ept_save_pdptrs(vcpu);
2098 static __init int cpu_has_kvm_support(void)
2100 return cpu_has_vmx();
2103 static __init int vmx_disabled_by_bios(void)
2107 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2108 if (msr & FEATURE_CONTROL_LOCKED) {
2109 /* launched w/ TXT and VMX disabled */
2110 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2113 /* launched w/o TXT and VMX only enabled w/ TXT */
2114 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2115 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2116 && !tboot_enabled()) {
2117 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2118 "activate TXT before enabling KVM\n");
2121 /* launched w/o TXT and VMX disabled */
2122 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2123 && !tboot_enabled())
2130 static void kvm_cpu_vmxon(u64 addr)
2132 cr4_set_bits(X86_CR4_VMXE);
2133 intel_pt_handle_vmx(1);
2135 asm volatile ("vmxon %0" : : "m"(addr));
2138 static int hardware_enable(void)
2140 int cpu = raw_smp_processor_id();
2141 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2144 if (cr4_read_shadow() & X86_CR4_VMXE)
2148 * This can happen if we hot-added a CPU but failed to allocate
2149 * VP assist page for it.
2151 if (static_branch_unlikely(&enable_evmcs) &&
2152 !hv_get_vp_assist_page(cpu))
2155 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2156 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
2157 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
2160 * Now we can enable the vmclear operation in kdump
2161 * since the loaded_vmcss_on_cpu list on this cpu
2162 * has been initialized.
2164 * Though the cpu is not in VMX operation now, there
2165 * is no problem to enable the vmclear operation
2166 * for the loaded_vmcss_on_cpu list is empty!
2168 crash_enable_local_vmclear(cpu);
2170 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2172 test_bits = FEATURE_CONTROL_LOCKED;
2173 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2174 if (tboot_enabled())
2175 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2177 if ((old & test_bits) != test_bits) {
2178 /* enable and lock */
2179 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2181 kvm_cpu_vmxon(phys_addr);
2188 static void vmclear_local_loaded_vmcss(void)
2190 int cpu = raw_smp_processor_id();
2191 struct loaded_vmcs *v, *n;
2193 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2194 loaded_vmcss_on_cpu_link)
2195 __loaded_vmcs_clear(v);
2199 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2202 static void kvm_cpu_vmxoff(void)
2204 asm volatile (__ex("vmxoff"));
2206 intel_pt_handle_vmx(0);
2207 cr4_clear_bits(X86_CR4_VMXE);
2210 static void hardware_disable(void)
2212 vmclear_local_loaded_vmcss();
2216 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2217 u32 msr, u32 *result)
2219 u32 vmx_msr_low, vmx_msr_high;
2220 u32 ctl = ctl_min | ctl_opt;
2222 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2224 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2225 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2227 /* Ensure minimum (required) set of control bits are supported. */
2235 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2236 struct vmx_capability *vmx_cap)
2238 u32 vmx_msr_low, vmx_msr_high;
2239 u32 min, opt, min2, opt2;
2240 u32 _pin_based_exec_control = 0;
2241 u32 _cpu_based_exec_control = 0;
2242 u32 _cpu_based_2nd_exec_control = 0;
2243 u32 _vmexit_control = 0;
2244 u32 _vmentry_control = 0;
2246 memset(vmcs_conf, 0, sizeof(*vmcs_conf));
2247 min = CPU_BASED_HLT_EXITING |
2248 #ifdef CONFIG_X86_64
2249 CPU_BASED_CR8_LOAD_EXITING |
2250 CPU_BASED_CR8_STORE_EXITING |
2252 CPU_BASED_CR3_LOAD_EXITING |
2253 CPU_BASED_CR3_STORE_EXITING |
2254 CPU_BASED_UNCOND_IO_EXITING |
2255 CPU_BASED_MOV_DR_EXITING |
2256 CPU_BASED_USE_TSC_OFFSETING |
2257 CPU_BASED_MWAIT_EXITING |
2258 CPU_BASED_MONITOR_EXITING |
2259 CPU_BASED_INVLPG_EXITING |
2260 CPU_BASED_RDPMC_EXITING;
2262 opt = CPU_BASED_TPR_SHADOW |
2263 CPU_BASED_USE_MSR_BITMAPS |
2264 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2265 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2266 &_cpu_based_exec_control) < 0)
2268 #ifdef CONFIG_X86_64
2269 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2270 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2271 ~CPU_BASED_CR8_STORE_EXITING;
2273 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2275 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2276 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2277 SECONDARY_EXEC_WBINVD_EXITING |
2278 SECONDARY_EXEC_ENABLE_VPID |
2279 SECONDARY_EXEC_ENABLE_EPT |
2280 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2281 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2282 SECONDARY_EXEC_DESC |
2283 SECONDARY_EXEC_RDTSCP |
2284 SECONDARY_EXEC_ENABLE_INVPCID |
2285 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2286 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2287 SECONDARY_EXEC_SHADOW_VMCS |
2288 SECONDARY_EXEC_XSAVES |
2289 SECONDARY_EXEC_RDSEED_EXITING |
2290 SECONDARY_EXEC_RDRAND_EXITING |
2291 SECONDARY_EXEC_ENABLE_PML |
2292 SECONDARY_EXEC_TSC_SCALING |
2293 SECONDARY_EXEC_PT_USE_GPA |
2294 SECONDARY_EXEC_PT_CONCEAL_VMX |
2295 SECONDARY_EXEC_ENABLE_VMFUNC |
2296 SECONDARY_EXEC_ENCLS_EXITING;
2297 if (adjust_vmx_controls(min2, opt2,
2298 MSR_IA32_VMX_PROCBASED_CTLS2,
2299 &_cpu_based_2nd_exec_control) < 0)
2302 #ifndef CONFIG_X86_64
2303 if (!(_cpu_based_2nd_exec_control &
2304 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2305 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2308 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2309 _cpu_based_2nd_exec_control &= ~(
2310 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2311 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2312 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2314 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
2315 &vmx_cap->ept, &vmx_cap->vpid);
2317 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2318 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2320 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2321 CPU_BASED_CR3_STORE_EXITING |
2322 CPU_BASED_INVLPG_EXITING);
2323 } else if (vmx_cap->ept) {
2325 pr_warn_once("EPT CAP should not exist if not support "
2326 "1-setting enable EPT VM-execution control\n");
2328 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
2331 pr_warn_once("VPID CAP should not exist if not support "
2332 "1-setting enable VPID VM-execution control\n");
2335 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
2336 #ifdef CONFIG_X86_64
2337 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2339 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2340 VM_EXIT_LOAD_IA32_PAT |
2341 VM_EXIT_LOAD_IA32_EFER |
2342 VM_EXIT_CLEAR_BNDCFGS |
2343 VM_EXIT_PT_CONCEAL_PIP |
2344 VM_EXIT_CLEAR_IA32_RTIT_CTL;
2345 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2346 &_vmexit_control) < 0)
2349 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2350 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2351 PIN_BASED_VMX_PREEMPTION_TIMER;
2352 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2353 &_pin_based_exec_control) < 0)
2356 if (cpu_has_broken_vmx_preemption_timer())
2357 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2358 if (!(_cpu_based_2nd_exec_control &
2359 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
2360 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2362 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2363 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2364 VM_ENTRY_LOAD_IA32_PAT |
2365 VM_ENTRY_LOAD_IA32_EFER |
2366 VM_ENTRY_LOAD_BNDCFGS |
2367 VM_ENTRY_PT_CONCEAL_PIP |
2368 VM_ENTRY_LOAD_IA32_RTIT_CTL;
2369 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2370 &_vmentry_control) < 0)
2374 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2375 * can't be used due to an errata where VM Exit may incorrectly clear
2376 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the
2377 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2379 if (boot_cpu_data.x86 == 0x6) {
2380 switch (boot_cpu_data.x86_model) {
2381 case 26: /* AAK155 */
2382 case 30: /* AAP115 */
2383 case 37: /* AAT100 */
2384 case 44: /* BC86,AAY89,BD102 */
2386 _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
2387 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2388 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2389 "does not work properly. Using workaround\n");
2397 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2399 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2400 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2403 #ifdef CONFIG_X86_64
2404 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2405 if (vmx_msr_high & (1u<<16))
2409 /* Require Write-Back (WB) memory type for VMCS accesses. */
2410 if (((vmx_msr_high >> 18) & 15) != 6)
2413 vmcs_conf->size = vmx_msr_high & 0x1fff;
2414 vmcs_conf->order = get_order(vmcs_conf->size);
2415 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
2417 vmcs_conf->revision_id = vmx_msr_low;
2419 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2420 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2421 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2422 vmcs_conf->vmexit_ctrl = _vmexit_control;
2423 vmcs_conf->vmentry_ctrl = _vmentry_control;
2425 if (static_branch_unlikely(&enable_evmcs))
2426 evmcs_sanitize_exec_ctrls(vmcs_conf);
2431 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
2433 int node = cpu_to_node(cpu);
2437 pages = __alloc_pages_node(node, flags, vmcs_config.order);
2440 vmcs = page_address(pages);
2441 memset(vmcs, 0, vmcs_config.size);
2443 /* KVM supports Enlightened VMCS v1 only */
2444 if (static_branch_unlikely(&enable_evmcs))
2445 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2447 vmcs->hdr.revision_id = vmcs_config.revision_id;
2450 vmcs->hdr.shadow_vmcs = 1;
2454 void free_vmcs(struct vmcs *vmcs)
2456 free_pages((unsigned long)vmcs, vmcs_config.order);
2460 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2462 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2464 if (!loaded_vmcs->vmcs)
2466 loaded_vmcs_clear(loaded_vmcs);
2467 free_vmcs(loaded_vmcs->vmcs);
2468 loaded_vmcs->vmcs = NULL;
2469 if (loaded_vmcs->msr_bitmap)
2470 free_page((unsigned long)loaded_vmcs->msr_bitmap);
2471 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
2474 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2476 loaded_vmcs->vmcs = alloc_vmcs(false);
2477 if (!loaded_vmcs->vmcs)
2480 loaded_vmcs->shadow_vmcs = NULL;
2481 loaded_vmcs->hv_timer_soft_disabled = false;
2482 loaded_vmcs_init(loaded_vmcs);
2484 if (cpu_has_vmx_msr_bitmap()) {
2485 loaded_vmcs->msr_bitmap = (unsigned long *)
2486 __get_free_page(GFP_KERNEL_ACCOUNT);
2487 if (!loaded_vmcs->msr_bitmap)
2489 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
2491 if (IS_ENABLED(CONFIG_HYPERV) &&
2492 static_branch_unlikely(&enable_evmcs) &&
2493 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2494 struct hv_enlightened_vmcs *evmcs =
2495 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2497 evmcs->hv_enlightenments_control.msr_bitmap = 1;
2501 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2502 memset(&loaded_vmcs->controls_shadow, 0,
2503 sizeof(struct vmcs_controls_shadow));
2508 free_loaded_vmcs(loaded_vmcs);
2512 static void free_kvm_area(void)
2516 for_each_possible_cpu(cpu) {
2517 free_vmcs(per_cpu(vmxarea, cpu));
2518 per_cpu(vmxarea, cpu) = NULL;
2522 static __init int alloc_kvm_area(void)
2526 for_each_possible_cpu(cpu) {
2529 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
2536 * When eVMCS is enabled, alloc_vmcs_cpu() sets
2537 * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2538 * revision_id reported by MSR_IA32_VMX_BASIC.
2540 * However, even though not explicitly documented by
2541 * TLFS, VMXArea passed as VMXON argument should
2542 * still be marked with revision_id reported by
2545 if (static_branch_unlikely(&enable_evmcs))
2546 vmcs->hdr.revision_id = vmcs_config.revision_id;
2548 per_cpu(vmxarea, cpu) = vmcs;
2553 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2554 struct kvm_segment *save)
2556 if (!emulate_invalid_guest_state) {
2558 * CS and SS RPL should be equal during guest entry according
2559 * to VMX spec, but in reality it is not always so. Since vcpu
2560 * is in the middle of the transition from real mode to
2561 * protected mode it is safe to assume that RPL 0 is a good
2564 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2565 save->selector &= ~SEGMENT_RPL_MASK;
2566 save->dpl = save->selector & SEGMENT_RPL_MASK;
2569 vmx_set_segment(vcpu, save, seg);
2572 static void enter_pmode(struct kvm_vcpu *vcpu)
2574 unsigned long flags;
2575 struct vcpu_vmx *vmx = to_vmx(vcpu);
2578 * Update real mode segment cache. It may be not up-to-date if sement
2579 * register was written while vcpu was in a guest mode.
2581 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2582 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2583 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2584 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2585 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2586 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2588 vmx->rmode.vm86_active = 0;
2590 vmx_segment_cache_clear(vmx);
2592 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2594 flags = vmcs_readl(GUEST_RFLAGS);
2595 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2596 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2597 vmcs_writel(GUEST_RFLAGS, flags);
2599 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2600 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2602 update_exception_bitmap(vcpu);
2604 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2605 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2606 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2607 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2608 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2609 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2612 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2614 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2615 struct kvm_segment var = *save;
2618 if (seg == VCPU_SREG_CS)
2621 if (!emulate_invalid_guest_state) {
2622 var.selector = var.base >> 4;
2623 var.base = var.base & 0xffff0;
2633 if (save->base & 0xf)
2634 printk_once(KERN_WARNING "kvm: segment base is not "
2635 "paragraph aligned when entering "
2636 "protected mode (seg=%d)", seg);
2639 vmcs_write16(sf->selector, var.selector);
2640 vmcs_writel(sf->base, var.base);
2641 vmcs_write32(sf->limit, var.limit);
2642 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2645 static void enter_rmode(struct kvm_vcpu *vcpu)
2647 unsigned long flags;
2648 struct vcpu_vmx *vmx = to_vmx(vcpu);
2649 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
2651 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2652 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2653 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2654 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2655 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2656 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2657 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2659 vmx->rmode.vm86_active = 1;
2662 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2663 * vcpu. Warn the user that an update is overdue.
2665 if (!kvm_vmx->tss_addr)
2666 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2667 "called before entering vcpu\n");
2669 vmx_segment_cache_clear(vmx);
2671 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
2672 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2673 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2675 flags = vmcs_readl(GUEST_RFLAGS);
2676 vmx->rmode.save_rflags = flags;
2678 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2680 vmcs_writel(GUEST_RFLAGS, flags);
2681 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2682 update_exception_bitmap(vcpu);
2684 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2685 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2686 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2687 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2688 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2689 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2691 kvm_mmu_reset_context(vcpu);
2694 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2696 struct vcpu_vmx *vmx = to_vmx(vcpu);
2697 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2702 vcpu->arch.efer = efer;
2703 if (efer & EFER_LMA) {
2704 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2707 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2709 msr->data = efer & ~EFER_LME;
2714 #ifdef CONFIG_X86_64
2716 static void enter_lmode(struct kvm_vcpu *vcpu)
2720 vmx_segment_cache_clear(to_vmx(vcpu));
2722 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2723 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
2724 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2726 vmcs_write32(GUEST_TR_AR_BYTES,
2727 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2728 | VMX_AR_TYPE_BUSY_64_TSS);
2730 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2733 static void exit_lmode(struct kvm_vcpu *vcpu)
2735 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2736 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2741 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2743 int vpid = to_vmx(vcpu)->vpid;
2745 if (!vpid_sync_vcpu_addr(vpid, addr))
2746 vpid_sync_context(vpid);
2749 * If VPIDs are not supported or enabled, then the above is a no-op.
2750 * But we don't really need a TLB flush in that case anyway, because
2751 * each VM entry/exit includes an implicit flush when VPID is 0.
2755 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2757 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2759 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2760 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2763 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2765 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
2766 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2767 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2770 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2772 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2774 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2775 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2778 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2780 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2782 if (!test_bit(VCPU_EXREG_PDPTR,
2783 (unsigned long *)&vcpu->arch.regs_dirty))
2786 if (is_pae_paging(vcpu)) {
2787 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2788 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2789 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2790 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
2794 void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2796 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2798 if (is_pae_paging(vcpu)) {
2799 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2800 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2801 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2802 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2805 __set_bit(VCPU_EXREG_PDPTR,
2806 (unsigned long *)&vcpu->arch.regs_avail);
2807 __set_bit(VCPU_EXREG_PDPTR,
2808 (unsigned long *)&vcpu->arch.regs_dirty);
2811 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2813 struct kvm_vcpu *vcpu)
2815 struct vcpu_vmx *vmx = to_vmx(vcpu);
2817 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2818 vmx_decache_cr3(vcpu);
2819 if (!(cr0 & X86_CR0_PG)) {
2820 /* From paging/starting to nonpaging */
2821 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2822 CPU_BASED_CR3_STORE_EXITING);
2823 vcpu->arch.cr0 = cr0;
2824 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2825 } else if (!is_paging(vcpu)) {
2826 /* From nonpaging to paging */
2827 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2828 CPU_BASED_CR3_STORE_EXITING);
2829 vcpu->arch.cr0 = cr0;
2830 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2833 if (!(cr0 & X86_CR0_WP))
2834 *hw_cr0 &= ~X86_CR0_WP;
2837 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2839 struct vcpu_vmx *vmx = to_vmx(vcpu);
2840 unsigned long hw_cr0;
2842 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
2843 if (enable_unrestricted_guest)
2844 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2846 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
2848 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2851 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2855 #ifdef CONFIG_X86_64
2856 if (vcpu->arch.efer & EFER_LME) {
2857 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2859 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2864 if (enable_ept && !enable_unrestricted_guest)
2865 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2867 vmcs_writel(CR0_READ_SHADOW, cr0);
2868 vmcs_writel(GUEST_CR0, hw_cr0);
2869 vcpu->arch.cr0 = cr0;
2871 /* depends on vcpu->arch.cr0 to be set to a new value */
2872 vmx->emulation_required = emulation_required(vcpu);
2875 static int get_ept_level(struct kvm_vcpu *vcpu)
2877 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
2882 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
2884 u64 eptp = VMX_EPTP_MT_WB;
2886 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
2888 if (enable_ept_ad_bits &&
2889 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
2890 eptp |= VMX_EPTP_AD_ENABLE_BIT;
2891 eptp |= (root_hpa & PAGE_MASK);
2896 void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2898 struct kvm *kvm = vcpu->kvm;
2899 unsigned long guest_cr3;
2904 eptp = construct_eptp(vcpu, cr3);
2905 vmcs_write64(EPT_POINTER, eptp);
2907 if (kvm_x86_ops->tlb_remote_flush) {
2908 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
2909 to_vmx(vcpu)->ept_pointer = eptp;
2910 to_kvm_vmx(kvm)->ept_pointers_match
2911 = EPT_POINTERS_CHECK;
2912 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
2915 if (enable_unrestricted_guest || is_paging(vcpu) ||
2916 is_guest_mode(vcpu))
2917 guest_cr3 = kvm_read_cr3(vcpu);
2919 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
2920 ept_load_pdptrs(vcpu);
2923 vmcs_writel(GUEST_CR3, guest_cr3);
2926 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2928 struct vcpu_vmx *vmx = to_vmx(vcpu);
2930 * Pass through host's Machine Check Enable value to hw_cr4, which
2931 * is in force while we are in guest mode. Do not let guests control
2932 * this bit, even if host CR4.MCE == 0.
2934 unsigned long hw_cr4;
2936 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
2937 if (enable_unrestricted_guest)
2938 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
2939 else if (vmx->rmode.vm86_active)
2940 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
2942 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
2944 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
2945 if (cr4 & X86_CR4_UMIP) {
2946 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
2947 hw_cr4 &= ~X86_CR4_UMIP;
2948 } else if (!is_guest_mode(vcpu) ||
2949 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
2950 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
2954 if (cr4 & X86_CR4_VMXE) {
2956 * To use VMXON (and later other VMX instructions), a guest
2957 * must first be able to turn on cr4.VMXE (see handle_vmon()).
2958 * So basically the check on whether to allow nested VMX
2959 * is here. We operate under the default treatment of SMM,
2960 * so VMX cannot be enabled under SMM.
2962 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
2966 if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
2969 vcpu->arch.cr4 = cr4;
2971 if (!enable_unrestricted_guest) {
2973 if (!is_paging(vcpu)) {
2974 hw_cr4 &= ~X86_CR4_PAE;
2975 hw_cr4 |= X86_CR4_PSE;
2976 } else if (!(cr4 & X86_CR4_PAE)) {
2977 hw_cr4 &= ~X86_CR4_PAE;
2982 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
2983 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
2984 * to be manually disabled when guest switches to non-paging
2987 * If !enable_unrestricted_guest, the CPU is always running
2988 * with CR0.PG=1 and CR4 needs to be modified.
2989 * If enable_unrestricted_guest, the CPU automatically
2990 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
2992 if (!is_paging(vcpu))
2993 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
2996 vmcs_writel(CR4_READ_SHADOW, cr4);
2997 vmcs_writel(GUEST_CR4, hw_cr4);
3001 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3003 struct vcpu_vmx *vmx = to_vmx(vcpu);
3006 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3007 *var = vmx->rmode.segs[seg];
3008 if (seg == VCPU_SREG_TR
3009 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3011 var->base = vmx_read_guest_seg_base(vmx, seg);
3012 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3015 var->base = vmx_read_guest_seg_base(vmx, seg);
3016 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3017 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3018 ar = vmx_read_guest_seg_ar(vmx, seg);
3019 var->unusable = (ar >> 16) & 1;
3020 var->type = ar & 15;
3021 var->s = (ar >> 4) & 1;
3022 var->dpl = (ar >> 5) & 3;
3024 * Some userspaces do not preserve unusable property. Since usable
3025 * segment has to be present according to VMX spec we can use present
3026 * property to amend userspace bug by making unusable segment always
3027 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3028 * segment as unusable.
3030 var->present = !var->unusable;
3031 var->avl = (ar >> 12) & 1;
3032 var->l = (ar >> 13) & 1;
3033 var->db = (ar >> 14) & 1;
3034 var->g = (ar >> 15) & 1;
3037 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3039 struct kvm_segment s;
3041 if (to_vmx(vcpu)->rmode.vm86_active) {
3042 vmx_get_segment(vcpu, &s, seg);
3045 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3048 int vmx_get_cpl(struct kvm_vcpu *vcpu)
3050 struct vcpu_vmx *vmx = to_vmx(vcpu);
3052 if (unlikely(vmx->rmode.vm86_active))
3055 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3056 return VMX_AR_DPL(ar);
3060 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3064 if (var->unusable || !var->present)
3067 ar = var->type & 15;
3068 ar |= (var->s & 1) << 4;
3069 ar |= (var->dpl & 3) << 5;
3070 ar |= (var->present & 1) << 7;
3071 ar |= (var->avl & 1) << 12;
3072 ar |= (var->l & 1) << 13;
3073 ar |= (var->db & 1) << 14;
3074 ar |= (var->g & 1) << 15;
3080 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3082 struct vcpu_vmx *vmx = to_vmx(vcpu);
3083 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3085 vmx_segment_cache_clear(vmx);
3087 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3088 vmx->rmode.segs[seg] = *var;
3089 if (seg == VCPU_SREG_TR)
3090 vmcs_write16(sf->selector, var->selector);
3092 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3096 vmcs_writel(sf->base, var->base);
3097 vmcs_write32(sf->limit, var->limit);
3098 vmcs_write16(sf->selector, var->selector);
3101 * Fix the "Accessed" bit in AR field of segment registers for older
3103 * IA32 arch specifies that at the time of processor reset the
3104 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3105 * is setting it to 0 in the userland code. This causes invalid guest
3106 * state vmexit when "unrestricted guest" mode is turned on.
3107 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3108 * tree. Newer qemu binaries with that qemu fix would not need this
3111 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3112 var->type |= 0x1; /* Accessed */
3114 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3117 vmx->emulation_required = emulation_required(vcpu);
3120 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3122 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3124 *db = (ar >> 14) & 1;
3125 *l = (ar >> 13) & 1;
3128 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3130 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3131 dt->address = vmcs_readl(GUEST_IDTR_BASE);
3134 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3136 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3137 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3140 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3142 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3143 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3146 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3148 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3149 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3152 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3154 struct kvm_segment var;
3157 vmx_get_segment(vcpu, &var, seg);
3159 if (seg == VCPU_SREG_CS)
3161 ar = vmx_segment_access_rights(&var);
3163 if (var.base != (var.selector << 4))
3165 if (var.limit != 0xffff)
3173 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3175 struct kvm_segment cs;
3176 unsigned int cs_rpl;
3178 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3179 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3183 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3187 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3188 if (cs.dpl > cs_rpl)
3191 if (cs.dpl != cs_rpl)
3197 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3201 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3203 struct kvm_segment ss;
3204 unsigned int ss_rpl;
3206 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3207 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3211 if (ss.type != 3 && ss.type != 7)
3215 if (ss.dpl != ss_rpl) /* DPL != RPL */
3223 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3225 struct kvm_segment var;
3228 vmx_get_segment(vcpu, &var, seg);
3229 rpl = var.selector & SEGMENT_RPL_MASK;
3237 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
3238 if (var.dpl < rpl) /* DPL < RPL */
3242 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3248 static bool tr_valid(struct kvm_vcpu *vcpu)
3250 struct kvm_segment tr;
3252 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3256 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
3258 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3266 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3268 struct kvm_segment ldtr;
3270 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3274 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
3284 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3286 struct kvm_segment cs, ss;
3288 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3289 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3291 return ((cs.selector & SEGMENT_RPL_MASK) ==
3292 (ss.selector & SEGMENT_RPL_MASK));
3296 * Check if guest state is valid. Returns true if valid, false if
3298 * We assume that registers are always usable
3300 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3302 if (enable_unrestricted_guest)
3305 /* real mode guest state checks */
3306 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3307 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3309 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3311 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3313 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3315 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3317 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3320 /* protected mode guest state checks */
3321 if (!cs_ss_rpl_check(vcpu))
3323 if (!code_segment_valid(vcpu))
3325 if (!stack_segment_valid(vcpu))
3327 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3329 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3331 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3333 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3335 if (!tr_valid(vcpu))
3337 if (!ldtr_valid(vcpu))
3341 * - Add checks on RIP
3342 * - Add checks on RFLAGS
3348 static int init_rmode_tss(struct kvm *kvm)
3354 idx = srcu_read_lock(&kvm->srcu);
3355 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
3356 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3359 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3360 r = kvm_write_guest_page(kvm, fn++, &data,
3361 TSS_IOPB_BASE_OFFSET, sizeof(u16));
3364 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3367 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3371 r = kvm_write_guest_page(kvm, fn, &data,
3372 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3375 srcu_read_unlock(&kvm->srcu, idx);
3379 static int init_rmode_identity_map(struct kvm *kvm)
3381 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
3383 kvm_pfn_t identity_map_pfn;
3386 /* Protect kvm_vmx->ept_identity_pagetable_done. */
3387 mutex_lock(&kvm->slots_lock);
3389 if (likely(kvm_vmx->ept_identity_pagetable_done))
3392 if (!kvm_vmx->ept_identity_map_addr)
3393 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3394 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
3396 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
3397 kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
3401 idx = srcu_read_lock(&kvm->srcu);
3402 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3405 /* Set up identity-mapping pagetable for EPT in real mode */
3406 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3407 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3408 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3409 r = kvm_write_guest_page(kvm, identity_map_pfn,
3410 &tmp, i * sizeof(tmp), sizeof(tmp));
3414 kvm_vmx->ept_identity_pagetable_done = true;
3417 srcu_read_unlock(&kvm->srcu, idx);
3420 mutex_unlock(&kvm->slots_lock);
3424 static void seg_setup(int seg)
3426 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3429 vmcs_write16(sf->selector, 0);
3430 vmcs_writel(sf->base, 0);
3431 vmcs_write32(sf->limit, 0xffff);
3433 if (seg == VCPU_SREG_CS)
3434 ar |= 0x08; /* code segment */
3436 vmcs_write32(sf->ar_bytes, ar);
3439 static int alloc_apic_access_page(struct kvm *kvm)
3444 mutex_lock(&kvm->slots_lock);
3445 if (kvm->arch.apic_access_page_done)
3447 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3448 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
3452 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
3453 if (is_error_page(page)) {
3459 * Do not pin the page in memory, so that memory hot-unplug
3460 * is able to migrate it.
3463 kvm->arch.apic_access_page_done = true;
3465 mutex_unlock(&kvm->slots_lock);
3469 int allocate_vpid(void)
3475 spin_lock(&vmx_vpid_lock);
3476 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3477 if (vpid < VMX_NR_VPIDS)
3478 __set_bit(vpid, vmx_vpid_bitmap);
3481 spin_unlock(&vmx_vpid_lock);
3485 void free_vpid(int vpid)
3487 if (!enable_vpid || vpid == 0)
3489 spin_lock(&vmx_vpid_lock);
3490 __clear_bit(vpid, vmx_vpid_bitmap);
3491 spin_unlock(&vmx_vpid_lock);
3494 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3497 int f = sizeof(unsigned long);
3499 if (!cpu_has_vmx_msr_bitmap())
3502 if (static_branch_unlikely(&enable_evmcs))
3503 evmcs_touch_msr_bitmap();
3506 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3507 * have the write-low and read-high bitmap offsets the wrong way round.
3508 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3510 if (msr <= 0x1fff) {
3511 if (type & MSR_TYPE_R)
3513 __clear_bit(msr, msr_bitmap + 0x000 / f);
3515 if (type & MSR_TYPE_W)
3517 __clear_bit(msr, msr_bitmap + 0x800 / f);
3519 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3521 if (type & MSR_TYPE_R)
3523 __clear_bit(msr, msr_bitmap + 0x400 / f);
3525 if (type & MSR_TYPE_W)
3527 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3532 static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3535 int f = sizeof(unsigned long);
3537 if (!cpu_has_vmx_msr_bitmap())
3540 if (static_branch_unlikely(&enable_evmcs))
3541 evmcs_touch_msr_bitmap();
3544 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3545 * have the write-low and read-high bitmap offsets the wrong way round.
3546 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3548 if (msr <= 0x1fff) {
3549 if (type & MSR_TYPE_R)
3551 __set_bit(msr, msr_bitmap + 0x000 / f);
3553 if (type & MSR_TYPE_W)
3555 __set_bit(msr, msr_bitmap + 0x800 / f);
3557 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3559 if (type & MSR_TYPE_R)
3561 __set_bit(msr, msr_bitmap + 0x400 / f);
3563 if (type & MSR_TYPE_W)
3565 __set_bit(msr, msr_bitmap + 0xc00 / f);
3570 static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
3571 u32 msr, int type, bool value)
3574 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
3576 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
3579 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
3583 if (cpu_has_secondary_exec_ctrls() &&
3584 (secondary_exec_controls_get(to_vmx(vcpu)) &
3585 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3586 mode |= MSR_BITMAP_MODE_X2APIC;
3587 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3588 mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3594 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
3599 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3600 unsigned word = msr / BITS_PER_LONG;
3601 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3602 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
3605 if (mode & MSR_BITMAP_MODE_X2APIC) {
3607 * TPR reads and writes can be virtualized even if virtual interrupt
3608 * delivery is not in use.
3610 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
3611 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3612 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
3613 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3614 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3619 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
3621 struct vcpu_vmx *vmx = to_vmx(vcpu);
3622 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3623 u8 mode = vmx_msr_bitmap_mode(vcpu);
3624 u8 changed = mode ^ vmx->msr_bitmap_mode;
3629 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
3630 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
3632 vmx->msr_bitmap_mode = mode;
3635 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx)
3637 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3638 bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3641 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS,
3643 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE,
3645 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK,
3647 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH,
3649 for (i = 0; i < vmx->pt_desc.addr_range; i++) {
3650 vmx_set_intercept_for_msr(msr_bitmap,
3651 MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3652 vmx_set_intercept_for_msr(msr_bitmap,
3653 MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3657 static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu)
3659 return enable_apicv;
3662 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3664 struct vcpu_vmx *vmx = to_vmx(vcpu);
3669 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3670 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
3671 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
3674 rvi = vmx_get_rvi();
3676 vapic_page = vmx->nested.virtual_apic_map.hva;
3677 vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
3679 return ((rvi & 0xf0) > (vppr & 0xf0));
3682 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3686 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3688 if (vcpu->mode == IN_GUEST_MODE) {
3690 * The vector of interrupt to be delivered to vcpu had
3691 * been set in PIR before this function.
3693 * Following cases will be reached in this block, and
3694 * we always send a notification event in all cases as
3697 * Case 1: vcpu keeps in non-root mode. Sending a
3698 * notification event posts the interrupt to vcpu.
3700 * Case 2: vcpu exits to root mode and is still
3701 * runnable. PIR will be synced to vIRR before the
3702 * next vcpu entry. Sending a notification event in
3703 * this case has no effect, as vcpu is not in root
3706 * Case 3: vcpu exits to root mode and is blocked.
3707 * vcpu_block() has already synced PIR to vIRR and
3708 * never blocks vcpu if vIRR is not cleared. Therefore,
3709 * a blocked vcpu here does not wait for any requested
3710 * interrupts in PIR, and sending a notification event
3711 * which has no effect is safe here.
3714 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
3721 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3724 struct vcpu_vmx *vmx = to_vmx(vcpu);
3726 if (is_guest_mode(vcpu) &&
3727 vector == vmx->nested.posted_intr_nv) {
3729 * If a posted intr is not recognized by hardware,
3730 * we will accomplish it in the next vmentry.
3732 vmx->nested.pi_pending = true;
3733 kvm_make_request(KVM_REQ_EVENT, vcpu);
3734 /* the PIR and ON have been set by L1. */
3735 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3736 kvm_vcpu_kick(vcpu);
3742 * Send interrupt to vcpu via posted interrupt way.
3743 * 1. If target vcpu is running(non-root mode), send posted interrupt
3744 * notification to vcpu and hardware will sync PIR to vIRR atomically.
3745 * 2. If target vcpu isn't running(root mode), kick it to pick up the
3746 * interrupt from PIR in next vmentry.
3748 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3750 struct vcpu_vmx *vmx = to_vmx(vcpu);
3753 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3757 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
3760 /* If a previous notification has sent the IPI, nothing to do. */
3761 if (pi_test_and_set_on(&vmx->pi_desc))
3764 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
3765 kvm_vcpu_kick(vcpu);
3769 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3770 * will not change in the lifetime of the guest.
3771 * Note that host-state that does change is set elsewhere. E.g., host-state
3772 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3774 void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
3778 unsigned long cr0, cr3, cr4;
3781 WARN_ON(cr0 & X86_CR0_TS);
3782 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
3785 * Save the most likely value for this task's CR3 in the VMCS.
3786 * We can't use __get_current_cr3_fast() because we're not atomic.
3789 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
3790 vmx->loaded_vmcs->host_state.cr3 = cr3;
3792 /* Save the most likely value for this task's CR4 in the VMCS. */
3793 cr4 = cr4_read_shadow();
3794 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
3795 vmx->loaded_vmcs->host_state.cr4 = cr4;
3797 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
3798 #ifdef CONFIG_X86_64
3800 * Load null selectors, so we can avoid reloading them in
3801 * vmx_prepare_switch_to_host(), in case userspace uses
3802 * the null selectors too (the expected case).
3804 vmcs_write16(HOST_DS_SELECTOR, 0);
3805 vmcs_write16(HOST_ES_SELECTOR, 0);
3807 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3808 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3810 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3811 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3813 vmcs_writel(HOST_IDTR_BASE, host_idt_base); /* 22.2.4 */
3815 vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
3817 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3818 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3819 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3820 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3822 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3823 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3824 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3827 if (cpu_has_load_ia32_efer())
3828 vmcs_write64(HOST_IA32_EFER, host_efer);
3831 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3833 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3835 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3836 if (is_guest_mode(&vmx->vcpu))
3837 vmx->vcpu.arch.cr4_guest_owned_bits &=
3838 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3839 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3842 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
3844 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
3846 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
3847 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
3850 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
3852 if (!enable_preemption_timer)
3853 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3855 return pin_based_exec_ctrl;
3858 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
3860 struct vcpu_vmx *vmx = to_vmx(vcpu);
3862 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
3863 if (cpu_has_secondary_exec_ctrls()) {
3864 if (kvm_vcpu_apicv_active(vcpu))
3865 secondary_exec_controls_setbit(vmx,
3866 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3867 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3869 secondary_exec_controls_clearbit(vmx,
3870 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3871 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3874 if (cpu_has_vmx_msr_bitmap())
3875 vmx_update_msr_bitmap(vcpu);
3878 u32 vmx_exec_control(struct vcpu_vmx *vmx)
3880 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3882 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
3883 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
3885 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
3886 exec_control &= ~CPU_BASED_TPR_SHADOW;
3887 #ifdef CONFIG_X86_64
3888 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3889 CPU_BASED_CR8_LOAD_EXITING;
3893 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3894 CPU_BASED_CR3_LOAD_EXITING |
3895 CPU_BASED_INVLPG_EXITING;
3896 if (kvm_mwait_in_guest(vmx->vcpu.kvm))
3897 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
3898 CPU_BASED_MONITOR_EXITING);
3899 if (kvm_hlt_in_guest(vmx->vcpu.kvm))
3900 exec_control &= ~CPU_BASED_HLT_EXITING;
3901 return exec_control;
3905 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
3907 struct kvm_vcpu *vcpu = &vmx->vcpu;
3909 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3911 if (pt_mode == PT_MODE_SYSTEM)
3912 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
3913 if (!cpu_need_virtualize_apic_accesses(vcpu))
3914 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3916 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3918 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3919 enable_unrestricted_guest = 0;
3921 if (!enable_unrestricted_guest)
3922 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3923 if (kvm_pause_in_guest(vmx->vcpu.kvm))
3924 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3925 if (!kvm_vcpu_apicv_active(vcpu))
3926 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
3927 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3928 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
3930 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
3931 * in vmx_set_cr4. */
3932 exec_control &= ~SECONDARY_EXEC_DESC;
3934 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
3936 We can NOT enable shadow_vmcs here because we don't have yet
3939 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
3942 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
3944 if (vmx_xsaves_supported()) {
3945 /* Exposing XSAVES only when XSAVE is exposed */
3946 bool xsaves_enabled =
3947 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
3948 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
3950 if (!xsaves_enabled)
3951 exec_control &= ~SECONDARY_EXEC_XSAVES;
3955 vmx->nested.msrs.secondary_ctls_high |=
3956 SECONDARY_EXEC_XSAVES;
3958 vmx->nested.msrs.secondary_ctls_high &=
3959 ~SECONDARY_EXEC_XSAVES;
3963 if (vmx_rdtscp_supported()) {
3964 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
3965 if (!rdtscp_enabled)
3966 exec_control &= ~SECONDARY_EXEC_RDTSCP;
3970 vmx->nested.msrs.secondary_ctls_high |=
3971 SECONDARY_EXEC_RDTSCP;
3973 vmx->nested.msrs.secondary_ctls_high &=
3974 ~SECONDARY_EXEC_RDTSCP;
3978 if (vmx_invpcid_supported()) {
3979 /* Exposing INVPCID only when PCID is exposed */
3980 bool invpcid_enabled =
3981 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
3982 guest_cpuid_has(vcpu, X86_FEATURE_PCID);
3984 if (!invpcid_enabled) {
3985 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
3986 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
3990 if (invpcid_enabled)
3991 vmx->nested.msrs.secondary_ctls_high |=
3992 SECONDARY_EXEC_ENABLE_INVPCID;
3994 vmx->nested.msrs.secondary_ctls_high &=
3995 ~SECONDARY_EXEC_ENABLE_INVPCID;
3999 if (vmx_rdrand_supported()) {
4000 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
4002 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
4006 vmx->nested.msrs.secondary_ctls_high |=
4007 SECONDARY_EXEC_RDRAND_EXITING;
4009 vmx->nested.msrs.secondary_ctls_high &=
4010 ~SECONDARY_EXEC_RDRAND_EXITING;
4014 if (vmx_rdseed_supported()) {
4015 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
4017 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
4021 vmx->nested.msrs.secondary_ctls_high |=
4022 SECONDARY_EXEC_RDSEED_EXITING;
4024 vmx->nested.msrs.secondary_ctls_high &=
4025 ~SECONDARY_EXEC_RDSEED_EXITING;
4029 vmx->secondary_exec_control = exec_control;
4032 static void ept_set_mmio_spte_mask(void)
4035 * EPT Misconfigurations can be generated if the value of bits 2:0
4036 * of an EPT paging-structure entry is 110b (write/execute).
4038 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
4039 VMX_EPT_MISCONFIG_WX_VALUE, 0);
4042 #define VMX_XSS_EXIT_BITMAP 0
4045 * Sets up the vmcs for emulated real mode.
4047 static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
4052 nested_vmx_vcpu_setup();
4054 if (cpu_has_vmx_msr_bitmap())
4055 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
4057 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4060 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4061 vmx->hv_deadline_tsc = -1;
4063 exec_controls_set(vmx, vmx_exec_control(vmx));
4065 if (cpu_has_secondary_exec_ctrls()) {
4066 vmx_compute_secondary_exec_control(vmx);
4067 secondary_exec_controls_set(vmx, vmx->secondary_exec_control);
4070 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4071 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4072 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4073 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4074 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4076 vmcs_write16(GUEST_INTR_STATUS, 0);
4078 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4079 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4082 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4083 vmcs_write32(PLE_GAP, ple_gap);
4084 vmx->ple_window = ple_window;
4085 vmx->ple_window_dirty = true;
4088 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4089 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4090 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4092 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4093 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
4094 vmx_set_constant_host_state(vmx);
4095 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4096 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4098 if (cpu_has_vmx_vmfunc())
4099 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4101 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4102 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4103 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
4104 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4105 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
4107 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4108 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4110 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4111 u32 index = vmx_msr_index[i];
4112 u32 data_low, data_high;
4115 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4117 if (wrmsr_safe(index, data_low, data_high) < 0)
4119 vmx->guest_msrs[j].index = i;
4120 vmx->guest_msrs[j].data = 0;
4121 vmx->guest_msrs[j].mask = -1ull;
4125 vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
4127 /* 22.2.1, 20.8.1 */
4128 vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
4130 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
4131 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
4133 set_cr4_guest_host_mask(vmx);
4135 if (vmx_xsaves_supported())
4136 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4139 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4140 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4143 if (cpu_has_vmx_encls_vmexit())
4144 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
4146 if (pt_mode == PT_MODE_HOST_GUEST) {
4147 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4148 /* Bit[6~0] are forced to 1, writes are ignored. */
4149 vmx->pt_desc.guest.output_mask = 0x7F;
4150 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4154 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4156 struct vcpu_vmx *vmx = to_vmx(vcpu);
4157 struct msr_data apic_base_msr;
4160 vmx->rmode.vm86_active = 0;
4163 vcpu->arch.microcode_version = 0x100000000ULL;
4164 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4165 vmx->hv_deadline_tsc = -1;
4166 kvm_set_cr8(vcpu, 0);
4169 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4170 MSR_IA32_APICBASE_ENABLE;
4171 if (kvm_vcpu_is_reset_bsp(vcpu))
4172 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4173 apic_base_msr.host_initiated = true;
4174 kvm_set_apic_base(vcpu, &apic_base_msr);
4177 vmx_segment_cache_clear(vmx);
4179 seg_setup(VCPU_SREG_CS);
4180 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4181 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4183 seg_setup(VCPU_SREG_DS);
4184 seg_setup(VCPU_SREG_ES);
4185 seg_setup(VCPU_SREG_FS);
4186 seg_setup(VCPU_SREG_GS);
4187 seg_setup(VCPU_SREG_SS);
4189 vmcs_write16(GUEST_TR_SELECTOR, 0);
4190 vmcs_writel(GUEST_TR_BASE, 0);
4191 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4192 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4194 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4195 vmcs_writel(GUEST_LDTR_BASE, 0);
4196 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4197 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4200 vmcs_write32(GUEST_SYSENTER_CS, 0);
4201 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4202 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4203 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4206 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
4207 kvm_rip_write(vcpu, 0xfff0);
4209 vmcs_writel(GUEST_GDTR_BASE, 0);
4210 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4212 vmcs_writel(GUEST_IDTR_BASE, 0);
4213 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4215 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4216 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4217 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4218 if (kvm_mpx_supported())
4219 vmcs_write64(GUEST_BNDCFGS, 0);
4223 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4225 if (cpu_has_vmx_tpr_shadow() && !init_event) {
4226 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4227 if (cpu_need_tpr_shadow(vcpu))
4228 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4229 __pa(vcpu->arch.apic->regs));
4230 vmcs_write32(TPR_THRESHOLD, 0);
4233 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4236 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4238 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4239 vmx->vcpu.arch.cr0 = cr0;
4240 vmx_set_cr0(vcpu, cr0); /* enter rmode */
4241 vmx_set_cr4(vcpu, 0);
4242 vmx_set_efer(vcpu, 0);
4244 update_exception_bitmap(vcpu);
4246 vpid_sync_context(vmx->vpid);
4248 vmx_clear_hlt(vcpu);
4251 static void enable_irq_window(struct kvm_vcpu *vcpu)
4253 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_INTR_PENDING);
4256 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4259 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4260 enable_irq_window(vcpu);
4264 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_NMI_PENDING);
4267 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4269 struct vcpu_vmx *vmx = to_vmx(vcpu);
4271 int irq = vcpu->arch.interrupt.nr;
4273 trace_kvm_inj_virq(irq);
4275 ++vcpu->stat.irq_injections;
4276 if (vmx->rmode.vm86_active) {
4278 if (vcpu->arch.interrupt.soft)
4279 inc_eip = vcpu->arch.event_exit_inst_len;
4280 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4281 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4284 intr = irq | INTR_INFO_VALID_MASK;
4285 if (vcpu->arch.interrupt.soft) {
4286 intr |= INTR_TYPE_SOFT_INTR;
4287 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4288 vmx->vcpu.arch.event_exit_inst_len);
4290 intr |= INTR_TYPE_EXT_INTR;
4291 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4293 vmx_clear_hlt(vcpu);
4296 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4298 struct vcpu_vmx *vmx = to_vmx(vcpu);
4302 * Tracking the NMI-blocked state in software is built upon
4303 * finding the next open IRQ window. This, in turn, depends on
4304 * well-behaving guests: They have to keep IRQs disabled at
4305 * least as long as the NMI handler runs. Otherwise we may
4306 * cause NMI nesting, maybe breaking the guest. But as this is
4307 * highly unlikely, we can live with the residual risk.
4309 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4310 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4313 ++vcpu->stat.nmi_injections;
4314 vmx->loaded_vmcs->nmi_known_unmasked = false;
4316 if (vmx->rmode.vm86_active) {
4317 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4318 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4322 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4323 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4325 vmx_clear_hlt(vcpu);
4328 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4330 struct vcpu_vmx *vmx = to_vmx(vcpu);
4334 return vmx->loaded_vmcs->soft_vnmi_blocked;
4335 if (vmx->loaded_vmcs->nmi_known_unmasked)
4337 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4338 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4342 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4344 struct vcpu_vmx *vmx = to_vmx(vcpu);
4347 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4348 vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4349 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4352 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4354 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4355 GUEST_INTR_STATE_NMI);
4357 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4358 GUEST_INTR_STATE_NMI);
4362 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4364 if (to_vmx(vcpu)->nested.nested_run_pending)
4368 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4371 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4372 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4373 | GUEST_INTR_STATE_NMI));
4376 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4378 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4379 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4380 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4381 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4384 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4388 if (enable_unrestricted_guest)
4391 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4395 to_kvm_vmx(kvm)->tss_addr = addr;
4396 return init_rmode_tss(kvm);
4399 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4401 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
4405 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4410 * Update instruction length as we may reinject the exception
4411 * from user space while in guest debugging mode.
4413 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4414 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4415 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4419 if (vcpu->guest_debug &
4420 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4437 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4438 int vec, u32 err_code)
4441 * Instruction with address size override prefix opcode 0x67
4442 * Cause the #SS fault with 0 error code in VM86 mode.
4444 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4445 if (kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4446 if (vcpu->arch.halt_request) {
4447 vcpu->arch.halt_request = 0;
4448 return kvm_vcpu_halt(vcpu);
4456 * Forward all other exceptions that are valid in real mode.
4457 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4458 * the required debugging infrastructure rework.
4460 kvm_queue_exception(vcpu, vec);
4465 * Trigger machine check on the host. We assume all the MSRs are already set up
4466 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4467 * We pass a fake environment to the machine check handler because we want
4468 * the guest to be always treated like user space, no matter what context
4469 * it used internally.
4471 static void kvm_machine_check(void)
4473 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4474 struct pt_regs regs = {
4475 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4476 .flags = X86_EFLAGS_IF,
4479 do_machine_check(®s, 0);
4483 static int handle_machine_check(struct kvm_vcpu *vcpu)
4485 /* handled by vmx_vcpu_run() */
4489 static int handle_exception_nmi(struct kvm_vcpu *vcpu)
4491 struct vcpu_vmx *vmx = to_vmx(vcpu);
4492 struct kvm_run *kvm_run = vcpu->run;
4493 u32 intr_info, ex_no, error_code;
4494 unsigned long cr2, rip, dr6;
4496 enum emulation_result er;
4498 vect_info = vmx->idt_vectoring_info;
4499 intr_info = vmx->exit_intr_info;
4501 if (is_machine_check(intr_info) || is_nmi(intr_info))
4502 return 1; /* handled by handle_exception_nmi_irqoff() */
4504 if (is_invalid_opcode(intr_info))
4505 return handle_ud(vcpu);
4508 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4509 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4511 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4512 WARN_ON_ONCE(!enable_vmware_backdoor);
4513 er = kvm_emulate_instruction(vcpu,
4514 EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL);
4515 if (er == EMULATE_USER_EXIT)
4517 else if (er != EMULATE_DONE)
4518 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4523 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4524 * MMIO, it is better to report an internal error.
4525 * See the comments in vmx_handle_exit.
4527 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4528 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4529 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4530 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4531 vcpu->run->internal.ndata = 3;
4532 vcpu->run->internal.data[0] = vect_info;
4533 vcpu->run->internal.data[1] = intr_info;
4534 vcpu->run->internal.data[2] = error_code;
4538 if (is_page_fault(intr_info)) {
4539 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4540 /* EPT won't cause page fault directly */
4541 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
4542 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
4545 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4547 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4548 return handle_rmode_exception(vcpu, ex_no, error_code);
4552 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4555 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4556 if (!(vcpu->guest_debug &
4557 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4558 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4559 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4560 if (is_icebp(intr_info))
4561 skip_emulated_instruction(vcpu);
4563 kvm_queue_exception(vcpu, DB_VECTOR);
4566 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4567 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4571 * Update instruction length as we may reinject #BP from
4572 * user space while in guest debugging mode. Reading it for
4573 * #DB as well causes no harm, it is not used in that case.
4575 vmx->vcpu.arch.event_exit_inst_len =
4576 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4577 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4578 rip = kvm_rip_read(vcpu);
4579 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4580 kvm_run->debug.arch.exception = ex_no;
4583 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4584 kvm_run->ex.exception = ex_no;
4585 kvm_run->ex.error_code = error_code;
4591 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4593 ++vcpu->stat.irq_exits;
4597 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4599 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4600 vcpu->mmio_needed = 0;
4604 static int handle_io(struct kvm_vcpu *vcpu)
4606 unsigned long exit_qualification;
4607 int size, in, string;
4610 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4611 string = (exit_qualification & 16) != 0;
4613 ++vcpu->stat.io_exits;
4616 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
4618 port = exit_qualification >> 16;
4619 size = (exit_qualification & 7) + 1;
4620 in = (exit_qualification & 8) != 0;
4622 return kvm_fast_pio(vcpu, size, port, in);
4626 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4629 * Patch in the VMCALL instruction:
4631 hypercall[0] = 0x0f;
4632 hypercall[1] = 0x01;
4633 hypercall[2] = 0xc1;
4636 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4637 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4639 if (is_guest_mode(vcpu)) {
4640 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4641 unsigned long orig_val = val;
4644 * We get here when L2 changed cr0 in a way that did not change
4645 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4646 * but did change L0 shadowed bits. So we first calculate the
4647 * effective cr0 value that L1 would like to write into the
4648 * hardware. It consists of the L2-owned bits from the new
4649 * value combined with the L1-owned bits from L1's guest_cr0.
4651 val = (val & ~vmcs12->cr0_guest_host_mask) |
4652 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4654 if (!nested_guest_cr0_valid(vcpu, val))
4657 if (kvm_set_cr0(vcpu, val))
4659 vmcs_writel(CR0_READ_SHADOW, orig_val);
4662 if (to_vmx(vcpu)->nested.vmxon &&
4663 !nested_host_cr0_valid(vcpu, val))
4666 return kvm_set_cr0(vcpu, val);
4670 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4672 if (is_guest_mode(vcpu)) {
4673 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4674 unsigned long orig_val = val;
4676 /* analogously to handle_set_cr0 */
4677 val = (val & ~vmcs12->cr4_guest_host_mask) |
4678 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4679 if (kvm_set_cr4(vcpu, val))
4681 vmcs_writel(CR4_READ_SHADOW, orig_val);
4684 return kvm_set_cr4(vcpu, val);
4687 static int handle_desc(struct kvm_vcpu *vcpu)
4689 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
4690 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
4693 static int handle_cr(struct kvm_vcpu *vcpu)
4695 unsigned long exit_qualification, val;
4701 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4702 cr = exit_qualification & 15;
4703 reg = (exit_qualification >> 8) & 15;
4704 switch ((exit_qualification >> 4) & 3) {
4705 case 0: /* mov to cr */
4706 val = kvm_register_readl(vcpu, reg);
4707 trace_kvm_cr_write(cr, val);
4710 err = handle_set_cr0(vcpu, val);
4711 return kvm_complete_insn_gp(vcpu, err);
4713 WARN_ON_ONCE(enable_unrestricted_guest);
4714 err = kvm_set_cr3(vcpu, val);
4715 return kvm_complete_insn_gp(vcpu, err);
4717 err = handle_set_cr4(vcpu, val);
4718 return kvm_complete_insn_gp(vcpu, err);
4720 u8 cr8_prev = kvm_get_cr8(vcpu);
4722 err = kvm_set_cr8(vcpu, cr8);
4723 ret = kvm_complete_insn_gp(vcpu, err);
4724 if (lapic_in_kernel(vcpu))
4726 if (cr8_prev <= cr8)
4729 * TODO: we might be squashing a
4730 * KVM_GUESTDBG_SINGLESTEP-triggered
4731 * KVM_EXIT_DEBUG here.
4733 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4739 WARN_ONCE(1, "Guest should always own CR0.TS");
4740 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4741 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4742 return kvm_skip_emulated_instruction(vcpu);
4743 case 1: /*mov from cr*/
4746 WARN_ON_ONCE(enable_unrestricted_guest);
4747 val = kvm_read_cr3(vcpu);
4748 kvm_register_write(vcpu, reg, val);
4749 trace_kvm_cr_read(cr, val);
4750 return kvm_skip_emulated_instruction(vcpu);
4752 val = kvm_get_cr8(vcpu);
4753 kvm_register_write(vcpu, reg, val);
4754 trace_kvm_cr_read(cr, val);
4755 return kvm_skip_emulated_instruction(vcpu);
4759 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4760 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4761 kvm_lmsw(vcpu, val);
4763 return kvm_skip_emulated_instruction(vcpu);
4767 vcpu->run->exit_reason = 0;
4768 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4769 (int)(exit_qualification >> 4) & 3, cr);
4773 static int handle_dr(struct kvm_vcpu *vcpu)
4775 unsigned long exit_qualification;
4778 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4779 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4781 /* First, if DR does not exist, trigger UD */
4782 if (!kvm_require_dr(vcpu, dr))
4785 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4786 if (!kvm_require_cpl(vcpu, 0))
4788 dr7 = vmcs_readl(GUEST_DR7);
4791 * As the vm-exit takes precedence over the debug trap, we
4792 * need to emulate the latter, either for the host or the
4793 * guest debugging itself.
4795 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4796 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4797 vcpu->run->debug.arch.dr7 = dr7;
4798 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
4799 vcpu->run->debug.arch.exception = DB_VECTOR;
4800 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4803 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4804 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
4805 kvm_queue_exception(vcpu, DB_VECTOR);
4810 if (vcpu->guest_debug == 0) {
4811 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
4814 * No more DR vmexits; force a reload of the debug registers
4815 * and reenter on this instruction. The next vmexit will
4816 * retrieve the full state of the debug registers.
4818 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4822 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4823 if (exit_qualification & TYPE_MOV_FROM_DR) {
4826 if (kvm_get_dr(vcpu, dr, &val))
4828 kvm_register_write(vcpu, reg, val);
4830 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4833 return kvm_skip_emulated_instruction(vcpu);
4836 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
4838 return vcpu->arch.dr6;
4841 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
4845 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
4847 get_debugreg(vcpu->arch.db[0], 0);
4848 get_debugreg(vcpu->arch.db[1], 1);
4849 get_debugreg(vcpu->arch.db[2], 2);
4850 get_debugreg(vcpu->arch.db[3], 3);
4851 get_debugreg(vcpu->arch.dr6, 6);
4852 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
4854 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
4855 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
4858 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4860 vmcs_writel(GUEST_DR7, val);
4863 static int handle_cpuid(struct kvm_vcpu *vcpu)
4865 return kvm_emulate_cpuid(vcpu);
4868 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4870 return kvm_emulate_rdmsr(vcpu);
4873 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4875 return kvm_emulate_wrmsr(vcpu);
4878 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4880 kvm_apic_update_ppr(vcpu);
4884 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4886 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_INTR_PENDING);
4888 kvm_make_request(KVM_REQ_EVENT, vcpu);
4890 ++vcpu->stat.irq_window_exits;
4894 static int handle_halt(struct kvm_vcpu *vcpu)
4896 return kvm_emulate_halt(vcpu);
4899 static int handle_vmcall(struct kvm_vcpu *vcpu)
4901 return kvm_emulate_hypercall(vcpu);
4904 static int handle_invd(struct kvm_vcpu *vcpu)
4906 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
4909 static int handle_invlpg(struct kvm_vcpu *vcpu)
4911 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4913 kvm_mmu_invlpg(vcpu, exit_qualification);
4914 return kvm_skip_emulated_instruction(vcpu);
4917 static int handle_rdpmc(struct kvm_vcpu *vcpu)
4921 err = kvm_rdpmc(vcpu);
4922 return kvm_complete_insn_gp(vcpu, err);
4925 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4927 return kvm_emulate_wbinvd(vcpu);
4930 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4932 u64 new_bv = kvm_read_edx_eax(vcpu);
4933 u32 index = kvm_rcx_read(vcpu);
4935 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4936 return kvm_skip_emulated_instruction(vcpu);
4940 static int handle_xsaves(struct kvm_vcpu *vcpu)
4942 kvm_skip_emulated_instruction(vcpu);
4943 WARN(1, "this should never happen\n");
4947 static int handle_xrstors(struct kvm_vcpu *vcpu)
4949 kvm_skip_emulated_instruction(vcpu);
4950 WARN(1, "this should never happen\n");
4954 static int handle_apic_access(struct kvm_vcpu *vcpu)
4956 if (likely(fasteoi)) {
4957 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4958 int access_type, offset;
4960 access_type = exit_qualification & APIC_ACCESS_TYPE;
4961 offset = exit_qualification & APIC_ACCESS_OFFSET;
4963 * Sane guest uses MOV to write EOI, with written value
4964 * not cared. So make a short-circuit here by avoiding
4965 * heavy instruction emulation.
4967 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4968 (offset == APIC_EOI)) {
4969 kvm_lapic_set_eoi(vcpu);
4970 return kvm_skip_emulated_instruction(vcpu);
4973 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
4976 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
4978 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4979 int vector = exit_qualification & 0xff;
4981 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
4982 kvm_apic_set_eoi_accelerated(vcpu, vector);
4986 static int handle_apic_write(struct kvm_vcpu *vcpu)
4988 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4989 u32 offset = exit_qualification & 0xfff;
4991 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
4992 kvm_apic_write_nodecode(vcpu, offset);
4996 static int handle_task_switch(struct kvm_vcpu *vcpu)
4998 struct vcpu_vmx *vmx = to_vmx(vcpu);
4999 unsigned long exit_qualification;
5000 bool has_error_code = false;
5003 int reason, type, idt_v, idt_index;
5005 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5006 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5007 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5009 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5011 reason = (u32)exit_qualification >> 30;
5012 if (reason == TASK_SWITCH_GATE && idt_v) {
5014 case INTR_TYPE_NMI_INTR:
5015 vcpu->arch.nmi_injected = false;
5016 vmx_set_nmi_mask(vcpu, true);
5018 case INTR_TYPE_EXT_INTR:
5019 case INTR_TYPE_SOFT_INTR:
5020 kvm_clear_interrupt_queue(vcpu);
5022 case INTR_TYPE_HARD_EXCEPTION:
5023 if (vmx->idt_vectoring_info &
5024 VECTORING_INFO_DELIVER_CODE_MASK) {
5025 has_error_code = true;
5027 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5030 case INTR_TYPE_SOFT_EXCEPTION:
5031 kvm_clear_exception_queue(vcpu);
5037 tss_selector = exit_qualification;
5039 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5040 type != INTR_TYPE_EXT_INTR &&
5041 type != INTR_TYPE_NMI_INTR))
5042 skip_emulated_instruction(vcpu);
5044 if (kvm_task_switch(vcpu, tss_selector,
5045 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5046 has_error_code, error_code) == EMULATE_FAIL) {
5047 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5048 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5049 vcpu->run->internal.ndata = 0;
5054 * TODO: What about debug traps on tss switch?
5055 * Are we supposed to inject them and update dr6?
5061 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5063 unsigned long exit_qualification;
5067 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5070 * EPT violation happened while executing iret from NMI,
5071 * "blocked by NMI" bit has to be set before next VM entry.
5072 * There are errata that may cause this bit to not be set:
5075 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5077 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5078 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5080 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5081 trace_kvm_page_fault(gpa, exit_qualification);
5083 /* Is it a read fault? */
5084 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
5085 ? PFERR_USER_MASK : 0;
5086 /* Is it a write fault? */
5087 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
5088 ? PFERR_WRITE_MASK : 0;
5089 /* Is it a fetch fault? */
5090 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
5091 ? PFERR_FETCH_MASK : 0;
5092 /* ept page table entry is present? */
5093 error_code |= (exit_qualification &
5094 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5095 EPT_VIOLATION_EXECUTABLE))
5096 ? PFERR_PRESENT_MASK : 0;
5098 error_code |= (exit_qualification & 0x100) != 0 ?
5099 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
5101 vcpu->arch.exit_qualification = exit_qualification;
5102 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5105 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5110 * A nested guest cannot optimize MMIO vmexits, because we have an
5111 * nGPA here instead of the required GPA.
5113 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5114 if (!is_guest_mode(vcpu) &&
5115 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5116 trace_kvm_fast_mmio(gpa);
5118 * Doing kvm_skip_emulated_instruction() depends on undefined
5119 * behavior: Intel's manual doesn't mandate
5120 * VM_EXIT_INSTRUCTION_LEN to be set in VMCS when EPT MISCONFIG
5121 * occurs and while on real hardware it was observed to be set,
5122 * other hypervisors (namely Hyper-V) don't set it, we end up
5123 * advancing IP with some random value. Disable fast mmio when
5124 * running nested and keep it for real hardware in hope that
5125 * VM_EXIT_INSTRUCTION_LEN will always be set correctly.
5127 if (!static_cpu_has(X86_FEATURE_HYPERVISOR))
5128 return kvm_skip_emulated_instruction(vcpu);
5130 return kvm_emulate_instruction(vcpu, EMULTYPE_SKIP) ==
5134 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
5137 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5139 WARN_ON_ONCE(!enable_vnmi);
5140 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_NMI_PENDING);
5141 ++vcpu->stat.nmi_window_exits;
5142 kvm_make_request(KVM_REQ_EVENT, vcpu);
5147 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5149 struct vcpu_vmx *vmx = to_vmx(vcpu);
5150 enum emulation_result err = EMULATE_DONE;
5152 bool intr_window_requested;
5153 unsigned count = 130;
5156 * We should never reach the point where we are emulating L2
5157 * due to invalid guest state as that means we incorrectly
5158 * allowed a nested VMEntry with an invalid vmcs12.
5160 WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
5162 intr_window_requested = exec_controls_get(vmx) &
5163 CPU_BASED_VIRTUAL_INTR_PENDING;
5165 while (vmx->emulation_required && count-- != 0) {
5166 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5167 return handle_interrupt_window(&vmx->vcpu);
5169 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
5172 err = kvm_emulate_instruction(vcpu, 0);
5174 if (err == EMULATE_USER_EXIT) {
5175 ++vcpu->stat.mmio_exits;
5180 if (err != EMULATE_DONE)
5181 goto emulation_error;
5183 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5184 vcpu->arch.exception.pending)
5185 goto emulation_error;
5187 if (vcpu->arch.halt_request) {
5188 vcpu->arch.halt_request = 0;
5189 ret = kvm_vcpu_halt(vcpu);
5193 if (signal_pending(current))
5203 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5204 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5205 vcpu->run->internal.ndata = 0;
5209 static void grow_ple_window(struct kvm_vcpu *vcpu)
5211 struct vcpu_vmx *vmx = to_vmx(vcpu);
5212 unsigned int old = vmx->ple_window;
5214 vmx->ple_window = __grow_ple_window(old, ple_window,
5218 if (vmx->ple_window != old) {
5219 vmx->ple_window_dirty = true;
5220 trace_kvm_ple_window_update(vcpu->vcpu_id,
5221 vmx->ple_window, old);
5225 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5227 struct vcpu_vmx *vmx = to_vmx(vcpu);
5228 unsigned int old = vmx->ple_window;
5230 vmx->ple_window = __shrink_ple_window(old, ple_window,
5234 if (vmx->ple_window != old) {
5235 vmx->ple_window_dirty = true;
5236 trace_kvm_ple_window_update(vcpu->vcpu_id,
5237 vmx->ple_window, old);
5242 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
5244 static void wakeup_handler(void)
5246 struct kvm_vcpu *vcpu;
5247 int cpu = smp_processor_id();
5249 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5250 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
5251 blocked_vcpu_list) {
5252 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
5254 if (pi_test_on(pi_desc) == 1)
5255 kvm_vcpu_kick(vcpu);
5257 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5260 static void vmx_enable_tdp(void)
5262 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
5263 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
5264 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
5265 0ull, VMX_EPT_EXECUTABLE_MASK,
5266 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
5267 VMX_EPT_RWX_MASK, 0ull);
5269 ept_set_mmio_spte_mask();
5274 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5275 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5277 static int handle_pause(struct kvm_vcpu *vcpu)
5279 if (!kvm_pause_in_guest(vcpu->kvm))
5280 grow_ple_window(vcpu);
5283 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5284 * VM-execution control is ignored if CPL > 0. OTOH, KVM
5285 * never set PAUSE_EXITING and just set PLE if supported,
5286 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5288 kvm_vcpu_on_spin(vcpu, true);
5289 return kvm_skip_emulated_instruction(vcpu);
5292 static int handle_nop(struct kvm_vcpu *vcpu)
5294 return kvm_skip_emulated_instruction(vcpu);
5297 static int handle_mwait(struct kvm_vcpu *vcpu)
5299 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5300 return handle_nop(vcpu);
5303 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5305 kvm_queue_exception(vcpu, UD_VECTOR);
5309 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5314 static int handle_monitor(struct kvm_vcpu *vcpu)
5316 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5317 return handle_nop(vcpu);
5320 static int handle_invpcid(struct kvm_vcpu *vcpu)
5322 u32 vmx_instruction_info;
5326 struct x86_exception e;
5328 unsigned long roots_to_free = 0;
5334 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
5335 kvm_queue_exception(vcpu, UD_VECTOR);
5339 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5340 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5343 kvm_inject_gp(vcpu, 0);
5347 /* According to the Intel instruction reference, the memory operand
5348 * is read even if it isn't needed (e.g., for type==all)
5350 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5351 vmx_instruction_info, false,
5352 sizeof(operand), &gva))
5355 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
5356 kvm_inject_page_fault(vcpu, &e);
5360 if (operand.pcid >> 12 != 0) {
5361 kvm_inject_gp(vcpu, 0);
5365 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
5368 case INVPCID_TYPE_INDIV_ADDR:
5369 if ((!pcid_enabled && (operand.pcid != 0)) ||
5370 is_noncanonical_address(operand.gla, vcpu)) {
5371 kvm_inject_gp(vcpu, 0);
5374 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
5375 return kvm_skip_emulated_instruction(vcpu);
5377 case INVPCID_TYPE_SINGLE_CTXT:
5378 if (!pcid_enabled && (operand.pcid != 0)) {
5379 kvm_inject_gp(vcpu, 0);
5383 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
5384 kvm_mmu_sync_roots(vcpu);
5385 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
5388 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5389 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3)
5391 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
5393 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
5395 * If neither the current cr3 nor any of the prev_roots use the
5396 * given PCID, then nothing needs to be done here because a
5397 * resync will happen anyway before switching to any other CR3.
5400 return kvm_skip_emulated_instruction(vcpu);
5402 case INVPCID_TYPE_ALL_NON_GLOBAL:
5404 * Currently, KVM doesn't mark global entries in the shadow
5405 * page tables, so a non-global flush just degenerates to a
5406 * global flush. If needed, we could optimize this later by
5407 * keeping track of global entries in shadow page tables.
5411 case INVPCID_TYPE_ALL_INCL_GLOBAL:
5412 kvm_mmu_unload(vcpu);
5413 return kvm_skip_emulated_instruction(vcpu);
5416 BUG(); /* We have already checked above that type <= 3 */
5420 static int handle_pml_full(struct kvm_vcpu *vcpu)
5422 unsigned long exit_qualification;
5424 trace_kvm_pml_full(vcpu->vcpu_id);
5426 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5429 * PML buffer FULL happened while executing iret from NMI,
5430 * "blocked by NMI" bit has to be set before next VM entry.
5432 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5434 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5435 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5436 GUEST_INTR_STATE_NMI);
5439 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5440 * here.., and there's no userspace involvement needed for PML.
5445 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
5447 struct vcpu_vmx *vmx = to_vmx(vcpu);
5449 if (!vmx->req_immediate_exit &&
5450 !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled))
5451 kvm_lapic_expired_hv_timer(vcpu);
5457 * When nested=0, all VMX instruction VM Exits filter here. The handlers
5458 * are overwritten by nested_vmx_setup() when nested=1.
5460 static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
5462 kvm_queue_exception(vcpu, UD_VECTOR);
5466 static int handle_encls(struct kvm_vcpu *vcpu)
5469 * SGX virtualization is not yet supported. There is no software
5470 * enable bit for SGX, so we have to trap ENCLS and inject a #UD
5471 * to prevent the guest from executing ENCLS.
5473 kvm_queue_exception(vcpu, UD_VECTOR);
5478 * The exit handlers return 1 if the exit was handled fully and guest execution
5479 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5480 * to be done to userspace and return 0.
5482 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5483 [EXIT_REASON_EXCEPTION_NMI] = handle_exception_nmi,
5484 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
5485 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
5486 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
5487 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
5488 [EXIT_REASON_CR_ACCESS] = handle_cr,
5489 [EXIT_REASON_DR_ACCESS] = handle_dr,
5490 [EXIT_REASON_CPUID] = handle_cpuid,
5491 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5492 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5493 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5494 [EXIT_REASON_HLT] = handle_halt,
5495 [EXIT_REASON_INVD] = handle_invd,
5496 [EXIT_REASON_INVLPG] = handle_invlpg,
5497 [EXIT_REASON_RDPMC] = handle_rdpmc,
5498 [EXIT_REASON_VMCALL] = handle_vmcall,
5499 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction,
5500 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction,
5501 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction,
5502 [EXIT_REASON_VMPTRST] = handle_vmx_instruction,
5503 [EXIT_REASON_VMREAD] = handle_vmx_instruction,
5504 [EXIT_REASON_VMRESUME] = handle_vmx_instruction,
5505 [EXIT_REASON_VMWRITE] = handle_vmx_instruction,
5506 [EXIT_REASON_VMOFF] = handle_vmx_instruction,
5507 [EXIT_REASON_VMON] = handle_vmx_instruction,
5508 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5509 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
5510 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
5511 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
5512 [EXIT_REASON_WBINVD] = handle_wbinvd,
5513 [EXIT_REASON_XSETBV] = handle_xsetbv,
5514 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
5515 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
5516 [EXIT_REASON_GDTR_IDTR] = handle_desc,
5517 [EXIT_REASON_LDTR_TR] = handle_desc,
5518 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5519 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
5520 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
5521 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
5522 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
5523 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
5524 [EXIT_REASON_INVEPT] = handle_vmx_instruction,
5525 [EXIT_REASON_INVVPID] = handle_vmx_instruction,
5526 [EXIT_REASON_RDRAND] = handle_invalid_op,
5527 [EXIT_REASON_RDSEED] = handle_invalid_op,
5528 [EXIT_REASON_XSAVES] = handle_xsaves,
5529 [EXIT_REASON_XRSTORS] = handle_xrstors,
5530 [EXIT_REASON_PML_FULL] = handle_pml_full,
5531 [EXIT_REASON_INVPCID] = handle_invpcid,
5532 [EXIT_REASON_VMFUNC] = handle_vmx_instruction,
5533 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
5534 [EXIT_REASON_ENCLS] = handle_encls,
5537 static const int kvm_vmx_max_exit_handlers =
5538 ARRAY_SIZE(kvm_vmx_exit_handlers);
5540 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5542 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5543 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5546 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
5549 __free_page(vmx->pml_pg);
5554 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
5556 struct vcpu_vmx *vmx = to_vmx(vcpu);
5560 pml_idx = vmcs_read16(GUEST_PML_INDEX);
5562 /* Do nothing if PML buffer is empty */
5563 if (pml_idx == (PML_ENTITY_NUM - 1))
5566 /* PML index always points to next available PML buffer entity */
5567 if (pml_idx >= PML_ENTITY_NUM)
5572 pml_buf = page_address(vmx->pml_pg);
5573 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5576 gpa = pml_buf[pml_idx];
5577 WARN_ON(gpa & (PAGE_SIZE - 1));
5578 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5581 /* reset PML index */
5582 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5586 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
5587 * Called before reporting dirty_bitmap to userspace.
5589 static void kvm_flush_pml_buffers(struct kvm *kvm)
5592 struct kvm_vcpu *vcpu;
5594 * We only need to kick vcpu out of guest mode here, as PML buffer
5595 * is flushed at beginning of all VMEXITs, and it's obvious that only
5596 * vcpus running in guest are possible to have unflushed GPAs in PML
5599 kvm_for_each_vcpu(i, vcpu, kvm)
5600 kvm_vcpu_kick(vcpu);
5603 static void vmx_dump_sel(char *name, uint32_t sel)
5605 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5606 name, vmcs_read16(sel),
5607 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5608 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5609 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
5612 static void vmx_dump_dtsel(char *name, uint32_t limit)
5614 pr_err("%s limit=0x%08x, base=0x%016lx\n",
5615 name, vmcs_read32(limit),
5616 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
5619 void dump_vmcs(void)
5621 u32 vmentry_ctl, vmexit_ctl;
5622 u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5627 if (!dump_invalid_vmcs) {
5628 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5632 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5633 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5634 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5635 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5636 cr4 = vmcs_readl(GUEST_CR4);
5637 efer = vmcs_read64(GUEST_IA32_EFER);
5638 secondary_exec_control = 0;
5639 if (cpu_has_secondary_exec_ctrls())
5640 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5642 pr_err("*** Guest State ***\n");
5643 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5644 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5645 vmcs_readl(CR0_GUEST_HOST_MASK));
5646 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5647 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5648 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5649 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
5650 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
5652 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
5653 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5654 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
5655 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
5657 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
5658 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5659 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
5660 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5661 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5662 vmcs_readl(GUEST_SYSENTER_ESP),
5663 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5664 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
5665 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
5666 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
5667 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
5668 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
5669 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
5670 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5671 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5672 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5673 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
5674 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
5675 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
5676 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5677 efer, vmcs_read64(GUEST_IA32_PAT));
5678 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
5679 vmcs_read64(GUEST_IA32_DEBUGCTL),
5680 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5681 if (cpu_has_load_perf_global_ctrl() &&
5682 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5683 pr_err("PerfGlobCtl = 0x%016llx\n",
5684 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5685 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5686 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5687 pr_err("Interruptibility = %08x ActivityState = %08x\n",
5688 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5689 vmcs_read32(GUEST_ACTIVITY_STATE));
5690 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5691 pr_err("InterruptStatus = %04x\n",
5692 vmcs_read16(GUEST_INTR_STATUS));
5694 pr_err("*** Host State ***\n");
5695 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
5696 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5697 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5698 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5699 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5700 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5701 vmcs_read16(HOST_TR_SELECTOR));
5702 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5703 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5704 vmcs_readl(HOST_TR_BASE));
5705 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5706 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5707 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5708 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5709 vmcs_readl(HOST_CR4));
5710 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5711 vmcs_readl(HOST_IA32_SYSENTER_ESP),
5712 vmcs_read32(HOST_IA32_SYSENTER_CS),
5713 vmcs_readl(HOST_IA32_SYSENTER_EIP));
5714 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
5715 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5716 vmcs_read64(HOST_IA32_EFER),
5717 vmcs_read64(HOST_IA32_PAT));
5718 if (cpu_has_load_perf_global_ctrl() &&
5719 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5720 pr_err("PerfGlobCtl = 0x%016llx\n",
5721 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
5723 pr_err("*** Control State ***\n");
5724 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5725 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5726 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5727 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5728 vmcs_read32(EXCEPTION_BITMAP),
5729 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5730 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5731 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5732 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5733 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5734 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5735 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5736 vmcs_read32(VM_EXIT_INTR_INFO),
5737 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5738 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5739 pr_err(" reason=%08x qualification=%016lx\n",
5740 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5741 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5742 vmcs_read32(IDT_VECTORING_INFO_FIELD),
5743 vmcs_read32(IDT_VECTORING_ERROR_CODE));
5744 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5745 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5746 pr_err("TSC Multiplier = 0x%016llx\n",
5747 vmcs_read64(TSC_MULTIPLIER));
5748 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5749 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5750 u16 status = vmcs_read16(GUEST_INTR_STATUS);
5751 pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5753 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
5754 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5755 pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
5756 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
5758 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5759 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5760 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5761 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5762 n = vmcs_read32(CR3_TARGET_COUNT);
5763 for (i = 0; i + 1 < n; i += 4)
5764 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
5765 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
5766 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
5768 pr_err("CR3 target%u=%016lx\n",
5769 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
5770 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5771 pr_err("PLE Gap=%08x Window=%08x\n",
5772 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5773 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5774 pr_err("Virtual processor ID = 0x%04x\n",
5775 vmcs_read16(VIRTUAL_PROCESSOR_ID));
5779 * The guest has exited. See if we can fix it or if we need userspace
5782 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5784 struct vcpu_vmx *vmx = to_vmx(vcpu);
5785 u32 exit_reason = vmx->exit_reason;
5786 u32 vectoring_info = vmx->idt_vectoring_info;
5788 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
5791 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5792 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5793 * querying dirty_bitmap, we only need to kick all vcpus out of guest
5794 * mode as if vcpus is in root mode, the PML buffer must has been
5798 vmx_flush_pml_buffer(vcpu);
5800 /* If guest state is invalid, start emulating */
5801 if (vmx->emulation_required)
5802 return handle_invalid_guest_state(vcpu);
5804 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
5805 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
5807 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5809 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5810 vcpu->run->fail_entry.hardware_entry_failure_reason
5815 if (unlikely(vmx->fail)) {
5817 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5818 vcpu->run->fail_entry.hardware_entry_failure_reason
5819 = vmcs_read32(VM_INSTRUCTION_ERROR);
5825 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5826 * delivery event since it indicates guest is accessing MMIO.
5827 * The vm-exit can be triggered again after return to guest that
5828 * will cause infinite loop.
5830 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5831 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5832 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5833 exit_reason != EXIT_REASON_PML_FULL &&
5834 exit_reason != EXIT_REASON_TASK_SWITCH)) {
5835 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5836 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5837 vcpu->run->internal.ndata = 3;
5838 vcpu->run->internal.data[0] = vectoring_info;
5839 vcpu->run->internal.data[1] = exit_reason;
5840 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5841 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
5842 vcpu->run->internal.ndata++;
5843 vcpu->run->internal.data[3] =
5844 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5849 if (unlikely(!enable_vnmi &&
5850 vmx->loaded_vmcs->soft_vnmi_blocked)) {
5851 if (vmx_interrupt_allowed(vcpu)) {
5852 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5853 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5854 vcpu->arch.nmi_pending) {
5856 * This CPU don't support us in finding the end of an
5857 * NMI-blocked window if the guest runs with IRQs
5858 * disabled. So we pull the trigger after 1 s of
5859 * futile waiting, but inform the user about this.
5861 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5862 "state on VCPU %d after 1 s timeout\n",
5863 __func__, vcpu->vcpu_id);
5864 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5868 if (exit_reason < kvm_vmx_max_exit_handlers
5869 && kvm_vmx_exit_handlers[exit_reason])
5870 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5872 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
5875 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5876 vcpu->run->internal.suberror =
5877 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
5878 vcpu->run->internal.ndata = 1;
5879 vcpu->run->internal.data[0] = exit_reason;
5885 * Software based L1D cache flush which is used when microcode providing
5886 * the cache control MSR is not loaded.
5888 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
5889 * flush it is required to read in 64 KiB because the replacement algorithm
5890 * is not exactly LRU. This could be sized at runtime via topology
5891 * information but as all relevant affected CPUs have 32KiB L1D cache size
5892 * there is no point in doing so.
5894 static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
5896 int size = PAGE_SIZE << L1D_CACHE_ORDER;
5899 * This code is only executed when the the flush mode is 'cond' or
5902 if (static_branch_likely(&vmx_l1d_flush_cond)) {
5906 * Clear the per-vcpu flush bit, it gets set again
5907 * either from vcpu_run() or from one of the unsafe
5910 flush_l1d = vcpu->arch.l1tf_flush_l1d;
5911 vcpu->arch.l1tf_flush_l1d = false;
5914 * Clear the per-cpu flush bit, it gets set again from
5915 * the interrupt handlers.
5917 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
5918 kvm_clear_cpu_l1tf_flush_l1d();
5924 vcpu->stat.l1d_flush++;
5926 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
5927 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
5932 /* First ensure the pages are in the TLB */
5933 "xorl %%eax, %%eax\n"
5934 ".Lpopulate_tlb:\n\t"
5935 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
5936 "addl $4096, %%eax\n\t"
5937 "cmpl %%eax, %[size]\n\t"
5938 "jne .Lpopulate_tlb\n\t"
5939 "xorl %%eax, %%eax\n\t"
5941 /* Now fill the cache */
5942 "xorl %%eax, %%eax\n"
5944 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
5945 "addl $64, %%eax\n\t"
5946 "cmpl %%eax, %[size]\n\t"
5947 "jne .Lfill_cache\n\t"
5949 :: [flush_pages] "r" (vmx_l1d_flush_pages),
5951 : "eax", "ebx", "ecx", "edx");
5954 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5956 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5958 if (is_guest_mode(vcpu) &&
5959 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
5962 if (irr == -1 || tpr < irr) {
5963 vmcs_write32(TPR_THRESHOLD, 0);
5967 vmcs_write32(TPR_THRESHOLD, irr);
5970 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
5972 struct vcpu_vmx *vmx = to_vmx(vcpu);
5973 u32 sec_exec_control;
5975 if (!lapic_in_kernel(vcpu))
5978 if (!flexpriority_enabled &&
5979 !cpu_has_vmx_virtualize_x2apic_mode())
5982 /* Postpone execution until vmcs01 is the current VMCS. */
5983 if (is_guest_mode(vcpu)) {
5984 vmx->nested.change_vmcs01_virtual_apic_mode = true;
5988 sec_exec_control = secondary_exec_controls_get(vmx);
5989 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
5990 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
5992 switch (kvm_get_apic_mode(vcpu)) {
5993 case LAPIC_MODE_INVALID:
5994 WARN_ONCE(true, "Invalid local APIC state");
5995 case LAPIC_MODE_DISABLED:
5997 case LAPIC_MODE_XAPIC:
5998 if (flexpriority_enabled) {
6000 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6001 vmx_flush_tlb(vcpu, true);
6004 case LAPIC_MODE_X2APIC:
6005 if (cpu_has_vmx_virtualize_x2apic_mode())
6007 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6010 secondary_exec_controls_set(vmx, sec_exec_control);
6012 vmx_update_msr_bitmap(vcpu);
6015 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
6017 if (!is_guest_mode(vcpu)) {
6018 vmcs_write64(APIC_ACCESS_ADDR, hpa);
6019 vmx_flush_tlb(vcpu, true);
6023 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6031 status = vmcs_read16(GUEST_INTR_STATUS);
6033 if (max_isr != old) {
6035 status |= max_isr << 8;
6036 vmcs_write16(GUEST_INTR_STATUS, status);
6040 static void vmx_set_rvi(int vector)
6048 status = vmcs_read16(GUEST_INTR_STATUS);
6049 old = (u8)status & 0xff;
6050 if ((u8)vector != old) {
6052 status |= (u8)vector;
6053 vmcs_write16(GUEST_INTR_STATUS, status);
6057 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6060 * When running L2, updating RVI is only relevant when
6061 * vmcs12 virtual-interrupt-delivery enabled.
6062 * However, it can be enabled only when L1 also
6063 * intercepts external-interrupts and in that case
6064 * we should not update vmcs02 RVI but instead intercept
6065 * interrupt. Therefore, do nothing when running L2.
6067 if (!is_guest_mode(vcpu))
6068 vmx_set_rvi(max_irr);
6071 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6073 struct vcpu_vmx *vmx = to_vmx(vcpu);
6075 bool max_irr_updated;
6077 WARN_ON(!vcpu->arch.apicv_active);
6078 if (pi_test_on(&vmx->pi_desc)) {
6079 pi_clear_on(&vmx->pi_desc);
6081 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
6082 * But on x86 this is just a compiler barrier anyway.
6084 smp_mb__after_atomic();
6086 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
6089 * If we are running L2 and L1 has a new pending interrupt
6090 * which can be injected, we should re-evaluate
6091 * what should be done with this new L1 interrupt.
6092 * If L1 intercepts external-interrupts, we should
6093 * exit from L2 to L1. Otherwise, interrupt should be
6094 * delivered directly to L2.
6096 if (is_guest_mode(vcpu) && max_irr_updated) {
6097 if (nested_exit_on_intr(vcpu))
6098 kvm_vcpu_exiting_guest_mode(vcpu);
6100 kvm_make_request(KVM_REQ_EVENT, vcpu);
6103 max_irr = kvm_lapic_find_highest_irr(vcpu);
6105 vmx_hwapic_irr_update(vcpu, max_irr);
6109 static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
6111 return pi_test_on(vcpu_to_pi_desc(vcpu));
6114 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6116 if (!kvm_vcpu_apicv_active(vcpu))
6119 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6120 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6121 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6122 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6125 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
6127 struct vcpu_vmx *vmx = to_vmx(vcpu);
6129 pi_clear_on(&vmx->pi_desc);
6130 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6133 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
6135 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6137 /* if exit due to PF check for async PF */
6138 if (is_page_fault(vmx->exit_intr_info))
6139 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
6141 /* Handle machine checks before interrupts are enabled */
6142 if (is_machine_check(vmx->exit_intr_info))
6143 kvm_machine_check();
6145 /* We need to handle NMIs before interrupts are enabled */
6146 if (is_nmi(vmx->exit_intr_info)) {
6147 kvm_before_interrupt(&vmx->vcpu);
6149 kvm_after_interrupt(&vmx->vcpu);
6153 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
6155 unsigned int vector;
6156 unsigned long entry;
6157 #ifdef CONFIG_X86_64
6163 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6164 if (WARN_ONCE(!is_external_intr(intr_info),
6165 "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6168 vector = intr_info & INTR_INFO_VECTOR_MASK;
6169 desc = (gate_desc *)host_idt_base + vector;
6170 entry = gate_offset(desc);
6172 kvm_before_interrupt(vcpu);
6175 #ifdef CONFIG_X86_64
6176 "mov %%" _ASM_SP ", %[sp]\n\t"
6177 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6182 __ASM_SIZE(push) " $%c[cs]\n\t"
6185 #ifdef CONFIG_X86_64
6190 THUNK_TARGET(entry),
6191 [ss]"i"(__KERNEL_DS),
6192 [cs]"i"(__KERNEL_CS)
6195 kvm_after_interrupt(vcpu);
6197 STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff);
6199 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu)
6201 struct vcpu_vmx *vmx = to_vmx(vcpu);
6203 if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
6204 handle_external_interrupt_irqoff(vcpu);
6205 else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)
6206 handle_exception_nmi_irqoff(vmx);
6209 static bool vmx_has_emulated_msr(int index)
6212 case MSR_IA32_SMBASE:
6214 * We cannot do SMM unless we can run the guest in big
6217 return enable_unrestricted_guest || emulate_invalid_guest_state;
6218 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6220 case MSR_AMD64_VIRT_SPEC_CTRL:
6221 /* This is AMD only. */
6228 static bool vmx_pt_supported(void)
6230 return pt_mode == PT_MODE_HOST_GUEST;
6233 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6238 bool idtv_info_valid;
6240 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6243 if (vmx->loaded_vmcs->nmi_known_unmasked)
6246 * Can't use vmx->exit_intr_info since we're not sure what
6247 * the exit reason is.
6249 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6250 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6251 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6253 * SDM 3: 27.7.1.2 (September 2008)
6254 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6255 * a guest IRET fault.
6256 * SDM 3: 23.2.2 (September 2008)
6257 * Bit 12 is undefined in any of the following cases:
6258 * If the VM exit sets the valid bit in the IDT-vectoring
6259 * information field.
6260 * If the VM exit is due to a double fault.
6262 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6263 vector != DF_VECTOR && !idtv_info_valid)
6264 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6265 GUEST_INTR_STATE_NMI);
6267 vmx->loaded_vmcs->nmi_known_unmasked =
6268 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6269 & GUEST_INTR_STATE_NMI);
6270 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6271 vmx->loaded_vmcs->vnmi_blocked_time +=
6272 ktime_to_ns(ktime_sub(ktime_get(),
6273 vmx->loaded_vmcs->entry_time));
6276 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6277 u32 idt_vectoring_info,
6278 int instr_len_field,
6279 int error_code_field)
6283 bool idtv_info_valid;
6285 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6287 vcpu->arch.nmi_injected = false;
6288 kvm_clear_exception_queue(vcpu);
6289 kvm_clear_interrupt_queue(vcpu);
6291 if (!idtv_info_valid)
6294 kvm_make_request(KVM_REQ_EVENT, vcpu);
6296 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6297 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6300 case INTR_TYPE_NMI_INTR:
6301 vcpu->arch.nmi_injected = true;
6303 * SDM 3: 27.7.1.2 (September 2008)
6304 * Clear bit "block by NMI" before VM entry if a NMI
6307 vmx_set_nmi_mask(vcpu, false);
6309 case INTR_TYPE_SOFT_EXCEPTION:
6310 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6312 case INTR_TYPE_HARD_EXCEPTION:
6313 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6314 u32 err = vmcs_read32(error_code_field);
6315 kvm_requeue_exception_e(vcpu, vector, err);
6317 kvm_requeue_exception(vcpu, vector);
6319 case INTR_TYPE_SOFT_INTR:
6320 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6322 case INTR_TYPE_EXT_INTR:
6323 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6330 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6332 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6333 VM_EXIT_INSTRUCTION_LEN,
6334 IDT_VECTORING_ERROR_CODE);
6337 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6339 __vmx_complete_interrupts(vcpu,
6340 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6341 VM_ENTRY_INSTRUCTION_LEN,
6342 VM_ENTRY_EXCEPTION_ERROR_CODE);
6344 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6347 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6350 struct perf_guest_switch_msr *msrs;
6352 msrs = perf_guest_get_msrs(&nr_msrs);
6357 for (i = 0; i < nr_msrs; i++)
6358 if (msrs[i].host == msrs[i].guest)
6359 clear_atomic_switch_msr(vmx, msrs[i].msr);
6361 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6362 msrs[i].host, false);
6365 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
6367 struct vcpu_vmx *vmx = to_vmx(vcpu);
6371 if (vmx->req_immediate_exit) {
6372 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6373 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6374 } else if (vmx->hv_deadline_tsc != -1) {
6376 if (vmx->hv_deadline_tsc > tscl)
6377 /* set_hv_timer ensures the delta fits in 32-bits */
6378 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6379 cpu_preemption_timer_multi);
6383 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6384 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6385 } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6386 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6387 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
6391 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
6393 if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6394 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6395 vmcs_writel(HOST_RSP, host_rsp);
6399 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched);
6401 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6403 struct vcpu_vmx *vmx = to_vmx(vcpu);
6404 unsigned long cr3, cr4;
6406 /* Record the guest's net vcpu time for enforced NMI injections. */
6407 if (unlikely(!enable_vnmi &&
6408 vmx->loaded_vmcs->soft_vnmi_blocked))
6409 vmx->loaded_vmcs->entry_time = ktime_get();
6411 /* Don't enter VMX if guest state is invalid, let the exit handler
6412 start emulation until we arrive back to a valid state */
6413 if (vmx->emulation_required)
6416 if (vmx->ple_window_dirty) {
6417 vmx->ple_window_dirty = false;
6418 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6421 if (vmx->nested.need_vmcs12_to_shadow_sync)
6422 nested_sync_vmcs12_to_shadow(vcpu);
6424 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6425 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6426 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6427 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6429 cr3 = __get_current_cr3_fast();
6430 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6431 vmcs_writel(HOST_CR3, cr3);
6432 vmx->loaded_vmcs->host_state.cr3 = cr3;
6435 cr4 = cr4_read_shadow();
6436 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6437 vmcs_writel(HOST_CR4, cr4);
6438 vmx->loaded_vmcs->host_state.cr4 = cr4;
6441 /* When single-stepping over STI and MOV SS, we must clear the
6442 * corresponding interruptibility bits in the guest state. Otherwise
6443 * vmentry fails as it then expects bit 14 (BS) in pending debug
6444 * exceptions being set, but that's not correct for the guest debugging
6446 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6447 vmx_set_interrupt_shadow(vcpu, 0);
6449 kvm_load_guest_xcr0(vcpu);
6451 if (static_cpu_has(X86_FEATURE_PKU) &&
6452 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
6453 vcpu->arch.pkru != vmx->host_pkru)
6454 __write_pkru(vcpu->arch.pkru);
6456 pt_guest_enter(vmx);
6458 atomic_switch_perf_msrs(vmx);
6460 if (enable_preemption_timer)
6461 vmx_update_hv_timer(vcpu);
6463 if (lapic_in_kernel(vcpu) &&
6464 vcpu->arch.apic->lapic_timer.timer_advance_ns)
6465 kvm_wait_lapic_expire(vcpu);
6468 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6469 * it's non-zero. Since vmentry is serialising on affected CPUs, there
6470 * is no need to worry about the conditional branch over the wrmsr
6471 * being speculatively taken.
6473 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6475 /* L1D Flush includes CPU buffer clear to mitigate MDS */
6476 if (static_branch_unlikely(&vmx_l1d_should_flush))
6477 vmx_l1d_flush(vcpu);
6478 else if (static_branch_unlikely(&mds_user_clear))
6479 mds_clear_cpu_buffers();
6481 if (vcpu->arch.cr2 != read_cr2())
6482 write_cr2(vcpu->arch.cr2);
6484 vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6485 vmx->loaded_vmcs->launched);
6487 vcpu->arch.cr2 = read_cr2();
6490 * We do not use IBRS in the kernel. If this vCPU has used the
6491 * SPEC_CTRL MSR it may have left it on; save the value and
6492 * turn it off. This is much more efficient than blindly adding
6493 * it to the atomic save/restore list. Especially as the former
6494 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6496 * For non-nested case:
6497 * If the L01 MSR bitmap does not intercept the MSR, then we need to
6501 * If the L02 MSR bitmap does not intercept the MSR, then we need to
6504 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6505 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
6507 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
6509 /* All fields are clean at this point */
6510 if (static_branch_unlikely(&enable_evmcs))
6511 current_evmcs->hv_clean_fields |=
6512 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
6514 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6515 if (vmx->host_debugctlmsr)
6516 update_debugctlmsr(vmx->host_debugctlmsr);
6518 #ifndef CONFIG_X86_64
6520 * The sysexit path does not restore ds/es, so we must set them to
6521 * a reasonable value ourselves.
6523 * We can't defer this to vmx_prepare_switch_to_host() since that
6524 * function may be executed in interrupt context, which saves and
6525 * restore segments around it, nullifying its effect.
6527 loadsegment(ds, __USER_DS);
6528 loadsegment(es, __USER_DS);
6531 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6532 | (1 << VCPU_EXREG_RFLAGS)
6533 | (1 << VCPU_EXREG_PDPTR)
6534 | (1 << VCPU_EXREG_SEGMENTS)
6535 | (1 << VCPU_EXREG_CR3));
6536 vcpu->arch.regs_dirty = 0;
6541 * eager fpu is enabled if PKEY is supported and CR4 is switched
6542 * back on host, so it is safe to read guest PKRU from current
6545 if (static_cpu_has(X86_FEATURE_PKU) &&
6546 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
6547 vcpu->arch.pkru = rdpkru();
6548 if (vcpu->arch.pkru != vmx->host_pkru)
6549 __write_pkru(vmx->host_pkru);
6552 kvm_put_guest_xcr0(vcpu);
6554 vmx->nested.nested_run_pending = 0;
6555 vmx->idt_vectoring_info = 0;
6557 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
6558 if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
6559 kvm_machine_check();
6561 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6564 vmx->loaded_vmcs->launched = 1;
6565 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6567 vmx_recover_nmi_blocking(vmx);
6568 vmx_complete_interrupts(vmx);
6571 static struct kvm *vmx_vm_alloc(void)
6573 struct kvm_vmx *kvm_vmx = __vmalloc(sizeof(struct kvm_vmx),
6574 GFP_KERNEL_ACCOUNT | __GFP_ZERO,
6576 return &kvm_vmx->kvm;
6579 static void vmx_vm_free(struct kvm *kvm)
6581 vfree(to_kvm_vmx(kvm));
6584 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6586 struct vcpu_vmx *vmx = to_vmx(vcpu);
6589 vmx_destroy_pml_buffer(vmx);
6590 free_vpid(vmx->vpid);
6591 nested_vmx_free_vcpu(vcpu);
6592 free_loaded_vmcs(vmx->loaded_vmcs);
6593 kfree(vmx->guest_msrs);
6594 kvm_vcpu_uninit(vcpu);
6595 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu);
6596 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
6597 kmem_cache_free(kvm_vcpu_cache, vmx);
6600 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6603 struct vcpu_vmx *vmx;
6604 unsigned long *msr_bitmap;
6607 BUILD_BUG_ON_MSG(offsetof(struct vcpu_vmx, vcpu) != 0,
6608 "struct kvm_vcpu must be at offset 0 for arch usercopy region");
6610 vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL_ACCOUNT);
6612 return ERR_PTR(-ENOMEM);
6614 vmx->vcpu.arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
6615 GFP_KERNEL_ACCOUNT);
6616 if (!vmx->vcpu.arch.user_fpu) {
6617 printk(KERN_ERR "kvm: failed to allocate kvm userspace's fpu\n");
6619 goto free_partial_vcpu;
6622 vmx->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
6623 GFP_KERNEL_ACCOUNT);
6624 if (!vmx->vcpu.arch.guest_fpu) {
6625 printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n");
6630 vmx->vpid = allocate_vpid();
6632 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6639 * If PML is turned on, failure on enabling PML just results in failure
6640 * of creating the vcpu, therefore we can simplify PML logic (by
6641 * avoiding dealing with cases, such as enabling PML partially on vcpus
6642 * for the guest, etc.
6645 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
6650 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL_ACCOUNT);
6651 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
6654 if (!vmx->guest_msrs)
6657 err = alloc_loaded_vmcs(&vmx->vmcs01);
6661 msr_bitmap = vmx->vmcs01.msr_bitmap;
6662 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
6663 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
6664 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
6665 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6666 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6667 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6668 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
6669 if (kvm_cstate_in_guest(kvm)) {
6670 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R);
6671 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6672 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6673 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6675 vmx->msr_bitmap_mode = 0;
6677 vmx->loaded_vmcs = &vmx->vmcs01;
6679 vmx_vcpu_load(&vmx->vcpu, cpu);
6680 vmx->vcpu.cpu = cpu;
6681 vmx_vcpu_setup(vmx);
6682 vmx_vcpu_put(&vmx->vcpu);
6684 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
6685 err = alloc_apic_access_page(kvm);
6690 if (enable_ept && !enable_unrestricted_guest) {
6691 err = init_rmode_identity_map(kvm);
6697 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
6699 kvm_vcpu_apicv_active(&vmx->vcpu));
6701 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
6703 vmx->nested.posted_intr_nv = -1;
6704 vmx->nested.current_vmptr = -1ull;
6706 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
6709 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
6710 * or POSTED_INTR_WAKEUP_VECTOR.
6712 vmx->pi_desc.nv = POSTED_INTR_VECTOR;
6713 vmx->pi_desc.sn = 1;
6715 vmx->ept_pointer = INVALID_PAGE;
6720 free_loaded_vmcs(vmx->loaded_vmcs);
6722 kfree(vmx->guest_msrs);
6724 vmx_destroy_pml_buffer(vmx);
6726 kvm_vcpu_uninit(&vmx->vcpu);
6728 free_vpid(vmx->vpid);
6729 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
6731 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu);
6733 kmem_cache_free(kvm_vcpu_cache, vmx);
6734 return ERR_PTR(err);
6737 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6738 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6740 static int vmx_vm_init(struct kvm *kvm)
6742 spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
6745 kvm->arch.pause_in_guest = true;
6747 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6748 switch (l1tf_mitigation) {
6749 case L1TF_MITIGATION_OFF:
6750 case L1TF_MITIGATION_FLUSH_NOWARN:
6751 /* 'I explicitly don't care' is set */
6753 case L1TF_MITIGATION_FLUSH:
6754 case L1TF_MITIGATION_FLUSH_NOSMT:
6755 case L1TF_MITIGATION_FULL:
6757 * Warn upon starting the first VM in a potentially
6758 * insecure environment.
6760 if (sched_smt_active())
6761 pr_warn_once(L1TF_MSG_SMT);
6762 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6763 pr_warn_once(L1TF_MSG_L1D);
6765 case L1TF_MITIGATION_FULL_FORCE:
6766 /* Flush is enforced */
6773 static int __init vmx_check_processor_compat(void)
6775 struct vmcs_config vmcs_conf;
6776 struct vmx_capability vmx_cap;
6778 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
6781 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept,
6783 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6784 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6785 smp_processor_id());
6791 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6796 /* For VT-d and EPT combination
6797 * 1. MMIO: always map as UC
6799 * a. VT-d without snooping control feature: can't guarantee the
6800 * result, try to trust guest.
6801 * b. VT-d with snooping control feature: snooping control feature of
6802 * VT-d engine can guarantee the cache correctness. Just set it
6803 * to WB to keep consistent with host. So the same as item 3.
6804 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6805 * consistent with host MTRR
6808 cache = MTRR_TYPE_UNCACHABLE;
6812 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
6813 ipat = VMX_EPT_IPAT_BIT;
6814 cache = MTRR_TYPE_WRBACK;
6818 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
6819 ipat = VMX_EPT_IPAT_BIT;
6820 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
6821 cache = MTRR_TYPE_WRBACK;
6823 cache = MTRR_TYPE_UNCACHABLE;
6827 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
6830 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
6833 static int vmx_get_lpage_level(void)
6835 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6836 return PT_DIRECTORY_LEVEL;
6838 /* For shadow and EPT supported 1GB page */
6839 return PT_PDPE_LEVEL;
6842 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx)
6845 * These bits in the secondary execution controls field
6846 * are dynamic, the others are mostly based on the hypervisor
6847 * architecture and the guest's CPUID. Do not touch the
6851 SECONDARY_EXEC_SHADOW_VMCS |
6852 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
6853 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6854 SECONDARY_EXEC_DESC;
6856 u32 new_ctl = vmx->secondary_exec_control;
6857 u32 cur_ctl = secondary_exec_controls_get(vmx);
6859 secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
6863 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
6864 * (indicating "allowed-1") if they are supported in the guest's CPUID.
6866 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
6868 struct vcpu_vmx *vmx = to_vmx(vcpu);
6869 struct kvm_cpuid_entry2 *entry;
6871 vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
6872 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
6874 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
6875 if (entry && (entry->_reg & (_cpuid_mask))) \
6876 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \
6879 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
6880 cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME));
6881 cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME));
6882 cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC));
6883 cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE));
6884 cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE));
6885 cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE));
6886 cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE));
6887 cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE));
6888 cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR));
6889 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
6890 cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX));
6891 cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX));
6892 cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID));
6893 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE));
6895 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6896 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE));
6897 cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP));
6898 cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP));
6899 cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU));
6900 cr4_fixed1_update(X86_CR4_UMIP, ecx, bit(X86_FEATURE_UMIP));
6902 #undef cr4_fixed1_update
6905 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
6907 struct vcpu_vmx *vmx = to_vmx(vcpu);
6909 if (kvm_mpx_supported()) {
6910 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
6913 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
6914 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
6916 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
6917 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
6922 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
6924 struct vcpu_vmx *vmx = to_vmx(vcpu);
6925 struct kvm_cpuid_entry2 *best = NULL;
6928 for (i = 0; i < PT_CPUID_LEAVES; i++) {
6929 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
6932 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
6933 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
6934 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
6935 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
6938 /* Get the number of configurable Address Ranges for filtering */
6939 vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
6940 PT_CAP_num_address_ranges);
6942 /* Initialize and clear the no dependency bits */
6943 vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
6944 RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
6947 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
6948 * will inject an #GP
6950 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
6951 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
6954 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
6955 * PSBFreq can be set
6957 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
6958 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
6959 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
6962 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
6963 * MTCFreq can be set
6965 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
6966 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
6967 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
6969 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
6970 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
6971 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
6974 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
6975 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
6976 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
6978 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
6979 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
6980 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
6982 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */
6983 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
6984 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
6986 /* unmask address range configure area */
6987 for (i = 0; i < vmx->pt_desc.addr_range; i++)
6988 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
6991 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6993 struct vcpu_vmx *vmx = to_vmx(vcpu);
6995 if (cpu_has_secondary_exec_ctrls()) {
6996 vmx_compute_secondary_exec_control(vmx);
6997 vmcs_set_secondary_exec_control(vmx);
7000 if (nested_vmx_allowed(vcpu))
7001 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7002 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7004 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7005 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7007 if (nested_vmx_allowed(vcpu)) {
7008 nested_vmx_cr_fixed1_bits_update(vcpu);
7009 nested_vmx_entry_exit_ctls_update(vcpu);
7012 if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7013 guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7014 update_intel_pt_cfg(vcpu);
7017 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7019 if (func == 1 && nested)
7020 entry->ecx |= bit(X86_FEATURE_VMX);
7023 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
7025 to_vmx(vcpu)->req_immediate_exit = true;
7028 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7029 struct x86_instruction_info *info,
7030 enum x86_intercept_stage stage)
7032 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7033 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7036 * RDPID causes #UD if disabled through secondary execution controls.
7037 * Because it is marked as EmulateOnUD, we need to intercept it here.
7039 if (info->intercept == x86_intercept_rdtscp &&
7040 !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
7041 ctxt->exception.vector = UD_VECTOR;
7042 ctxt->exception.error_code_valid = false;
7043 return X86EMUL_PROPAGATE_FAULT;
7046 /* TODO: check more intercepts... */
7047 return X86EMUL_CONTINUE;
7050 #ifdef CONFIG_X86_64
7051 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7052 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7053 u64 divisor, u64 *result)
7055 u64 low = a << shift, high = a >> (64 - shift);
7057 /* To avoid the overflow on divq */
7058 if (high >= divisor)
7061 /* Low hold the result, high hold rem which is discarded */
7062 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7063 "rm" (divisor), "0" (low), "1" (high));
7069 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7072 struct vcpu_vmx *vmx;
7073 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
7074 struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
7076 if (kvm_mwait_in_guest(vcpu->kvm) ||
7077 kvm_can_post_timer_interrupt(vcpu))
7082 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7083 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
7084 lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7085 ktimer->timer_advance_ns);
7087 if (delta_tsc > lapic_timer_advance_cycles)
7088 delta_tsc -= lapic_timer_advance_cycles;
7092 /* Convert to host delta tsc if tsc scaling is enabled */
7093 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
7094 delta_tsc && u64_shl_div_u64(delta_tsc,
7095 kvm_tsc_scaling_ratio_frac_bits,
7096 vcpu->arch.tsc_scaling_ratio, &delta_tsc))
7100 * If the delta tsc can't fit in the 32 bit after the multi shift,
7101 * we can't use the preemption timer.
7102 * It's possible that it fits on later vmentries, but checking
7103 * on every vmentry is costly so we just use an hrtimer.
7105 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7108 vmx->hv_deadline_tsc = tscl + delta_tsc;
7109 *expired = !delta_tsc;
7113 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7115 to_vmx(vcpu)->hv_deadline_tsc = -1;
7119 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
7121 if (!kvm_pause_in_guest(vcpu->kvm))
7122 shrink_ple_window(vcpu);
7125 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
7126 struct kvm_memory_slot *slot)
7128 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
7129 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
7132 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
7133 struct kvm_memory_slot *slot)
7135 kvm_mmu_slot_set_dirty(kvm, slot);
7138 static void vmx_flush_log_dirty(struct kvm *kvm)
7140 kvm_flush_pml_buffers(kvm);
7143 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
7145 struct vmcs12 *vmcs12;
7146 struct vcpu_vmx *vmx = to_vmx(vcpu);
7149 if (is_guest_mode(vcpu)) {
7150 WARN_ON_ONCE(vmx->nested.pml_full);
7153 * Check if PML is enabled for the nested guest.
7154 * Whether eptp bit 6 is set is already checked
7155 * as part of A/D emulation.
7157 vmcs12 = get_vmcs12(vcpu);
7158 if (!nested_cpu_has_pml(vmcs12))
7161 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
7162 vmx->nested.pml_full = true;
7166 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
7167 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index;
7169 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa,
7170 offset_in_page(dst), sizeof(gpa)))
7173 vmcs12->guest_pml_index--;
7179 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
7180 struct kvm_memory_slot *memslot,
7181 gfn_t offset, unsigned long mask)
7183 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
7186 static void __pi_post_block(struct kvm_vcpu *vcpu)
7188 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7189 struct pi_desc old, new;
7193 old.control = new.control = pi_desc->control;
7194 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
7195 "Wakeup handler not enabled while the VCPU is blocked\n");
7197 dest = cpu_physical_id(vcpu->cpu);
7199 if (x2apic_enabled())
7202 new.ndst = (dest << 8) & 0xFF00;
7204 /* set 'NV' to 'notification vector' */
7205 new.nv = POSTED_INTR_VECTOR;
7206 } while (cmpxchg64(&pi_desc->control, old.control,
7207 new.control) != old.control);
7209 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
7210 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7211 list_del(&vcpu->blocked_vcpu_list);
7212 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7213 vcpu->pre_pcpu = -1;
7218 * This routine does the following things for vCPU which is going
7219 * to be blocked if VT-d PI is enabled.
7220 * - Store the vCPU to the wakeup list, so when interrupts happen
7221 * we can find the right vCPU to wake up.
7222 * - Change the Posted-interrupt descriptor as below:
7223 * 'NDST' <-- vcpu->pre_pcpu
7224 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
7225 * - If 'ON' is set during this process, which means at least one
7226 * interrupt is posted for this vCPU, we cannot block it, in
7227 * this case, return 1, otherwise, return 0.
7230 static int pi_pre_block(struct kvm_vcpu *vcpu)
7233 struct pi_desc old, new;
7234 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7236 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
7237 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7238 !kvm_vcpu_apicv_active(vcpu))
7241 WARN_ON(irqs_disabled());
7242 local_irq_disable();
7243 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
7244 vcpu->pre_pcpu = vcpu->cpu;
7245 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7246 list_add_tail(&vcpu->blocked_vcpu_list,
7247 &per_cpu(blocked_vcpu_on_cpu,
7249 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7253 old.control = new.control = pi_desc->control;
7255 WARN((pi_desc->sn == 1),
7256 "Warning: SN field of posted-interrupts "
7257 "is set before blocking\n");
7260 * Since vCPU can be preempted during this process,
7261 * vcpu->cpu could be different with pre_pcpu, we
7262 * need to set pre_pcpu as the destination of wakeup
7263 * notification event, then we can find the right vCPU
7264 * to wakeup in wakeup handler if interrupts happen
7265 * when the vCPU is in blocked state.
7267 dest = cpu_physical_id(vcpu->pre_pcpu);
7269 if (x2apic_enabled())
7272 new.ndst = (dest << 8) & 0xFF00;
7274 /* set 'NV' to 'wakeup vector' */
7275 new.nv = POSTED_INTR_WAKEUP_VECTOR;
7276 } while (cmpxchg64(&pi_desc->control, old.control,
7277 new.control) != old.control);
7279 /* We should not block the vCPU if an interrupt is posted for it. */
7280 if (pi_test_on(pi_desc) == 1)
7281 __pi_post_block(vcpu);
7284 return (vcpu->pre_pcpu == -1);
7287 static int vmx_pre_block(struct kvm_vcpu *vcpu)
7289 if (pi_pre_block(vcpu))
7292 if (kvm_lapic_hv_timer_in_use(vcpu))
7293 kvm_lapic_switch_to_sw_timer(vcpu);
7298 static void pi_post_block(struct kvm_vcpu *vcpu)
7300 if (vcpu->pre_pcpu == -1)
7303 WARN_ON(irqs_disabled());
7304 local_irq_disable();
7305 __pi_post_block(vcpu);
7309 static void vmx_post_block(struct kvm_vcpu *vcpu)
7311 if (kvm_x86_ops->set_hv_timer)
7312 kvm_lapic_switch_to_hv_timer(vcpu);
7314 pi_post_block(vcpu);
7318 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
7321 * @host_irq: host irq of the interrupt
7322 * @guest_irq: gsi of the interrupt
7323 * @set: set or unset PI
7324 * returns 0 on success, < 0 on failure
7326 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
7327 uint32_t guest_irq, bool set)
7329 struct kvm_kernel_irq_routing_entry *e;
7330 struct kvm_irq_routing_table *irq_rt;
7331 struct kvm_lapic_irq irq;
7332 struct kvm_vcpu *vcpu;
7333 struct vcpu_data vcpu_info;
7336 if (!kvm_arch_has_assigned_device(kvm) ||
7337 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7338 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
7341 idx = srcu_read_lock(&kvm->irq_srcu);
7342 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
7343 if (guest_irq >= irq_rt->nr_rt_entries ||
7344 hlist_empty(&irq_rt->map[guest_irq])) {
7345 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
7346 guest_irq, irq_rt->nr_rt_entries);
7350 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
7351 if (e->type != KVM_IRQ_ROUTING_MSI)
7354 * VT-d PI cannot support posting multicast/broadcast
7355 * interrupts to a vCPU, we still use interrupt remapping
7356 * for these kind of interrupts.
7358 * For lowest-priority interrupts, we only support
7359 * those with single CPU as the destination, e.g. user
7360 * configures the interrupts via /proc/irq or uses
7361 * irqbalance to make the interrupts single-CPU.
7363 * We will support full lowest-priority interrupt later.
7365 * In addition, we can only inject generic interrupts using
7366 * the PI mechanism, refuse to route others through it.
7369 kvm_set_msi_irq(kvm, e, &irq);
7370 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) ||
7371 !kvm_irq_is_postable(&irq)) {
7373 * Make sure the IRTE is in remapped mode if
7374 * we don't handle it in posted mode.
7376 ret = irq_set_vcpu_affinity(host_irq, NULL);
7379 "failed to back to remapped mode, irq: %u\n",
7387 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
7388 vcpu_info.vector = irq.vector;
7390 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
7391 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
7394 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
7396 ret = irq_set_vcpu_affinity(host_irq, NULL);
7399 printk(KERN_INFO "%s: failed to update PI IRTE\n",
7407 srcu_read_unlock(&kvm->irq_srcu, idx);
7411 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7413 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7414 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7415 FEATURE_CONTROL_LMCE;
7417 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7418 ~FEATURE_CONTROL_LMCE;
7421 static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
7423 /* we need a nested vmexit to enter SMM, postpone if run is pending */
7424 if (to_vmx(vcpu)->nested.nested_run_pending)
7429 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7431 struct vcpu_vmx *vmx = to_vmx(vcpu);
7433 vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7434 if (vmx->nested.smm.guest_mode)
7435 nested_vmx_vmexit(vcpu, -1, 0, 0);
7437 vmx->nested.smm.vmxon = vmx->nested.vmxon;
7438 vmx->nested.vmxon = false;
7439 vmx_clear_hlt(vcpu);
7443 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
7445 struct vcpu_vmx *vmx = to_vmx(vcpu);
7448 if (vmx->nested.smm.vmxon) {
7449 vmx->nested.vmxon = true;
7450 vmx->nested.smm.vmxon = false;
7453 if (vmx->nested.smm.guest_mode) {
7454 ret = nested_vmx_enter_non_root_mode(vcpu, false);
7458 vmx->nested.smm.guest_mode = false;
7463 static int enable_smi_window(struct kvm_vcpu *vcpu)
7468 static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7473 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7475 return to_vmx(vcpu)->nested.vmxon;
7478 static __init int hardware_setup(void)
7480 unsigned long host_bndcfgs;
7484 rdmsrl_safe(MSR_EFER, &host_efer);
7487 host_idt_base = dt.address;
7489 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7490 kvm_define_shared_msr(i, vmx_msr_index[i]);
7492 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7495 if (boot_cpu_has(X86_FEATURE_NX))
7496 kvm_enable_efer_bits(EFER_NX);
7498 if (boot_cpu_has(X86_FEATURE_MPX)) {
7499 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7500 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7503 if (boot_cpu_has(X86_FEATURE_XSAVES))
7504 rdmsrl(MSR_IA32_XSS, host_xss);
7506 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7507 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7510 if (!cpu_has_vmx_ept() ||
7511 !cpu_has_vmx_ept_4levels() ||
7512 !cpu_has_vmx_ept_mt_wb() ||
7513 !cpu_has_vmx_invept_global())
7516 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7517 enable_ept_ad_bits = 0;
7519 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7520 enable_unrestricted_guest = 0;
7522 if (!cpu_has_vmx_flexpriority())
7523 flexpriority_enabled = 0;
7525 if (!cpu_has_virtual_nmis())
7529 * set_apic_access_page_addr() is used to reload apic access
7530 * page upon invalidation. No need to do anything if not
7531 * using the APIC_ACCESS_ADDR VMCS field.
7533 if (!flexpriority_enabled)
7534 kvm_x86_ops->set_apic_access_page_addr = NULL;
7536 if (!cpu_has_vmx_tpr_shadow())
7537 kvm_x86_ops->update_cr8_intercept = NULL;
7539 if (enable_ept && !cpu_has_vmx_ept_2m_page())
7540 kvm_disable_largepages();
7542 #if IS_ENABLED(CONFIG_HYPERV)
7543 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7545 kvm_x86_ops->tlb_remote_flush = hv_remote_flush_tlb;
7546 kvm_x86_ops->tlb_remote_flush_with_range =
7547 hv_remote_flush_tlb_with_range;
7551 if (!cpu_has_vmx_ple()) {
7554 ple_window_grow = 0;
7556 ple_window_shrink = 0;
7559 if (!cpu_has_vmx_apicv()) {
7561 kvm_x86_ops->sync_pir_to_irr = NULL;
7564 if (cpu_has_vmx_tsc_scaling()) {
7565 kvm_has_tsc_control = true;
7566 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7567 kvm_tsc_scaling_ratio_frac_bits = 48;
7570 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7578 * Only enable PML when hardware supports PML feature, and both EPT
7579 * and EPT A/D bit features are enabled -- PML depends on them to work.
7581 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7585 kvm_x86_ops->slot_enable_log_dirty = NULL;
7586 kvm_x86_ops->slot_disable_log_dirty = NULL;
7587 kvm_x86_ops->flush_log_dirty = NULL;
7588 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7591 if (!cpu_has_vmx_preemption_timer())
7592 enable_preemption_timer = false;
7594 if (enable_preemption_timer) {
7595 u64 use_timer_freq = 5000ULL * 1000 * 1000;
7598 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7599 cpu_preemption_timer_multi =
7600 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7603 use_timer_freq = (u64)tsc_khz * 1000;
7604 use_timer_freq >>= cpu_preemption_timer_multi;
7607 * KVM "disables" the preemption timer by setting it to its max
7608 * value. Don't use the timer if it might cause spurious exits
7609 * at a rate faster than 0.1 Hz (of uninterrupted guest time).
7611 if (use_timer_freq > 0xffffffffu / 10)
7612 enable_preemption_timer = false;
7615 if (!enable_preemption_timer) {
7616 kvm_x86_ops->set_hv_timer = NULL;
7617 kvm_x86_ops->cancel_hv_timer = NULL;
7618 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit;
7621 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
7623 kvm_mce_cap_supported |= MCG_LMCE_P;
7625 if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
7627 if (!enable_ept || !cpu_has_vmx_intel_pt())
7628 pt_mode = PT_MODE_SYSTEM;
7631 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
7632 vmx_capability.ept, enable_apicv);
7634 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
7639 r = alloc_kvm_area();
7641 nested_vmx_hardware_unsetup();
7645 static __exit void hardware_unsetup(void)
7648 nested_vmx_hardware_unsetup();
7653 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
7654 .cpu_has_kvm_support = cpu_has_kvm_support,
7655 .disabled_by_bios = vmx_disabled_by_bios,
7656 .hardware_setup = hardware_setup,
7657 .hardware_unsetup = hardware_unsetup,
7658 .check_processor_compatibility = vmx_check_processor_compat,
7659 .hardware_enable = hardware_enable,
7660 .hardware_disable = hardware_disable,
7661 .cpu_has_accelerated_tpr = report_flexpriority,
7662 .has_emulated_msr = vmx_has_emulated_msr,
7664 .vm_init = vmx_vm_init,
7665 .vm_alloc = vmx_vm_alloc,
7666 .vm_free = vmx_vm_free,
7668 .vcpu_create = vmx_create_vcpu,
7669 .vcpu_free = vmx_free_vcpu,
7670 .vcpu_reset = vmx_vcpu_reset,
7672 .prepare_guest_switch = vmx_prepare_switch_to_guest,
7673 .vcpu_load = vmx_vcpu_load,
7674 .vcpu_put = vmx_vcpu_put,
7676 .update_bp_intercept = update_exception_bitmap,
7677 .get_msr_feature = vmx_get_msr_feature,
7678 .get_msr = vmx_get_msr,
7679 .set_msr = vmx_set_msr,
7680 .get_segment_base = vmx_get_segment_base,
7681 .get_segment = vmx_get_segment,
7682 .set_segment = vmx_set_segment,
7683 .get_cpl = vmx_get_cpl,
7684 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7685 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7686 .decache_cr3 = vmx_decache_cr3,
7687 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7688 .set_cr0 = vmx_set_cr0,
7689 .set_cr3 = vmx_set_cr3,
7690 .set_cr4 = vmx_set_cr4,
7691 .set_efer = vmx_set_efer,
7692 .get_idt = vmx_get_idt,
7693 .set_idt = vmx_set_idt,
7694 .get_gdt = vmx_get_gdt,
7695 .set_gdt = vmx_set_gdt,
7696 .get_dr6 = vmx_get_dr6,
7697 .set_dr6 = vmx_set_dr6,
7698 .set_dr7 = vmx_set_dr7,
7699 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
7700 .cache_reg = vmx_cache_reg,
7701 .get_rflags = vmx_get_rflags,
7702 .set_rflags = vmx_set_rflags,
7704 .tlb_flush = vmx_flush_tlb,
7705 .tlb_flush_gva = vmx_flush_tlb_gva,
7707 .run = vmx_vcpu_run,
7708 .handle_exit = vmx_handle_exit,
7709 .skip_emulated_instruction = __skip_emulated_instruction,
7710 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7711 .get_interrupt_shadow = vmx_get_interrupt_shadow,
7712 .patch_hypercall = vmx_patch_hypercall,
7713 .set_irq = vmx_inject_irq,
7714 .set_nmi = vmx_inject_nmi,
7715 .queue_exception = vmx_queue_exception,
7716 .cancel_injection = vmx_cancel_injection,
7717 .interrupt_allowed = vmx_interrupt_allowed,
7718 .nmi_allowed = vmx_nmi_allowed,
7719 .get_nmi_mask = vmx_get_nmi_mask,
7720 .set_nmi_mask = vmx_set_nmi_mask,
7721 .enable_nmi_window = enable_nmi_window,
7722 .enable_irq_window = enable_irq_window,
7723 .update_cr8_intercept = update_cr8_intercept,
7724 .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
7725 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
7726 .get_enable_apicv = vmx_get_enable_apicv,
7727 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
7728 .load_eoi_exitmap = vmx_load_eoi_exitmap,
7729 .apicv_post_state_restore = vmx_apicv_post_state_restore,
7730 .hwapic_irr_update = vmx_hwapic_irr_update,
7731 .hwapic_isr_update = vmx_hwapic_isr_update,
7732 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
7733 .sync_pir_to_irr = vmx_sync_pir_to_irr,
7734 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
7735 .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt,
7737 .set_tss_addr = vmx_set_tss_addr,
7738 .set_identity_map_addr = vmx_set_identity_map_addr,
7739 .get_tdp_level = get_ept_level,
7740 .get_mt_mask = vmx_get_mt_mask,
7742 .get_exit_info = vmx_get_exit_info,
7744 .get_lpage_level = vmx_get_lpage_level,
7746 .cpuid_update = vmx_cpuid_update,
7748 .rdtscp_supported = vmx_rdtscp_supported,
7749 .invpcid_supported = vmx_invpcid_supported,
7751 .set_supported_cpuid = vmx_set_supported_cpuid,
7753 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7755 .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
7756 .write_l1_tsc_offset = vmx_write_l1_tsc_offset,
7758 .set_tdp_cr3 = vmx_set_cr3,
7760 .check_intercept = vmx_check_intercept,
7761 .handle_exit_irqoff = vmx_handle_exit_irqoff,
7762 .mpx_supported = vmx_mpx_supported,
7763 .xsaves_supported = vmx_xsaves_supported,
7764 .umip_emulated = vmx_umip_emulated,
7765 .pt_supported = vmx_pt_supported,
7767 .request_immediate_exit = vmx_request_immediate_exit,
7769 .sched_in = vmx_sched_in,
7771 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
7772 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
7773 .flush_log_dirty = vmx_flush_log_dirty,
7774 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
7775 .write_log_dirty = vmx_write_pml_buffer,
7777 .pre_block = vmx_pre_block,
7778 .post_block = vmx_post_block,
7780 .pmu_ops = &intel_pmu_ops,
7782 .update_pi_irte = vmx_update_pi_irte,
7784 #ifdef CONFIG_X86_64
7785 .set_hv_timer = vmx_set_hv_timer,
7786 .cancel_hv_timer = vmx_cancel_hv_timer,
7789 .setup_mce = vmx_setup_mce,
7791 .smi_allowed = vmx_smi_allowed,
7792 .pre_enter_smm = vmx_pre_enter_smm,
7793 .pre_leave_smm = vmx_pre_leave_smm,
7794 .enable_smi_window = enable_smi_window,
7796 .check_nested_events = NULL,
7797 .get_nested_state = NULL,
7798 .set_nested_state = NULL,
7799 .get_vmcs12_pages = NULL,
7800 .nested_enable_evmcs = NULL,
7801 .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault,
7802 .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
7805 static void vmx_cleanup_l1d_flush(void)
7807 if (vmx_l1d_flush_pages) {
7808 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
7809 vmx_l1d_flush_pages = NULL;
7811 /* Restore state so sysfs ignores VMX */
7812 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
7815 static void vmx_exit(void)
7817 #ifdef CONFIG_KEXEC_CORE
7818 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
7824 #if IS_ENABLED(CONFIG_HYPERV)
7825 if (static_branch_unlikely(&enable_evmcs)) {
7827 struct hv_vp_assist_page *vp_ap;
7829 * Reset everything to support using non-enlightened VMCS
7830 * access later (e.g. when we reload the module with
7831 * enlightened_vmcs=0)
7833 for_each_online_cpu(cpu) {
7834 vp_ap = hv_get_vp_assist_page(cpu);
7839 vp_ap->current_nested_vmcs = 0;
7840 vp_ap->enlighten_vmentry = 0;
7843 static_branch_disable(&enable_evmcs);
7846 vmx_cleanup_l1d_flush();
7848 module_exit(vmx_exit);
7850 static int __init vmx_init(void)
7854 #if IS_ENABLED(CONFIG_HYPERV)
7856 * Enlightened VMCS usage should be recommended and the host needs
7857 * to support eVMCS v1 or above. We can also disable eVMCS support
7858 * with module parameter.
7860 if (enlightened_vmcs &&
7861 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
7862 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
7863 KVM_EVMCS_VERSION) {
7866 /* Check that we have assist pages on all online CPUs */
7867 for_each_online_cpu(cpu) {
7868 if (!hv_get_vp_assist_page(cpu)) {
7869 enlightened_vmcs = false;
7874 if (enlightened_vmcs) {
7875 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
7876 static_branch_enable(&enable_evmcs);
7879 enlightened_vmcs = false;
7883 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7884 __alignof__(struct vcpu_vmx), THIS_MODULE);
7889 * Must be called after kvm_init() so enable_ept is properly set
7890 * up. Hand the parameter mitigation value in which was stored in
7891 * the pre module init parser. If no parameter was given, it will
7892 * contain 'auto' which will be turned into the default 'cond'
7895 if (boot_cpu_has(X86_BUG_L1TF)) {
7896 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
7903 #ifdef CONFIG_KEXEC_CORE
7904 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
7905 crash_vmclear_local_loaded_vmcss);
7907 vmx_check_vmcs12_offsets();
7911 module_init(vmx_init);