arch/x86/kvm/vmx/vmx.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Kernel-based Virtual Machine driver for Linux
   4  *
   5  * This module enables machines with Intel VT-x extensions to run virtual
   6  * machines without emulation or binary translation.
   7  *
   8  * Copyright (C) 2006 Qumranet, Inc.
   9  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  10  *
  11  * Authors:
  12  *   Avi Kivity   <avi@qumranet.com>
  13  *   Yaniv Kamay  <yaniv@qumranet.com>
  14  */
  15
  16 #include <linux/frame.h>
  17 #include <linux/highmem.h>
  18 #include <linux/hrtimer.h>
  19 #include <linux/kernel.h>
  20 #include <linux/kvm_host.h>
  21 #include <linux/module.h>
  22 #include <linux/moduleparam.h>
  23 #include <linux/mod_devicetable.h>
  24 #include <linux/mm.h>
  25 #include <linux/sched.h>
  26 #include <linux/sched/smt.h>
  27 #include <linux/slab.h>
  28 #include <linux/tboot.h>
  29 #include <linux/trace_events.h>
  30
  31 #include <asm/apic.h>
  32 #include <asm/asm.h>
  33 #include <asm/cpu.h>
  34 #include <asm/debugreg.h>
  35 #include <asm/desc.h>
  36 #include <asm/fpu/internal.h>
  37 #include <asm/io.h>
  38 #include <asm/irq_remapping.h>
  39 #include <asm/kexec.h>
  40 #include <asm/perf_event.h>
  41 #include <asm/mce.h>
  42 #include <asm/mmu_context.h>
  43 #include <asm/mshyperv.h>
  44 #include <asm/spec-ctrl.h>
  45 #include <asm/virtext.h>
  46 #include <asm/vmx.h>
  47
  48 #include "capabilities.h"
  49 #include "cpuid.h"
  50 #include "evmcs.h"
  51 #include "irq.h"
  52 #include "kvm_cache_regs.h"
  53 #include "lapic.h"
  54 #include "mmu.h"
  55 #include "nested.h"
  56 #include "ops.h"
  57 #include "pmu.h"
  58 #include "trace.h"
  59 #include "vmcs.h"
  60 #include "vmcs12.h"
  61 #include "vmx.h"
  62 #include "x86.h"
  63
  64 MODULE_AUTHOR("Qumranet");
  65 MODULE_LICENSE("GPL");
  66
  67 static const struct x86_cpu_id vmx_cpu_id[] = {
  68         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  69         {}
  70 };
  71 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  72
  73 bool __read_mostly enable_vpid = 1;
  74 module_param_named(vpid, enable_vpid, bool, 0444);
  75
  76 static bool __read_mostly enable_vnmi = 1;
  77 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
  78
  79 bool __read_mostly flexpriority_enabled = 1;
  80 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  81
  82 bool __read_mostly enable_ept = 1;
  83 module_param_named(ept, enable_ept, bool, S_IRUGO);
  84
  85 bool __read_mostly enable_unrestricted_guest = 1;
  86 module_param_named(unrestricted_guest,
  87                         enable_unrestricted_guest, bool, S_IRUGO);
  88
  89 bool __read_mostly enable_ept_ad_bits = 1;
  90 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  91
  92 static bool __read_mostly emulate_invalid_guest_state = true;
  93 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  94
  95 static bool __read_mostly fasteoi = 1;
  96 module_param(fasteoi, bool, S_IRUGO);
  97
  98 bool __read_mostly enable_apicv = 1;
  99 module_param(enable_apicv, bool, S_IRUGO);
 100
 101 /*
 102  * If nested=1, nested virtualization is supported, i.e., guests may use
 103  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 104  * use VMX instructions.
 105  */
 106 static bool __read_mostly nested = 1;
 107 module_param(nested, bool, S_IRUGO);
 108
 109 bool __read_mostly enable_pml = 1;
 110 module_param_named(pml, enable_pml, bool, S_IRUGO);
 111
 112 static bool __read_mostly dump_invalid_vmcs = 0;
 113 module_param(dump_invalid_vmcs, bool, 0644);
 114
 115 #define MSR_BITMAP_MODE_X2APIC          1
 116 #define MSR_BITMAP_MODE_X2APIC_APICV    2
 117
 118 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 119
 120 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 121 static int __read_mostly cpu_preemption_timer_multi;
 122 static bool __read_mostly enable_preemption_timer = 1;
 123 #ifdef CONFIG_X86_64
 124 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 125 #endif
 126
 127 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
 128 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
 129 #define KVM_VM_CR0_ALWAYS_ON                            \
 130         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST |      \
 131          X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
 132 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 133         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 134          | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
 135
 136 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
 137 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 138 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 139
 140 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 141
 142 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
 143         RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
 144         RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
 145         RTIT_STATUS_BYTECNT))
 146
 147 #define MSR_IA32_RTIT_OUTPUT_BASE_MASK \
 148         (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f)
 149
 150 /*
 151  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 152  * ple_gap:    upper bound on the amount of time between two successive
 153  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 154  *             According to test, this time is usually smaller than 128 cycles.
 155  * ple_window: upper bound on the amount of time a guest is allowed to execute
 156  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 157  *             less than 2^12 cycles
 158  * Time is measured based on a counter that runs at the same rate as the TSC,
 159  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 160  */
 161 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
 162 module_param(ple_gap, uint, 0444);
 163
 164 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 165 module_param(ple_window, uint, 0444);
 166
 167 /* Default doubles per-vcpu window every exit. */
 168 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 169 module_param(ple_window_grow, uint, 0444);
 170
 171 /* Default resets per-vcpu window every exit to ple_window. */
 172 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 173 module_param(ple_window_shrink, uint, 0444);
 174
 175 /* Default is to compute the maximum so we can never overflow. */
 176 static unsigned int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 177 module_param(ple_window_max, uint, 0444);
 178
 179 /* Default is SYSTEM mode, 1 for host-guest mode */
 180 int __read_mostly pt_mode = PT_MODE_SYSTEM;
 181 module_param(pt_mode, int, S_IRUGO);
 182
 183 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
 184 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
 185 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
 186
 187 /* Storage for pre module init parameter parsing */
 188 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
 189
 190 static const struct {
 191         const char *option;
 192         bool for_parse;
 193 } vmentry_l1d_param[] = {
 194         [VMENTER_L1D_FLUSH_AUTO]         = {"auto", true},
 195         [VMENTER_L1D_FLUSH_NEVER]        = {"never", true},
 196         [VMENTER_L1D_FLUSH_COND]         = {"cond", true},
 197         [VMENTER_L1D_FLUSH_ALWAYS]       = {"always", true},
 198         [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
 199         [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
 200 };
 201
 202 #define L1D_CACHE_ORDER 4
 203 static void *vmx_l1d_flush_pages;
 204
 205 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
 206 {
 207         struct page *page;
 208         unsigned int i;
 209
 210         if (!boot_cpu_has_bug(X86_BUG_L1TF)) {
 211                 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
 212                 return 0;
 213         }
 214
 215         if (!enable_ept) {
 216                 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
 217                 return 0;
 218         }
 219
 220         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
 221                 u64 msr;
 222
 223                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
 224                 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
 225                         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
 226                         return 0;
 227                 }
 228         }
 229
 230         /* If set to auto use the default l1tf mitigation method */
 231         if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
 232                 switch (l1tf_mitigation) {
 233                 case L1TF_MITIGATION_OFF:
 234                         l1tf = VMENTER_L1D_FLUSH_NEVER;
 235                         break;
 236                 case L1TF_MITIGATION_FLUSH_NOWARN:
 237                 case L1TF_MITIGATION_FLUSH:
 238                 case L1TF_MITIGATION_FLUSH_NOSMT:
 239                         l1tf = VMENTER_L1D_FLUSH_COND;
 240                         break;
 241                 case L1TF_MITIGATION_FULL:
 242                 case L1TF_MITIGATION_FULL_FORCE:
 243                         l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 244                         break;
 245                 }
 246         } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
 247                 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 248         }
 249
 250         if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
 251             !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
 252                 /*
 253                  * This allocation for vmx_l1d_flush_pages is not tied to a VM
 254                  * lifetime and so should not be charged to a memcg.
 255                  */
 256                 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
 257                 if (!page)
 258                         return -ENOMEM;
 259                 vmx_l1d_flush_pages = page_address(page);
 260
 261                 /*
 262                  * Initialize each page with a different pattern in
 263                  * order to protect against KSM in the nested
 264                  * virtualization case.
 265                  */
 266                 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
 267                         memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
 268                                PAGE_SIZE);
 269                 }
 270         }
 271
 272         l1tf_vmx_mitigation = l1tf;
 273
 274         if (l1tf != VMENTER_L1D_FLUSH_NEVER)
 275                 static_branch_enable(&vmx_l1d_should_flush);
 276         else
 277                 static_branch_disable(&vmx_l1d_should_flush);
 278
 279         if (l1tf == VMENTER_L1D_FLUSH_COND)
 280                 static_branch_enable(&vmx_l1d_flush_cond);
 281         else
 282                 static_branch_disable(&vmx_l1d_flush_cond);
 283         return 0;
 284 }
 285
 286 static int vmentry_l1d_flush_parse(const char *s)
 287 {
 288         unsigned int i;
 289
 290         if (s) {
 291                 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
 292                         if (vmentry_l1d_param[i].for_parse &&
 293                             sysfs_streq(s, vmentry_l1d_param[i].option))
 294                                 return i;
 295                 }
 296         }
 297         return -EINVAL;
 298 }
 299
 300 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
 301 {
 302         int l1tf, ret;
 303
 304         l1tf = vmentry_l1d_flush_parse(s);
 305         if (l1tf < 0)
 306                 return l1tf;
 307
 308         if (!boot_cpu_has(X86_BUG_L1TF))
 309                 return 0;
 310
 311         /*
 312          * Has vmx_init() run already? If not then this is the pre init
 313          * parameter parsing. In that case just store the value and let
 314          * vmx_init() do the proper setup after enable_ept has been
 315          * established.
 316          */
 317         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
 318                 vmentry_l1d_flush_param = l1tf;
 319                 return 0;
 320         }
 321
 322         mutex_lock(&vmx_l1d_flush_mutex);
 323         ret = vmx_setup_l1d_flush(l1tf);
 324         mutex_unlock(&vmx_l1d_flush_mutex);
 325         return ret;
 326 }
 327
 328 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
 329 {
 330         if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
 331                 return sprintf(s, "???\n");
 332
 333         return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
 334 }
 335
 336 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
 337         .set = vmentry_l1d_flush_set,
 338         .get = vmentry_l1d_flush_get,
 339 };
 340 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
 341
 342 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 343 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 344 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
 345                                                           u32 msr, int type);
 346
 347 void vmx_vmexit(void);
 348
 349 #define vmx_insn_failed(fmt...)         \
 350 do {                                    \
 351         WARN_ONCE(1, fmt);              \
 352         pr_warn_ratelimited(fmt);       \
 353 } while (0)
 354
 355 asmlinkage void vmread_error(unsigned long field, bool fault)
 356 {
 357         if (fault)
 358                 kvm_spurious_fault();
 359         else
 360                 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field);
 361 }
 362
 363 noinline void vmwrite_error(unsigned long field, unsigned long value)
 364 {
 365         vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n",
 366                         field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 367 }
 368
 369 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr)
 370 {
 371         vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr);
 372 }
 373
 374 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr)
 375 {
 376         vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr);
 377 }
 378
 379 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva)
 380 {
 381         vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n",
 382                         ext, vpid, gva);
 383 }
 384
 385 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa)
 386 {
 387         vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n",
 388                         ext, eptp, gpa);
 389 }
 390
 391 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 392 DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 393 /*
 394  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 395  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 396  */
 397 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 398
 399 /*
 400  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 401  * can find which vCPU should be waken up.
 402  */
 403 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 404 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 405
 406 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 407 static DEFINE_SPINLOCK(vmx_vpid_lock);
 408
 409 struct vmcs_config vmcs_config;
 410 struct vmx_capability vmx_capability;
 411
 412 #define VMX_SEGMENT_FIELD(seg)                                  \
 413         [VCPU_SREG_##seg] = {                                   \
 414                 .selector = GUEST_##seg##_SELECTOR,             \
 415                 .base = GUEST_##seg##_BASE,                     \
 416                 .limit = GUEST_##seg##_LIMIT,                   \
 417                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 418         }
 419
 420 static const struct kvm_vmx_segment_field {
 421         unsigned selector;
 422         unsigned base;
 423         unsigned limit;
 424         unsigned ar_bytes;
 425 } kvm_vmx_segment_fields[] = {
 426         VMX_SEGMENT_FIELD(CS),
 427         VMX_SEGMENT_FIELD(DS),
 428         VMX_SEGMENT_FIELD(ES),
 429         VMX_SEGMENT_FIELD(FS),
 430         VMX_SEGMENT_FIELD(GS),
 431         VMX_SEGMENT_FIELD(SS),
 432         VMX_SEGMENT_FIELD(TR),
 433         VMX_SEGMENT_FIELD(LDTR),
 434 };
 435
 436 static unsigned long host_idt_base;
 437
 438 /*
 439  * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
 440  * will emulate SYSCALL in legacy mode if the vendor string in guest
 441  * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
 442  * support this emulation, IA32_STAR must always be included in
 443  * vmx_msr_index[], even in i386 builds.
 444  */
 445 const u32 vmx_msr_index[] = {
 446 #ifdef CONFIG_X86_64
 447         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 448 #endif
 449         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 450         MSR_IA32_TSX_CTRL,
 451 };
 452
 453 #if IS_ENABLED(CONFIG_HYPERV)
 454 static bool __read_mostly enlightened_vmcs = true;
 455 module_param(enlightened_vmcs, bool, 0444);
 456
 457 /* check_ept_pointer() should be under protection of ept_pointer_lock. */
 458 static void check_ept_pointer_match(struct kvm *kvm)
 459 {
 460         struct kvm_vcpu *vcpu;
 461         u64 tmp_eptp = INVALID_PAGE;
 462         int i;
 463
 464         kvm_for_each_vcpu(i, vcpu, kvm) {
 465                 if (!VALID_PAGE(tmp_eptp)) {
 466                         tmp_eptp = to_vmx(vcpu)->ept_pointer;
 467                 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
 468                         to_kvm_vmx(kvm)->ept_pointers_match
 469                                 = EPT_POINTERS_MISMATCH;
 470                         return;
 471                 }
 472         }
 473
 474         to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
 475 }
 476
 477 static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush,
 478                 void *data)
 479 {
 480         struct kvm_tlb_range *range = data;
 481
 482         return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn,
 483                         range->pages);
 484 }
 485
 486 static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm,
 487                 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range)
 488 {
 489         u64 ept_pointer = to_vmx(vcpu)->ept_pointer;
 490
 491         /*
 492          * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address
 493          * of the base of EPT PML4 table, strip off EPT configuration
 494          * information.
 495          */
 496         if (range)
 497                 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK,
 498                                 kvm_fill_hv_flush_list_func, (void *)range);
 499         else
 500                 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK);
 501 }
 502
 503 static int hv_remote_flush_tlb_with_range(struct kvm *kvm,
 504                 struct kvm_tlb_range *range)
 505 {
 506         struct kvm_vcpu *vcpu;
 507         int ret = 0, i;
 508
 509         spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
 510
 511         if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
 512                 check_ept_pointer_match(kvm);
 513
 514         if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
 515                 kvm_for_each_vcpu(i, vcpu, kvm) {
 516                         /* If ept_pointer is invalid pointer, bypass flush request. */
 517                         if (VALID_PAGE(to_vmx(vcpu)->ept_pointer))
 518                                 ret |= __hv_remote_flush_tlb_with_range(
 519                                         kvm, vcpu, range);
 520                 }
 521         } else {
 522                 ret = __hv_remote_flush_tlb_with_range(kvm,
 523                                 kvm_get_vcpu(kvm, 0), range);
 524         }
 525
 526         spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
 527         return ret;
 528 }
 529 static int hv_remote_flush_tlb(struct kvm *kvm)
 530 {
 531         return hv_remote_flush_tlb_with_range(kvm, NULL);
 532 }
 533
 534 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
 535 {
 536         struct hv_enlightened_vmcs *evmcs;
 537         struct hv_partition_assist_pg **p_hv_pa_pg =
 538                         &vcpu->kvm->arch.hyperv.hv_pa_pg;
 539         /*
 540          * Synthetic VM-Exit is not enabled in current code and so All
 541          * evmcs in singe VM shares same assist page.
 542          */
 543         if (!*p_hv_pa_pg)
 544                 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL);
 545
 546         if (!*p_hv_pa_pg)
 547                 return -ENOMEM;
 548
 549         evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
 550
 551         evmcs->partition_assist_page =
 552                 __pa(*p_hv_pa_pg);
 553         evmcs->hv_vm_id = (unsigned long)vcpu->kvm;
 554         evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
 555
 556         return 0;
 557 }
 558
 559 #endif /* IS_ENABLED(CONFIG_HYPERV) */
 560
 561 /*
 562  * Comment's format: document - errata name - stepping - processor name.
 563  * Refer from
 564  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
 565  */
 566 static u32 vmx_preemption_cpu_tfms[] = {
 567 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
 568 0x000206E6,
 569 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
 570 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
 571 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
 572 0x00020652,
 573 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
 574 0x00020655,
 575 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
 576 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
 577 /*
 578  * 320767.pdf - AAP86  - B1 -
 579  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
 580  */
 581 0x000106E5,
 582 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
 583 0x000106A0,
 584 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
 585 0x000106A1,
 586 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
 587 0x000106A4,
 588  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
 589  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
 590  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
 591 0x000106A5,
 592  /* Xeon E3-1220 V2 */
 593 0x000306A8,
 594 };
 595
 596 static inline bool cpu_has_broken_vmx_preemption_timer(void)
 597 {
 598         u32 eax = cpuid_eax(0x00000001), i;
 599
 600         /* Clear the reserved bits */
 601         eax &= ~(0x3U << 14 | 0xfU << 28);
 602         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
 603                 if (eax == vmx_preemption_cpu_tfms[i])
 604                         return true;
 605
 606         return false;
 607 }
 608
 609 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
 610 {
 611         return flexpriority_enabled && lapic_in_kernel(vcpu);
 612 }
 613
 614 static inline bool report_flexpriority(void)
 615 {
 616         return flexpriority_enabled;
 617 }
 618
 619 static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 620 {
 621         int i;
 622
 623         for (i = 0; i < vmx->nmsrs; ++i)
 624                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 625                         return i;
 626         return -1;
 627 }
 628
 629 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 630 {
 631         int i;
 632
 633         i = __find_msr_index(vmx, msr);
 634         if (i >= 0)
 635                 return &vmx->guest_msrs[i];
 636         return NULL;
 637 }
 638
 639 static int vmx_set_guest_msr(struct vcpu_vmx *vmx, struct shared_msr_entry *msr, u64 data)
 640 {
 641         int ret = 0;
 642
 643         u64 old_msr_data = msr->data;
 644         msr->data = data;
 645         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
 646                 preempt_disable();
 647                 ret = kvm_set_shared_msr(msr->index, msr->data,
 648                                          msr->mask);
 649                 preempt_enable();
 650                 if (ret)
 651                         msr->data = old_msr_data;
 652         }
 653         return ret;
 654 }
 655
 656 #ifdef CONFIG_KEXEC_CORE
 657 static void crash_vmclear_local_loaded_vmcss(void)
 658 {
 659         int cpu = raw_smp_processor_id();
 660         struct loaded_vmcs *v;
 661
 662         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
 663                             loaded_vmcss_on_cpu_link)
 664                 vmcs_clear(v->vmcs);
 665 }
 666 #endif /* CONFIG_KEXEC_CORE */
 667
 668 static void __loaded_vmcs_clear(void *arg)
 669 {
 670         struct loaded_vmcs *loaded_vmcs = arg;
 671         int cpu = raw_smp_processor_id();
 672
 673         if (loaded_vmcs->cpu != cpu)
 674                 return; /* vcpu migration can race with cpu offline */
 675         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
 676                 per_cpu(current_vmcs, cpu) = NULL;
 677
 678         vmcs_clear(loaded_vmcs->vmcs);
 679         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
 680                 vmcs_clear(loaded_vmcs->shadow_vmcs);
 681
 682         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
 683
 684         /*
 685          * Ensure all writes to loaded_vmcs, including deleting it from its
 686          * current percpu list, complete before setting loaded_vmcs->vcpu to
 687          * -1, otherwise a different cpu can see vcpu == -1 first and add
 688          * loaded_vmcs to its percpu list before it's deleted from this cpu's
 689          * list. Pairs with the smp_rmb() in vmx_vcpu_load_vmcs().
 690          */
 691         smp_wmb();
 692
 693         loaded_vmcs->cpu = -1;
 694         loaded_vmcs->launched = 0;
 695 }
 696
 697 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
 698 {
 699         int cpu = loaded_vmcs->cpu;
 700
 701         if (cpu != -1)
 702                 smp_call_function_single(cpu,
 703                          __loaded_vmcs_clear, loaded_vmcs, 1);
 704 }
 705
 706 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
 707                                        unsigned field)
 708 {
 709         bool ret;
 710         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
 711
 712         if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) {
 713                 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS);
 714                 vmx->segment_cache.bitmask = 0;
 715         }
 716         ret = vmx->segment_cache.bitmask & mask;
 717         vmx->segment_cache.bitmask |= mask;
 718         return ret;
 719 }
 720
 721 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
 722 {
 723         u16 *p = &vmx->segment_cache.seg[seg].selector;
 724
 725         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
 726                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
 727         return *p;
 728 }
 729
 730 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
 731 {
 732         ulong *p = &vmx->segment_cache.seg[seg].base;
 733
 734         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
 735                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
 736         return *p;
 737 }
 738
 739 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
 740 {
 741         u32 *p = &vmx->segment_cache.seg[seg].limit;
 742
 743         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
 744                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
 745         return *p;
 746 }
 747
 748 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
 749 {
 750         u32 *p = &vmx->segment_cache.seg[seg].ar;
 751
 752         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
 753                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
 754         return *p;
 755 }
 756
 757 void update_exception_bitmap(struct kvm_vcpu *vcpu)
 758 {
 759         u32 eb;
 760
 761         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
 762              (1u << DB_VECTOR) | (1u << AC_VECTOR);
 763         /*
 764          * Guest access to VMware backdoor ports could legitimately
 765          * trigger #GP because of TSS I/O permission bitmap.
 766          * We intercept those #GP and allow access to them anyway
 767          * as VMware does.
 768          */
 769         if (enable_vmware_backdoor)
 770                 eb |= (1u << GP_VECTOR);
 771         if ((vcpu->guest_debug &
 772              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
 773             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
 774                 eb |= 1u << BP_VECTOR;
 775         if (to_vmx(vcpu)->rmode.vm86_active)
 776                 eb = ~0;
 777         if (enable_ept)
 778                 eb &= ~(1u << PF_VECTOR);
 779
 780         /* When we are running a nested L2 guest and L1 specified for it a
 781          * certain exception bitmap, we must trap the same exceptions and pass
 782          * them to L1. When running L2, we will only handle the exceptions
 783          * specified above if L1 did not want them.
 784          */
 785         if (is_guest_mode(vcpu))
 786                 eb |= get_vmcs12(vcpu)->exception_bitmap;
 787
 788         vmcs_write32(EXCEPTION_BITMAP, eb);
 789 }
 790
 791 /*
 792  * Check if MSR is intercepted for currently loaded MSR bitmap.
 793  */
 794 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
 795 {
 796         unsigned long *msr_bitmap;
 797         int f = sizeof(unsigned long);
 798
 799         if (!cpu_has_vmx_msr_bitmap())
 800                 return true;
 801
 802         msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
 803
 804         if (msr <= 0x1fff) {
 805                 return !!test_bit(msr, msr_bitmap + 0x800 / f);
 806         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
 807                 msr &= 0x1fff;
 808                 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
 809         }
 810
 811         return true;
 812 }
 813
 814 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
 815                 unsigned long entry, unsigned long exit)
 816 {
 817         vm_entry_controls_clearbit(vmx, entry);
 818         vm_exit_controls_clearbit(vmx, exit);
 819 }
 820
 821 int vmx_find_msr_index(struct vmx_msrs *m, u32 msr)
 822 {
 823         unsigned int i;
 824
 825         for (i = 0; i < m->nr; ++i) {
 826                 if (m->val[i].index == msr)
 827                         return i;
 828         }
 829         return -ENOENT;
 830 }
 831
 832 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
 833 {
 834         int i;
 835         struct msr_autoload *m = &vmx->msr_autoload;
 836
 837         switch (msr) {
 838         case MSR_EFER:
 839                 if (cpu_has_load_ia32_efer()) {
 840                         clear_atomic_switch_msr_special(vmx,
 841                                         VM_ENTRY_LOAD_IA32_EFER,
 842                                         VM_EXIT_LOAD_IA32_EFER);
 843                         return;
 844                 }
 845                 break;
 846         case MSR_CORE_PERF_GLOBAL_CTRL:
 847                 if (cpu_has_load_perf_global_ctrl()) {
 848                         clear_atomic_switch_msr_special(vmx,
 849                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
 850                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
 851                         return;
 852                 }
 853                 break;
 854         }
 855         i = vmx_find_msr_index(&m->guest, msr);
 856         if (i < 0)
 857                 goto skip_guest;
 858         --m->guest.nr;
 859         m->guest.val[i] = m->guest.val[m->guest.nr];
 860         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
 861
 862 skip_guest:
 863         i = vmx_find_msr_index(&m->host, msr);
 864         if (i < 0)
 865                 return;
 866
 867         --m->host.nr;
 868         m->host.val[i] = m->host.val[m->host.nr];
 869         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
 870 }
 871
 872 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
 873                 unsigned long entry, unsigned long exit,
 874                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
 875                 u64 guest_val, u64 host_val)
 876 {
 877         vmcs_write64(guest_val_vmcs, guest_val);
 878         if (host_val_vmcs != HOST_IA32_EFER)
 879                 vmcs_write64(host_val_vmcs, host_val);
 880         vm_entry_controls_setbit(vmx, entry);
 881         vm_exit_controls_setbit(vmx, exit);
 882 }
 883
 884 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
 885                                   u64 guest_val, u64 host_val, bool entry_only)
 886 {
 887         int i, j = 0;
 888         struct msr_autoload *m = &vmx->msr_autoload;
 889
 890         switch (msr) {
 891         case MSR_EFER:
 892                 if (cpu_has_load_ia32_efer()) {
 893                         add_atomic_switch_msr_special(vmx,
 894                                         VM_ENTRY_LOAD_IA32_EFER,
 895                                         VM_EXIT_LOAD_IA32_EFER,
 896                                         GUEST_IA32_EFER,
 897                                         HOST_IA32_EFER,
 898                                         guest_val, host_val);
 899                         return;
 900                 }
 901                 break;
 902         case MSR_CORE_PERF_GLOBAL_CTRL:
 903                 if (cpu_has_load_perf_global_ctrl()) {
 904                         add_atomic_switch_msr_special(vmx,
 905                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
 906                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
 907                                         GUEST_IA32_PERF_GLOBAL_CTRL,
 908                                         HOST_IA32_PERF_GLOBAL_CTRL,
 909                                         guest_val, host_val);
 910                         return;
 911                 }
 912                 break;
 913         case MSR_IA32_PEBS_ENABLE:
 914                 /* PEBS needs a quiescent period after being disabled (to write
 915                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
 916                  * provide that period, so a CPU could write host's record into
 917                  * guest's memory.
 918                  */
 919                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
 920         }
 921
 922         i = vmx_find_msr_index(&m->guest, msr);
 923         if (!entry_only)
 924                 j = vmx_find_msr_index(&m->host, msr);
 925
 926         if ((i < 0 && m->guest.nr == NR_LOADSTORE_MSRS) ||
 927                 (j < 0 &&  m->host.nr == NR_LOADSTORE_MSRS)) {
 928                 printk_once(KERN_WARNING "Not enough msr switch entries. "
 929                                 "Can't add msr %x\n", msr);
 930                 return;
 931         }
 932         if (i < 0) {
 933                 i = m->guest.nr++;
 934                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
 935         }
 936         m->guest.val[i].index = msr;
 937         m->guest.val[i].value = guest_val;
 938
 939         if (entry_only)
 940                 return;
 941
 942         if (j < 0) {
 943                 j = m->host.nr++;
 944                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
 945         }
 946         m->host.val[j].index = msr;
 947         m->host.val[j].value = host_val;
 948 }
 949
 950 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
 951 {
 952         u64 guest_efer = vmx->vcpu.arch.efer;
 953         u64 ignore_bits = 0;
 954
 955         /* Shadow paging assumes NX to be available.  */
 956         if (!enable_ept)
 957                 guest_efer |= EFER_NX;
 958
 959         /*
 960          * LMA and LME handled by hardware; SCE meaningless outside long mode.
 961          */
 962         ignore_bits |= EFER_SCE;
 963 #ifdef CONFIG_X86_64
 964         ignore_bits |= EFER_LMA | EFER_LME;
 965         /* SCE is meaningful only in long mode on Intel */
 966         if (guest_efer & EFER_LMA)
 967                 ignore_bits &= ~(u64)EFER_SCE;
 968 #endif
 969
 970         /*
 971          * On EPT, we can't emulate NX, so we must switch EFER atomically.
 972          * On CPUs that support "load IA32_EFER", always switch EFER
 973          * atomically, since it's faster than switching it manually.
 974          */
 975         if (cpu_has_load_ia32_efer() ||
 976             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
 977                 if (!(guest_efer & EFER_LMA))
 978                         guest_efer &= ~EFER_LME;
 979                 if (guest_efer != host_efer)
 980                         add_atomic_switch_msr(vmx, MSR_EFER,
 981                                               guest_efer, host_efer, false);
 982                 else
 983                         clear_atomic_switch_msr(vmx, MSR_EFER);
 984                 return false;
 985         } else {
 986                 clear_atomic_switch_msr(vmx, MSR_EFER);
 987
 988                 guest_efer &= ~ignore_bits;
 989                 guest_efer |= host_efer & ignore_bits;
 990
 991                 vmx->guest_msrs[efer_offset].data = guest_efer;
 992                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
 993
 994                 return true;
 995         }
 996 }
 997
 998 #ifdef CONFIG_X86_32
 999 /*
1000  * On 32-bit kernels, VM exits still load the FS and GS bases from the
1001  * VMCS rather than the segment table.  KVM uses this helper to figure
1002  * out the current bases to poke them into the VMCS before entry.
1003  */
1004 static unsigned long segment_base(u16 selector)
1005 {
1006         struct desc_struct *table;
1007         unsigned long v;
1008
1009         if (!(selector & ~SEGMENT_RPL_MASK))
1010                 return 0;
1011
1012         table = get_current_gdt_ro();
1013
1014         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
1015                 u16 ldt_selector = kvm_read_ldt();
1016
1017                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
1018                         return 0;
1019
1020                 table = (struct desc_struct *)segment_base(ldt_selector);
1021         }
1022         v = get_desc_base(&table[selector >> 3]);
1023         return v;
1024 }
1025 #endif
1026
1027 static inline bool pt_can_write_msr(struct vcpu_vmx *vmx)
1028 {
1029         return vmx_pt_mode_is_host_guest() &&
1030                !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
1031 }
1032
1033 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
1034 {
1035         u32 i;
1036
1037         wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1038         wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1039         wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1040         wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1041         for (i = 0; i < addr_range; i++) {
1042                 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1043                 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1044         }
1045 }
1046
1047 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
1048 {
1049         u32 i;
1050
1051         rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1052         rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1053         rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1054         rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1055         for (i = 0; i < addr_range; i++) {
1056                 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1057                 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1058         }
1059 }
1060
1061 static void pt_guest_enter(struct vcpu_vmx *vmx)
1062 {
1063         if (vmx_pt_mode_is_system())
1064                 return;
1065
1066         /*
1067          * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1068          * Save host state before VM entry.
1069          */
1070         rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1071         if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1072                 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1073                 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1074                 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1075         }
1076 }
1077
1078 static void pt_guest_exit(struct vcpu_vmx *vmx)
1079 {
1080         if (vmx_pt_mode_is_system())
1081                 return;
1082
1083         if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1084                 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1085                 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1086         }
1087
1088         /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1089         wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1090 }
1091
1092 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1093                         unsigned long fs_base, unsigned long gs_base)
1094 {
1095         if (unlikely(fs_sel != host->fs_sel)) {
1096                 if (!(fs_sel & 7))
1097                         vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1098                 else
1099                         vmcs_write16(HOST_FS_SELECTOR, 0);
1100                 host->fs_sel = fs_sel;
1101         }
1102         if (unlikely(gs_sel != host->gs_sel)) {
1103                 if (!(gs_sel & 7))
1104                         vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1105                 else
1106                         vmcs_write16(HOST_GS_SELECTOR, 0);
1107                 host->gs_sel = gs_sel;
1108         }
1109         if (unlikely(fs_base != host->fs_base)) {
1110                 vmcs_writel(HOST_FS_BASE, fs_base);
1111                 host->fs_base = fs_base;
1112         }
1113         if (unlikely(gs_base != host->gs_base)) {
1114                 vmcs_writel(HOST_GS_BASE, gs_base);
1115                 host->gs_base = gs_base;
1116         }
1117 }
1118
1119 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1120 {
1121         struct vcpu_vmx *vmx = to_vmx(vcpu);
1122         struct vmcs_host_state *host_state;
1123 #ifdef CONFIG_X86_64
1124         int cpu = raw_smp_processor_id();
1125 #endif
1126         unsigned long fs_base, gs_base;
1127         u16 fs_sel, gs_sel;
1128         int i;
1129
1130         vmx->req_immediate_exit = false;
1131
1132         /*
1133          * Note that guest MSRs to be saved/restored can also be changed
1134          * when guest state is loaded. This happens when guest transitions
1135          * to/from long-mode by setting MSR_EFER.LMA.
1136          */
1137         if (!vmx->guest_msrs_ready) {
1138                 vmx->guest_msrs_ready = true;
1139                 for (i = 0; i < vmx->save_nmsrs; ++i)
1140                         kvm_set_shared_msr(vmx->guest_msrs[i].index,
1141                                            vmx->guest_msrs[i].data,
1142                                            vmx->guest_msrs[i].mask);
1143
1144         }
1145
1146         if (vmx->nested.need_vmcs12_to_shadow_sync)
1147                 nested_sync_vmcs12_to_shadow(vcpu);
1148
1149         if (vmx->guest_state_loaded)
1150                 return;
1151
1152         host_state = &vmx->loaded_vmcs->host_state;
1153
1154         /*
1155          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1156          * allow segment selectors with cpl > 0 or ti == 1.
1157          */
1158         host_state->ldt_sel = kvm_read_ldt();
1159
1160 #ifdef CONFIG_X86_64
1161         savesegment(ds, host_state->ds_sel);
1162         savesegment(es, host_state->es_sel);
1163
1164         gs_base = cpu_kernelmode_gs_base(cpu);
1165         if (likely(is_64bit_mm(current->mm))) {
1166                 save_fsgs_for_kvm();
1167                 fs_sel = current->thread.fsindex;
1168                 gs_sel = current->thread.gsindex;
1169                 fs_base = current->thread.fsbase;
1170                 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
1171         } else {
1172                 savesegment(fs, fs_sel);
1173                 savesegment(gs, gs_sel);
1174                 fs_base = read_msr(MSR_FS_BASE);
1175                 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
1176         }
1177
1178         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1179 #else
1180         savesegment(fs, fs_sel);
1181         savesegment(gs, gs_sel);
1182         fs_base = segment_base(fs_sel);
1183         gs_base = segment_base(gs_sel);
1184 #endif
1185
1186         vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
1187         vmx->guest_state_loaded = true;
1188 }
1189
1190 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
1191 {
1192         struct vmcs_host_state *host_state;
1193
1194         if (!vmx->guest_state_loaded)
1195                 return;
1196
1197         host_state = &vmx->loaded_vmcs->host_state;
1198
1199         ++vmx->vcpu.stat.host_state_reload;
1200
1201 #ifdef CONFIG_X86_64
1202         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1203 #endif
1204         if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1205                 kvm_load_ldt(host_state->ldt_sel);
1206 #ifdef CONFIG_X86_64
1207                 load_gs_index(host_state->gs_sel);
1208 #else
1209                 loadsegment(gs, host_state->gs_sel);
1210 #endif
1211         }
1212         if (host_state->fs_sel & 7)
1213                 loadsegment(fs, host_state->fs_sel);
1214 #ifdef CONFIG_X86_64
1215         if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1216                 loadsegment(ds, host_state->ds_sel);
1217                 loadsegment(es, host_state->es_sel);
1218         }
1219 #endif
1220         invalidate_tss_limit();
1221 #ifdef CONFIG_X86_64
1222         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1223 #endif
1224         load_fixmap_gdt(raw_smp_processor_id());
1225         vmx->guest_state_loaded = false;
1226         vmx->guest_msrs_ready = false;
1227 }
1228
1229 #ifdef CONFIG_X86_64
1230 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
1231 {
1232         preempt_disable();
1233         if (vmx->guest_state_loaded)
1234                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1235         preempt_enable();
1236         return vmx->msr_guest_kernel_gs_base;
1237 }
1238
1239 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1240 {
1241         preempt_disable();
1242         if (vmx->guest_state_loaded)
1243                 wrmsrl(MSR_KERNEL_GS_BASE, data);
1244         preempt_enable();
1245         vmx->msr_guest_kernel_gs_base = data;
1246 }
1247 #endif
1248
1249 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1250 {
1251         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1252         struct pi_desc old, new;
1253         unsigned int dest;
1254
1255         /*
1256          * In case of hot-plug or hot-unplug, we may have to undo
1257          * vmx_vcpu_pi_put even if there is no assigned device.  And we
1258          * always keep PI.NDST up to date for simplicity: it makes the
1259          * code easier, and CPU migration is not a fast path.
1260          */
1261         if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
1262                 return;
1263
1264         /*
1265          * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
1266          * PI.NDST: pi_post_block is the one expected to change PID.NDST and the
1267          * wakeup handler expects the vCPU to be on the blocked_vcpu_list that
1268          * matches PI.NDST. Otherwise, a vcpu may not be able to be woken up
1269          * correctly.
1270          */
1271         if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || vcpu->cpu == cpu) {
1272                 pi_clear_sn(pi_desc);
1273                 goto after_clear_sn;
1274         }
1275
1276         /* The full case.  */
1277         do {
1278                 old.control = new.control = pi_desc->control;
1279
1280                 dest = cpu_physical_id(cpu);
1281
1282                 if (x2apic_enabled())
1283                         new.ndst = dest;
1284                 else
1285                         new.ndst = (dest << 8) & 0xFF00;
1286
1287                 new.sn = 0;
1288         } while (cmpxchg64(&pi_desc->control, old.control,
1289                            new.control) != old.control);
1290
1291 after_clear_sn:
1292
1293         /*
1294          * Clear SN before reading the bitmap.  The VT-d firmware
1295          * writes the bitmap and reads SN atomically (5.2.3 in the
1296          * spec), so it doesn't really have a memory barrier that
1297          * pairs with this, but we cannot do that and we need one.
1298          */
1299         smp_mb__after_atomic();
1300
1301         if (!pi_is_pir_empty(pi_desc))
1302                 pi_set_on(pi_desc);
1303 }
1304
1305 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu)
1306 {
1307         struct vcpu_vmx *vmx = to_vmx(vcpu);
1308         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
1309
1310         if (!already_loaded) {
1311                 loaded_vmcs_clear(vmx->loaded_vmcs);
1312                 local_irq_disable();
1313
1314                 /*
1315                  * Ensure loaded_vmcs->cpu is read before adding loaded_vmcs to
1316                  * this cpu's percpu list, otherwise it may not yet be deleted
1317                  * from its previous cpu's percpu list.  Pairs with the
1318                  * smb_wmb() in __loaded_vmcs_clear().
1319                  */
1320                 smp_rmb();
1321
1322                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1323                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1324                 local_irq_enable();
1325         }
1326
1327         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1328                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1329                 vmcs_load(vmx->loaded_vmcs->vmcs);
1330                 indirect_branch_prediction_barrier();
1331         }
1332
1333         if (!already_loaded) {
1334                 void *gdt = get_current_gdt_ro();
1335                 unsigned long sysenter_esp;
1336
1337                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1338
1339                 /*
1340                  * Linux uses per-cpu TSS and GDT, so set these when switching
1341                  * processors.  See 22.2.4.
1342                  */
1343                 vmcs_writel(HOST_TR_BASE,
1344                             (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
1345                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
1346
1347                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1348                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1349
1350                 vmx->loaded_vmcs->cpu = cpu;
1351         }
1352
1353         /* Setup TSC multiplier */
1354         if (kvm_has_tsc_control &&
1355             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
1356                 decache_tsc_multiplier(vmx);
1357 }
1358
1359 /*
1360  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1361  * vcpu mutex is already taken.
1362  */
1363 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1364 {
1365         struct vcpu_vmx *vmx = to_vmx(vcpu);
1366
1367         vmx_vcpu_load_vmcs(vcpu, cpu);
1368
1369         vmx_vcpu_pi_load(vcpu, cpu);
1370
1371         vmx->host_pkru = read_pkru();
1372         vmx->host_debugctlmsr = get_debugctlmsr();
1373 }
1374
1375 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
1376 {
1377         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1378
1379         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1380                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
1381                 !kvm_vcpu_apicv_active(vcpu))
1382                 return;
1383
1384         /* Set SN when the vCPU is preempted */
1385         if (vcpu->preempted)
1386                 pi_set_sn(pi_desc);
1387 }
1388
1389 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1390 {
1391         vmx_vcpu_pi_put(vcpu);
1392
1393         vmx_prepare_switch_to_host(to_vmx(vcpu));
1394 }
1395
1396 static bool emulation_required(struct kvm_vcpu *vcpu)
1397 {
1398         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
1399 }
1400
1401 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1402 {
1403         struct vcpu_vmx *vmx = to_vmx(vcpu);
1404         unsigned long rflags, save_rflags;
1405
1406         if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) {
1407                 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1408                 rflags = vmcs_readl(GUEST_RFLAGS);
1409                 if (vmx->rmode.vm86_active) {
1410                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1411                         save_rflags = vmx->rmode.save_rflags;
1412                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1413                 }
1414                 vmx->rflags = rflags;
1415         }
1416         return vmx->rflags;
1417 }
1418
1419 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1420 {
1421         struct vcpu_vmx *vmx = to_vmx(vcpu);
1422         unsigned long old_rflags;
1423
1424         if (enable_unrestricted_guest) {
1425                 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1426                 vmx->rflags = rflags;
1427                 vmcs_writel(GUEST_RFLAGS, rflags);
1428                 return;
1429         }
1430
1431         old_rflags = vmx_get_rflags(vcpu);
1432         vmx->rflags = rflags;
1433         if (vmx->rmode.vm86_active) {
1434                 vmx->rmode.save_rflags = rflags;
1435                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1436         }
1437         vmcs_writel(GUEST_RFLAGS, rflags);
1438
1439         if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM)
1440                 vmx->emulation_required = emulation_required(vcpu);
1441 }
1442
1443 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1444 {
1445         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1446         int ret = 0;
1447
1448         if (interruptibility & GUEST_INTR_STATE_STI)
1449                 ret |= KVM_X86_SHADOW_INT_STI;
1450         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1451                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1452
1453         return ret;
1454 }
1455
1456 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1457 {
1458         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1459         u32 interruptibility = interruptibility_old;
1460
1461         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1462
1463         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1464                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1465         else if (mask & KVM_X86_SHADOW_INT_STI)
1466                 interruptibility |= GUEST_INTR_STATE_STI;
1467
1468         if ((interruptibility != interruptibility_old))
1469                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1470 }
1471
1472 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1473 {
1474         struct vcpu_vmx *vmx = to_vmx(vcpu);
1475         unsigned long value;
1476
1477         /*
1478          * Any MSR write that attempts to change bits marked reserved will
1479          * case a #GP fault.
1480          */
1481         if (data & vmx->pt_desc.ctl_bitmask)
1482                 return 1;
1483
1484         /*
1485          * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1486          * result in a #GP unless the same write also clears TraceEn.
1487          */
1488         if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1489                 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1490                 return 1;
1491
1492         /*
1493          * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1494          * and FabricEn would cause #GP, if
1495          * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1496          */
1497         if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1498                 !(data & RTIT_CTL_FABRIC_EN) &&
1499                 !intel_pt_validate_cap(vmx->pt_desc.caps,
1500                                         PT_CAP_single_range_output))
1501                 return 1;
1502
1503         /*
1504          * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1505          * utilize encodings marked reserved will casue a #GP fault.
1506          */
1507         value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1508         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1509                         !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1510                         RTIT_CTL_MTC_RANGE_OFFSET, &value))
1511                 return 1;
1512         value = intel_pt_validate_cap(vmx->pt_desc.caps,
1513                                                 PT_CAP_cycle_thresholds);
1514         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1515                         !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1516                         RTIT_CTL_CYC_THRESH_OFFSET, &value))
1517                 return 1;
1518         value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1519         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1520                         !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1521                         RTIT_CTL_PSB_FREQ_OFFSET, &value))
1522                 return 1;
1523
1524         /*
1525          * If ADDRx_CFG is reserved or the encodings is >2 will
1526          * cause a #GP fault.
1527          */
1528         value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1529         if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
1530                 return 1;
1531         value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1532         if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
1533                 return 1;
1534         value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1535         if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
1536                 return 1;
1537         value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1538         if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
1539                 return 1;
1540
1541         return 0;
1542 }
1543
1544 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
1545 {
1546         unsigned long rip;
1547
1548         /*
1549          * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
1550          * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
1551          * set when EPT misconfig occurs.  In practice, real hardware updates
1552          * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
1553          * (namely Hyper-V) don't set it due to it being undefined behavior,
1554          * i.e. we end up advancing IP with some random value.
1555          */
1556         if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
1557             to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) {
1558                 rip = kvm_rip_read(vcpu);
1559                 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1560                 kvm_rip_write(vcpu, rip);
1561         } else {
1562                 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
1563                         return 0;
1564         }
1565
1566         /* skipping an emulated instruction also counts */
1567         vmx_set_interrupt_shadow(vcpu, 0);
1568
1569         return 1;
1570 }
1571
1572
1573 /*
1574  * Recognizes a pending MTF VM-exit and records the nested state for later
1575  * delivery.
1576  */
1577 static void vmx_update_emulated_instruction(struct kvm_vcpu *vcpu)
1578 {
1579         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1580         struct vcpu_vmx *vmx = to_vmx(vcpu);
1581
1582         if (!is_guest_mode(vcpu))
1583                 return;
1584
1585         /*
1586          * Per the SDM, MTF takes priority over debug-trap exceptions besides
1587          * T-bit traps. As instruction emulation is completed (i.e. at the
1588          * instruction boundary), any #DB exception pending delivery must be a
1589          * debug-trap. Record the pending MTF state to be delivered in
1590          * vmx_check_nested_events().
1591          */
1592         if (nested_cpu_has_mtf(vmcs12) &&
1593             (!vcpu->arch.exception.pending ||
1594              vcpu->arch.exception.nr == DB_VECTOR))
1595                 vmx->nested.mtf_pending = true;
1596         else
1597                 vmx->nested.mtf_pending = false;
1598 }
1599
1600 static int vmx_skip_emulated_instruction(struct kvm_vcpu *vcpu)
1601 {
1602         vmx_update_emulated_instruction(vcpu);
1603         return skip_emulated_instruction(vcpu);
1604 }
1605
1606 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1607 {
1608         /*
1609          * Ensure that we clear the HLT state in the VMCS.  We don't need to
1610          * explicitly skip the instruction because if the HLT state is set,
1611          * then the instruction is already executing and RIP has already been
1612          * advanced.
1613          */
1614         if (kvm_hlt_in_guest(vcpu->kvm) &&
1615                         vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1616                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1617 }
1618
1619 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
1620 {
1621         struct vcpu_vmx *vmx = to_vmx(vcpu);
1622         unsigned nr = vcpu->arch.exception.nr;
1623         bool has_error_code = vcpu->arch.exception.has_error_code;
1624         u32 error_code = vcpu->arch.exception.error_code;
1625         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1626
1627         kvm_deliver_exception_payload(vcpu);
1628
1629         if (has_error_code) {
1630                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1631                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1632         }
1633
1634         if (vmx->rmode.vm86_active) {
1635                 int inc_eip = 0;
1636                 if (kvm_exception_is_soft(nr))
1637                         inc_eip = vcpu->arch.event_exit_inst_len;
1638                 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
1639                 return;
1640         }
1641
1642         WARN_ON_ONCE(vmx->emulation_required);
1643
1644         if (kvm_exception_is_soft(nr)) {
1645                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1646                              vmx->vcpu.arch.event_exit_inst_len);
1647                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1648         } else
1649                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1650
1651         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1652
1653         vmx_clear_hlt(vcpu);
1654 }
1655
1656 /*
1657  * Swap MSR entry in host/guest MSR entry array.
1658  */
1659 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1660 {
1661         struct shared_msr_entry tmp;
1662
1663         tmp = vmx->guest_msrs[to];
1664         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1665         vmx->guest_msrs[from] = tmp;
1666 }
1667
1668 /*
1669  * Set up the vmcs to automatically save and restore system
1670  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1671  * mode, as fiddling with msrs is very expensive.
1672  */
1673 static void setup_msrs(struct vcpu_vmx *vmx)
1674 {
1675         int save_nmsrs, index;
1676
1677         save_nmsrs = 0;
1678 #ifdef CONFIG_X86_64
1679         /*
1680          * The SYSCALL MSRs are only needed on long mode guests, and only
1681          * when EFER.SCE is set.
1682          */
1683         if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) {
1684                 index = __find_msr_index(vmx, MSR_STAR);
1685                 if (index >= 0)
1686                         move_msr_up(vmx, index, save_nmsrs++);
1687                 index = __find_msr_index(vmx, MSR_LSTAR);
1688                 if (index >= 0)
1689                         move_msr_up(vmx, index, save_nmsrs++);
1690                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1691                 if (index >= 0)
1692                         move_msr_up(vmx, index, save_nmsrs++);
1693         }
1694 #endif
1695         index = __find_msr_index(vmx, MSR_EFER);
1696         if (index >= 0 && update_transition_efer(vmx, index))
1697                 move_msr_up(vmx, index, save_nmsrs++);
1698         index = __find_msr_index(vmx, MSR_TSC_AUX);
1699         if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
1700                 move_msr_up(vmx, index, save_nmsrs++);
1701         index = __find_msr_index(vmx, MSR_IA32_TSX_CTRL);
1702         if (index >= 0)
1703                 move_msr_up(vmx, index, save_nmsrs++);
1704
1705         vmx->save_nmsrs = save_nmsrs;
1706         vmx->guest_msrs_ready = false;
1707
1708         if (cpu_has_vmx_msr_bitmap())
1709                 vmx_update_msr_bitmap(&vmx->vcpu);
1710 }
1711
1712 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1713 {
1714         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1715
1716         if (is_guest_mode(vcpu) &&
1717             (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING))
1718                 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
1719
1720         return vcpu->arch.tsc_offset;
1721 }
1722
1723 static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1724 {
1725         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1726         u64 g_tsc_offset = 0;
1727
1728         /*
1729          * We're here if L1 chose not to trap WRMSR to TSC. According
1730          * to the spec, this should set L1's TSC; The offset that L1
1731          * set for L2 remains unchanged, and still needs to be added
1732          * to the newly set TSC to get L2's TSC.
1733          */
1734         if (is_guest_mode(vcpu) &&
1735             (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING))
1736                 g_tsc_offset = vmcs12->tsc_offset;
1737
1738         trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1739                                    vcpu->arch.tsc_offset - g_tsc_offset,
1740                                    offset);
1741         vmcs_write64(TSC_OFFSET, offset + g_tsc_offset);
1742         return offset + g_tsc_offset;
1743 }
1744
1745 /*
1746  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1747  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1748  * all guests if the "nested" module option is off, and can also be disabled
1749  * for a single guest by disabling its VMX cpuid bit.
1750  */
1751 bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1752 {
1753         return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
1754 }
1755
1756 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1757                                                  uint64_t val)
1758 {
1759         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
1760
1761         return !(val & ~valid_bits);
1762 }
1763
1764 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
1765 {
1766         switch (msr->index) {
1767         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1768                 if (!nested)
1769                         return 1;
1770                 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1771         default:
1772                 return 1;
1773         }
1774 }
1775
1776 /*
1777  * Reads an msr value (of 'msr_index') into 'pdata'.
1778  * Returns 0 on success, non-0 otherwise.
1779  * Assumes vcpu_load() was already called.
1780  */
1781 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1782 {
1783         struct vcpu_vmx *vmx = to_vmx(vcpu);
1784         struct shared_msr_entry *msr;
1785         u32 index;
1786
1787         switch (msr_info->index) {
1788 #ifdef CONFIG_X86_64
1789         case MSR_FS_BASE:
1790                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
1791                 break;
1792         case MSR_GS_BASE:
1793                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
1794                 break;
1795         case MSR_KERNEL_GS_BASE:
1796                 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
1797                 break;
1798 #endif
1799         case MSR_EFER:
1800                 return kvm_get_msr_common(vcpu, msr_info);
1801         case MSR_IA32_TSX_CTRL:
1802                 if (!msr_info->host_initiated &&
1803                     !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
1804                         return 1;
1805                 goto find_shared_msr;
1806         case MSR_IA32_UMWAIT_CONTROL:
1807                 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1808                         return 1;
1809
1810                 msr_info->data = vmx->msr_ia32_umwait_control;
1811                 break;
1812         case MSR_IA32_SPEC_CTRL:
1813                 if (!msr_info->host_initiated &&
1814                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1815                         return 1;
1816
1817                 msr_info->data = to_vmx(vcpu)->spec_ctrl;
1818                 break;
1819         case MSR_IA32_SYSENTER_CS:
1820                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
1821                 break;
1822         case MSR_IA32_SYSENTER_EIP:
1823                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
1824                 break;
1825         case MSR_IA32_SYSENTER_ESP:
1826                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
1827                 break;
1828         case MSR_IA32_BNDCFGS:
1829                 if (!kvm_mpx_supported() ||
1830                     (!msr_info->host_initiated &&
1831                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1832                         return 1;
1833                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
1834                 break;
1835         case MSR_IA32_MCG_EXT_CTL:
1836                 if (!msr_info->host_initiated &&
1837                     !(vmx->msr_ia32_feature_control &
1838                       FEAT_CTL_LMCE_ENABLED))
1839                         return 1;
1840                 msr_info->data = vcpu->arch.mcg_ext_ctl;
1841                 break;
1842         case MSR_IA32_FEAT_CTL:
1843                 msr_info->data = vmx->msr_ia32_feature_control;
1844                 break;
1845         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1846                 if (!nested_vmx_allowed(vcpu))
1847                         return 1;
1848                 if (vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1849                                     &msr_info->data))
1850                         return 1;
1851                 /*
1852                  * Enlightened VMCS v1 doesn't have certain fields, but buggy
1853                  * Hyper-V versions are still trying to use corresponding
1854                  * features when they are exposed. Filter out the essential
1855                  * minimum.
1856                  */
1857                 if (!msr_info->host_initiated &&
1858                     vmx->nested.enlightened_vmcs_enabled)
1859                         nested_evmcs_filter_control_msr(msr_info->index,
1860                                                         &msr_info->data);
1861                 break;
1862         case MSR_IA32_RTIT_CTL:
1863                 if (!vmx_pt_mode_is_host_guest())
1864                         return 1;
1865                 msr_info->data = vmx->pt_desc.guest.ctl;
1866                 break;
1867         case MSR_IA32_RTIT_STATUS:
1868                 if (!vmx_pt_mode_is_host_guest())
1869                         return 1;
1870                 msr_info->data = vmx->pt_desc.guest.status;
1871                 break;
1872         case MSR_IA32_RTIT_CR3_MATCH:
1873                 if (!vmx_pt_mode_is_host_guest() ||
1874                         !intel_pt_validate_cap(vmx->pt_desc.caps,
1875                                                 PT_CAP_cr3_filtering))
1876                         return 1;
1877                 msr_info->data = vmx->pt_desc.guest.cr3_match;
1878                 break;
1879         case MSR_IA32_RTIT_OUTPUT_BASE:
1880                 if (!vmx_pt_mode_is_host_guest() ||
1881                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1882                                         PT_CAP_topa_output) &&
1883                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1884                                         PT_CAP_single_range_output)))
1885                         return 1;
1886                 msr_info->data = vmx->pt_desc.guest.output_base;
1887                 break;
1888         case MSR_IA32_RTIT_OUTPUT_MASK:
1889                 if (!vmx_pt_mode_is_host_guest() ||
1890                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1891                                         PT_CAP_topa_output) &&
1892                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1893                                         PT_CAP_single_range_output)))
1894                         return 1;
1895                 msr_info->data = vmx->pt_desc.guest.output_mask;
1896                 break;
1897         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1898                 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1899                 if (!vmx_pt_mode_is_host_guest() ||
1900                         (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
1901                                         PT_CAP_num_address_ranges)))
1902                         return 1;
1903                 if (index % 2)
1904                         msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1905                 else
1906                         msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1907                 break;
1908         case MSR_TSC_AUX:
1909                 if (!msr_info->host_initiated &&
1910                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
1911                         return 1;
1912                 goto find_shared_msr;
1913         default:
1914         find_shared_msr:
1915                 msr = find_msr_entry(vmx, msr_info->index);
1916                 if (msr) {
1917                         msr_info->data = msr->data;
1918                         break;
1919                 }
1920                 return kvm_get_msr_common(vcpu, msr_info);
1921         }
1922
1923         return 0;
1924 }
1925
1926 /*
1927  * Writes msr value into the appropriate "register".
1928  * Returns 0 on success, non-0 otherwise.
1929  * Assumes vcpu_load() was already called.
1930  */
1931 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1932 {
1933         struct vcpu_vmx *vmx = to_vmx(vcpu);
1934         struct shared_msr_entry *msr;
1935         int ret = 0;
1936         u32 msr_index = msr_info->index;
1937         u64 data = msr_info->data;
1938         u32 index;
1939
1940         switch (msr_index) {
1941         case MSR_EFER:
1942                 ret = kvm_set_msr_common(vcpu, msr_info);
1943                 break;
1944 #ifdef CONFIG_X86_64
1945         case MSR_FS_BASE:
1946                 vmx_segment_cache_clear(vmx);
1947                 vmcs_writel(GUEST_FS_BASE, data);
1948                 break;
1949         case MSR_GS_BASE:
1950                 vmx_segment_cache_clear(vmx);
1951                 vmcs_writel(GUEST_GS_BASE, data);
1952                 break;
1953         case MSR_KERNEL_GS_BASE:
1954                 vmx_write_guest_kernel_gs_base(vmx, data);
1955                 break;
1956 #endif
1957         case MSR_IA32_SYSENTER_CS:
1958                 if (is_guest_mode(vcpu))
1959                         get_vmcs12(vcpu)->guest_sysenter_cs = data;
1960                 vmcs_write32(GUEST_SYSENTER_CS, data);
1961                 break;
1962         case MSR_IA32_SYSENTER_EIP:
1963                 if (is_guest_mode(vcpu))
1964                         get_vmcs12(vcpu)->guest_sysenter_eip = data;
1965                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1966                 break;
1967         case MSR_IA32_SYSENTER_ESP:
1968                 if (is_guest_mode(vcpu))
1969                         get_vmcs12(vcpu)->guest_sysenter_esp = data;
1970                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1971                 break;
1972         case MSR_IA32_DEBUGCTLMSR:
1973                 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
1974                                                 VM_EXIT_SAVE_DEBUG_CONTROLS)
1975                         get_vmcs12(vcpu)->guest_ia32_debugctl = data;
1976
1977                 ret = kvm_set_msr_common(vcpu, msr_info);
1978                 break;
1979
1980         case MSR_IA32_BNDCFGS:
1981                 if (!kvm_mpx_supported() ||
1982                     (!msr_info->host_initiated &&
1983                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1984                         return 1;
1985                 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
1986                     (data & MSR_IA32_BNDCFGS_RSVD))
1987                         return 1;
1988                 vmcs_write64(GUEST_BNDCFGS, data);
1989                 break;
1990         case MSR_IA32_UMWAIT_CONTROL:
1991                 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1992                         return 1;
1993
1994                 /* The reserved bit 1 and non-32 bit [63:32] should be zero */
1995                 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
1996                         return 1;
1997
1998                 vmx->msr_ia32_umwait_control = data;
1999                 break;
2000         case MSR_IA32_SPEC_CTRL:
2001                 if (!msr_info->host_initiated &&
2002                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2003                         return 1;
2004
2005                 if (data & ~kvm_spec_ctrl_valid_bits(vcpu))
2006                         return 1;
2007
2008                 vmx->spec_ctrl = data;
2009                 if (!data)
2010                         break;
2011
2012                 /*
2013                  * For non-nested:
2014                  * When it's written (to non-zero) for the first time, pass
2015                  * it through.
2016                  *
2017                  * For nested:
2018                  * The handling of the MSR bitmap for L2 guests is done in
2019                  * nested_vmx_prepare_msr_bitmap. We should not touch the
2020                  * vmcs02.msr_bitmap here since it gets completely overwritten
2021                  * in the merging. We update the vmcs01 here for L1 as well
2022                  * since it will end up touching the MSR anyway now.
2023                  */
2024                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
2025                                               MSR_IA32_SPEC_CTRL,
2026                                               MSR_TYPE_RW);
2027                 break;
2028         case MSR_IA32_TSX_CTRL:
2029                 if (!msr_info->host_initiated &&
2030                     !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
2031                         return 1;
2032                 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR))
2033                         return 1;
2034                 goto find_shared_msr;
2035         case MSR_IA32_PRED_CMD:
2036                 if (!msr_info->host_initiated &&
2037                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2038                         return 1;
2039
2040                 if (data & ~PRED_CMD_IBPB)
2041                         return 1;
2042                 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL))
2043                         return 1;
2044                 if (!data)
2045                         break;
2046
2047                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2048
2049                 /*
2050                  * For non-nested:
2051                  * When it's written (to non-zero) for the first time, pass
2052                  * it through.
2053                  *
2054                  * For nested:
2055                  * The handling of the MSR bitmap for L2 guests is done in
2056                  * nested_vmx_prepare_msr_bitmap. We should not touch the
2057                  * vmcs02.msr_bitmap here since it gets completely overwritten
2058                  * in the merging.
2059                  */
2060                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
2061                                               MSR_TYPE_W);
2062                 break;
2063         case MSR_IA32_CR_PAT:
2064                 if (!kvm_pat_valid(data))
2065                         return 1;
2066
2067                 if (is_guest_mode(vcpu) &&
2068                     get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
2069                         get_vmcs12(vcpu)->guest_ia32_pat = data;
2070
2071                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2072                         vmcs_write64(GUEST_IA32_PAT, data);
2073                         vcpu->arch.pat = data;
2074                         break;
2075                 }
2076                 ret = kvm_set_msr_common(vcpu, msr_info);
2077                 break;
2078         case MSR_IA32_TSC_ADJUST:
2079                 ret = kvm_set_msr_common(vcpu, msr_info);
2080                 break;
2081         case MSR_IA32_MCG_EXT_CTL:
2082                 if ((!msr_info->host_initiated &&
2083                      !(to_vmx(vcpu)->msr_ia32_feature_control &
2084                        FEAT_CTL_LMCE_ENABLED)) ||
2085                     (data & ~MCG_EXT_CTL_LMCE_EN))
2086                         return 1;
2087                 vcpu->arch.mcg_ext_ctl = data;
2088                 break;
2089         case MSR_IA32_FEAT_CTL:
2090                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
2091                     (to_vmx(vcpu)->msr_ia32_feature_control &
2092                      FEAT_CTL_LOCKED && !msr_info->host_initiated))
2093                         return 1;
2094                 vmx->msr_ia32_feature_control = data;
2095                 if (msr_info->host_initiated && data == 0)
2096                         vmx_leave_nested(vcpu);
2097                 break;
2098         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2099                 if (!msr_info->host_initiated)
2100                         return 1; /* they are read-only */
2101                 if (!nested_vmx_allowed(vcpu))
2102                         return 1;
2103                 return vmx_set_vmx_msr(vcpu, msr_index, data);
2104         case MSR_IA32_RTIT_CTL:
2105                 if (!vmx_pt_mode_is_host_guest() ||
2106                         vmx_rtit_ctl_check(vcpu, data) ||
2107                         vmx->nested.vmxon)
2108                         return 1;
2109                 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
2110                 vmx->pt_desc.guest.ctl = data;
2111                 pt_update_intercept_for_msr(vmx);
2112                 break;
2113         case MSR_IA32_RTIT_STATUS:
2114                 if (!pt_can_write_msr(vmx))
2115                         return 1;
2116                 if (data & MSR_IA32_RTIT_STATUS_MASK)
2117                         return 1;
2118                 vmx->pt_desc.guest.status = data;
2119                 break;
2120         case MSR_IA32_RTIT_CR3_MATCH:
2121                 if (!pt_can_write_msr(vmx))
2122                         return 1;
2123                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2124                                            PT_CAP_cr3_filtering))
2125                         return 1;
2126                 vmx->pt_desc.guest.cr3_match = data;
2127                 break;
2128         case MSR_IA32_RTIT_OUTPUT_BASE:
2129                 if (!pt_can_write_msr(vmx))
2130                         return 1;
2131                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2132                                            PT_CAP_topa_output) &&
2133                     !intel_pt_validate_cap(vmx->pt_desc.caps,
2134                                            PT_CAP_single_range_output))
2135                         return 1;
2136                 if (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK)
2137                         return 1;
2138                 vmx->pt_desc.guest.output_base = data;
2139                 break;
2140         case MSR_IA32_RTIT_OUTPUT_MASK:
2141                 if (!pt_can_write_msr(vmx))
2142                         return 1;
2143                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2144                                            PT_CAP_topa_output) &&
2145                     !intel_pt_validate_cap(vmx->pt_desc.caps,
2146                                            PT_CAP_single_range_output))
2147                         return 1;
2148                 vmx->pt_desc.guest.output_mask = data;
2149                 break;
2150         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2151                 if (!pt_can_write_msr(vmx))
2152                         return 1;
2153                 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2154                 if (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
2155                                                        PT_CAP_num_address_ranges))
2156                         return 1;
2157                 if (is_noncanonical_address(data, vcpu))
2158                         return 1;
2159                 if (index % 2)
2160                         vmx->pt_desc.guest.addr_b[index / 2] = data;
2161                 else
2162                         vmx->pt_desc.guest.addr_a[index / 2] = data;
2163                 break;
2164         case MSR_TSC_AUX:
2165                 if (!msr_info->host_initiated &&
2166                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
2167                         return 1;
2168                 /* Check reserved bit, higher 32 bits should be zero */
2169                 if ((data >> 32) != 0)
2170                         return 1;
2171                 goto find_shared_msr;
2172
2173         default:
2174         find_shared_msr:
2175                 msr = find_msr_entry(vmx, msr_index);
2176                 if (msr)
2177                         ret = vmx_set_guest_msr(vmx, msr, data);
2178                 else
2179                         ret = kvm_set_msr_common(vcpu, msr_info);
2180         }
2181
2182         return ret;
2183 }
2184
2185 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2186 {
2187         kvm_register_mark_available(vcpu, reg);
2188
2189         switch (reg) {
2190         case VCPU_REGS_RSP:
2191                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2192                 break;
2193         case VCPU_REGS_RIP:
2194                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2195                 break;
2196         case VCPU_EXREG_PDPTR:
2197                 if (enable_ept)
2198                         ept_save_pdptrs(vcpu);
2199                 break;
2200         case VCPU_EXREG_CR3:
2201                 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
2202                         vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2203                 break;
2204         default:
2205                 WARN_ON_ONCE(1);
2206                 break;
2207         }
2208 }
2209
2210 static __init int cpu_has_kvm_support(void)
2211 {
2212         return cpu_has_vmx();
2213 }
2214
2215 static __init int vmx_disabled_by_bios(void)
2216 {
2217         return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
2218                !boot_cpu_has(X86_FEATURE_VMX);
2219 }
2220
2221 static int kvm_cpu_vmxon(u64 vmxon_pointer)
2222 {
2223         u64 msr;
2224
2225         cr4_set_bits(X86_CR4_VMXE);
2226         intel_pt_handle_vmx(1);
2227
2228         asm_volatile_goto("1: vmxon %[vmxon_pointer]\n\t"
2229                           _ASM_EXTABLE(1b, %l[fault])
2230                           : : [vmxon_pointer] "m"(vmxon_pointer)
2231                           : : fault);
2232         return 0;
2233
2234 fault:
2235         WARN_ONCE(1, "VMXON faulted, MSR_IA32_FEAT_CTL (0x3a) = 0x%llx\n",
2236                   rdmsrl_safe(MSR_IA32_FEAT_CTL, &msr) ? 0xdeadbeef : msr);
2237         intel_pt_handle_vmx(0);
2238         cr4_clear_bits(X86_CR4_VMXE);
2239
2240         return -EFAULT;
2241 }
2242
2243 static int hardware_enable(void)
2244 {
2245         int cpu = raw_smp_processor_id();
2246         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2247         int r;
2248
2249         if (cr4_read_shadow() & X86_CR4_VMXE)
2250                 return -EBUSY;
2251
2252         /*
2253          * This can happen if we hot-added a CPU but failed to allocate
2254          * VP assist page for it.
2255          */
2256         if (static_branch_unlikely(&enable_evmcs) &&
2257             !hv_get_vp_assist_page(cpu))
2258                 return -EFAULT;
2259
2260         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2261         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
2262         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
2263
2264         r = kvm_cpu_vmxon(phys_addr);
2265         if (r)
2266                 return r;
2267
2268         if (enable_ept)
2269                 ept_sync_global();
2270
2271         return 0;
2272 }
2273
2274 static void vmclear_local_loaded_vmcss(void)
2275 {
2276         int cpu = raw_smp_processor_id();
2277         struct loaded_vmcs *v, *n;
2278
2279         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2280                                  loaded_vmcss_on_cpu_link)
2281                 __loaded_vmcs_clear(v);
2282 }
2283
2284
2285 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2286  * tricks.
2287  */
2288 static void kvm_cpu_vmxoff(void)
2289 {
2290         asm volatile (__ex("vmxoff"));
2291
2292         intel_pt_handle_vmx(0);
2293         cr4_clear_bits(X86_CR4_VMXE);
2294 }
2295
2296 static void hardware_disable(void)
2297 {
2298         vmclear_local_loaded_vmcss();
2299         kvm_cpu_vmxoff();
2300 }
2301
2302 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2303                                       u32 msr, u32 *result)
2304 {
2305         u32 vmx_msr_low, vmx_msr_high;
2306         u32 ctl = ctl_min | ctl_opt;
2307
2308         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2309
2310         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2311         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2312
2313         /* Ensure minimum (required) set of control bits are supported. */
2314         if (ctl_min & ~ctl)
2315                 return -EIO;
2316
2317         *result = ctl;
2318         return 0;
2319 }
2320
2321 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2322                                     struct vmx_capability *vmx_cap)
2323 {
2324         u32 vmx_msr_low, vmx_msr_high;
2325         u32 min, opt, min2, opt2;
2326         u32 _pin_based_exec_control = 0;
2327         u32 _cpu_based_exec_control = 0;
2328         u32 _cpu_based_2nd_exec_control = 0;
2329         u32 _vmexit_control = 0;
2330         u32 _vmentry_control = 0;
2331
2332         memset(vmcs_conf, 0, sizeof(*vmcs_conf));
2333         min = CPU_BASED_HLT_EXITING |
2334 #ifdef CONFIG_X86_64
2335               CPU_BASED_CR8_LOAD_EXITING |
2336               CPU_BASED_CR8_STORE_EXITING |
2337 #endif
2338               CPU_BASED_CR3_LOAD_EXITING |
2339               CPU_BASED_CR3_STORE_EXITING |
2340               CPU_BASED_UNCOND_IO_EXITING |
2341               CPU_BASED_MOV_DR_EXITING |
2342               CPU_BASED_USE_TSC_OFFSETTING |
2343               CPU_BASED_MWAIT_EXITING |
2344               CPU_BASED_MONITOR_EXITING |
2345               CPU_BASED_INVLPG_EXITING |
2346               CPU_BASED_RDPMC_EXITING;
2347
2348         opt = CPU_BASED_TPR_SHADOW |
2349               CPU_BASED_USE_MSR_BITMAPS |
2350               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2351         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2352                                 &_cpu_based_exec_control) < 0)
2353                 return -EIO;
2354 #ifdef CONFIG_X86_64
2355         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2356                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2357                                            ~CPU_BASED_CR8_STORE_EXITING;
2358 #endif
2359         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2360                 min2 = 0;
2361                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2362                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2363                         SECONDARY_EXEC_WBINVD_EXITING |
2364                         SECONDARY_EXEC_ENABLE_VPID |
2365                         SECONDARY_EXEC_ENABLE_EPT |
2366                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2367                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2368                         SECONDARY_EXEC_DESC |
2369                         SECONDARY_EXEC_RDTSCP |
2370                         SECONDARY_EXEC_ENABLE_INVPCID |
2371                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2372                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2373                         SECONDARY_EXEC_SHADOW_VMCS |
2374                         SECONDARY_EXEC_XSAVES |
2375                         SECONDARY_EXEC_RDSEED_EXITING |
2376                         SECONDARY_EXEC_RDRAND_EXITING |
2377                         SECONDARY_EXEC_ENABLE_PML |
2378                         SECONDARY_EXEC_TSC_SCALING |
2379                         SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
2380                         SECONDARY_EXEC_PT_USE_GPA |
2381                         SECONDARY_EXEC_PT_CONCEAL_VMX |
2382                         SECONDARY_EXEC_ENABLE_VMFUNC |
2383                         SECONDARY_EXEC_ENCLS_EXITING;
2384                 if (adjust_vmx_controls(min2, opt2,
2385                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2386                                         &_cpu_based_2nd_exec_control) < 0)
2387                         return -EIO;
2388         }
2389 #ifndef CONFIG_X86_64
2390         if (!(_cpu_based_2nd_exec_control &
2391                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2392                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2393 #endif
2394
2395         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2396                 _cpu_based_2nd_exec_control &= ~(
2397                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2398                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2399                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2400
2401         rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
2402                 &vmx_cap->ept, &vmx_cap->vpid);
2403
2404         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2405                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2406                    enabled */
2407                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2408                                              CPU_BASED_CR3_STORE_EXITING |
2409                                              CPU_BASED_INVLPG_EXITING);
2410         } else if (vmx_cap->ept) {
2411                 vmx_cap->ept = 0;
2412                 pr_warn_once("EPT CAP should not exist if not support "
2413                                 "1-setting enable EPT VM-execution control\n");
2414         }
2415         if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
2416                 vmx_cap->vpid) {
2417                 vmx_cap->vpid = 0;
2418                 pr_warn_once("VPID CAP should not exist if not support "
2419                                 "1-setting enable VPID VM-execution control\n");
2420         }
2421
2422         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
2423 #ifdef CONFIG_X86_64
2424         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2425 #endif
2426         opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2427               VM_EXIT_LOAD_IA32_PAT |
2428               VM_EXIT_LOAD_IA32_EFER |
2429               VM_EXIT_CLEAR_BNDCFGS |
2430               VM_EXIT_PT_CONCEAL_PIP |
2431               VM_EXIT_CLEAR_IA32_RTIT_CTL;
2432         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2433                                 &_vmexit_control) < 0)
2434                 return -EIO;
2435
2436         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2437         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2438                  PIN_BASED_VMX_PREEMPTION_TIMER;
2439         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2440                                 &_pin_based_exec_control) < 0)
2441                 return -EIO;
2442
2443         if (cpu_has_broken_vmx_preemption_timer())
2444                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2445         if (!(_cpu_based_2nd_exec_control &
2446                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
2447                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2448
2449         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2450         opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2451               VM_ENTRY_LOAD_IA32_PAT |
2452               VM_ENTRY_LOAD_IA32_EFER |
2453               VM_ENTRY_LOAD_BNDCFGS |
2454               VM_ENTRY_PT_CONCEAL_PIP |
2455               VM_ENTRY_LOAD_IA32_RTIT_CTL;
2456         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2457                                 &_vmentry_control) < 0)
2458                 return -EIO;
2459
2460         /*
2461          * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2462          * can't be used due to an errata where VM Exit may incorrectly clear
2463          * IA32_PERF_GLOBAL_CTRL[34:32].  Workaround the errata by using the
2464          * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2465          */
2466         if (boot_cpu_data.x86 == 0x6) {
2467                 switch (boot_cpu_data.x86_model) {
2468                 case 26: /* AAK155 */
2469                 case 30: /* AAP115 */
2470                 case 37: /* AAT100 */
2471                 case 44: /* BC86,AAY89,BD102 */
2472                 case 46: /* BA97 */
2473                         _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
2474                         _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2475                         pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2476                                         "does not work properly. Using workaround\n");
2477                         break;
2478                 default:
2479                         break;
2480                 }
2481         }
2482
2483
2484         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2485
2486         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2487         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2488                 return -EIO;
2489
2490 #ifdef CONFIG_X86_64
2491         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2492         if (vmx_msr_high & (1u<<16))
2493                 return -EIO;
2494 #endif
2495
2496         /* Require Write-Back (WB) memory type for VMCS accesses. */
2497         if (((vmx_msr_high >> 18) & 15) != 6)
2498                 return -EIO;
2499
2500         vmcs_conf->size = vmx_msr_high & 0x1fff;
2501         vmcs_conf->order = get_order(vmcs_conf->size);
2502         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
2503
2504         vmcs_conf->revision_id = vmx_msr_low;
2505
2506         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2507         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2508         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2509         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2510         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2511
2512         if (static_branch_unlikely(&enable_evmcs))
2513                 evmcs_sanitize_exec_ctrls(vmcs_conf);
2514
2515         return 0;
2516 }
2517
2518 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
2519 {
2520         int node = cpu_to_node(cpu);
2521         struct page *pages;
2522         struct vmcs *vmcs;
2523
2524         pages = __alloc_pages_node(node, flags, vmcs_config.order);
2525         if (!pages)
2526                 return NULL;
2527         vmcs = page_address(pages);
2528         memset(vmcs, 0, vmcs_config.size);
2529
2530         /* KVM supports Enlightened VMCS v1 only */
2531         if (static_branch_unlikely(&enable_evmcs))
2532                 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2533         else
2534                 vmcs->hdr.revision_id = vmcs_config.revision_id;
2535
2536         if (shadow)
2537                 vmcs->hdr.shadow_vmcs = 1;
2538         return vmcs;
2539 }
2540
2541 void free_vmcs(struct vmcs *vmcs)
2542 {
2543         free_pages((unsigned long)vmcs, vmcs_config.order);
2544 }
2545
2546 /*
2547  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2548  */
2549 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2550 {
2551         if (!loaded_vmcs->vmcs)
2552                 return;
2553         loaded_vmcs_clear(loaded_vmcs);
2554         free_vmcs(loaded_vmcs->vmcs);
2555         loaded_vmcs->vmcs = NULL;
2556         if (loaded_vmcs->msr_bitmap)
2557                 free_page((unsigned long)loaded_vmcs->msr_bitmap);
2558         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
2559 }
2560
2561 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2562 {
2563         loaded_vmcs->vmcs = alloc_vmcs(false);
2564         if (!loaded_vmcs->vmcs)
2565                 return -ENOMEM;
2566
2567         vmcs_clear(loaded_vmcs->vmcs);
2568
2569         loaded_vmcs->shadow_vmcs = NULL;
2570         loaded_vmcs->hv_timer_soft_disabled = false;
2571         loaded_vmcs->cpu = -1;
2572         loaded_vmcs->launched = 0;
2573
2574         if (cpu_has_vmx_msr_bitmap()) {
2575                 loaded_vmcs->msr_bitmap = (unsigned long *)
2576                                 __get_free_page(GFP_KERNEL_ACCOUNT);
2577                 if (!loaded_vmcs->msr_bitmap)
2578                         goto out_vmcs;
2579                 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
2580
2581                 if (IS_ENABLED(CONFIG_HYPERV) &&
2582                     static_branch_unlikely(&enable_evmcs) &&
2583                     (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2584                         struct hv_enlightened_vmcs *evmcs =
2585                                 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2586
2587                         evmcs->hv_enlightenments_control.msr_bitmap = 1;
2588                 }
2589         }
2590
2591         memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2592         memset(&loaded_vmcs->controls_shadow, 0,
2593                 sizeof(struct vmcs_controls_shadow));
2594
2595         return 0;
2596
2597 out_vmcs:
2598         free_loaded_vmcs(loaded_vmcs);
2599         return -ENOMEM;
2600 }
2601
2602 static void free_kvm_area(void)
2603 {
2604         int cpu;
2605
2606         for_each_possible_cpu(cpu) {
2607                 free_vmcs(per_cpu(vmxarea, cpu));
2608                 per_cpu(vmxarea, cpu) = NULL;
2609         }
2610 }
2611
2612 static __init int alloc_kvm_area(void)
2613 {
2614         int cpu;
2615
2616         for_each_possible_cpu(cpu) {
2617                 struct vmcs *vmcs;
2618
2619                 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
2620                 if (!vmcs) {
2621                         free_kvm_area();
2622                         return -ENOMEM;
2623                 }
2624
2625                 /*
2626                  * When eVMCS is enabled, alloc_vmcs_cpu() sets
2627                  * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2628                  * revision_id reported by MSR_IA32_VMX_BASIC.
2629                  *
2630                  * However, even though not explicitly documented by
2631                  * TLFS, VMXArea passed as VMXON argument should
2632                  * still be marked with revision_id reported by
2633                  * physical CPU.
2634                  */
2635                 if (static_branch_unlikely(&enable_evmcs))
2636                         vmcs->hdr.revision_id = vmcs_config.revision_id;
2637
2638                 per_cpu(vmxarea, cpu) = vmcs;
2639         }
2640         return 0;
2641 }
2642
2643 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2644                 struct kvm_segment *save)
2645 {
2646         if (!emulate_invalid_guest_state) {
2647                 /*
2648                  * CS and SS RPL should be equal during guest entry according
2649                  * to VMX spec, but in reality it is not always so. Since vcpu
2650                  * is in the middle of the transition from real mode to
2651                  * protected mode it is safe to assume that RPL 0 is a good
2652                  * default value.
2653                  */
2654                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2655                         save->selector &= ~SEGMENT_RPL_MASK;
2656                 save->dpl = save->selector & SEGMENT_RPL_MASK;
2657                 save->s = 1;
2658         }
2659         vmx_set_segment(vcpu, save, seg);
2660 }
2661
2662 static void enter_pmode(struct kvm_vcpu *vcpu)
2663 {
2664         unsigned long flags;
2665         struct vcpu_vmx *vmx = to_vmx(vcpu);
2666
2667         /*
2668          * Update real mode segment cache. It may be not up-to-date if sement
2669          * register was written while vcpu was in a guest mode.
2670          */
2671         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2672         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2673         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2674         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2675         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2676         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2677
2678         vmx->rmode.vm86_active = 0;
2679
2680         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2681
2682         flags = vmcs_readl(GUEST_RFLAGS);
2683         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2684         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2685         vmcs_writel(GUEST_RFLAGS, flags);
2686
2687         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2688                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2689
2690         update_exception_bitmap(vcpu);
2691
2692         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2693         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2694         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2695         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2696         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2697         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2698 }
2699
2700 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2701 {
2702         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2703         struct kvm_segment var = *save;
2704
2705         var.dpl = 0x3;
2706         if (seg == VCPU_SREG_CS)
2707                 var.type = 0x3;
2708
2709         if (!emulate_invalid_guest_state) {
2710                 var.selector = var.base >> 4;
2711                 var.base = var.base & 0xffff0;
2712                 var.limit = 0xffff;
2713                 var.g = 0;
2714                 var.db = 0;
2715                 var.present = 1;
2716                 var.s = 1;
2717                 var.l = 0;
2718                 var.unusable = 0;
2719                 var.type = 0x3;
2720                 var.avl = 0;
2721                 if (save->base & 0xf)
2722                         printk_once(KERN_WARNING "kvm: segment base is not "
2723                                         "paragraph aligned when entering "
2724                                         "protected mode (seg=%d)", seg);
2725         }
2726
2727         vmcs_write16(sf->selector, var.selector);
2728         vmcs_writel(sf->base, var.base);
2729         vmcs_write32(sf->limit, var.limit);
2730         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2731 }
2732
2733 static void enter_rmode(struct kvm_vcpu *vcpu)
2734 {
2735         unsigned long flags;
2736         struct vcpu_vmx *vmx = to_vmx(vcpu);
2737         struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
2738
2739         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2740         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2741         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2742         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2743         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2744         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2745         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2746
2747         vmx->rmode.vm86_active = 1;
2748
2749         /*
2750          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2751          * vcpu. Warn the user that an update is overdue.
2752          */
2753         if (!kvm_vmx->tss_addr)
2754                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2755                              "called before entering vcpu\n");
2756
2757         vmx_segment_cache_clear(vmx);
2758
2759         vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
2760         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2761         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2762
2763         flags = vmcs_readl(GUEST_RFLAGS);
2764         vmx->rmode.save_rflags = flags;
2765
2766         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2767
2768         vmcs_writel(GUEST_RFLAGS, flags);
2769         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2770         update_exception_bitmap(vcpu);
2771
2772         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2773         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2774         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2775         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2776         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2777         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2778
2779         kvm_mmu_reset_context(vcpu);
2780 }
2781
2782 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2783 {
2784         struct vcpu_vmx *vmx = to_vmx(vcpu);
2785         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2786
2787         if (!msr)
2788                 return;
2789
2790         vcpu->arch.efer = efer;
2791         if (efer & EFER_LMA) {
2792                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2793                 msr->data = efer;
2794         } else {
2795                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2796
2797                 msr->data = efer & ~EFER_LME;
2798         }
2799         setup_msrs(vmx);
2800 }
2801
2802 #ifdef CONFIG_X86_64
2803
2804 static void enter_lmode(struct kvm_vcpu *vcpu)
2805 {
2806         u32 guest_tr_ar;
2807
2808         vmx_segment_cache_clear(to_vmx(vcpu));
2809
2810         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2811         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
2812                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2813                                      __func__);
2814                 vmcs_write32(GUEST_TR_AR_BYTES,
2815                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2816                              | VMX_AR_TYPE_BUSY_64_TSS);
2817         }
2818         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2819 }
2820
2821 static void exit_lmode(struct kvm_vcpu *vcpu)
2822 {
2823         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2824         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2825 }
2826
2827 #endif
2828
2829 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2830 {
2831         int vpid = to_vmx(vcpu)->vpid;
2832
2833         if (!vpid_sync_vcpu_addr(vpid, addr))
2834                 vpid_sync_context(vpid);
2835
2836         /*
2837          * If VPIDs are not supported or enabled, then the above is a no-op.
2838          * But we don't really need a TLB flush in that case anyway, because
2839          * each VM entry/exit includes an implicit flush when VPID is 0.
2840          */
2841 }
2842
2843 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2844 {
2845         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2846
2847         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2848         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2849 }
2850
2851 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2852 {
2853         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2854
2855         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2856         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2857 }
2858
2859 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2860 {
2861         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2862
2863         if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR))
2864                 return;
2865
2866         if (is_pae_paging(vcpu)) {
2867                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2868                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2869                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2870                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
2871         }
2872 }
2873
2874 void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2875 {
2876         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2877
2878         if (is_pae_paging(vcpu)) {
2879                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2880                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2881                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2882                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2883         }
2884
2885         kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
2886 }
2887
2888 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2889                                         unsigned long cr0,
2890                                         struct kvm_vcpu *vcpu)
2891 {
2892         struct vcpu_vmx *vmx = to_vmx(vcpu);
2893
2894         if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3))
2895                 vmx_cache_reg(vcpu, VCPU_EXREG_CR3);
2896         if (!(cr0 & X86_CR0_PG)) {
2897                 /* From paging/starting to nonpaging */
2898                 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2899                                           CPU_BASED_CR3_STORE_EXITING);
2900                 vcpu->arch.cr0 = cr0;
2901                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2902         } else if (!is_paging(vcpu)) {
2903                 /* From nonpaging to paging */
2904                 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2905                                             CPU_BASED_CR3_STORE_EXITING);
2906                 vcpu->arch.cr0 = cr0;
2907                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2908         }
2909
2910         if (!(cr0 & X86_CR0_WP))
2911                 *hw_cr0 &= ~X86_CR0_WP;
2912 }
2913
2914 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2915 {
2916         struct vcpu_vmx *vmx = to_vmx(vcpu);
2917         unsigned long hw_cr0;
2918
2919         hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
2920         if (enable_unrestricted_guest)
2921                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2922         else {
2923                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
2924
2925                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2926                         enter_pmode(vcpu);
2927
2928                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2929                         enter_rmode(vcpu);
2930         }
2931
2932 #ifdef CONFIG_X86_64
2933         if (vcpu->arch.efer & EFER_LME) {
2934                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2935                         enter_lmode(vcpu);
2936                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2937                         exit_lmode(vcpu);
2938         }
2939 #endif
2940
2941         if (enable_ept && !enable_unrestricted_guest)
2942                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2943
2944         vmcs_writel(CR0_READ_SHADOW, cr0);
2945         vmcs_writel(GUEST_CR0, hw_cr0);
2946         vcpu->arch.cr0 = cr0;
2947
2948         /* depends on vcpu->arch.cr0 to be set to a new value */
2949         vmx->emulation_required = emulation_required(vcpu);
2950 }
2951
2952 static int get_ept_level(struct kvm_vcpu *vcpu)
2953 {
2954         if (is_guest_mode(vcpu) && nested_cpu_has_ept(get_vmcs12(vcpu)))
2955                 return vmx_eptp_page_walk_level(nested_ept_get_eptp(vcpu));
2956         if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
2957                 return 5;
2958         return 4;
2959 }
2960
2961 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
2962 {
2963         u64 eptp = VMX_EPTP_MT_WB;
2964
2965         eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
2966
2967         if (enable_ept_ad_bits &&
2968             (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
2969                 eptp |= VMX_EPTP_AD_ENABLE_BIT;
2970         eptp |= (root_hpa & PAGE_MASK);
2971
2972         return eptp;
2973 }
2974
2975 void vmx_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long cr3)
2976 {
2977         struct kvm *kvm = vcpu->kvm;
2978         bool update_guest_cr3 = true;
2979         unsigned long guest_cr3;
2980         u64 eptp;
2981
2982         guest_cr3 = cr3;
2983         if (enable_ept) {
2984                 eptp = construct_eptp(vcpu, cr3);
2985                 vmcs_write64(EPT_POINTER, eptp);
2986
2987                 if (kvm_x86_ops->tlb_remote_flush) {
2988                         spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
2989                         to_vmx(vcpu)->ept_pointer = eptp;
2990                         to_kvm_vmx(kvm)->ept_pointers_match
2991                                 = EPT_POINTERS_CHECK;
2992                         spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
2993                 }
2994
2995                 /* Loading vmcs02.GUEST_CR3 is handled by nested VM-Enter. */
2996                 if (is_guest_mode(vcpu))
2997                         update_guest_cr3 = false;
2998                 else if (!enable_unrestricted_guest && !is_paging(vcpu))
2999                         guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
3000                 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3001                         guest_cr3 = vcpu->arch.cr3;
3002                 else /* vmcs01.GUEST_CR3 is already up-to-date. */
3003                         update_guest_cr3 = false;
3004                 ept_load_pdptrs(vcpu);
3005         }
3006
3007         if (update_guest_cr3)
3008                 vmcs_writel(GUEST_CR3, guest_cr3);
3009 }
3010
3011 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3012 {
3013         struct vcpu_vmx *vmx = to_vmx(vcpu);
3014         /*
3015          * Pass through host's Machine Check Enable value to hw_cr4, which
3016          * is in force while we are in guest mode.  Do not let guests control
3017          * this bit, even if host CR4.MCE == 0.
3018          */
3019         unsigned long hw_cr4;
3020
3021         hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
3022         if (enable_unrestricted_guest)
3023                 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
3024         else if (vmx->rmode.vm86_active)
3025                 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
3026         else
3027                 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
3028
3029         if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
3030                 if (cr4 & X86_CR4_UMIP) {
3031                         secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
3032                         hw_cr4 &= ~X86_CR4_UMIP;
3033                 } else if (!is_guest_mode(vcpu) ||
3034                         !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
3035                         secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
3036                 }
3037         }
3038
3039         if (cr4 & X86_CR4_VMXE) {
3040                 /*
3041                  * To use VMXON (and later other VMX instructions), a guest
3042                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3043                  * So basically the check on whether to allow nested VMX
3044                  * is here.  We operate under the default treatment of SMM,
3045                  * so VMX cannot be enabled under SMM.
3046                  */
3047                 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
3048                         return 1;
3049         }
3050
3051         if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
3052                 return 1;
3053
3054         vcpu->arch.cr4 = cr4;
3055
3056         if (!enable_unrestricted_guest) {
3057                 if (enable_ept) {
3058                         if (!is_paging(vcpu)) {
3059                                 hw_cr4 &= ~X86_CR4_PAE;
3060                                 hw_cr4 |= X86_CR4_PSE;
3061                         } else if (!(cr4 & X86_CR4_PAE)) {
3062                                 hw_cr4 &= ~X86_CR4_PAE;
3063                         }
3064                 }
3065
3066                 /*
3067                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3068                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
3069                  * to be manually disabled when guest switches to non-paging
3070                  * mode.
3071                  *
3072                  * If !enable_unrestricted_guest, the CPU is always running
3073                  * with CR0.PG=1 and CR4 needs to be modified.
3074                  * If enable_unrestricted_guest, the CPU automatically
3075                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3076                  */
3077                 if (!is_paging(vcpu))
3078                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3079         }
3080
3081         vmcs_writel(CR4_READ_SHADOW, cr4);
3082         vmcs_writel(GUEST_CR4, hw_cr4);
3083         return 0;
3084 }
3085
3086 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3087 {
3088         struct vcpu_vmx *vmx = to_vmx(vcpu);
3089         u32 ar;
3090
3091         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3092                 *var = vmx->rmode.segs[seg];
3093                 if (seg == VCPU_SREG_TR
3094                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3095                         return;
3096                 var->base = vmx_read_guest_seg_base(vmx, seg);
3097                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3098                 return;
3099         }
3100         var->base = vmx_read_guest_seg_base(vmx, seg);
3101         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3102         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3103         ar = vmx_read_guest_seg_ar(vmx, seg);
3104         var->unusable = (ar >> 16) & 1;
3105         var->type = ar & 15;
3106         var->s = (ar >> 4) & 1;
3107         var->dpl = (ar >> 5) & 3;
3108         /*
3109          * Some userspaces do not preserve unusable property. Since usable
3110          * segment has to be present according to VMX spec we can use present
3111          * property to amend userspace bug by making unusable segment always
3112          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3113          * segment as unusable.
3114          */
3115         var->present = !var->unusable;
3116         var->avl = (ar >> 12) & 1;
3117         var->l = (ar >> 13) & 1;
3118         var->db = (ar >> 14) & 1;
3119         var->g = (ar >> 15) & 1;
3120 }
3121
3122 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3123 {
3124         struct kvm_segment s;
3125
3126         if (to_vmx(vcpu)->rmode.vm86_active) {
3127                 vmx_get_segment(vcpu, &s, seg);
3128                 return s.base;
3129         }
3130         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3131 }
3132
3133 int vmx_get_cpl(struct kvm_vcpu *vcpu)
3134 {
3135         struct vcpu_vmx *vmx = to_vmx(vcpu);
3136
3137         if (unlikely(vmx->rmode.vm86_active))
3138                 return 0;
3139         else {
3140                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3141                 return VMX_AR_DPL(ar);
3142         }
3143 }
3144
3145 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3146 {
3147         u32 ar;
3148
3149         if (var->unusable || !var->present)
3150                 ar = 1 << 16;
3151         else {
3152                 ar = var->type & 15;
3153                 ar |= (var->s & 1) << 4;
3154                 ar |= (var->dpl & 3) << 5;
3155                 ar |= (var->present & 1) << 7;
3156                 ar |= (var->avl & 1) << 12;
3157                 ar |= (var->l & 1) << 13;
3158                 ar |= (var->db & 1) << 14;
3159                 ar |= (var->g & 1) << 15;
3160         }
3161
3162         return ar;
3163 }
3164
3165 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3166 {
3167         struct vcpu_vmx *vmx = to_vmx(vcpu);
3168         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3169
3170         vmx_segment_cache_clear(vmx);
3171
3172         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3173                 vmx->rmode.segs[seg] = *var;
3174                 if (seg == VCPU_SREG_TR)
3175                         vmcs_write16(sf->selector, var->selector);
3176                 else if (var->s)
3177                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3178                 goto out;
3179         }
3180
3181         vmcs_writel(sf->base, var->base);
3182         vmcs_write32(sf->limit, var->limit);
3183         vmcs_write16(sf->selector, var->selector);
3184
3185         /*
3186          *   Fix the "Accessed" bit in AR field of segment registers for older
3187          * qemu binaries.
3188          *   IA32 arch specifies that at the time of processor reset the
3189          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3190          * is setting it to 0 in the userland code. This causes invalid guest
3191          * state vmexit when "unrestricted guest" mode is turned on.
3192          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3193          * tree. Newer qemu binaries with that qemu fix would not need this
3194          * kvm hack.
3195          */
3196         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3197                 var->type |= 0x1; /* Accessed */
3198
3199         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3200
3201 out:
3202         vmx->emulation_required = emulation_required(vcpu);
3203 }
3204
3205 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3206 {
3207         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3208
3209         *db = (ar >> 14) & 1;
3210         *l = (ar >> 13) & 1;
3211 }
3212
3213 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3214 {
3215         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3216         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3217 }
3218
3219 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3220 {
3221         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3222         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3223 }
3224
3225 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3226 {
3227         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3228         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3229 }
3230
3231 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3232 {
3233         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3234         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3235 }
3236
3237 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3238 {
3239         struct kvm_segment var;
3240         u32 ar;
3241
3242         vmx_get_segment(vcpu, &var, seg);
3243         var.dpl = 0x3;
3244         if (seg == VCPU_SREG_CS)
3245                 var.type = 0x3;
3246         ar = vmx_segment_access_rights(&var);
3247
3248         if (var.base != (var.selector << 4))
3249                 return false;
3250         if (var.limit != 0xffff)
3251                 return false;
3252         if (ar != 0xf3)
3253                 return false;
3254
3255         return true;
3256 }
3257
3258 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3259 {
3260         struct kvm_segment cs;
3261         unsigned int cs_rpl;
3262
3263         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3264         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3265
3266         if (cs.unusable)
3267                 return false;
3268         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3269                 return false;
3270         if (!cs.s)
3271                 return false;
3272         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3273                 if (cs.dpl > cs_rpl)
3274                         return false;
3275         } else {
3276                 if (cs.dpl != cs_rpl)
3277                         return false;
3278         }
3279         if (!cs.present)
3280                 return false;
3281
3282         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3283         return true;
3284 }
3285
3286 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3287 {
3288         struct kvm_segment ss;
3289         unsigned int ss_rpl;
3290
3291         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3292         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3293
3294         if (ss.unusable)
3295                 return true;
3296         if (ss.type != 3 && ss.type != 7)
3297                 return false;
3298         if (!ss.s)
3299                 return false;
3300         if (ss.dpl != ss_rpl) /* DPL != RPL */
3301                 return false;
3302         if (!ss.present)
3303                 return false;
3304
3305         return true;
3306 }
3307
3308 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3309 {
3310         struct kvm_segment var;
3311         unsigned int rpl;
3312
3313         vmx_get_segment(vcpu, &var, seg);
3314         rpl = var.selector & SEGMENT_RPL_MASK;
3315
3316         if (var.unusable)
3317                 return true;
3318         if (!var.s)
3319                 return false;
3320         if (!var.present)
3321                 return false;
3322         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
3323                 if (var.dpl < rpl) /* DPL < RPL */
3324                         return false;
3325         }
3326
3327         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3328          * rights flags
3329          */
3330         return true;
3331 }
3332
3333 static bool tr_valid(struct kvm_vcpu *vcpu)
3334 {
3335         struct kvm_segment tr;
3336
3337         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3338
3339         if (tr.unusable)
3340                 return false;
3341         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
3342                 return false;
3343         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3344                 return false;
3345         if (!tr.present)
3346                 return false;
3347
3348         return true;
3349 }
3350
3351 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3352 {
3353         struct kvm_segment ldtr;
3354
3355         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3356
3357         if (ldtr.unusable)
3358                 return true;
3359         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
3360                 return false;
3361         if (ldtr.type != 2)
3362                 return false;
3363         if (!ldtr.present)
3364                 return false;
3365
3366         return true;
3367 }
3368
3369 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3370 {
3371         struct kvm_segment cs, ss;
3372
3373         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3374         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3375
3376         return ((cs.selector & SEGMENT_RPL_MASK) ==
3377                  (ss.selector & SEGMENT_RPL_MASK));
3378 }
3379
3380 /*
3381  * Check if guest state is valid. Returns true if valid, false if
3382  * not.
3383  * We assume that registers are always usable
3384  */
3385 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3386 {
3387         if (enable_unrestricted_guest)
3388                 return true;
3389
3390         /* real mode guest state checks */
3391         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3392                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3393                         return false;
3394                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3395                         return false;
3396                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3397                         return false;
3398                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3399                         return false;
3400                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3401                         return false;
3402                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3403                         return false;
3404         } else {
3405         /* protected mode guest state checks */
3406                 if (!cs_ss_rpl_check(vcpu))
3407                         return false;
3408                 if (!code_segment_valid(vcpu))
3409                         return false;
3410                 if (!stack_segment_valid(vcpu))
3411                         return false;
3412                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3413                         return false;
3414                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3415                         return false;
3416                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3417                         return false;
3418                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3419                         return false;
3420                 if (!tr_valid(vcpu))
3421                         return false;
3422                 if (!ldtr_valid(vcpu))
3423                         return false;
3424         }
3425         /* TODO:
3426          * - Add checks on RIP
3427          * - Add checks on RFLAGS
3428          */
3429
3430         return true;
3431 }
3432
3433 static int init_rmode_tss(struct kvm *kvm)
3434 {
3435         gfn_t fn;
3436         u16 data = 0;
3437         int idx, r;
3438
3439         idx = srcu_read_lock(&kvm->srcu);
3440         fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
3441         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3442         if (r < 0)
3443                 goto out;
3444         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3445         r = kvm_write_guest_page(kvm, fn++, &data,
3446                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3447         if (r < 0)
3448                 goto out;
3449         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3450         if (r < 0)
3451                 goto out;
3452         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3453         if (r < 0)
3454                 goto out;
3455         data = ~0;
3456         r = kvm_write_guest_page(kvm, fn, &data,
3457                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3458                                  sizeof(u8));
3459 out:
3460         srcu_read_unlock(&kvm->srcu, idx);
3461         return r;
3462 }
3463
3464 static int init_rmode_identity_map(struct kvm *kvm)
3465 {
3466         struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
3467         int i, r = 0;
3468         kvm_pfn_t identity_map_pfn;
3469         u32 tmp;
3470
3471         /* Protect kvm_vmx->ept_identity_pagetable_done. */
3472         mutex_lock(&kvm->slots_lock);
3473
3474         if (likely(kvm_vmx->ept_identity_pagetable_done))
3475                 goto out;
3476
3477         if (!kvm_vmx->ept_identity_map_addr)
3478                 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3479         identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
3480
3481         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
3482                                     kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
3483         if (r < 0)
3484                 goto out;
3485
3486         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3487         if (r < 0)
3488                 goto out;
3489         /* Set up identity-mapping pagetable for EPT in real mode */
3490         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3491                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3492                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3493                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3494                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3495                 if (r < 0)
3496                         goto out;
3497         }
3498         kvm_vmx->ept_identity_pagetable_done = true;
3499
3500 out:
3501         mutex_unlock(&kvm->slots_lock);
3502         return r;
3503 }
3504
3505 static void seg_setup(int seg)
3506 {
3507         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3508         unsigned int ar;
3509
3510         vmcs_write16(sf->selector, 0);
3511         vmcs_writel(sf->base, 0);
3512         vmcs_write32(sf->limit, 0xffff);
3513         ar = 0x93;
3514         if (seg == VCPU_SREG_CS)
3515                 ar |= 0x08; /* code segment */
3516
3517         vmcs_write32(sf->ar_bytes, ar);
3518 }
3519
3520 static int alloc_apic_access_page(struct kvm *kvm)
3521 {
3522         struct page *page;
3523         int r = 0;
3524
3525         mutex_lock(&kvm->slots_lock);
3526         if (kvm->arch.apic_access_page_done)
3527                 goto out;
3528         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3529                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
3530         if (r)
3531                 goto out;
3532
3533         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
3534         if (is_error_page(page)) {
3535                 r = -EFAULT;
3536                 goto out;
3537         }
3538
3539         /*
3540          * Do not pin the page in memory, so that memory hot-unplug
3541          * is able to migrate it.
3542          */
3543         put_page(page);
3544         kvm->arch.apic_access_page_done = true;
3545 out:
3546         mutex_unlock(&kvm->slots_lock);
3547         return r;
3548 }
3549
3550 int allocate_vpid(void)
3551 {
3552         int vpid;
3553
3554         if (!enable_vpid)
3555                 return 0;
3556         spin_lock(&vmx_vpid_lock);
3557         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3558         if (vpid < VMX_NR_VPIDS)
3559                 __set_bit(vpid, vmx_vpid_bitmap);
3560         else
3561                 vpid = 0;
3562         spin_unlock(&vmx_vpid_lock);
3563         return vpid;
3564 }
3565
3566 void free_vpid(int vpid)
3567 {
3568         if (!enable_vpid || vpid == 0)
3569                 return;
3570         spin_lock(&vmx_vpid_lock);
3571         __clear_bit(vpid, vmx_vpid_bitmap);
3572         spin_unlock(&vmx_vpid_lock);
3573 }
3574
3575 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3576                                                           u32 msr, int type)
3577 {
3578         int f = sizeof(unsigned long);
3579
3580         if (!cpu_has_vmx_msr_bitmap())
3581                 return;
3582
3583         if (static_branch_unlikely(&enable_evmcs))
3584                 evmcs_touch_msr_bitmap();
3585
3586         /*
3587          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3588          * have the write-low and read-high bitmap offsets the wrong way round.
3589          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3590          */
3591         if (msr <= 0x1fff) {
3592                 if (type & MSR_TYPE_R)
3593                         /* read-low */
3594                         __clear_bit(msr, msr_bitmap + 0x000 / f);
3595
3596                 if (type & MSR_TYPE_W)
3597                         /* write-low */
3598                         __clear_bit(msr, msr_bitmap + 0x800 / f);
3599
3600         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3601                 msr &= 0x1fff;
3602                 if (type & MSR_TYPE_R)
3603                         /* read-high */
3604                         __clear_bit(msr, msr_bitmap + 0x400 / f);
3605
3606                 if (type & MSR_TYPE_W)
3607                         /* write-high */
3608                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
3609
3610         }
3611 }
3612
3613 static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3614                                                          u32 msr, int type)
3615 {
3616         int f = sizeof(unsigned long);
3617
3618         if (!cpu_has_vmx_msr_bitmap())
3619                 return;
3620
3621         if (static_branch_unlikely(&enable_evmcs))
3622                 evmcs_touch_msr_bitmap();
3623
3624         /*
3625          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3626          * have the write-low and read-high bitmap offsets the wrong way round.
3627          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3628          */
3629         if (msr <= 0x1fff) {
3630                 if (type & MSR_TYPE_R)
3631                         /* read-low */
3632                         __set_bit(msr, msr_bitmap + 0x000 / f);
3633
3634                 if (type & MSR_TYPE_W)
3635                         /* write-low */
3636                         __set_bit(msr, msr_bitmap + 0x800 / f);
3637
3638         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3639                 msr &= 0x1fff;
3640                 if (type & MSR_TYPE_R)
3641                         /* read-high */
3642                         __set_bit(msr, msr_bitmap + 0x400 / f);
3643
3644                 if (type & MSR_TYPE_W)
3645                         /* write-high */
3646                         __set_bit(msr, msr_bitmap + 0xc00 / f);
3647
3648         }
3649 }
3650
3651 static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
3652                                                       u32 msr, int type, bool value)
3653 {
3654         if (value)
3655                 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
3656         else
3657                 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
3658 }
3659
3660 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
3661 {
3662         u8 mode = 0;
3663
3664         if (cpu_has_secondary_exec_ctrls() &&
3665             (secondary_exec_controls_get(to_vmx(vcpu)) &
3666              SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3667                 mode |= MSR_BITMAP_MODE_X2APIC;
3668                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3669                         mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3670         }
3671
3672         return mode;
3673 }
3674
3675 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
3676                                          u8 mode)
3677 {
3678         int msr;
3679
3680         for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3681                 unsigned word = msr / BITS_PER_LONG;
3682                 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3683                 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
3684         }
3685
3686         if (mode & MSR_BITMAP_MODE_X2APIC) {
3687                 /*
3688                  * TPR reads and writes can be virtualized even if virtual interrupt
3689                  * delivery is not in use.
3690                  */
3691                 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
3692                 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3693                         vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
3694                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3695                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3696                 }
3697         }
3698 }
3699
3700 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
3701 {
3702         struct vcpu_vmx *vmx = to_vmx(vcpu);
3703         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3704         u8 mode = vmx_msr_bitmap_mode(vcpu);
3705         u8 changed = mode ^ vmx->msr_bitmap_mode;
3706
3707         if (!changed)
3708                 return;
3709
3710         if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
3711                 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
3712
3713         vmx->msr_bitmap_mode = mode;
3714 }
3715
3716 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx)
3717 {
3718         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3719         bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3720         u32 i;
3721
3722         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS,
3723                                                         MSR_TYPE_RW, flag);
3724         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE,
3725                                                         MSR_TYPE_RW, flag);
3726         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK,
3727                                                         MSR_TYPE_RW, flag);
3728         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH,
3729                                                         MSR_TYPE_RW, flag);
3730         for (i = 0; i < vmx->pt_desc.addr_range; i++) {
3731                 vmx_set_intercept_for_msr(msr_bitmap,
3732                         MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3733                 vmx_set_intercept_for_msr(msr_bitmap,
3734                         MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3735         }
3736 }
3737
3738 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3739 {
3740         struct vcpu_vmx *vmx = to_vmx(vcpu);
3741         void *vapic_page;
3742         u32 vppr;
3743         int rvi;
3744
3745         if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3746                 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
3747                 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
3748                 return false;
3749
3750         rvi = vmx_get_rvi();
3751
3752         vapic_page = vmx->nested.virtual_apic_map.hva;
3753         vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
3754
3755         return ((rvi & 0xf0) > (vppr & 0xf0));
3756 }
3757
3758 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3759                                                      bool nested)
3760 {
3761 #ifdef CONFIG_SMP
3762         int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3763
3764         if (vcpu->mode == IN_GUEST_MODE) {
3765                 /*
3766                  * The vector of interrupt to be delivered to vcpu had
3767                  * been set in PIR before this function.
3768                  *
3769                  * Following cases will be reached in this block, and
3770                  * we always send a notification event in all cases as
3771                  * explained below.
3772                  *
3773                  * Case 1: vcpu keeps in non-root mode. Sending a
3774                  * notification event posts the interrupt to vcpu.
3775                  *
3776                  * Case 2: vcpu exits to root mode and is still
3777                  * runnable. PIR will be synced to vIRR before the
3778                  * next vcpu entry. Sending a notification event in
3779                  * this case has no effect, as vcpu is not in root
3780                  * mode.
3781                  *
3782                  * Case 3: vcpu exits to root mode and is blocked.
3783                  * vcpu_block() has already synced PIR to vIRR and
3784                  * never blocks vcpu if vIRR is not cleared. Therefore,
3785                  * a blocked vcpu here does not wait for any requested
3786                  * interrupts in PIR, and sending a notification event
3787                  * which has no effect is safe here.
3788                  */
3789
3790                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
3791                 return true;
3792         }
3793 #endif
3794         return false;
3795 }
3796
3797 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3798                                                 int vector)
3799 {
3800         struct vcpu_vmx *vmx = to_vmx(vcpu);
3801
3802         if (is_guest_mode(vcpu) &&
3803             vector == vmx->nested.posted_intr_nv) {
3804                 /*
3805                  * If a posted intr is not recognized by hardware,
3806                  * we will accomplish it in the next vmentry.
3807                  */
3808                 vmx->nested.pi_pending = true;
3809                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3810                 /* the PIR and ON have been set by L1. */
3811                 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3812                         kvm_vcpu_kick(vcpu);
3813                 return 0;
3814         }
3815         return -1;
3816 }
3817 /*
3818  * Send interrupt to vcpu via posted interrupt way.
3819  * 1. If target vcpu is running(non-root mode), send posted interrupt
3820  * notification to vcpu and hardware will sync PIR to vIRR atomically.
3821  * 2. If target vcpu isn't running(root mode), kick it to pick up the
3822  * interrupt from PIR in next vmentry.
3823  */
3824 static int vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3825 {
3826         struct vcpu_vmx *vmx = to_vmx(vcpu);
3827         int r;
3828
3829         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3830         if (!r)
3831                 return 0;
3832
3833         if (!vcpu->arch.apicv_active)
3834                 return -1;
3835
3836         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
3837                 return 0;
3838
3839         /* If a previous notification has sent the IPI, nothing to do.  */
3840         if (pi_test_and_set_on(&vmx->pi_desc))
3841                 return 0;
3842
3843         if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
3844                 kvm_vcpu_kick(vcpu);
3845
3846         return 0;
3847 }
3848
3849 /*
3850  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3851  * will not change in the lifetime of the guest.
3852  * Note that host-state that does change is set elsewhere. E.g., host-state
3853  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3854  */
3855 void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
3856 {
3857         u32 low32, high32;
3858         unsigned long tmpl;
3859         unsigned long cr0, cr3, cr4;
3860
3861         cr0 = read_cr0();
3862         WARN_ON(cr0 & X86_CR0_TS);
3863         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
3864
3865         /*
3866          * Save the most likely value for this task's CR3 in the VMCS.
3867          * We can't use __get_current_cr3_fast() because we're not atomic.
3868          */
3869         cr3 = __read_cr3();
3870         vmcs_writel(HOST_CR3, cr3);             /* 22.2.3  FIXME: shadow tables */
3871         vmx->loaded_vmcs->host_state.cr3 = cr3;
3872
3873         /* Save the most likely value for this task's CR4 in the VMCS. */
3874         cr4 = cr4_read_shadow();
3875         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
3876         vmx->loaded_vmcs->host_state.cr4 = cr4;
3877
3878         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
3879 #ifdef CONFIG_X86_64
3880         /*
3881          * Load null selectors, so we can avoid reloading them in
3882          * vmx_prepare_switch_to_host(), in case userspace uses
3883          * the null selectors too (the expected case).
3884          */
3885         vmcs_write16(HOST_DS_SELECTOR, 0);
3886         vmcs_write16(HOST_ES_SELECTOR, 0);
3887 #else
3888         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3889         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3890 #endif
3891         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3892         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
3893
3894         vmcs_writel(HOST_IDTR_BASE, host_idt_base);   /* 22.2.4 */
3895
3896         vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
3897
3898         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3899         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3900         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3901         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
3902
3903         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3904                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3905                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3906         }
3907
3908         if (cpu_has_load_ia32_efer())
3909                 vmcs_write64(HOST_IA32_EFER, host_efer);
3910 }
3911
3912 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3913 {
3914         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3915         if (enable_ept)
3916                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3917         if (is_guest_mode(&vmx->vcpu))
3918                 vmx->vcpu.arch.cr4_guest_owned_bits &=
3919                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3920         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3921 }
3922
3923 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
3924 {
3925         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
3926
3927         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
3928                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
3929
3930         if (!enable_vnmi)
3931                 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
3932
3933         if (!enable_preemption_timer)
3934                 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3935
3936         return pin_based_exec_ctrl;
3937 }
3938
3939 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
3940 {
3941         struct vcpu_vmx *vmx = to_vmx(vcpu);
3942
3943         pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
3944         if (cpu_has_secondary_exec_ctrls()) {
3945                 if (kvm_vcpu_apicv_active(vcpu))
3946                         secondary_exec_controls_setbit(vmx,
3947                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
3948                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3949                 else
3950                         secondary_exec_controls_clearbit(vmx,
3951                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3952                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3953         }
3954
3955         if (cpu_has_vmx_msr_bitmap())
3956                 vmx_update_msr_bitmap(vcpu);
3957 }
3958
3959 u32 vmx_exec_control(struct vcpu_vmx *vmx)
3960 {
3961         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3962
3963         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
3964                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
3965
3966         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
3967                 exec_control &= ~CPU_BASED_TPR_SHADOW;
3968 #ifdef CONFIG_X86_64
3969                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3970                                 CPU_BASED_CR8_LOAD_EXITING;
3971 #endif
3972         }
3973         if (!enable_ept)
3974                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3975                                 CPU_BASED_CR3_LOAD_EXITING  |
3976                                 CPU_BASED_INVLPG_EXITING;
3977         if (kvm_mwait_in_guest(vmx->vcpu.kvm))
3978                 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
3979                                 CPU_BASED_MONITOR_EXITING);
3980         if (kvm_hlt_in_guest(vmx->vcpu.kvm))
3981                 exec_control &= ~CPU_BASED_HLT_EXITING;
3982         return exec_control;
3983 }
3984
3985
3986 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
3987 {
3988         struct kvm_vcpu *vcpu = &vmx->vcpu;
3989
3990         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3991
3992         if (vmx_pt_mode_is_system())
3993                 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
3994         if (!cpu_need_virtualize_apic_accesses(vcpu))
3995                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3996         if (vmx->vpid == 0)
3997                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3998         if (!enable_ept) {
3999                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4000                 enable_unrestricted_guest = 0;
4001         }
4002         if (!enable_unrestricted_guest)
4003                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4004         if (kvm_pause_in_guest(vmx->vcpu.kvm))
4005                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4006         if (!kvm_vcpu_apicv_active(vcpu))
4007                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4008                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4009         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4010
4011         /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
4012          * in vmx_set_cr4.  */
4013         exec_control &= ~SECONDARY_EXEC_DESC;
4014
4015         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4016            (handle_vmptrld).
4017            We can NOT enable shadow_vmcs here because we don't have yet
4018            a current VMCS12
4019         */
4020         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4021
4022         if (!enable_pml)
4023                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4024
4025         if (vmx_xsaves_supported()) {
4026                 /* Exposing XSAVES only when XSAVE is exposed */
4027                 bool xsaves_enabled =
4028                         boot_cpu_has(X86_FEATURE_XSAVE) &&
4029                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4030                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
4031
4032                 vcpu->arch.xsaves_enabled = xsaves_enabled;
4033
4034                 if (!xsaves_enabled)
4035                         exec_control &= ~SECONDARY_EXEC_XSAVES;
4036
4037                 if (nested) {
4038                         if (xsaves_enabled)
4039                                 vmx->nested.msrs.secondary_ctls_high |=
4040                                         SECONDARY_EXEC_XSAVES;
4041                         else
4042                                 vmx->nested.msrs.secondary_ctls_high &=
4043                                         ~SECONDARY_EXEC_XSAVES;
4044                 }
4045         }
4046
4047         if (cpu_has_vmx_rdtscp()) {
4048                 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
4049                 if (!rdtscp_enabled)
4050                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
4051
4052                 if (nested) {
4053                         if (rdtscp_enabled)
4054                                 vmx->nested.msrs.secondary_ctls_high |=
4055                                         SECONDARY_EXEC_RDTSCP;
4056                         else
4057                                 vmx->nested.msrs.secondary_ctls_high &=
4058                                         ~SECONDARY_EXEC_RDTSCP;
4059                 }
4060         }
4061
4062         if (cpu_has_vmx_invpcid()) {
4063                 /* Exposing INVPCID only when PCID is exposed */
4064                 bool invpcid_enabled =
4065                         guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
4066                         guest_cpuid_has(vcpu, X86_FEATURE_PCID);
4067
4068                 if (!invpcid_enabled) {
4069                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4070                         guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
4071                 }
4072
4073                 if (nested) {
4074                         if (invpcid_enabled)
4075                                 vmx->nested.msrs.secondary_ctls_high |=
4076                                         SECONDARY_EXEC_ENABLE_INVPCID;
4077                         else
4078                                 vmx->nested.msrs.secondary_ctls_high &=
4079                                         ~SECONDARY_EXEC_ENABLE_INVPCID;
4080                 }
4081         }
4082
4083         if (vmx_rdrand_supported()) {
4084                 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
4085                 if (rdrand_enabled)
4086                         exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
4087
4088                 if (nested) {
4089                         if (rdrand_enabled)
4090                                 vmx->nested.msrs.secondary_ctls_high |=
4091                                         SECONDARY_EXEC_RDRAND_EXITING;
4092                         else
4093                                 vmx->nested.msrs.secondary_ctls_high &=
4094                                         ~SECONDARY_EXEC_RDRAND_EXITING;
4095                 }
4096         }
4097
4098         if (vmx_rdseed_supported()) {
4099                 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
4100                 if (rdseed_enabled)
4101                         exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
4102
4103                 if (nested) {
4104                         if (rdseed_enabled)
4105                                 vmx->nested.msrs.secondary_ctls_high |=
4106                                         SECONDARY_EXEC_RDSEED_EXITING;
4107                         else
4108                                 vmx->nested.msrs.secondary_ctls_high &=
4109                                         ~SECONDARY_EXEC_RDSEED_EXITING;
4110                 }
4111         }
4112
4113         if (vmx_waitpkg_supported()) {
4114                 bool waitpkg_enabled =
4115                         guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG);
4116
4117                 if (!waitpkg_enabled)
4118                         exec_control &= ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4119
4120                 if (nested) {
4121                         if (waitpkg_enabled)
4122                                 vmx->nested.msrs.secondary_ctls_high |=
4123                                         SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4124                         else
4125                                 vmx->nested.msrs.secondary_ctls_high &=
4126                                         ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4127                 }
4128         }
4129
4130         vmx->secondary_exec_control = exec_control;
4131 }
4132
4133 static void ept_set_mmio_spte_mask(void)
4134 {
4135         /*
4136          * EPT Misconfigurations can be generated if the value of bits 2:0
4137          * of an EPT paging-structure entry is 110b (write/execute).
4138          */
4139         kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
4140                                    VMX_EPT_MISCONFIG_WX_VALUE, 0);
4141 }
4142
4143 #define VMX_XSS_EXIT_BITMAP 0
4144
4145 /*
4146  * Noting that the initialization of Guest-state Area of VMCS is in
4147  * vmx_vcpu_reset().
4148  */
4149 static void init_vmcs(struct vcpu_vmx *vmx)
4150 {
4151         if (nested)
4152                 nested_vmx_set_vmcs_shadowing_bitmap();
4153
4154         if (cpu_has_vmx_msr_bitmap())
4155                 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
4156
4157         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4158
4159         /* Control */
4160         pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4161
4162         exec_controls_set(vmx, vmx_exec_control(vmx));
4163
4164         if (cpu_has_secondary_exec_ctrls()) {
4165                 vmx_compute_secondary_exec_control(vmx);
4166                 secondary_exec_controls_set(vmx, vmx->secondary_exec_control);
4167         }
4168
4169         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4170                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4171                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4172                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4173                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4174
4175                 vmcs_write16(GUEST_INTR_STATUS, 0);
4176
4177                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4178                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4179         }
4180
4181         if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4182                 vmcs_write32(PLE_GAP, ple_gap);
4183                 vmx->ple_window = ple_window;
4184                 vmx->ple_window_dirty = true;
4185         }
4186
4187         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4188         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4189         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4190
4191         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4192         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4193         vmx_set_constant_host_state(vmx);
4194         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4195         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4196
4197         if (cpu_has_vmx_vmfunc())
4198                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4199
4200         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4201         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4202         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
4203         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4204         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
4205
4206         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4207                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4208
4209         vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
4210
4211         /* 22.2.1, 20.8.1 */
4212         vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
4213
4214         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
4215         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
4216
4217         set_cr4_guest_host_mask(vmx);
4218
4219         if (vmx->vpid != 0)
4220                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4221
4222         if (vmx_xsaves_supported())
4223                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4224
4225         if (enable_pml) {
4226                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4227                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4228         }
4229
4230         if (cpu_has_vmx_encls_vmexit())
4231                 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
4232
4233         if (vmx_pt_mode_is_host_guest()) {
4234                 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4235                 /* Bit[6~0] are forced to 1, writes are ignored. */
4236                 vmx->pt_desc.guest.output_mask = 0x7F;
4237                 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4238         }
4239 }
4240
4241 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4242 {
4243         struct vcpu_vmx *vmx = to_vmx(vcpu);
4244         struct msr_data apic_base_msr;
4245         u64 cr0;
4246
4247         vmx->rmode.vm86_active = 0;
4248         vmx->spec_ctrl = 0;
4249
4250         vmx->msr_ia32_umwait_control = 0;
4251
4252         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4253         vmx->hv_deadline_tsc = -1;
4254         kvm_set_cr8(vcpu, 0);
4255
4256         if (!init_event) {
4257                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4258                                      MSR_IA32_APICBASE_ENABLE;
4259                 if (kvm_vcpu_is_reset_bsp(vcpu))
4260                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4261                 apic_base_msr.host_initiated = true;
4262                 kvm_set_apic_base(vcpu, &apic_base_msr);
4263         }
4264
4265         vmx_segment_cache_clear(vmx);
4266
4267         seg_setup(VCPU_SREG_CS);
4268         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4269         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4270
4271         seg_setup(VCPU_SREG_DS);
4272         seg_setup(VCPU_SREG_ES);
4273         seg_setup(VCPU_SREG_FS);
4274         seg_setup(VCPU_SREG_GS);
4275         seg_setup(VCPU_SREG_SS);
4276
4277         vmcs_write16(GUEST_TR_SELECTOR, 0);
4278         vmcs_writel(GUEST_TR_BASE, 0);
4279         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4280         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4281
4282         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4283         vmcs_writel(GUEST_LDTR_BASE, 0);
4284         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4285         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4286
4287         if (!init_event) {
4288                 vmcs_write32(GUEST_SYSENTER_CS, 0);
4289                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4290                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4291                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4292         }
4293
4294         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
4295         kvm_rip_write(vcpu, 0xfff0);
4296
4297         vmcs_writel(GUEST_GDTR_BASE, 0);
4298         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4299
4300         vmcs_writel(GUEST_IDTR_BASE, 0);
4301         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4302
4303         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4304         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4305         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4306         if (kvm_mpx_supported())
4307                 vmcs_write64(GUEST_BNDCFGS, 0);
4308
4309         setup_msrs(vmx);
4310
4311         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4312
4313         if (cpu_has_vmx_tpr_shadow() && !init_event) {
4314                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4315                 if (cpu_need_tpr_shadow(vcpu))
4316                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4317                                      __pa(vcpu->arch.apic->regs));
4318                 vmcs_write32(TPR_THRESHOLD, 0);
4319         }
4320
4321         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4322
4323         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4324         vmx->vcpu.arch.cr0 = cr0;
4325         vmx_set_cr0(vcpu, cr0); /* enter rmode */
4326         vmx_set_cr4(vcpu, 0);
4327         vmx_set_efer(vcpu, 0);
4328
4329         update_exception_bitmap(vcpu);
4330
4331         vpid_sync_context(vmx->vpid);
4332         if (init_event)
4333                 vmx_clear_hlt(vcpu);
4334 }
4335
4336 static void enable_irq_window(struct kvm_vcpu *vcpu)
4337 {
4338         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
4339 }
4340
4341 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4342 {
4343         if (!enable_vnmi ||
4344             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4345                 enable_irq_window(vcpu);
4346                 return;
4347         }
4348
4349         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
4350 }
4351
4352 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4353 {
4354         struct vcpu_vmx *vmx = to_vmx(vcpu);
4355         uint32_t intr;
4356         int irq = vcpu->arch.interrupt.nr;
4357
4358         trace_kvm_inj_virq(irq);
4359
4360         ++vcpu->stat.irq_injections;
4361         if (vmx->rmode.vm86_active) {
4362                 int inc_eip = 0;
4363                 if (vcpu->arch.interrupt.soft)
4364                         inc_eip = vcpu->arch.event_exit_inst_len;
4365                 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
4366                 return;
4367         }
4368         intr = irq | INTR_INFO_VALID_MASK;
4369         if (vcpu->arch.interrupt.soft) {
4370                 intr |= INTR_TYPE_SOFT_INTR;
4371                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4372                              vmx->vcpu.arch.event_exit_inst_len);
4373         } else
4374                 intr |= INTR_TYPE_EXT_INTR;
4375         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4376
4377         vmx_clear_hlt(vcpu);
4378 }
4379
4380 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4381 {
4382         struct vcpu_vmx *vmx = to_vmx(vcpu);
4383
4384         if (!enable_vnmi) {
4385                 /*
4386                  * Tracking the NMI-blocked state in software is built upon
4387                  * finding the next open IRQ window. This, in turn, depends on
4388                  * well-behaving guests: They have to keep IRQs disabled at
4389                  * least as long as the NMI handler runs. Otherwise we may
4390                  * cause NMI nesting, maybe breaking the guest. But as this is
4391                  * highly unlikely, we can live with the residual risk.
4392                  */
4393                 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4394                 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4395         }
4396
4397         ++vcpu->stat.nmi_injections;
4398         vmx->loaded_vmcs->nmi_known_unmasked = false;
4399
4400         if (vmx->rmode.vm86_active) {
4401                 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
4402                 return;
4403         }
4404
4405         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4406                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4407
4408         vmx_clear_hlt(vcpu);
4409 }
4410
4411 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4412 {
4413         struct vcpu_vmx *vmx = to_vmx(vcpu);
4414         bool masked;
4415
4416         if (!enable_vnmi)
4417                 return vmx->loaded_vmcs->soft_vnmi_blocked;
4418         if (vmx->loaded_vmcs->nmi_known_unmasked)
4419                 return false;
4420         masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4421         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4422         return masked;
4423 }
4424
4425 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4426 {
4427         struct vcpu_vmx *vmx = to_vmx(vcpu);
4428
4429         if (!enable_vnmi) {
4430                 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4431                         vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4432                         vmx->loaded_vmcs->vnmi_blocked_time = 0;
4433                 }
4434         } else {
4435                 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4436                 if (masked)
4437                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4438                                       GUEST_INTR_STATE_NMI);
4439                 else
4440                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4441                                         GUEST_INTR_STATE_NMI);
4442         }
4443 }
4444
4445 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4446 {
4447         if (to_vmx(vcpu)->nested.nested_run_pending)
4448                 return 0;
4449
4450         if (!enable_vnmi &&
4451             to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4452                 return 0;
4453
4454         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4455                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4456                    | GUEST_INTR_STATE_NMI));
4457 }
4458
4459 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4460 {
4461         if (to_vmx(vcpu)->nested.nested_run_pending)
4462                 return false;
4463
4464         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4465                 return true;
4466
4467         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4468                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4469                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4470 }
4471
4472 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4473 {
4474         int ret;
4475
4476         if (enable_unrestricted_guest)
4477                 return 0;
4478
4479         mutex_lock(&kvm->slots_lock);
4480         ret = __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4481                                       PAGE_SIZE * 3);
4482         mutex_unlock(&kvm->slots_lock);
4483
4484         if (ret)
4485                 return ret;
4486         to_kvm_vmx(kvm)->tss_addr = addr;
4487         return init_rmode_tss(kvm);
4488 }
4489
4490 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4491 {
4492         to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
4493         return 0;
4494 }
4495
4496 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4497 {
4498         switch (vec) {
4499         case BP_VECTOR:
4500                 /*
4501                  * Update instruction length as we may reinject the exception
4502                  * from user space while in guest debugging mode.
4503                  */
4504                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4505                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4506                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4507                         return false;
4508                 /* fall through */
4509         case DB_VECTOR:
4510                 if (vcpu->guest_debug &
4511                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4512                         return false;
4513                 /* fall through */
4514         case DE_VECTOR:
4515         case OF_VECTOR:
4516         case BR_VECTOR:
4517         case UD_VECTOR:
4518         case DF_VECTOR:
4519         case SS_VECTOR:
4520         case GP_VECTOR:
4521         case MF_VECTOR:
4522                 return true;
4523         }
4524         return false;
4525 }
4526
4527 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4528                                   int vec, u32 err_code)
4529 {
4530         /*
4531          * Instruction with address size override prefix opcode 0x67
4532          * Cause the #SS fault with 0 error code in VM86 mode.
4533          */
4534         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4535                 if (kvm_emulate_instruction(vcpu, 0)) {
4536                         if (vcpu->arch.halt_request) {
4537                                 vcpu->arch.halt_request = 0;
4538                                 return kvm_vcpu_halt(vcpu);
4539                         }
4540                         return 1;
4541                 }
4542                 return 0;
4543         }
4544
4545         /*
4546          * Forward all other exceptions that are valid in real mode.
4547          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4548          *        the required debugging infrastructure rework.
4549          */
4550         kvm_queue_exception(vcpu, vec);
4551         return 1;
4552 }
4553
4554 /*
4555  * Trigger machine check on the host. We assume all the MSRs are already set up
4556  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4557  * We pass a fake environment to the machine check handler because we want
4558  * the guest to be always treated like user space, no matter what context
4559  * it used internally.
4560  */
4561 static void kvm_machine_check(void)
4562 {
4563 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4564         struct pt_regs regs = {
4565                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4566                 .flags = X86_EFLAGS_IF,
4567         };
4568
4569         do_machine_check(&regs, 0);
4570 #endif
4571 }
4572
4573 static int handle_machine_check(struct kvm_vcpu *vcpu)
4574 {
4575         /* handled by vmx_vcpu_run() */
4576         return 1;
4577 }
4578
4579 static int handle_exception_nmi(struct kvm_vcpu *vcpu)
4580 {
4581         struct vcpu_vmx *vmx = to_vmx(vcpu);
4582         struct kvm_run *kvm_run = vcpu->run;
4583         u32 intr_info, ex_no, error_code;
4584         unsigned long cr2, rip, dr6;
4585         u32 vect_info;
4586
4587         vect_info = vmx->idt_vectoring_info;
4588         intr_info = vmx->exit_intr_info;
4589
4590         if (is_machine_check(intr_info) || is_nmi(intr_info))
4591                 return 1; /* handled by handle_exception_nmi_irqoff() */
4592
4593         if (is_invalid_opcode(intr_info))
4594                 return handle_ud(vcpu);
4595
4596         error_code = 0;
4597         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4598                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4599
4600         if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4601                 WARN_ON_ONCE(!enable_vmware_backdoor);
4602
4603                 /*
4604                  * VMware backdoor emulation on #GP interception only handles
4605                  * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
4606                  * error code on #GP.
4607                  */
4608                 if (error_code) {
4609                         kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4610                         return 1;
4611                 }
4612                 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
4613         }
4614
4615         /*
4616          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4617          * MMIO, it is better to report an internal error.
4618          * See the comments in vmx_handle_exit.
4619          */
4620         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4621             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4622                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4623                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4624                 vcpu->run->internal.ndata = 3;
4625                 vcpu->run->internal.data[0] = vect_info;
4626                 vcpu->run->internal.data[1] = intr_info;
4627                 vcpu->run->internal.data[2] = error_code;
4628                 return 0;
4629         }
4630
4631         if (is_page_fault(intr_info)) {
4632                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4633                 /* EPT won't cause page fault directly */
4634                 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
4635                 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
4636         }
4637
4638         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4639
4640         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4641                 return handle_rmode_exception(vcpu, ex_no, error_code);
4642
4643         switch (ex_no) {
4644         case AC_VECTOR:
4645                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4646                 return 1;
4647         case DB_VECTOR:
4648                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4649                 if (!(vcpu->guest_debug &
4650                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4651                         vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4652                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
4653                         if (is_icebp(intr_info))
4654                                 WARN_ON(!skip_emulated_instruction(vcpu));
4655
4656                         kvm_queue_exception(vcpu, DB_VECTOR);
4657                         return 1;
4658                 }
4659                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4660                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4661                 /* fall through */
4662         case BP_VECTOR:
4663                 /*
4664                  * Update instruction length as we may reinject #BP from
4665                  * user space while in guest debugging mode. Reading it for
4666                  * #DB as well causes no harm, it is not used in that case.
4667                  */
4668                 vmx->vcpu.arch.event_exit_inst_len =
4669                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4670                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4671                 rip = kvm_rip_read(vcpu);
4672                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4673                 kvm_run->debug.arch.exception = ex_no;
4674                 break;
4675         default:
4676                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4677                 kvm_run->ex.exception = ex_no;
4678                 kvm_run->ex.error_code = error_code;
4679                 break;
4680         }
4681         return 0;
4682 }
4683
4684 static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu)
4685 {
4686         ++vcpu->stat.irq_exits;
4687         return 1;
4688 }
4689
4690 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4691 {
4692         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4693         vcpu->mmio_needed = 0;
4694         return 0;
4695 }
4696
4697 static int handle_io(struct kvm_vcpu *vcpu)
4698 {
4699         unsigned long exit_qualification;
4700         int size, in, string;
4701         unsigned port;
4702
4703         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4704         string = (exit_qualification & 16) != 0;
4705
4706         ++vcpu->stat.io_exits;
4707
4708         if (string)
4709                 return kvm_emulate_instruction(vcpu, 0);
4710
4711         port = exit_qualification >> 16;
4712         size = (exit_qualification & 7) + 1;
4713         in = (exit_qualification & 8) != 0;
4714
4715         return kvm_fast_pio(vcpu, size, port, in);
4716 }
4717
4718 static void
4719 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4720 {
4721         /*
4722          * Patch in the VMCALL instruction:
4723          */
4724         hypercall[0] = 0x0f;
4725         hypercall[1] = 0x01;
4726         hypercall[2] = 0xc1;
4727 }
4728
4729 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4730 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4731 {
4732         if (is_guest_mode(vcpu)) {
4733                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4734                 unsigned long orig_val = val;
4735
4736                 /*
4737                  * We get here when L2 changed cr0 in a way that did not change
4738                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4739                  * but did change L0 shadowed bits. So we first calculate the
4740                  * effective cr0 value that L1 would like to write into the
4741                  * hardware. It consists of the L2-owned bits from the new
4742                  * value combined with the L1-owned bits from L1's guest_cr0.
4743                  */
4744                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4745                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4746
4747                 if (!nested_guest_cr0_valid(vcpu, val))
4748                         return 1;
4749
4750                 if (kvm_set_cr0(vcpu, val))
4751                         return 1;
4752                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4753                 return 0;
4754         } else {
4755                 if (to_vmx(vcpu)->nested.vmxon &&
4756                     !nested_host_cr0_valid(vcpu, val))
4757                         return 1;
4758
4759                 return kvm_set_cr0(vcpu, val);
4760         }
4761 }
4762
4763 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4764 {
4765         if (is_guest_mode(vcpu)) {
4766                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4767                 unsigned long orig_val = val;
4768
4769                 /* analogously to handle_set_cr0 */
4770                 val = (val & ~vmcs12->cr4_guest_host_mask) |
4771                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4772                 if (kvm_set_cr4(vcpu, val))
4773                         return 1;
4774                 vmcs_writel(CR4_READ_SHADOW, orig_val);
4775                 return 0;
4776         } else
4777                 return kvm_set_cr4(vcpu, val);
4778 }
4779
4780 static int handle_desc(struct kvm_vcpu *vcpu)
4781 {
4782         WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
4783         return kvm_emulate_instruction(vcpu, 0);
4784 }
4785
4786 static int handle_cr(struct kvm_vcpu *vcpu)
4787 {
4788         unsigned long exit_qualification, val;
4789         int cr;
4790         int reg;
4791         int err;
4792         int ret;
4793
4794         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4795         cr = exit_qualification & 15;
4796         reg = (exit_qualification >> 8) & 15;
4797         switch ((exit_qualification >> 4) & 3) {
4798         case 0: /* mov to cr */
4799                 val = kvm_register_readl(vcpu, reg);
4800                 trace_kvm_cr_write(cr, val);
4801                 switch (cr) {
4802                 case 0:
4803                         err = handle_set_cr0(vcpu, val);
4804                         return kvm_complete_insn_gp(vcpu, err);
4805                 case 3:
4806                         WARN_ON_ONCE(enable_unrestricted_guest);
4807                         err = kvm_set_cr3(vcpu, val);
4808                         return kvm_complete_insn_gp(vcpu, err);
4809                 case 4:
4810                         err = handle_set_cr4(vcpu, val);
4811                         return kvm_complete_insn_gp(vcpu, err);
4812                 case 8: {
4813                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4814                                 u8 cr8 = (u8)val;
4815                                 err = kvm_set_cr8(vcpu, cr8);
4816                                 ret = kvm_complete_insn_gp(vcpu, err);
4817                                 if (lapic_in_kernel(vcpu))
4818                                         return ret;
4819                                 if (cr8_prev <= cr8)
4820                                         return ret;
4821                                 /*
4822                                  * TODO: we might be squashing a
4823                                  * KVM_GUESTDBG_SINGLESTEP-triggered
4824                                  * KVM_EXIT_DEBUG here.
4825                                  */
4826                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4827                                 return 0;
4828                         }
4829                 }
4830                 break;
4831         case 2: /* clts */
4832                 WARN_ONCE(1, "Guest should always own CR0.TS");
4833                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4834                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4835                 return kvm_skip_emulated_instruction(vcpu);
4836         case 1: /*mov from cr*/
4837                 switch (cr) {
4838                 case 3:
4839                         WARN_ON_ONCE(enable_unrestricted_guest);
4840                         val = kvm_read_cr3(vcpu);
4841                         kvm_register_write(vcpu, reg, val);
4842                         trace_kvm_cr_read(cr, val);
4843                         return kvm_skip_emulated_instruction(vcpu);
4844                 case 8:
4845                         val = kvm_get_cr8(vcpu);
4846                         kvm_register_write(vcpu, reg, val);
4847                         trace_kvm_cr_read(cr, val);
4848                         return kvm_skip_emulated_instruction(vcpu);
4849                 }
4850                 break;
4851         case 3: /* lmsw */
4852                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4853                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4854                 kvm_lmsw(vcpu, val);
4855
4856                 return kvm_skip_emulated_instruction(vcpu);
4857         default:
4858                 break;
4859         }
4860         vcpu->run->exit_reason = 0;
4861         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4862                (int)(exit_qualification >> 4) & 3, cr);
4863         return 0;
4864 }
4865
4866 static int handle_dr(struct kvm_vcpu *vcpu)
4867 {
4868         unsigned long exit_qualification;
4869         int dr, dr7, reg;
4870
4871         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4872         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4873
4874         /* First, if DR does not exist, trigger UD */
4875         if (!kvm_require_dr(vcpu, dr))
4876                 return 1;
4877
4878         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4879         if (!kvm_require_cpl(vcpu, 0))
4880                 return 1;
4881         dr7 = vmcs_readl(GUEST_DR7);
4882         if (dr7 & DR7_GD) {
4883                 /*
4884                  * As the vm-exit takes precedence over the debug trap, we
4885                  * need to emulate the latter, either for the host or the
4886                  * guest debugging itself.
4887                  */
4888                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4889                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4890                         vcpu->run->debug.arch.dr7 = dr7;
4891                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
4892                         vcpu->run->debug.arch.exception = DB_VECTOR;
4893                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4894                         return 0;
4895                 } else {
4896                         vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4897                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
4898                         kvm_queue_exception(vcpu, DB_VECTOR);
4899                         return 1;
4900                 }
4901         }
4902
4903         if (vcpu->guest_debug == 0) {
4904                 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
4905
4906                 /*
4907                  * No more DR vmexits; force a reload of the debug registers
4908                  * and reenter on this instruction.  The next vmexit will
4909                  * retrieve the full state of the debug registers.
4910                  */
4911                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4912                 return 1;
4913         }
4914
4915         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4916         if (exit_qualification & TYPE_MOV_FROM_DR) {
4917                 unsigned long val;
4918
4919                 if (kvm_get_dr(vcpu, dr, &val))
4920                         return 1;
4921                 kvm_register_write(vcpu, reg, val);
4922         } else
4923                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4924                         return 1;
4925
4926         return kvm_skip_emulated_instruction(vcpu);
4927 }
4928
4929 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
4930 {
4931         return vcpu->arch.dr6;
4932 }
4933
4934 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
4935 {
4936 }
4937
4938 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
4939 {
4940         get_debugreg(vcpu->arch.db[0], 0);
4941         get_debugreg(vcpu->arch.db[1], 1);
4942         get_debugreg(vcpu->arch.db[2], 2);
4943         get_debugreg(vcpu->arch.db[3], 3);
4944         get_debugreg(vcpu->arch.dr6, 6);
4945         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
4946
4947         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
4948         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
4949 }
4950
4951 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4952 {
4953         vmcs_writel(GUEST_DR7, val);
4954 }
4955
4956 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4957 {
4958         kvm_apic_update_ppr(vcpu);
4959         return 1;
4960 }
4961
4962 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4963 {
4964         exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
4965
4966         kvm_make_request(KVM_REQ_EVENT, vcpu);
4967
4968         ++vcpu->stat.irq_window_exits;
4969         return 1;
4970 }
4971
4972 static int handle_vmcall(struct kvm_vcpu *vcpu)
4973 {
4974         return kvm_emulate_hypercall(vcpu);
4975 }
4976
4977 static int handle_invd(struct kvm_vcpu *vcpu)
4978 {
4979         return kvm_emulate_instruction(vcpu, 0);
4980 }
4981
4982 static int handle_invlpg(struct kvm_vcpu *vcpu)
4983 {
4984         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4985
4986         kvm_mmu_invlpg(vcpu, exit_qualification);
4987         return kvm_skip_emulated_instruction(vcpu);
4988 }
4989
4990 static int handle_rdpmc(struct kvm_vcpu *vcpu)
4991 {
4992         int err;
4993
4994         err = kvm_rdpmc(vcpu);
4995         return kvm_complete_insn_gp(vcpu, err);
4996 }
4997
4998 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4999 {
5000         return kvm_emulate_wbinvd(vcpu);
5001 }
5002
5003 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5004 {
5005         u64 new_bv = kvm_read_edx_eax(vcpu);
5006         u32 index = kvm_rcx_read(vcpu);
5007
5008         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5009                 return kvm_skip_emulated_instruction(vcpu);
5010         return 1;
5011 }
5012
5013 static int handle_apic_access(struct kvm_vcpu *vcpu)
5014 {
5015         if (likely(fasteoi)) {
5016                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5017                 int access_type, offset;
5018
5019                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5020                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5021                 /*
5022                  * Sane guest uses MOV to write EOI, with written value
5023                  * not cared. So make a short-circuit here by avoiding
5024                  * heavy instruction emulation.
5025                  */
5026                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5027                     (offset == APIC_EOI)) {
5028                         kvm_lapic_set_eoi(vcpu);
5029                         return kvm_skip_emulated_instruction(vcpu);
5030                 }
5031         }
5032         return kvm_emulate_instruction(vcpu, 0);
5033 }
5034
5035 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5036 {
5037         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5038         int vector = exit_qualification & 0xff;
5039
5040         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5041         kvm_apic_set_eoi_accelerated(vcpu, vector);
5042         return 1;
5043 }
5044
5045 static int handle_apic_write(struct kvm_vcpu *vcpu)
5046 {
5047         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5048         u32 offset = exit_qualification & 0xfff;
5049
5050         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5051         kvm_apic_write_nodecode(vcpu, offset);
5052         return 1;
5053 }
5054
5055 static int handle_task_switch(struct kvm_vcpu *vcpu)
5056 {
5057         struct vcpu_vmx *vmx = to_vmx(vcpu);
5058         unsigned long exit_qualification;
5059         bool has_error_code = false;
5060         u32 error_code = 0;
5061         u16 tss_selector;
5062         int reason, type, idt_v, idt_index;
5063
5064         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5065         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5066         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5067
5068         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5069
5070         reason = (u32)exit_qualification >> 30;
5071         if (reason == TASK_SWITCH_GATE && idt_v) {
5072                 switch (type) {
5073                 case INTR_TYPE_NMI_INTR:
5074                         vcpu->arch.nmi_injected = false;
5075                         vmx_set_nmi_mask(vcpu, true);
5076                         break;
5077                 case INTR_TYPE_EXT_INTR:
5078                 case INTR_TYPE_SOFT_INTR:
5079                         kvm_clear_interrupt_queue(vcpu);
5080                         break;
5081                 case INTR_TYPE_HARD_EXCEPTION:
5082                         if (vmx->idt_vectoring_info &
5083                             VECTORING_INFO_DELIVER_CODE_MASK) {
5084                                 has_error_code = true;
5085                                 error_code =
5086                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5087                         }
5088                         /* fall through */
5089                 case INTR_TYPE_SOFT_EXCEPTION:
5090                         kvm_clear_exception_queue(vcpu);
5091                         break;
5092                 default:
5093                         break;
5094                 }
5095         }
5096         tss_selector = exit_qualification;
5097
5098         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5099                        type != INTR_TYPE_EXT_INTR &&
5100                        type != INTR_TYPE_NMI_INTR))
5101                 WARN_ON(!skip_emulated_instruction(vcpu));
5102
5103         /*
5104          * TODO: What about debug traps on tss switch?
5105          *       Are we supposed to inject them and update dr6?
5106          */
5107         return kvm_task_switch(vcpu, tss_selector,
5108                                type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
5109                                reason, has_error_code, error_code);
5110 }
5111
5112 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5113 {
5114         unsigned long exit_qualification;
5115         gpa_t gpa;
5116         u64 error_code;
5117
5118         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5119
5120         /*
5121          * EPT violation happened while executing iret from NMI,
5122          * "blocked by NMI" bit has to be set before next VM entry.
5123          * There are errata that may cause this bit to not be set:
5124          * AAK134, BY25.
5125          */
5126         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5127                         enable_vnmi &&
5128                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5129                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5130
5131         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5132         trace_kvm_page_fault(gpa, exit_qualification);
5133
5134         /* Is it a read fault? */
5135         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
5136                      ? PFERR_USER_MASK : 0;
5137         /* Is it a write fault? */
5138         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
5139                       ? PFERR_WRITE_MASK : 0;
5140         /* Is it a fetch fault? */
5141         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
5142                       ? PFERR_FETCH_MASK : 0;
5143         /* ept page table entry is present? */
5144         error_code |= (exit_qualification &
5145                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5146                         EPT_VIOLATION_EXECUTABLE))
5147                       ? PFERR_PRESENT_MASK : 0;
5148
5149         error_code |= (exit_qualification & 0x100) != 0 ?
5150                PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
5151
5152         vcpu->arch.exit_qualification = exit_qualification;
5153         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5154 }
5155
5156 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5157 {
5158         gpa_t gpa;
5159
5160         /*
5161          * A nested guest cannot optimize MMIO vmexits, because we have an
5162          * nGPA here instead of the required GPA.
5163          */
5164         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5165         if (!is_guest_mode(vcpu) &&
5166             !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5167                 trace_kvm_fast_mmio(gpa);
5168                 return kvm_skip_emulated_instruction(vcpu);
5169         }
5170
5171         return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
5172 }
5173
5174 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5175 {
5176         WARN_ON_ONCE(!enable_vnmi);
5177         exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
5178         ++vcpu->stat.nmi_window_exits;
5179         kvm_make_request(KVM_REQ_EVENT, vcpu);
5180
5181         return 1;
5182 }
5183
5184 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5185 {
5186         struct vcpu_vmx *vmx = to_vmx(vcpu);
5187         bool intr_window_requested;
5188         unsigned count = 130;
5189
5190         /*
5191          * We should never reach the point where we are emulating L2
5192          * due to invalid guest state as that means we incorrectly
5193          * allowed a nested VMEntry with an invalid vmcs12.
5194          */
5195         WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
5196
5197         intr_window_requested = exec_controls_get(vmx) &
5198                                 CPU_BASED_INTR_WINDOW_EXITING;
5199
5200         while (vmx->emulation_required && count-- != 0) {
5201                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5202                         return handle_interrupt_window(&vmx->vcpu);
5203
5204                 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
5205                         return 1;
5206
5207                 if (!kvm_emulate_instruction(vcpu, 0))
5208                         return 0;
5209
5210                 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5211                     vcpu->arch.exception.pending) {
5212                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5213                         vcpu->run->internal.suberror =
5214                                                 KVM_INTERNAL_ERROR_EMULATION;
5215                         vcpu->run->internal.ndata = 0;
5216                         return 0;
5217                 }
5218
5219                 if (vcpu->arch.halt_request) {
5220                         vcpu->arch.halt_request = 0;
5221                         return kvm_vcpu_halt(vcpu);
5222                 }
5223
5224                 /*
5225                  * Note, return 1 and not 0, vcpu_run() is responsible for
5226                  * morphing the pending signal into the proper return code.
5227                  */
5228                 if (signal_pending(current))
5229                         return 1;
5230
5231                 if (need_resched())
5232                         schedule();
5233         }
5234
5235         return 1;
5236 }
5237
5238 static void grow_ple_window(struct kvm_vcpu *vcpu)
5239 {
5240         struct vcpu_vmx *vmx = to_vmx(vcpu);
5241         unsigned int old = vmx->ple_window;
5242
5243         vmx->ple_window = __grow_ple_window(old, ple_window,
5244                                             ple_window_grow,
5245                                             ple_window_max);
5246
5247         if (vmx->ple_window != old) {
5248                 vmx->ple_window_dirty = true;
5249                 trace_kvm_ple_window_update(vcpu->vcpu_id,
5250                                             vmx->ple_window, old);
5251         }
5252 }
5253
5254 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5255 {
5256         struct vcpu_vmx *vmx = to_vmx(vcpu);
5257         unsigned int old = vmx->ple_window;
5258
5259         vmx->ple_window = __shrink_ple_window(old, ple_window,
5260                                               ple_window_shrink,
5261                                               ple_window);
5262
5263         if (vmx->ple_window != old) {
5264                 vmx->ple_window_dirty = true;
5265                 trace_kvm_ple_window_update(vcpu->vcpu_id,
5266                                             vmx->ple_window, old);
5267         }
5268 }
5269
5270 /*
5271  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
5272  */
5273 static void wakeup_handler(void)
5274 {
5275         struct kvm_vcpu *vcpu;
5276         int cpu = smp_processor_id();
5277
5278         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5279         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
5280                         blocked_vcpu_list) {
5281                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
5282
5283                 if (pi_test_on(pi_desc) == 1)
5284                         kvm_vcpu_kick(vcpu);
5285         }
5286         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5287 }
5288
5289 static void vmx_enable_tdp(void)
5290 {
5291         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
5292                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
5293                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
5294                 0ull, VMX_EPT_EXECUTABLE_MASK,
5295                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
5296                 VMX_EPT_RWX_MASK, 0ull);
5297
5298         ept_set_mmio_spte_mask();
5299 }
5300
5301 /*
5302  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5303  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5304  */
5305 static int handle_pause(struct kvm_vcpu *vcpu)
5306 {
5307         if (!kvm_pause_in_guest(vcpu->kvm))
5308                 grow_ple_window(vcpu);
5309
5310         /*
5311          * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5312          * VM-execution control is ignored if CPL > 0. OTOH, KVM
5313          * never set PAUSE_EXITING and just set PLE if supported,
5314          * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5315          */
5316         kvm_vcpu_on_spin(vcpu, true);
5317         return kvm_skip_emulated_instruction(vcpu);
5318 }
5319
5320 static int handle_nop(struct kvm_vcpu *vcpu)
5321 {
5322         return kvm_skip_emulated_instruction(vcpu);
5323 }
5324
5325 static int handle_mwait(struct kvm_vcpu *vcpu)
5326 {
5327         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5328         return handle_nop(vcpu);
5329 }
5330
5331 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5332 {
5333         kvm_queue_exception(vcpu, UD_VECTOR);
5334         return 1;
5335 }
5336
5337 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5338 {
5339         return 1;
5340 }
5341
5342 static int handle_monitor(struct kvm_vcpu *vcpu)
5343 {
5344         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5345         return handle_nop(vcpu);
5346 }
5347
5348 static int handle_invpcid(struct kvm_vcpu *vcpu)
5349 {
5350         u32 vmx_instruction_info;
5351         unsigned long type;
5352         bool pcid_enabled;
5353         gva_t gva;
5354         struct x86_exception e;
5355         unsigned i;
5356         unsigned long roots_to_free = 0;
5357         struct {
5358                 u64 pcid;
5359                 u64 gla;
5360         } operand;
5361
5362         if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
5363                 kvm_queue_exception(vcpu, UD_VECTOR);
5364                 return 1;
5365         }
5366
5367         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5368         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5369
5370         if (type > 3) {
5371                 kvm_inject_gp(vcpu, 0);
5372                 return 1;
5373         }
5374
5375         /* According to the Intel instruction reference, the memory operand
5376          * is read even if it isn't needed (e.g., for type==all)
5377          */
5378         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5379                                 vmx_instruction_info, false,
5380                                 sizeof(operand), &gva))
5381                 return 1;
5382
5383         if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
5384                 kvm_inject_page_fault(vcpu, &e);
5385                 return 1;
5386         }
5387
5388         if (operand.pcid >> 12 != 0) {
5389                 kvm_inject_gp(vcpu, 0);
5390                 return 1;
5391         }
5392
5393         pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
5394
5395         switch (type) {
5396         case INVPCID_TYPE_INDIV_ADDR:
5397                 if ((!pcid_enabled && (operand.pcid != 0)) ||
5398                     is_noncanonical_address(operand.gla, vcpu)) {
5399                         kvm_inject_gp(vcpu, 0);
5400                         return 1;
5401                 }
5402                 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
5403                 return kvm_skip_emulated_instruction(vcpu);
5404
5405         case INVPCID_TYPE_SINGLE_CTXT:
5406                 if (!pcid_enabled && (operand.pcid != 0)) {
5407                         kvm_inject_gp(vcpu, 0);
5408                         return 1;
5409                 }
5410
5411                 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
5412                         kvm_mmu_sync_roots(vcpu);
5413                         kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
5414                 }
5415
5416                 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5417                         if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3)
5418                             == operand.pcid)
5419                                 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
5420
5421                 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
5422                 /*
5423                  * If neither the current cr3 nor any of the prev_roots use the
5424                  * given PCID, then nothing needs to be done here because a
5425                  * resync will happen anyway before switching to any other CR3.
5426                  */
5427
5428                 return kvm_skip_emulated_instruction(vcpu);
5429
5430         case INVPCID_TYPE_ALL_NON_GLOBAL:
5431                 /*
5432                  * Currently, KVM doesn't mark global entries in the shadow
5433                  * page tables, so a non-global flush just degenerates to a
5434                  * global flush. If needed, we could optimize this later by
5435                  * keeping track of global entries in shadow page tables.
5436                  */
5437
5438                 /* fall-through */
5439         case INVPCID_TYPE_ALL_INCL_GLOBAL:
5440                 kvm_mmu_unload(vcpu);
5441                 return kvm_skip_emulated_instruction(vcpu);
5442
5443         default:
5444                 BUG(); /* We have already checked above that type <= 3 */
5445         }
5446 }
5447
5448 static int handle_pml_full(struct kvm_vcpu *vcpu)
5449 {
5450         unsigned long exit_qualification;
5451
5452         trace_kvm_pml_full(vcpu->vcpu_id);
5453
5454         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5455
5456         /*
5457          * PML buffer FULL happened while executing iret from NMI,
5458          * "blocked by NMI" bit has to be set before next VM entry.
5459          */
5460         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5461                         enable_vnmi &&
5462                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5463                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5464                                 GUEST_INTR_STATE_NMI);
5465
5466         /*
5467          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5468          * here.., and there's no userspace involvement needed for PML.
5469          */
5470         return 1;
5471 }
5472
5473 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
5474 {
5475         struct vcpu_vmx *vmx = to_vmx(vcpu);
5476
5477         if (!vmx->req_immediate_exit &&
5478             !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled))
5479                 kvm_lapic_expired_hv_timer(vcpu);
5480
5481         return 1;
5482 }
5483
5484 /*
5485  * When nested=0, all VMX instruction VM Exits filter here.  The handlers
5486  * are overwritten by nested_vmx_setup() when nested=1.
5487  */
5488 static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
5489 {
5490         kvm_queue_exception(vcpu, UD_VECTOR);
5491         return 1;
5492 }
5493
5494 static int handle_encls(struct kvm_vcpu *vcpu)
5495 {
5496         /*
5497          * SGX virtualization is not yet supported.  There is no software
5498          * enable bit for SGX, so we have to trap ENCLS and inject a #UD
5499          * to prevent the guest from executing ENCLS.
5500          */
5501         kvm_queue_exception(vcpu, UD_VECTOR);
5502         return 1;
5503 }
5504
5505 /*
5506  * The exit handlers return 1 if the exit was handled fully and guest execution
5507  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5508  * to be done to userspace and return 0.
5509  */
5510 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5511         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception_nmi,
5512         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5513         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5514         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5515         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5516         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5517         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5518         [EXIT_REASON_CPUID]                   = kvm_emulate_cpuid,
5519         [EXIT_REASON_MSR_READ]                = kvm_emulate_rdmsr,
5520         [EXIT_REASON_MSR_WRITE]               = kvm_emulate_wrmsr,
5521         [EXIT_REASON_INTERRUPT_WINDOW]        = handle_interrupt_window,
5522         [EXIT_REASON_HLT]                     = kvm_emulate_halt,
5523         [EXIT_REASON_INVD]                    = handle_invd,
5524         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5525         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
5526         [EXIT_REASON_VMCALL]                  = handle_vmcall,
5527         [EXIT_REASON_VMCLEAR]                 = handle_vmx_instruction,
5528         [EXIT_REASON_VMLAUNCH]                = handle_vmx_instruction,
5529         [EXIT_REASON_VMPTRLD]                 = handle_vmx_instruction,
5530         [EXIT_REASON_VMPTRST]                 = handle_vmx_instruction,
5531         [EXIT_REASON_VMREAD]                  = handle_vmx_instruction,
5532         [EXIT_REASON_VMRESUME]                = handle_vmx_instruction,
5533         [EXIT_REASON_VMWRITE]                 = handle_vmx_instruction,
5534         [EXIT_REASON_VMOFF]                   = handle_vmx_instruction,
5535         [EXIT_REASON_VMON]                    = handle_vmx_instruction,
5536         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5537         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5538         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
5539         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
5540         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
5541         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
5542         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5543         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5544         [EXIT_REASON_GDTR_IDTR]               = handle_desc,
5545         [EXIT_REASON_LDTR_TR]                 = handle_desc,
5546         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5547         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5548         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5549         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
5550         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
5551         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
5552         [EXIT_REASON_INVEPT]                  = handle_vmx_instruction,
5553         [EXIT_REASON_INVVPID]                 = handle_vmx_instruction,
5554         [EXIT_REASON_RDRAND]                  = handle_invalid_op,
5555         [EXIT_REASON_RDSEED]                  = handle_invalid_op,
5556         [EXIT_REASON_PML_FULL]                = handle_pml_full,
5557         [EXIT_REASON_INVPCID]                 = handle_invpcid,
5558         [EXIT_REASON_VMFUNC]                  = handle_vmx_instruction,
5559         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
5560         [EXIT_REASON_ENCLS]                   = handle_encls,
5561 };
5562
5563 static const int kvm_vmx_max_exit_handlers =
5564         ARRAY_SIZE(kvm_vmx_exit_handlers);
5565
5566 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5567 {
5568         *info1 = vmcs_readl(EXIT_QUALIFICATION);
5569         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5570 }
5571
5572 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
5573 {
5574         if (vmx->pml_pg) {
5575                 __free_page(vmx->pml_pg);
5576                 vmx->pml_pg = NULL;
5577         }
5578 }
5579
5580 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
5581 {
5582         struct vcpu_vmx *vmx = to_vmx(vcpu);
5583         u64 *pml_buf;
5584         u16 pml_idx;
5585
5586         pml_idx = vmcs_read16(GUEST_PML_INDEX);
5587
5588         /* Do nothing if PML buffer is empty */
5589         if (pml_idx == (PML_ENTITY_NUM - 1))
5590                 return;
5591
5592         /* PML index always points to next available PML buffer entity */
5593         if (pml_idx >= PML_ENTITY_NUM)
5594                 pml_idx = 0;
5595         else
5596                 pml_idx++;
5597
5598         pml_buf = page_address(vmx->pml_pg);
5599         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5600                 u64 gpa;
5601
5602                 gpa = pml_buf[pml_idx];
5603                 WARN_ON(gpa & (PAGE_SIZE - 1));
5604                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5605         }
5606
5607         /* reset PML index */
5608         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5609 }
5610
5611 /*
5612  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
5613  * Called before reporting dirty_bitmap to userspace.
5614  */
5615 static void kvm_flush_pml_buffers(struct kvm *kvm)
5616 {
5617         int i;
5618         struct kvm_vcpu *vcpu;
5619         /*
5620          * We only need to kick vcpu out of guest mode here, as PML buffer
5621          * is flushed at beginning of all VMEXITs, and it's obvious that only
5622          * vcpus running in guest are possible to have unflushed GPAs in PML
5623          * buffer.
5624          */
5625         kvm_for_each_vcpu(i, vcpu, kvm)
5626                 kvm_vcpu_kick(vcpu);
5627 }
5628
5629 static void vmx_dump_sel(char *name, uint32_t sel)
5630 {
5631         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5632                name, vmcs_read16(sel),
5633                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5634                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5635                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
5636 }
5637
5638 static void vmx_dump_dtsel(char *name, uint32_t limit)
5639 {
5640         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
5641                name, vmcs_read32(limit),
5642                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
5643 }
5644
5645 void dump_vmcs(void)
5646 {
5647         u32 vmentry_ctl, vmexit_ctl;
5648         u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5649         unsigned long cr4;
5650         u64 efer;
5651         int i, n;
5652
5653         if (!dump_invalid_vmcs) {
5654                 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5655                 return;
5656         }
5657
5658         vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5659         vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5660         cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5661         pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5662         cr4 = vmcs_readl(GUEST_CR4);
5663         efer = vmcs_read64(GUEST_IA32_EFER);
5664         secondary_exec_control = 0;
5665         if (cpu_has_secondary_exec_ctrls())
5666                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5667
5668         pr_err("*** Guest State ***\n");
5669         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5670                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5671                vmcs_readl(CR0_GUEST_HOST_MASK));
5672         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5673                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5674         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5675         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
5676             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
5677         {
5678                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
5679                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5680                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
5681                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
5682         }
5683         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
5684                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5685         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
5686                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5687         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5688                vmcs_readl(GUEST_SYSENTER_ESP),
5689                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5690         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
5691         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
5692         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
5693         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
5694         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
5695         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
5696         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5697         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5698         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5699         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
5700         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
5701             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
5702                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
5703                        efer, vmcs_read64(GUEST_IA32_PAT));
5704         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
5705                vmcs_read64(GUEST_IA32_DEBUGCTL),
5706                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5707         if (cpu_has_load_perf_global_ctrl() &&
5708             vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5709                 pr_err("PerfGlobCtl = 0x%016llx\n",
5710                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5711         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5712                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5713         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
5714                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5715                vmcs_read32(GUEST_ACTIVITY_STATE));
5716         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5717                 pr_err("InterruptStatus = %04x\n",
5718                        vmcs_read16(GUEST_INTR_STATUS));
5719
5720         pr_err("*** Host State ***\n");
5721         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
5722                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5723         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5724                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5725                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5726                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5727                vmcs_read16(HOST_TR_SELECTOR));
5728         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5729                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5730                vmcs_readl(HOST_TR_BASE));
5731         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5732                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5733         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5734                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5735                vmcs_readl(HOST_CR4));
5736         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5737                vmcs_readl(HOST_IA32_SYSENTER_ESP),
5738                vmcs_read32(HOST_IA32_SYSENTER_CS),
5739                vmcs_readl(HOST_IA32_SYSENTER_EIP));
5740         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
5741                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
5742                        vmcs_read64(HOST_IA32_EFER),
5743                        vmcs_read64(HOST_IA32_PAT));
5744         if (cpu_has_load_perf_global_ctrl() &&
5745             vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5746                 pr_err("PerfGlobCtl = 0x%016llx\n",
5747                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
5748
5749         pr_err("*** Control State ***\n");
5750         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5751                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5752         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5753         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5754                vmcs_read32(EXCEPTION_BITMAP),
5755                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5756                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5757         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5758                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5759                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5760                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5761         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5762                vmcs_read32(VM_EXIT_INTR_INFO),
5763                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5764                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5765         pr_err("        reason=%08x qualification=%016lx\n",
5766                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5767         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5768                vmcs_read32(IDT_VECTORING_INFO_FIELD),
5769                vmcs_read32(IDT_VECTORING_ERROR_CODE));
5770         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5771         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5772                 pr_err("TSC Multiplier = 0x%016llx\n",
5773                        vmcs_read64(TSC_MULTIPLIER));
5774         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5775                 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5776                         u16 status = vmcs_read16(GUEST_INTR_STATUS);
5777                         pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5778                 }
5779                 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
5780                 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5781                         pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
5782                 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
5783         }
5784         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5785                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5786         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5787                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5788         n = vmcs_read32(CR3_TARGET_COUNT);
5789         for (i = 0; i + 1 < n; i += 4)
5790                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
5791                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
5792                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
5793         if (i < n)
5794                 pr_err("CR3 target%u=%016lx\n",
5795                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
5796         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5797                 pr_err("PLE Gap=%08x Window=%08x\n",
5798                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5799         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5800                 pr_err("Virtual processor ID = 0x%04x\n",
5801                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
5802 }
5803
5804 /*
5805  * The guest has exited.  See if we can fix it or if we need userspace
5806  * assistance.
5807  */
5808 static int vmx_handle_exit(struct kvm_vcpu *vcpu,
5809         enum exit_fastpath_completion exit_fastpath)
5810 {
5811         struct vcpu_vmx *vmx = to_vmx(vcpu);
5812         u32 exit_reason = vmx->exit_reason;
5813         u32 vectoring_info = vmx->idt_vectoring_info;
5814
5815         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
5816
5817         /*
5818          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5819          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5820          * querying dirty_bitmap, we only need to kick all vcpus out of guest
5821          * mode as if vcpus is in root mode, the PML buffer must has been
5822          * flushed already.
5823          */
5824         if (enable_pml)
5825                 vmx_flush_pml_buffer(vcpu);
5826
5827         /* If guest state is invalid, start emulating */
5828         if (vmx->emulation_required)
5829                 return handle_invalid_guest_state(vcpu);
5830
5831         if (is_guest_mode(vcpu)) {
5832                 /*
5833                  * The host physical addresses of some pages of guest memory
5834                  * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
5835                  * Page). The CPU may write to these pages via their host
5836                  * physical address while L2 is running, bypassing any
5837                  * address-translation-based dirty tracking (e.g. EPT write
5838                  * protection).
5839                  *
5840                  * Mark them dirty on every exit from L2 to prevent them from
5841                  * getting out of sync with dirty tracking.
5842                  */
5843                 nested_mark_vmcs12_pages_dirty(vcpu);
5844
5845                 if (nested_vmx_exit_reflected(vcpu, exit_reason))
5846                         return nested_vmx_reflect_vmexit(vcpu, exit_reason);
5847         }
5848
5849         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5850                 dump_vmcs();
5851                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5852                 vcpu->run->fail_entry.hardware_entry_failure_reason
5853                         = exit_reason;
5854                 return 0;
5855         }
5856
5857         if (unlikely(vmx->fail)) {
5858                 dump_vmcs();
5859                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5860                 vcpu->run->fail_entry.hardware_entry_failure_reason
5861                         = vmcs_read32(VM_INSTRUCTION_ERROR);
5862                 return 0;
5863         }
5864
5865         /*
5866          * Note:
5867          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5868          * delivery event since it indicates guest is accessing MMIO.
5869          * The vm-exit can be triggered again after return to guest that
5870          * will cause infinite loop.
5871          */
5872         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5873                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5874                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
5875                         exit_reason != EXIT_REASON_PML_FULL &&
5876                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
5877                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5878                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5879                 vcpu->run->internal.ndata = 3;
5880                 vcpu->run->internal.data[0] = vectoring_info;
5881                 vcpu->run->internal.data[1] = exit_reason;
5882                 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5883                 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
5884                         vcpu->run->internal.ndata++;
5885                         vcpu->run->internal.data[3] =
5886                                 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5887                 }
5888                 return 0;
5889         }
5890
5891         if (unlikely(!enable_vnmi &&
5892                      vmx->loaded_vmcs->soft_vnmi_blocked)) {
5893                 if (vmx_interrupt_allowed(vcpu)) {
5894                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5895                 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5896                            vcpu->arch.nmi_pending) {
5897                         /*
5898                          * This CPU don't support us in finding the end of an
5899                          * NMI-blocked window if the guest runs with IRQs
5900                          * disabled. So we pull the trigger after 1 s of
5901                          * futile waiting, but inform the user about this.
5902                          */
5903                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5904                                "state on VCPU %d after 1 s timeout\n",
5905                                __func__, vcpu->vcpu_id);
5906                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5907                 }
5908         }
5909
5910         if (exit_fastpath == EXIT_FASTPATH_SKIP_EMUL_INS) {
5911                 kvm_skip_emulated_instruction(vcpu);
5912                 return 1;
5913         }
5914
5915         if (exit_reason >= kvm_vmx_max_exit_handlers)
5916                 goto unexpected_vmexit;
5917 #ifdef CONFIG_RETPOLINE
5918         if (exit_reason == EXIT_REASON_MSR_WRITE)
5919                 return kvm_emulate_wrmsr(vcpu);
5920         else if (exit_reason == EXIT_REASON_PREEMPTION_TIMER)
5921                 return handle_preemption_timer(vcpu);
5922         else if (exit_reason == EXIT_REASON_INTERRUPT_WINDOW)
5923                 return handle_interrupt_window(vcpu);
5924         else if (exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
5925                 return handle_external_interrupt(vcpu);
5926         else if (exit_reason == EXIT_REASON_HLT)
5927                 return kvm_emulate_halt(vcpu);
5928         else if (exit_reason == EXIT_REASON_EPT_MISCONFIG)
5929                 return handle_ept_misconfig(vcpu);
5930 #endif
5931
5932         exit_reason = array_index_nospec(exit_reason,
5933                                          kvm_vmx_max_exit_handlers);
5934         if (!kvm_vmx_exit_handlers[exit_reason])
5935                 goto unexpected_vmexit;
5936
5937         return kvm_vmx_exit_handlers[exit_reason](vcpu);
5938
5939 unexpected_vmexit:
5940         vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n", exit_reason);
5941         dump_vmcs();
5942         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5943         vcpu->run->internal.suberror =
5944                         KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
5945         vcpu->run->internal.ndata = 1;
5946         vcpu->run->internal.data[0] = exit_reason;
5947         return 0;
5948 }
5949
5950 /*
5951  * Software based L1D cache flush which is used when microcode providing
5952  * the cache control MSR is not loaded.
5953  *
5954  * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
5955  * flush it is required to read in 64 KiB because the replacement algorithm
5956  * is not exactly LRU. This could be sized at runtime via topology
5957  * information but as all relevant affected CPUs have 32KiB L1D cache size
5958  * there is no point in doing so.
5959  */
5960 static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
5961 {
5962         int size = PAGE_SIZE << L1D_CACHE_ORDER;
5963
5964         /*
5965          * This code is only executed when the the flush mode is 'cond' or
5966          * 'always'
5967          */
5968         if (static_branch_likely(&vmx_l1d_flush_cond)) {
5969                 bool flush_l1d;
5970
5971                 /*
5972                  * Clear the per-vcpu flush bit, it gets set again
5973                  * either from vcpu_run() or from one of the unsafe
5974                  * VMEXIT handlers.
5975                  */
5976                 flush_l1d = vcpu->arch.l1tf_flush_l1d;
5977                 vcpu->arch.l1tf_flush_l1d = false;
5978
5979                 /*
5980                  * Clear the per-cpu flush bit, it gets set again from
5981                  * the interrupt handlers.
5982                  */
5983                 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
5984                 kvm_clear_cpu_l1tf_flush_l1d();
5985
5986                 if (!flush_l1d)
5987                         return;
5988         }
5989
5990         vcpu->stat.l1d_flush++;
5991
5992         if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
5993                 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
5994                 return;
5995         }
5996
5997         asm volatile(
5998                 /* First ensure the pages are in the TLB */
5999                 "xorl   %%eax, %%eax\n"
6000                 ".Lpopulate_tlb:\n\t"
6001                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6002                 "addl   $4096, %%eax\n\t"
6003                 "cmpl   %%eax, %[size]\n\t"
6004                 "jne    .Lpopulate_tlb\n\t"
6005                 "xorl   %%eax, %%eax\n\t"
6006                 "cpuid\n\t"
6007                 /* Now fill the cache */
6008                 "xorl   %%eax, %%eax\n"
6009                 ".Lfill_cache:\n"
6010                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6011                 "addl   $64, %%eax\n\t"
6012                 "cmpl   %%eax, %[size]\n\t"
6013                 "jne    .Lfill_cache\n\t"
6014                 "lfence\n"
6015                 :: [flush_pages] "r" (vmx_l1d_flush_pages),
6016                     [size] "r" (size)
6017                 : "eax", "ebx", "ecx", "edx");
6018 }
6019
6020 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6021 {
6022         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6023         int tpr_threshold;
6024
6025         if (is_guest_mode(vcpu) &&
6026                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
6027                 return;
6028
6029         tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr;
6030         if (is_guest_mode(vcpu))
6031                 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold;
6032         else
6033                 vmcs_write32(TPR_THRESHOLD, tpr_threshold);
6034 }
6035
6036 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
6037 {
6038         struct vcpu_vmx *vmx = to_vmx(vcpu);
6039         u32 sec_exec_control;
6040
6041         if (!lapic_in_kernel(vcpu))
6042                 return;
6043
6044         if (!flexpriority_enabled &&
6045             !cpu_has_vmx_virtualize_x2apic_mode())
6046                 return;
6047
6048         /* Postpone execution until vmcs01 is the current VMCS. */
6049         if (is_guest_mode(vcpu)) {
6050                 vmx->nested.change_vmcs01_virtual_apic_mode = true;
6051                 return;
6052         }
6053
6054         sec_exec_control = secondary_exec_controls_get(vmx);
6055         sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6056                               SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
6057
6058         switch (kvm_get_apic_mode(vcpu)) {
6059         case LAPIC_MODE_INVALID:
6060                 WARN_ONCE(true, "Invalid local APIC state");
6061         case LAPIC_MODE_DISABLED:
6062                 break;
6063         case LAPIC_MODE_XAPIC:
6064                 if (flexpriority_enabled) {
6065                         sec_exec_control |=
6066                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6067                         vmx_flush_tlb(vcpu, true);
6068                 }
6069                 break;
6070         case LAPIC_MODE_X2APIC:
6071                 if (cpu_has_vmx_virtualize_x2apic_mode())
6072                         sec_exec_control |=
6073                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6074                 break;
6075         }
6076         secondary_exec_controls_set(vmx, sec_exec_control);
6077
6078         vmx_update_msr_bitmap(vcpu);
6079 }
6080
6081 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
6082 {
6083         if (!is_guest_mode(vcpu)) {
6084                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
6085                 vmx_flush_tlb(vcpu, true);
6086         }
6087 }
6088
6089 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6090 {
6091         u16 status;
6092         u8 old;
6093
6094         if (max_isr == -1)
6095                 max_isr = 0;
6096
6097         status = vmcs_read16(GUEST_INTR_STATUS);
6098         old = status >> 8;
6099         if (max_isr != old) {
6100                 status &= 0xff;
6101                 status |= max_isr << 8;
6102                 vmcs_write16(GUEST_INTR_STATUS, status);
6103         }
6104 }
6105
6106 static void vmx_set_rvi(int vector)
6107 {
6108         u16 status;
6109         u8 old;
6110
6111         if (vector == -1)
6112                 vector = 0;
6113
6114         status = vmcs_read16(GUEST_INTR_STATUS);
6115         old = (u8)status & 0xff;
6116         if ((u8)vector != old) {
6117                 status &= ~0xff;
6118                 status |= (u8)vector;
6119                 vmcs_write16(GUEST_INTR_STATUS, status);
6120         }
6121 }
6122
6123 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6124 {
6125         /*
6126          * When running L2, updating RVI is only relevant when
6127          * vmcs12 virtual-interrupt-delivery enabled.
6128          * However, it can be enabled only when L1 also
6129          * intercepts external-interrupts and in that case
6130          * we should not update vmcs02 RVI but instead intercept
6131          * interrupt. Therefore, do nothing when running L2.
6132          */
6133         if (!is_guest_mode(vcpu))
6134                 vmx_set_rvi(max_irr);
6135 }
6136
6137 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6138 {
6139         struct vcpu_vmx *vmx = to_vmx(vcpu);
6140         int max_irr;
6141         bool max_irr_updated;
6142
6143         WARN_ON(!vcpu->arch.apicv_active);
6144         if (pi_test_on(&vmx->pi_desc)) {
6145                 pi_clear_on(&vmx->pi_desc);
6146                 /*
6147                  * IOMMU can write to PID.ON, so the barrier matters even on UP.
6148                  * But on x86 this is just a compiler barrier anyway.
6149                  */
6150                 smp_mb__after_atomic();
6151                 max_irr_updated =
6152                         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
6153
6154                 /*
6155                  * If we are running L2 and L1 has a new pending interrupt
6156                  * which can be injected, we should re-evaluate
6157                  * what should be done with this new L1 interrupt.
6158                  * If L1 intercepts external-interrupts, we should
6159                  * exit from L2 to L1. Otherwise, interrupt should be
6160                  * delivered directly to L2.
6161                  */
6162                 if (is_guest_mode(vcpu) && max_irr_updated) {
6163                         if (nested_exit_on_intr(vcpu))
6164                                 kvm_vcpu_exiting_guest_mode(vcpu);
6165                         else
6166                                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6167                 }
6168         } else {
6169                 max_irr = kvm_lapic_find_highest_irr(vcpu);
6170         }
6171         vmx_hwapic_irr_update(vcpu, max_irr);
6172         return max_irr;
6173 }
6174
6175 static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
6176 {
6177         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6178
6179         return pi_test_on(pi_desc) ||
6180                 (pi_test_sn(pi_desc) && !pi_is_pir_empty(pi_desc));
6181 }
6182
6183 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6184 {
6185         if (!kvm_vcpu_apicv_active(vcpu))
6186                 return;
6187
6188         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6189         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6190         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6191         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6192 }
6193
6194 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
6195 {
6196         struct vcpu_vmx *vmx = to_vmx(vcpu);
6197
6198         pi_clear_on(&vmx->pi_desc);
6199         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6200 }
6201
6202 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
6203 {
6204         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6205
6206         /* if exit due to PF check for async PF */
6207         if (is_page_fault(vmx->exit_intr_info)) {
6208                 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
6209         /* Handle machine checks before interrupts are enabled */
6210         } else if (is_machine_check(vmx->exit_intr_info)) {
6211                 kvm_machine_check();
6212         /* We need to handle NMIs before interrupts are enabled */
6213         } else if (is_nmi(vmx->exit_intr_info)) {
6214                 kvm_before_interrupt(&vmx->vcpu);
6215                 asm("int $2");
6216                 kvm_after_interrupt(&vmx->vcpu);
6217         }
6218 }
6219
6220 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
6221 {
6222         unsigned int vector;
6223         unsigned long entry;
6224 #ifdef CONFIG_X86_64
6225         unsigned long tmp;
6226 #endif
6227         gate_desc *desc;
6228         u32 intr_info;
6229
6230         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6231         if (WARN_ONCE(!is_external_intr(intr_info),
6232             "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6233                 return;
6234
6235         vector = intr_info & INTR_INFO_VECTOR_MASK;
6236         desc = (gate_desc *)host_idt_base + vector;
6237         entry = gate_offset(desc);
6238
6239         kvm_before_interrupt(vcpu);
6240
6241         asm volatile(
6242 #ifdef CONFIG_X86_64
6243                 "mov %%" _ASM_SP ", %[sp]\n\t"
6244                 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6245                 "push $%c[ss]\n\t"
6246                 "push %[sp]\n\t"
6247 #endif
6248                 "pushf\n\t"
6249                 __ASM_SIZE(push) " $%c[cs]\n\t"
6250                 CALL_NOSPEC
6251                 :
6252 #ifdef CONFIG_X86_64
6253                 [sp]"=&r"(tmp),
6254 #endif
6255                 ASM_CALL_CONSTRAINT
6256                 :
6257                 THUNK_TARGET(entry),
6258                 [ss]"i"(__KERNEL_DS),
6259                 [cs]"i"(__KERNEL_CS)
6260         );
6261
6262         kvm_after_interrupt(vcpu);
6263 }
6264 STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff);
6265
6266 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu,
6267         enum exit_fastpath_completion *exit_fastpath)
6268 {
6269         struct vcpu_vmx *vmx = to_vmx(vcpu);
6270
6271         if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
6272                 handle_external_interrupt_irqoff(vcpu);
6273         else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)
6274                 handle_exception_nmi_irqoff(vmx);
6275         else if (!is_guest_mode(vcpu) &&
6276                 vmx->exit_reason == EXIT_REASON_MSR_WRITE)
6277                 *exit_fastpath = handle_fastpath_set_msr_irqoff(vcpu);
6278 }
6279
6280 static bool vmx_has_emulated_msr(int index)
6281 {
6282         switch (index) {
6283         case MSR_IA32_SMBASE:
6284                 /*
6285                  * We cannot do SMM unless we can run the guest in big
6286                  * real mode.
6287                  */
6288                 return enable_unrestricted_guest || emulate_invalid_guest_state;
6289         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6290                 return nested;
6291         case MSR_AMD64_VIRT_SPEC_CTRL:
6292                 /* This is AMD only.  */
6293                 return false;
6294         default:
6295                 return true;
6296         }
6297 }
6298
6299 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6300 {
6301         u32 exit_intr_info;
6302         bool unblock_nmi;
6303         u8 vector;
6304         bool idtv_info_valid;
6305
6306         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6307
6308         if (enable_vnmi) {
6309                 if (vmx->loaded_vmcs->nmi_known_unmasked)
6310                         return;
6311                 /*
6312                  * Can't use vmx->exit_intr_info since we're not sure what
6313                  * the exit reason is.
6314                  */
6315                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6316                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6317                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6318                 /*
6319                  * SDM 3: 27.7.1.2 (September 2008)
6320                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6321                  * a guest IRET fault.
6322                  * SDM 3: 23.2.2 (September 2008)
6323                  * Bit 12 is undefined in any of the following cases:
6324                  *  If the VM exit sets the valid bit in the IDT-vectoring
6325                  *   information field.
6326                  *  If the VM exit is due to a double fault.
6327                  */
6328                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6329                     vector != DF_VECTOR && !idtv_info_valid)
6330                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6331                                       GUEST_INTR_STATE_NMI);
6332                 else
6333                         vmx->loaded_vmcs->nmi_known_unmasked =
6334                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6335                                   & GUEST_INTR_STATE_NMI);
6336         } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6337                 vmx->loaded_vmcs->vnmi_blocked_time +=
6338                         ktime_to_ns(ktime_sub(ktime_get(),
6339                                               vmx->loaded_vmcs->entry_time));
6340 }
6341
6342 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6343                                       u32 idt_vectoring_info,
6344                                       int instr_len_field,
6345                                       int error_code_field)
6346 {
6347         u8 vector;
6348         int type;
6349         bool idtv_info_valid;
6350
6351         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6352
6353         vcpu->arch.nmi_injected = false;
6354         kvm_clear_exception_queue(vcpu);
6355         kvm_clear_interrupt_queue(vcpu);
6356
6357         if (!idtv_info_valid)
6358                 return;
6359
6360         kvm_make_request(KVM_REQ_EVENT, vcpu);
6361
6362         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6363         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6364
6365         switch (type) {
6366         case INTR_TYPE_NMI_INTR:
6367                 vcpu->arch.nmi_injected = true;
6368                 /*
6369                  * SDM 3: 27.7.1.2 (September 2008)
6370                  * Clear bit "block by NMI" before VM entry if a NMI
6371                  * delivery faulted.
6372                  */
6373                 vmx_set_nmi_mask(vcpu, false);
6374                 break;
6375         case INTR_TYPE_SOFT_EXCEPTION:
6376                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6377                 /* fall through */
6378         case INTR_TYPE_HARD_EXCEPTION:
6379                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6380                         u32 err = vmcs_read32(error_code_field);
6381                         kvm_requeue_exception_e(vcpu, vector, err);
6382                 } else
6383                         kvm_requeue_exception(vcpu, vector);
6384                 break;
6385         case INTR_TYPE_SOFT_INTR:
6386                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6387                 /* fall through */
6388         case INTR_TYPE_EXT_INTR:
6389                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6390                 break;
6391         default:
6392                 break;
6393         }
6394 }
6395
6396 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6397 {
6398         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6399                                   VM_EXIT_INSTRUCTION_LEN,
6400                                   IDT_VECTORING_ERROR_CODE);
6401 }
6402
6403 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6404 {
6405         __vmx_complete_interrupts(vcpu,
6406                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6407                                   VM_ENTRY_INSTRUCTION_LEN,
6408                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6409
6410         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6411 }
6412
6413 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6414 {
6415         int i, nr_msrs;
6416         struct perf_guest_switch_msr *msrs;
6417
6418         msrs = perf_guest_get_msrs(&nr_msrs);
6419
6420         if (!msrs)
6421                 return;
6422
6423         for (i = 0; i < nr_msrs; i++)
6424                 if (msrs[i].host == msrs[i].guest)
6425                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6426                 else
6427                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6428                                         msrs[i].host, false);
6429 }
6430
6431 static void atomic_switch_umwait_control_msr(struct vcpu_vmx *vmx)
6432 {
6433         u32 host_umwait_control;
6434
6435         if (!vmx_has_waitpkg(vmx))
6436                 return;
6437
6438         host_umwait_control = get_umwait_control_msr();
6439
6440         if (vmx->msr_ia32_umwait_control != host_umwait_control)
6441                 add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL,
6442                         vmx->msr_ia32_umwait_control,
6443                         host_umwait_control, false);
6444         else
6445                 clear_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL);
6446 }
6447
6448 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
6449 {
6450         struct vcpu_vmx *vmx = to_vmx(vcpu);
6451         u64 tscl;
6452         u32 delta_tsc;
6453
6454         if (vmx->req_immediate_exit) {
6455                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6456                 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6457         } else if (vmx->hv_deadline_tsc != -1) {
6458                 tscl = rdtsc();
6459                 if (vmx->hv_deadline_tsc > tscl)
6460                         /* set_hv_timer ensures the delta fits in 32-bits */
6461                         delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6462                                 cpu_preemption_timer_multi);
6463                 else
6464                         delta_tsc = 0;
6465
6466                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6467                 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6468         } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6469                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6470                 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
6471         }
6472 }
6473
6474 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
6475 {
6476         if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6477                 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6478                 vmcs_writel(HOST_RSP, host_rsp);
6479         }
6480 }
6481
6482 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched);
6483
6484 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6485 {
6486         struct vcpu_vmx *vmx = to_vmx(vcpu);
6487         unsigned long cr3, cr4;
6488
6489         /* Record the guest's net vcpu time for enforced NMI injections. */
6490         if (unlikely(!enable_vnmi &&
6491                      vmx->loaded_vmcs->soft_vnmi_blocked))
6492                 vmx->loaded_vmcs->entry_time = ktime_get();
6493
6494         /* Don't enter VMX if guest state is invalid, let the exit handler
6495            start emulation until we arrive back to a valid state */
6496         if (vmx->emulation_required)
6497                 return;
6498
6499         if (vmx->ple_window_dirty) {
6500                 vmx->ple_window_dirty = false;
6501                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6502         }
6503
6504         /*
6505          * We did this in prepare_switch_to_guest, because it needs to
6506          * be within srcu_read_lock.
6507          */
6508         WARN_ON_ONCE(vmx->nested.need_vmcs12_to_shadow_sync);
6509
6510         if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP))
6511                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6512         if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP))
6513                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6514
6515         cr3 = __get_current_cr3_fast();
6516         if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6517                 vmcs_writel(HOST_CR3, cr3);
6518                 vmx->loaded_vmcs->host_state.cr3 = cr3;
6519         }
6520
6521         cr4 = cr4_read_shadow();
6522         if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6523                 vmcs_writel(HOST_CR4, cr4);
6524                 vmx->loaded_vmcs->host_state.cr4 = cr4;
6525         }
6526
6527         /* When single-stepping over STI and MOV SS, we must clear the
6528          * corresponding interruptibility bits in the guest state. Otherwise
6529          * vmentry fails as it then expects bit 14 (BS) in pending debug
6530          * exceptions being set, but that's not correct for the guest debugging
6531          * case. */
6532         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6533                 vmx_set_interrupt_shadow(vcpu, 0);
6534
6535         kvm_load_guest_xsave_state(vcpu);
6536
6537         if (static_cpu_has(X86_FEATURE_PKU) &&
6538             kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
6539             vcpu->arch.pkru != vmx->host_pkru)
6540                 __write_pkru(vcpu->arch.pkru);
6541
6542         pt_guest_enter(vmx);
6543
6544         if (vcpu_to_pmu(vcpu)->version)
6545                 atomic_switch_perf_msrs(vmx);
6546         atomic_switch_umwait_control_msr(vmx);
6547
6548         if (enable_preemption_timer)
6549                 vmx_update_hv_timer(vcpu);
6550
6551         if (lapic_in_kernel(vcpu) &&
6552                 vcpu->arch.apic->lapic_timer.timer_advance_ns)
6553                 kvm_wait_lapic_expire(vcpu);
6554
6555         /*
6556          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6557          * it's non-zero. Since vmentry is serialising on affected CPUs, there
6558          * is no need to worry about the conditional branch over the wrmsr
6559          * being speculatively taken.
6560          */
6561         x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6562
6563         /* L1D Flush includes CPU buffer clear to mitigate MDS */
6564         if (static_branch_unlikely(&vmx_l1d_should_flush))
6565                 vmx_l1d_flush(vcpu);
6566         else if (static_branch_unlikely(&mds_user_clear))
6567                 mds_clear_cpu_buffers();
6568
6569         if (vcpu->arch.cr2 != read_cr2())
6570                 write_cr2(vcpu->arch.cr2);
6571
6572         vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6573                                    vmx->loaded_vmcs->launched);
6574
6575         vcpu->arch.cr2 = read_cr2();
6576
6577         /*
6578          * We do not use IBRS in the kernel. If this vCPU has used the
6579          * SPEC_CTRL MSR it may have left it on; save the value and
6580          * turn it off. This is much more efficient than blindly adding
6581          * it to the atomic save/restore list. Especially as the former
6582          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6583          *
6584          * For non-nested case:
6585          * If the L01 MSR bitmap does not intercept the MSR, then we need to
6586          * save it.
6587          *
6588          * For nested case:
6589          * If the L02 MSR bitmap does not intercept the MSR, then we need to
6590          * save it.
6591          */
6592         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6593                 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
6594
6595         x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
6596
6597         /* All fields are clean at this point */
6598         if (static_branch_unlikely(&enable_evmcs))
6599                 current_evmcs->hv_clean_fields |=
6600                         HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
6601
6602         if (static_branch_unlikely(&enable_evmcs))
6603                 current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index;
6604
6605         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6606         if (vmx->host_debugctlmsr)
6607                 update_debugctlmsr(vmx->host_debugctlmsr);
6608
6609 #ifndef CONFIG_X86_64
6610         /*
6611          * The sysexit path does not restore ds/es, so we must set them to
6612          * a reasonable value ourselves.
6613          *
6614          * We can't defer this to vmx_prepare_switch_to_host() since that
6615          * function may be executed in interrupt context, which saves and
6616          * restore segments around it, nullifying its effect.
6617          */
6618         loadsegment(ds, __USER_DS);
6619         loadsegment(es, __USER_DS);
6620 #endif
6621
6622         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6623                                   | (1 << VCPU_EXREG_RFLAGS)
6624                                   | (1 << VCPU_EXREG_PDPTR)
6625                                   | (1 << VCPU_EXREG_SEGMENTS)
6626                                   | (1 << VCPU_EXREG_CR3));
6627         vcpu->arch.regs_dirty = 0;
6628
6629         pt_guest_exit(vmx);
6630
6631         /*
6632          * eager fpu is enabled if PKEY is supported and CR4 is switched
6633          * back on host, so it is safe to read guest PKRU from current
6634          * XSAVE.
6635          */
6636         if (static_cpu_has(X86_FEATURE_PKU) &&
6637             kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
6638                 vcpu->arch.pkru = rdpkru();
6639                 if (vcpu->arch.pkru != vmx->host_pkru)
6640                         __write_pkru(vmx->host_pkru);
6641         }
6642
6643         kvm_load_host_xsave_state(vcpu);
6644
6645         vmx->nested.nested_run_pending = 0;
6646         vmx->idt_vectoring_info = 0;
6647
6648         vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
6649         if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
6650                 kvm_machine_check();
6651
6652         if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6653                 return;
6654
6655         vmx->loaded_vmcs->launched = 1;
6656         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6657
6658         vmx_recover_nmi_blocking(vmx);
6659         vmx_complete_interrupts(vmx);
6660 }
6661
6662 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6663 {
6664         struct vcpu_vmx *vmx = to_vmx(vcpu);
6665
6666         if (enable_pml)
6667                 vmx_destroy_pml_buffer(vmx);
6668         free_vpid(vmx->vpid);
6669         nested_vmx_free_vcpu(vcpu);
6670         free_loaded_vmcs(vmx->loaded_vmcs);
6671 }
6672
6673 static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
6674 {
6675         struct vcpu_vmx *vmx;
6676         unsigned long *msr_bitmap;
6677         int i, cpu, err;
6678
6679         BUILD_BUG_ON(offsetof(struct vcpu_vmx, vcpu) != 0);
6680         vmx = to_vmx(vcpu);
6681
6682         err = -ENOMEM;
6683
6684         vmx->vpid = allocate_vpid();
6685
6686         /*
6687          * If PML is turned on, failure on enabling PML just results in failure
6688          * of creating the vcpu, therefore we can simplify PML logic (by
6689          * avoiding dealing with cases, such as enabling PML partially on vcpus
6690          * for the guest), etc.
6691          */
6692         if (enable_pml) {
6693                 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
6694                 if (!vmx->pml_pg)
6695                         goto free_vpid;
6696         }
6697
6698         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) != NR_SHARED_MSRS);
6699
6700         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6701                 u32 index = vmx_msr_index[i];
6702                 u32 data_low, data_high;
6703                 int j = vmx->nmsrs;
6704
6705                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
6706                         continue;
6707                 if (wrmsr_safe(index, data_low, data_high) < 0)
6708                         continue;
6709
6710                 vmx->guest_msrs[j].index = i;
6711                 vmx->guest_msrs[j].data = 0;
6712                 switch (index) {
6713                 case MSR_IA32_TSX_CTRL:
6714                         /*
6715                          * No need to pass TSX_CTRL_CPUID_CLEAR through, so
6716                          * let's avoid changing CPUID bits under the host
6717                          * kernel's feet.
6718                          */
6719                         vmx->guest_msrs[j].mask = ~(u64)TSX_CTRL_CPUID_CLEAR;
6720                         break;
6721                 default:
6722                         vmx->guest_msrs[j].mask = -1ull;
6723                         break;
6724                 }
6725                 ++vmx->nmsrs;
6726         }
6727
6728         err = alloc_loaded_vmcs(&vmx->vmcs01);
6729         if (err < 0)
6730                 goto free_pml;
6731
6732         msr_bitmap = vmx->vmcs01.msr_bitmap;
6733         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
6734         vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
6735         vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
6736         vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6737         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6738         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6739         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
6740         if (kvm_cstate_in_guest(vcpu->kvm)) {
6741                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R);
6742                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6743                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6744                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6745         }
6746         vmx->msr_bitmap_mode = 0;
6747
6748         vmx->loaded_vmcs = &vmx->vmcs01;
6749         cpu = get_cpu();
6750         vmx_vcpu_load(vcpu, cpu);
6751         vcpu->cpu = cpu;
6752         init_vmcs(vmx);
6753         vmx_vcpu_put(vcpu);
6754         put_cpu();
6755         if (cpu_need_virtualize_apic_accesses(vcpu)) {
6756                 err = alloc_apic_access_page(vcpu->kvm);
6757                 if (err)
6758                         goto free_vmcs;
6759         }
6760
6761         if (enable_ept && !enable_unrestricted_guest) {
6762                 err = init_rmode_identity_map(vcpu->kvm);
6763                 if (err)
6764                         goto free_vmcs;
6765         }
6766
6767         if (nested)
6768                 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
6769                                            vmx_capability.ept);
6770         else
6771                 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
6772
6773         vmx->nested.posted_intr_nv = -1;
6774         vmx->nested.current_vmptr = -1ull;
6775
6776         vcpu->arch.microcode_version = 0x100000000ULL;
6777         vmx->msr_ia32_feature_control_valid_bits = FEAT_CTL_LOCKED;
6778
6779         /*
6780          * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
6781          * or POSTED_INTR_WAKEUP_VECTOR.
6782          */
6783         vmx->pi_desc.nv = POSTED_INTR_VECTOR;
6784         vmx->pi_desc.sn = 1;
6785
6786         vmx->ept_pointer = INVALID_PAGE;
6787
6788         return 0;
6789
6790 free_vmcs:
6791         free_loaded_vmcs(vmx->loaded_vmcs);
6792 free_pml:
6793         vmx_destroy_pml_buffer(vmx);
6794 free_vpid:
6795         free_vpid(vmx->vpid);
6796         return err;
6797 }
6798
6799 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6800 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6801
6802 static int vmx_vm_init(struct kvm *kvm)
6803 {
6804         spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
6805
6806         if (!ple_gap)
6807                 kvm->arch.pause_in_guest = true;
6808
6809         if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6810                 switch (l1tf_mitigation) {
6811                 case L1TF_MITIGATION_OFF:
6812                 case L1TF_MITIGATION_FLUSH_NOWARN:
6813                         /* 'I explicitly don't care' is set */
6814                         break;
6815                 case L1TF_MITIGATION_FLUSH:
6816                 case L1TF_MITIGATION_FLUSH_NOSMT:
6817                 case L1TF_MITIGATION_FULL:
6818                         /*
6819                          * Warn upon starting the first VM in a potentially
6820                          * insecure environment.
6821                          */
6822                         if (sched_smt_active())
6823                                 pr_warn_once(L1TF_MSG_SMT);
6824                         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6825                                 pr_warn_once(L1TF_MSG_L1D);
6826                         break;
6827                 case L1TF_MITIGATION_FULL_FORCE:
6828                         /* Flush is enforced */
6829                         break;
6830                 }
6831         }
6832         kvm_apicv_init(kvm, enable_apicv);
6833         return 0;
6834 }
6835
6836 static int __init vmx_check_processor_compat(void)
6837 {
6838         struct vmcs_config vmcs_conf;
6839         struct vmx_capability vmx_cap;
6840
6841         if (!this_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
6842             !this_cpu_has(X86_FEATURE_VMX)) {
6843                 pr_err("kvm: VMX is disabled on CPU %d\n", smp_processor_id());
6844                 return -EIO;
6845         }
6846
6847         if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
6848                 return -EIO;
6849         if (nested)
6850                 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept);
6851         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6852                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6853                                 smp_processor_id());
6854                 return -EIO;
6855         }
6856         return 0;
6857 }
6858
6859 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6860 {
6861         u8 cache;
6862         u64 ipat = 0;
6863
6864         /* We wanted to honor guest CD/MTRR/PAT, but doing so could result in
6865          * memory aliases with conflicting memory types and sometimes MCEs.
6866          * We have to be careful as to what are honored and when.
6867          *
6868          * For MMIO, guest CD/MTRR are ignored.  The EPT memory type is set to
6869          * UC.  The effective memory type is UC or WC depending on guest PAT.
6870          * This was historically the source of MCEs and we want to be
6871          * conservative.
6872          *
6873          * When there is no need to deal with noncoherent DMA (e.g., no VT-d
6874          * or VT-d has snoop control), guest CD/MTRR/PAT are all ignored.  The
6875          * EPT memory type is set to WB.  The effective memory type is forced
6876          * WB.
6877          *
6878          * Otherwise, we trust guest.  Guest CD/MTRR/PAT are all honored.  The
6879          * EPT memory type is used to emulate guest CD/MTRR.
6880          */
6881
6882         if (is_mmio) {
6883                 cache = MTRR_TYPE_UNCACHABLE;
6884                 goto exit;
6885         }
6886
6887         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
6888                 ipat = VMX_EPT_IPAT_BIT;
6889                 cache = MTRR_TYPE_WRBACK;
6890                 goto exit;
6891         }
6892
6893         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
6894                 ipat = VMX_EPT_IPAT_BIT;
6895                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
6896                         cache = MTRR_TYPE_WRBACK;
6897                 else
6898                         cache = MTRR_TYPE_UNCACHABLE;
6899                 goto exit;
6900         }
6901
6902         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
6903
6904 exit:
6905         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
6906 }
6907
6908 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx)
6909 {
6910         /*
6911          * These bits in the secondary execution controls field
6912          * are dynamic, the others are mostly based on the hypervisor
6913          * architecture and the guest's CPUID.  Do not touch the
6914          * dynamic bits.
6915          */
6916         u32 mask =
6917                 SECONDARY_EXEC_SHADOW_VMCS |
6918                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
6919                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6920                 SECONDARY_EXEC_DESC;
6921
6922         u32 new_ctl = vmx->secondary_exec_control;
6923         u32 cur_ctl = secondary_exec_controls_get(vmx);
6924
6925         secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
6926 }
6927
6928 /*
6929  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
6930  * (indicating "allowed-1") if they are supported in the guest's CPUID.
6931  */
6932 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
6933 {
6934         struct vcpu_vmx *vmx = to_vmx(vcpu);
6935         struct kvm_cpuid_entry2 *entry;
6936
6937         vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
6938         vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
6939
6940 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
6941         if (entry && (entry->_reg & (_cpuid_mask)))                     \
6942                 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask);     \
6943 } while (0)
6944
6945         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
6946         cr4_fixed1_update(X86_CR4_VME,        edx, feature_bit(VME));
6947         cr4_fixed1_update(X86_CR4_PVI,        edx, feature_bit(VME));
6948         cr4_fixed1_update(X86_CR4_TSD,        edx, feature_bit(TSC));
6949         cr4_fixed1_update(X86_CR4_DE,         edx, feature_bit(DE));
6950         cr4_fixed1_update(X86_CR4_PSE,        edx, feature_bit(PSE));
6951         cr4_fixed1_update(X86_CR4_PAE,        edx, feature_bit(PAE));
6952         cr4_fixed1_update(X86_CR4_MCE,        edx, feature_bit(MCE));
6953         cr4_fixed1_update(X86_CR4_PGE,        edx, feature_bit(PGE));
6954         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, feature_bit(FXSR));
6955         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, feature_bit(XMM));
6956         cr4_fixed1_update(X86_CR4_VMXE,       ecx, feature_bit(VMX));
6957         cr4_fixed1_update(X86_CR4_SMXE,       ecx, feature_bit(SMX));
6958         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, feature_bit(PCID));
6959         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, feature_bit(XSAVE));
6960
6961         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6962         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, feature_bit(FSGSBASE));
6963         cr4_fixed1_update(X86_CR4_SMEP,       ebx, feature_bit(SMEP));
6964         cr4_fixed1_update(X86_CR4_SMAP,       ebx, feature_bit(SMAP));
6965         cr4_fixed1_update(X86_CR4_PKE,        ecx, feature_bit(PKU));
6966         cr4_fixed1_update(X86_CR4_UMIP,       ecx, feature_bit(UMIP));
6967         cr4_fixed1_update(X86_CR4_LA57,       ecx, feature_bit(LA57));
6968
6969 #undef cr4_fixed1_update
6970 }
6971
6972 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
6973 {
6974         struct vcpu_vmx *vmx = to_vmx(vcpu);
6975
6976         if (kvm_mpx_supported()) {
6977                 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
6978
6979                 if (mpx_enabled) {
6980                         vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
6981                         vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
6982                 } else {
6983                         vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
6984                         vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
6985                 }
6986         }
6987 }
6988
6989 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
6990 {
6991         struct vcpu_vmx *vmx = to_vmx(vcpu);
6992         struct kvm_cpuid_entry2 *best = NULL;
6993         int i;
6994
6995         for (i = 0; i < PT_CPUID_LEAVES; i++) {
6996                 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
6997                 if (!best)
6998                         return;
6999                 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
7000                 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
7001                 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
7002                 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
7003         }
7004
7005         /* Get the number of configurable Address Ranges for filtering */
7006         vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
7007                                                 PT_CAP_num_address_ranges);
7008
7009         /* Initialize and clear the no dependency bits */
7010         vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
7011                         RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
7012
7013         /*
7014          * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
7015          * will inject an #GP
7016          */
7017         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
7018                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
7019
7020         /*
7021          * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
7022          * PSBFreq can be set
7023          */
7024         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
7025                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
7026                                 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
7027
7028         /*
7029          * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
7030          * MTCFreq can be set
7031          */
7032         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
7033                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
7034                                 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
7035
7036         /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
7037         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
7038                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
7039                                                         RTIT_CTL_PTW_EN);
7040
7041         /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7042         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
7043                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
7044
7045         /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7046         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
7047                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
7048
7049         /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */
7050         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
7051                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
7052
7053         /* unmask address range configure area */
7054         for (i = 0; i < vmx->pt_desc.addr_range; i++)
7055                 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
7056 }
7057
7058 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7059 {
7060         struct vcpu_vmx *vmx = to_vmx(vcpu);
7061
7062         /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */
7063         vcpu->arch.xsaves_enabled = false;
7064
7065         if (cpu_has_secondary_exec_ctrls()) {
7066                 vmx_compute_secondary_exec_control(vmx);
7067                 vmcs_set_secondary_exec_control(vmx);
7068         }
7069
7070         if (nested_vmx_allowed(vcpu))
7071                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7072                         FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7073                         FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX;
7074         else
7075                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7076                         ~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7077                           FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX);
7078
7079         if (nested_vmx_allowed(vcpu)) {
7080                 nested_vmx_cr_fixed1_bits_update(vcpu);
7081                 nested_vmx_entry_exit_ctls_update(vcpu);
7082         }
7083
7084         if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7085                         guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7086                 update_intel_pt_cfg(vcpu);
7087
7088         if (boot_cpu_has(X86_FEATURE_RTM)) {
7089                 struct shared_msr_entry *msr;
7090                 msr = find_msr_entry(vmx, MSR_IA32_TSX_CTRL);
7091                 if (msr) {
7092                         bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM);
7093                         vmx_set_guest_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE);
7094                 }
7095         }
7096 }
7097
7098 static __init void vmx_set_cpu_caps(void)
7099 {
7100         kvm_set_cpu_caps();
7101
7102         /* CPUID 0x1 */
7103         if (nested)
7104                 kvm_cpu_cap_set(X86_FEATURE_VMX);
7105
7106         /* CPUID 0x7 */
7107         if (kvm_mpx_supported())
7108                 kvm_cpu_cap_check_and_set(X86_FEATURE_MPX);
7109         if (cpu_has_vmx_invpcid())
7110                 kvm_cpu_cap_check_and_set(X86_FEATURE_INVPCID);
7111         if (vmx_pt_mode_is_host_guest())
7112                 kvm_cpu_cap_check_and_set(X86_FEATURE_INTEL_PT);
7113
7114         /* PKU is not yet implemented for shadow paging. */
7115         if (enable_ept && boot_cpu_has(X86_FEATURE_OSPKE))
7116                 kvm_cpu_cap_check_and_set(X86_FEATURE_PKU);
7117
7118         if (vmx_umip_emulated())
7119                 kvm_cpu_cap_set(X86_FEATURE_UMIP);
7120
7121         /* CPUID 0xD.1 */
7122         supported_xss = 0;
7123         if (!vmx_xsaves_supported())
7124                 kvm_cpu_cap_clear(X86_FEATURE_XSAVES);
7125
7126         /* CPUID 0x80000001 */
7127         if (!cpu_has_vmx_rdtscp())
7128                 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP);
7129 }
7130
7131 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
7132 {
7133         to_vmx(vcpu)->req_immediate_exit = true;
7134 }
7135
7136 static int vmx_check_intercept_io(struct kvm_vcpu *vcpu,
7137                                   struct x86_instruction_info *info)
7138 {
7139         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7140         unsigned short port;
7141         bool intercept;
7142         int size;
7143
7144         if (info->intercept == x86_intercept_in ||
7145             info->intercept == x86_intercept_ins) {
7146                 port = info->src_val;
7147                 size = info->dst_bytes;
7148         } else {
7149                 port = info->dst_val;
7150                 size = info->src_bytes;
7151         }
7152
7153         /*
7154          * If the 'use IO bitmaps' VM-execution control is 0, IO instruction
7155          * VM-exits depend on the 'unconditional IO exiting' VM-execution
7156          * control.
7157          *
7158          * Otherwise, IO instruction VM-exits are controlled by the IO bitmaps.
7159          */
7160         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7161                 intercept = nested_cpu_has(vmcs12,
7162                                            CPU_BASED_UNCOND_IO_EXITING);
7163         else
7164                 intercept = nested_vmx_check_io_bitmaps(vcpu, port, size);
7165
7166         return intercept ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE;
7167 }
7168
7169 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7170                                struct x86_instruction_info *info,
7171                                enum x86_intercept_stage stage,
7172                                struct x86_exception *exception)
7173 {
7174         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7175
7176         switch (info->intercept) {
7177         /*
7178          * RDPID causes #UD if disabled through secondary execution controls.
7179          * Because it is marked as EmulateOnUD, we need to intercept it here.
7180          */
7181         case x86_intercept_rdtscp:
7182                 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
7183                         exception->vector = UD_VECTOR;
7184                         exception->error_code_valid = false;
7185                         return X86EMUL_PROPAGATE_FAULT;
7186                 }
7187                 break;
7188
7189         case x86_intercept_in:
7190         case x86_intercept_ins:
7191         case x86_intercept_out:
7192         case x86_intercept_outs:
7193                 return vmx_check_intercept_io(vcpu, info);
7194
7195         /* TODO: check more intercepts... */
7196         default:
7197                 break;
7198         }
7199
7200         return X86EMUL_UNHANDLEABLE;
7201 }
7202
7203 #ifdef CONFIG_X86_64
7204 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7205 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7206                                   u64 divisor, u64 *result)
7207 {
7208         u64 low = a << shift, high = a >> (64 - shift);
7209
7210         /* To avoid the overflow on divq */
7211         if (high >= divisor)
7212                 return 1;
7213
7214         /* Low hold the result, high hold rem which is discarded */
7215         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7216             "rm" (divisor), "0" (low), "1" (high));
7217         *result = low;
7218
7219         return 0;
7220 }
7221
7222 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7223                             bool *expired)
7224 {
7225         struct vcpu_vmx *vmx;
7226         u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
7227         struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
7228
7229         if (kvm_mwait_in_guest(vcpu->kvm) ||
7230                 kvm_can_post_timer_interrupt(vcpu))
7231                 return -EOPNOTSUPP;
7232
7233         vmx = to_vmx(vcpu);
7234         tscl = rdtsc();
7235         guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7236         delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
7237         lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7238                                                     ktimer->timer_advance_ns);
7239
7240         if (delta_tsc > lapic_timer_advance_cycles)
7241                 delta_tsc -= lapic_timer_advance_cycles;
7242         else
7243                 delta_tsc = 0;
7244
7245         /* Convert to host delta tsc if tsc scaling is enabled */
7246         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
7247             delta_tsc && u64_shl_div_u64(delta_tsc,
7248                                 kvm_tsc_scaling_ratio_frac_bits,
7249                                 vcpu->arch.tsc_scaling_ratio, &delta_tsc))
7250                 return -ERANGE;
7251
7252         /*
7253          * If the delta tsc can't fit in the 32 bit after the multi shift,
7254          * we can't use the preemption timer.
7255          * It's possible that it fits on later vmentries, but checking
7256          * on every vmentry is costly so we just use an hrtimer.
7257          */
7258         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7259                 return -ERANGE;
7260
7261         vmx->hv_deadline_tsc = tscl + delta_tsc;
7262         *expired = !delta_tsc;
7263         return 0;
7264 }
7265
7266 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7267 {
7268         to_vmx(vcpu)->hv_deadline_tsc = -1;
7269 }
7270 #endif
7271
7272 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
7273 {
7274         if (!kvm_pause_in_guest(vcpu->kvm))
7275                 shrink_ple_window(vcpu);
7276 }
7277
7278 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
7279                                      struct kvm_memory_slot *slot)
7280 {
7281         if (!kvm_dirty_log_manual_protect_and_init_set(kvm))
7282                 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
7283         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
7284 }
7285
7286 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
7287                                        struct kvm_memory_slot *slot)
7288 {
7289         kvm_mmu_slot_set_dirty(kvm, slot);
7290 }
7291
7292 static void vmx_flush_log_dirty(struct kvm *kvm)
7293 {
7294         kvm_flush_pml_buffers(kvm);
7295 }
7296
7297 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
7298 {
7299         struct vmcs12 *vmcs12;
7300         struct vcpu_vmx *vmx = to_vmx(vcpu);
7301         gpa_t gpa, dst;
7302
7303         if (is_guest_mode(vcpu)) {
7304                 WARN_ON_ONCE(vmx->nested.pml_full);
7305
7306                 /*
7307                  * Check if PML is enabled for the nested guest.
7308                  * Whether eptp bit 6 is set is already checked
7309                  * as part of A/D emulation.
7310                  */
7311                 vmcs12 = get_vmcs12(vcpu);
7312                 if (!nested_cpu_has_pml(vmcs12))
7313                         return 0;
7314
7315                 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
7316                         vmx->nested.pml_full = true;
7317                         return 1;
7318                 }
7319
7320                 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
7321                 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index;
7322
7323                 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa,
7324                                          offset_in_page(dst), sizeof(gpa)))
7325                         return 0;
7326
7327                 vmcs12->guest_pml_index--;
7328         }
7329
7330         return 0;
7331 }
7332
7333 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
7334                                            struct kvm_memory_slot *memslot,
7335                                            gfn_t offset, unsigned long mask)
7336 {
7337         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
7338 }
7339
7340 static void __pi_post_block(struct kvm_vcpu *vcpu)
7341 {
7342         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7343         struct pi_desc old, new;
7344         unsigned int dest;
7345
7346         do {
7347                 old.control = new.control = pi_desc->control;
7348                 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
7349                      "Wakeup handler not enabled while the VCPU is blocked\n");
7350
7351                 dest = cpu_physical_id(vcpu->cpu);
7352
7353                 if (x2apic_enabled())
7354                         new.ndst = dest;
7355                 else
7356                         new.ndst = (dest << 8) & 0xFF00;
7357
7358                 /* set 'NV' to 'notification vector' */
7359                 new.nv = POSTED_INTR_VECTOR;
7360         } while (cmpxchg64(&pi_desc->control, old.control,
7361                            new.control) != old.control);
7362
7363         if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
7364                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7365                 list_del(&vcpu->blocked_vcpu_list);
7366                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7367                 vcpu->pre_pcpu = -1;
7368         }
7369 }
7370
7371 /*
7372  * This routine does the following things for vCPU which is going
7373  * to be blocked if VT-d PI is enabled.
7374  * - Store the vCPU to the wakeup list, so when interrupts happen
7375  *   we can find the right vCPU to wake up.
7376  * - Change the Posted-interrupt descriptor as below:
7377  *      'NDST' <-- vcpu->pre_pcpu
7378  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
7379  * - If 'ON' is set during this process, which means at least one
7380  *   interrupt is posted for this vCPU, we cannot block it, in
7381  *   this case, return 1, otherwise, return 0.
7382  *
7383  */
7384 static int pi_pre_block(struct kvm_vcpu *vcpu)
7385 {
7386         unsigned int dest;
7387         struct pi_desc old, new;
7388         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7389
7390         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
7391                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
7392                 !kvm_vcpu_apicv_active(vcpu))
7393                 return 0;
7394
7395         WARN_ON(irqs_disabled());
7396         local_irq_disable();
7397         if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
7398                 vcpu->pre_pcpu = vcpu->cpu;
7399                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7400                 list_add_tail(&vcpu->blocked_vcpu_list,
7401                               &per_cpu(blocked_vcpu_on_cpu,
7402                                        vcpu->pre_pcpu));
7403                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7404         }
7405
7406         do {
7407                 old.control = new.control = pi_desc->control;
7408
7409                 WARN((pi_desc->sn == 1),
7410                      "Warning: SN field of posted-interrupts "
7411                      "is set before blocking\n");
7412
7413                 /*
7414                  * Since vCPU can be preempted during this process,
7415                  * vcpu->cpu could be different with pre_pcpu, we
7416                  * need to set pre_pcpu as the destination of wakeup
7417                  * notification event, then we can find the right vCPU
7418                  * to wakeup in wakeup handler if interrupts happen
7419                  * when the vCPU is in blocked state.
7420                  */
7421                 dest = cpu_physical_id(vcpu->pre_pcpu);
7422
7423                 if (x2apic_enabled())
7424                         new.ndst = dest;
7425                 else
7426                         new.ndst = (dest << 8) & 0xFF00;
7427
7428                 /* set 'NV' to 'wakeup vector' */
7429                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
7430         } while (cmpxchg64(&pi_desc->control, old.control,
7431                            new.control) != old.control);
7432
7433         /* We should not block the vCPU if an interrupt is posted for it.  */
7434         if (pi_test_on(pi_desc) == 1)
7435                 __pi_post_block(vcpu);
7436
7437         local_irq_enable();
7438         return (vcpu->pre_pcpu == -1);
7439 }
7440
7441 static int vmx_pre_block(struct kvm_vcpu *vcpu)
7442 {
7443         if (pi_pre_block(vcpu))
7444                 return 1;
7445
7446         if (kvm_lapic_hv_timer_in_use(vcpu))
7447                 kvm_lapic_switch_to_sw_timer(vcpu);
7448
7449         return 0;
7450 }
7451
7452 static void pi_post_block(struct kvm_vcpu *vcpu)
7453 {
7454         if (vcpu->pre_pcpu == -1)
7455                 return;
7456
7457         WARN_ON(irqs_disabled());
7458         local_irq_disable();
7459         __pi_post_block(vcpu);
7460         local_irq_enable();
7461 }
7462
7463 static void vmx_post_block(struct kvm_vcpu *vcpu)
7464 {
7465         if (kvm_x86_ops->set_hv_timer)
7466                 kvm_lapic_switch_to_hv_timer(vcpu);
7467
7468         pi_post_block(vcpu);
7469 }
7470
7471 /*
7472  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
7473  *
7474  * @kvm: kvm
7475  * @host_irq: host irq of the interrupt
7476  * @guest_irq: gsi of the interrupt
7477  * @set: set or unset PI
7478  * returns 0 on success, < 0 on failure
7479  */
7480 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
7481                               uint32_t guest_irq, bool set)
7482 {
7483         struct kvm_kernel_irq_routing_entry *e;
7484         struct kvm_irq_routing_table *irq_rt;
7485         struct kvm_lapic_irq irq;
7486         struct kvm_vcpu *vcpu;
7487         struct vcpu_data vcpu_info;
7488         int idx, ret = 0;
7489
7490         if (!kvm_arch_has_assigned_device(kvm) ||
7491                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7492                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
7493                 return 0;
7494
7495         idx = srcu_read_lock(&kvm->irq_srcu);
7496         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
7497         if (guest_irq >= irq_rt->nr_rt_entries ||
7498             hlist_empty(&irq_rt->map[guest_irq])) {
7499                 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
7500                              guest_irq, irq_rt->nr_rt_entries);
7501                 goto out;
7502         }
7503
7504         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
7505                 if (e->type != KVM_IRQ_ROUTING_MSI)
7506                         continue;
7507                 /*
7508                  * VT-d PI cannot support posting multicast/broadcast
7509                  * interrupts to a vCPU, we still use interrupt remapping
7510                  * for these kind of interrupts.
7511                  *
7512                  * For lowest-priority interrupts, we only support
7513                  * those with single CPU as the destination, e.g. user
7514                  * configures the interrupts via /proc/irq or uses
7515                  * irqbalance to make the interrupts single-CPU.
7516                  *
7517                  * We will support full lowest-priority interrupt later.
7518                  *
7519                  * In addition, we can only inject generic interrupts using
7520                  * the PI mechanism, refuse to route others through it.
7521                  */
7522
7523                 kvm_set_msi_irq(kvm, e, &irq);
7524                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) ||
7525                     !kvm_irq_is_postable(&irq)) {
7526                         /*
7527                          * Make sure the IRTE is in remapped mode if
7528                          * we don't handle it in posted mode.
7529                          */
7530                         ret = irq_set_vcpu_affinity(host_irq, NULL);
7531                         if (ret < 0) {
7532                                 printk(KERN_INFO
7533                                    "failed to back to remapped mode, irq: %u\n",
7534                                    host_irq);
7535                                 goto out;
7536                         }
7537
7538                         continue;
7539                 }
7540
7541                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
7542                 vcpu_info.vector = irq.vector;
7543
7544                 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
7545                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
7546
7547                 if (set)
7548                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
7549                 else
7550                         ret = irq_set_vcpu_affinity(host_irq, NULL);
7551
7552                 if (ret < 0) {
7553                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
7554                                         __func__);
7555                         goto out;
7556                 }
7557         }
7558
7559         ret = 0;
7560 out:
7561         srcu_read_unlock(&kvm->irq_srcu, idx);
7562         return ret;
7563 }
7564
7565 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7566 {
7567         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7568                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7569                         FEAT_CTL_LMCE_ENABLED;
7570         else
7571                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7572                         ~FEAT_CTL_LMCE_ENABLED;
7573 }
7574
7575 static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
7576 {
7577         /* we need a nested vmexit to enter SMM, postpone if run is pending */
7578         if (to_vmx(vcpu)->nested.nested_run_pending)
7579                 return 0;
7580         return 1;
7581 }
7582
7583 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7584 {
7585         struct vcpu_vmx *vmx = to_vmx(vcpu);
7586
7587         vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7588         if (vmx->nested.smm.guest_mode)
7589                 nested_vmx_vmexit(vcpu, -1, 0, 0);
7590
7591         vmx->nested.smm.vmxon = vmx->nested.vmxon;
7592         vmx->nested.vmxon = false;
7593         vmx_clear_hlt(vcpu);
7594         return 0;
7595 }
7596
7597 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
7598 {
7599         struct vcpu_vmx *vmx = to_vmx(vcpu);
7600         int ret;
7601
7602         if (vmx->nested.smm.vmxon) {
7603                 vmx->nested.vmxon = true;
7604                 vmx->nested.smm.vmxon = false;
7605         }
7606
7607         if (vmx->nested.smm.guest_mode) {
7608                 ret = nested_vmx_enter_non_root_mode(vcpu, false);
7609                 if (ret)
7610                         return ret;
7611
7612                 vmx->nested.smm.guest_mode = false;
7613         }
7614         return 0;
7615 }
7616
7617 static int enable_smi_window(struct kvm_vcpu *vcpu)
7618 {
7619         return 0;
7620 }
7621
7622 static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7623 {
7624         return false;
7625 }
7626
7627 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7628 {
7629         return to_vmx(vcpu)->nested.vmxon;
7630 }
7631
7632 static __init int hardware_setup(void)
7633 {
7634         unsigned long host_bndcfgs;
7635         struct desc_ptr dt;
7636         int r, i, ept_lpage_level;
7637
7638         store_idt(&dt);
7639         host_idt_base = dt.address;
7640
7641         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7642                 kvm_define_shared_msr(i, vmx_msr_index[i]);
7643
7644         if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7645                 return -EIO;
7646
7647         if (boot_cpu_has(X86_FEATURE_NX))
7648                 kvm_enable_efer_bits(EFER_NX);
7649
7650         if (boot_cpu_has(X86_FEATURE_MPX)) {
7651                 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7652                 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7653         }
7654
7655         if (!cpu_has_vmx_mpx())
7656                 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS |
7657                                     XFEATURE_MASK_BNDCSR);
7658
7659         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7660             !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7661                 enable_vpid = 0;
7662
7663         if (!cpu_has_vmx_ept() ||
7664             !cpu_has_vmx_ept_4levels() ||
7665             !cpu_has_vmx_ept_mt_wb() ||
7666             !cpu_has_vmx_invept_global())
7667                 enable_ept = 0;
7668
7669         if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7670                 enable_ept_ad_bits = 0;
7671
7672         if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7673                 enable_unrestricted_guest = 0;
7674
7675         if (!cpu_has_vmx_flexpriority())
7676                 flexpriority_enabled = 0;
7677
7678         if (!cpu_has_virtual_nmis())
7679                 enable_vnmi = 0;
7680
7681         /*
7682          * set_apic_access_page_addr() is used to reload apic access
7683          * page upon invalidation.  No need to do anything if not
7684          * using the APIC_ACCESS_ADDR VMCS field.
7685          */
7686         if (!flexpriority_enabled)
7687                 kvm_x86_ops->set_apic_access_page_addr = NULL;
7688
7689         if (!cpu_has_vmx_tpr_shadow())
7690                 kvm_x86_ops->update_cr8_intercept = NULL;
7691
7692 #if IS_ENABLED(CONFIG_HYPERV)
7693         if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7694             && enable_ept) {
7695                 kvm_x86_ops->tlb_remote_flush = hv_remote_flush_tlb;
7696                 kvm_x86_ops->tlb_remote_flush_with_range =
7697                                 hv_remote_flush_tlb_with_range;
7698         }
7699 #endif
7700
7701         if (!cpu_has_vmx_ple()) {
7702                 ple_gap = 0;
7703                 ple_window = 0;
7704                 ple_window_grow = 0;
7705                 ple_window_max = 0;
7706                 ple_window_shrink = 0;
7707         }
7708
7709         if (!cpu_has_vmx_apicv()) {
7710                 enable_apicv = 0;
7711                 kvm_x86_ops->sync_pir_to_irr = NULL;
7712         }
7713
7714         if (cpu_has_vmx_tsc_scaling()) {
7715                 kvm_has_tsc_control = true;
7716                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7717                 kvm_tsc_scaling_ratio_frac_bits = 48;
7718         }
7719
7720         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7721
7722         if (enable_ept)
7723                 vmx_enable_tdp();
7724
7725         if (!enable_ept)
7726                 ept_lpage_level = 0;
7727         else if (cpu_has_vmx_ept_1g_page())
7728                 ept_lpage_level = PT_PDPE_LEVEL;
7729         else if (cpu_has_vmx_ept_2m_page())
7730                 ept_lpage_level = PT_DIRECTORY_LEVEL;
7731         else
7732                 ept_lpage_level = PT_PAGE_TABLE_LEVEL;
7733         kvm_configure_mmu(enable_ept, ept_lpage_level);
7734
7735         /*
7736          * Only enable PML when hardware supports PML feature, and both EPT
7737          * and EPT A/D bit features are enabled -- PML depends on them to work.
7738          */
7739         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7740                 enable_pml = 0;
7741
7742         if (!enable_pml) {
7743                 kvm_x86_ops->slot_enable_log_dirty = NULL;
7744                 kvm_x86_ops->slot_disable_log_dirty = NULL;
7745                 kvm_x86_ops->flush_log_dirty = NULL;
7746                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7747         }
7748
7749         if (!cpu_has_vmx_preemption_timer())
7750                 enable_preemption_timer = false;
7751
7752         if (enable_preemption_timer) {
7753                 u64 use_timer_freq = 5000ULL * 1000 * 1000;
7754                 u64 vmx_msr;
7755
7756                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7757                 cpu_preemption_timer_multi =
7758                         vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7759
7760                 if (tsc_khz)
7761                         use_timer_freq = (u64)tsc_khz * 1000;
7762                 use_timer_freq >>= cpu_preemption_timer_multi;
7763
7764                 /*
7765                  * KVM "disables" the preemption timer by setting it to its max
7766                  * value.  Don't use the timer if it might cause spurious exits
7767                  * at a rate faster than 0.1 Hz (of uninterrupted guest time).
7768                  */
7769                 if (use_timer_freq > 0xffffffffu / 10)
7770                         enable_preemption_timer = false;
7771         }
7772
7773         if (!enable_preemption_timer) {
7774                 kvm_x86_ops->set_hv_timer = NULL;
7775                 kvm_x86_ops->cancel_hv_timer = NULL;
7776                 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit;
7777         }
7778
7779         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
7780
7781         kvm_mce_cap_supported |= MCG_LMCE_P;
7782
7783         if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
7784                 return -EINVAL;
7785         if (!enable_ept || !cpu_has_vmx_intel_pt())
7786                 pt_mode = PT_MODE_SYSTEM;
7787
7788         if (nested) {
7789                 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
7790                                            vmx_capability.ept);
7791
7792                 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
7793                 if (r)
7794                         return r;
7795         }
7796
7797         vmx_set_cpu_caps();
7798
7799         r = alloc_kvm_area();
7800         if (r)
7801                 nested_vmx_hardware_unsetup();
7802         return r;
7803 }
7804
7805 static __exit void hardware_unsetup(void)
7806 {
7807         if (nested)
7808                 nested_vmx_hardware_unsetup();
7809
7810         free_kvm_area();
7811 }
7812
7813 static bool vmx_check_apicv_inhibit_reasons(ulong bit)
7814 {
7815         ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) |
7816                           BIT(APICV_INHIBIT_REASON_HYPERV);
7817
7818         return supported & BIT(bit);
7819 }
7820
7821 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
7822         .cpu_has_kvm_support = cpu_has_kvm_support,
7823         .disabled_by_bios = vmx_disabled_by_bios,
7824         .hardware_setup = hardware_setup,
7825         .hardware_unsetup = hardware_unsetup,
7826         .check_processor_compatibility = vmx_check_processor_compat,
7827         .hardware_enable = hardware_enable,
7828         .hardware_disable = hardware_disable,
7829         .cpu_has_accelerated_tpr = report_flexpriority,
7830         .has_emulated_msr = vmx_has_emulated_msr,
7831
7832         .vm_size = sizeof(struct kvm_vmx),
7833         .vm_init = vmx_vm_init,
7834
7835         .vcpu_create = vmx_create_vcpu,
7836         .vcpu_free = vmx_free_vcpu,
7837         .vcpu_reset = vmx_vcpu_reset,
7838
7839         .prepare_guest_switch = vmx_prepare_switch_to_guest,
7840         .vcpu_load = vmx_vcpu_load,
7841         .vcpu_put = vmx_vcpu_put,
7842
7843         .update_bp_intercept = update_exception_bitmap,
7844         .get_msr_feature = vmx_get_msr_feature,
7845         .get_msr = vmx_get_msr,
7846         .set_msr = vmx_set_msr,
7847         .get_segment_base = vmx_get_segment_base,
7848         .get_segment = vmx_get_segment,
7849         .set_segment = vmx_set_segment,
7850         .get_cpl = vmx_get_cpl,
7851         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7852         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7853         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7854         .set_cr0 = vmx_set_cr0,
7855         .set_cr4 = vmx_set_cr4,
7856         .set_efer = vmx_set_efer,
7857         .get_idt = vmx_get_idt,
7858         .set_idt = vmx_set_idt,
7859         .get_gdt = vmx_get_gdt,
7860         .set_gdt = vmx_set_gdt,
7861         .get_dr6 = vmx_get_dr6,
7862         .set_dr6 = vmx_set_dr6,
7863         .set_dr7 = vmx_set_dr7,
7864         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
7865         .cache_reg = vmx_cache_reg,
7866         .get_rflags = vmx_get_rflags,
7867         .set_rflags = vmx_set_rflags,
7868
7869         .tlb_flush = vmx_flush_tlb,
7870         .tlb_flush_gva = vmx_flush_tlb_gva,
7871
7872         .run = vmx_vcpu_run,
7873         .handle_exit = vmx_handle_exit,
7874         .skip_emulated_instruction = vmx_skip_emulated_instruction,
7875         .update_emulated_instruction = vmx_update_emulated_instruction,
7876         .set_interrupt_shadow = vmx_set_interrupt_shadow,
7877         .get_interrupt_shadow = vmx_get_interrupt_shadow,
7878         .patch_hypercall = vmx_patch_hypercall,
7879         .set_irq = vmx_inject_irq,
7880         .set_nmi = vmx_inject_nmi,
7881         .queue_exception = vmx_queue_exception,
7882         .cancel_injection = vmx_cancel_injection,
7883         .interrupt_allowed = vmx_interrupt_allowed,
7884         .nmi_allowed = vmx_nmi_allowed,
7885         .get_nmi_mask = vmx_get_nmi_mask,
7886         .set_nmi_mask = vmx_set_nmi_mask,
7887         .enable_nmi_window = enable_nmi_window,
7888         .enable_irq_window = enable_irq_window,
7889         .update_cr8_intercept = update_cr8_intercept,
7890         .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
7891         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
7892         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
7893         .load_eoi_exitmap = vmx_load_eoi_exitmap,
7894         .apicv_post_state_restore = vmx_apicv_post_state_restore,
7895         .check_apicv_inhibit_reasons = vmx_check_apicv_inhibit_reasons,
7896         .hwapic_irr_update = vmx_hwapic_irr_update,
7897         .hwapic_isr_update = vmx_hwapic_isr_update,
7898         .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
7899         .sync_pir_to_irr = vmx_sync_pir_to_irr,
7900         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
7901         .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt,
7902
7903         .set_tss_addr = vmx_set_tss_addr,
7904         .set_identity_map_addr = vmx_set_identity_map_addr,
7905         .get_tdp_level = get_ept_level,
7906         .get_mt_mask = vmx_get_mt_mask,
7907
7908         .get_exit_info = vmx_get_exit_info,
7909
7910         .cpuid_update = vmx_cpuid_update,
7911
7912         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7913
7914         .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
7915         .write_l1_tsc_offset = vmx_write_l1_tsc_offset,
7916
7917         .load_mmu_pgd = vmx_load_mmu_pgd,
7918
7919         .check_intercept = vmx_check_intercept,
7920         .handle_exit_irqoff = vmx_handle_exit_irqoff,
7921
7922         .request_immediate_exit = vmx_request_immediate_exit,
7923
7924         .sched_in = vmx_sched_in,
7925
7926         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
7927         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
7928         .flush_log_dirty = vmx_flush_log_dirty,
7929         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
7930         .write_log_dirty = vmx_write_pml_buffer,
7931
7932         .pre_block = vmx_pre_block,
7933         .post_block = vmx_post_block,
7934
7935         .pmu_ops = &intel_pmu_ops,
7936
7937         .update_pi_irte = vmx_update_pi_irte,
7938
7939 #ifdef CONFIG_X86_64
7940         .set_hv_timer = vmx_set_hv_timer,
7941         .cancel_hv_timer = vmx_cancel_hv_timer,
7942 #endif
7943
7944         .setup_mce = vmx_setup_mce,
7945
7946         .smi_allowed = vmx_smi_allowed,
7947         .pre_enter_smm = vmx_pre_enter_smm,
7948         .pre_leave_smm = vmx_pre_leave_smm,
7949         .enable_smi_window = enable_smi_window,
7950
7951         .check_nested_events = NULL,
7952         .get_nested_state = NULL,
7953         .set_nested_state = NULL,
7954         .get_vmcs12_pages = NULL,
7955         .nested_enable_evmcs = NULL,
7956         .nested_get_evmcs_version = NULL,
7957         .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault,
7958         .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
7959 };
7960
7961 static void vmx_cleanup_l1d_flush(void)
7962 {
7963         if (vmx_l1d_flush_pages) {
7964                 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
7965                 vmx_l1d_flush_pages = NULL;
7966         }
7967         /* Restore state so sysfs ignores VMX */
7968         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
7969 }
7970
7971 static void vmx_exit(void)
7972 {
7973 #ifdef CONFIG_KEXEC_CORE
7974         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
7975         synchronize_rcu();
7976 #endif
7977
7978         kvm_exit();
7979
7980 #if IS_ENABLED(CONFIG_HYPERV)
7981         if (static_branch_unlikely(&enable_evmcs)) {
7982                 int cpu;
7983                 struct hv_vp_assist_page *vp_ap;
7984                 /*
7985                  * Reset everything to support using non-enlightened VMCS
7986                  * access later (e.g. when we reload the module with
7987                  * enlightened_vmcs=0)
7988                  */
7989                 for_each_online_cpu(cpu) {
7990                         vp_ap = hv_get_vp_assist_page(cpu);
7991
7992                         if (!vp_ap)
7993                                 continue;
7994
7995                         vp_ap->nested_control.features.directhypercall = 0;
7996                         vp_ap->current_nested_vmcs = 0;
7997                         vp_ap->enlighten_vmentry = 0;
7998                 }
7999
8000                 static_branch_disable(&enable_evmcs);
8001         }
8002 #endif
8003         vmx_cleanup_l1d_flush();
8004 }
8005 module_exit(vmx_exit);
8006
8007 static int __init vmx_init(void)
8008 {
8009         int r;
8010
8011 #if IS_ENABLED(CONFIG_HYPERV)
8012         /*
8013          * Enlightened VMCS usage should be recommended and the host needs
8014          * to support eVMCS v1 or above. We can also disable eVMCS support
8015          * with module parameter.
8016          */
8017         if (enlightened_vmcs &&
8018             ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
8019             (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
8020             KVM_EVMCS_VERSION) {
8021                 int cpu;
8022
8023                 /* Check that we have assist pages on all online CPUs */
8024                 for_each_online_cpu(cpu) {
8025                         if (!hv_get_vp_assist_page(cpu)) {
8026                                 enlightened_vmcs = false;
8027                                 break;
8028                         }
8029                 }
8030
8031                 if (enlightened_vmcs) {
8032                         pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
8033                         static_branch_enable(&enable_evmcs);
8034                 }
8035
8036                 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
8037                         vmx_x86_ops.enable_direct_tlbflush
8038                                 = hv_enable_direct_tlbflush;
8039
8040         } else {
8041                 enlightened_vmcs = false;
8042         }
8043 #endif
8044
8045         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8046                      __alignof__(struct vcpu_vmx), THIS_MODULE);
8047         if (r)
8048                 return r;
8049
8050         /*
8051          * Must be called after kvm_init() so enable_ept is properly set
8052          * up. Hand the parameter mitigation value in which was stored in
8053          * the pre module init parser. If no parameter was given, it will
8054          * contain 'auto' which will be turned into the default 'cond'
8055          * mitigation mode.
8056          */
8057         r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
8058         if (r) {
8059                 vmx_exit();
8060                 return r;
8061         }
8062
8063 #ifdef CONFIG_KEXEC_CORE
8064         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8065                            crash_vmclear_local_loaded_vmcss);
8066 #endif
8067         vmx_check_vmcs12_offsets();
8068
8069         return 0;
8070 }
8071 module_init(vmx_init);