arch/x86/kvm/vmx/vmx.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Kernel-based Virtual Machine driver for Linux
   4  *
   5  * This module enables machines with Intel VT-x extensions to run virtual
   6  * machines without emulation or binary translation.
   7  *
   8  * Copyright (C) 2006 Qumranet, Inc.
   9  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  10  *
  11  * Authors:
  12  *   Avi Kivity   <avi@qumranet.com>
  13  *   Yaniv Kamay  <yaniv@qumranet.com>
  14  */
  15
  16 #include <linux/highmem.h>
  17 #include <linux/hrtimer.h>
  18 #include <linux/kernel.h>
  19 #include <linux/kvm_host.h>
  20 #include <linux/module.h>
  21 #include <linux/moduleparam.h>
  22 #include <linux/mod_devicetable.h>
  23 #include <linux/mm.h>
  24 #include <linux/objtool.h>
  25 #include <linux/sched.h>
  26 #include <linux/sched/smt.h>
  27 #include <linux/slab.h>
  28 #include <linux/tboot.h>
  29 #include <linux/trace_events.h>
  30 #include <linux/entry-kvm.h>
  31
  32 #include <asm/apic.h>
  33 #include <asm/asm.h>
  34 #include <asm/cpu.h>
  35 #include <asm/cpu_device_id.h>
  36 #include <asm/debugreg.h>
  37 #include <asm/desc.h>
  38 #include <asm/fpu/internal.h>
  39 #include <asm/idtentry.h>
  40 #include <asm/io.h>
  41 #include <asm/irq_remapping.h>
  42 #include <asm/kexec.h>
  43 #include <asm/perf_event.h>
  44 #include <asm/mmu_context.h>
  45 #include <asm/mshyperv.h>
  46 #include <asm/mwait.h>
  47 #include <asm/spec-ctrl.h>
  48 #include <asm/virtext.h>
  49 #include <asm/vmx.h>
  50
  51 #include "capabilities.h"
  52 #include "cpuid.h"
  53 #include "evmcs.h"
  54 #include "hyperv.h"
  55 #include "kvm_onhyperv.h"
  56 #include "irq.h"
  57 #include "kvm_cache_regs.h"
  58 #include "lapic.h"
  59 #include "mmu.h"
  60 #include "nested.h"
  61 #include "pmu.h"
  62 #include "sgx.h"
  63 #include "trace.h"
  64 #include "vmcs.h"
  65 #include "vmcs12.h"
  66 #include "vmx.h"
  67 #include "x86.h"
  68
  69 MODULE_AUTHOR("Qumranet");
  70 MODULE_LICENSE("GPL");
  71
  72 #ifdef MODULE
  73 static const struct x86_cpu_id vmx_cpu_id[] = {
  74         X86_MATCH_FEATURE(X86_FEATURE_VMX, NULL),
  75         {}
  76 };
  77 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  78 #endif
  79
  80 bool __read_mostly enable_vpid = 1;
  81 module_param_named(vpid, enable_vpid, bool, 0444);
  82
  83 static bool __read_mostly enable_vnmi = 1;
  84 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
  85
  86 bool __read_mostly flexpriority_enabled = 1;
  87 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  88
  89 bool __read_mostly enable_ept = 1;
  90 module_param_named(ept, enable_ept, bool, S_IRUGO);
  91
  92 bool __read_mostly enable_unrestricted_guest = 1;
  93 module_param_named(unrestricted_guest,
  94                         enable_unrestricted_guest, bool, S_IRUGO);
  95
  96 bool __read_mostly enable_ept_ad_bits = 1;
  97 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  98
  99 static bool __read_mostly emulate_invalid_guest_state = true;
 100 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
 101
 102 static bool __read_mostly fasteoi = 1;
 103 module_param(fasteoi, bool, S_IRUGO);
 104
 105 module_param(enable_apicv, bool, S_IRUGO);
 106
 107 /*
 108  * If nested=1, nested virtualization is supported, i.e., guests may use
 109  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 110  * use VMX instructions.
 111  */
 112 static bool __read_mostly nested = 1;
 113 module_param(nested, bool, S_IRUGO);
 114
 115 bool __read_mostly enable_pml = 1;
 116 module_param_named(pml, enable_pml, bool, S_IRUGO);
 117
 118 static bool __read_mostly dump_invalid_vmcs = 0;
 119 module_param(dump_invalid_vmcs, bool, 0644);
 120
 121 #define MSR_BITMAP_MODE_X2APIC          1
 122 #define MSR_BITMAP_MODE_X2APIC_APICV    2
 123
 124 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 125
 126 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 127 static int __read_mostly cpu_preemption_timer_multi;
 128 static bool __read_mostly enable_preemption_timer = 1;
 129 #ifdef CONFIG_X86_64
 130 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 131 #endif
 132
 133 extern bool __read_mostly allow_smaller_maxphyaddr;
 134 module_param(allow_smaller_maxphyaddr, bool, S_IRUGO);
 135
 136 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
 137 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
 138 #define KVM_VM_CR0_ALWAYS_ON                            \
 139         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 140
 141 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
 142 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 143 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 144
 145 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 146
 147 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
 148         RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
 149         RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
 150         RTIT_STATUS_BYTECNT))
 151
 152 /*
 153  * List of MSRs that can be directly passed to the guest.
 154  * In addition to these x2apic and PT MSRs are handled specially.
 155  */
 156 static u32 vmx_possible_passthrough_msrs[MAX_POSSIBLE_PASSTHROUGH_MSRS] = {
 157         MSR_IA32_SPEC_CTRL,
 158         MSR_IA32_PRED_CMD,
 159         MSR_IA32_TSC,
 160 #ifdef CONFIG_X86_64
 161         MSR_FS_BASE,
 162         MSR_GS_BASE,
 163         MSR_KERNEL_GS_BASE,
 164 #endif
 165         MSR_IA32_SYSENTER_CS,
 166         MSR_IA32_SYSENTER_ESP,
 167         MSR_IA32_SYSENTER_EIP,
 168         MSR_CORE_C1_RES,
 169         MSR_CORE_C3_RESIDENCY,
 170         MSR_CORE_C6_RESIDENCY,
 171         MSR_CORE_C7_RESIDENCY,
 172 };
 173
 174 /*
 175  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 176  * ple_gap:    upper bound on the amount of time between two successive
 177  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 178  *             According to test, this time is usually smaller than 128 cycles.
 179  * ple_window: upper bound on the amount of time a guest is allowed to execute
 180  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 181  *             less than 2^12 cycles
 182  * Time is measured based on a counter that runs at the same rate as the TSC,
 183  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 184  */
 185 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
 186 module_param(ple_gap, uint, 0444);
 187
 188 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 189 module_param(ple_window, uint, 0444);
 190
 191 /* Default doubles per-vcpu window every exit. */
 192 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 193 module_param(ple_window_grow, uint, 0444);
 194
 195 /* Default resets per-vcpu window every exit to ple_window. */
 196 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 197 module_param(ple_window_shrink, uint, 0444);
 198
 199 /* Default is to compute the maximum so we can never overflow. */
 200 static unsigned int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 201 module_param(ple_window_max, uint, 0444);
 202
 203 /* Default is SYSTEM mode, 1 for host-guest mode */
 204 int __read_mostly pt_mode = PT_MODE_SYSTEM;
 205 module_param(pt_mode, int, S_IRUGO);
 206
 207 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
 208 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
 209 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
 210
 211 /* Storage for pre module init parameter parsing */
 212 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
 213
 214 static const struct {
 215         const char *option;
 216         bool for_parse;
 217 } vmentry_l1d_param[] = {
 218         [VMENTER_L1D_FLUSH_AUTO]         = {"auto", true},
 219         [VMENTER_L1D_FLUSH_NEVER]        = {"never", true},
 220         [VMENTER_L1D_FLUSH_COND]         = {"cond", true},
 221         [VMENTER_L1D_FLUSH_ALWAYS]       = {"always", true},
 222         [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
 223         [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
 224 };
 225
 226 #define L1D_CACHE_ORDER 4
 227 static void *vmx_l1d_flush_pages;
 228
 229 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
 230 {
 231         struct page *page;
 232         unsigned int i;
 233
 234         if (!boot_cpu_has_bug(X86_BUG_L1TF)) {
 235                 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
 236                 return 0;
 237         }
 238
 239         if (!enable_ept) {
 240                 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
 241                 return 0;
 242         }
 243
 244         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
 245                 u64 msr;
 246
 247                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
 248                 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
 249                         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
 250                         return 0;
 251                 }
 252         }
 253
 254         /* If set to auto use the default l1tf mitigation method */
 255         if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
 256                 switch (l1tf_mitigation) {
 257                 case L1TF_MITIGATION_OFF:
 258                         l1tf = VMENTER_L1D_FLUSH_NEVER;
 259                         break;
 260                 case L1TF_MITIGATION_FLUSH_NOWARN:
 261                 case L1TF_MITIGATION_FLUSH:
 262                 case L1TF_MITIGATION_FLUSH_NOSMT:
 263                         l1tf = VMENTER_L1D_FLUSH_COND;
 264                         break;
 265                 case L1TF_MITIGATION_FULL:
 266                 case L1TF_MITIGATION_FULL_FORCE:
 267                         l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 268                         break;
 269                 }
 270         } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
 271                 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 272         }
 273
 274         if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
 275             !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
 276                 /*
 277                  * This allocation for vmx_l1d_flush_pages is not tied to a VM
 278                  * lifetime and so should not be charged to a memcg.
 279                  */
 280                 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
 281                 if (!page)
 282                         return -ENOMEM;
 283                 vmx_l1d_flush_pages = page_address(page);
 284
 285                 /*
 286                  * Initialize each page with a different pattern in
 287                  * order to protect against KSM in the nested
 288                  * virtualization case.
 289                  */
 290                 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
 291                         memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
 292                                PAGE_SIZE);
 293                 }
 294         }
 295
 296         l1tf_vmx_mitigation = l1tf;
 297
 298         if (l1tf != VMENTER_L1D_FLUSH_NEVER)
 299                 static_branch_enable(&vmx_l1d_should_flush);
 300         else
 301                 static_branch_disable(&vmx_l1d_should_flush);
 302
 303         if (l1tf == VMENTER_L1D_FLUSH_COND)
 304                 static_branch_enable(&vmx_l1d_flush_cond);
 305         else
 306                 static_branch_disable(&vmx_l1d_flush_cond);
 307         return 0;
 308 }
 309
 310 static int vmentry_l1d_flush_parse(const char *s)
 311 {
 312         unsigned int i;
 313
 314         if (s) {
 315                 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
 316                         if (vmentry_l1d_param[i].for_parse &&
 317                             sysfs_streq(s, vmentry_l1d_param[i].option))
 318                                 return i;
 319                 }
 320         }
 321         return -EINVAL;
 322 }
 323
 324 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
 325 {
 326         int l1tf, ret;
 327
 328         l1tf = vmentry_l1d_flush_parse(s);
 329         if (l1tf < 0)
 330                 return l1tf;
 331
 332         if (!boot_cpu_has(X86_BUG_L1TF))
 333                 return 0;
 334
 335         /*
 336          * Has vmx_init() run already? If not then this is the pre init
 337          * parameter parsing. In that case just store the value and let
 338          * vmx_init() do the proper setup after enable_ept has been
 339          * established.
 340          */
 341         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
 342                 vmentry_l1d_flush_param = l1tf;
 343                 return 0;
 344         }
 345
 346         mutex_lock(&vmx_l1d_flush_mutex);
 347         ret = vmx_setup_l1d_flush(l1tf);
 348         mutex_unlock(&vmx_l1d_flush_mutex);
 349         return ret;
 350 }
 351
 352 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
 353 {
 354         if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
 355                 return sprintf(s, "???\n");
 356
 357         return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
 358 }
 359
 360 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
 361         .set = vmentry_l1d_flush_set,
 362         .get = vmentry_l1d_flush_get,
 363 };
 364 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
 365
 366 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 367
 368 void vmx_vmexit(void);
 369
 370 #define vmx_insn_failed(fmt...)         \
 371 do {                                    \
 372         WARN_ONCE(1, fmt);              \
 373         pr_warn_ratelimited(fmt);       \
 374 } while (0)
 375
 376 asmlinkage void vmread_error(unsigned long field, bool fault)
 377 {
 378         if (fault)
 379                 kvm_spurious_fault();
 380         else
 381                 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field);
 382 }
 383
 384 noinline void vmwrite_error(unsigned long field, unsigned long value)
 385 {
 386         vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n",
 387                         field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 388 }
 389
 390 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr)
 391 {
 392         vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr);
 393 }
 394
 395 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr)
 396 {
 397         vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr);
 398 }
 399
 400 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva)
 401 {
 402         vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n",
 403                         ext, vpid, gva);
 404 }
 405
 406 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa)
 407 {
 408         vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n",
 409                         ext, eptp, gpa);
 410 }
 411
 412 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 413 DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 414 /*
 415  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 416  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 417  */
 418 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 419
 420 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 421 static DEFINE_SPINLOCK(vmx_vpid_lock);
 422
 423 struct vmcs_config vmcs_config;
 424 struct vmx_capability vmx_capability;
 425
 426 #define VMX_SEGMENT_FIELD(seg)                                  \
 427         [VCPU_SREG_##seg] = {                                   \
 428                 .selector = GUEST_##seg##_SELECTOR,             \
 429                 .base = GUEST_##seg##_BASE,                     \
 430                 .limit = GUEST_##seg##_LIMIT,                   \
 431                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 432         }
 433
 434 static const struct kvm_vmx_segment_field {
 435         unsigned selector;
 436         unsigned base;
 437         unsigned limit;
 438         unsigned ar_bytes;
 439 } kvm_vmx_segment_fields[] = {
 440         VMX_SEGMENT_FIELD(CS),
 441         VMX_SEGMENT_FIELD(DS),
 442         VMX_SEGMENT_FIELD(ES),
 443         VMX_SEGMENT_FIELD(FS),
 444         VMX_SEGMENT_FIELD(GS),
 445         VMX_SEGMENT_FIELD(SS),
 446         VMX_SEGMENT_FIELD(TR),
 447         VMX_SEGMENT_FIELD(LDTR),
 448 };
 449
 450 static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
 451 {
 452         vmx->segment_cache.bitmask = 0;
 453 }
 454
 455 static unsigned long host_idt_base;
 456
 457 #if IS_ENABLED(CONFIG_HYPERV)
 458 static bool __read_mostly enlightened_vmcs = true;
 459 module_param(enlightened_vmcs, bool, 0444);
 460
 461 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
 462 {
 463         struct hv_enlightened_vmcs *evmcs;
 464         struct hv_partition_assist_pg **p_hv_pa_pg =
 465                         &to_kvm_hv(vcpu->kvm)->hv_pa_pg;
 466         /*
 467          * Synthetic VM-Exit is not enabled in current code and so All
 468          * evmcs in singe VM shares same assist page.
 469          */
 470         if (!*p_hv_pa_pg)
 471                 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL_ACCOUNT);
 472
 473         if (!*p_hv_pa_pg)
 474                 return -ENOMEM;
 475
 476         evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
 477
 478         evmcs->partition_assist_page =
 479                 __pa(*p_hv_pa_pg);
 480         evmcs->hv_vm_id = (unsigned long)vcpu->kvm;
 481         evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
 482
 483         return 0;
 484 }
 485
 486 #endif /* IS_ENABLED(CONFIG_HYPERV) */
 487
 488 /*
 489  * Comment's format: document - errata name - stepping - processor name.
 490  * Refer from
 491  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
 492  */
 493 static u32 vmx_preemption_cpu_tfms[] = {
 494 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
 495 0x000206E6,
 496 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
 497 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
 498 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
 499 0x00020652,
 500 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
 501 0x00020655,
 502 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
 503 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
 504 /*
 505  * 320767.pdf - AAP86  - B1 -
 506  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
 507  */
 508 0x000106E5,
 509 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
 510 0x000106A0,
 511 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
 512 0x000106A1,
 513 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
 514 0x000106A4,
 515  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
 516  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
 517  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
 518 0x000106A5,
 519  /* Xeon E3-1220 V2 */
 520 0x000306A8,
 521 };
 522
 523 static inline bool cpu_has_broken_vmx_preemption_timer(void)
 524 {
 525         u32 eax = cpuid_eax(0x00000001), i;
 526
 527         /* Clear the reserved bits */
 528         eax &= ~(0x3U << 14 | 0xfU << 28);
 529         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
 530                 if (eax == vmx_preemption_cpu_tfms[i])
 531                         return true;
 532
 533         return false;
 534 }
 535
 536 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
 537 {
 538         return flexpriority_enabled && lapic_in_kernel(vcpu);
 539 }
 540
 541 static inline bool report_flexpriority(void)
 542 {
 543         return flexpriority_enabled;
 544 }
 545
 546 static int possible_passthrough_msr_slot(u32 msr)
 547 {
 548         u32 i;
 549
 550         for (i = 0; i < ARRAY_SIZE(vmx_possible_passthrough_msrs); i++)
 551                 if (vmx_possible_passthrough_msrs[i] == msr)
 552                         return i;
 553
 554         return -ENOENT;
 555 }
 556
 557 static bool is_valid_passthrough_msr(u32 msr)
 558 {
 559         bool r;
 560
 561         switch (msr) {
 562         case 0x800 ... 0x8ff:
 563                 /* x2APIC MSRs. These are handled in vmx_update_msr_bitmap_x2apic() */
 564                 return true;
 565         case MSR_IA32_RTIT_STATUS:
 566         case MSR_IA32_RTIT_OUTPUT_BASE:
 567         case MSR_IA32_RTIT_OUTPUT_MASK:
 568         case MSR_IA32_RTIT_CR3_MATCH:
 569         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
 570                 /* PT MSRs. These are handled in pt_update_intercept_for_msr() */
 571         case MSR_LBR_SELECT:
 572         case MSR_LBR_TOS:
 573         case MSR_LBR_INFO_0 ... MSR_LBR_INFO_0 + 31:
 574         case MSR_LBR_NHM_FROM ... MSR_LBR_NHM_FROM + 31:
 575         case MSR_LBR_NHM_TO ... MSR_LBR_NHM_TO + 31:
 576         case MSR_LBR_CORE_FROM ... MSR_LBR_CORE_FROM + 8:
 577         case MSR_LBR_CORE_TO ... MSR_LBR_CORE_TO + 8:
 578                 /* LBR MSRs. These are handled in vmx_update_intercept_for_lbr_msrs() */
 579                 return true;
 580         }
 581
 582         r = possible_passthrough_msr_slot(msr) != -ENOENT;
 583
 584         WARN(!r, "Invalid MSR %x, please adapt vmx_possible_passthrough_msrs[]", msr);
 585
 586         return r;
 587 }
 588
 589 struct vmx_uret_msr *vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr)
 590 {
 591         int i;
 592
 593         i = kvm_find_user_return_msr(msr);
 594         if (i >= 0)
 595                 return &vmx->guest_uret_msrs[i];
 596         return NULL;
 597 }
 598
 599 static int vmx_set_guest_uret_msr(struct vcpu_vmx *vmx,
 600                                   struct vmx_uret_msr *msr, u64 data)
 601 {
 602         unsigned int slot = msr - vmx->guest_uret_msrs;
 603         int ret = 0;
 604
 605         u64 old_msr_data = msr->data;
 606         msr->data = data;
 607         if (msr->load_into_hardware) {
 608                 preempt_disable();
 609                 ret = kvm_set_user_return_msr(slot, msr->data, msr->mask);
 610                 preempt_enable();
 611                 if (ret)
 612                         msr->data = old_msr_data;
 613         }
 614         return ret;
 615 }
 616
 617 #ifdef CONFIG_KEXEC_CORE
 618 static void crash_vmclear_local_loaded_vmcss(void)
 619 {
 620         int cpu = raw_smp_processor_id();
 621         struct loaded_vmcs *v;
 622
 623         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
 624                             loaded_vmcss_on_cpu_link)
 625                 vmcs_clear(v->vmcs);
 626 }
 627 #endif /* CONFIG_KEXEC_CORE */
 628
 629 static void __loaded_vmcs_clear(void *arg)
 630 {
 631         struct loaded_vmcs *loaded_vmcs = arg;
 632         int cpu = raw_smp_processor_id();
 633
 634         if (loaded_vmcs->cpu != cpu)
 635                 return; /* vcpu migration can race with cpu offline */
 636         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
 637                 per_cpu(current_vmcs, cpu) = NULL;
 638
 639         vmcs_clear(loaded_vmcs->vmcs);
 640         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
 641                 vmcs_clear(loaded_vmcs->shadow_vmcs);
 642
 643         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
 644
 645         /*
 646          * Ensure all writes to loaded_vmcs, including deleting it from its
 647          * current percpu list, complete before setting loaded_vmcs->vcpu to
 648          * -1, otherwise a different cpu can see vcpu == -1 first and add
 649          * loaded_vmcs to its percpu list before it's deleted from this cpu's
 650          * list. Pairs with the smp_rmb() in vmx_vcpu_load_vmcs().
 651          */
 652         smp_wmb();
 653
 654         loaded_vmcs->cpu = -1;
 655         loaded_vmcs->launched = 0;
 656 }
 657
 658 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
 659 {
 660         int cpu = loaded_vmcs->cpu;
 661
 662         if (cpu != -1)
 663                 smp_call_function_single(cpu,
 664                          __loaded_vmcs_clear, loaded_vmcs, 1);
 665 }
 666
 667 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
 668                                        unsigned field)
 669 {
 670         bool ret;
 671         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
 672
 673         if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) {
 674                 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS);
 675                 vmx->segment_cache.bitmask = 0;
 676         }
 677         ret = vmx->segment_cache.bitmask & mask;
 678         vmx->segment_cache.bitmask |= mask;
 679         return ret;
 680 }
 681
 682 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
 683 {
 684         u16 *p = &vmx->segment_cache.seg[seg].selector;
 685
 686         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
 687                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
 688         return *p;
 689 }
 690
 691 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
 692 {
 693         ulong *p = &vmx->segment_cache.seg[seg].base;
 694
 695         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
 696                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
 697         return *p;
 698 }
 699
 700 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
 701 {
 702         u32 *p = &vmx->segment_cache.seg[seg].limit;
 703
 704         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
 705                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
 706         return *p;
 707 }
 708
 709 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
 710 {
 711         u32 *p = &vmx->segment_cache.seg[seg].ar;
 712
 713         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
 714                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
 715         return *p;
 716 }
 717
 718 void vmx_update_exception_bitmap(struct kvm_vcpu *vcpu)
 719 {
 720         u32 eb;
 721
 722         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
 723              (1u << DB_VECTOR) | (1u << AC_VECTOR);
 724         /*
 725          * Guest access to VMware backdoor ports could legitimately
 726          * trigger #GP because of TSS I/O permission bitmap.
 727          * We intercept those #GP and allow access to them anyway
 728          * as VMware does.
 729          */
 730         if (enable_vmware_backdoor)
 731                 eb |= (1u << GP_VECTOR);
 732         if ((vcpu->guest_debug &
 733              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
 734             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
 735                 eb |= 1u << BP_VECTOR;
 736         if (to_vmx(vcpu)->rmode.vm86_active)
 737                 eb = ~0;
 738         if (!vmx_need_pf_intercept(vcpu))
 739                 eb &= ~(1u << PF_VECTOR);
 740
 741         /* When we are running a nested L2 guest and L1 specified for it a
 742          * certain exception bitmap, we must trap the same exceptions and pass
 743          * them to L1. When running L2, we will only handle the exceptions
 744          * specified above if L1 did not want them.
 745          */
 746         if (is_guest_mode(vcpu))
 747                 eb |= get_vmcs12(vcpu)->exception_bitmap;
 748         else {
 749                 int mask = 0, match = 0;
 750
 751                 if (enable_ept && (eb & (1u << PF_VECTOR))) {
 752                         /*
 753                          * If EPT is enabled, #PF is currently only intercepted
 754                          * if MAXPHYADDR is smaller on the guest than on the
 755                          * host.  In that case we only care about present,
 756                          * non-reserved faults.  For vmcs02, however, PFEC_MASK
 757                          * and PFEC_MATCH are set in prepare_vmcs02_rare.
 758                          */
 759                         mask = PFERR_PRESENT_MASK | PFERR_RSVD_MASK;
 760                         match = PFERR_PRESENT_MASK;
 761                 }
 762                 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, mask);
 763                 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, match);
 764         }
 765
 766         vmcs_write32(EXCEPTION_BITMAP, eb);
 767 }
 768
 769 /*
 770  * Check if MSR is intercepted for currently loaded MSR bitmap.
 771  */
 772 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
 773 {
 774         unsigned long *msr_bitmap;
 775         int f = sizeof(unsigned long);
 776
 777         if (!cpu_has_vmx_msr_bitmap())
 778                 return true;
 779
 780         msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
 781
 782         if (msr <= 0x1fff) {
 783                 return !!test_bit(msr, msr_bitmap + 0x800 / f);
 784         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
 785                 msr &= 0x1fff;
 786                 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
 787         }
 788
 789         return true;
 790 }
 791
 792 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
 793                 unsigned long entry, unsigned long exit)
 794 {
 795         vm_entry_controls_clearbit(vmx, entry);
 796         vm_exit_controls_clearbit(vmx, exit);
 797 }
 798
 799 int vmx_find_loadstore_msr_slot(struct vmx_msrs *m, u32 msr)
 800 {
 801         unsigned int i;
 802
 803         for (i = 0; i < m->nr; ++i) {
 804                 if (m->val[i].index == msr)
 805                         return i;
 806         }
 807         return -ENOENT;
 808 }
 809
 810 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
 811 {
 812         int i;
 813         struct msr_autoload *m = &vmx->msr_autoload;
 814
 815         switch (msr) {
 816         case MSR_EFER:
 817                 if (cpu_has_load_ia32_efer()) {
 818                         clear_atomic_switch_msr_special(vmx,
 819                                         VM_ENTRY_LOAD_IA32_EFER,
 820                                         VM_EXIT_LOAD_IA32_EFER);
 821                         return;
 822                 }
 823                 break;
 824         case MSR_CORE_PERF_GLOBAL_CTRL:
 825                 if (cpu_has_load_perf_global_ctrl()) {
 826                         clear_atomic_switch_msr_special(vmx,
 827                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
 828                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
 829                         return;
 830                 }
 831                 break;
 832         }
 833         i = vmx_find_loadstore_msr_slot(&m->guest, msr);
 834         if (i < 0)
 835                 goto skip_guest;
 836         --m->guest.nr;
 837         m->guest.val[i] = m->guest.val[m->guest.nr];
 838         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
 839
 840 skip_guest:
 841         i = vmx_find_loadstore_msr_slot(&m->host, msr);
 842         if (i < 0)
 843                 return;
 844
 845         --m->host.nr;
 846         m->host.val[i] = m->host.val[m->host.nr];
 847         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
 848 }
 849
 850 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
 851                 unsigned long entry, unsigned long exit,
 852                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
 853                 u64 guest_val, u64 host_val)
 854 {
 855         vmcs_write64(guest_val_vmcs, guest_val);
 856         if (host_val_vmcs != HOST_IA32_EFER)
 857                 vmcs_write64(host_val_vmcs, host_val);
 858         vm_entry_controls_setbit(vmx, entry);
 859         vm_exit_controls_setbit(vmx, exit);
 860 }
 861
 862 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
 863                                   u64 guest_val, u64 host_val, bool entry_only)
 864 {
 865         int i, j = 0;
 866         struct msr_autoload *m = &vmx->msr_autoload;
 867
 868         switch (msr) {
 869         case MSR_EFER:
 870                 if (cpu_has_load_ia32_efer()) {
 871                         add_atomic_switch_msr_special(vmx,
 872                                         VM_ENTRY_LOAD_IA32_EFER,
 873                                         VM_EXIT_LOAD_IA32_EFER,
 874                                         GUEST_IA32_EFER,
 875                                         HOST_IA32_EFER,
 876                                         guest_val, host_val);
 877                         return;
 878                 }
 879                 break;
 880         case MSR_CORE_PERF_GLOBAL_CTRL:
 881                 if (cpu_has_load_perf_global_ctrl()) {
 882                         add_atomic_switch_msr_special(vmx,
 883                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
 884                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
 885                                         GUEST_IA32_PERF_GLOBAL_CTRL,
 886                                         HOST_IA32_PERF_GLOBAL_CTRL,
 887                                         guest_val, host_val);
 888                         return;
 889                 }
 890                 break;
 891         case MSR_IA32_PEBS_ENABLE:
 892                 /* PEBS needs a quiescent period after being disabled (to write
 893                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
 894                  * provide that period, so a CPU could write host's record into
 895                  * guest's memory.
 896                  */
 897                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
 898         }
 899
 900         i = vmx_find_loadstore_msr_slot(&m->guest, msr);
 901         if (!entry_only)
 902                 j = vmx_find_loadstore_msr_slot(&m->host, msr);
 903
 904         if ((i < 0 && m->guest.nr == MAX_NR_LOADSTORE_MSRS) ||
 905             (j < 0 &&  m->host.nr == MAX_NR_LOADSTORE_MSRS)) {
 906                 printk_once(KERN_WARNING "Not enough msr switch entries. "
 907                                 "Can't add msr %x\n", msr);
 908                 return;
 909         }
 910         if (i < 0) {
 911                 i = m->guest.nr++;
 912                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
 913         }
 914         m->guest.val[i].index = msr;
 915         m->guest.val[i].value = guest_val;
 916
 917         if (entry_only)
 918                 return;
 919
 920         if (j < 0) {
 921                 j = m->host.nr++;
 922                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
 923         }
 924         m->host.val[j].index = msr;
 925         m->host.val[j].value = host_val;
 926 }
 927
 928 static bool update_transition_efer(struct vcpu_vmx *vmx)
 929 {
 930         u64 guest_efer = vmx->vcpu.arch.efer;
 931         u64 ignore_bits = 0;
 932         int i;
 933
 934         /* Shadow paging assumes NX to be available.  */
 935         if (!enable_ept)
 936                 guest_efer |= EFER_NX;
 937
 938         /*
 939          * LMA and LME handled by hardware; SCE meaningless outside long mode.
 940          */
 941         ignore_bits |= EFER_SCE;
 942 #ifdef CONFIG_X86_64
 943         ignore_bits |= EFER_LMA | EFER_LME;
 944         /* SCE is meaningful only in long mode on Intel */
 945         if (guest_efer & EFER_LMA)
 946                 ignore_bits &= ~(u64)EFER_SCE;
 947 #endif
 948
 949         /*
 950          * On EPT, we can't emulate NX, so we must switch EFER atomically.
 951          * On CPUs that support "load IA32_EFER", always switch EFER
 952          * atomically, since it's faster than switching it manually.
 953          */
 954         if (cpu_has_load_ia32_efer() ||
 955             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
 956                 if (!(guest_efer & EFER_LMA))
 957                         guest_efer &= ~EFER_LME;
 958                 if (guest_efer != host_efer)
 959                         add_atomic_switch_msr(vmx, MSR_EFER,
 960                                               guest_efer, host_efer, false);
 961                 else
 962                         clear_atomic_switch_msr(vmx, MSR_EFER);
 963                 return false;
 964         }
 965
 966         i = kvm_find_user_return_msr(MSR_EFER);
 967         if (i < 0)
 968                 return false;
 969
 970         clear_atomic_switch_msr(vmx, MSR_EFER);
 971
 972         guest_efer &= ~ignore_bits;
 973         guest_efer |= host_efer & ignore_bits;
 974
 975         vmx->guest_uret_msrs[i].data = guest_efer;
 976         vmx->guest_uret_msrs[i].mask = ~ignore_bits;
 977
 978         return true;
 979 }
 980
 981 #ifdef CONFIG_X86_32
 982 /*
 983  * On 32-bit kernels, VM exits still load the FS and GS bases from the
 984  * VMCS rather than the segment table.  KVM uses this helper to figure
 985  * out the current bases to poke them into the VMCS before entry.
 986  */
 987 static unsigned long segment_base(u16 selector)
 988 {
 989         struct desc_struct *table;
 990         unsigned long v;
 991
 992         if (!(selector & ~SEGMENT_RPL_MASK))
 993                 return 0;
 994
 995         table = get_current_gdt_ro();
 996
 997         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
 998                 u16 ldt_selector = kvm_read_ldt();
 999
1000                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
1001                         return 0;
1002
1003                 table = (struct desc_struct *)segment_base(ldt_selector);
1004         }
1005         v = get_desc_base(&table[selector >> 3]);
1006         return v;
1007 }
1008 #endif
1009
1010 static inline bool pt_can_write_msr(struct vcpu_vmx *vmx)
1011 {
1012         return vmx_pt_mode_is_host_guest() &&
1013                !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
1014 }
1015
1016 static inline bool pt_output_base_valid(struct kvm_vcpu *vcpu, u64 base)
1017 {
1018         /* The base must be 128-byte aligned and a legal physical address. */
1019         return kvm_vcpu_is_legal_aligned_gpa(vcpu, base, 128);
1020 }
1021
1022 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
1023 {
1024         u32 i;
1025
1026         wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1027         wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1028         wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1029         wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1030         for (i = 0; i < addr_range; i++) {
1031                 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1032                 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1033         }
1034 }
1035
1036 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
1037 {
1038         u32 i;
1039
1040         rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1041         rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1042         rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1043         rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1044         for (i = 0; i < addr_range; i++) {
1045                 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1046                 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1047         }
1048 }
1049
1050 static void pt_guest_enter(struct vcpu_vmx *vmx)
1051 {
1052         if (vmx_pt_mode_is_system())
1053                 return;
1054
1055         /*
1056          * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1057          * Save host state before VM entry.
1058          */
1059         rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1060         if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1061                 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1062                 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1063                 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1064         }
1065 }
1066
1067 static void pt_guest_exit(struct vcpu_vmx *vmx)
1068 {
1069         if (vmx_pt_mode_is_system())
1070                 return;
1071
1072         if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1073                 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1074                 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1075         }
1076
1077         /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1078         wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1079 }
1080
1081 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1082                         unsigned long fs_base, unsigned long gs_base)
1083 {
1084         if (unlikely(fs_sel != host->fs_sel)) {
1085                 if (!(fs_sel & 7))
1086                         vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1087                 else
1088                         vmcs_write16(HOST_FS_SELECTOR, 0);
1089                 host->fs_sel = fs_sel;
1090         }
1091         if (unlikely(gs_sel != host->gs_sel)) {
1092                 if (!(gs_sel & 7))
1093                         vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1094                 else
1095                         vmcs_write16(HOST_GS_SELECTOR, 0);
1096                 host->gs_sel = gs_sel;
1097         }
1098         if (unlikely(fs_base != host->fs_base)) {
1099                 vmcs_writel(HOST_FS_BASE, fs_base);
1100                 host->fs_base = fs_base;
1101         }
1102         if (unlikely(gs_base != host->gs_base)) {
1103                 vmcs_writel(HOST_GS_BASE, gs_base);
1104                 host->gs_base = gs_base;
1105         }
1106 }
1107
1108 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1109 {
1110         struct vcpu_vmx *vmx = to_vmx(vcpu);
1111         struct vmcs_host_state *host_state;
1112 #ifdef CONFIG_X86_64
1113         int cpu = raw_smp_processor_id();
1114 #endif
1115         unsigned long fs_base, gs_base;
1116         u16 fs_sel, gs_sel;
1117         int i;
1118
1119         vmx->req_immediate_exit = false;
1120
1121         /*
1122          * Note that guest MSRs to be saved/restored can also be changed
1123          * when guest state is loaded. This happens when guest transitions
1124          * to/from long-mode by setting MSR_EFER.LMA.
1125          */
1126         if (!vmx->guest_uret_msrs_loaded) {
1127                 vmx->guest_uret_msrs_loaded = true;
1128                 for (i = 0; i < kvm_nr_uret_msrs; ++i) {
1129                         if (!vmx->guest_uret_msrs[i].load_into_hardware)
1130                                 continue;
1131
1132                         kvm_set_user_return_msr(i,
1133                                                 vmx->guest_uret_msrs[i].data,
1134                                                 vmx->guest_uret_msrs[i].mask);
1135                 }
1136         }
1137
1138         if (vmx->nested.need_vmcs12_to_shadow_sync)
1139                 nested_sync_vmcs12_to_shadow(vcpu);
1140
1141         if (vmx->guest_state_loaded)
1142                 return;
1143
1144         host_state = &vmx->loaded_vmcs->host_state;
1145
1146         /*
1147          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1148          * allow segment selectors with cpl > 0 or ti == 1.
1149          */
1150         host_state->ldt_sel = kvm_read_ldt();
1151
1152 #ifdef CONFIG_X86_64
1153         savesegment(ds, host_state->ds_sel);
1154         savesegment(es, host_state->es_sel);
1155
1156         gs_base = cpu_kernelmode_gs_base(cpu);
1157         if (likely(is_64bit_mm(current->mm))) {
1158                 current_save_fsgs();
1159                 fs_sel = current->thread.fsindex;
1160                 gs_sel = current->thread.gsindex;
1161                 fs_base = current->thread.fsbase;
1162                 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
1163         } else {
1164                 savesegment(fs, fs_sel);
1165                 savesegment(gs, gs_sel);
1166                 fs_base = read_msr(MSR_FS_BASE);
1167                 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
1168         }
1169
1170         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1171 #else
1172         savesegment(fs, fs_sel);
1173         savesegment(gs, gs_sel);
1174         fs_base = segment_base(fs_sel);
1175         gs_base = segment_base(gs_sel);
1176 #endif
1177
1178         vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
1179         vmx->guest_state_loaded = true;
1180 }
1181
1182 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
1183 {
1184         struct vmcs_host_state *host_state;
1185
1186         if (!vmx->guest_state_loaded)
1187                 return;
1188
1189         host_state = &vmx->loaded_vmcs->host_state;
1190
1191         ++vmx->vcpu.stat.host_state_reload;
1192
1193 #ifdef CONFIG_X86_64
1194         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1195 #endif
1196         if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1197                 kvm_load_ldt(host_state->ldt_sel);
1198 #ifdef CONFIG_X86_64
1199                 load_gs_index(host_state->gs_sel);
1200 #else
1201                 loadsegment(gs, host_state->gs_sel);
1202 #endif
1203         }
1204         if (host_state->fs_sel & 7)
1205                 loadsegment(fs, host_state->fs_sel);
1206 #ifdef CONFIG_X86_64
1207         if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1208                 loadsegment(ds, host_state->ds_sel);
1209                 loadsegment(es, host_state->es_sel);
1210         }
1211 #endif
1212         invalidate_tss_limit();
1213 #ifdef CONFIG_X86_64
1214         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1215 #endif
1216         load_fixmap_gdt(raw_smp_processor_id());
1217         vmx->guest_state_loaded = false;
1218         vmx->guest_uret_msrs_loaded = false;
1219 }
1220
1221 #ifdef CONFIG_X86_64
1222 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
1223 {
1224         preempt_disable();
1225         if (vmx->guest_state_loaded)
1226                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1227         preempt_enable();
1228         return vmx->msr_guest_kernel_gs_base;
1229 }
1230
1231 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1232 {
1233         preempt_disable();
1234         if (vmx->guest_state_loaded)
1235                 wrmsrl(MSR_KERNEL_GS_BASE, data);
1236         preempt_enable();
1237         vmx->msr_guest_kernel_gs_base = data;
1238 }
1239 #endif
1240
1241 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu,
1242                         struct loaded_vmcs *buddy)
1243 {
1244         struct vcpu_vmx *vmx = to_vmx(vcpu);
1245         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
1246         struct vmcs *prev;
1247
1248         if (!already_loaded) {
1249                 loaded_vmcs_clear(vmx->loaded_vmcs);
1250                 local_irq_disable();
1251
1252                 /*
1253                  * Ensure loaded_vmcs->cpu is read before adding loaded_vmcs to
1254                  * this cpu's percpu list, otherwise it may not yet be deleted
1255                  * from its previous cpu's percpu list.  Pairs with the
1256                  * smb_wmb() in __loaded_vmcs_clear().
1257                  */
1258                 smp_rmb();
1259
1260                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1261                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1262                 local_irq_enable();
1263         }
1264
1265         prev = per_cpu(current_vmcs, cpu);
1266         if (prev != vmx->loaded_vmcs->vmcs) {
1267                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1268                 vmcs_load(vmx->loaded_vmcs->vmcs);
1269
1270                 /*
1271                  * No indirect branch prediction barrier needed when switching
1272                  * the active VMCS within a guest, e.g. on nested VM-Enter.
1273                  * The L1 VMM can protect itself with retpolines, IBPB or IBRS.
1274                  */
1275                 if (!buddy || WARN_ON_ONCE(buddy->vmcs != prev))
1276                         indirect_branch_prediction_barrier();
1277         }
1278
1279         if (!already_loaded) {
1280                 void *gdt = get_current_gdt_ro();
1281                 unsigned long sysenter_esp;
1282
1283                 /*
1284                  * Flush all EPTP/VPID contexts, the new pCPU may have stale
1285                  * TLB entries from its previous association with the vCPU.
1286                  */
1287                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1288
1289                 /*
1290                  * Linux uses per-cpu TSS and GDT, so set these when switching
1291                  * processors.  See 22.2.4.
1292                  */
1293                 vmcs_writel(HOST_TR_BASE,
1294                             (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
1295                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
1296
1297                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1298                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1299
1300                 vmx->loaded_vmcs->cpu = cpu;
1301         }
1302 }
1303
1304 /*
1305  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1306  * vcpu mutex is already taken.
1307  */
1308 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1309 {
1310         struct vcpu_vmx *vmx = to_vmx(vcpu);
1311
1312         vmx_vcpu_load_vmcs(vcpu, cpu, NULL);
1313
1314         vmx_vcpu_pi_load(vcpu, cpu);
1315
1316         vmx->host_debugctlmsr = get_debugctlmsr();
1317 }
1318
1319 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1320 {
1321         vmx_vcpu_pi_put(vcpu);
1322
1323         vmx_prepare_switch_to_host(to_vmx(vcpu));
1324 }
1325
1326 bool vmx_emulation_required(struct kvm_vcpu *vcpu)
1327 {
1328         return emulate_invalid_guest_state && !vmx_guest_state_valid(vcpu);
1329 }
1330
1331 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1332 {
1333         struct vcpu_vmx *vmx = to_vmx(vcpu);
1334         unsigned long rflags, save_rflags;
1335
1336         if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) {
1337                 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1338                 rflags = vmcs_readl(GUEST_RFLAGS);
1339                 if (vmx->rmode.vm86_active) {
1340                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1341                         save_rflags = vmx->rmode.save_rflags;
1342                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1343                 }
1344                 vmx->rflags = rflags;
1345         }
1346         return vmx->rflags;
1347 }
1348
1349 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1350 {
1351         struct vcpu_vmx *vmx = to_vmx(vcpu);
1352         unsigned long old_rflags;
1353
1354         if (is_unrestricted_guest(vcpu)) {
1355                 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1356                 vmx->rflags = rflags;
1357                 vmcs_writel(GUEST_RFLAGS, rflags);
1358                 return;
1359         }
1360
1361         old_rflags = vmx_get_rflags(vcpu);
1362         vmx->rflags = rflags;
1363         if (vmx->rmode.vm86_active) {
1364                 vmx->rmode.save_rflags = rflags;
1365                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1366         }
1367         vmcs_writel(GUEST_RFLAGS, rflags);
1368
1369         if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM)
1370                 vmx->emulation_required = vmx_emulation_required(vcpu);
1371 }
1372
1373 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1374 {
1375         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1376         int ret = 0;
1377
1378         if (interruptibility & GUEST_INTR_STATE_STI)
1379                 ret |= KVM_X86_SHADOW_INT_STI;
1380         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1381                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1382
1383         return ret;
1384 }
1385
1386 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1387 {
1388         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1389         u32 interruptibility = interruptibility_old;
1390
1391         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1392
1393         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1394                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1395         else if (mask & KVM_X86_SHADOW_INT_STI)
1396                 interruptibility |= GUEST_INTR_STATE_STI;
1397
1398         if ((interruptibility != interruptibility_old))
1399                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1400 }
1401
1402 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1403 {
1404         struct vcpu_vmx *vmx = to_vmx(vcpu);
1405         unsigned long value;
1406
1407         /*
1408          * Any MSR write that attempts to change bits marked reserved will
1409          * case a #GP fault.
1410          */
1411         if (data & vmx->pt_desc.ctl_bitmask)
1412                 return 1;
1413
1414         /*
1415          * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1416          * result in a #GP unless the same write also clears TraceEn.
1417          */
1418         if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1419                 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1420                 return 1;
1421
1422         /*
1423          * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1424          * and FabricEn would cause #GP, if
1425          * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1426          */
1427         if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1428                 !(data & RTIT_CTL_FABRIC_EN) &&
1429                 !intel_pt_validate_cap(vmx->pt_desc.caps,
1430                                         PT_CAP_single_range_output))
1431                 return 1;
1432
1433         /*
1434          * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1435          * utilize encodings marked reserved will cause a #GP fault.
1436          */
1437         value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1438         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1439                         !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1440                         RTIT_CTL_MTC_RANGE_OFFSET, &value))
1441                 return 1;
1442         value = intel_pt_validate_cap(vmx->pt_desc.caps,
1443                                                 PT_CAP_cycle_thresholds);
1444         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1445                         !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1446                         RTIT_CTL_CYC_THRESH_OFFSET, &value))
1447                 return 1;
1448         value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1449         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1450                         !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1451                         RTIT_CTL_PSB_FREQ_OFFSET, &value))
1452                 return 1;
1453
1454         /*
1455          * If ADDRx_CFG is reserved or the encodings is >2 will
1456          * cause a #GP fault.
1457          */
1458         value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1459         if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
1460                 return 1;
1461         value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1462         if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
1463                 return 1;
1464         value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1465         if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
1466                 return 1;
1467         value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1468         if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
1469                 return 1;
1470
1471         return 0;
1472 }
1473
1474 static bool vmx_can_emulate_instruction(struct kvm_vcpu *vcpu, void *insn, int insn_len)
1475 {
1476         /*
1477          * Emulation of instructions in SGX enclaves is impossible as RIP does
1478          * not point  tthe failing instruction, and even if it did, the code
1479          * stream is inaccessible.  Inject #UD instead of exiting to userspace
1480          * so that guest userspace can't DoS the guest simply by triggering
1481          * emulation (enclaves are CPL3 only).
1482          */
1483         if (to_vmx(vcpu)->exit_reason.enclave_mode) {
1484                 kvm_queue_exception(vcpu, UD_VECTOR);
1485                 return false;
1486         }
1487         return true;
1488 }
1489
1490 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
1491 {
1492         union vmx_exit_reason exit_reason = to_vmx(vcpu)->exit_reason;
1493         unsigned long rip, orig_rip;
1494         u32 instr_len;
1495
1496         /*
1497          * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
1498          * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
1499          * set when EPT misconfig occurs.  In practice, real hardware updates
1500          * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
1501          * (namely Hyper-V) don't set it due to it being undefined behavior,
1502          * i.e. we end up advancing IP with some random value.
1503          */
1504         if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
1505             exit_reason.basic != EXIT_REASON_EPT_MISCONFIG) {
1506                 instr_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1507
1508                 /*
1509                  * Emulating an enclave's instructions isn't supported as KVM
1510                  * cannot access the enclave's memory or its true RIP, e.g. the
1511                  * vmcs.GUEST_RIP points at the exit point of the enclave, not
1512                  * the RIP that actually triggered the VM-Exit.  But, because
1513                  * most instructions that cause VM-Exit will #UD in an enclave,
1514                  * most instruction-based VM-Exits simply do not occur.
1515                  *
1516                  * There are a few exceptions, notably the debug instructions
1517                  * INT1ICEBRK and INT3, as they are allowed in debug enclaves
1518                  * and generate #DB/#BP as expected, which KVM might intercept.
1519                  * But again, the CPU does the dirty work and saves an instr
1520                  * length of zero so VMMs don't shoot themselves in the foot.
1521                  * WARN if KVM tries to skip a non-zero length instruction on
1522                  * a VM-Exit from an enclave.
1523                  */
1524                 if (!instr_len)
1525                         goto rip_updated;
1526
1527                 WARN(exit_reason.enclave_mode,
1528                      "KVM: skipping instruction after SGX enclave VM-Exit");
1529
1530                 orig_rip = kvm_rip_read(vcpu);
1531                 rip = orig_rip + instr_len;
1532 #ifdef CONFIG_X86_64
1533                 /*
1534                  * We need to mask out the high 32 bits of RIP if not in 64-bit
1535                  * mode, but just finding out that we are in 64-bit mode is
1536                  * quite expensive.  Only do it if there was a carry.
1537                  */
1538                 if (unlikely(((rip ^ orig_rip) >> 31) == 3) && !is_64_bit_mode(vcpu))
1539                         rip = (u32)rip;
1540 #endif
1541                 kvm_rip_write(vcpu, rip);
1542         } else {
1543                 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
1544                         return 0;
1545         }
1546
1547 rip_updated:
1548         /* skipping an emulated instruction also counts */
1549         vmx_set_interrupt_shadow(vcpu, 0);
1550
1551         return 1;
1552 }
1553
1554 /*
1555  * Recognizes a pending MTF VM-exit and records the nested state for later
1556  * delivery.
1557  */
1558 static void vmx_update_emulated_instruction(struct kvm_vcpu *vcpu)
1559 {
1560         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1561         struct vcpu_vmx *vmx = to_vmx(vcpu);
1562
1563         if (!is_guest_mode(vcpu))
1564                 return;
1565
1566         /*
1567          * Per the SDM, MTF takes priority over debug-trap exceptions besides
1568          * T-bit traps. As instruction emulation is completed (i.e. at the
1569          * instruction boundary), any #DB exception pending delivery must be a
1570          * debug-trap. Record the pending MTF state to be delivered in
1571          * vmx_check_nested_events().
1572          */
1573         if (nested_cpu_has_mtf(vmcs12) &&
1574             (!vcpu->arch.exception.pending ||
1575              vcpu->arch.exception.nr == DB_VECTOR))
1576                 vmx->nested.mtf_pending = true;
1577         else
1578                 vmx->nested.mtf_pending = false;
1579 }
1580
1581 static int vmx_skip_emulated_instruction(struct kvm_vcpu *vcpu)
1582 {
1583         vmx_update_emulated_instruction(vcpu);
1584         return skip_emulated_instruction(vcpu);
1585 }
1586
1587 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1588 {
1589         /*
1590          * Ensure that we clear the HLT state in the VMCS.  We don't need to
1591          * explicitly skip the instruction because if the HLT state is set,
1592          * then the instruction is already executing and RIP has already been
1593          * advanced.
1594          */
1595         if (kvm_hlt_in_guest(vcpu->kvm) &&
1596                         vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1597                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1598 }
1599
1600 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
1601 {
1602         struct vcpu_vmx *vmx = to_vmx(vcpu);
1603         unsigned nr = vcpu->arch.exception.nr;
1604         bool has_error_code = vcpu->arch.exception.has_error_code;
1605         u32 error_code = vcpu->arch.exception.error_code;
1606         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1607
1608         kvm_deliver_exception_payload(vcpu);
1609
1610         if (has_error_code) {
1611                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1612                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1613         }
1614
1615         if (vmx->rmode.vm86_active) {
1616                 int inc_eip = 0;
1617                 if (kvm_exception_is_soft(nr))
1618                         inc_eip = vcpu->arch.event_exit_inst_len;
1619                 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
1620                 return;
1621         }
1622
1623         WARN_ON_ONCE(vmx->emulation_required);
1624
1625         if (kvm_exception_is_soft(nr)) {
1626                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1627                              vmx->vcpu.arch.event_exit_inst_len);
1628                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1629         } else
1630                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1631
1632         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1633
1634         vmx_clear_hlt(vcpu);
1635 }
1636
1637 static void vmx_setup_uret_msr(struct vcpu_vmx *vmx, unsigned int msr,
1638                                bool load_into_hardware)
1639 {
1640         struct vmx_uret_msr *uret_msr;
1641
1642         uret_msr = vmx_find_uret_msr(vmx, msr);
1643         if (!uret_msr)
1644                 return;
1645
1646         uret_msr->load_into_hardware = load_into_hardware;
1647 }
1648
1649 /*
1650  * Configuring user return MSRs to automatically save, load, and restore MSRs
1651  * that need to be shoved into hardware when running the guest.  Note, omitting
1652  * an MSR here does _NOT_ mean it's not emulated, only that it will not be
1653  * loaded into hardware when running the guest.
1654  */
1655 static void vmx_setup_uret_msrs(struct vcpu_vmx *vmx)
1656 {
1657 #ifdef CONFIG_X86_64
1658         bool load_syscall_msrs;
1659
1660         /*
1661          * The SYSCALL MSRs are only needed on long mode guests, and only
1662          * when EFER.SCE is set.
1663          */
1664         load_syscall_msrs = is_long_mode(&vmx->vcpu) &&
1665                             (vmx->vcpu.arch.efer & EFER_SCE);
1666
1667         vmx_setup_uret_msr(vmx, MSR_STAR, load_syscall_msrs);
1668         vmx_setup_uret_msr(vmx, MSR_LSTAR, load_syscall_msrs);
1669         vmx_setup_uret_msr(vmx, MSR_SYSCALL_MASK, load_syscall_msrs);
1670 #endif
1671         vmx_setup_uret_msr(vmx, MSR_EFER, update_transition_efer(vmx));
1672
1673         vmx_setup_uret_msr(vmx, MSR_TSC_AUX,
1674                            guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP) ||
1675                            guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDPID));
1676
1677         /*
1678          * hle=0, rtm=0, tsx_ctrl=1 can be found with some combinations of new
1679          * kernel and old userspace.  If those guests run on a tsx=off host, do
1680          * allow guests to use TSX_CTRL, but don't change the value in hardware
1681          * so that TSX remains always disabled.
1682          */
1683         vmx_setup_uret_msr(vmx, MSR_IA32_TSX_CTRL, boot_cpu_has(X86_FEATURE_RTM));
1684
1685         /*
1686          * The set of MSRs to load may have changed, reload MSRs before the
1687          * next VM-Enter.
1688          */
1689         vmx->guest_uret_msrs_loaded = false;
1690 }
1691
1692 u64 vmx_get_l2_tsc_offset(struct kvm_vcpu *vcpu)
1693 {
1694         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1695
1696         if (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETTING))
1697                 return vmcs12->tsc_offset;
1698
1699         return 0;
1700 }
1701
1702 u64 vmx_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu)
1703 {
1704         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1705
1706         if (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETTING) &&
1707             nested_cpu_has2(vmcs12, SECONDARY_EXEC_TSC_SCALING))
1708                 return vmcs12->tsc_multiplier;
1709
1710         return kvm_default_tsc_scaling_ratio;
1711 }
1712
1713 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1714 {
1715         vmcs_write64(TSC_OFFSET, offset);
1716 }
1717
1718 static void vmx_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 multiplier)
1719 {
1720         vmcs_write64(TSC_MULTIPLIER, multiplier);
1721 }
1722
1723 /*
1724  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1725  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1726  * all guests if the "nested" module option is off, and can also be disabled
1727  * for a single guest by disabling its VMX cpuid bit.
1728  */
1729 bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1730 {
1731         return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
1732 }
1733
1734 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1735                                                  uint64_t val)
1736 {
1737         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
1738
1739         return !(val & ~valid_bits);
1740 }
1741
1742 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
1743 {
1744         switch (msr->index) {
1745         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1746                 if (!nested)
1747                         return 1;
1748                 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1749         case MSR_IA32_PERF_CAPABILITIES:
1750                 msr->data = vmx_get_perf_capabilities();
1751                 return 0;
1752         default:
1753                 return KVM_MSR_RET_INVALID;
1754         }
1755 }
1756
1757 /*
1758  * Reads an msr value (of 'msr_index') into 'pdata'.
1759  * Returns 0 on success, non-0 otherwise.
1760  * Assumes vcpu_load() was already called.
1761  */
1762 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1763 {
1764         struct vcpu_vmx *vmx = to_vmx(vcpu);
1765         struct vmx_uret_msr *msr;
1766         u32 index;
1767
1768         switch (msr_info->index) {
1769 #ifdef CONFIG_X86_64
1770         case MSR_FS_BASE:
1771                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
1772                 break;
1773         case MSR_GS_BASE:
1774                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
1775                 break;
1776         case MSR_KERNEL_GS_BASE:
1777                 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
1778                 break;
1779 #endif
1780         case MSR_EFER:
1781                 return kvm_get_msr_common(vcpu, msr_info);
1782         case MSR_IA32_TSX_CTRL:
1783                 if (!msr_info->host_initiated &&
1784                     !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
1785                         return 1;
1786                 goto find_uret_msr;
1787         case MSR_IA32_UMWAIT_CONTROL:
1788                 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1789                         return 1;
1790
1791                 msr_info->data = vmx->msr_ia32_umwait_control;
1792                 break;
1793         case MSR_IA32_SPEC_CTRL:
1794                 if (!msr_info->host_initiated &&
1795                     !guest_has_spec_ctrl_msr(vcpu))
1796                         return 1;
1797
1798                 msr_info->data = to_vmx(vcpu)->spec_ctrl;
1799                 break;
1800         case MSR_IA32_SYSENTER_CS:
1801                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
1802                 break;
1803         case MSR_IA32_SYSENTER_EIP:
1804                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
1805                 break;
1806         case MSR_IA32_SYSENTER_ESP:
1807                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
1808                 break;
1809         case MSR_IA32_BNDCFGS:
1810                 if (!kvm_mpx_supported() ||
1811                     (!msr_info->host_initiated &&
1812                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1813                         return 1;
1814                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
1815                 break;
1816         case MSR_IA32_MCG_EXT_CTL:
1817                 if (!msr_info->host_initiated &&
1818                     !(vmx->msr_ia32_feature_control &
1819                       FEAT_CTL_LMCE_ENABLED))
1820                         return 1;
1821                 msr_info->data = vcpu->arch.mcg_ext_ctl;
1822                 break;
1823         case MSR_IA32_FEAT_CTL:
1824                 msr_info->data = vmx->msr_ia32_feature_control;
1825                 break;
1826         case MSR_IA32_SGXLEPUBKEYHASH0 ... MSR_IA32_SGXLEPUBKEYHASH3:
1827                 if (!msr_info->host_initiated &&
1828                     !guest_cpuid_has(vcpu, X86_FEATURE_SGX_LC))
1829                         return 1;
1830                 msr_info->data = to_vmx(vcpu)->msr_ia32_sgxlepubkeyhash
1831                         [msr_info->index - MSR_IA32_SGXLEPUBKEYHASH0];
1832                 break;
1833         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1834                 if (!nested_vmx_allowed(vcpu))
1835                         return 1;
1836                 if (vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1837                                     &msr_info->data))
1838                         return 1;
1839                 /*
1840                  * Enlightened VMCS v1 doesn't have certain VMCS fields but
1841                  * instead of just ignoring the features, different Hyper-V
1842                  * versions are either trying to use them and fail or do some
1843                  * sanity checking and refuse to boot. Filter all unsupported
1844                  * features out.
1845                  */
1846                 if (!msr_info->host_initiated &&
1847                     vmx->nested.enlightened_vmcs_enabled)
1848                         nested_evmcs_filter_control_msr(msr_info->index,
1849                                                         &msr_info->data);
1850                 break;
1851         case MSR_IA32_RTIT_CTL:
1852                 if (!vmx_pt_mode_is_host_guest())
1853                         return 1;
1854                 msr_info->data = vmx->pt_desc.guest.ctl;
1855                 break;
1856         case MSR_IA32_RTIT_STATUS:
1857                 if (!vmx_pt_mode_is_host_guest())
1858                         return 1;
1859                 msr_info->data = vmx->pt_desc.guest.status;
1860                 break;
1861         case MSR_IA32_RTIT_CR3_MATCH:
1862                 if (!vmx_pt_mode_is_host_guest() ||
1863                         !intel_pt_validate_cap(vmx->pt_desc.caps,
1864                                                 PT_CAP_cr3_filtering))
1865                         return 1;
1866                 msr_info->data = vmx->pt_desc.guest.cr3_match;
1867                 break;
1868         case MSR_IA32_RTIT_OUTPUT_BASE:
1869                 if (!vmx_pt_mode_is_host_guest() ||
1870                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1871                                         PT_CAP_topa_output) &&
1872                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1873                                         PT_CAP_single_range_output)))
1874                         return 1;
1875                 msr_info->data = vmx->pt_desc.guest.output_base;
1876                 break;
1877         case MSR_IA32_RTIT_OUTPUT_MASK:
1878                 if (!vmx_pt_mode_is_host_guest() ||
1879                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1880                                         PT_CAP_topa_output) &&
1881                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1882                                         PT_CAP_single_range_output)))
1883                         return 1;
1884                 msr_info->data = vmx->pt_desc.guest.output_mask;
1885                 break;
1886         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1887                 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1888                 if (!vmx_pt_mode_is_host_guest() ||
1889                         (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
1890                                         PT_CAP_num_address_ranges)))
1891                         return 1;
1892                 if (index % 2)
1893                         msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1894                 else
1895                         msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1896                 break;
1897         case MSR_IA32_DEBUGCTLMSR:
1898                 msr_info->data = vmcs_read64(GUEST_IA32_DEBUGCTL);
1899                 break;
1900         default:
1901         find_uret_msr:
1902                 msr = vmx_find_uret_msr(vmx, msr_info->index);
1903                 if (msr) {
1904                         msr_info->data = msr->data;
1905                         break;
1906                 }
1907                 return kvm_get_msr_common(vcpu, msr_info);
1908         }
1909
1910         return 0;
1911 }
1912
1913 static u64 nested_vmx_truncate_sysenter_addr(struct kvm_vcpu *vcpu,
1914                                                     u64 data)
1915 {
1916 #ifdef CONFIG_X86_64
1917         if (!guest_cpuid_has(vcpu, X86_FEATURE_LM))
1918                 return (u32)data;
1919 #endif
1920         return (unsigned long)data;
1921 }
1922
1923 static u64 vcpu_supported_debugctl(struct kvm_vcpu *vcpu)
1924 {
1925         u64 debugctl = vmx_supported_debugctl();
1926
1927         if (!intel_pmu_lbr_is_enabled(vcpu))
1928                 debugctl &= ~DEBUGCTLMSR_LBR_MASK;
1929
1930         if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT))
1931                 debugctl &= ~DEBUGCTLMSR_BUS_LOCK_DETECT;
1932
1933         return debugctl;
1934 }
1935
1936 /*
1937  * Writes msr value into the appropriate "register".
1938  * Returns 0 on success, non-0 otherwise.
1939  * Assumes vcpu_load() was already called.
1940  */
1941 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1942 {
1943         struct vcpu_vmx *vmx = to_vmx(vcpu);
1944         struct vmx_uret_msr *msr;
1945         int ret = 0;
1946         u32 msr_index = msr_info->index;
1947         u64 data = msr_info->data;
1948         u32 index;
1949
1950         switch (msr_index) {
1951         case MSR_EFER:
1952                 ret = kvm_set_msr_common(vcpu, msr_info);
1953                 break;
1954 #ifdef CONFIG_X86_64
1955         case MSR_FS_BASE:
1956                 vmx_segment_cache_clear(vmx);
1957                 vmcs_writel(GUEST_FS_BASE, data);
1958                 break;
1959         case MSR_GS_BASE:
1960                 vmx_segment_cache_clear(vmx);
1961                 vmcs_writel(GUEST_GS_BASE, data);
1962                 break;
1963         case MSR_KERNEL_GS_BASE:
1964                 vmx_write_guest_kernel_gs_base(vmx, data);
1965                 break;
1966 #endif
1967         case MSR_IA32_SYSENTER_CS:
1968                 if (is_guest_mode(vcpu))
1969                         get_vmcs12(vcpu)->guest_sysenter_cs = data;
1970                 vmcs_write32(GUEST_SYSENTER_CS, data);
1971                 break;
1972         case MSR_IA32_SYSENTER_EIP:
1973                 if (is_guest_mode(vcpu)) {
1974                         data = nested_vmx_truncate_sysenter_addr(vcpu, data);
1975                         get_vmcs12(vcpu)->guest_sysenter_eip = data;
1976                 }
1977                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1978                 break;
1979         case MSR_IA32_SYSENTER_ESP:
1980                 if (is_guest_mode(vcpu)) {
1981                         data = nested_vmx_truncate_sysenter_addr(vcpu, data);
1982                         get_vmcs12(vcpu)->guest_sysenter_esp = data;
1983                 }
1984                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1985                 break;
1986         case MSR_IA32_DEBUGCTLMSR: {
1987                 u64 invalid = data & ~vcpu_supported_debugctl(vcpu);
1988                 if (invalid & (DEBUGCTLMSR_BTF|DEBUGCTLMSR_LBR)) {
1989                         if (report_ignored_msrs)
1990                                 vcpu_unimpl(vcpu, "%s: BTF|LBR in IA32_DEBUGCTLMSR 0x%llx, nop\n",
1991                                             __func__, data);
1992                         data &= ~(DEBUGCTLMSR_BTF|DEBUGCTLMSR_LBR);
1993                         invalid &= ~(DEBUGCTLMSR_BTF|DEBUGCTLMSR_LBR);
1994                 }
1995
1996                 if (invalid)
1997                         return 1;
1998
1999                 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
2000                                                 VM_EXIT_SAVE_DEBUG_CONTROLS)
2001                         get_vmcs12(vcpu)->guest_ia32_debugctl = data;
2002
2003                 vmcs_write64(GUEST_IA32_DEBUGCTL, data);
2004                 if (intel_pmu_lbr_is_enabled(vcpu) && !to_vmx(vcpu)->lbr_desc.event &&
2005                     (data & DEBUGCTLMSR_LBR))
2006                         intel_pmu_create_guest_lbr_event(vcpu);
2007                 return 0;
2008         }
2009         case MSR_IA32_BNDCFGS:
2010                 if (!kvm_mpx_supported() ||
2011                     (!msr_info->host_initiated &&
2012                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
2013                         return 1;
2014                 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
2015                     (data & MSR_IA32_BNDCFGS_RSVD))
2016                         return 1;
2017                 vmcs_write64(GUEST_BNDCFGS, data);
2018                 break;
2019         case MSR_IA32_UMWAIT_CONTROL:
2020                 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
2021                         return 1;
2022
2023                 /* The reserved bit 1 and non-32 bit [63:32] should be zero */
2024                 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
2025                         return 1;
2026
2027                 vmx->msr_ia32_umwait_control = data;
2028                 break;
2029         case MSR_IA32_SPEC_CTRL:
2030                 if (!msr_info->host_initiated &&
2031                     !guest_has_spec_ctrl_msr(vcpu))
2032                         return 1;
2033
2034                 if (kvm_spec_ctrl_test_value(data))
2035                         return 1;
2036
2037                 vmx->spec_ctrl = data;
2038                 if (!data)
2039                         break;
2040
2041                 /*
2042                  * For non-nested:
2043                  * When it's written (to non-zero) for the first time, pass
2044                  * it through.
2045                  *
2046                  * For nested:
2047                  * The handling of the MSR bitmap for L2 guests is done in
2048                  * nested_vmx_prepare_msr_bitmap. We should not touch the
2049                  * vmcs02.msr_bitmap here since it gets completely overwritten
2050                  * in the merging. We update the vmcs01 here for L1 as well
2051                  * since it will end up touching the MSR anyway now.
2052                  */
2053                 vmx_disable_intercept_for_msr(vcpu,
2054                                               MSR_IA32_SPEC_CTRL,
2055                                               MSR_TYPE_RW);
2056                 break;
2057         case MSR_IA32_TSX_CTRL:
2058                 if (!msr_info->host_initiated &&
2059                     !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
2060                         return 1;
2061                 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR))
2062                         return 1;
2063                 goto find_uret_msr;
2064         case MSR_IA32_PRED_CMD:
2065                 if (!msr_info->host_initiated &&
2066                     !guest_has_pred_cmd_msr(vcpu))
2067                         return 1;
2068
2069                 if (data & ~PRED_CMD_IBPB)
2070                         return 1;
2071                 if (!boot_cpu_has(X86_FEATURE_IBPB))
2072                         return 1;
2073                 if (!data)
2074                         break;
2075
2076                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2077
2078                 /*
2079                  * For non-nested:
2080                  * When it's written (to non-zero) for the first time, pass
2081                  * it through.
2082                  *
2083                  * For nested:
2084                  * The handling of the MSR bitmap for L2 guests is done in
2085                  * nested_vmx_prepare_msr_bitmap. We should not touch the
2086                  * vmcs02.msr_bitmap here since it gets completely overwritten
2087                  * in the merging.
2088                  */
2089                 vmx_disable_intercept_for_msr(vcpu, MSR_IA32_PRED_CMD, MSR_TYPE_W);
2090                 break;
2091         case MSR_IA32_CR_PAT:
2092                 if (!kvm_pat_valid(data))
2093                         return 1;
2094
2095                 if (is_guest_mode(vcpu) &&
2096                     get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
2097                         get_vmcs12(vcpu)->guest_ia32_pat = data;
2098
2099                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2100                         vmcs_write64(GUEST_IA32_PAT, data);
2101                         vcpu->arch.pat = data;
2102                         break;
2103                 }
2104                 ret = kvm_set_msr_common(vcpu, msr_info);
2105                 break;
2106         case MSR_IA32_TSC_ADJUST:
2107                 ret = kvm_set_msr_common(vcpu, msr_info);
2108                 break;
2109         case MSR_IA32_MCG_EXT_CTL:
2110                 if ((!msr_info->host_initiated &&
2111                      !(to_vmx(vcpu)->msr_ia32_feature_control &
2112                        FEAT_CTL_LMCE_ENABLED)) ||
2113                     (data & ~MCG_EXT_CTL_LMCE_EN))
2114                         return 1;
2115                 vcpu->arch.mcg_ext_ctl = data;
2116                 break;
2117         case MSR_IA32_FEAT_CTL:
2118                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
2119                     (to_vmx(vcpu)->msr_ia32_feature_control &
2120                      FEAT_CTL_LOCKED && !msr_info->host_initiated))
2121                         return 1;
2122                 vmx->msr_ia32_feature_control = data;
2123                 if (msr_info->host_initiated && data == 0)
2124                         vmx_leave_nested(vcpu);
2125
2126                 /* SGX may be enabled/disabled by guest's firmware */
2127                 vmx_write_encls_bitmap(vcpu, NULL);
2128                 break;
2129         case MSR_IA32_SGXLEPUBKEYHASH0 ... MSR_IA32_SGXLEPUBKEYHASH3:
2130                 /*
2131                  * On real hardware, the LE hash MSRs are writable before
2132                  * the firmware sets bit 0 in MSR 0x7a ("activating" SGX),
2133                  * at which point SGX related bits in IA32_FEATURE_CONTROL
2134                  * become writable.
2135                  *
2136                  * KVM does not emulate SGX activation for simplicity, so
2137                  * allow writes to the LE hash MSRs if IA32_FEATURE_CONTROL
2138                  * is unlocked.  This is technically not architectural
2139                  * behavior, but it's close enough.
2140                  */
2141                 if (!msr_info->host_initiated &&
2142                     (!guest_cpuid_has(vcpu, X86_FEATURE_SGX_LC) ||
2143                     ((vmx->msr_ia32_feature_control & FEAT_CTL_LOCKED) &&
2144                     !(vmx->msr_ia32_feature_control & FEAT_CTL_SGX_LC_ENABLED))))
2145                         return 1;
2146                 vmx->msr_ia32_sgxlepubkeyhash
2147                         [msr_index - MSR_IA32_SGXLEPUBKEYHASH0] = data;
2148                 break;
2149         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2150                 if (!msr_info->host_initiated)
2151                         return 1; /* they are read-only */
2152                 if (!nested_vmx_allowed(vcpu))
2153                         return 1;
2154                 return vmx_set_vmx_msr(vcpu, msr_index, data);
2155         case MSR_IA32_RTIT_CTL:
2156                 if (!vmx_pt_mode_is_host_guest() ||
2157                         vmx_rtit_ctl_check(vcpu, data) ||
2158                         vmx->nested.vmxon)
2159                         return 1;
2160                 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
2161                 vmx->pt_desc.guest.ctl = data;
2162                 pt_update_intercept_for_msr(vcpu);
2163                 break;
2164         case MSR_IA32_RTIT_STATUS:
2165                 if (!pt_can_write_msr(vmx))
2166                         return 1;
2167                 if (data & MSR_IA32_RTIT_STATUS_MASK)
2168                         return 1;
2169                 vmx->pt_desc.guest.status = data;
2170                 break;
2171         case MSR_IA32_RTIT_CR3_MATCH:
2172                 if (!pt_can_write_msr(vmx))
2173                         return 1;
2174                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2175                                            PT_CAP_cr3_filtering))
2176                         return 1;
2177                 vmx->pt_desc.guest.cr3_match = data;
2178                 break;
2179         case MSR_IA32_RTIT_OUTPUT_BASE:
2180                 if (!pt_can_write_msr(vmx))
2181                         return 1;
2182                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2183                                            PT_CAP_topa_output) &&
2184                     !intel_pt_validate_cap(vmx->pt_desc.caps,
2185                                            PT_CAP_single_range_output))
2186                         return 1;
2187                 if (!pt_output_base_valid(vcpu, data))
2188                         return 1;
2189                 vmx->pt_desc.guest.output_base = data;
2190                 break;
2191         case MSR_IA32_RTIT_OUTPUT_MASK:
2192                 if (!pt_can_write_msr(vmx))
2193                         return 1;
2194                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2195                                            PT_CAP_topa_output) &&
2196                     !intel_pt_validate_cap(vmx->pt_desc.caps,
2197                                            PT_CAP_single_range_output))
2198                         return 1;
2199                 vmx->pt_desc.guest.output_mask = data;
2200                 break;
2201         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2202                 if (!pt_can_write_msr(vmx))
2203                         return 1;
2204                 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2205                 if (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
2206                                                        PT_CAP_num_address_ranges))
2207                         return 1;
2208                 if (is_noncanonical_address(data, vcpu))
2209                         return 1;
2210                 if (index % 2)
2211                         vmx->pt_desc.guest.addr_b[index / 2] = data;
2212                 else
2213                         vmx->pt_desc.guest.addr_a[index / 2] = data;
2214                 break;
2215         case MSR_IA32_PERF_CAPABILITIES:
2216                 if (data && !vcpu_to_pmu(vcpu)->version)
2217                         return 1;
2218                 if (data & PMU_CAP_LBR_FMT) {
2219                         if ((data & PMU_CAP_LBR_FMT) !=
2220                             (vmx_get_perf_capabilities() & PMU_CAP_LBR_FMT))
2221                                 return 1;
2222                         if (!intel_pmu_lbr_is_compatible(vcpu))
2223                                 return 1;
2224                 }
2225                 ret = kvm_set_msr_common(vcpu, msr_info);
2226                 break;
2227
2228         default:
2229         find_uret_msr:
2230                 msr = vmx_find_uret_msr(vmx, msr_index);
2231                 if (msr)
2232                         ret = vmx_set_guest_uret_msr(vmx, msr, data);
2233                 else
2234                         ret = kvm_set_msr_common(vcpu, msr_info);
2235         }
2236
2237         return ret;
2238 }
2239
2240 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2241 {
2242         unsigned long guest_owned_bits;
2243
2244         kvm_register_mark_available(vcpu, reg);
2245
2246         switch (reg) {
2247         case VCPU_REGS_RSP:
2248                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2249                 break;
2250         case VCPU_REGS_RIP:
2251                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2252                 break;
2253         case VCPU_EXREG_PDPTR:
2254                 if (enable_ept)
2255                         ept_save_pdptrs(vcpu);
2256                 break;
2257         case VCPU_EXREG_CR0:
2258                 guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2259
2260                 vcpu->arch.cr0 &= ~guest_owned_bits;
2261                 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & guest_owned_bits;
2262                 break;
2263         case VCPU_EXREG_CR3:
2264                 /*
2265                  * When intercepting CR3 loads, e.g. for shadowing paging, KVM's
2266                  * CR3 is loaded into hardware, not the guest's CR3.
2267                  */
2268                 if (!(exec_controls_get(to_vmx(vcpu)) & CPU_BASED_CR3_LOAD_EXITING))
2269                         vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2270                 break;
2271         case VCPU_EXREG_CR4:
2272                 guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2273
2274                 vcpu->arch.cr4 &= ~guest_owned_bits;
2275                 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & guest_owned_bits;
2276                 break;
2277         default:
2278                 KVM_BUG_ON(1, vcpu->kvm);
2279                 break;
2280         }
2281 }
2282
2283 static __init int cpu_has_kvm_support(void)
2284 {
2285         return cpu_has_vmx();
2286 }
2287
2288 static __init int vmx_disabled_by_bios(void)
2289 {
2290         return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
2291                !boot_cpu_has(X86_FEATURE_VMX);
2292 }
2293
2294 static int kvm_cpu_vmxon(u64 vmxon_pointer)
2295 {
2296         u64 msr;
2297
2298         cr4_set_bits(X86_CR4_VMXE);
2299
2300         asm_volatile_goto("1: vmxon %[vmxon_pointer]\n\t"
2301                           _ASM_EXTABLE(1b, %l[fault])
2302                           : : [vmxon_pointer] "m"(vmxon_pointer)
2303                           : : fault);
2304         return 0;
2305
2306 fault:
2307         WARN_ONCE(1, "VMXON faulted, MSR_IA32_FEAT_CTL (0x3a) = 0x%llx\n",
2308                   rdmsrl_safe(MSR_IA32_FEAT_CTL, &msr) ? 0xdeadbeef : msr);
2309         cr4_clear_bits(X86_CR4_VMXE);
2310
2311         return -EFAULT;
2312 }
2313
2314 static int hardware_enable(void)
2315 {
2316         int cpu = raw_smp_processor_id();
2317         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2318         int r;
2319
2320         if (cr4_read_shadow() & X86_CR4_VMXE)
2321                 return -EBUSY;
2322
2323         /*
2324          * This can happen if we hot-added a CPU but failed to allocate
2325          * VP assist page for it.
2326          */
2327         if (static_branch_unlikely(&enable_evmcs) &&
2328             !hv_get_vp_assist_page(cpu))
2329                 return -EFAULT;
2330
2331         intel_pt_handle_vmx(1);
2332
2333         r = kvm_cpu_vmxon(phys_addr);
2334         if (r) {
2335                 intel_pt_handle_vmx(0);
2336                 return r;
2337         }
2338
2339         if (enable_ept)
2340                 ept_sync_global();
2341
2342         return 0;
2343 }
2344
2345 static void vmclear_local_loaded_vmcss(void)
2346 {
2347         int cpu = raw_smp_processor_id();
2348         struct loaded_vmcs *v, *n;
2349
2350         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2351                                  loaded_vmcss_on_cpu_link)
2352                 __loaded_vmcs_clear(v);
2353 }
2354
2355 static void hardware_disable(void)
2356 {
2357         vmclear_local_loaded_vmcss();
2358
2359         if (cpu_vmxoff())
2360                 kvm_spurious_fault();
2361
2362         intel_pt_handle_vmx(0);
2363 }
2364
2365 /*
2366  * There is no X86_FEATURE for SGX yet, but anyway we need to query CPUID
2367  * directly instead of going through cpu_has(), to ensure KVM is trapping
2368  * ENCLS whenever it's supported in hardware.  It does not matter whether
2369  * the host OS supports or has enabled SGX.
2370  */
2371 static bool cpu_has_sgx(void)
2372 {
2373         return cpuid_eax(0) >= 0x12 && (cpuid_eax(0x12) & BIT(0));
2374 }
2375
2376 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2377                                       u32 msr, u32 *result)
2378 {
2379         u32 vmx_msr_low, vmx_msr_high;
2380         u32 ctl = ctl_min | ctl_opt;
2381
2382         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2383
2384         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2385         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2386
2387         /* Ensure minimum (required) set of control bits are supported. */
2388         if (ctl_min & ~ctl)
2389                 return -EIO;
2390
2391         *result = ctl;
2392         return 0;
2393 }
2394
2395 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2396                                     struct vmx_capability *vmx_cap)
2397 {
2398         u32 vmx_msr_low, vmx_msr_high;
2399         u32 min, opt, min2, opt2;
2400         u32 _pin_based_exec_control = 0;
2401         u32 _cpu_based_exec_control = 0;
2402         u32 _cpu_based_2nd_exec_control = 0;
2403         u32 _vmexit_control = 0;
2404         u32 _vmentry_control = 0;
2405
2406         memset(vmcs_conf, 0, sizeof(*vmcs_conf));
2407         min = CPU_BASED_HLT_EXITING |
2408 #ifdef CONFIG_X86_64
2409               CPU_BASED_CR8_LOAD_EXITING |
2410               CPU_BASED_CR8_STORE_EXITING |
2411 #endif
2412               CPU_BASED_CR3_LOAD_EXITING |
2413               CPU_BASED_CR3_STORE_EXITING |
2414               CPU_BASED_UNCOND_IO_EXITING |
2415               CPU_BASED_MOV_DR_EXITING |
2416               CPU_BASED_USE_TSC_OFFSETTING |
2417               CPU_BASED_MWAIT_EXITING |
2418               CPU_BASED_MONITOR_EXITING |
2419               CPU_BASED_INVLPG_EXITING |
2420               CPU_BASED_RDPMC_EXITING;
2421
2422         opt = CPU_BASED_TPR_SHADOW |
2423               CPU_BASED_USE_MSR_BITMAPS |
2424               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2425         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2426                                 &_cpu_based_exec_control) < 0)
2427                 return -EIO;
2428 #ifdef CONFIG_X86_64
2429         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2430                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2431                                            ~CPU_BASED_CR8_STORE_EXITING;
2432 #endif
2433         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2434                 min2 = 0;
2435                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2436                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2437                         SECONDARY_EXEC_WBINVD_EXITING |
2438                         SECONDARY_EXEC_ENABLE_VPID |
2439                         SECONDARY_EXEC_ENABLE_EPT |
2440                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2441                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2442                         SECONDARY_EXEC_DESC |
2443                         SECONDARY_EXEC_ENABLE_RDTSCP |
2444                         SECONDARY_EXEC_ENABLE_INVPCID |
2445                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2446                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2447                         SECONDARY_EXEC_SHADOW_VMCS |
2448                         SECONDARY_EXEC_XSAVES |
2449                         SECONDARY_EXEC_RDSEED_EXITING |
2450                         SECONDARY_EXEC_RDRAND_EXITING |
2451                         SECONDARY_EXEC_ENABLE_PML |
2452                         SECONDARY_EXEC_TSC_SCALING |
2453                         SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
2454                         SECONDARY_EXEC_PT_USE_GPA |
2455                         SECONDARY_EXEC_PT_CONCEAL_VMX |
2456                         SECONDARY_EXEC_ENABLE_VMFUNC |
2457                         SECONDARY_EXEC_BUS_LOCK_DETECTION;
2458                 if (cpu_has_sgx())
2459                         opt2 |= SECONDARY_EXEC_ENCLS_EXITING;
2460                 if (adjust_vmx_controls(min2, opt2,
2461                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2462                                         &_cpu_based_2nd_exec_control) < 0)
2463                         return -EIO;
2464         }
2465 #ifndef CONFIG_X86_64
2466         if (!(_cpu_based_2nd_exec_control &
2467                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2468                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2469 #endif
2470
2471         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2472                 _cpu_based_2nd_exec_control &= ~(
2473                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2474                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2475                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2476
2477         rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
2478                 &vmx_cap->ept, &vmx_cap->vpid);
2479
2480         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2481                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2482                    enabled */
2483                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2484                                              CPU_BASED_CR3_STORE_EXITING |
2485                                              CPU_BASED_INVLPG_EXITING);
2486         } else if (vmx_cap->ept) {
2487                 vmx_cap->ept = 0;
2488                 pr_warn_once("EPT CAP should not exist if not support "
2489                                 "1-setting enable EPT VM-execution control\n");
2490         }
2491         if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
2492                 vmx_cap->vpid) {
2493                 vmx_cap->vpid = 0;
2494                 pr_warn_once("VPID CAP should not exist if not support "
2495                                 "1-setting enable VPID VM-execution control\n");
2496         }
2497
2498         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
2499 #ifdef CONFIG_X86_64
2500         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2501 #endif
2502         opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2503               VM_EXIT_LOAD_IA32_PAT |
2504               VM_EXIT_LOAD_IA32_EFER |
2505               VM_EXIT_CLEAR_BNDCFGS |
2506               VM_EXIT_PT_CONCEAL_PIP |
2507               VM_EXIT_CLEAR_IA32_RTIT_CTL;
2508         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2509                                 &_vmexit_control) < 0)
2510                 return -EIO;
2511
2512         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2513         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2514                  PIN_BASED_VMX_PREEMPTION_TIMER;
2515         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2516                                 &_pin_based_exec_control) < 0)
2517                 return -EIO;
2518
2519         if (cpu_has_broken_vmx_preemption_timer())
2520                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2521         if (!(_cpu_based_2nd_exec_control &
2522                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
2523                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2524
2525         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2526         opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2527               VM_ENTRY_LOAD_IA32_PAT |
2528               VM_ENTRY_LOAD_IA32_EFER |
2529               VM_ENTRY_LOAD_BNDCFGS |
2530               VM_ENTRY_PT_CONCEAL_PIP |
2531               VM_ENTRY_LOAD_IA32_RTIT_CTL;
2532         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2533                                 &_vmentry_control) < 0)
2534                 return -EIO;
2535
2536         /*
2537          * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2538          * can't be used due to an errata where VM Exit may incorrectly clear
2539          * IA32_PERF_GLOBAL_CTRL[34:32].  Workaround the errata by using the
2540          * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2541          */
2542         if (boot_cpu_data.x86 == 0x6) {
2543                 switch (boot_cpu_data.x86_model) {
2544                 case 26: /* AAK155 */
2545                 case 30: /* AAP115 */
2546                 case 37: /* AAT100 */
2547                 case 44: /* BC86,AAY89,BD102 */
2548                 case 46: /* BA97 */
2549                         _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
2550                         _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2551                         pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2552                                         "does not work properly. Using workaround\n");
2553                         break;
2554                 default:
2555                         break;
2556                 }
2557         }
2558
2559
2560         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2561
2562         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2563         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2564                 return -EIO;
2565
2566 #ifdef CONFIG_X86_64
2567         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2568         if (vmx_msr_high & (1u<<16))
2569                 return -EIO;
2570 #endif
2571
2572         /* Require Write-Back (WB) memory type for VMCS accesses. */
2573         if (((vmx_msr_high >> 18) & 15) != 6)
2574                 return -EIO;
2575
2576         vmcs_conf->size = vmx_msr_high & 0x1fff;
2577         vmcs_conf->order = get_order(vmcs_conf->size);
2578         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
2579
2580         vmcs_conf->revision_id = vmx_msr_low;
2581
2582         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2583         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2584         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2585         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2586         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2587
2588 #if IS_ENABLED(CONFIG_HYPERV)
2589         if (enlightened_vmcs)
2590                 evmcs_sanitize_exec_ctrls(vmcs_conf);
2591 #endif
2592
2593         return 0;
2594 }
2595
2596 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
2597 {
2598         int node = cpu_to_node(cpu);
2599         struct page *pages;
2600         struct vmcs *vmcs;
2601
2602         pages = __alloc_pages_node(node, flags, vmcs_config.order);
2603         if (!pages)
2604                 return NULL;
2605         vmcs = page_address(pages);
2606         memset(vmcs, 0, vmcs_config.size);
2607
2608         /* KVM supports Enlightened VMCS v1 only */
2609         if (static_branch_unlikely(&enable_evmcs))
2610                 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2611         else
2612                 vmcs->hdr.revision_id = vmcs_config.revision_id;
2613
2614         if (shadow)
2615                 vmcs->hdr.shadow_vmcs = 1;
2616         return vmcs;
2617 }
2618
2619 void free_vmcs(struct vmcs *vmcs)
2620 {
2621         free_pages((unsigned long)vmcs, vmcs_config.order);
2622 }
2623
2624 /*
2625  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2626  */
2627 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2628 {
2629         if (!loaded_vmcs->vmcs)
2630                 return;
2631         loaded_vmcs_clear(loaded_vmcs);
2632         free_vmcs(loaded_vmcs->vmcs);
2633         loaded_vmcs->vmcs = NULL;
2634         if (loaded_vmcs->msr_bitmap)
2635                 free_page((unsigned long)loaded_vmcs->msr_bitmap);
2636         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
2637 }
2638
2639 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2640 {
2641         loaded_vmcs->vmcs = alloc_vmcs(false);
2642         if (!loaded_vmcs->vmcs)
2643                 return -ENOMEM;
2644
2645         vmcs_clear(loaded_vmcs->vmcs);
2646
2647         loaded_vmcs->shadow_vmcs = NULL;
2648         loaded_vmcs->hv_timer_soft_disabled = false;
2649         loaded_vmcs->cpu = -1;
2650         loaded_vmcs->launched = 0;
2651
2652         if (cpu_has_vmx_msr_bitmap()) {
2653                 loaded_vmcs->msr_bitmap = (unsigned long *)
2654                                 __get_free_page(GFP_KERNEL_ACCOUNT);
2655                 if (!loaded_vmcs->msr_bitmap)
2656                         goto out_vmcs;
2657                 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
2658
2659                 if (IS_ENABLED(CONFIG_HYPERV) &&
2660                     static_branch_unlikely(&enable_evmcs) &&
2661                     (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2662                         struct hv_enlightened_vmcs *evmcs =
2663                                 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2664
2665                         evmcs->hv_enlightenments_control.msr_bitmap = 1;
2666                 }
2667         }
2668
2669         memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2670         memset(&loaded_vmcs->controls_shadow, 0,
2671                 sizeof(struct vmcs_controls_shadow));
2672
2673         return 0;
2674
2675 out_vmcs:
2676         free_loaded_vmcs(loaded_vmcs);
2677         return -ENOMEM;
2678 }
2679
2680 static void free_kvm_area(void)
2681 {
2682         int cpu;
2683
2684         for_each_possible_cpu(cpu) {
2685                 free_vmcs(per_cpu(vmxarea, cpu));
2686                 per_cpu(vmxarea, cpu) = NULL;
2687         }
2688 }
2689
2690 static __init int alloc_kvm_area(void)
2691 {
2692         int cpu;
2693
2694         for_each_possible_cpu(cpu) {
2695                 struct vmcs *vmcs;
2696
2697                 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
2698                 if (!vmcs) {
2699                         free_kvm_area();
2700                         return -ENOMEM;
2701                 }
2702
2703                 /*
2704                  * When eVMCS is enabled, alloc_vmcs_cpu() sets
2705                  * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2706                  * revision_id reported by MSR_IA32_VMX_BASIC.
2707                  *
2708                  * However, even though not explicitly documented by
2709                  * TLFS, VMXArea passed as VMXON argument should
2710                  * still be marked with revision_id reported by
2711                  * physical CPU.
2712                  */
2713                 if (static_branch_unlikely(&enable_evmcs))
2714                         vmcs->hdr.revision_id = vmcs_config.revision_id;
2715
2716                 per_cpu(vmxarea, cpu) = vmcs;
2717         }
2718         return 0;
2719 }
2720
2721 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2722                 struct kvm_segment *save)
2723 {
2724         if (!emulate_invalid_guest_state) {
2725                 /*
2726                  * CS and SS RPL should be equal during guest entry according
2727                  * to VMX spec, but in reality it is not always so. Since vcpu
2728                  * is in the middle of the transition from real mode to
2729                  * protected mode it is safe to assume that RPL 0 is a good
2730                  * default value.
2731                  */
2732                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2733                         save->selector &= ~SEGMENT_RPL_MASK;
2734                 save->dpl = save->selector & SEGMENT_RPL_MASK;
2735                 save->s = 1;
2736         }
2737         __vmx_set_segment(vcpu, save, seg);
2738 }
2739
2740 static void enter_pmode(struct kvm_vcpu *vcpu)
2741 {
2742         unsigned long flags;
2743         struct vcpu_vmx *vmx = to_vmx(vcpu);
2744
2745         /*
2746          * Update real mode segment cache. It may be not up-to-date if segment
2747          * register was written while vcpu was in a guest mode.
2748          */
2749         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2750         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2751         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2752         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2753         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2754         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2755
2756         vmx->rmode.vm86_active = 0;
2757
2758         __vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2759
2760         flags = vmcs_readl(GUEST_RFLAGS);
2761         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2762         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2763         vmcs_writel(GUEST_RFLAGS, flags);
2764
2765         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2766                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2767
2768         vmx_update_exception_bitmap(vcpu);
2769
2770         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2771         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2772         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2773         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2774         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2775         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2776 }
2777
2778 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2779 {
2780         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2781         struct kvm_segment var = *save;
2782
2783         var.dpl = 0x3;
2784         if (seg == VCPU_SREG_CS)
2785                 var.type = 0x3;
2786
2787         if (!emulate_invalid_guest_state) {
2788                 var.selector = var.base >> 4;
2789                 var.base = var.base & 0xffff0;
2790                 var.limit = 0xffff;
2791                 var.g = 0;
2792                 var.db = 0;
2793                 var.present = 1;
2794                 var.s = 1;
2795                 var.l = 0;
2796                 var.unusable = 0;
2797                 var.type = 0x3;
2798                 var.avl = 0;
2799                 if (save->base & 0xf)
2800                         printk_once(KERN_WARNING "kvm: segment base is not "
2801                                         "paragraph aligned when entering "
2802                                         "protected mode (seg=%d)", seg);
2803         }
2804
2805         vmcs_write16(sf->selector, var.selector);
2806         vmcs_writel(sf->base, var.base);
2807         vmcs_write32(sf->limit, var.limit);
2808         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2809 }
2810
2811 static void enter_rmode(struct kvm_vcpu *vcpu)
2812 {
2813         unsigned long flags;
2814         struct vcpu_vmx *vmx = to_vmx(vcpu);
2815         struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
2816
2817         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2818         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2819         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2820         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2821         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2822         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2823         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2824
2825         vmx->rmode.vm86_active = 1;
2826
2827         /*
2828          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2829          * vcpu. Warn the user that an update is overdue.
2830          */
2831         if (!kvm_vmx->tss_addr)
2832                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2833                              "called before entering vcpu\n");
2834
2835         vmx_segment_cache_clear(vmx);
2836
2837         vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
2838         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2839         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2840
2841         flags = vmcs_readl(GUEST_RFLAGS);
2842         vmx->rmode.save_rflags = flags;
2843
2844         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2845
2846         vmcs_writel(GUEST_RFLAGS, flags);
2847         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2848         vmx_update_exception_bitmap(vcpu);
2849
2850         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2851         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2852         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2853         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2854         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2855         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2856 }
2857
2858 int vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2859 {
2860         struct vcpu_vmx *vmx = to_vmx(vcpu);
2861         struct vmx_uret_msr *msr = vmx_find_uret_msr(vmx, MSR_EFER);
2862
2863         /* Nothing to do if hardware doesn't support EFER. */
2864         if (!msr)
2865                 return 0;
2866
2867         vcpu->arch.efer = efer;
2868         if (efer & EFER_LMA) {
2869                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2870                 msr->data = efer;
2871         } else {
2872                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2873
2874                 msr->data = efer & ~EFER_LME;
2875         }
2876         vmx_setup_uret_msrs(vmx);
2877         return 0;
2878 }
2879
2880 #ifdef CONFIG_X86_64
2881
2882 static void enter_lmode(struct kvm_vcpu *vcpu)
2883 {
2884         u32 guest_tr_ar;
2885
2886         vmx_segment_cache_clear(to_vmx(vcpu));
2887
2888         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2889         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
2890                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2891                                      __func__);
2892                 vmcs_write32(GUEST_TR_AR_BYTES,
2893                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2894                              | VMX_AR_TYPE_BUSY_64_TSS);
2895         }
2896         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2897 }
2898
2899 static void exit_lmode(struct kvm_vcpu *vcpu)
2900 {
2901         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2902         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2903 }
2904
2905 #endif
2906
2907 static void vmx_flush_tlb_all(struct kvm_vcpu *vcpu)
2908 {
2909         struct vcpu_vmx *vmx = to_vmx(vcpu);
2910
2911         /*
2912          * INVEPT must be issued when EPT is enabled, irrespective of VPID, as
2913          * the CPU is not required to invalidate guest-physical mappings on
2914          * VM-Entry, even if VPID is disabled.  Guest-physical mappings are
2915          * associated with the root EPT structure and not any particular VPID
2916          * (INVVPID also isn't required to invalidate guest-physical mappings).
2917          */
2918         if (enable_ept) {
2919                 ept_sync_global();
2920         } else if (enable_vpid) {
2921                 if (cpu_has_vmx_invvpid_global()) {
2922                         vpid_sync_vcpu_global();
2923                 } else {
2924                         vpid_sync_vcpu_single(vmx->vpid);
2925                         vpid_sync_vcpu_single(vmx->nested.vpid02);
2926                 }
2927         }
2928 }
2929
2930 static void vmx_flush_tlb_current(struct kvm_vcpu *vcpu)
2931 {
2932         struct kvm_mmu *mmu = vcpu->arch.mmu;
2933         u64 root_hpa = mmu->root_hpa;
2934
2935         /* No flush required if the current context is invalid. */
2936         if (!VALID_PAGE(root_hpa))
2937                 return;
2938
2939         if (enable_ept)
2940                 ept_sync_context(construct_eptp(vcpu, root_hpa,
2941                                                 mmu->shadow_root_level));
2942         else if (!is_guest_mode(vcpu))
2943                 vpid_sync_context(to_vmx(vcpu)->vpid);
2944         else
2945                 vpid_sync_context(nested_get_vpid02(vcpu));
2946 }
2947
2948 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2949 {
2950         /*
2951          * vpid_sync_vcpu_addr() is a nop if vmx->vpid==0, see the comment in
2952          * vmx_flush_tlb_guest() for an explanation of why this is ok.
2953          */
2954         vpid_sync_vcpu_addr(to_vmx(vcpu)->vpid, addr);
2955 }
2956
2957 static void vmx_flush_tlb_guest(struct kvm_vcpu *vcpu)
2958 {
2959         /*
2960          * vpid_sync_context() is a nop if vmx->vpid==0, e.g. if enable_vpid==0
2961          * or a vpid couldn't be allocated for this vCPU.  VM-Enter and VM-Exit
2962          * are required to flush GVA->{G,H}PA mappings from the TLB if vpid is
2963          * disabled (VM-Enter with vpid enabled and vpid==0 is disallowed),
2964          * i.e. no explicit INVVPID is necessary.
2965          */
2966         vpid_sync_context(to_vmx(vcpu)->vpid);
2967 }
2968
2969 void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu)
2970 {
2971         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2972
2973         if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR))
2974                 return;
2975
2976         if (is_pae_paging(vcpu)) {
2977                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2978                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2979                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2980                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
2981         }
2982 }
2983
2984 void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2985 {
2986         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2987
2988         if (WARN_ON_ONCE(!is_pae_paging(vcpu)))
2989                 return;
2990
2991         mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2992         mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2993         mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2994         mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2995
2996         kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
2997 }
2998
2999 #define CR3_EXITING_BITS (CPU_BASED_CR3_LOAD_EXITING | \
3000                           CPU_BASED_CR3_STORE_EXITING)
3001
3002 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3003 {
3004         struct vcpu_vmx *vmx = to_vmx(vcpu);
3005         unsigned long hw_cr0, old_cr0_pg;
3006         u32 tmp;
3007
3008         old_cr0_pg = kvm_read_cr0_bits(vcpu, X86_CR0_PG);
3009
3010         hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
3011         if (is_unrestricted_guest(vcpu))
3012                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3013         else {
3014                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3015                 if (!enable_ept)
3016                         hw_cr0 |= X86_CR0_WP;
3017
3018                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3019                         enter_pmode(vcpu);
3020
3021                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3022                         enter_rmode(vcpu);
3023         }
3024
3025         vmcs_writel(CR0_READ_SHADOW, cr0);
3026         vmcs_writel(GUEST_CR0, hw_cr0);
3027         vcpu->arch.cr0 = cr0;
3028         kvm_register_mark_available(vcpu, VCPU_EXREG_CR0);
3029
3030 #ifdef CONFIG_X86_64
3031         if (vcpu->arch.efer & EFER_LME) {
3032                 if (!old_cr0_pg && (cr0 & X86_CR0_PG))
3033                         enter_lmode(vcpu);
3034                 else if (old_cr0_pg && !(cr0 & X86_CR0_PG))
3035                         exit_lmode(vcpu);
3036         }
3037 #endif
3038
3039         if (enable_ept && !is_unrestricted_guest(vcpu)) {
3040                 /*
3041                  * Ensure KVM has an up-to-date snapshot of the guest's CR3.  If
3042                  * the below code _enables_ CR3 exiting, vmx_cache_reg() will
3043                  * (correctly) stop reading vmcs.GUEST_CR3 because it thinks
3044                  * KVM's CR3 is installed.
3045                  */
3046                 if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3))
3047                         vmx_cache_reg(vcpu, VCPU_EXREG_CR3);
3048
3049                 /*
3050                  * When running with EPT but not unrestricted guest, KVM must
3051                  * intercept CR3 accesses when paging is _disabled_.  This is
3052                  * necessary because restricted guests can't actually run with
3053                  * paging disabled, and so KVM stuffs its own CR3 in order to
3054                  * run the guest when identity mapped page tables.
3055                  *
3056                  * Do _NOT_ check the old CR0.PG, e.g. to optimize away the
3057                  * update, it may be stale with respect to CR3 interception,
3058                  * e.g. after nested VM-Enter.
3059                  *
3060                  * Lastly, honor L1's desires, i.e. intercept CR3 loads and/or
3061                  * stores to forward them to L1, even if KVM does not need to
3062                  * intercept them to preserve its identity mapped page tables.
3063                  */
3064                 if (!(cr0 & X86_CR0_PG)) {
3065                         exec_controls_setbit(vmx, CR3_EXITING_BITS);
3066                 } else if (!is_guest_mode(vcpu)) {
3067                         exec_controls_clearbit(vmx, CR3_EXITING_BITS);
3068                 } else {
3069                         tmp = exec_controls_get(vmx);
3070                         tmp &= ~CR3_EXITING_BITS;
3071                         tmp |= get_vmcs12(vcpu)->cpu_based_vm_exec_control & CR3_EXITING_BITS;
3072                         exec_controls_set(vmx, tmp);
3073                 }
3074
3075                 /* Note, vmx_set_cr4() consumes the new vcpu->arch.cr0. */
3076                 if ((old_cr0_pg ^ cr0) & X86_CR0_PG)
3077                         vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3078         }
3079
3080         /* depends on vcpu->arch.cr0 to be set to a new value */
3081         vmx->emulation_required = vmx_emulation_required(vcpu);
3082 }
3083
3084 static int vmx_get_max_tdp_level(void)
3085 {
3086         if (cpu_has_vmx_ept_5levels())
3087                 return 5;
3088         return 4;
3089 }
3090
3091 u64 construct_eptp(struct kvm_vcpu *vcpu, hpa_t root_hpa, int root_level)
3092 {
3093         u64 eptp = VMX_EPTP_MT_WB;
3094
3095         eptp |= (root_level == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
3096
3097         if (enable_ept_ad_bits &&
3098             (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
3099                 eptp |= VMX_EPTP_AD_ENABLE_BIT;
3100         eptp |= root_hpa;
3101
3102         return eptp;
3103 }
3104
3105 static void vmx_load_mmu_pgd(struct kvm_vcpu *vcpu, hpa_t root_hpa,
3106                              int root_level)
3107 {
3108         struct kvm *kvm = vcpu->kvm;
3109         bool update_guest_cr3 = true;
3110         unsigned long guest_cr3;
3111         u64 eptp;
3112
3113         if (enable_ept) {
3114                 eptp = construct_eptp(vcpu, root_hpa, root_level);
3115                 vmcs_write64(EPT_POINTER, eptp);
3116
3117                 hv_track_root_tdp(vcpu, root_hpa);
3118
3119                 if (!enable_unrestricted_guest && !is_paging(vcpu))
3120                         guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
3121                 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3122                         guest_cr3 = vcpu->arch.cr3;
3123                 else /* vmcs01.GUEST_CR3 is already up-to-date. */
3124                         update_guest_cr3 = false;
3125                 vmx_ept_load_pdptrs(vcpu);
3126         } else {
3127                 guest_cr3 = root_hpa | kvm_get_active_pcid(vcpu);
3128         }
3129
3130         if (update_guest_cr3)
3131                 vmcs_writel(GUEST_CR3, guest_cr3);
3132 }
3133
3134 static bool vmx_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3135 {
3136         /*
3137          * We operate under the default treatment of SMM, so VMX cannot be
3138          * enabled under SMM.  Note, whether or not VMXE is allowed at all is
3139          * handled by kvm_is_valid_cr4().
3140          */
3141         if ((cr4 & X86_CR4_VMXE) && is_smm(vcpu))
3142                 return false;
3143
3144         if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
3145                 return false;
3146
3147         return true;
3148 }
3149
3150 void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3151 {
3152         unsigned long old_cr4 = vcpu->arch.cr4;
3153         struct vcpu_vmx *vmx = to_vmx(vcpu);
3154         /*
3155          * Pass through host's Machine Check Enable value to hw_cr4, which
3156          * is in force while we are in guest mode.  Do not let guests control
3157          * this bit, even if host CR4.MCE == 0.
3158          */
3159         unsigned long hw_cr4;
3160
3161         hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
3162         if (is_unrestricted_guest(vcpu))
3163                 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
3164         else if (vmx->rmode.vm86_active)
3165                 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
3166         else
3167                 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
3168
3169         if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
3170                 if (cr4 & X86_CR4_UMIP) {
3171                         secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
3172                         hw_cr4 &= ~X86_CR4_UMIP;
3173                 } else if (!is_guest_mode(vcpu) ||
3174                         !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
3175                         secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
3176                 }
3177         }
3178
3179         vcpu->arch.cr4 = cr4;
3180         kvm_register_mark_available(vcpu, VCPU_EXREG_CR4);
3181
3182         if (!is_unrestricted_guest(vcpu)) {
3183                 if (enable_ept) {
3184                         if (!is_paging(vcpu)) {
3185                                 hw_cr4 &= ~X86_CR4_PAE;
3186                                 hw_cr4 |= X86_CR4_PSE;
3187                         } else if (!(cr4 & X86_CR4_PAE)) {
3188                                 hw_cr4 &= ~X86_CR4_PAE;
3189                         }
3190                 }
3191
3192                 /*
3193                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3194                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
3195                  * to be manually disabled when guest switches to non-paging
3196                  * mode.
3197                  *
3198                  * If !enable_unrestricted_guest, the CPU is always running
3199                  * with CR0.PG=1 and CR4 needs to be modified.
3200                  * If enable_unrestricted_guest, the CPU automatically
3201                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3202                  */
3203                 if (!is_paging(vcpu))
3204                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3205         }
3206
3207         vmcs_writel(CR4_READ_SHADOW, cr4);
3208         vmcs_writel(GUEST_CR4, hw_cr4);
3209
3210         if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
3211                 kvm_update_cpuid_runtime(vcpu);
3212 }
3213
3214 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3215 {
3216         struct vcpu_vmx *vmx = to_vmx(vcpu);
3217         u32 ar;
3218
3219         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3220                 *var = vmx->rmode.segs[seg];
3221                 if (seg == VCPU_SREG_TR
3222                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3223                         return;
3224                 var->base = vmx_read_guest_seg_base(vmx, seg);
3225                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3226                 return;
3227         }
3228         var->base = vmx_read_guest_seg_base(vmx, seg);
3229         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3230         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3231         ar = vmx_read_guest_seg_ar(vmx, seg);
3232         var->unusable = (ar >> 16) & 1;
3233         var->type = ar & 15;
3234         var->s = (ar >> 4) & 1;
3235         var->dpl = (ar >> 5) & 3;
3236         /*
3237          * Some userspaces do not preserve unusable property. Since usable
3238          * segment has to be present according to VMX spec we can use present
3239          * property to amend userspace bug by making unusable segment always
3240          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3241          * segment as unusable.
3242          */
3243         var->present = !var->unusable;
3244         var->avl = (ar >> 12) & 1;
3245         var->l = (ar >> 13) & 1;
3246         var->db = (ar >> 14) & 1;
3247         var->g = (ar >> 15) & 1;
3248 }
3249
3250 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3251 {
3252         struct kvm_segment s;
3253
3254         if (to_vmx(vcpu)->rmode.vm86_active) {
3255                 vmx_get_segment(vcpu, &s, seg);
3256                 return s.base;
3257         }
3258         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3259 }
3260
3261 int vmx_get_cpl(struct kvm_vcpu *vcpu)
3262 {
3263         struct vcpu_vmx *vmx = to_vmx(vcpu);
3264
3265         if (unlikely(vmx->rmode.vm86_active))
3266                 return 0;
3267         else {
3268                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3269                 return VMX_AR_DPL(ar);
3270         }
3271 }
3272
3273 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3274 {
3275         u32 ar;
3276
3277         if (var->unusable || !var->present)
3278                 ar = 1 << 16;
3279         else {
3280                 ar = var->type & 15;
3281                 ar |= (var->s & 1) << 4;
3282                 ar |= (var->dpl & 3) << 5;
3283                 ar |= (var->present & 1) << 7;
3284                 ar |= (var->avl & 1) << 12;
3285                 ar |= (var->l & 1) << 13;
3286                 ar |= (var->db & 1) << 14;
3287                 ar |= (var->g & 1) << 15;
3288         }
3289
3290         return ar;
3291 }
3292
3293 void __vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3294 {
3295         struct vcpu_vmx *vmx = to_vmx(vcpu);
3296         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3297
3298         vmx_segment_cache_clear(vmx);
3299
3300         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3301                 vmx->rmode.segs[seg] = *var;
3302                 if (seg == VCPU_SREG_TR)
3303                         vmcs_write16(sf->selector, var->selector);
3304                 else if (var->s)
3305                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3306                 return;
3307         }
3308
3309         vmcs_writel(sf->base, var->base);
3310         vmcs_write32(sf->limit, var->limit);
3311         vmcs_write16(sf->selector, var->selector);
3312
3313         /*
3314          *   Fix the "Accessed" bit in AR field of segment registers for older
3315          * qemu binaries.
3316          *   IA32 arch specifies that at the time of processor reset the
3317          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3318          * is setting it to 0 in the userland code. This causes invalid guest
3319          * state vmexit when "unrestricted guest" mode is turned on.
3320          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3321          * tree. Newer qemu binaries with that qemu fix would not need this
3322          * kvm hack.
3323          */
3324         if (is_unrestricted_guest(vcpu) && (seg != VCPU_SREG_LDTR))
3325                 var->type |= 0x1; /* Accessed */
3326
3327         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3328 }
3329
3330 static void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3331 {
3332         __vmx_set_segment(vcpu, var, seg);
3333
3334         to_vmx(vcpu)->emulation_required = vmx_emulation_required(vcpu);
3335 }
3336
3337 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3338 {
3339         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3340
3341         *db = (ar >> 14) & 1;
3342         *l = (ar >> 13) & 1;
3343 }
3344
3345 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3346 {
3347         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3348         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3349 }
3350
3351 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3352 {
3353         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3354         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3355 }
3356
3357 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3358 {
3359         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3360         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3361 }
3362
3363 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3364 {
3365         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3366         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3367 }
3368
3369 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3370 {
3371         struct kvm_segment var;
3372         u32 ar;
3373
3374         vmx_get_segment(vcpu, &var, seg);
3375         var.dpl = 0x3;
3376         if (seg == VCPU_SREG_CS)
3377                 var.type = 0x3;
3378         ar = vmx_segment_access_rights(&var);
3379
3380         if (var.base != (var.selector << 4))
3381                 return false;
3382         if (var.limit != 0xffff)
3383                 return false;
3384         if (ar != 0xf3)
3385                 return false;
3386
3387         return true;
3388 }
3389
3390 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3391 {
3392         struct kvm_segment cs;
3393         unsigned int cs_rpl;
3394
3395         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3396         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3397
3398         if (cs.unusable)
3399                 return false;
3400         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3401                 return false;
3402         if (!cs.s)
3403                 return false;
3404         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3405                 if (cs.dpl > cs_rpl)
3406                         return false;
3407         } else {
3408                 if (cs.dpl != cs_rpl)
3409                         return false;
3410         }
3411         if (!cs.present)
3412                 return false;
3413
3414         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3415         return true;
3416 }
3417
3418 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3419 {
3420         struct kvm_segment ss;
3421         unsigned int ss_rpl;
3422
3423         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3424         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3425
3426         if (ss.unusable)
3427                 return true;
3428         if (ss.type != 3 && ss.type != 7)
3429                 return false;
3430         if (!ss.s)
3431                 return false;
3432         if (ss.dpl != ss_rpl) /* DPL != RPL */
3433                 return false;
3434         if (!ss.present)
3435                 return false;
3436
3437         return true;
3438 }
3439
3440 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3441 {
3442         struct kvm_segment var;
3443         unsigned int rpl;
3444
3445         vmx_get_segment(vcpu, &var, seg);
3446         rpl = var.selector & SEGMENT_RPL_MASK;
3447
3448         if (var.unusable)
3449                 return true;
3450         if (!var.s)
3451                 return false;
3452         if (!var.present)
3453                 return false;
3454         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
3455                 if (var.dpl < rpl) /* DPL < RPL */
3456                         return false;
3457         }
3458
3459         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3460          * rights flags
3461          */
3462         return true;
3463 }
3464
3465 static bool tr_valid(struct kvm_vcpu *vcpu)
3466 {
3467         struct kvm_segment tr;
3468
3469         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3470
3471         if (tr.unusable)
3472                 return false;
3473         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
3474                 return false;
3475         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3476                 return false;
3477         if (!tr.present)
3478                 return false;
3479
3480         return true;
3481 }
3482
3483 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3484 {
3485         struct kvm_segment ldtr;
3486
3487         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3488
3489         if (ldtr.unusable)
3490                 return true;
3491         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
3492                 return false;
3493         if (ldtr.type != 2)
3494                 return false;
3495         if (!ldtr.present)
3496                 return false;
3497
3498         return true;
3499 }
3500
3501 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3502 {
3503         struct kvm_segment cs, ss;
3504
3505         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3506         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3507
3508         return ((cs.selector & SEGMENT_RPL_MASK) ==
3509                  (ss.selector & SEGMENT_RPL_MASK));
3510 }
3511
3512 /*
3513  * Check if guest state is valid. Returns true if valid, false if
3514  * not.
3515  * We assume that registers are always usable
3516  */
3517 bool __vmx_guest_state_valid(struct kvm_vcpu *vcpu)
3518 {
3519         /* real mode guest state checks */
3520         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3521                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3522                         return false;
3523                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3524                         return false;
3525                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3526                         return false;
3527                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3528                         return false;
3529                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3530                         return false;
3531                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3532                         return false;
3533         } else {
3534         /* protected mode guest state checks */
3535                 if (!cs_ss_rpl_check(vcpu))
3536                         return false;
3537                 if (!code_segment_valid(vcpu))
3538                         return false;
3539                 if (!stack_segment_valid(vcpu))
3540                         return false;
3541                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3542                         return false;
3543                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3544                         return false;
3545                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3546                         return false;
3547                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3548                         return false;
3549                 if (!tr_valid(vcpu))
3550                         return false;
3551                 if (!ldtr_valid(vcpu))
3552                         return false;
3553         }
3554         /* TODO:
3555          * - Add checks on RIP
3556          * - Add checks on RFLAGS
3557          */
3558
3559         return true;
3560 }
3561
3562 static int init_rmode_tss(struct kvm *kvm, void __user *ua)
3563 {
3564         const void *zero_page = (const void *) __va(page_to_phys(ZERO_PAGE(0)));
3565         u16 data;
3566         int i;
3567
3568         for (i = 0; i < 3; i++) {
3569                 if (__copy_to_user(ua + PAGE_SIZE * i, zero_page, PAGE_SIZE))
3570                         return -EFAULT;
3571         }
3572
3573         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3574         if (__copy_to_user(ua + TSS_IOPB_BASE_OFFSET, &data, sizeof(u16)))
3575                 return -EFAULT;
3576
3577         data = ~0;
3578         if (__copy_to_user(ua + RMODE_TSS_SIZE - 1, &data, sizeof(u8)))
3579                 return -EFAULT;
3580
3581         return 0;
3582 }
3583
3584 static int init_rmode_identity_map(struct kvm *kvm)
3585 {
3586         struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
3587         int i, r = 0;
3588         void __user *uaddr;
3589         u32 tmp;
3590
3591         /* Protect kvm_vmx->ept_identity_pagetable_done. */
3592         mutex_lock(&kvm->slots_lock);
3593
3594         if (likely(kvm_vmx->ept_identity_pagetable_done))
3595                 goto out;
3596
3597         if (!kvm_vmx->ept_identity_map_addr)
3598                 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3599
3600         uaddr = __x86_set_memory_region(kvm,
3601                                         IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
3602                                         kvm_vmx->ept_identity_map_addr,
3603                                         PAGE_SIZE);
3604         if (IS_ERR(uaddr)) {
3605                 r = PTR_ERR(uaddr);
3606                 goto out;
3607         }
3608
3609         /* Set up identity-mapping pagetable for EPT in real mode */
3610         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3611                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3612                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3613                 if (__copy_to_user(uaddr + i * sizeof(tmp), &tmp, sizeof(tmp))) {
3614                         r = -EFAULT;
3615                         goto out;
3616                 }
3617         }
3618         kvm_vmx->ept_identity_pagetable_done = true;
3619
3620 out:
3621         mutex_unlock(&kvm->slots_lock);
3622         return r;
3623 }
3624
3625 static void seg_setup(int seg)
3626 {
3627         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3628         unsigned int ar;
3629
3630         vmcs_write16(sf->selector, 0);
3631         vmcs_writel(sf->base, 0);
3632         vmcs_write32(sf->limit, 0xffff);
3633         ar = 0x93;
3634         if (seg == VCPU_SREG_CS)
3635                 ar |= 0x08; /* code segment */
3636
3637         vmcs_write32(sf->ar_bytes, ar);
3638 }
3639
3640 static int alloc_apic_access_page(struct kvm *kvm)
3641 {
3642         struct page *page;
3643         void __user *hva;
3644         int ret = 0;
3645
3646         mutex_lock(&kvm->slots_lock);
3647         if (kvm->arch.apic_access_memslot_enabled)
3648                 goto out;
3649         hva = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3650                                       APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
3651         if (IS_ERR(hva)) {
3652                 ret = PTR_ERR(hva);
3653                 goto out;
3654         }
3655
3656         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
3657         if (is_error_page(page)) {
3658                 ret = -EFAULT;
3659                 goto out;
3660         }
3661
3662         /*
3663          * Do not pin the page in memory, so that memory hot-unplug
3664          * is able to migrate it.
3665          */
3666         put_page(page);
3667         kvm->arch.apic_access_memslot_enabled = true;
3668 out:
3669         mutex_unlock(&kvm->slots_lock);
3670         return ret;
3671 }
3672
3673 int allocate_vpid(void)
3674 {
3675         int vpid;
3676
3677         if (!enable_vpid)
3678                 return 0;
3679         spin_lock(&vmx_vpid_lock);
3680         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3681         if (vpid < VMX_NR_VPIDS)
3682                 __set_bit(vpid, vmx_vpid_bitmap);
3683         else
3684                 vpid = 0;
3685         spin_unlock(&vmx_vpid_lock);
3686         return vpid;
3687 }
3688
3689 void free_vpid(int vpid)
3690 {
3691         if (!enable_vpid || vpid == 0)
3692                 return;
3693         spin_lock(&vmx_vpid_lock);
3694         __clear_bit(vpid, vmx_vpid_bitmap);
3695         spin_unlock(&vmx_vpid_lock);
3696 }
3697
3698 static void vmx_clear_msr_bitmap_read(ulong *msr_bitmap, u32 msr)
3699 {
3700         int f = sizeof(unsigned long);
3701
3702         if (msr <= 0x1fff)
3703                 __clear_bit(msr, msr_bitmap + 0x000 / f);
3704         else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
3705                 __clear_bit(msr & 0x1fff, msr_bitmap + 0x400 / f);
3706 }
3707
3708 static void vmx_clear_msr_bitmap_write(ulong *msr_bitmap, u32 msr)
3709 {
3710         int f = sizeof(unsigned long);
3711
3712         if (msr <= 0x1fff)
3713                 __clear_bit(msr, msr_bitmap + 0x800 / f);
3714         else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
3715                 __clear_bit(msr & 0x1fff, msr_bitmap + 0xc00 / f);
3716 }
3717
3718 static void vmx_set_msr_bitmap_read(ulong *msr_bitmap, u32 msr)
3719 {
3720         int f = sizeof(unsigned long);
3721
3722         if (msr <= 0x1fff)
3723                 __set_bit(msr, msr_bitmap + 0x000 / f);
3724         else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
3725                 __set_bit(msr & 0x1fff, msr_bitmap + 0x400 / f);
3726 }
3727
3728 static void vmx_set_msr_bitmap_write(ulong *msr_bitmap, u32 msr)
3729 {
3730         int f = sizeof(unsigned long);
3731
3732         if (msr <= 0x1fff)
3733                 __set_bit(msr, msr_bitmap + 0x800 / f);
3734         else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
3735                 __set_bit(msr & 0x1fff, msr_bitmap + 0xc00 / f);
3736 }
3737
3738 void vmx_disable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type)
3739 {
3740         struct vcpu_vmx *vmx = to_vmx(vcpu);
3741         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3742
3743         if (!cpu_has_vmx_msr_bitmap())
3744                 return;
3745
3746         if (static_branch_unlikely(&enable_evmcs))
3747                 evmcs_touch_msr_bitmap();
3748
3749         /*
3750          * Mark the desired intercept state in shadow bitmap, this is needed
3751          * for resync when the MSR filters change.
3752         */
3753         if (is_valid_passthrough_msr(msr)) {
3754                 int idx = possible_passthrough_msr_slot(msr);
3755
3756                 if (idx != -ENOENT) {
3757                         if (type & MSR_TYPE_R)
3758                                 clear_bit(idx, vmx->shadow_msr_intercept.read);
3759                         if (type & MSR_TYPE_W)
3760                                 clear_bit(idx, vmx->shadow_msr_intercept.write);
3761                 }
3762         }
3763
3764         if ((type & MSR_TYPE_R) &&
3765             !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ)) {
3766                 vmx_set_msr_bitmap_read(msr_bitmap, msr);
3767                 type &= ~MSR_TYPE_R;
3768         }
3769
3770         if ((type & MSR_TYPE_W) &&
3771             !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE)) {
3772                 vmx_set_msr_bitmap_write(msr_bitmap, msr);
3773                 type &= ~MSR_TYPE_W;
3774         }
3775
3776         if (type & MSR_TYPE_R)
3777                 vmx_clear_msr_bitmap_read(msr_bitmap, msr);
3778
3779         if (type & MSR_TYPE_W)
3780                 vmx_clear_msr_bitmap_write(msr_bitmap, msr);
3781 }
3782
3783 void vmx_enable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type)
3784 {
3785         struct vcpu_vmx *vmx = to_vmx(vcpu);
3786         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3787
3788         if (!cpu_has_vmx_msr_bitmap())
3789                 return;
3790
3791         if (static_branch_unlikely(&enable_evmcs))
3792                 evmcs_touch_msr_bitmap();
3793
3794         /*
3795          * Mark the desired intercept state in shadow bitmap, this is needed
3796          * for resync when the MSR filter changes.
3797         */
3798         if (is_valid_passthrough_msr(msr)) {
3799                 int idx = possible_passthrough_msr_slot(msr);
3800
3801                 if (idx != -ENOENT) {
3802                         if (type & MSR_TYPE_R)
3803                                 set_bit(idx, vmx->shadow_msr_intercept.read);
3804                         if (type & MSR_TYPE_W)
3805                                 set_bit(idx, vmx->shadow_msr_intercept.write);
3806                 }
3807         }
3808
3809         if (type & MSR_TYPE_R)
3810                 vmx_set_msr_bitmap_read(msr_bitmap, msr);
3811
3812         if (type & MSR_TYPE_W)
3813                 vmx_set_msr_bitmap_write(msr_bitmap, msr);
3814 }
3815
3816 static void vmx_reset_x2apic_msrs(struct kvm_vcpu *vcpu, u8 mode)
3817 {
3818         unsigned long *msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap;
3819         unsigned long read_intercept;
3820         int msr;
3821
3822         read_intercept = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3823
3824         for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3825                 unsigned int read_idx = msr / BITS_PER_LONG;
3826                 unsigned int write_idx = read_idx + (0x800 / sizeof(long));
3827
3828                 msr_bitmap[read_idx] = read_intercept;
3829                 msr_bitmap[write_idx] = ~0ul;
3830         }
3831 }
3832
3833 static void vmx_update_msr_bitmap_x2apic(struct kvm_vcpu *vcpu)
3834 {
3835         struct vcpu_vmx *vmx = to_vmx(vcpu);
3836         u8 mode;
3837
3838         if (!cpu_has_vmx_msr_bitmap())
3839                 return;
3840
3841         if (cpu_has_secondary_exec_ctrls() &&
3842             (secondary_exec_controls_get(vmx) &
3843              SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3844                 mode = MSR_BITMAP_MODE_X2APIC;
3845                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3846                         mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3847         } else {
3848                 mode = 0;
3849         }
3850
3851         if (mode == vmx->x2apic_msr_bitmap_mode)
3852                 return;
3853
3854         vmx->x2apic_msr_bitmap_mode = mode;
3855
3856         vmx_reset_x2apic_msrs(vcpu, mode);
3857
3858         /*
3859          * TPR reads and writes can be virtualized even if virtual interrupt
3860          * delivery is not in use.
3861          */
3862         vmx_set_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW,
3863                                   !(mode & MSR_BITMAP_MODE_X2APIC));
3864
3865         if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3866                 vmx_enable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_RW);
3867                 vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3868                 vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3869         }
3870 }
3871
3872 void pt_update_intercept_for_msr(struct kvm_vcpu *vcpu)
3873 {
3874         struct vcpu_vmx *vmx = to_vmx(vcpu);
3875         bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3876         u32 i;
3877
3878         vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_STATUS, MSR_TYPE_RW, flag);
3879         vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_BASE, MSR_TYPE_RW, flag);
3880         vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_MASK, MSR_TYPE_RW, flag);
3881         vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_CR3_MATCH, MSR_TYPE_RW, flag);
3882         for (i = 0; i < vmx->pt_desc.addr_range; i++) {
3883                 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3884                 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3885         }
3886 }
3887
3888 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3889 {
3890         struct vcpu_vmx *vmx = to_vmx(vcpu);
3891         void *vapic_page;
3892         u32 vppr;
3893         int rvi;
3894
3895         if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3896                 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
3897                 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
3898                 return false;
3899
3900         rvi = vmx_get_rvi();
3901
3902         vapic_page = vmx->nested.virtual_apic_map.hva;
3903         vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
3904
3905         return ((rvi & 0xf0) > (vppr & 0xf0));
3906 }
3907
3908 static void vmx_msr_filter_changed(struct kvm_vcpu *vcpu)
3909 {
3910         struct vcpu_vmx *vmx = to_vmx(vcpu);
3911         u32 i;
3912
3913         /*
3914          * Set intercept permissions for all potentially passed through MSRs
3915          * again. They will automatically get filtered through the MSR filter,
3916          * so we are back in sync after this.
3917          */
3918         for (i = 0; i < ARRAY_SIZE(vmx_possible_passthrough_msrs); i++) {
3919                 u32 msr = vmx_possible_passthrough_msrs[i];
3920                 bool read = test_bit(i, vmx->shadow_msr_intercept.read);
3921                 bool write = test_bit(i, vmx->shadow_msr_intercept.write);
3922
3923                 vmx_set_intercept_for_msr(vcpu, msr, MSR_TYPE_R, read);
3924                 vmx_set_intercept_for_msr(vcpu, msr, MSR_TYPE_W, write);
3925         }
3926
3927         pt_update_intercept_for_msr(vcpu);
3928 }
3929
3930 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3931                                                      bool nested)
3932 {
3933 #ifdef CONFIG_SMP
3934         int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3935
3936         if (vcpu->mode == IN_GUEST_MODE) {
3937                 /*
3938                  * The vector of interrupt to be delivered to vcpu had
3939                  * been set in PIR before this function.
3940                  *
3941                  * Following cases will be reached in this block, and
3942                  * we always send a notification event in all cases as
3943                  * explained below.
3944                  *
3945                  * Case 1: vcpu keeps in non-root mode. Sending a
3946                  * notification event posts the interrupt to vcpu.
3947                  *
3948                  * Case 2: vcpu exits to root mode and is still
3949                  * runnable. PIR will be synced to vIRR before the
3950                  * next vcpu entry. Sending a notification event in
3951                  * this case has no effect, as vcpu is not in root
3952                  * mode.
3953                  *
3954                  * Case 3: vcpu exits to root mode and is blocked.
3955                  * vcpu_block() has already synced PIR to vIRR and
3956                  * never blocks vcpu if vIRR is not cleared. Therefore,
3957                  * a blocked vcpu here does not wait for any requested
3958                  * interrupts in PIR, and sending a notification event
3959                  * which has no effect is safe here.
3960                  */
3961
3962                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
3963                 return true;
3964         }
3965 #endif
3966         return false;
3967 }
3968
3969 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3970                                                 int vector)
3971 {
3972         struct vcpu_vmx *vmx = to_vmx(vcpu);
3973
3974         if (is_guest_mode(vcpu) &&
3975             vector == vmx->nested.posted_intr_nv) {
3976                 /*
3977                  * If a posted intr is not recognized by hardware,
3978                  * we will accomplish it in the next vmentry.
3979                  */
3980                 vmx->nested.pi_pending = true;
3981                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3982                 /* the PIR and ON have been set by L1. */
3983                 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3984                         kvm_vcpu_kick(vcpu);
3985                 return 0;
3986         }
3987         return -1;
3988 }
3989 /*
3990  * Send interrupt to vcpu via posted interrupt way.
3991  * 1. If target vcpu is running(non-root mode), send posted interrupt
3992  * notification to vcpu and hardware will sync PIR to vIRR atomically.
3993  * 2. If target vcpu isn't running(root mode), kick it to pick up the
3994  * interrupt from PIR in next vmentry.
3995  */
3996 static int vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3997 {
3998         struct vcpu_vmx *vmx = to_vmx(vcpu);
3999         int r;
4000
4001         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4002         if (!r)
4003                 return 0;
4004
4005         if (!vcpu->arch.apicv_active)
4006                 return -1;
4007
4008         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4009                 return 0;
4010
4011         /* If a previous notification has sent the IPI, nothing to do.  */
4012         if (pi_test_and_set_on(&vmx->pi_desc))
4013                 return 0;
4014
4015         if (vcpu != kvm_get_running_vcpu() &&
4016             !kvm_vcpu_trigger_posted_interrupt(vcpu, false))
4017                 kvm_vcpu_kick(vcpu);
4018
4019         return 0;
4020 }
4021
4022 /*
4023  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4024  * will not change in the lifetime of the guest.
4025  * Note that host-state that does change is set elsewhere. E.g., host-state
4026  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4027  */
4028 void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4029 {
4030         u32 low32, high32;
4031         unsigned long tmpl;
4032         unsigned long cr0, cr3, cr4;
4033
4034         cr0 = read_cr0();
4035         WARN_ON(cr0 & X86_CR0_TS);
4036         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
4037
4038         /*
4039          * Save the most likely value for this task's CR3 in the VMCS.
4040          * We can't use __get_current_cr3_fast() because we're not atomic.
4041          */
4042         cr3 = __read_cr3();
4043         vmcs_writel(HOST_CR3, cr3);             /* 22.2.3  FIXME: shadow tables */
4044         vmx->loaded_vmcs->host_state.cr3 = cr3;
4045
4046         /* Save the most likely value for this task's CR4 in the VMCS. */
4047         cr4 = cr4_read_shadow();
4048         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4049         vmx->loaded_vmcs->host_state.cr4 = cr4;
4050
4051         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4052 #ifdef CONFIG_X86_64
4053         /*
4054          * Load null selectors, so we can avoid reloading them in
4055          * vmx_prepare_switch_to_host(), in case userspace uses
4056          * the null selectors too (the expected case).
4057          */
4058         vmcs_write16(HOST_DS_SELECTOR, 0);
4059         vmcs_write16(HOST_ES_SELECTOR, 0);
4060 #else
4061         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4062         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4063 #endif
4064         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4065         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4066
4067         vmcs_writel(HOST_IDTR_BASE, host_idt_base);   /* 22.2.4 */
4068
4069         vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
4070
4071         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4072         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4073         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4074         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4075
4076         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4077                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4078                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4079         }
4080
4081         if (cpu_has_load_ia32_efer())
4082                 vmcs_write64(HOST_IA32_EFER, host_efer);
4083 }
4084
4085 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4086 {
4087         struct kvm_vcpu *vcpu = &vmx->vcpu;
4088
4089         vcpu->arch.cr4_guest_owned_bits = KVM_POSSIBLE_CR4_GUEST_BITS &
4090                                           ~vcpu->arch.cr4_guest_rsvd_bits;
4091         if (!enable_ept)
4092                 vcpu->arch.cr4_guest_owned_bits &= ~X86_CR4_PGE;
4093         if (is_guest_mode(&vmx->vcpu))
4094                 vcpu->arch.cr4_guest_owned_bits &=
4095                         ~get_vmcs12(vcpu)->cr4_guest_host_mask;
4096         vmcs_writel(CR4_GUEST_HOST_MASK, ~vcpu->arch.cr4_guest_owned_bits);
4097 }
4098
4099 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4100 {
4101         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4102
4103         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4104                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4105
4106         if (!enable_vnmi)
4107                 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
4108
4109         if (!enable_preemption_timer)
4110                 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4111
4112         return pin_based_exec_ctrl;
4113 }
4114
4115 static u32 vmx_vmentry_ctrl(void)
4116 {
4117         u32 vmentry_ctrl = vmcs_config.vmentry_ctrl;
4118
4119         if (vmx_pt_mode_is_system())
4120                 vmentry_ctrl &= ~(VM_ENTRY_PT_CONCEAL_PIP |
4121                                   VM_ENTRY_LOAD_IA32_RTIT_CTL);
4122         /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
4123         return vmentry_ctrl &
4124                 ~(VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VM_ENTRY_LOAD_IA32_EFER);
4125 }
4126
4127 static u32 vmx_vmexit_ctrl(void)
4128 {
4129         u32 vmexit_ctrl = vmcs_config.vmexit_ctrl;
4130
4131         if (vmx_pt_mode_is_system())
4132                 vmexit_ctrl &= ~(VM_EXIT_PT_CONCEAL_PIP |
4133                                  VM_EXIT_CLEAR_IA32_RTIT_CTL);
4134         /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
4135         return vmexit_ctrl &
4136                 ~(VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | VM_EXIT_LOAD_IA32_EFER);
4137 }
4138
4139 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4140 {
4141         struct vcpu_vmx *vmx = to_vmx(vcpu);
4142
4143         pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4144         if (cpu_has_secondary_exec_ctrls()) {
4145                 if (kvm_vcpu_apicv_active(vcpu))
4146                         secondary_exec_controls_setbit(vmx,
4147                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
4148                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4149                 else
4150                         secondary_exec_controls_clearbit(vmx,
4151                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
4152                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4153         }
4154
4155         vmx_update_msr_bitmap_x2apic(vcpu);
4156 }
4157
4158 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4159 {
4160         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4161
4162         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4163                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4164
4165         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4166                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4167 #ifdef CONFIG_X86_64
4168                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4169                                 CPU_BASED_CR8_LOAD_EXITING;
4170 #endif
4171         }
4172         if (!enable_ept)
4173                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4174                                 CPU_BASED_CR3_LOAD_EXITING  |
4175                                 CPU_BASED_INVLPG_EXITING;
4176         if (kvm_mwait_in_guest(vmx->vcpu.kvm))
4177                 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
4178                                 CPU_BASED_MONITOR_EXITING);
4179         if (kvm_hlt_in_guest(vmx->vcpu.kvm))
4180                 exec_control &= ~CPU_BASED_HLT_EXITING;
4181         return exec_control;
4182 }
4183
4184 /*
4185  * Adjust a single secondary execution control bit to intercept/allow an
4186  * instruction in the guest.  This is usually done based on whether or not a
4187  * feature has been exposed to the guest in order to correctly emulate faults.
4188  */
4189 static inline void
4190 vmx_adjust_secondary_exec_control(struct vcpu_vmx *vmx, u32 *exec_control,
4191                                   u32 control, bool enabled, bool exiting)
4192 {
4193         /*
4194          * If the control is for an opt-in feature, clear the control if the
4195          * feature is not exposed to the guest, i.e. not enabled.  If the
4196          * control is opt-out, i.e. an exiting control, clear the control if
4197          * the feature _is_ exposed to the guest, i.e. exiting/interception is
4198          * disabled for the associated instruction.  Note, the caller is
4199          * responsible presetting exec_control to set all supported bits.
4200          */
4201         if (enabled == exiting)
4202                 *exec_control &= ~control;
4203
4204         /*
4205          * Update the nested MSR settings so that a nested VMM can/can't set
4206          * controls for features that are/aren't exposed to the guest.
4207          */
4208         if (nested) {
4209                 if (enabled)
4210                         vmx->nested.msrs.secondary_ctls_high |= control;
4211                 else
4212                         vmx->nested.msrs.secondary_ctls_high &= ~control;
4213         }
4214 }
4215
4216 /*
4217  * Wrapper macro for the common case of adjusting a secondary execution control
4218  * based on a single guest CPUID bit, with a dedicated feature bit.  This also
4219  * verifies that the control is actually supported by KVM and hardware.
4220  */
4221 #define vmx_adjust_sec_exec_control(vmx, exec_control, name, feat_name, ctrl_name, exiting) \
4222 ({                                                                       \
4223         bool __enabled;                                                  \
4224                                                                          \
4225         if (cpu_has_vmx_##name()) {                                      \
4226                 __enabled = guest_cpuid_has(&(vmx)->vcpu,                \
4227                                             X86_FEATURE_##feat_name);    \
4228                 vmx_adjust_secondary_exec_control(vmx, exec_control,     \
4229                         SECONDARY_EXEC_##ctrl_name, __enabled, exiting); \
4230         }                                                                \
4231 })
4232
4233 /* More macro magic for ENABLE_/opt-in versus _EXITING/opt-out controls. */
4234 #define vmx_adjust_sec_exec_feature(vmx, exec_control, lname, uname) \
4235         vmx_adjust_sec_exec_control(vmx, exec_control, lname, uname, ENABLE_##uname, false)
4236
4237 #define vmx_adjust_sec_exec_exiting(vmx, exec_control, lname, uname) \
4238         vmx_adjust_sec_exec_control(vmx, exec_control, lname, uname, uname##_EXITING, true)
4239
4240 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4241 {
4242         struct kvm_vcpu *vcpu = &vmx->vcpu;
4243
4244         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4245
4246         if (vmx_pt_mode_is_system())
4247                 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
4248         if (!cpu_need_virtualize_apic_accesses(vcpu))
4249                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4250         if (vmx->vpid == 0)
4251                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4252         if (!enable_ept) {
4253                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4254                 enable_unrestricted_guest = 0;
4255         }
4256         if (!enable_unrestricted_guest)
4257                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4258         if (kvm_pause_in_guest(vmx->vcpu.kvm))
4259                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4260         if (!kvm_vcpu_apicv_active(vcpu))
4261                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4262                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4263         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4264
4265         /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
4266          * in vmx_set_cr4.  */
4267         exec_control &= ~SECONDARY_EXEC_DESC;
4268
4269         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4270            (handle_vmptrld).
4271            We can NOT enable shadow_vmcs here because we don't have yet
4272            a current VMCS12
4273         */
4274         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4275
4276         /*
4277          * PML is enabled/disabled when dirty logging of memsmlots changes, but
4278          * it needs to be set here when dirty logging is already active, e.g.
4279          * if this vCPU was created after dirty logging was enabled.
4280          */
4281         if (!vcpu->kvm->arch.cpu_dirty_logging_count)
4282                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4283
4284         if (cpu_has_vmx_xsaves()) {
4285                 /* Exposing XSAVES only when XSAVE is exposed */
4286                 bool xsaves_enabled =
4287                         boot_cpu_has(X86_FEATURE_XSAVE) &&
4288                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4289                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
4290
4291                 vcpu->arch.xsaves_enabled = xsaves_enabled;
4292
4293                 vmx_adjust_secondary_exec_control(vmx, &exec_control,
4294                                                   SECONDARY_EXEC_XSAVES,
4295                                                   xsaves_enabled, false);
4296         }
4297
4298         /*
4299          * RDPID is also gated by ENABLE_RDTSCP, turn on the control if either
4300          * feature is exposed to the guest.  This creates a virtualization hole
4301          * if both are supported in hardware but only one is exposed to the
4302          * guest, but letting the guest execute RDTSCP or RDPID when either one
4303          * is advertised is preferable to emulating the advertised instruction
4304          * in KVM on #UD, and obviously better than incorrectly injecting #UD.
4305          */
4306         if (cpu_has_vmx_rdtscp()) {
4307                 bool rdpid_or_rdtscp_enabled =
4308                         guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) ||
4309                         guest_cpuid_has(vcpu, X86_FEATURE_RDPID);
4310
4311                 vmx_adjust_secondary_exec_control(vmx, &exec_control,
4312                                                   SECONDARY_EXEC_ENABLE_RDTSCP,
4313                                                   rdpid_or_rdtscp_enabled, false);
4314         }
4315         vmx_adjust_sec_exec_feature(vmx, &exec_control, invpcid, INVPCID);
4316
4317         vmx_adjust_sec_exec_exiting(vmx, &exec_control, rdrand, RDRAND);
4318         vmx_adjust_sec_exec_exiting(vmx, &exec_control, rdseed, RDSEED);
4319
4320         vmx_adjust_sec_exec_control(vmx, &exec_control, waitpkg, WAITPKG,
4321                                     ENABLE_USR_WAIT_PAUSE, false);
4322
4323         if (!vcpu->kvm->arch.bus_lock_detection_enabled)
4324                 exec_control &= ~SECONDARY_EXEC_BUS_LOCK_DETECTION;
4325
4326         return exec_control;
4327 }
4328
4329 #define VMX_XSS_EXIT_BITMAP 0
4330
4331 /*
4332  * Noting that the initialization of Guest-state Area of VMCS is in
4333  * vmx_vcpu_reset().
4334  */
4335 static void init_vmcs(struct vcpu_vmx *vmx)
4336 {
4337         if (nested)
4338                 nested_vmx_set_vmcs_shadowing_bitmap();
4339
4340         if (cpu_has_vmx_msr_bitmap())
4341                 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
4342
4343         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4344
4345         /* Control */
4346         pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4347
4348         exec_controls_set(vmx, vmx_exec_control(vmx));
4349
4350         if (cpu_has_secondary_exec_ctrls())
4351                 secondary_exec_controls_set(vmx, vmx_secondary_exec_control(vmx));
4352
4353         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4354                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4355                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4356                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4357                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4358
4359                 vmcs_write16(GUEST_INTR_STATUS, 0);
4360
4361                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4362                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4363         }
4364
4365         if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4366                 vmcs_write32(PLE_GAP, ple_gap);
4367                 vmx->ple_window = ple_window;
4368                 vmx->ple_window_dirty = true;
4369         }
4370
4371         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4372         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4373         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4374
4375         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4376         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4377         vmx_set_constant_host_state(vmx);
4378         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4379         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4380
4381         if (cpu_has_vmx_vmfunc())
4382                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4383
4384         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4385         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4386         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
4387         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4388         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
4389
4390         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4391                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4392
4393         vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
4394
4395         /* 22.2.1, 20.8.1 */
4396         vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
4397
4398         vmx->vcpu.arch.cr0_guest_owned_bits = KVM_POSSIBLE_CR0_GUEST_BITS;
4399         vmcs_writel(CR0_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr0_guest_owned_bits);
4400
4401         set_cr4_guest_host_mask(vmx);
4402
4403         if (vmx->vpid != 0)
4404                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4405
4406         if (cpu_has_vmx_xsaves())
4407                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4408
4409         if (enable_pml) {
4410                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4411                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4412         }
4413
4414         vmx_write_encls_bitmap(&vmx->vcpu, NULL);
4415
4416         if (vmx_pt_mode_is_host_guest()) {
4417                 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4418                 /* Bit[6~0] are forced to 1, writes are ignored. */
4419                 vmx->pt_desc.guest.output_mask = 0x7F;
4420                 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4421         }
4422
4423         vmcs_write32(GUEST_SYSENTER_CS, 0);
4424         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4425         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4426         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4427
4428         if (cpu_has_vmx_tpr_shadow()) {
4429                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4430                 if (cpu_need_tpr_shadow(&vmx->vcpu))
4431                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4432                                      __pa(vmx->vcpu.arch.apic->regs));
4433                 vmcs_write32(TPR_THRESHOLD, 0);
4434         }
4435
4436         vmx_setup_uret_msrs(vmx);
4437 }
4438
4439 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4440 {
4441         struct vcpu_vmx *vmx = to_vmx(vcpu);
4442
4443         vmx->rmode.vm86_active = 0;
4444         vmx->spec_ctrl = 0;
4445
4446         vmx->msr_ia32_umwait_control = 0;
4447
4448         vmx->hv_deadline_tsc = -1;
4449         kvm_set_cr8(vcpu, 0);
4450
4451         vmx_segment_cache_clear(vmx);
4452
4453         seg_setup(VCPU_SREG_CS);
4454         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4455         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4456
4457         seg_setup(VCPU_SREG_DS);
4458         seg_setup(VCPU_SREG_ES);
4459         seg_setup(VCPU_SREG_FS);
4460         seg_setup(VCPU_SREG_GS);
4461         seg_setup(VCPU_SREG_SS);
4462
4463         vmcs_write16(GUEST_TR_SELECTOR, 0);
4464         vmcs_writel(GUEST_TR_BASE, 0);
4465         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4466         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4467
4468         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4469         vmcs_writel(GUEST_LDTR_BASE, 0);
4470         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4471         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4472
4473         vmcs_writel(GUEST_GDTR_BASE, 0);
4474         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4475
4476         vmcs_writel(GUEST_IDTR_BASE, 0);
4477         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4478
4479         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4480         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4481         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4482         if (kvm_mpx_supported())
4483                 vmcs_write64(GUEST_BNDCFGS, 0);
4484
4485         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4486
4487         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4488
4489         vpid_sync_context(vmx->vpid);
4490 }
4491
4492 static void vmx_enable_irq_window(struct kvm_vcpu *vcpu)
4493 {
4494         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
4495 }
4496
4497 static void vmx_enable_nmi_window(struct kvm_vcpu *vcpu)
4498 {
4499         if (!enable_vnmi ||
4500             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4501                 vmx_enable_irq_window(vcpu);
4502                 return;
4503         }
4504
4505         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
4506 }
4507
4508 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4509 {
4510         struct vcpu_vmx *vmx = to_vmx(vcpu);
4511         uint32_t intr;
4512         int irq = vcpu->arch.interrupt.nr;
4513
4514         trace_kvm_inj_virq(irq);
4515
4516         ++vcpu->stat.irq_injections;
4517         if (vmx->rmode.vm86_active) {
4518                 int inc_eip = 0;
4519                 if (vcpu->arch.interrupt.soft)
4520                         inc_eip = vcpu->arch.event_exit_inst_len;
4521                 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
4522                 return;
4523         }
4524         intr = irq | INTR_INFO_VALID_MASK;
4525         if (vcpu->arch.interrupt.soft) {
4526                 intr |= INTR_TYPE_SOFT_INTR;
4527                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4528                              vmx->vcpu.arch.event_exit_inst_len);
4529         } else
4530                 intr |= INTR_TYPE_EXT_INTR;
4531         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4532
4533         vmx_clear_hlt(vcpu);
4534 }
4535
4536 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4537 {
4538         struct vcpu_vmx *vmx = to_vmx(vcpu);
4539
4540         if (!enable_vnmi) {
4541                 /*
4542                  * Tracking the NMI-blocked state in software is built upon
4543                  * finding the next open IRQ window. This, in turn, depends on
4544                  * well-behaving guests: They have to keep IRQs disabled at
4545                  * least as long as the NMI handler runs. Otherwise we may
4546                  * cause NMI nesting, maybe breaking the guest. But as this is
4547                  * highly unlikely, we can live with the residual risk.
4548                  */
4549                 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4550                 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4551         }
4552
4553         ++vcpu->stat.nmi_injections;
4554         vmx->loaded_vmcs->nmi_known_unmasked = false;
4555
4556         if (vmx->rmode.vm86_active) {
4557                 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
4558                 return;
4559         }
4560
4561         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4562                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4563
4564         vmx_clear_hlt(vcpu);
4565 }
4566
4567 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4568 {
4569         struct vcpu_vmx *vmx = to_vmx(vcpu);
4570         bool masked;
4571
4572         if (!enable_vnmi)
4573                 return vmx->loaded_vmcs->soft_vnmi_blocked;
4574         if (vmx->loaded_vmcs->nmi_known_unmasked)
4575                 return false;
4576         masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4577         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4578         return masked;
4579 }
4580
4581 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4582 {
4583         struct vcpu_vmx *vmx = to_vmx(vcpu);
4584
4585         if (!enable_vnmi) {
4586                 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4587                         vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4588                         vmx->loaded_vmcs->vnmi_blocked_time = 0;
4589                 }
4590         } else {
4591                 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4592                 if (masked)
4593                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4594                                       GUEST_INTR_STATE_NMI);
4595                 else
4596                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4597                                         GUEST_INTR_STATE_NMI);
4598         }
4599 }
4600
4601 bool vmx_nmi_blocked(struct kvm_vcpu *vcpu)
4602 {
4603         if (is_guest_mode(vcpu) && nested_exit_on_nmi(vcpu))
4604                 return false;
4605
4606         if (!enable_vnmi && to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4607                 return true;
4608
4609         return (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4610                 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI |
4611                  GUEST_INTR_STATE_NMI));
4612 }
4613
4614 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4615 {
4616         if (to_vmx(vcpu)->nested.nested_run_pending)
4617                 return -EBUSY;
4618
4619         /* An NMI must not be injected into L2 if it's supposed to VM-Exit.  */
4620         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(vcpu))
4621                 return -EBUSY;
4622
4623         return !vmx_nmi_blocked(vcpu);
4624 }
4625
4626 bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu)
4627 {
4628         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4629                 return false;
4630
4631         return !(vmx_get_rflags(vcpu) & X86_EFLAGS_IF) ||
4632                (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4633                 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4634 }
4635
4636 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4637 {
4638         if (to_vmx(vcpu)->nested.nested_run_pending)
4639                 return -EBUSY;
4640
4641        /*
4642         * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
4643         * e.g. if the IRQ arrived asynchronously after checking nested events.
4644         */
4645         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4646                 return -EBUSY;
4647
4648         return !vmx_interrupt_blocked(vcpu);
4649 }
4650
4651 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4652 {
4653         void __user *ret;
4654
4655         if (enable_unrestricted_guest)
4656                 return 0;
4657
4658         mutex_lock(&kvm->slots_lock);
4659         ret = __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4660                                       PAGE_SIZE * 3);
4661         mutex_unlock(&kvm->slots_lock);
4662
4663         if (IS_ERR(ret))
4664                 return PTR_ERR(ret);
4665
4666         to_kvm_vmx(kvm)->tss_addr = addr;
4667
4668         return init_rmode_tss(kvm, ret);
4669 }
4670
4671 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4672 {
4673         to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
4674         return 0;
4675 }
4676
4677 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4678 {
4679         switch (vec) {
4680         case BP_VECTOR:
4681                 /*
4682                  * Update instruction length as we may reinject the exception
4683                  * from user space while in guest debugging mode.
4684                  */
4685                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4686                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4687                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4688                         return false;
4689                 fallthrough;
4690         case DB_VECTOR:
4691                 return !(vcpu->guest_debug &
4692                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP));
4693         case DE_VECTOR:
4694         case OF_VECTOR:
4695         case BR_VECTOR:
4696         case UD_VECTOR:
4697         case DF_VECTOR:
4698         case SS_VECTOR:
4699         case GP_VECTOR:
4700         case MF_VECTOR:
4701                 return true;
4702         }
4703         return false;
4704 }
4705
4706 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4707                                   int vec, u32 err_code)
4708 {
4709         /*
4710          * Instruction with address size override prefix opcode 0x67
4711          * Cause the #SS fault with 0 error code in VM86 mode.
4712          */
4713         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4714                 if (kvm_emulate_instruction(vcpu, 0)) {
4715                         if (vcpu->arch.halt_request) {
4716                                 vcpu->arch.halt_request = 0;
4717                                 return kvm_vcpu_halt(vcpu);
4718                         }
4719                         return 1;
4720                 }
4721                 return 0;
4722         }
4723
4724         /*
4725          * Forward all other exceptions that are valid in real mode.
4726          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4727          *        the required debugging infrastructure rework.
4728          */
4729         kvm_queue_exception(vcpu, vec);
4730         return 1;
4731 }
4732
4733 static int handle_machine_check(struct kvm_vcpu *vcpu)
4734 {
4735         /* handled by vmx_vcpu_run() */
4736         return 1;
4737 }
4738
4739 /*
4740  * If the host has split lock detection disabled, then #AC is
4741  * unconditionally injected into the guest, which is the pre split lock
4742  * detection behaviour.
4743  *
4744  * If the host has split lock detection enabled then #AC is
4745  * only injected into the guest when:
4746  *  - Guest CPL == 3 (user mode)
4747  *  - Guest has #AC detection enabled in CR0
4748  *  - Guest EFLAGS has AC bit set
4749  */
4750 bool vmx_guest_inject_ac(struct kvm_vcpu *vcpu)
4751 {
4752         if (!boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
4753                 return true;
4754
4755         return vmx_get_cpl(vcpu) == 3 && kvm_read_cr0_bits(vcpu, X86_CR0_AM) &&
4756                (kvm_get_rflags(vcpu) & X86_EFLAGS_AC);
4757 }
4758
4759 static int handle_exception_nmi(struct kvm_vcpu *vcpu)
4760 {
4761         struct vcpu_vmx *vmx = to_vmx(vcpu);
4762         struct kvm_run *kvm_run = vcpu->run;
4763         u32 intr_info, ex_no, error_code;
4764         unsigned long cr2, dr6;
4765         u32 vect_info;
4766
4767         vect_info = vmx->idt_vectoring_info;
4768         intr_info = vmx_get_intr_info(vcpu);
4769
4770         if (is_machine_check(intr_info) || is_nmi(intr_info))
4771                 return 1; /* handled by handle_exception_nmi_irqoff() */
4772
4773         if (is_invalid_opcode(intr_info))
4774                 return handle_ud(vcpu);
4775
4776         error_code = 0;
4777         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4778                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4779
4780         if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4781                 WARN_ON_ONCE(!enable_vmware_backdoor);
4782
4783                 /*
4784                  * VMware backdoor emulation on #GP interception only handles
4785                  * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
4786                  * error code on #GP.
4787                  */
4788                 if (error_code) {
4789                         kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4790                         return 1;
4791                 }
4792                 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
4793         }
4794
4795         /*
4796          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4797          * MMIO, it is better to report an internal error.
4798          * See the comments in vmx_handle_exit.
4799          */
4800         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4801             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4802                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4803                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4804                 vcpu->run->internal.ndata = 4;
4805                 vcpu->run->internal.data[0] = vect_info;
4806                 vcpu->run->internal.data[1] = intr_info;
4807                 vcpu->run->internal.data[2] = error_code;
4808                 vcpu->run->internal.data[3] = vcpu->arch.last_vmentry_cpu;
4809                 return 0;
4810         }
4811
4812         if (is_page_fault(intr_info)) {
4813                 cr2 = vmx_get_exit_qual(vcpu);
4814                 if (enable_ept && !vcpu->arch.apf.host_apf_flags) {
4815                         /*
4816                          * EPT will cause page fault only if we need to
4817                          * detect illegal GPAs.
4818                          */
4819                         WARN_ON_ONCE(!allow_smaller_maxphyaddr);
4820                         kvm_fixup_and_inject_pf_error(vcpu, cr2, error_code);
4821                         return 1;
4822                 } else
4823                         return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
4824         }
4825
4826         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4827
4828         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4829                 return handle_rmode_exception(vcpu, ex_no, error_code);
4830
4831         switch (ex_no) {
4832         case DB_VECTOR:
4833                 dr6 = vmx_get_exit_qual(vcpu);
4834                 if (!(vcpu->guest_debug &
4835                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4836                         if (is_icebp(intr_info))
4837                                 WARN_ON(!skip_emulated_instruction(vcpu));
4838
4839                         kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
4840                         return 1;
4841                 }
4842                 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW;
4843                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4844                 fallthrough;
4845         case BP_VECTOR:
4846                 /*
4847                  * Update instruction length as we may reinject #BP from
4848                  * user space while in guest debugging mode. Reading it for
4849                  * #DB as well causes no harm, it is not used in that case.
4850                  */
4851                 vmx->vcpu.arch.event_exit_inst_len =
4852                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4853                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4854                 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
4855                 kvm_run->debug.arch.exception = ex_no;
4856                 break;
4857         case AC_VECTOR:
4858                 if (vmx_guest_inject_ac(vcpu)) {
4859                         kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4860                         return 1;
4861                 }
4862
4863                 /*
4864                  * Handle split lock. Depending on detection mode this will
4865                  * either warn and disable split lock detection for this
4866                  * task or force SIGBUS on it.
4867                  */
4868                 if (handle_guest_split_lock(kvm_rip_read(vcpu)))
4869                         return 1;
4870                 fallthrough;
4871         default:
4872                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4873                 kvm_run->ex.exception = ex_no;
4874                 kvm_run->ex.error_code = error_code;
4875                 break;
4876         }
4877         return 0;
4878 }
4879
4880 static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu)
4881 {
4882         ++vcpu->stat.irq_exits;
4883         return 1;
4884 }
4885
4886 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4887 {
4888         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4889         vcpu->mmio_needed = 0;
4890         return 0;
4891 }
4892
4893 static int handle_io(struct kvm_vcpu *vcpu)
4894 {
4895         unsigned long exit_qualification;
4896         int size, in, string;
4897         unsigned port;
4898
4899         exit_qualification = vmx_get_exit_qual(vcpu);
4900         string = (exit_qualification & 16) != 0;
4901
4902         ++vcpu->stat.io_exits;
4903
4904         if (string)
4905                 return kvm_emulate_instruction(vcpu, 0);
4906
4907         port = exit_qualification >> 16;
4908         size = (exit_qualification & 7) + 1;
4909         in = (exit_qualification & 8) != 0;
4910
4911         return kvm_fast_pio(vcpu, size, port, in);
4912 }
4913
4914 static void
4915 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4916 {
4917         /*
4918          * Patch in the VMCALL instruction:
4919          */
4920         hypercall[0] = 0x0f;
4921         hypercall[1] = 0x01;
4922         hypercall[2] = 0xc1;
4923 }
4924
4925 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4926 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4927 {
4928         if (is_guest_mode(vcpu)) {
4929                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4930                 unsigned long orig_val = val;
4931
4932                 /*
4933                  * We get here when L2 changed cr0 in a way that did not change
4934                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4935                  * but did change L0 shadowed bits. So we first calculate the
4936                  * effective cr0 value that L1 would like to write into the
4937                  * hardware. It consists of the L2-owned bits from the new
4938                  * value combined with the L1-owned bits from L1's guest_cr0.
4939                  */
4940                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4941                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4942
4943                 if (!nested_guest_cr0_valid(vcpu, val))
4944                         return 1;
4945
4946                 if (kvm_set_cr0(vcpu, val))
4947                         return 1;
4948                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4949                 return 0;
4950         } else {
4951                 if (to_vmx(vcpu)->nested.vmxon &&
4952                     !nested_host_cr0_valid(vcpu, val))
4953                         return 1;
4954
4955                 return kvm_set_cr0(vcpu, val);
4956         }
4957 }
4958
4959 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4960 {
4961         if (is_guest_mode(vcpu)) {
4962                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4963                 unsigned long orig_val = val;
4964
4965                 /* analogously to handle_set_cr0 */
4966                 val = (val & ~vmcs12->cr4_guest_host_mask) |
4967                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4968                 if (kvm_set_cr4(vcpu, val))
4969                         return 1;
4970                 vmcs_writel(CR4_READ_SHADOW, orig_val);
4971                 return 0;
4972         } else
4973                 return kvm_set_cr4(vcpu, val);
4974 }
4975
4976 static int handle_desc(struct kvm_vcpu *vcpu)
4977 {
4978         WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
4979         return kvm_emulate_instruction(vcpu, 0);
4980 }
4981
4982 static int handle_cr(struct kvm_vcpu *vcpu)
4983 {
4984         unsigned long exit_qualification, val;
4985         int cr;
4986         int reg;
4987         int err;
4988         int ret;
4989
4990         exit_qualification = vmx_get_exit_qual(vcpu);
4991         cr = exit_qualification & 15;
4992         reg = (exit_qualification >> 8) & 15;
4993         switch ((exit_qualification >> 4) & 3) {
4994         case 0: /* mov to cr */
4995                 val = kvm_register_read(vcpu, reg);
4996                 trace_kvm_cr_write(cr, val);
4997                 switch (cr) {
4998                 case 0:
4999                         err = handle_set_cr0(vcpu, val);
5000                         return kvm_complete_insn_gp(vcpu, err);
5001                 case 3:
5002                         WARN_ON_ONCE(enable_unrestricted_guest);
5003
5004                         err = kvm_set_cr3(vcpu, val);
5005                         return kvm_complete_insn_gp(vcpu, err);
5006                 case 4:
5007                         err = handle_set_cr4(vcpu, val);
5008                         return kvm_complete_insn_gp(vcpu, err);
5009                 case 8: {
5010                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5011                                 u8 cr8 = (u8)val;
5012                                 err = kvm_set_cr8(vcpu, cr8);
5013                                 ret = kvm_complete_insn_gp(vcpu, err);
5014                                 if (lapic_in_kernel(vcpu))
5015                                         return ret;
5016                                 if (cr8_prev <= cr8)
5017                                         return ret;
5018                                 /*
5019                                  * TODO: we might be squashing a
5020                                  * KVM_GUESTDBG_SINGLESTEP-triggered
5021                                  * KVM_EXIT_DEBUG here.
5022                                  */
5023                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5024                                 return 0;
5025                         }
5026                 }
5027                 break;
5028         case 2: /* clts */
5029                 KVM_BUG(1, vcpu->kvm, "Guest always owns CR0.TS");
5030                 return -EIO;
5031         case 1: /*mov from cr*/
5032                 switch (cr) {
5033                 case 3:
5034                         WARN_ON_ONCE(enable_unrestricted_guest);
5035
5036                         val = kvm_read_cr3(vcpu);
5037                         kvm_register_write(vcpu, reg, val);
5038                         trace_kvm_cr_read(cr, val);
5039                         return kvm_skip_emulated_instruction(vcpu);
5040                 case 8:
5041                         val = kvm_get_cr8(vcpu);
5042                         kvm_register_write(vcpu, reg, val);
5043                         trace_kvm_cr_read(cr, val);
5044                         return kvm_skip_emulated_instruction(vcpu);
5045                 }
5046                 break;
5047         case 3: /* lmsw */
5048                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5049                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5050                 kvm_lmsw(vcpu, val);
5051
5052                 return kvm_skip_emulated_instruction(vcpu);
5053         default:
5054                 break;
5055         }
5056         vcpu->run->exit_reason = 0;
5057         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5058                (int)(exit_qualification >> 4) & 3, cr);
5059         return 0;
5060 }
5061
5062 static int handle_dr(struct kvm_vcpu *vcpu)
5063 {
5064         unsigned long exit_qualification;
5065         int dr, dr7, reg;
5066         int err = 1;
5067
5068         exit_qualification = vmx_get_exit_qual(vcpu);
5069         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5070
5071         /* First, if DR does not exist, trigger UD */
5072         if (!kvm_require_dr(vcpu, dr))
5073                 return 1;
5074
5075         if (kvm_x86_ops.get_cpl(vcpu) > 0)
5076                 goto out;
5077
5078         dr7 = vmcs_readl(GUEST_DR7);
5079         if (dr7 & DR7_GD) {
5080                 /*
5081                  * As the vm-exit takes precedence over the debug trap, we
5082                  * need to emulate the latter, either for the host or the
5083                  * guest debugging itself.
5084                  */
5085                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5086                         vcpu->run->debug.arch.dr6 = DR6_BD | DR6_ACTIVE_LOW;
5087                         vcpu->run->debug.arch.dr7 = dr7;
5088                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5089                         vcpu->run->debug.arch.exception = DB_VECTOR;
5090                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5091                         return 0;
5092                 } else {
5093                         kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BD);
5094                         return 1;
5095                 }
5096         }
5097
5098         if (vcpu->guest_debug == 0) {
5099                 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
5100
5101                 /*
5102                  * No more DR vmexits; force a reload of the debug registers
5103                  * and reenter on this instruction.  The next vmexit will
5104                  * retrieve the full state of the debug registers.
5105                  */
5106                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5107                 return 1;
5108         }
5109
5110         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5111         if (exit_qualification & TYPE_MOV_FROM_DR) {
5112                 unsigned long val;
5113
5114                 kvm_get_dr(vcpu, dr, &val);
5115                 kvm_register_write(vcpu, reg, val);
5116                 err = 0;
5117         } else {
5118                 err = kvm_set_dr(vcpu, dr, kvm_register_read(vcpu, reg));
5119         }
5120
5121 out:
5122         return kvm_complete_insn_gp(vcpu, err);
5123 }
5124
5125 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5126 {
5127         get_debugreg(vcpu->arch.db[0], 0);
5128         get_debugreg(vcpu->arch.db[1], 1);
5129         get_debugreg(vcpu->arch.db[2], 2);
5130         get_debugreg(vcpu->arch.db[3], 3);
5131         get_debugreg(vcpu->arch.dr6, 6);
5132         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5133
5134         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5135         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
5136
5137         /*
5138          * exc_debug expects dr6 to be cleared after it runs, avoid that it sees
5139          * a stale dr6 from the guest.
5140          */
5141         set_debugreg(DR6_RESERVED, 6);
5142 }
5143
5144 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5145 {
5146         vmcs_writel(GUEST_DR7, val);
5147 }
5148
5149 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5150 {
5151         kvm_apic_update_ppr(vcpu);
5152         return 1;
5153 }
5154
5155 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5156 {
5157         exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
5158
5159         kvm_make_request(KVM_REQ_EVENT, vcpu);
5160
5161         ++vcpu->stat.irq_window_exits;
5162         return 1;
5163 }
5164
5165 static int handle_invlpg(struct kvm_vcpu *vcpu)
5166 {
5167         unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5168
5169         kvm_mmu_invlpg(vcpu, exit_qualification);
5170         return kvm_skip_emulated_instruction(vcpu);
5171 }
5172
5173 static int handle_apic_access(struct kvm_vcpu *vcpu)
5174 {
5175         if (likely(fasteoi)) {
5176                 unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5177                 int access_type, offset;
5178
5179                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5180                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5181                 /*
5182                  * Sane guest uses MOV to write EOI, with written value
5183                  * not cared. So make a short-circuit here by avoiding
5184                  * heavy instruction emulation.
5185                  */
5186                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5187                     (offset == APIC_EOI)) {
5188                         kvm_lapic_set_eoi(vcpu);
5189                         return kvm_skip_emulated_instruction(vcpu);
5190                 }
5191         }
5192         return kvm_emulate_instruction(vcpu, 0);
5193 }
5194
5195 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5196 {
5197         unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5198         int vector = exit_qualification & 0xff;
5199
5200         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5201         kvm_apic_set_eoi_accelerated(vcpu, vector);
5202         return 1;
5203 }
5204
5205 static int handle_apic_write(struct kvm_vcpu *vcpu)
5206 {
5207         unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5208         u32 offset = exit_qualification & 0xfff;
5209
5210         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5211         kvm_apic_write_nodecode(vcpu, offset);
5212         return 1;
5213 }
5214
5215 static int handle_task_switch(struct kvm_vcpu *vcpu)
5216 {
5217         struct vcpu_vmx *vmx = to_vmx(vcpu);
5218         unsigned long exit_qualification;
5219         bool has_error_code = false;
5220         u32 error_code = 0;
5221         u16 tss_selector;
5222         int reason, type, idt_v, idt_index;
5223
5224         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5225         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5226         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5227
5228         exit_qualification = vmx_get_exit_qual(vcpu);
5229
5230         reason = (u32)exit_qualification >> 30;
5231         if (reason == TASK_SWITCH_GATE && idt_v) {
5232                 switch (type) {
5233                 case INTR_TYPE_NMI_INTR:
5234                         vcpu->arch.nmi_injected = false;
5235                         vmx_set_nmi_mask(vcpu, true);
5236                         break;
5237                 case INTR_TYPE_EXT_INTR:
5238                 case INTR_TYPE_SOFT_INTR:
5239                         kvm_clear_interrupt_queue(vcpu);
5240                         break;
5241                 case INTR_TYPE_HARD_EXCEPTION:
5242                         if (vmx->idt_vectoring_info &
5243                             VECTORING_INFO_DELIVER_CODE_MASK) {
5244                                 has_error_code = true;
5245                                 error_code =
5246                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5247                         }
5248                         fallthrough;
5249                 case INTR_TYPE_SOFT_EXCEPTION:
5250                         kvm_clear_exception_queue(vcpu);
5251                         break;
5252                 default:
5253                         break;
5254                 }
5255         }
5256         tss_selector = exit_qualification;
5257
5258         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5259                        type != INTR_TYPE_EXT_INTR &&
5260                        type != INTR_TYPE_NMI_INTR))
5261                 WARN_ON(!skip_emulated_instruction(vcpu));
5262
5263         /*
5264          * TODO: What about debug traps on tss switch?
5265          *       Are we supposed to inject them and update dr6?
5266          */
5267         return kvm_task_switch(vcpu, tss_selector,
5268                                type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
5269                                reason, has_error_code, error_code);
5270 }
5271
5272 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5273 {
5274         unsigned long exit_qualification;
5275         gpa_t gpa;
5276         u64 error_code;
5277
5278         exit_qualification = vmx_get_exit_qual(vcpu);
5279
5280         /*
5281          * EPT violation happened while executing iret from NMI,
5282          * "blocked by NMI" bit has to be set before next VM entry.
5283          * There are errata that may cause this bit to not be set:
5284          * AAK134, BY25.
5285          */
5286         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5287                         enable_vnmi &&
5288                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5289                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5290
5291         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5292         trace_kvm_page_fault(gpa, exit_qualification);
5293
5294         /* Is it a read fault? */
5295         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
5296                      ? PFERR_USER_MASK : 0;
5297         /* Is it a write fault? */
5298         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
5299                       ? PFERR_WRITE_MASK : 0;
5300         /* Is it a fetch fault? */
5301         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
5302                       ? PFERR_FETCH_MASK : 0;
5303         /* ept page table entry is present? */
5304         error_code |= (exit_qualification &
5305                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5306                         EPT_VIOLATION_EXECUTABLE))
5307                       ? PFERR_PRESENT_MASK : 0;
5308
5309         error_code |= (exit_qualification & EPT_VIOLATION_GVA_TRANSLATED) != 0 ?
5310                PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
5311
5312         vcpu->arch.exit_qualification = exit_qualification;
5313
5314         /*
5315          * Check that the GPA doesn't exceed physical memory limits, as that is
5316          * a guest page fault.  We have to emulate the instruction here, because
5317          * if the illegal address is that of a paging structure, then
5318          * EPT_VIOLATION_ACC_WRITE bit is set.  Alternatively, if supported we
5319          * would also use advanced VM-exit information for EPT violations to
5320          * reconstruct the page fault error code.
5321          */
5322         if (unlikely(allow_smaller_maxphyaddr && kvm_vcpu_is_illegal_gpa(vcpu, gpa)))
5323                 return kvm_emulate_instruction(vcpu, 0);
5324
5325         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5326 }
5327
5328 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5329 {
5330         gpa_t gpa;
5331
5332         if (!vmx_can_emulate_instruction(vcpu, NULL, 0))
5333                 return 1;
5334
5335         /*
5336          * A nested guest cannot optimize MMIO vmexits, because we have an
5337          * nGPA here instead of the required GPA.
5338          */
5339         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5340         if (!is_guest_mode(vcpu) &&
5341             !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5342                 trace_kvm_fast_mmio(gpa);
5343                 return kvm_skip_emulated_instruction(vcpu);
5344         }
5345
5346         return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
5347 }
5348
5349 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5350 {
5351         if (KVM_BUG_ON(!enable_vnmi, vcpu->kvm))
5352                 return -EIO;
5353
5354         exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
5355         ++vcpu->stat.nmi_window_exits;
5356         kvm_make_request(KVM_REQ_EVENT, vcpu);
5357
5358         return 1;
5359 }
5360
5361 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5362 {
5363         struct vcpu_vmx *vmx = to_vmx(vcpu);
5364         bool intr_window_requested;
5365         unsigned count = 130;
5366
5367         intr_window_requested = exec_controls_get(vmx) &
5368                                 CPU_BASED_INTR_WINDOW_EXITING;
5369
5370         while (vmx->emulation_required && count-- != 0) {
5371                 if (intr_window_requested && !vmx_interrupt_blocked(vcpu))
5372                         return handle_interrupt_window(&vmx->vcpu);
5373
5374                 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
5375                         return 1;
5376
5377                 if (!kvm_emulate_instruction(vcpu, 0))
5378                         return 0;
5379
5380                 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5381                     vcpu->arch.exception.pending) {
5382                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5383                         vcpu->run->internal.suberror =
5384                                                 KVM_INTERNAL_ERROR_EMULATION;
5385                         vcpu->run->internal.ndata = 0;
5386                         return 0;
5387                 }
5388
5389                 if (vcpu->arch.halt_request) {
5390                         vcpu->arch.halt_request = 0;
5391                         return kvm_vcpu_halt(vcpu);
5392                 }
5393
5394                 /*
5395                  * Note, return 1 and not 0, vcpu_run() will invoke
5396                  * xfer_to_guest_mode() which will create a proper return
5397                  * code.
5398                  */
5399                 if (__xfer_to_guest_mode_work_pending())
5400                         return 1;
5401         }
5402
5403         return 1;
5404 }
5405
5406 static void grow_ple_window(struct kvm_vcpu *vcpu)
5407 {
5408         struct vcpu_vmx *vmx = to_vmx(vcpu);
5409         unsigned int old = vmx->ple_window;
5410
5411         vmx->ple_window = __grow_ple_window(old, ple_window,
5412                                             ple_window_grow,
5413                                             ple_window_max);
5414
5415         if (vmx->ple_window != old) {
5416                 vmx->ple_window_dirty = true;
5417                 trace_kvm_ple_window_update(vcpu->vcpu_id,
5418                                             vmx->ple_window, old);
5419         }
5420 }
5421
5422 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5423 {
5424         struct vcpu_vmx *vmx = to_vmx(vcpu);
5425         unsigned int old = vmx->ple_window;
5426
5427         vmx->ple_window = __shrink_ple_window(old, ple_window,
5428                                               ple_window_shrink,
5429                                               ple_window);
5430
5431         if (vmx->ple_window != old) {
5432                 vmx->ple_window_dirty = true;
5433                 trace_kvm_ple_window_update(vcpu->vcpu_id,
5434                                             vmx->ple_window, old);
5435         }
5436 }
5437
5438 /*
5439  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5440  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5441  */
5442 static int handle_pause(struct kvm_vcpu *vcpu)
5443 {
5444         if (!kvm_pause_in_guest(vcpu->kvm))
5445                 grow_ple_window(vcpu);
5446
5447         /*
5448          * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5449          * VM-execution control is ignored if CPL > 0. OTOH, KVM
5450          * never set PAUSE_EXITING and just set PLE if supported,
5451          * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5452          */
5453         kvm_vcpu_on_spin(vcpu, true);
5454         return kvm_skip_emulated_instruction(vcpu);
5455 }
5456
5457 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5458 {
5459         return 1;
5460 }
5461
5462 static int handle_invpcid(struct kvm_vcpu *vcpu)
5463 {
5464         u32 vmx_instruction_info;
5465         unsigned long type;
5466         gva_t gva;
5467         struct {
5468                 u64 pcid;
5469                 u64 gla;
5470         } operand;
5471
5472         if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
5473                 kvm_queue_exception(vcpu, UD_VECTOR);
5474                 return 1;
5475         }
5476
5477         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5478         type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
5479
5480         if (type > 3) {
5481                 kvm_inject_gp(vcpu, 0);
5482                 return 1;
5483         }
5484
5485         /* According to the Intel instruction reference, the memory operand
5486          * is read even if it isn't needed (e.g., for type==all)
5487          */
5488         if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu),
5489                                 vmx_instruction_info, false,
5490                                 sizeof(operand), &gva))
5491                 return 1;
5492
5493         return kvm_handle_invpcid(vcpu, type, gva);
5494 }
5495
5496 static int handle_pml_full(struct kvm_vcpu *vcpu)
5497 {
5498         unsigned long exit_qualification;
5499
5500         trace_kvm_pml_full(vcpu->vcpu_id);
5501
5502         exit_qualification = vmx_get_exit_qual(vcpu);
5503
5504         /*
5505          * PML buffer FULL happened while executing iret from NMI,
5506          * "blocked by NMI" bit has to be set before next VM entry.
5507          */
5508         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5509                         enable_vnmi &&
5510                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5511                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5512                                 GUEST_INTR_STATE_NMI);
5513
5514         /*
5515          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5516          * here.., and there's no userspace involvement needed for PML.
5517          */
5518         return 1;
5519 }
5520
5521 static fastpath_t handle_fastpath_preemption_timer(struct kvm_vcpu *vcpu)
5522 {
5523         struct vcpu_vmx *vmx = to_vmx(vcpu);
5524
5525         if (!vmx->req_immediate_exit &&
5526             !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled)) {
5527                 kvm_lapic_expired_hv_timer(vcpu);
5528                 return EXIT_FASTPATH_REENTER_GUEST;
5529         }
5530
5531         return EXIT_FASTPATH_NONE;
5532 }
5533
5534 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
5535 {
5536         handle_fastpath_preemption_timer(vcpu);
5537         return 1;
5538 }
5539
5540 /*
5541  * When nested=0, all VMX instruction VM Exits filter here.  The handlers
5542  * are overwritten by nested_vmx_setup() when nested=1.
5543  */
5544 static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
5545 {
5546         kvm_queue_exception(vcpu, UD_VECTOR);
5547         return 1;
5548 }
5549
5550 #ifndef CONFIG_X86_SGX_KVM
5551 static int handle_encls(struct kvm_vcpu *vcpu)
5552 {
5553         /*
5554          * SGX virtualization is disabled.  There is no software enable bit for
5555          * SGX, so KVM intercepts all ENCLS leafs and injects a #UD to prevent
5556          * the guest from executing ENCLS (when SGX is supported by hardware).
5557          */
5558         kvm_queue_exception(vcpu, UD_VECTOR);
5559         return 1;
5560 }
5561 #endif /* CONFIG_X86_SGX_KVM */
5562
5563 static int handle_bus_lock_vmexit(struct kvm_vcpu *vcpu)
5564 {
5565         vcpu->run->exit_reason = KVM_EXIT_X86_BUS_LOCK;
5566         vcpu->run->flags |= KVM_RUN_X86_BUS_LOCK;
5567         return 0;
5568 }
5569
5570 /*
5571  * The exit handlers return 1 if the exit was handled fully and guest execution
5572  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5573  * to be done to userspace and return 0.
5574  */
5575 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5576         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception_nmi,
5577         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5578         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5579         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5580         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5581         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5582         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5583         [EXIT_REASON_CPUID]                   = kvm_emulate_cpuid,
5584         [EXIT_REASON_MSR_READ]                = kvm_emulate_rdmsr,
5585         [EXIT_REASON_MSR_WRITE]               = kvm_emulate_wrmsr,
5586         [EXIT_REASON_INTERRUPT_WINDOW]        = handle_interrupt_window,
5587         [EXIT_REASON_HLT]                     = kvm_emulate_halt,
5588         [EXIT_REASON_INVD]                    = kvm_emulate_invd,
5589         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5590         [EXIT_REASON_RDPMC]                   = kvm_emulate_rdpmc,
5591         [EXIT_REASON_VMCALL]                  = kvm_emulate_hypercall,
5592         [EXIT_REASON_VMCLEAR]                 = handle_vmx_instruction,
5593         [EXIT_REASON_VMLAUNCH]                = handle_vmx_instruction,
5594         [EXIT_REASON_VMPTRLD]                 = handle_vmx_instruction,
5595         [EXIT_REASON_VMPTRST]                 = handle_vmx_instruction,
5596         [EXIT_REASON_VMREAD]                  = handle_vmx_instruction,
5597         [EXIT_REASON_VMRESUME]                = handle_vmx_instruction,
5598         [EXIT_REASON_VMWRITE]                 = handle_vmx_instruction,
5599         [EXIT_REASON_VMOFF]                   = handle_vmx_instruction,
5600         [EXIT_REASON_VMON]                    = handle_vmx_instruction,
5601         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5602         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5603         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
5604         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
5605         [EXIT_REASON_WBINVD]                  = kvm_emulate_wbinvd,
5606         [EXIT_REASON_XSETBV]                  = kvm_emulate_xsetbv,
5607         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5608         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5609         [EXIT_REASON_GDTR_IDTR]               = handle_desc,
5610         [EXIT_REASON_LDTR_TR]                 = handle_desc,
5611         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5612         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5613         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5614         [EXIT_REASON_MWAIT_INSTRUCTION]       = kvm_emulate_mwait,
5615         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
5616         [EXIT_REASON_MONITOR_INSTRUCTION]     = kvm_emulate_monitor,
5617         [EXIT_REASON_INVEPT]                  = handle_vmx_instruction,
5618         [EXIT_REASON_INVVPID]                 = handle_vmx_instruction,
5619         [EXIT_REASON_RDRAND]                  = kvm_handle_invalid_op,
5620         [EXIT_REASON_RDSEED]                  = kvm_handle_invalid_op,
5621         [EXIT_REASON_PML_FULL]                = handle_pml_full,
5622         [EXIT_REASON_INVPCID]                 = handle_invpcid,
5623         [EXIT_REASON_VMFUNC]                  = handle_vmx_instruction,
5624         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
5625         [EXIT_REASON_ENCLS]                   = handle_encls,
5626         [EXIT_REASON_BUS_LOCK]                = handle_bus_lock_vmexit,
5627 };
5628
5629 static const int kvm_vmx_max_exit_handlers =
5630         ARRAY_SIZE(kvm_vmx_exit_handlers);
5631
5632 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2,
5633                               u32 *intr_info, u32 *error_code)
5634 {
5635         struct vcpu_vmx *vmx = to_vmx(vcpu);
5636
5637         *info1 = vmx_get_exit_qual(vcpu);
5638         if (!(vmx->exit_reason.failed_vmentry)) {
5639                 *info2 = vmx->idt_vectoring_info;
5640                 *intr_info = vmx_get_intr_info(vcpu);
5641                 if (is_exception_with_error_code(*intr_info))
5642                         *error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5643                 else
5644                         *error_code = 0;
5645         } else {
5646                 *info2 = 0;
5647                 *intr_info = 0;
5648                 *error_code = 0;
5649         }
5650 }
5651
5652 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
5653 {
5654         if (vmx->pml_pg) {
5655                 __free_page(vmx->pml_pg);
5656                 vmx->pml_pg = NULL;
5657         }
5658 }
5659
5660 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
5661 {
5662         struct vcpu_vmx *vmx = to_vmx(vcpu);
5663         u64 *pml_buf;
5664         u16 pml_idx;
5665
5666         pml_idx = vmcs_read16(GUEST_PML_INDEX);
5667
5668         /* Do nothing if PML buffer is empty */
5669         if (pml_idx == (PML_ENTITY_NUM - 1))
5670                 return;
5671
5672         /* PML index always points to next available PML buffer entity */
5673         if (pml_idx >= PML_ENTITY_NUM)
5674                 pml_idx = 0;
5675         else
5676                 pml_idx++;
5677
5678         pml_buf = page_address(vmx->pml_pg);
5679         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5680                 u64 gpa;
5681
5682                 gpa = pml_buf[pml_idx];
5683                 WARN_ON(gpa & (PAGE_SIZE - 1));
5684                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5685         }
5686
5687         /* reset PML index */
5688         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5689 }
5690
5691 static void vmx_dump_sel(char *name, uint32_t sel)
5692 {
5693         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5694                name, vmcs_read16(sel),
5695                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5696                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5697                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
5698 }
5699
5700 static void vmx_dump_dtsel(char *name, uint32_t limit)
5701 {
5702         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
5703                name, vmcs_read32(limit),
5704                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
5705 }
5706
5707 static void vmx_dump_msrs(char *name, struct vmx_msrs *m)
5708 {
5709         unsigned int i;
5710         struct vmx_msr_entry *e;
5711
5712         pr_err("MSR %s:\n", name);
5713         for (i = 0, e = m->val; i < m->nr; ++i, ++e)
5714                 pr_err("  %2d: msr=0x%08x value=0x%016llx\n", i, e->index, e->value);
5715 }
5716
5717 void dump_vmcs(struct kvm_vcpu *vcpu)
5718 {
5719         struct vcpu_vmx *vmx = to_vmx(vcpu);
5720         u32 vmentry_ctl, vmexit_ctl;
5721         u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5722         unsigned long cr4;
5723         int efer_slot;
5724
5725         if (!dump_invalid_vmcs) {
5726                 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5727                 return;
5728         }
5729
5730         vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5731         vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5732         cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5733         pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5734         cr4 = vmcs_readl(GUEST_CR4);
5735         secondary_exec_control = 0;
5736         if (cpu_has_secondary_exec_ctrls())
5737                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5738
5739         pr_err("VMCS %p, last attempted VM-entry on CPU %d\n",
5740                vmx->loaded_vmcs->vmcs, vcpu->arch.last_vmentry_cpu);
5741         pr_err("*** Guest State ***\n");
5742         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5743                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5744                vmcs_readl(CR0_GUEST_HOST_MASK));
5745         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5746                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5747         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5748         if (cpu_has_vmx_ept()) {
5749                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
5750                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5751                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
5752                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
5753         }
5754         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
5755                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5756         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
5757                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5758         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5759                vmcs_readl(GUEST_SYSENTER_ESP),
5760                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5761         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
5762         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
5763         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
5764         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
5765         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
5766         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
5767         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5768         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5769         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5770         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
5771         efer_slot = vmx_find_loadstore_msr_slot(&vmx->msr_autoload.guest, MSR_EFER);
5772         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_EFER)
5773                 pr_err("EFER= 0x%016llx\n", vmcs_read64(GUEST_IA32_EFER));
5774         else if (efer_slot >= 0)
5775                 pr_err("EFER= 0x%016llx (autoload)\n",
5776                        vmx->msr_autoload.guest.val[efer_slot].value);
5777         else if (vmentry_ctl & VM_ENTRY_IA32E_MODE)
5778                 pr_err("EFER= 0x%016llx (effective)\n",
5779                        vcpu->arch.efer | (EFER_LMA | EFER_LME));
5780         else
5781                 pr_err("EFER= 0x%016llx (effective)\n",
5782                        vcpu->arch.efer & ~(EFER_LMA | EFER_LME));
5783         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PAT)
5784                 pr_err("PAT = 0x%016llx\n", vmcs_read64(GUEST_IA32_PAT));
5785         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
5786                vmcs_read64(GUEST_IA32_DEBUGCTL),
5787                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5788         if (cpu_has_load_perf_global_ctrl() &&
5789             vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5790                 pr_err("PerfGlobCtl = 0x%016llx\n",
5791                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5792         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5793                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5794         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
5795                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5796                vmcs_read32(GUEST_ACTIVITY_STATE));
5797         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5798                 pr_err("InterruptStatus = %04x\n",
5799                        vmcs_read16(GUEST_INTR_STATUS));
5800         if (vmcs_read32(VM_ENTRY_MSR_LOAD_COUNT) > 0)
5801                 vmx_dump_msrs("guest autoload", &vmx->msr_autoload.guest);
5802         if (vmcs_read32(VM_EXIT_MSR_STORE_COUNT) > 0)
5803                 vmx_dump_msrs("guest autostore", &vmx->msr_autostore.guest);
5804
5805         pr_err("*** Host State ***\n");
5806         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
5807                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5808         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5809                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5810                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5811                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5812                vmcs_read16(HOST_TR_SELECTOR));
5813         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5814                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5815                vmcs_readl(HOST_TR_BASE));
5816         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5817                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5818         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5819                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5820                vmcs_readl(HOST_CR4));
5821         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5822                vmcs_readl(HOST_IA32_SYSENTER_ESP),
5823                vmcs_read32(HOST_IA32_SYSENTER_CS),
5824                vmcs_readl(HOST_IA32_SYSENTER_EIP));
5825         if (vmexit_ctl & VM_EXIT_LOAD_IA32_EFER)
5826                 pr_err("EFER= 0x%016llx\n", vmcs_read64(HOST_IA32_EFER));
5827         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PAT)
5828                 pr_err("PAT = 0x%016llx\n", vmcs_read64(HOST_IA32_PAT));
5829         if (cpu_has_load_perf_global_ctrl() &&
5830             vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5831                 pr_err("PerfGlobCtl = 0x%016llx\n",
5832                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
5833         if (vmcs_read32(VM_EXIT_MSR_LOAD_COUNT) > 0)
5834                 vmx_dump_msrs("host autoload", &vmx->msr_autoload.host);
5835
5836         pr_err("*** Control State ***\n");
5837         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5838                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5839         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5840         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5841                vmcs_read32(EXCEPTION_BITMAP),
5842                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5843                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5844         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5845                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5846                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5847                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5848         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5849                vmcs_read32(VM_EXIT_INTR_INFO),
5850                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5851                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5852         pr_err("        reason=%08x qualification=%016lx\n",
5853                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5854         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5855                vmcs_read32(IDT_VECTORING_INFO_FIELD),
5856                vmcs_read32(IDT_VECTORING_ERROR_CODE));
5857         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5858         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5859                 pr_err("TSC Multiplier = 0x%016llx\n",
5860                        vmcs_read64(TSC_MULTIPLIER));
5861         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5862                 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5863                         u16 status = vmcs_read16(GUEST_INTR_STATUS);
5864                         pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5865                 }
5866                 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
5867                 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5868                         pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
5869                 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
5870         }
5871         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5872                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5873         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5874                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5875         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5876                 pr_err("PLE Gap=%08x Window=%08x\n",
5877                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5878         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5879                 pr_err("Virtual processor ID = 0x%04x\n",
5880                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
5881 }
5882
5883 /*
5884  * The guest has exited.  See if we can fix it or if we need userspace
5885  * assistance.
5886  */
5887 static int __vmx_handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
5888 {
5889         struct vcpu_vmx *vmx = to_vmx(vcpu);
5890         union vmx_exit_reason exit_reason = vmx->exit_reason;
5891         u32 vectoring_info = vmx->idt_vectoring_info;
5892         u16 exit_handler_index;
5893
5894         /*
5895          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5896          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5897          * querying dirty_bitmap, we only need to kick all vcpus out of guest
5898          * mode as if vcpus is in root mode, the PML buffer must has been
5899          * flushed already.  Note, PML is never enabled in hardware while
5900          * running L2.
5901          */
5902         if (enable_pml && !is_guest_mode(vcpu))
5903                 vmx_flush_pml_buffer(vcpu);
5904
5905         /*
5906          * We should never reach this point with a pending nested VM-Enter, and
5907          * more specifically emulation of L2 due to invalid guest state (see
5908          * below) should never happen as that means we incorrectly allowed a
5909          * nested VM-Enter with an invalid vmcs12.
5910          */
5911         if (KVM_BUG_ON(vmx->nested.nested_run_pending, vcpu->kvm))
5912                 return -EIO;
5913
5914         /* If guest state is invalid, start emulating */
5915         if (vmx->emulation_required)
5916                 return handle_invalid_guest_state(vcpu);
5917
5918         if (is_guest_mode(vcpu)) {
5919                 /*
5920                  * PML is never enabled when running L2, bail immediately if a
5921                  * PML full exit occurs as something is horribly wrong.
5922                  */
5923                 if (exit_reason.basic == EXIT_REASON_PML_FULL)
5924                         goto unexpected_vmexit;
5925
5926                 /*
5927                  * The host physical addresses of some pages of guest memory
5928                  * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
5929                  * Page). The CPU may write to these pages via their host
5930                  * physical address while L2 is running, bypassing any
5931                  * address-translation-based dirty tracking (e.g. EPT write
5932                  * protection).
5933                  *
5934                  * Mark them dirty on every exit from L2 to prevent them from
5935                  * getting out of sync with dirty tracking.
5936                  */
5937                 nested_mark_vmcs12_pages_dirty(vcpu);
5938
5939                 if (nested_vmx_reflect_vmexit(vcpu))
5940                         return 1;
5941         }
5942
5943         if (exit_reason.failed_vmentry) {
5944                 dump_vmcs(vcpu);
5945                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5946                 vcpu->run->fail_entry.hardware_entry_failure_reason
5947                         = exit_reason.full;
5948                 vcpu->run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
5949                 return 0;
5950         }
5951
5952         if (unlikely(vmx->fail)) {
5953                 dump_vmcs(vcpu);
5954                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5955                 vcpu->run->fail_entry.hardware_entry_failure_reason
5956                         = vmcs_read32(VM_INSTRUCTION_ERROR);
5957                 vcpu->run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
5958                 return 0;
5959         }
5960
5961         /*
5962          * Note:
5963          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5964          * delivery event since it indicates guest is accessing MMIO.
5965          * The vm-exit can be triggered again after return to guest that
5966          * will cause infinite loop.
5967          */
5968         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5969             (exit_reason.basic != EXIT_REASON_EXCEPTION_NMI &&
5970              exit_reason.basic != EXIT_REASON_EPT_VIOLATION &&
5971              exit_reason.basic != EXIT_REASON_PML_FULL &&
5972              exit_reason.basic != EXIT_REASON_APIC_ACCESS &&
5973              exit_reason.basic != EXIT_REASON_TASK_SWITCH)) {
5974                 int ndata = 3;
5975
5976                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5977                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5978                 vcpu->run->internal.data[0] = vectoring_info;
5979                 vcpu->run->internal.data[1] = exit_reason.full;
5980                 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5981                 if (exit_reason.basic == EXIT_REASON_EPT_MISCONFIG) {
5982                         vcpu->run->internal.data[ndata++] =
5983                                 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5984                 }
5985                 vcpu->run->internal.data[ndata++] = vcpu->arch.last_vmentry_cpu;
5986                 vcpu->run->internal.ndata = ndata;
5987                 return 0;
5988         }
5989
5990         if (unlikely(!enable_vnmi &&
5991                      vmx->loaded_vmcs->soft_vnmi_blocked)) {
5992                 if (!vmx_interrupt_blocked(vcpu)) {
5993                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5994                 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5995                            vcpu->arch.nmi_pending) {
5996                         /*
5997                          * This CPU don't support us in finding the end of an
5998                          * NMI-blocked window if the guest runs with IRQs
5999                          * disabled. So we pull the trigger after 1 s of
6000                          * futile waiting, but inform the user about this.
6001                          */
6002                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6003                                "state on VCPU %d after 1 s timeout\n",
6004                                __func__, vcpu->vcpu_id);
6005                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
6006                 }
6007         }
6008
6009         if (exit_fastpath != EXIT_FASTPATH_NONE)
6010                 return 1;
6011
6012         if (exit_reason.basic >= kvm_vmx_max_exit_handlers)
6013                 goto unexpected_vmexit;
6014 #ifdef CONFIG_RETPOLINE
6015         if (exit_reason.basic == EXIT_REASON_MSR_WRITE)
6016                 return kvm_emulate_wrmsr(vcpu);
6017         else if (exit_reason.basic == EXIT_REASON_PREEMPTION_TIMER)
6018                 return handle_preemption_timer(vcpu);
6019         else if (exit_reason.basic == EXIT_REASON_INTERRUPT_WINDOW)
6020                 return handle_interrupt_window(vcpu);
6021         else if (exit_reason.basic == EXIT_REASON_EXTERNAL_INTERRUPT)
6022                 return handle_external_interrupt(vcpu);
6023         else if (exit_reason.basic == EXIT_REASON_HLT)
6024                 return kvm_emulate_halt(vcpu);
6025         else if (exit_reason.basic == EXIT_REASON_EPT_MISCONFIG)
6026                 return handle_ept_misconfig(vcpu);
6027 #endif
6028
6029         exit_handler_index = array_index_nospec((u16)exit_reason.basic,
6030                                                 kvm_vmx_max_exit_handlers);
6031         if (!kvm_vmx_exit_handlers[exit_handler_index])
6032                 goto unexpected_vmexit;
6033
6034         return kvm_vmx_exit_handlers[exit_handler_index](vcpu);
6035
6036 unexpected_vmexit:
6037         vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
6038                     exit_reason.full);
6039         dump_vmcs(vcpu);
6040         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6041         vcpu->run->internal.suberror =
6042                         KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
6043         vcpu->run->internal.ndata = 2;
6044         vcpu->run->internal.data[0] = exit_reason.full;
6045         vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
6046         return 0;
6047 }
6048
6049 static int vmx_handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
6050 {
6051         int ret = __vmx_handle_exit(vcpu, exit_fastpath);
6052
6053         /*
6054          * Even when current exit reason is handled by KVM internally, we
6055          * still need to exit to user space when bus lock detected to inform
6056          * that there is a bus lock in guest.
6057          */
6058         if (to_vmx(vcpu)->exit_reason.bus_lock_detected) {
6059                 if (ret > 0)
6060                         vcpu->run->exit_reason = KVM_EXIT_X86_BUS_LOCK;
6061
6062                 vcpu->run->flags |= KVM_RUN_X86_BUS_LOCK;
6063                 return 0;
6064         }
6065         return ret;
6066 }
6067
6068 /*
6069  * Software based L1D cache flush which is used when microcode providing
6070  * the cache control MSR is not loaded.
6071  *
6072  * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
6073  * flush it is required to read in 64 KiB because the replacement algorithm
6074  * is not exactly LRU. This could be sized at runtime via topology
6075  * information but as all relevant affected CPUs have 32KiB L1D cache size
6076  * there is no point in doing so.
6077  */
6078 static noinstr void vmx_l1d_flush(struct kvm_vcpu *vcpu)
6079 {
6080         int size = PAGE_SIZE << L1D_CACHE_ORDER;
6081
6082         /*
6083          * This code is only executed when the the flush mode is 'cond' or
6084          * 'always'
6085          */
6086         if (static_branch_likely(&vmx_l1d_flush_cond)) {
6087                 bool flush_l1d;
6088
6089                 /*
6090                  * Clear the per-vcpu flush bit, it gets set again
6091                  * either from vcpu_run() or from one of the unsafe
6092                  * VMEXIT handlers.
6093                  */
6094                 flush_l1d = vcpu->arch.l1tf_flush_l1d;
6095                 vcpu->arch.l1tf_flush_l1d = false;
6096
6097                 /*
6098                  * Clear the per-cpu flush bit, it gets set again from
6099                  * the interrupt handlers.
6100                  */
6101                 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
6102                 kvm_clear_cpu_l1tf_flush_l1d();
6103
6104                 if (!flush_l1d)
6105                         return;
6106         }
6107
6108         vcpu->stat.l1d_flush++;
6109
6110         if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
6111                 native_wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
6112                 return;
6113         }
6114
6115         asm volatile(
6116                 /* First ensure the pages are in the TLB */
6117                 "xorl   %%eax, %%eax\n"
6118                 ".Lpopulate_tlb:\n\t"
6119                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6120                 "addl   $4096, %%eax\n\t"
6121                 "cmpl   %%eax, %[size]\n\t"
6122                 "jne    .Lpopulate_tlb\n\t"
6123                 "xorl   %%eax, %%eax\n\t"
6124                 "cpuid\n\t"
6125                 /* Now fill the cache */
6126                 "xorl   %%eax, %%eax\n"
6127                 ".Lfill_cache:\n"
6128                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6129                 "addl   $64, %%eax\n\t"
6130                 "cmpl   %%eax, %[size]\n\t"
6131                 "jne    .Lfill_cache\n\t"
6132                 "lfence\n"
6133                 :: [flush_pages] "r" (vmx_l1d_flush_pages),
6134                     [size] "r" (size)
6135                 : "eax", "ebx", "ecx", "edx");
6136 }
6137
6138 static void vmx_update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6139 {
6140         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6141         int tpr_threshold;
6142
6143         if (is_guest_mode(vcpu) &&
6144                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
6145                 return;
6146
6147         tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr;
6148         if (is_guest_mode(vcpu))
6149                 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold;
6150         else
6151                 vmcs_write32(TPR_THRESHOLD, tpr_threshold);
6152 }
6153
6154 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
6155 {
6156         struct vcpu_vmx *vmx = to_vmx(vcpu);
6157         u32 sec_exec_control;
6158
6159         if (!lapic_in_kernel(vcpu))
6160                 return;
6161
6162         if (!flexpriority_enabled &&
6163             !cpu_has_vmx_virtualize_x2apic_mode())
6164                 return;
6165
6166         /* Postpone execution until vmcs01 is the current VMCS. */
6167         if (is_guest_mode(vcpu)) {
6168                 vmx->nested.change_vmcs01_virtual_apic_mode = true;
6169                 return;
6170         }
6171
6172         sec_exec_control = secondary_exec_controls_get(vmx);
6173         sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6174                               SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
6175
6176         switch (kvm_get_apic_mode(vcpu)) {
6177         case LAPIC_MODE_INVALID:
6178                 WARN_ONCE(true, "Invalid local APIC state");
6179                 break;
6180         case LAPIC_MODE_DISABLED:
6181                 break;
6182         case LAPIC_MODE_XAPIC:
6183                 if (flexpriority_enabled) {
6184                         sec_exec_control |=
6185                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6186                         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6187
6188                         /*
6189                          * Flush the TLB, reloading the APIC access page will
6190                          * only do so if its physical address has changed, but
6191                          * the guest may have inserted a non-APIC mapping into
6192                          * the TLB while the APIC access page was disabled.
6193                          */
6194                         kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
6195                 }
6196                 break;
6197         case LAPIC_MODE_X2APIC:
6198                 if (cpu_has_vmx_virtualize_x2apic_mode())
6199                         sec_exec_control |=
6200                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6201                 break;
6202         }
6203         secondary_exec_controls_set(vmx, sec_exec_control);
6204
6205         vmx_update_msr_bitmap_x2apic(vcpu);
6206 }
6207
6208 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu)
6209 {
6210         struct page *page;
6211
6212         /* Defer reload until vmcs01 is the current VMCS. */
6213         if (is_guest_mode(vcpu)) {
6214                 to_vmx(vcpu)->nested.reload_vmcs01_apic_access_page = true;
6215                 return;
6216         }
6217
6218         if (!(secondary_exec_controls_get(to_vmx(vcpu)) &
6219             SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
6220                 return;
6221
6222         page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6223         if (is_error_page(page))
6224                 return;
6225
6226         vmcs_write64(APIC_ACCESS_ADDR, page_to_phys(page));
6227         vmx_flush_tlb_current(vcpu);
6228
6229         /*
6230          * Do not pin apic access page in memory, the MMU notifier
6231          * will call us again if it is migrated or swapped out.
6232          */
6233         put_page(page);
6234 }
6235
6236 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6237 {
6238         u16 status;
6239         u8 old;
6240
6241         if (max_isr == -1)
6242                 max_isr = 0;
6243
6244         status = vmcs_read16(GUEST_INTR_STATUS);
6245         old = status >> 8;
6246         if (max_isr != old) {
6247                 status &= 0xff;
6248                 status |= max_isr << 8;
6249                 vmcs_write16(GUEST_INTR_STATUS, status);
6250         }
6251 }
6252
6253 static void vmx_set_rvi(int vector)
6254 {
6255         u16 status;
6256         u8 old;
6257
6258         if (vector == -1)
6259                 vector = 0;
6260
6261         status = vmcs_read16(GUEST_INTR_STATUS);
6262         old = (u8)status & 0xff;
6263         if ((u8)vector != old) {
6264                 status &= ~0xff;
6265                 status |= (u8)vector;
6266                 vmcs_write16(GUEST_INTR_STATUS, status);
6267         }
6268 }
6269
6270 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6271 {
6272         /*
6273          * When running L2, updating RVI is only relevant when
6274          * vmcs12 virtual-interrupt-delivery enabled.
6275          * However, it can be enabled only when L1 also
6276          * intercepts external-interrupts and in that case
6277          * we should not update vmcs02 RVI but instead intercept
6278          * interrupt. Therefore, do nothing when running L2.
6279          */
6280         if (!is_guest_mode(vcpu))
6281                 vmx_set_rvi(max_irr);
6282 }
6283
6284 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6285 {
6286         struct vcpu_vmx *vmx = to_vmx(vcpu);
6287         int max_irr;
6288         bool max_irr_updated;
6289
6290         if (KVM_BUG_ON(!vcpu->arch.apicv_active, vcpu->kvm))
6291                 return -EIO;
6292
6293         if (pi_test_on(&vmx->pi_desc)) {
6294                 pi_clear_on(&vmx->pi_desc);
6295                 /*
6296                  * IOMMU can write to PID.ON, so the barrier matters even on UP.
6297                  * But on x86 this is just a compiler barrier anyway.
6298                  */
6299                 smp_mb__after_atomic();
6300                 max_irr_updated =
6301                         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
6302
6303                 /*
6304                  * If we are running L2 and L1 has a new pending interrupt
6305                  * which can be injected, we should re-evaluate
6306                  * what should be done with this new L1 interrupt.
6307                  * If L1 intercepts external-interrupts, we should
6308                  * exit from L2 to L1. Otherwise, interrupt should be
6309                  * delivered directly to L2.
6310                  */
6311                 if (is_guest_mode(vcpu) && max_irr_updated) {
6312                         if (nested_exit_on_intr(vcpu))
6313                                 kvm_vcpu_exiting_guest_mode(vcpu);
6314                         else
6315                                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6316                 }
6317         } else {
6318                 max_irr = kvm_lapic_find_highest_irr(vcpu);
6319         }
6320         vmx_hwapic_irr_update(vcpu, max_irr);
6321         return max_irr;
6322 }
6323
6324 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6325 {
6326         if (!kvm_vcpu_apicv_active(vcpu))
6327                 return;
6328
6329         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6330         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6331         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6332         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6333 }
6334
6335 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
6336 {
6337         struct vcpu_vmx *vmx = to_vmx(vcpu);
6338
6339         pi_clear_on(&vmx->pi_desc);
6340         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6341 }
6342
6343 void vmx_do_interrupt_nmi_irqoff(unsigned long entry);
6344
6345 static void handle_interrupt_nmi_irqoff(struct kvm_vcpu *vcpu,
6346                                         unsigned long entry)
6347 {
6348         kvm_before_interrupt(vcpu);
6349         vmx_do_interrupt_nmi_irqoff(entry);
6350         kvm_after_interrupt(vcpu);
6351 }
6352
6353 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
6354 {
6355         const unsigned long nmi_entry = (unsigned long)asm_exc_nmi_noist;
6356         u32 intr_info = vmx_get_intr_info(&vmx->vcpu);
6357
6358         /* if exit due to PF check for async PF */
6359         if (is_page_fault(intr_info))
6360                 vmx->vcpu.arch.apf.host_apf_flags = kvm_read_and_reset_apf_flags();
6361         /* Handle machine checks before interrupts are enabled */
6362         else if (is_machine_check(intr_info))
6363                 kvm_machine_check();
6364         /* We need to handle NMIs before interrupts are enabled */
6365         else if (is_nmi(intr_info))
6366                 handle_interrupt_nmi_irqoff(&vmx->vcpu, nmi_entry);
6367 }
6368
6369 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
6370 {
6371         u32 intr_info = vmx_get_intr_info(vcpu);
6372         unsigned int vector = intr_info & INTR_INFO_VECTOR_MASK;
6373         gate_desc *desc = (gate_desc *)host_idt_base + vector;
6374
6375         if (KVM_BUG(!is_external_intr(intr_info), vcpu->kvm,
6376             "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6377                 return;
6378
6379         handle_interrupt_nmi_irqoff(vcpu, gate_offset(desc));
6380 }
6381
6382 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu)
6383 {
6384         struct vcpu_vmx *vmx = to_vmx(vcpu);
6385
6386         if (vmx->emulation_required)
6387                 return;
6388
6389         if (vmx->exit_reason.basic == EXIT_REASON_EXTERNAL_INTERRUPT)
6390                 handle_external_interrupt_irqoff(vcpu);
6391         else if (vmx->exit_reason.basic == EXIT_REASON_EXCEPTION_NMI)
6392                 handle_exception_nmi_irqoff(vmx);
6393 }
6394
6395 /*
6396  * The kvm parameter can be NULL (module initialization, or invocation before
6397  * VM creation). Be sure to check the kvm parameter before using it.
6398  */
6399 static bool vmx_has_emulated_msr(struct kvm *kvm, u32 index)
6400 {
6401         switch (index) {
6402         case MSR_IA32_SMBASE:
6403                 /*
6404                  * We cannot do SMM unless we can run the guest in big
6405                  * real mode.
6406                  */
6407                 return enable_unrestricted_guest || emulate_invalid_guest_state;
6408         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6409                 return nested;
6410         case MSR_AMD64_VIRT_SPEC_CTRL:
6411                 /* This is AMD only.  */
6412                 return false;
6413         default:
6414                 return true;
6415         }
6416 }
6417
6418 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6419 {
6420         u32 exit_intr_info;
6421         bool unblock_nmi;
6422         u8 vector;
6423         bool idtv_info_valid;
6424
6425         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6426
6427         if (enable_vnmi) {
6428                 if (vmx->loaded_vmcs->nmi_known_unmasked)
6429                         return;
6430
6431                 exit_intr_info = vmx_get_intr_info(&vmx->vcpu);
6432                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6433                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6434                 /*
6435                  * SDM 3: 27.7.1.2 (September 2008)
6436                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6437                  * a guest IRET fault.
6438                  * SDM 3: 23.2.2 (September 2008)
6439                  * Bit 12 is undefined in any of the following cases:
6440                  *  If the VM exit sets the valid bit in the IDT-vectoring
6441                  *   information field.
6442                  *  If the VM exit is due to a double fault.
6443                  */
6444                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6445                     vector != DF_VECTOR && !idtv_info_valid)
6446                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6447                                       GUEST_INTR_STATE_NMI);
6448                 else
6449                         vmx->loaded_vmcs->nmi_known_unmasked =
6450                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6451                                   & GUEST_INTR_STATE_NMI);
6452         } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6453                 vmx->loaded_vmcs->vnmi_blocked_time +=
6454                         ktime_to_ns(ktime_sub(ktime_get(),
6455                                               vmx->loaded_vmcs->entry_time));
6456 }
6457
6458 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6459                                       u32 idt_vectoring_info,
6460                                       int instr_len_field,
6461                                       int error_code_field)
6462 {
6463         u8 vector;
6464         int type;
6465         bool idtv_info_valid;
6466
6467         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6468
6469         vcpu->arch.nmi_injected = false;
6470         kvm_clear_exception_queue(vcpu);
6471         kvm_clear_interrupt_queue(vcpu);
6472
6473         if (!idtv_info_valid)
6474                 return;
6475
6476         kvm_make_request(KVM_REQ_EVENT, vcpu);
6477
6478         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6479         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6480
6481         switch (type) {
6482         case INTR_TYPE_NMI_INTR:
6483                 vcpu->arch.nmi_injected = true;
6484                 /*
6485                  * SDM 3: 27.7.1.2 (September 2008)
6486                  * Clear bit "block by NMI" before VM entry if a NMI
6487                  * delivery faulted.
6488                  */
6489                 vmx_set_nmi_mask(vcpu, false);
6490                 break;
6491         case INTR_TYPE_SOFT_EXCEPTION:
6492                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6493                 fallthrough;
6494         case INTR_TYPE_HARD_EXCEPTION:
6495                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6496                         u32 err = vmcs_read32(error_code_field);
6497                         kvm_requeue_exception_e(vcpu, vector, err);
6498                 } else
6499                         kvm_requeue_exception(vcpu, vector);
6500                 break;
6501         case INTR_TYPE_SOFT_INTR:
6502                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6503                 fallthrough;
6504         case INTR_TYPE_EXT_INTR:
6505                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6506                 break;
6507         default:
6508                 break;
6509         }
6510 }
6511
6512 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6513 {
6514         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6515                                   VM_EXIT_INSTRUCTION_LEN,
6516                                   IDT_VECTORING_ERROR_CODE);
6517 }
6518
6519 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6520 {
6521         __vmx_complete_interrupts(vcpu,
6522                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6523                                   VM_ENTRY_INSTRUCTION_LEN,
6524                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6525
6526         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6527 }
6528
6529 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6530 {
6531         int i, nr_msrs;
6532         struct perf_guest_switch_msr *msrs;
6533
6534         /* Note, nr_msrs may be garbage if perf_guest_get_msrs() returns NULL. */
6535         msrs = perf_guest_get_msrs(&nr_msrs);
6536         if (!msrs)
6537                 return;
6538
6539         for (i = 0; i < nr_msrs; i++)
6540                 if (msrs[i].host == msrs[i].guest)
6541                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6542                 else
6543                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6544                                         msrs[i].host, false);
6545 }
6546
6547 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
6548 {
6549         struct vcpu_vmx *vmx = to_vmx(vcpu);
6550         u64 tscl;
6551         u32 delta_tsc;
6552
6553         if (vmx->req_immediate_exit) {
6554                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6555                 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6556         } else if (vmx->hv_deadline_tsc != -1) {
6557                 tscl = rdtsc();
6558                 if (vmx->hv_deadline_tsc > tscl)
6559                         /* set_hv_timer ensures the delta fits in 32-bits */
6560                         delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6561                                 cpu_preemption_timer_multi);
6562                 else
6563                         delta_tsc = 0;
6564
6565                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6566                 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6567         } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6568                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6569                 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
6570         }
6571 }
6572
6573 void noinstr vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
6574 {
6575         if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6576                 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6577                 vmcs_writel(HOST_RSP, host_rsp);
6578         }
6579 }
6580
6581 static fastpath_t vmx_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
6582 {
6583         switch (to_vmx(vcpu)->exit_reason.basic) {
6584         case EXIT_REASON_MSR_WRITE:
6585                 return handle_fastpath_set_msr_irqoff(vcpu);
6586         case EXIT_REASON_PREEMPTION_TIMER:
6587                 return handle_fastpath_preemption_timer(vcpu);
6588         default:
6589                 return EXIT_FASTPATH_NONE;
6590         }
6591 }
6592
6593 static noinstr void vmx_vcpu_enter_exit(struct kvm_vcpu *vcpu,
6594                                         struct vcpu_vmx *vmx)
6595 {
6596         kvm_guest_enter_irqoff();
6597
6598         /* L1D Flush includes CPU buffer clear to mitigate MDS */
6599         if (static_branch_unlikely(&vmx_l1d_should_flush))
6600                 vmx_l1d_flush(vcpu);
6601         else if (static_branch_unlikely(&mds_user_clear))
6602                 mds_clear_cpu_buffers();
6603
6604         if (vcpu->arch.cr2 != native_read_cr2())
6605                 native_write_cr2(vcpu->arch.cr2);
6606
6607         vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6608                                    vmx->loaded_vmcs->launched);
6609
6610         vcpu->arch.cr2 = native_read_cr2();
6611
6612         kvm_guest_exit_irqoff();
6613 }
6614
6615 static fastpath_t vmx_vcpu_run(struct kvm_vcpu *vcpu)
6616 {
6617         struct vcpu_vmx *vmx = to_vmx(vcpu);
6618         unsigned long cr3, cr4;
6619
6620         /* Record the guest's net vcpu time for enforced NMI injections. */
6621         if (unlikely(!enable_vnmi &&
6622                      vmx->loaded_vmcs->soft_vnmi_blocked))
6623                 vmx->loaded_vmcs->entry_time = ktime_get();
6624
6625         /*
6626          * Don't enter VMX if guest state is invalid, let the exit handler
6627          * start emulation until we arrive back to a valid state.  Synthesize a
6628          * consistency check VM-Exit due to invalid guest state and bail.
6629          */
6630         if (unlikely(vmx->emulation_required)) {
6631
6632                 /* We don't emulate invalid state of a nested guest */
6633                 vmx->fail = is_guest_mode(vcpu);
6634
6635                 vmx->exit_reason.full = EXIT_REASON_INVALID_STATE;
6636                 vmx->exit_reason.failed_vmentry = 1;
6637                 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_1);
6638                 vmx->exit_qualification = ENTRY_FAIL_DEFAULT;
6639                 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_2);
6640                 vmx->exit_intr_info = 0;
6641                 return EXIT_FASTPATH_NONE;
6642         }
6643
6644         trace_kvm_entry(vcpu);
6645
6646         if (vmx->ple_window_dirty) {
6647                 vmx->ple_window_dirty = false;
6648                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6649         }
6650
6651         /*
6652          * We did this in prepare_switch_to_guest, because it needs to
6653          * be within srcu_read_lock.
6654          */
6655         WARN_ON_ONCE(vmx->nested.need_vmcs12_to_shadow_sync);
6656
6657         if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP))
6658                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6659         if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP))
6660                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6661
6662         cr3 = __get_current_cr3_fast();
6663         if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6664                 vmcs_writel(HOST_CR3, cr3);
6665                 vmx->loaded_vmcs->host_state.cr3 = cr3;
6666         }
6667
6668         cr4 = cr4_read_shadow();
6669         if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6670                 vmcs_writel(HOST_CR4, cr4);
6671                 vmx->loaded_vmcs->host_state.cr4 = cr4;
6672         }
6673
6674         /* When KVM_DEBUGREG_WONT_EXIT, dr6 is accessible in guest. */
6675         if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
6676                 set_debugreg(vcpu->arch.dr6, 6);
6677
6678         /* When single-stepping over STI and MOV SS, we must clear the
6679          * corresponding interruptibility bits in the guest state. Otherwise
6680          * vmentry fails as it then expects bit 14 (BS) in pending debug
6681          * exceptions being set, but that's not correct for the guest debugging
6682          * case. */
6683         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6684                 vmx_set_interrupt_shadow(vcpu, 0);
6685
6686         kvm_load_guest_xsave_state(vcpu);
6687
6688         pt_guest_enter(vmx);
6689
6690         atomic_switch_perf_msrs(vmx);
6691         if (intel_pmu_lbr_is_enabled(vcpu))
6692                 vmx_passthrough_lbr_msrs(vcpu);
6693
6694         if (enable_preemption_timer)
6695                 vmx_update_hv_timer(vcpu);
6696
6697         kvm_wait_lapic_expire(vcpu);
6698
6699         /*
6700          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6701          * it's non-zero. Since vmentry is serialising on affected CPUs, there
6702          * is no need to worry about the conditional branch over the wrmsr
6703          * being speculatively taken.
6704          */
6705         x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6706
6707         /* The actual VMENTER/EXIT is in the .noinstr.text section. */
6708         vmx_vcpu_enter_exit(vcpu, vmx);
6709
6710         /*
6711          * We do not use IBRS in the kernel. If this vCPU has used the
6712          * SPEC_CTRL MSR it may have left it on; save the value and
6713          * turn it off. This is much more efficient than blindly adding
6714          * it to the atomic save/restore list. Especially as the former
6715          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6716          *
6717          * For non-nested case:
6718          * If the L01 MSR bitmap does not intercept the MSR, then we need to
6719          * save it.
6720          *
6721          * For nested case:
6722          * If the L02 MSR bitmap does not intercept the MSR, then we need to
6723          * save it.
6724          */
6725         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6726                 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
6727
6728         x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
6729
6730         /* All fields are clean at this point */
6731         if (static_branch_unlikely(&enable_evmcs)) {
6732                 current_evmcs->hv_clean_fields |=
6733                         HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
6734
6735                 current_evmcs->hv_vp_id = kvm_hv_get_vpindex(vcpu);
6736         }
6737
6738         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6739         if (vmx->host_debugctlmsr)
6740                 update_debugctlmsr(vmx->host_debugctlmsr);
6741
6742 #ifndef CONFIG_X86_64
6743         /*
6744          * The sysexit path does not restore ds/es, so we must set them to
6745          * a reasonable value ourselves.
6746          *
6747          * We can't defer this to vmx_prepare_switch_to_host() since that
6748          * function may be executed in interrupt context, which saves and
6749          * restore segments around it, nullifying its effect.
6750          */
6751         loadsegment(ds, __USER_DS);
6752         loadsegment(es, __USER_DS);
6753 #endif
6754
6755         vmx_register_cache_reset(vcpu);
6756
6757         pt_guest_exit(vmx);
6758
6759         kvm_load_host_xsave_state(vcpu);
6760
6761         if (is_guest_mode(vcpu)) {
6762                 /*
6763                  * Track VMLAUNCH/VMRESUME that have made past guest state
6764                  * checking.
6765                  */
6766                 if (vmx->nested.nested_run_pending &&
6767                     !vmx->exit_reason.failed_vmentry)
6768                         ++vcpu->stat.nested_run;
6769
6770                 vmx->nested.nested_run_pending = 0;
6771         }
6772
6773         vmx->idt_vectoring_info = 0;
6774
6775         if (unlikely(vmx->fail)) {
6776                 vmx->exit_reason.full = 0xdead;
6777                 return EXIT_FASTPATH_NONE;
6778         }
6779
6780         vmx->exit_reason.full = vmcs_read32(VM_EXIT_REASON);
6781         if (unlikely((u16)vmx->exit_reason.basic == EXIT_REASON_MCE_DURING_VMENTRY))
6782                 kvm_machine_check();
6783
6784         if (likely(!vmx->exit_reason.failed_vmentry))
6785                 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6786
6787         trace_kvm_exit(vmx->exit_reason.full, vcpu, KVM_ISA_VMX);
6788
6789         if (unlikely(vmx->exit_reason.failed_vmentry))
6790                 return EXIT_FASTPATH_NONE;
6791
6792         vmx->loaded_vmcs->launched = 1;
6793
6794         vmx_recover_nmi_blocking(vmx);
6795         vmx_complete_interrupts(vmx);
6796
6797         if (is_guest_mode(vcpu))
6798                 return EXIT_FASTPATH_NONE;
6799
6800         return vmx_exit_handlers_fastpath(vcpu);
6801 }
6802
6803 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6804 {
6805         struct vcpu_vmx *vmx = to_vmx(vcpu);
6806
6807         if (enable_pml)
6808                 vmx_destroy_pml_buffer(vmx);
6809         free_vpid(vmx->vpid);
6810         nested_vmx_free_vcpu(vcpu);
6811         free_loaded_vmcs(vmx->loaded_vmcs);
6812 }
6813
6814 static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
6815 {
6816         struct vmx_uret_msr *tsx_ctrl;
6817         struct vcpu_vmx *vmx;
6818         int i, cpu, err;
6819
6820         BUILD_BUG_ON(offsetof(struct vcpu_vmx, vcpu) != 0);
6821         vmx = to_vmx(vcpu);
6822
6823         err = -ENOMEM;
6824
6825         vmx->vpid = allocate_vpid();
6826
6827         /*
6828          * If PML is turned on, failure on enabling PML just results in failure
6829          * of creating the vcpu, therefore we can simplify PML logic (by
6830          * avoiding dealing with cases, such as enabling PML partially on vcpus
6831          * for the guest), etc.
6832          */
6833         if (enable_pml) {
6834                 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
6835                 if (!vmx->pml_pg)
6836                         goto free_vpid;
6837         }
6838
6839         for (i = 0; i < kvm_nr_uret_msrs; ++i) {
6840                 vmx->guest_uret_msrs[i].data = 0;
6841                 vmx->guest_uret_msrs[i].mask = -1ull;
6842         }
6843         if (boot_cpu_has(X86_FEATURE_RTM)) {
6844                 /*
6845                  * TSX_CTRL_CPUID_CLEAR is handled in the CPUID interception.
6846                  * Keep the host value unchanged to avoid changing CPUID bits
6847                  * under the host kernel's feet.
6848                  */
6849                 tsx_ctrl = vmx_find_uret_msr(vmx, MSR_IA32_TSX_CTRL);
6850                 if (tsx_ctrl)
6851                         tsx_ctrl->mask = ~(u64)TSX_CTRL_CPUID_CLEAR;
6852         }
6853
6854         err = alloc_loaded_vmcs(&vmx->vmcs01);
6855         if (err < 0)
6856                 goto free_pml;
6857
6858         /* The MSR bitmap starts with all ones */
6859         bitmap_fill(vmx->shadow_msr_intercept.read, MAX_POSSIBLE_PASSTHROUGH_MSRS);
6860         bitmap_fill(vmx->shadow_msr_intercept.write, MAX_POSSIBLE_PASSTHROUGH_MSRS);
6861
6862         vmx_disable_intercept_for_msr(vcpu, MSR_IA32_TSC, MSR_TYPE_R);
6863 #ifdef CONFIG_X86_64
6864         vmx_disable_intercept_for_msr(vcpu, MSR_FS_BASE, MSR_TYPE_RW);
6865         vmx_disable_intercept_for_msr(vcpu, MSR_GS_BASE, MSR_TYPE_RW);
6866         vmx_disable_intercept_for_msr(vcpu, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6867 #endif
6868         vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6869         vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6870         vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
6871         if (kvm_cstate_in_guest(vcpu->kvm)) {
6872                 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C1_RES, MSR_TYPE_R);
6873                 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6874                 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6875                 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6876         }
6877
6878         vmx->loaded_vmcs = &vmx->vmcs01;
6879         cpu = get_cpu();
6880         vmx_vcpu_load(vcpu, cpu);
6881         vcpu->cpu = cpu;
6882         init_vmcs(vmx);
6883         vmx_vcpu_put(vcpu);
6884         put_cpu();
6885         if (cpu_need_virtualize_apic_accesses(vcpu)) {
6886                 err = alloc_apic_access_page(vcpu->kvm);
6887                 if (err)
6888                         goto free_vmcs;
6889         }
6890
6891         if (enable_ept && !enable_unrestricted_guest) {
6892                 err = init_rmode_identity_map(vcpu->kvm);
6893                 if (err)
6894                         goto free_vmcs;
6895         }
6896
6897         if (nested)
6898                 memcpy(&vmx->nested.msrs, &vmcs_config.nested, sizeof(vmx->nested.msrs));
6899         else
6900                 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
6901
6902         vcpu_setup_sgx_lepubkeyhash(vcpu);
6903
6904         vmx->nested.posted_intr_nv = -1;
6905         vmx->nested.current_vmptr = -1ull;
6906         vmx->nested.hv_evmcs_vmptr = EVMPTR_INVALID;
6907
6908         vcpu->arch.microcode_version = 0x100000000ULL;
6909         vmx->msr_ia32_feature_control_valid_bits = FEAT_CTL_LOCKED;
6910
6911         /*
6912          * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
6913          * or POSTED_INTR_WAKEUP_VECTOR.
6914          */
6915         vmx->pi_desc.nv = POSTED_INTR_VECTOR;
6916         vmx->pi_desc.sn = 1;
6917
6918         return 0;
6919
6920 free_vmcs:
6921         free_loaded_vmcs(vmx->loaded_vmcs);
6922 free_pml:
6923         vmx_destroy_pml_buffer(vmx);
6924 free_vpid:
6925         free_vpid(vmx->vpid);
6926         return err;
6927 }
6928
6929 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6930 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6931
6932 static int vmx_vm_init(struct kvm *kvm)
6933 {
6934         if (!ple_gap)
6935                 kvm->arch.pause_in_guest = true;
6936
6937         if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6938                 switch (l1tf_mitigation) {
6939                 case L1TF_MITIGATION_OFF:
6940                 case L1TF_MITIGATION_FLUSH_NOWARN:
6941                         /* 'I explicitly don't care' is set */
6942                         break;
6943                 case L1TF_MITIGATION_FLUSH:
6944                 case L1TF_MITIGATION_FLUSH_NOSMT:
6945                 case L1TF_MITIGATION_FULL:
6946                         /*
6947                          * Warn upon starting the first VM in a potentially
6948                          * insecure environment.
6949                          */
6950                         if (sched_smt_active())
6951                                 pr_warn_once(L1TF_MSG_SMT);
6952                         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6953                                 pr_warn_once(L1TF_MSG_L1D);
6954                         break;
6955                 case L1TF_MITIGATION_FULL_FORCE:
6956                         /* Flush is enforced */
6957                         break;
6958                 }
6959         }
6960         return 0;
6961 }
6962
6963 static int __init vmx_check_processor_compat(void)
6964 {
6965         struct vmcs_config vmcs_conf;
6966         struct vmx_capability vmx_cap;
6967
6968         if (!this_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
6969             !this_cpu_has(X86_FEATURE_VMX)) {
6970                 pr_err("kvm: VMX is disabled on CPU %d\n", smp_processor_id());
6971                 return -EIO;
6972         }
6973
6974         if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
6975                 return -EIO;
6976         if (nested)
6977                 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept);
6978         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6979                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6980                                 smp_processor_id());
6981                 return -EIO;
6982         }
6983         return 0;
6984 }
6985
6986 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6987 {
6988         u8 cache;
6989         u64 ipat = 0;
6990
6991         /* We wanted to honor guest CD/MTRR/PAT, but doing so could result in
6992          * memory aliases with conflicting memory types and sometimes MCEs.
6993          * We have to be careful as to what are honored and when.
6994          *
6995          * For MMIO, guest CD/MTRR are ignored.  The EPT memory type is set to
6996          * UC.  The effective memory type is UC or WC depending on guest PAT.
6997          * This was historically the source of MCEs and we want to be
6998          * conservative.
6999          *
7000          * When there is no need to deal with noncoherent DMA (e.g., no VT-d
7001          * or VT-d has snoop control), guest CD/MTRR/PAT are all ignored.  The
7002          * EPT memory type is set to WB.  The effective memory type is forced
7003          * WB.
7004          *
7005          * Otherwise, we trust guest.  Guest CD/MTRR/PAT are all honored.  The
7006          * EPT memory type is used to emulate guest CD/MTRR.
7007          */
7008
7009         if (is_mmio) {
7010                 cache = MTRR_TYPE_UNCACHABLE;
7011                 goto exit;
7012         }
7013
7014         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
7015                 ipat = VMX_EPT_IPAT_BIT;
7016                 cache = MTRR_TYPE_WRBACK;
7017                 goto exit;
7018         }
7019
7020         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
7021                 ipat = VMX_EPT_IPAT_BIT;
7022                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
7023                         cache = MTRR_TYPE_WRBACK;
7024                 else
7025                         cache = MTRR_TYPE_UNCACHABLE;
7026                 goto exit;
7027         }
7028
7029         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
7030
7031 exit:
7032         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
7033 }
7034
7035 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx, u32 new_ctl)
7036 {
7037         /*
7038          * These bits in the secondary execution controls field
7039          * are dynamic, the others are mostly based on the hypervisor
7040          * architecture and the guest's CPUID.  Do not touch the
7041          * dynamic bits.
7042          */
7043         u32 mask =
7044                 SECONDARY_EXEC_SHADOW_VMCS |
7045                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
7046                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
7047                 SECONDARY_EXEC_DESC;
7048
7049         u32 cur_ctl = secondary_exec_controls_get(vmx);
7050
7051         secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
7052 }
7053
7054 /*
7055  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
7056  * (indicating "allowed-1") if they are supported in the guest's CPUID.
7057  */
7058 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
7059 {
7060         struct vcpu_vmx *vmx = to_vmx(vcpu);
7061         struct kvm_cpuid_entry2 *entry;
7062
7063         vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
7064         vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
7065
7066 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
7067         if (entry && (entry->_reg & (_cpuid_mask)))                     \
7068                 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask);     \
7069 } while (0)
7070
7071         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
7072         cr4_fixed1_update(X86_CR4_VME,        edx, feature_bit(VME));
7073         cr4_fixed1_update(X86_CR4_PVI,        edx, feature_bit(VME));
7074         cr4_fixed1_update(X86_CR4_TSD,        edx, feature_bit(TSC));
7075         cr4_fixed1_update(X86_CR4_DE,         edx, feature_bit(DE));
7076         cr4_fixed1_update(X86_CR4_PSE,        edx, feature_bit(PSE));
7077         cr4_fixed1_update(X86_CR4_PAE,        edx, feature_bit(PAE));
7078         cr4_fixed1_update(X86_CR4_MCE,        edx, feature_bit(MCE));
7079         cr4_fixed1_update(X86_CR4_PGE,        edx, feature_bit(PGE));
7080         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, feature_bit(FXSR));
7081         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, feature_bit(XMM));
7082         cr4_fixed1_update(X86_CR4_VMXE,       ecx, feature_bit(VMX));
7083         cr4_fixed1_update(X86_CR4_SMXE,       ecx, feature_bit(SMX));
7084         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, feature_bit(PCID));
7085         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, feature_bit(XSAVE));
7086
7087         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7088         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, feature_bit(FSGSBASE));
7089         cr4_fixed1_update(X86_CR4_SMEP,       ebx, feature_bit(SMEP));
7090         cr4_fixed1_update(X86_CR4_SMAP,       ebx, feature_bit(SMAP));
7091         cr4_fixed1_update(X86_CR4_PKE,        ecx, feature_bit(PKU));
7092         cr4_fixed1_update(X86_CR4_UMIP,       ecx, feature_bit(UMIP));
7093         cr4_fixed1_update(X86_CR4_LA57,       ecx, feature_bit(LA57));
7094
7095 #undef cr4_fixed1_update
7096 }
7097
7098 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
7099 {
7100         struct vcpu_vmx *vmx = to_vmx(vcpu);
7101
7102         if (kvm_mpx_supported()) {
7103                 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
7104
7105                 if (mpx_enabled) {
7106                         vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
7107                         vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
7108                 } else {
7109                         vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
7110                         vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
7111                 }
7112         }
7113 }
7114
7115 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
7116 {
7117         struct vcpu_vmx *vmx = to_vmx(vcpu);
7118         struct kvm_cpuid_entry2 *best = NULL;
7119         int i;
7120
7121         for (i = 0; i < PT_CPUID_LEAVES; i++) {
7122                 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
7123                 if (!best)
7124                         return;
7125                 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
7126                 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
7127                 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
7128                 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
7129         }
7130
7131         /* Get the number of configurable Address Ranges for filtering */
7132         vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
7133                                                 PT_CAP_num_address_ranges);
7134
7135         /* Initialize and clear the no dependency bits */
7136         vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
7137                         RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
7138
7139         /*
7140          * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
7141          * will inject an #GP
7142          */
7143         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
7144                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
7145
7146         /*
7147          * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
7148          * PSBFreq can be set
7149          */
7150         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
7151                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
7152                                 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
7153
7154         /*
7155          * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
7156          * MTCFreq can be set
7157          */
7158         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
7159                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
7160                                 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
7161
7162         /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
7163         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
7164                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
7165                                                         RTIT_CTL_PTW_EN);
7166
7167         /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7168         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
7169                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
7170
7171         /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7172         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
7173                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
7174
7175         /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabricEn can be set */
7176         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
7177                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
7178
7179         /* unmask address range configure area */
7180         for (i = 0; i < vmx->pt_desc.addr_range; i++)
7181                 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
7182 }
7183
7184 static void vmx_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
7185 {
7186         struct vcpu_vmx *vmx = to_vmx(vcpu);
7187
7188         /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */
7189         vcpu->arch.xsaves_enabled = false;
7190
7191         vmx_setup_uret_msrs(vmx);
7192
7193         if (cpu_has_secondary_exec_ctrls())
7194                 vmcs_set_secondary_exec_control(vmx,
7195                                                 vmx_secondary_exec_control(vmx));
7196
7197         if (nested_vmx_allowed(vcpu))
7198                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7199                         FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7200                         FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX;
7201         else
7202                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7203                         ~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7204                           FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX);
7205
7206         if (nested_vmx_allowed(vcpu)) {
7207                 nested_vmx_cr_fixed1_bits_update(vcpu);
7208                 nested_vmx_entry_exit_ctls_update(vcpu);
7209         }
7210
7211         if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7212                         guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7213                 update_intel_pt_cfg(vcpu);
7214
7215         if (boot_cpu_has(X86_FEATURE_RTM)) {
7216                 struct vmx_uret_msr *msr;
7217                 msr = vmx_find_uret_msr(vmx, MSR_IA32_TSX_CTRL);
7218                 if (msr) {
7219                         bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM);
7220                         vmx_set_guest_uret_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE);
7221                 }
7222         }
7223
7224         set_cr4_guest_host_mask(vmx);
7225
7226         vmx_write_encls_bitmap(vcpu, NULL);
7227         if (guest_cpuid_has(vcpu, X86_FEATURE_SGX))
7228                 vmx->msr_ia32_feature_control_valid_bits |= FEAT_CTL_SGX_ENABLED;
7229         else
7230                 vmx->msr_ia32_feature_control_valid_bits &= ~FEAT_CTL_SGX_ENABLED;
7231
7232         if (guest_cpuid_has(vcpu, X86_FEATURE_SGX_LC))
7233                 vmx->msr_ia32_feature_control_valid_bits |=
7234                         FEAT_CTL_SGX_LC_ENABLED;
7235         else
7236                 vmx->msr_ia32_feature_control_valid_bits &=
7237                         ~FEAT_CTL_SGX_LC_ENABLED;
7238
7239         /* Refresh #PF interception to account for MAXPHYADDR changes. */
7240         vmx_update_exception_bitmap(vcpu);
7241 }
7242
7243 static __init void vmx_set_cpu_caps(void)
7244 {
7245         kvm_set_cpu_caps();
7246
7247         /* CPUID 0x1 */
7248         if (nested)
7249                 kvm_cpu_cap_set(X86_FEATURE_VMX);
7250
7251         /* CPUID 0x7 */
7252         if (kvm_mpx_supported())
7253                 kvm_cpu_cap_check_and_set(X86_FEATURE_MPX);
7254         if (!cpu_has_vmx_invpcid())
7255                 kvm_cpu_cap_clear(X86_FEATURE_INVPCID);
7256         if (vmx_pt_mode_is_host_guest())
7257                 kvm_cpu_cap_check_and_set(X86_FEATURE_INTEL_PT);
7258
7259         if (!enable_sgx) {
7260                 kvm_cpu_cap_clear(X86_FEATURE_SGX);
7261                 kvm_cpu_cap_clear(X86_FEATURE_SGX_LC);
7262                 kvm_cpu_cap_clear(X86_FEATURE_SGX1);
7263                 kvm_cpu_cap_clear(X86_FEATURE_SGX2);
7264         }
7265
7266         if (vmx_umip_emulated())
7267                 kvm_cpu_cap_set(X86_FEATURE_UMIP);
7268
7269         /* CPUID 0xD.1 */
7270         supported_xss = 0;
7271         if (!cpu_has_vmx_xsaves())
7272                 kvm_cpu_cap_clear(X86_FEATURE_XSAVES);
7273
7274         /* CPUID 0x80000001 and 0x7 (RDPID) */
7275         if (!cpu_has_vmx_rdtscp()) {
7276                 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP);
7277                 kvm_cpu_cap_clear(X86_FEATURE_RDPID);
7278         }
7279
7280         if (cpu_has_vmx_waitpkg())
7281                 kvm_cpu_cap_check_and_set(X86_FEATURE_WAITPKG);
7282 }
7283
7284 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
7285 {
7286         to_vmx(vcpu)->req_immediate_exit = true;
7287 }
7288
7289 static int vmx_check_intercept_io(struct kvm_vcpu *vcpu,
7290                                   struct x86_instruction_info *info)
7291 {
7292         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7293         unsigned short port;
7294         bool intercept;
7295         int size;
7296
7297         if (info->intercept == x86_intercept_in ||
7298             info->intercept == x86_intercept_ins) {
7299                 port = info->src_val;
7300                 size = info->dst_bytes;
7301         } else {
7302                 port = info->dst_val;
7303                 size = info->src_bytes;
7304         }
7305
7306         /*
7307          * If the 'use IO bitmaps' VM-execution control is 0, IO instruction
7308          * VM-exits depend on the 'unconditional IO exiting' VM-execution
7309          * control.
7310          *
7311          * Otherwise, IO instruction VM-exits are controlled by the IO bitmaps.
7312          */
7313         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7314                 intercept = nested_cpu_has(vmcs12,
7315                                            CPU_BASED_UNCOND_IO_EXITING);
7316         else
7317                 intercept = nested_vmx_check_io_bitmaps(vcpu, port, size);
7318
7319         /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED.  */
7320         return intercept ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE;
7321 }
7322
7323 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7324                                struct x86_instruction_info *info,
7325                                enum x86_intercept_stage stage,
7326                                struct x86_exception *exception)
7327 {
7328         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7329
7330         switch (info->intercept) {
7331         /*
7332          * RDPID causes #UD if disabled through secondary execution controls.
7333          * Because it is marked as EmulateOnUD, we need to intercept it here.
7334          * Note, RDPID is hidden behind ENABLE_RDTSCP.
7335          */
7336         case x86_intercept_rdpid:
7337                 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_RDTSCP)) {
7338                         exception->vector = UD_VECTOR;
7339                         exception->error_code_valid = false;
7340                         return X86EMUL_PROPAGATE_FAULT;
7341                 }
7342                 break;
7343
7344         case x86_intercept_in:
7345         case x86_intercept_ins:
7346         case x86_intercept_out:
7347         case x86_intercept_outs:
7348                 return vmx_check_intercept_io(vcpu, info);
7349
7350         case x86_intercept_lgdt:
7351         case x86_intercept_lidt:
7352         case x86_intercept_lldt:
7353         case x86_intercept_ltr:
7354         case x86_intercept_sgdt:
7355         case x86_intercept_sidt:
7356         case x86_intercept_sldt:
7357         case x86_intercept_str:
7358                 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC))
7359                         return X86EMUL_CONTINUE;
7360
7361                 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED.  */
7362                 break;
7363
7364         /* TODO: check more intercepts... */
7365         default:
7366                 break;
7367         }
7368
7369         return X86EMUL_UNHANDLEABLE;
7370 }
7371
7372 #ifdef CONFIG_X86_64
7373 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7374 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7375                                   u64 divisor, u64 *result)
7376 {
7377         u64 low = a << shift, high = a >> (64 - shift);
7378
7379         /* To avoid the overflow on divq */
7380         if (high >= divisor)
7381                 return 1;
7382
7383         /* Low hold the result, high hold rem which is discarded */
7384         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7385             "rm" (divisor), "0" (low), "1" (high));
7386         *result = low;
7387
7388         return 0;
7389 }
7390
7391 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7392                             bool *expired)
7393 {
7394         struct vcpu_vmx *vmx;
7395         u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
7396         struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
7397
7398         vmx = to_vmx(vcpu);
7399         tscl = rdtsc();
7400         guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7401         delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
7402         lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7403                                                     ktimer->timer_advance_ns);
7404
7405         if (delta_tsc > lapic_timer_advance_cycles)
7406                 delta_tsc -= lapic_timer_advance_cycles;
7407         else
7408                 delta_tsc = 0;
7409
7410         /* Convert to host delta tsc if tsc scaling is enabled */
7411         if (vcpu->arch.l1_tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
7412             delta_tsc && u64_shl_div_u64(delta_tsc,
7413                                 kvm_tsc_scaling_ratio_frac_bits,
7414                                 vcpu->arch.l1_tsc_scaling_ratio, &delta_tsc))
7415                 return -ERANGE;
7416
7417         /*
7418          * If the delta tsc can't fit in the 32 bit after the multi shift,
7419          * we can't use the preemption timer.
7420          * It's possible that it fits on later vmentries, but checking
7421          * on every vmentry is costly so we just use an hrtimer.
7422          */
7423         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7424                 return -ERANGE;
7425
7426         vmx->hv_deadline_tsc = tscl + delta_tsc;
7427         *expired = !delta_tsc;
7428         return 0;
7429 }
7430
7431 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7432 {
7433         to_vmx(vcpu)->hv_deadline_tsc = -1;
7434 }
7435 #endif
7436
7437 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
7438 {
7439         if (!kvm_pause_in_guest(vcpu->kvm))
7440                 shrink_ple_window(vcpu);
7441 }
7442
7443 void vmx_update_cpu_dirty_logging(struct kvm_vcpu *vcpu)
7444 {
7445         struct vcpu_vmx *vmx = to_vmx(vcpu);
7446
7447         if (is_guest_mode(vcpu)) {
7448                 vmx->nested.update_vmcs01_cpu_dirty_logging = true;
7449                 return;
7450         }
7451
7452         /*
7453          * Note, cpu_dirty_logging_count can be changed concurrent with this
7454          * code, but in that case another update request will be made and so
7455          * the guest will never run with a stale PML value.
7456          */
7457         if (vcpu->kvm->arch.cpu_dirty_logging_count)
7458                 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_ENABLE_PML);
7459         else
7460                 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_ENABLE_PML);
7461 }
7462
7463 static int vmx_pre_block(struct kvm_vcpu *vcpu)
7464 {
7465         if (pi_pre_block(vcpu))
7466                 return 1;
7467
7468         if (kvm_lapic_hv_timer_in_use(vcpu))
7469                 kvm_lapic_switch_to_sw_timer(vcpu);
7470
7471         return 0;
7472 }
7473
7474 static void vmx_post_block(struct kvm_vcpu *vcpu)
7475 {
7476         if (kvm_x86_ops.set_hv_timer)
7477                 kvm_lapic_switch_to_hv_timer(vcpu);
7478
7479         pi_post_block(vcpu);
7480 }
7481
7482 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7483 {
7484         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7485                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7486                         FEAT_CTL_LMCE_ENABLED;
7487         else
7488                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7489                         ~FEAT_CTL_LMCE_ENABLED;
7490 }
7491
7492 static int vmx_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
7493 {
7494         /* we need a nested vmexit to enter SMM, postpone if run is pending */
7495         if (to_vmx(vcpu)->nested.nested_run_pending)
7496                 return -EBUSY;
7497         return !is_smm(vcpu);
7498 }
7499
7500 static int vmx_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7501 {
7502         struct vcpu_vmx *vmx = to_vmx(vcpu);
7503
7504         vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7505         if (vmx->nested.smm.guest_mode)
7506                 nested_vmx_vmexit(vcpu, -1, 0, 0);
7507
7508         vmx->nested.smm.vmxon = vmx->nested.vmxon;
7509         vmx->nested.vmxon = false;
7510         vmx_clear_hlt(vcpu);
7511         return 0;
7512 }
7513
7514 static int vmx_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
7515 {
7516         struct vcpu_vmx *vmx = to_vmx(vcpu);
7517         int ret;
7518
7519         if (vmx->nested.smm.vmxon) {
7520                 vmx->nested.vmxon = true;
7521                 vmx->nested.smm.vmxon = false;
7522         }
7523
7524         if (vmx->nested.smm.guest_mode) {
7525                 ret = nested_vmx_enter_non_root_mode(vcpu, false);
7526                 if (ret)
7527                         return ret;
7528
7529                 vmx->nested.smm.guest_mode = false;
7530         }
7531         return 0;
7532 }
7533
7534 static void vmx_enable_smi_window(struct kvm_vcpu *vcpu)
7535 {
7536         /* RSM will cause a vmexit anyway.  */
7537 }
7538
7539 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7540 {
7541         return to_vmx(vcpu)->nested.vmxon && !is_guest_mode(vcpu);
7542 }
7543
7544 static void vmx_migrate_timers(struct kvm_vcpu *vcpu)
7545 {
7546         if (is_guest_mode(vcpu)) {
7547                 struct hrtimer *timer = &to_vmx(vcpu)->nested.preemption_timer;
7548
7549                 if (hrtimer_try_to_cancel(timer) == 1)
7550                         hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED);
7551         }
7552 }
7553
7554 static void hardware_unsetup(void)
7555 {
7556         if (nested)
7557                 nested_vmx_hardware_unsetup();
7558
7559         free_kvm_area();
7560 }
7561
7562 static bool vmx_check_apicv_inhibit_reasons(ulong bit)
7563 {
7564         ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) |
7565                           BIT(APICV_INHIBIT_REASON_HYPERV);
7566
7567         return supported & BIT(bit);
7568 }
7569
7570 static struct kvm_x86_ops vmx_x86_ops __initdata = {
7571         .hardware_unsetup = hardware_unsetup,
7572
7573         .hardware_enable = hardware_enable,
7574         .hardware_disable = hardware_disable,
7575         .cpu_has_accelerated_tpr = report_flexpriority,
7576         .has_emulated_msr = vmx_has_emulated_msr,
7577
7578         .vm_size = sizeof(struct kvm_vmx),
7579         .vm_init = vmx_vm_init,
7580
7581         .vcpu_create = vmx_create_vcpu,
7582         .vcpu_free = vmx_free_vcpu,
7583         .vcpu_reset = vmx_vcpu_reset,
7584
7585         .prepare_guest_switch = vmx_prepare_switch_to_guest,
7586         .vcpu_load = vmx_vcpu_load,
7587         .vcpu_put = vmx_vcpu_put,
7588
7589         .update_exception_bitmap = vmx_update_exception_bitmap,
7590         .get_msr_feature = vmx_get_msr_feature,
7591         .get_msr = vmx_get_msr,
7592         .set_msr = vmx_set_msr,
7593         .get_segment_base = vmx_get_segment_base,
7594         .get_segment = vmx_get_segment,
7595         .set_segment = vmx_set_segment,
7596         .get_cpl = vmx_get_cpl,
7597         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7598         .set_cr0 = vmx_set_cr0,
7599         .is_valid_cr4 = vmx_is_valid_cr4,
7600         .set_cr4 = vmx_set_cr4,
7601         .set_efer = vmx_set_efer,
7602         .get_idt = vmx_get_idt,
7603         .set_idt = vmx_set_idt,
7604         .get_gdt = vmx_get_gdt,
7605         .set_gdt = vmx_set_gdt,
7606         .set_dr7 = vmx_set_dr7,
7607         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
7608         .cache_reg = vmx_cache_reg,
7609         .get_rflags = vmx_get_rflags,
7610         .set_rflags = vmx_set_rflags,
7611
7612         .tlb_flush_all = vmx_flush_tlb_all,
7613         .tlb_flush_current = vmx_flush_tlb_current,
7614         .tlb_flush_gva = vmx_flush_tlb_gva,
7615         .tlb_flush_guest = vmx_flush_tlb_guest,
7616
7617         .run = vmx_vcpu_run,
7618         .handle_exit = vmx_handle_exit,
7619         .skip_emulated_instruction = vmx_skip_emulated_instruction,
7620         .update_emulated_instruction = vmx_update_emulated_instruction,
7621         .set_interrupt_shadow = vmx_set_interrupt_shadow,
7622         .get_interrupt_shadow = vmx_get_interrupt_shadow,
7623         .patch_hypercall = vmx_patch_hypercall,
7624         .set_irq = vmx_inject_irq,
7625         .set_nmi = vmx_inject_nmi,
7626         .queue_exception = vmx_queue_exception,
7627         .cancel_injection = vmx_cancel_injection,
7628         .interrupt_allowed = vmx_interrupt_allowed,
7629         .nmi_allowed = vmx_nmi_allowed,
7630         .get_nmi_mask = vmx_get_nmi_mask,
7631         .set_nmi_mask = vmx_set_nmi_mask,
7632         .enable_nmi_window = vmx_enable_nmi_window,
7633         .enable_irq_window = vmx_enable_irq_window,
7634         .update_cr8_intercept = vmx_update_cr8_intercept,
7635         .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
7636         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
7637         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
7638         .load_eoi_exitmap = vmx_load_eoi_exitmap,
7639         .apicv_post_state_restore = vmx_apicv_post_state_restore,
7640         .check_apicv_inhibit_reasons = vmx_check_apicv_inhibit_reasons,
7641         .hwapic_irr_update = vmx_hwapic_irr_update,
7642         .hwapic_isr_update = vmx_hwapic_isr_update,
7643         .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
7644         .sync_pir_to_irr = vmx_sync_pir_to_irr,
7645         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
7646         .dy_apicv_has_pending_interrupt = pi_has_pending_interrupt,
7647
7648         .set_tss_addr = vmx_set_tss_addr,
7649         .set_identity_map_addr = vmx_set_identity_map_addr,
7650         .get_mt_mask = vmx_get_mt_mask,
7651
7652         .get_exit_info = vmx_get_exit_info,
7653
7654         .vcpu_after_set_cpuid = vmx_vcpu_after_set_cpuid,
7655
7656         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7657
7658         .get_l2_tsc_offset = vmx_get_l2_tsc_offset,
7659         .get_l2_tsc_multiplier = vmx_get_l2_tsc_multiplier,
7660         .write_tsc_offset = vmx_write_tsc_offset,
7661         .write_tsc_multiplier = vmx_write_tsc_multiplier,
7662
7663         .load_mmu_pgd = vmx_load_mmu_pgd,
7664
7665         .check_intercept = vmx_check_intercept,
7666         .handle_exit_irqoff = vmx_handle_exit_irqoff,
7667
7668         .request_immediate_exit = vmx_request_immediate_exit,
7669
7670         .sched_in = vmx_sched_in,
7671
7672         .cpu_dirty_log_size = PML_ENTITY_NUM,
7673         .update_cpu_dirty_logging = vmx_update_cpu_dirty_logging,
7674
7675         .pre_block = vmx_pre_block,
7676         .post_block = vmx_post_block,
7677
7678         .pmu_ops = &intel_pmu_ops,
7679         .nested_ops = &vmx_nested_ops,
7680
7681         .update_pi_irte = pi_update_irte,
7682         .start_assignment = vmx_pi_start_assignment,
7683
7684 #ifdef CONFIG_X86_64
7685         .set_hv_timer = vmx_set_hv_timer,
7686         .cancel_hv_timer = vmx_cancel_hv_timer,
7687 #endif
7688
7689         .setup_mce = vmx_setup_mce,
7690
7691         .smi_allowed = vmx_smi_allowed,
7692         .enter_smm = vmx_enter_smm,
7693         .leave_smm = vmx_leave_smm,
7694         .enable_smi_window = vmx_enable_smi_window,
7695
7696         .can_emulate_instruction = vmx_can_emulate_instruction,
7697         .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
7698         .migrate_timers = vmx_migrate_timers,
7699
7700         .msr_filter_changed = vmx_msr_filter_changed,
7701         .complete_emulated_msr = kvm_complete_insn_gp,
7702
7703         .vcpu_deliver_sipi_vector = kvm_vcpu_deliver_sipi_vector,
7704 };
7705
7706 static __init void vmx_setup_user_return_msrs(void)
7707 {
7708
7709         /*
7710          * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
7711          * will emulate SYSCALL in legacy mode if the vendor string in guest
7712          * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
7713          * support this emulation, MSR_STAR is included in the list for i386,
7714          * but is never loaded into hardware.  MSR_CSTAR is also never loaded
7715          * into hardware and is here purely for emulation purposes.
7716          */
7717         const u32 vmx_uret_msrs_list[] = {
7718         #ifdef CONFIG_X86_64
7719                 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
7720         #endif
7721                 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
7722                 MSR_IA32_TSX_CTRL,
7723         };
7724         int i;
7725
7726         BUILD_BUG_ON(ARRAY_SIZE(vmx_uret_msrs_list) != MAX_NR_USER_RETURN_MSRS);
7727
7728         for (i = 0; i < ARRAY_SIZE(vmx_uret_msrs_list); ++i)
7729                 kvm_add_user_return_msr(vmx_uret_msrs_list[i]);
7730 }
7731
7732 static __init int hardware_setup(void)
7733 {
7734         unsigned long host_bndcfgs;
7735         struct desc_ptr dt;
7736         int r, ept_lpage_level;
7737
7738         store_idt(&dt);
7739         host_idt_base = dt.address;
7740
7741         vmx_setup_user_return_msrs();
7742
7743         if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7744                 return -EIO;
7745
7746         if (boot_cpu_has(X86_FEATURE_NX))
7747                 kvm_enable_efer_bits(EFER_NX);
7748
7749         if (boot_cpu_has(X86_FEATURE_MPX)) {
7750                 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7751                 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7752         }
7753
7754         if (!cpu_has_vmx_mpx())
7755                 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS |
7756                                     XFEATURE_MASK_BNDCSR);
7757
7758         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7759             !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7760                 enable_vpid = 0;
7761
7762         if (!cpu_has_vmx_ept() ||
7763             !cpu_has_vmx_ept_4levels() ||
7764             !cpu_has_vmx_ept_mt_wb() ||
7765             !cpu_has_vmx_invept_global())
7766                 enable_ept = 0;
7767
7768         /* NX support is required for shadow paging. */
7769         if (!enable_ept && !boot_cpu_has(X86_FEATURE_NX)) {
7770                 pr_err_ratelimited("kvm: NX (Execute Disable) not supported\n");
7771                 return -EOPNOTSUPP;
7772         }
7773
7774         if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7775                 enable_ept_ad_bits = 0;
7776
7777         if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7778                 enable_unrestricted_guest = 0;
7779
7780         if (!cpu_has_vmx_flexpriority())
7781                 flexpriority_enabled = 0;
7782
7783         if (!cpu_has_virtual_nmis())
7784                 enable_vnmi = 0;
7785
7786         /*
7787          * set_apic_access_page_addr() is used to reload apic access
7788          * page upon invalidation.  No need to do anything if not
7789          * using the APIC_ACCESS_ADDR VMCS field.
7790          */
7791         if (!flexpriority_enabled)
7792                 vmx_x86_ops.set_apic_access_page_addr = NULL;
7793
7794         if (!cpu_has_vmx_tpr_shadow())
7795                 vmx_x86_ops.update_cr8_intercept = NULL;
7796
7797 #if IS_ENABLED(CONFIG_HYPERV)
7798         if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7799             && enable_ept) {
7800                 vmx_x86_ops.tlb_remote_flush = hv_remote_flush_tlb;
7801                 vmx_x86_ops.tlb_remote_flush_with_range =
7802                                 hv_remote_flush_tlb_with_range;
7803         }
7804 #endif
7805
7806         if (!cpu_has_vmx_ple()) {
7807                 ple_gap = 0;
7808                 ple_window = 0;
7809                 ple_window_grow = 0;
7810                 ple_window_max = 0;
7811                 ple_window_shrink = 0;
7812         }
7813
7814         if (!cpu_has_vmx_apicv()) {
7815                 enable_apicv = 0;
7816                 vmx_x86_ops.sync_pir_to_irr = NULL;
7817         }
7818
7819         if (cpu_has_vmx_tsc_scaling()) {
7820                 kvm_has_tsc_control = true;
7821                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7822                 kvm_tsc_scaling_ratio_frac_bits = 48;
7823         }
7824
7825         kvm_has_bus_lock_exit = cpu_has_vmx_bus_lock_detection();
7826
7827         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7828
7829         if (enable_ept)
7830                 kvm_mmu_set_ept_masks(enable_ept_ad_bits,
7831                                       cpu_has_vmx_ept_execute_only());
7832
7833         if (!enable_ept)
7834                 ept_lpage_level = 0;
7835         else if (cpu_has_vmx_ept_1g_page())
7836                 ept_lpage_level = PG_LEVEL_1G;
7837         else if (cpu_has_vmx_ept_2m_page())
7838                 ept_lpage_level = PG_LEVEL_2M;
7839         else
7840                 ept_lpage_level = PG_LEVEL_4K;
7841         kvm_configure_mmu(enable_ept, 0, vmx_get_max_tdp_level(),
7842                           ept_lpage_level);
7843
7844         /*
7845          * Only enable PML when hardware supports PML feature, and both EPT
7846          * and EPT A/D bit features are enabled -- PML depends on them to work.
7847          */
7848         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7849                 enable_pml = 0;
7850
7851         if (!enable_pml)
7852                 vmx_x86_ops.cpu_dirty_log_size = 0;
7853
7854         if (!cpu_has_vmx_preemption_timer())
7855                 enable_preemption_timer = false;
7856
7857         if (enable_preemption_timer) {
7858                 u64 use_timer_freq = 5000ULL * 1000 * 1000;
7859                 u64 vmx_msr;
7860
7861                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7862                 cpu_preemption_timer_multi =
7863                         vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7864
7865                 if (tsc_khz)
7866                         use_timer_freq = (u64)tsc_khz * 1000;
7867                 use_timer_freq >>= cpu_preemption_timer_multi;
7868
7869                 /*
7870                  * KVM "disables" the preemption timer by setting it to its max
7871                  * value.  Don't use the timer if it might cause spurious exits
7872                  * at a rate faster than 0.1 Hz (of uninterrupted guest time).
7873                  */
7874                 if (use_timer_freq > 0xffffffffu / 10)
7875                         enable_preemption_timer = false;
7876         }
7877
7878         if (!enable_preemption_timer) {
7879                 vmx_x86_ops.set_hv_timer = NULL;
7880                 vmx_x86_ops.cancel_hv_timer = NULL;
7881                 vmx_x86_ops.request_immediate_exit = __kvm_request_immediate_exit;
7882         }
7883
7884         kvm_set_posted_intr_wakeup_handler(pi_wakeup_handler);
7885
7886         kvm_mce_cap_supported |= MCG_LMCE_P;
7887
7888         if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
7889                 return -EINVAL;
7890         if (!enable_ept || !cpu_has_vmx_intel_pt())
7891                 pt_mode = PT_MODE_SYSTEM;
7892
7893         setup_default_sgx_lepubkeyhash();
7894
7895         if (nested) {
7896                 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
7897                                            vmx_capability.ept);
7898
7899                 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
7900                 if (r)
7901                         return r;
7902         }
7903
7904         vmx_set_cpu_caps();
7905
7906         r = alloc_kvm_area();
7907         if (r)
7908                 nested_vmx_hardware_unsetup();
7909         return r;
7910 }
7911
7912 static struct kvm_x86_init_ops vmx_init_ops __initdata = {
7913         .cpu_has_kvm_support = cpu_has_kvm_support,
7914         .disabled_by_bios = vmx_disabled_by_bios,
7915         .check_processor_compatibility = vmx_check_processor_compat,
7916         .hardware_setup = hardware_setup,
7917
7918         .runtime_ops = &vmx_x86_ops,
7919 };
7920
7921 static void vmx_cleanup_l1d_flush(void)
7922 {
7923         if (vmx_l1d_flush_pages) {
7924                 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
7925                 vmx_l1d_flush_pages = NULL;
7926         }
7927         /* Restore state so sysfs ignores VMX */
7928         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
7929 }
7930
7931 static void vmx_exit(void)
7932 {
7933 #ifdef CONFIG_KEXEC_CORE
7934         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
7935         synchronize_rcu();
7936 #endif
7937
7938         kvm_exit();
7939
7940 #if IS_ENABLED(CONFIG_HYPERV)
7941         if (static_branch_unlikely(&enable_evmcs)) {
7942                 int cpu;
7943                 struct hv_vp_assist_page *vp_ap;
7944                 /*
7945                  * Reset everything to support using non-enlightened VMCS
7946                  * access later (e.g. when we reload the module with
7947                  * enlightened_vmcs=0)
7948                  */
7949                 for_each_online_cpu(cpu) {
7950                         vp_ap = hv_get_vp_assist_page(cpu);
7951
7952                         if (!vp_ap)
7953                                 continue;
7954
7955                         vp_ap->nested_control.features.directhypercall = 0;
7956                         vp_ap->current_nested_vmcs = 0;
7957                         vp_ap->enlighten_vmentry = 0;
7958                 }
7959
7960                 static_branch_disable(&enable_evmcs);
7961         }
7962 #endif
7963         vmx_cleanup_l1d_flush();
7964
7965         allow_smaller_maxphyaddr = false;
7966 }
7967 module_exit(vmx_exit);
7968
7969 static int __init vmx_init(void)
7970 {
7971         int r, cpu;
7972
7973 #if IS_ENABLED(CONFIG_HYPERV)
7974         /*
7975          * Enlightened VMCS usage should be recommended and the host needs
7976          * to support eVMCS v1 or above. We can also disable eVMCS support
7977          * with module parameter.
7978          */
7979         if (enlightened_vmcs &&
7980             ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
7981             (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
7982             KVM_EVMCS_VERSION) {
7983                 int cpu;
7984
7985                 /* Check that we have assist pages on all online CPUs */
7986                 for_each_online_cpu(cpu) {
7987                         if (!hv_get_vp_assist_page(cpu)) {
7988                                 enlightened_vmcs = false;
7989                                 break;
7990                         }
7991                 }
7992
7993                 if (enlightened_vmcs) {
7994                         pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
7995                         static_branch_enable(&enable_evmcs);
7996                 }
7997
7998                 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
7999                         vmx_x86_ops.enable_direct_tlbflush
8000                                 = hv_enable_direct_tlbflush;
8001
8002         } else {
8003                 enlightened_vmcs = false;
8004         }
8005 #endif
8006
8007         r = kvm_init(&vmx_init_ops, sizeof(struct vcpu_vmx),
8008                      __alignof__(struct vcpu_vmx), THIS_MODULE);
8009         if (r)
8010                 return r;
8011
8012         /*
8013          * Must be called after kvm_init() so enable_ept is properly set
8014          * up. Hand the parameter mitigation value in which was stored in
8015          * the pre module init parser. If no parameter was given, it will
8016          * contain 'auto' which will be turned into the default 'cond'
8017          * mitigation mode.
8018          */
8019         r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
8020         if (r) {
8021                 vmx_exit();
8022                 return r;
8023         }
8024
8025         for_each_possible_cpu(cpu) {
8026                 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8027
8028                 pi_init_cpu(cpu);
8029         }
8030
8031 #ifdef CONFIG_KEXEC_CORE
8032         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8033                            crash_vmclear_local_loaded_vmcss);
8034 #endif
8035         vmx_check_vmcs12_offsets();
8036
8037         /*
8038          * Shadow paging doesn't have a (further) performance penalty
8039          * from GUEST_MAXPHYADDR < HOST_MAXPHYADDR so enable it
8040          * by default
8041          */
8042         if (!enable_ept)
8043                 allow_smaller_maxphyaddr = true;
8044
8045         return 0;
8046 }
8047 module_init(vmx_init);