arch/x86/kvm/vmx/vmx.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Kernel-based Virtual Machine driver for Linux
   4  *
   5  * This module enables machines with Intel VT-x extensions to run virtual
   6  * machines without emulation or binary translation.
   7  *
   8  * Copyright (C) 2006 Qumranet, Inc.
   9  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  10  *
  11  * Authors:
  12  *   Avi Kivity   <avi@qumranet.com>
  13  *   Yaniv Kamay  <yaniv@qumranet.com>
  14  */
  15
  16 #include <linux/highmem.h>
  17 #include <linux/hrtimer.h>
  18 #include <linux/kernel.h>
  19 #include <linux/kvm_host.h>
  20 #include <linux/module.h>
  21 #include <linux/moduleparam.h>
  22 #include <linux/mod_devicetable.h>
  23 #include <linux/mm.h>
  24 #include <linux/objtool.h>
  25 #include <linux/sched.h>
  26 #include <linux/sched/smt.h>
  27 #include <linux/slab.h>
  28 #include <linux/tboot.h>
  29 #include <linux/trace_events.h>
  30 #include <linux/entry-kvm.h>
  31
  32 #include <asm/apic.h>
  33 #include <asm/asm.h>
  34 #include <asm/cpu.h>
  35 #include <asm/cpu_device_id.h>
  36 #include <asm/debugreg.h>
  37 #include <asm/desc.h>
  38 #include <asm/fpu/internal.h>
  39 #include <asm/idtentry.h>
  40 #include <asm/io.h>
  41 #include <asm/irq_remapping.h>
  42 #include <asm/kexec.h>
  43 #include <asm/perf_event.h>
  44 #include <asm/mmu_context.h>
  45 #include <asm/mshyperv.h>
  46 #include <asm/mwait.h>
  47 #include <asm/spec-ctrl.h>
  48 #include <asm/virtext.h>
  49 #include <asm/vmx.h>
  50
  51 #include "capabilities.h"
  52 #include "cpuid.h"
  53 #include "evmcs.h"
  54 #include "hyperv.h"
  55 #include "kvm_onhyperv.h"
  56 #include "irq.h"
  57 #include "kvm_cache_regs.h"
  58 #include "lapic.h"
  59 #include "mmu.h"
  60 #include "nested.h"
  61 #include "pmu.h"
  62 #include "sgx.h"
  63 #include "trace.h"
  64 #include "vmcs.h"
  65 #include "vmcs12.h"
  66 #include "vmx.h"
  67 #include "x86.h"
  68
  69 MODULE_AUTHOR("Qumranet");
  70 MODULE_LICENSE("GPL");
  71
  72 #ifdef MODULE
  73 static const struct x86_cpu_id vmx_cpu_id[] = {
  74         X86_MATCH_FEATURE(X86_FEATURE_VMX, NULL),
  75         {}
  76 };
  77 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  78 #endif
  79
  80 bool __read_mostly enable_vpid = 1;
  81 module_param_named(vpid, enable_vpid, bool, 0444);
  82
  83 static bool __read_mostly enable_vnmi = 1;
  84 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
  85
  86 bool __read_mostly flexpriority_enabled = 1;
  87 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  88
  89 bool __read_mostly enable_ept = 1;
  90 module_param_named(ept, enable_ept, bool, S_IRUGO);
  91
  92 bool __read_mostly enable_unrestricted_guest = 1;
  93 module_param_named(unrestricted_guest,
  94                         enable_unrestricted_guest, bool, S_IRUGO);
  95
  96 bool __read_mostly enable_ept_ad_bits = 1;
  97 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  98
  99 static bool __read_mostly emulate_invalid_guest_state = true;
 100 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
 101
 102 static bool __read_mostly fasteoi = 1;
 103 module_param(fasteoi, bool, S_IRUGO);
 104
 105 module_param(enable_apicv, bool, S_IRUGO);
 106
 107 /*
 108  * If nested=1, nested virtualization is supported, i.e., guests may use
 109  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 110  * use VMX instructions.
 111  */
 112 static bool __read_mostly nested = 1;
 113 module_param(nested, bool, S_IRUGO);
 114
 115 bool __read_mostly enable_pml = 1;
 116 module_param_named(pml, enable_pml, bool, S_IRUGO);
 117
 118 static bool __read_mostly dump_invalid_vmcs = 0;
 119 module_param(dump_invalid_vmcs, bool, 0644);
 120
 121 #define MSR_BITMAP_MODE_X2APIC          1
 122 #define MSR_BITMAP_MODE_X2APIC_APICV    2
 123
 124 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 125
 126 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 127 static int __read_mostly cpu_preemption_timer_multi;
 128 static bool __read_mostly enable_preemption_timer = 1;
 129 #ifdef CONFIG_X86_64
 130 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 131 #endif
 132
 133 extern bool __read_mostly allow_smaller_maxphyaddr;
 134 module_param(allow_smaller_maxphyaddr, bool, S_IRUGO);
 135
 136 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
 137 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
 138 #define KVM_VM_CR0_ALWAYS_ON                            \
 139         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 140
 141 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
 142 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 143 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 144
 145 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 146
 147 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
 148         RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
 149         RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
 150         RTIT_STATUS_BYTECNT))
 151
 152 /*
 153  * List of MSRs that can be directly passed to the guest.
 154  * In addition to these x2apic and PT MSRs are handled specially.
 155  */
 156 static u32 vmx_possible_passthrough_msrs[MAX_POSSIBLE_PASSTHROUGH_MSRS] = {
 157         MSR_IA32_SPEC_CTRL,
 158         MSR_IA32_PRED_CMD,
 159         MSR_IA32_TSC,
 160 #ifdef CONFIG_X86_64
 161         MSR_FS_BASE,
 162         MSR_GS_BASE,
 163         MSR_KERNEL_GS_BASE,
 164 #endif
 165         MSR_IA32_SYSENTER_CS,
 166         MSR_IA32_SYSENTER_ESP,
 167         MSR_IA32_SYSENTER_EIP,
 168         MSR_CORE_C1_RES,
 169         MSR_CORE_C3_RESIDENCY,
 170         MSR_CORE_C6_RESIDENCY,
 171         MSR_CORE_C7_RESIDENCY,
 172 };
 173
 174 /*
 175  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 176  * ple_gap:    upper bound on the amount of time between two successive
 177  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 178  *             According to test, this time is usually smaller than 128 cycles.
 179  * ple_window: upper bound on the amount of time a guest is allowed to execute
 180  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 181  *             less than 2^12 cycles
 182  * Time is measured based on a counter that runs at the same rate as the TSC,
 183  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 184  */
 185 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
 186 module_param(ple_gap, uint, 0444);
 187
 188 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 189 module_param(ple_window, uint, 0444);
 190
 191 /* Default doubles per-vcpu window every exit. */
 192 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 193 module_param(ple_window_grow, uint, 0444);
 194
 195 /* Default resets per-vcpu window every exit to ple_window. */
 196 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 197 module_param(ple_window_shrink, uint, 0444);
 198
 199 /* Default is to compute the maximum so we can never overflow. */
 200 static unsigned int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 201 module_param(ple_window_max, uint, 0444);
 202
 203 /* Default is SYSTEM mode, 1 for host-guest mode */
 204 int __read_mostly pt_mode = PT_MODE_SYSTEM;
 205 module_param(pt_mode, int, S_IRUGO);
 206
 207 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
 208 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
 209 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
 210
 211 /* Storage for pre module init parameter parsing */
 212 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
 213
 214 static const struct {
 215         const char *option;
 216         bool for_parse;
 217 } vmentry_l1d_param[] = {
 218         [VMENTER_L1D_FLUSH_AUTO]         = {"auto", true},
 219         [VMENTER_L1D_FLUSH_NEVER]        = {"never", true},
 220         [VMENTER_L1D_FLUSH_COND]         = {"cond", true},
 221         [VMENTER_L1D_FLUSH_ALWAYS]       = {"always", true},
 222         [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
 223         [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
 224 };
 225
 226 #define L1D_CACHE_ORDER 4
 227 static void *vmx_l1d_flush_pages;
 228
 229 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
 230 {
 231         struct page *page;
 232         unsigned int i;
 233
 234         if (!boot_cpu_has_bug(X86_BUG_L1TF)) {
 235                 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
 236                 return 0;
 237         }
 238
 239         if (!enable_ept) {
 240                 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
 241                 return 0;
 242         }
 243
 244         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
 245                 u64 msr;
 246
 247                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
 248                 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
 249                         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
 250                         return 0;
 251                 }
 252         }
 253
 254         /* If set to auto use the default l1tf mitigation method */
 255         if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
 256                 switch (l1tf_mitigation) {
 257                 case L1TF_MITIGATION_OFF:
 258                         l1tf = VMENTER_L1D_FLUSH_NEVER;
 259                         break;
 260                 case L1TF_MITIGATION_FLUSH_NOWARN:
 261                 case L1TF_MITIGATION_FLUSH:
 262                 case L1TF_MITIGATION_FLUSH_NOSMT:
 263                         l1tf = VMENTER_L1D_FLUSH_COND;
 264                         break;
 265                 case L1TF_MITIGATION_FULL:
 266                 case L1TF_MITIGATION_FULL_FORCE:
 267                         l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 268                         break;
 269                 }
 270         } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
 271                 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 272         }
 273
 274         if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
 275             !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
 276                 /*
 277                  * This allocation for vmx_l1d_flush_pages is not tied to a VM
 278                  * lifetime and so should not be charged to a memcg.
 279                  */
 280                 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
 281                 if (!page)
 282                         return -ENOMEM;
 283                 vmx_l1d_flush_pages = page_address(page);
 284
 285                 /*
 286                  * Initialize each page with a different pattern in
 287                  * order to protect against KSM in the nested
 288                  * virtualization case.
 289                  */
 290                 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
 291                         memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
 292                                PAGE_SIZE);
 293                 }
 294         }
 295
 296         l1tf_vmx_mitigation = l1tf;
 297
 298         if (l1tf != VMENTER_L1D_FLUSH_NEVER)
 299                 static_branch_enable(&vmx_l1d_should_flush);
 300         else
 301                 static_branch_disable(&vmx_l1d_should_flush);
 302
 303         if (l1tf == VMENTER_L1D_FLUSH_COND)
 304                 static_branch_enable(&vmx_l1d_flush_cond);
 305         else
 306                 static_branch_disable(&vmx_l1d_flush_cond);
 307         return 0;
 308 }
 309
 310 static int vmentry_l1d_flush_parse(const char *s)
 311 {
 312         unsigned int i;
 313
 314         if (s) {
 315                 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
 316                         if (vmentry_l1d_param[i].for_parse &&
 317                             sysfs_streq(s, vmentry_l1d_param[i].option))
 318                                 return i;
 319                 }
 320         }
 321         return -EINVAL;
 322 }
 323
 324 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
 325 {
 326         int l1tf, ret;
 327
 328         l1tf = vmentry_l1d_flush_parse(s);
 329         if (l1tf < 0)
 330                 return l1tf;
 331
 332         if (!boot_cpu_has(X86_BUG_L1TF))
 333                 return 0;
 334
 335         /*
 336          * Has vmx_init() run already? If not then this is the pre init
 337          * parameter parsing. In that case just store the value and let
 338          * vmx_init() do the proper setup after enable_ept has been
 339          * established.
 340          */
 341         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
 342                 vmentry_l1d_flush_param = l1tf;
 343                 return 0;
 344         }
 345
 346         mutex_lock(&vmx_l1d_flush_mutex);
 347         ret = vmx_setup_l1d_flush(l1tf);
 348         mutex_unlock(&vmx_l1d_flush_mutex);
 349         return ret;
 350 }
 351
 352 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
 353 {
 354         if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
 355                 return sprintf(s, "???\n");
 356
 357         return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
 358 }
 359
 360 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
 361         .set = vmentry_l1d_flush_set,
 362         .get = vmentry_l1d_flush_get,
 363 };
 364 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
 365
 366 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 367
 368 void vmx_vmexit(void);
 369
 370 #define vmx_insn_failed(fmt...)         \
 371 do {                                    \
 372         WARN_ONCE(1, fmt);              \
 373         pr_warn_ratelimited(fmt);       \
 374 } while (0)
 375
 376 asmlinkage void vmread_error(unsigned long field, bool fault)
 377 {
 378         if (fault)
 379                 kvm_spurious_fault();
 380         else
 381                 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field);
 382 }
 383
 384 noinline void vmwrite_error(unsigned long field, unsigned long value)
 385 {
 386         vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n",
 387                         field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 388 }
 389
 390 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr)
 391 {
 392         vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr);
 393 }
 394
 395 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr)
 396 {
 397         vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr);
 398 }
 399
 400 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva)
 401 {
 402         vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n",
 403                         ext, vpid, gva);
 404 }
 405
 406 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa)
 407 {
 408         vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n",
 409                         ext, eptp, gpa);
 410 }
 411
 412 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 413 DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 414 /*
 415  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 416  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 417  */
 418 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 419
 420 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 421 static DEFINE_SPINLOCK(vmx_vpid_lock);
 422
 423 struct vmcs_config vmcs_config;
 424 struct vmx_capability vmx_capability;
 425
 426 #define VMX_SEGMENT_FIELD(seg)                                  \
 427         [VCPU_SREG_##seg] = {                                   \
 428                 .selector = GUEST_##seg##_SELECTOR,             \
 429                 .base = GUEST_##seg##_BASE,                     \
 430                 .limit = GUEST_##seg##_LIMIT,                   \
 431                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 432         }
 433
 434 static const struct kvm_vmx_segment_field {
 435         unsigned selector;
 436         unsigned base;
 437         unsigned limit;
 438         unsigned ar_bytes;
 439 } kvm_vmx_segment_fields[] = {
 440         VMX_SEGMENT_FIELD(CS),
 441         VMX_SEGMENT_FIELD(DS),
 442         VMX_SEGMENT_FIELD(ES),
 443         VMX_SEGMENT_FIELD(FS),
 444         VMX_SEGMENT_FIELD(GS),
 445         VMX_SEGMENT_FIELD(SS),
 446         VMX_SEGMENT_FIELD(TR),
 447         VMX_SEGMENT_FIELD(LDTR),
 448 };
 449
 450 static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
 451 {
 452         vmx->segment_cache.bitmask = 0;
 453 }
 454
 455 static unsigned long host_idt_base;
 456
 457 #if IS_ENABLED(CONFIG_HYPERV)
 458 static bool __read_mostly enlightened_vmcs = true;
 459 module_param(enlightened_vmcs, bool, 0444);
 460
 461 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
 462 {
 463         struct hv_enlightened_vmcs *evmcs;
 464         struct hv_partition_assist_pg **p_hv_pa_pg =
 465                         &to_kvm_hv(vcpu->kvm)->hv_pa_pg;
 466         /*
 467          * Synthetic VM-Exit is not enabled in current code and so All
 468          * evmcs in singe VM shares same assist page.
 469          */
 470         if (!*p_hv_pa_pg)
 471                 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL_ACCOUNT);
 472
 473         if (!*p_hv_pa_pg)
 474                 return -ENOMEM;
 475
 476         evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
 477
 478         evmcs->partition_assist_page =
 479                 __pa(*p_hv_pa_pg);
 480         evmcs->hv_vm_id = (unsigned long)vcpu->kvm;
 481         evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
 482
 483         return 0;
 484 }
 485
 486 #endif /* IS_ENABLED(CONFIG_HYPERV) */
 487
 488 /*
 489  * Comment's format: document - errata name - stepping - processor name.
 490  * Refer from
 491  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
 492  */
 493 static u32 vmx_preemption_cpu_tfms[] = {
 494 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
 495 0x000206E6,
 496 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
 497 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
 498 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
 499 0x00020652,
 500 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
 501 0x00020655,
 502 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
 503 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
 504 /*
 505  * 320767.pdf - AAP86  - B1 -
 506  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
 507  */
 508 0x000106E5,
 509 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
 510 0x000106A0,
 511 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
 512 0x000106A1,
 513 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
 514 0x000106A4,
 515  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
 516  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
 517  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
 518 0x000106A5,
 519  /* Xeon E3-1220 V2 */
 520 0x000306A8,
 521 };
 522
 523 static inline bool cpu_has_broken_vmx_preemption_timer(void)
 524 {
 525         u32 eax = cpuid_eax(0x00000001), i;
 526
 527         /* Clear the reserved bits */
 528         eax &= ~(0x3U << 14 | 0xfU << 28);
 529         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
 530                 if (eax == vmx_preemption_cpu_tfms[i])
 531                         return true;
 532
 533         return false;
 534 }
 535
 536 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
 537 {
 538         return flexpriority_enabled && lapic_in_kernel(vcpu);
 539 }
 540
 541 static inline bool report_flexpriority(void)
 542 {
 543         return flexpriority_enabled;
 544 }
 545
 546 static int possible_passthrough_msr_slot(u32 msr)
 547 {
 548         u32 i;
 549
 550         for (i = 0; i < ARRAY_SIZE(vmx_possible_passthrough_msrs); i++)
 551                 if (vmx_possible_passthrough_msrs[i] == msr)
 552                         return i;
 553
 554         return -ENOENT;
 555 }
 556
 557 static bool is_valid_passthrough_msr(u32 msr)
 558 {
 559         bool r;
 560
 561         switch (msr) {
 562         case 0x800 ... 0x8ff:
 563                 /* x2APIC MSRs. These are handled in vmx_update_msr_bitmap_x2apic() */
 564                 return true;
 565         case MSR_IA32_RTIT_STATUS:
 566         case MSR_IA32_RTIT_OUTPUT_BASE:
 567         case MSR_IA32_RTIT_OUTPUT_MASK:
 568         case MSR_IA32_RTIT_CR3_MATCH:
 569         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
 570                 /* PT MSRs. These are handled in pt_update_intercept_for_msr() */
 571         case MSR_LBR_SELECT:
 572         case MSR_LBR_TOS:
 573         case MSR_LBR_INFO_0 ... MSR_LBR_INFO_0 + 31:
 574         case MSR_LBR_NHM_FROM ... MSR_LBR_NHM_FROM + 31:
 575         case MSR_LBR_NHM_TO ... MSR_LBR_NHM_TO + 31:
 576         case MSR_LBR_CORE_FROM ... MSR_LBR_CORE_FROM + 8:
 577         case MSR_LBR_CORE_TO ... MSR_LBR_CORE_TO + 8:
 578                 /* LBR MSRs. These are handled in vmx_update_intercept_for_lbr_msrs() */
 579                 return true;
 580         }
 581
 582         r = possible_passthrough_msr_slot(msr) != -ENOENT;
 583
 584         WARN(!r, "Invalid MSR %x, please adapt vmx_possible_passthrough_msrs[]", msr);
 585
 586         return r;
 587 }
 588
 589 struct vmx_uret_msr *vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr)
 590 {
 591         int i;
 592
 593         i = kvm_find_user_return_msr(msr);
 594         if (i >= 0)
 595                 return &vmx->guest_uret_msrs[i];
 596         return NULL;
 597 }
 598
 599 static int vmx_set_guest_uret_msr(struct vcpu_vmx *vmx,
 600                                   struct vmx_uret_msr *msr, u64 data)
 601 {
 602         unsigned int slot = msr - vmx->guest_uret_msrs;
 603         int ret = 0;
 604
 605         u64 old_msr_data = msr->data;
 606         msr->data = data;
 607         if (msr->load_into_hardware) {
 608                 preempt_disable();
 609                 ret = kvm_set_user_return_msr(slot, msr->data, msr->mask);
 610                 preempt_enable();
 611                 if (ret)
 612                         msr->data = old_msr_data;
 613         }
 614         return ret;
 615 }
 616
 617 #ifdef CONFIG_KEXEC_CORE
 618 static void crash_vmclear_local_loaded_vmcss(void)
 619 {
 620         int cpu = raw_smp_processor_id();
 621         struct loaded_vmcs *v;
 622
 623         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
 624                             loaded_vmcss_on_cpu_link)
 625                 vmcs_clear(v->vmcs);
 626 }
 627 #endif /* CONFIG_KEXEC_CORE */
 628
 629 static void __loaded_vmcs_clear(void *arg)
 630 {
 631         struct loaded_vmcs *loaded_vmcs = arg;
 632         int cpu = raw_smp_processor_id();
 633
 634         if (loaded_vmcs->cpu != cpu)
 635                 return; /* vcpu migration can race with cpu offline */
 636         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
 637                 per_cpu(current_vmcs, cpu) = NULL;
 638
 639         vmcs_clear(loaded_vmcs->vmcs);
 640         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
 641                 vmcs_clear(loaded_vmcs->shadow_vmcs);
 642
 643         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
 644
 645         /*
 646          * Ensure all writes to loaded_vmcs, including deleting it from its
 647          * current percpu list, complete before setting loaded_vmcs->vcpu to
 648          * -1, otherwise a different cpu can see vcpu == -1 first and add
 649          * loaded_vmcs to its percpu list before it's deleted from this cpu's
 650          * list. Pairs with the smp_rmb() in vmx_vcpu_load_vmcs().
 651          */
 652         smp_wmb();
 653
 654         loaded_vmcs->cpu = -1;
 655         loaded_vmcs->launched = 0;
 656 }
 657
 658 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
 659 {
 660         int cpu = loaded_vmcs->cpu;
 661
 662         if (cpu != -1)
 663                 smp_call_function_single(cpu,
 664                          __loaded_vmcs_clear, loaded_vmcs, 1);
 665 }
 666
 667 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
 668                                        unsigned field)
 669 {
 670         bool ret;
 671         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
 672
 673         if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) {
 674                 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS);
 675                 vmx->segment_cache.bitmask = 0;
 676         }
 677         ret = vmx->segment_cache.bitmask & mask;
 678         vmx->segment_cache.bitmask |= mask;
 679         return ret;
 680 }
 681
 682 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
 683 {
 684         u16 *p = &vmx->segment_cache.seg[seg].selector;
 685
 686         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
 687                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
 688         return *p;
 689 }
 690
 691 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
 692 {
 693         ulong *p = &vmx->segment_cache.seg[seg].base;
 694
 695         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
 696                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
 697         return *p;
 698 }
 699
 700 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
 701 {
 702         u32 *p = &vmx->segment_cache.seg[seg].limit;
 703
 704         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
 705                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
 706         return *p;
 707 }
 708
 709 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
 710 {
 711         u32 *p = &vmx->segment_cache.seg[seg].ar;
 712
 713         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
 714                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
 715         return *p;
 716 }
 717
 718 void vmx_update_exception_bitmap(struct kvm_vcpu *vcpu)
 719 {
 720         u32 eb;
 721
 722         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
 723              (1u << DB_VECTOR) | (1u << AC_VECTOR);
 724         /*
 725          * Guest access to VMware backdoor ports could legitimately
 726          * trigger #GP because of TSS I/O permission bitmap.
 727          * We intercept those #GP and allow access to them anyway
 728          * as VMware does.
 729          */
 730         if (enable_vmware_backdoor)
 731                 eb |= (1u << GP_VECTOR);
 732         if ((vcpu->guest_debug &
 733              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
 734             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
 735                 eb |= 1u << BP_VECTOR;
 736         if (to_vmx(vcpu)->rmode.vm86_active)
 737                 eb = ~0;
 738         if (!vmx_need_pf_intercept(vcpu))
 739                 eb &= ~(1u << PF_VECTOR);
 740
 741         /* When we are running a nested L2 guest and L1 specified for it a
 742          * certain exception bitmap, we must trap the same exceptions and pass
 743          * them to L1. When running L2, we will only handle the exceptions
 744          * specified above if L1 did not want them.
 745          */
 746         if (is_guest_mode(vcpu))
 747                 eb |= get_vmcs12(vcpu)->exception_bitmap;
 748         else {
 749                 int mask = 0, match = 0;
 750
 751                 if (enable_ept && (eb & (1u << PF_VECTOR))) {
 752                         /*
 753                          * If EPT is enabled, #PF is currently only intercepted
 754                          * if MAXPHYADDR is smaller on the guest than on the
 755                          * host.  In that case we only care about present,
 756                          * non-reserved faults.  For vmcs02, however, PFEC_MASK
 757                          * and PFEC_MATCH are set in prepare_vmcs02_rare.
 758                          */
 759                         mask = PFERR_PRESENT_MASK | PFERR_RSVD_MASK;
 760                         match = PFERR_PRESENT_MASK;
 761                 }
 762                 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, mask);
 763                 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, match);
 764         }
 765
 766         vmcs_write32(EXCEPTION_BITMAP, eb);
 767 }
 768
 769 /*
 770  * Check if MSR is intercepted for currently loaded MSR bitmap.
 771  */
 772 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
 773 {
 774         unsigned long *msr_bitmap;
 775         int f = sizeof(unsigned long);
 776
 777         if (!cpu_has_vmx_msr_bitmap())
 778                 return true;
 779
 780         msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
 781
 782         if (msr <= 0x1fff) {
 783                 return !!test_bit(msr, msr_bitmap + 0x800 / f);
 784         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
 785                 msr &= 0x1fff;
 786                 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
 787         }
 788
 789         return true;
 790 }
 791
 792 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
 793                 unsigned long entry, unsigned long exit)
 794 {
 795         vm_entry_controls_clearbit(vmx, entry);
 796         vm_exit_controls_clearbit(vmx, exit);
 797 }
 798
 799 int vmx_find_loadstore_msr_slot(struct vmx_msrs *m, u32 msr)
 800 {
 801         unsigned int i;
 802
 803         for (i = 0; i < m->nr; ++i) {
 804                 if (m->val[i].index == msr)
 805                         return i;
 806         }
 807         return -ENOENT;
 808 }
 809
 810 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
 811 {
 812         int i;
 813         struct msr_autoload *m = &vmx->msr_autoload;
 814
 815         switch (msr) {
 816         case MSR_EFER:
 817                 if (cpu_has_load_ia32_efer()) {
 818                         clear_atomic_switch_msr_special(vmx,
 819                                         VM_ENTRY_LOAD_IA32_EFER,
 820                                         VM_EXIT_LOAD_IA32_EFER);
 821                         return;
 822                 }
 823                 break;
 824         case MSR_CORE_PERF_GLOBAL_CTRL:
 825                 if (cpu_has_load_perf_global_ctrl()) {
 826                         clear_atomic_switch_msr_special(vmx,
 827                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
 828                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
 829                         return;
 830                 }
 831                 break;
 832         }
 833         i = vmx_find_loadstore_msr_slot(&m->guest, msr);
 834         if (i < 0)
 835                 goto skip_guest;
 836         --m->guest.nr;
 837         m->guest.val[i] = m->guest.val[m->guest.nr];
 838         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
 839
 840 skip_guest:
 841         i = vmx_find_loadstore_msr_slot(&m->host, msr);
 842         if (i < 0)
 843                 return;
 844
 845         --m->host.nr;
 846         m->host.val[i] = m->host.val[m->host.nr];
 847         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
 848 }
 849
 850 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
 851                 unsigned long entry, unsigned long exit,
 852                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
 853                 u64 guest_val, u64 host_val)
 854 {
 855         vmcs_write64(guest_val_vmcs, guest_val);
 856         if (host_val_vmcs != HOST_IA32_EFER)
 857                 vmcs_write64(host_val_vmcs, host_val);
 858         vm_entry_controls_setbit(vmx, entry);
 859         vm_exit_controls_setbit(vmx, exit);
 860 }
 861
 862 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
 863                                   u64 guest_val, u64 host_val, bool entry_only)
 864 {
 865         int i, j = 0;
 866         struct msr_autoload *m = &vmx->msr_autoload;
 867
 868         switch (msr) {
 869         case MSR_EFER:
 870                 if (cpu_has_load_ia32_efer()) {
 871                         add_atomic_switch_msr_special(vmx,
 872                                         VM_ENTRY_LOAD_IA32_EFER,
 873                                         VM_EXIT_LOAD_IA32_EFER,
 874                                         GUEST_IA32_EFER,
 875                                         HOST_IA32_EFER,
 876                                         guest_val, host_val);
 877                         return;
 878                 }
 879                 break;
 880         case MSR_CORE_PERF_GLOBAL_CTRL:
 881                 if (cpu_has_load_perf_global_ctrl()) {
 882                         add_atomic_switch_msr_special(vmx,
 883                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
 884                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
 885                                         GUEST_IA32_PERF_GLOBAL_CTRL,
 886                                         HOST_IA32_PERF_GLOBAL_CTRL,
 887                                         guest_val, host_val);
 888                         return;
 889                 }
 890                 break;
 891         case MSR_IA32_PEBS_ENABLE:
 892                 /* PEBS needs a quiescent period after being disabled (to write
 893                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
 894                  * provide that period, so a CPU could write host's record into
 895                  * guest's memory.
 896                  */
 897                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
 898         }
 899
 900         i = vmx_find_loadstore_msr_slot(&m->guest, msr);
 901         if (!entry_only)
 902                 j = vmx_find_loadstore_msr_slot(&m->host, msr);
 903
 904         if ((i < 0 && m->guest.nr == MAX_NR_LOADSTORE_MSRS) ||
 905             (j < 0 &&  m->host.nr == MAX_NR_LOADSTORE_MSRS)) {
 906                 printk_once(KERN_WARNING "Not enough msr switch entries. "
 907                                 "Can't add msr %x\n", msr);
 908                 return;
 909         }
 910         if (i < 0) {
 911                 i = m->guest.nr++;
 912                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
 913         }
 914         m->guest.val[i].index = msr;
 915         m->guest.val[i].value = guest_val;
 916
 917         if (entry_only)
 918                 return;
 919
 920         if (j < 0) {
 921                 j = m->host.nr++;
 922                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
 923         }
 924         m->host.val[j].index = msr;
 925         m->host.val[j].value = host_val;
 926 }
 927
 928 static bool update_transition_efer(struct vcpu_vmx *vmx)
 929 {
 930         u64 guest_efer = vmx->vcpu.arch.efer;
 931         u64 ignore_bits = 0;
 932         int i;
 933
 934         /* Shadow paging assumes NX to be available.  */
 935         if (!enable_ept)
 936                 guest_efer |= EFER_NX;
 937
 938         /*
 939          * LMA and LME handled by hardware; SCE meaningless outside long mode.
 940          */
 941         ignore_bits |= EFER_SCE;
 942 #ifdef CONFIG_X86_64
 943         ignore_bits |= EFER_LMA | EFER_LME;
 944         /* SCE is meaningful only in long mode on Intel */
 945         if (guest_efer & EFER_LMA)
 946                 ignore_bits &= ~(u64)EFER_SCE;
 947 #endif
 948
 949         /*
 950          * On EPT, we can't emulate NX, so we must switch EFER atomically.
 951          * On CPUs that support "load IA32_EFER", always switch EFER
 952          * atomically, since it's faster than switching it manually.
 953          */
 954         if (cpu_has_load_ia32_efer() ||
 955             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
 956                 if (!(guest_efer & EFER_LMA))
 957                         guest_efer &= ~EFER_LME;
 958                 if (guest_efer != host_efer)
 959                         add_atomic_switch_msr(vmx, MSR_EFER,
 960                                               guest_efer, host_efer, false);
 961                 else
 962                         clear_atomic_switch_msr(vmx, MSR_EFER);
 963                 return false;
 964         }
 965
 966         i = kvm_find_user_return_msr(MSR_EFER);
 967         if (i < 0)
 968                 return false;
 969
 970         clear_atomic_switch_msr(vmx, MSR_EFER);
 971
 972         guest_efer &= ~ignore_bits;
 973         guest_efer |= host_efer & ignore_bits;
 974
 975         vmx->guest_uret_msrs[i].data = guest_efer;
 976         vmx->guest_uret_msrs[i].mask = ~ignore_bits;
 977
 978         return true;
 979 }
 980
 981 #ifdef CONFIG_X86_32
 982 /*
 983  * On 32-bit kernels, VM exits still load the FS and GS bases from the
 984  * VMCS rather than the segment table.  KVM uses this helper to figure
 985  * out the current bases to poke them into the VMCS before entry.
 986  */
 987 static unsigned long segment_base(u16 selector)
 988 {
 989         struct desc_struct *table;
 990         unsigned long v;
 991
 992         if (!(selector & ~SEGMENT_RPL_MASK))
 993                 return 0;
 994
 995         table = get_current_gdt_ro();
 996
 997         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
 998                 u16 ldt_selector = kvm_read_ldt();
 999
1000                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
1001                         return 0;
1002
1003                 table = (struct desc_struct *)segment_base(ldt_selector);
1004         }
1005         v = get_desc_base(&table[selector >> 3]);
1006         return v;
1007 }
1008 #endif
1009
1010 static inline bool pt_can_write_msr(struct vcpu_vmx *vmx)
1011 {
1012         return vmx_pt_mode_is_host_guest() &&
1013                !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
1014 }
1015
1016 static inline bool pt_output_base_valid(struct kvm_vcpu *vcpu, u64 base)
1017 {
1018         /* The base must be 128-byte aligned and a legal physical address. */
1019         return kvm_vcpu_is_legal_aligned_gpa(vcpu, base, 128);
1020 }
1021
1022 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
1023 {
1024         u32 i;
1025
1026         wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1027         wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1028         wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1029         wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1030         for (i = 0; i < addr_range; i++) {
1031                 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1032                 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1033         }
1034 }
1035
1036 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
1037 {
1038         u32 i;
1039
1040         rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1041         rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1042         rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1043         rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1044         for (i = 0; i < addr_range; i++) {
1045                 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1046                 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1047         }
1048 }
1049
1050 static void pt_guest_enter(struct vcpu_vmx *vmx)
1051 {
1052         if (vmx_pt_mode_is_system())
1053                 return;
1054
1055         /*
1056          * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1057          * Save host state before VM entry.
1058          */
1059         rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1060         if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1061                 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1062                 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1063                 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1064         }
1065 }
1066
1067 static void pt_guest_exit(struct vcpu_vmx *vmx)
1068 {
1069         if (vmx_pt_mode_is_system())
1070                 return;
1071
1072         if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1073                 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1074                 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1075         }
1076
1077         /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1078         wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1079 }
1080
1081 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1082                         unsigned long fs_base, unsigned long gs_base)
1083 {
1084         if (unlikely(fs_sel != host->fs_sel)) {
1085                 if (!(fs_sel & 7))
1086                         vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1087                 else
1088                         vmcs_write16(HOST_FS_SELECTOR, 0);
1089                 host->fs_sel = fs_sel;
1090         }
1091         if (unlikely(gs_sel != host->gs_sel)) {
1092                 if (!(gs_sel & 7))
1093                         vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1094                 else
1095                         vmcs_write16(HOST_GS_SELECTOR, 0);
1096                 host->gs_sel = gs_sel;
1097         }
1098         if (unlikely(fs_base != host->fs_base)) {
1099                 vmcs_writel(HOST_FS_BASE, fs_base);
1100                 host->fs_base = fs_base;
1101         }
1102         if (unlikely(gs_base != host->gs_base)) {
1103                 vmcs_writel(HOST_GS_BASE, gs_base);
1104                 host->gs_base = gs_base;
1105         }
1106 }
1107
1108 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1109 {
1110         struct vcpu_vmx *vmx = to_vmx(vcpu);
1111         struct vmcs_host_state *host_state;
1112 #ifdef CONFIG_X86_64
1113         int cpu = raw_smp_processor_id();
1114 #endif
1115         unsigned long fs_base, gs_base;
1116         u16 fs_sel, gs_sel;
1117         int i;
1118
1119         vmx->req_immediate_exit = false;
1120
1121         /*
1122          * Note that guest MSRs to be saved/restored can also be changed
1123          * when guest state is loaded. This happens when guest transitions
1124          * to/from long-mode by setting MSR_EFER.LMA.
1125          */
1126         if (!vmx->guest_uret_msrs_loaded) {
1127                 vmx->guest_uret_msrs_loaded = true;
1128                 for (i = 0; i < kvm_nr_uret_msrs; ++i) {
1129                         if (!vmx->guest_uret_msrs[i].load_into_hardware)
1130                                 continue;
1131
1132                         kvm_set_user_return_msr(i,
1133                                                 vmx->guest_uret_msrs[i].data,
1134                                                 vmx->guest_uret_msrs[i].mask);
1135                 }
1136         }
1137
1138         if (vmx->nested.need_vmcs12_to_shadow_sync)
1139                 nested_sync_vmcs12_to_shadow(vcpu);
1140
1141         if (vmx->guest_state_loaded)
1142                 return;
1143
1144         host_state = &vmx->loaded_vmcs->host_state;
1145
1146         /*
1147          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1148          * allow segment selectors with cpl > 0 or ti == 1.
1149          */
1150         host_state->ldt_sel = kvm_read_ldt();
1151
1152 #ifdef CONFIG_X86_64
1153         savesegment(ds, host_state->ds_sel);
1154         savesegment(es, host_state->es_sel);
1155
1156         gs_base = cpu_kernelmode_gs_base(cpu);
1157         if (likely(is_64bit_mm(current->mm))) {
1158                 current_save_fsgs();
1159                 fs_sel = current->thread.fsindex;
1160                 gs_sel = current->thread.gsindex;
1161                 fs_base = current->thread.fsbase;
1162                 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
1163         } else {
1164                 savesegment(fs, fs_sel);
1165                 savesegment(gs, gs_sel);
1166                 fs_base = read_msr(MSR_FS_BASE);
1167                 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
1168         }
1169
1170         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1171 #else
1172         savesegment(fs, fs_sel);
1173         savesegment(gs, gs_sel);
1174         fs_base = segment_base(fs_sel);
1175         gs_base = segment_base(gs_sel);
1176 #endif
1177
1178         vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
1179         vmx->guest_state_loaded = true;
1180 }
1181
1182 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
1183 {
1184         struct vmcs_host_state *host_state;
1185
1186         if (!vmx->guest_state_loaded)
1187                 return;
1188
1189         host_state = &vmx->loaded_vmcs->host_state;
1190
1191         ++vmx->vcpu.stat.host_state_reload;
1192
1193 #ifdef CONFIG_X86_64
1194         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1195 #endif
1196         if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1197                 kvm_load_ldt(host_state->ldt_sel);
1198 #ifdef CONFIG_X86_64
1199                 load_gs_index(host_state->gs_sel);
1200 #else
1201                 loadsegment(gs, host_state->gs_sel);
1202 #endif
1203         }
1204         if (host_state->fs_sel & 7)
1205                 loadsegment(fs, host_state->fs_sel);
1206 #ifdef CONFIG_X86_64
1207         if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1208                 loadsegment(ds, host_state->ds_sel);
1209                 loadsegment(es, host_state->es_sel);
1210         }
1211 #endif
1212         invalidate_tss_limit();
1213 #ifdef CONFIG_X86_64
1214         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1215 #endif
1216         load_fixmap_gdt(raw_smp_processor_id());
1217         vmx->guest_state_loaded = false;
1218         vmx->guest_uret_msrs_loaded = false;
1219 }
1220
1221 #ifdef CONFIG_X86_64
1222 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
1223 {
1224         preempt_disable();
1225         if (vmx->guest_state_loaded)
1226                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1227         preempt_enable();
1228         return vmx->msr_guest_kernel_gs_base;
1229 }
1230
1231 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1232 {
1233         preempt_disable();
1234         if (vmx->guest_state_loaded)
1235                 wrmsrl(MSR_KERNEL_GS_BASE, data);
1236         preempt_enable();
1237         vmx->msr_guest_kernel_gs_base = data;
1238 }
1239 #endif
1240
1241 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu,
1242                         struct loaded_vmcs *buddy)
1243 {
1244         struct vcpu_vmx *vmx = to_vmx(vcpu);
1245         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
1246         struct vmcs *prev;
1247
1248         if (!already_loaded) {
1249                 loaded_vmcs_clear(vmx->loaded_vmcs);
1250                 local_irq_disable();
1251
1252                 /*
1253                  * Ensure loaded_vmcs->cpu is read before adding loaded_vmcs to
1254                  * this cpu's percpu list, otherwise it may not yet be deleted
1255                  * from its previous cpu's percpu list.  Pairs with the
1256                  * smb_wmb() in __loaded_vmcs_clear().
1257                  */
1258                 smp_rmb();
1259
1260                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1261                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1262                 local_irq_enable();
1263         }
1264
1265         prev = per_cpu(current_vmcs, cpu);
1266         if (prev != vmx->loaded_vmcs->vmcs) {
1267                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1268                 vmcs_load(vmx->loaded_vmcs->vmcs);
1269
1270                 /*
1271                  * No indirect branch prediction barrier needed when switching
1272                  * the active VMCS within a guest, e.g. on nested VM-Enter.
1273                  * The L1 VMM can protect itself with retpolines, IBPB or IBRS.
1274                  */
1275                 if (!buddy || WARN_ON_ONCE(buddy->vmcs != prev))
1276                         indirect_branch_prediction_barrier();
1277         }
1278
1279         if (!already_loaded) {
1280                 void *gdt = get_current_gdt_ro();
1281                 unsigned long sysenter_esp;
1282
1283                 /*
1284                  * Flush all EPTP/VPID contexts, the new pCPU may have stale
1285                  * TLB entries from its previous association with the vCPU.
1286                  */
1287                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1288
1289                 /*
1290                  * Linux uses per-cpu TSS and GDT, so set these when switching
1291                  * processors.  See 22.2.4.
1292                  */
1293                 vmcs_writel(HOST_TR_BASE,
1294                             (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
1295                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
1296
1297                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1298                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1299
1300                 vmx->loaded_vmcs->cpu = cpu;
1301         }
1302 }
1303
1304 /*
1305  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1306  * vcpu mutex is already taken.
1307  */
1308 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1309 {
1310         struct vcpu_vmx *vmx = to_vmx(vcpu);
1311
1312         vmx_vcpu_load_vmcs(vcpu, cpu, NULL);
1313
1314         vmx_vcpu_pi_load(vcpu, cpu);
1315
1316         vmx->host_debugctlmsr = get_debugctlmsr();
1317 }
1318
1319 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1320 {
1321         vmx_vcpu_pi_put(vcpu);
1322
1323         vmx_prepare_switch_to_host(to_vmx(vcpu));
1324 }
1325
1326 static bool emulation_required(struct kvm_vcpu *vcpu)
1327 {
1328         return emulate_invalid_guest_state && !vmx_guest_state_valid(vcpu);
1329 }
1330
1331 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1332 {
1333         struct vcpu_vmx *vmx = to_vmx(vcpu);
1334         unsigned long rflags, save_rflags;
1335
1336         if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) {
1337                 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1338                 rflags = vmcs_readl(GUEST_RFLAGS);
1339                 if (vmx->rmode.vm86_active) {
1340                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1341                         save_rflags = vmx->rmode.save_rflags;
1342                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1343                 }
1344                 vmx->rflags = rflags;
1345         }
1346         return vmx->rflags;
1347 }
1348
1349 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1350 {
1351         struct vcpu_vmx *vmx = to_vmx(vcpu);
1352         unsigned long old_rflags;
1353
1354         if (is_unrestricted_guest(vcpu)) {
1355                 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1356                 vmx->rflags = rflags;
1357                 vmcs_writel(GUEST_RFLAGS, rflags);
1358                 return;
1359         }
1360
1361         old_rflags = vmx_get_rflags(vcpu);
1362         vmx->rflags = rflags;
1363         if (vmx->rmode.vm86_active) {
1364                 vmx->rmode.save_rflags = rflags;
1365                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1366         }
1367         vmcs_writel(GUEST_RFLAGS, rflags);
1368
1369         if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM)
1370                 vmx->emulation_required = emulation_required(vcpu);
1371 }
1372
1373 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1374 {
1375         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1376         int ret = 0;
1377
1378         if (interruptibility & GUEST_INTR_STATE_STI)
1379                 ret |= KVM_X86_SHADOW_INT_STI;
1380         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1381                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1382
1383         return ret;
1384 }
1385
1386 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1387 {
1388         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1389         u32 interruptibility = interruptibility_old;
1390
1391         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1392
1393         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1394                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1395         else if (mask & KVM_X86_SHADOW_INT_STI)
1396                 interruptibility |= GUEST_INTR_STATE_STI;
1397
1398         if ((interruptibility != interruptibility_old))
1399                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1400 }
1401
1402 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1403 {
1404         struct vcpu_vmx *vmx = to_vmx(vcpu);
1405         unsigned long value;
1406
1407         /*
1408          * Any MSR write that attempts to change bits marked reserved will
1409          * case a #GP fault.
1410          */
1411         if (data & vmx->pt_desc.ctl_bitmask)
1412                 return 1;
1413
1414         /*
1415          * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1416          * result in a #GP unless the same write also clears TraceEn.
1417          */
1418         if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1419                 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1420                 return 1;
1421
1422         /*
1423          * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1424          * and FabricEn would cause #GP, if
1425          * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1426          */
1427         if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1428                 !(data & RTIT_CTL_FABRIC_EN) &&
1429                 !intel_pt_validate_cap(vmx->pt_desc.caps,
1430                                         PT_CAP_single_range_output))
1431                 return 1;
1432
1433         /*
1434          * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1435          * utilize encodings marked reserved will cause a #GP fault.
1436          */
1437         value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1438         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1439                         !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1440                         RTIT_CTL_MTC_RANGE_OFFSET, &value))
1441                 return 1;
1442         value = intel_pt_validate_cap(vmx->pt_desc.caps,
1443                                                 PT_CAP_cycle_thresholds);
1444         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1445                         !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1446                         RTIT_CTL_CYC_THRESH_OFFSET, &value))
1447                 return 1;
1448         value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1449         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1450                         !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1451                         RTIT_CTL_PSB_FREQ_OFFSET, &value))
1452                 return 1;
1453
1454         /*
1455          * If ADDRx_CFG is reserved or the encodings is >2 will
1456          * cause a #GP fault.
1457          */
1458         value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1459         if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
1460                 return 1;
1461         value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1462         if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
1463                 return 1;
1464         value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1465         if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
1466                 return 1;
1467         value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1468         if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
1469                 return 1;
1470
1471         return 0;
1472 }
1473
1474 static bool vmx_can_emulate_instruction(struct kvm_vcpu *vcpu, void *insn, int insn_len)
1475 {
1476         /*
1477          * Emulation of instructions in SGX enclaves is impossible as RIP does
1478          * not point  tthe failing instruction, and even if it did, the code
1479          * stream is inaccessible.  Inject #UD instead of exiting to userspace
1480          * so that guest userspace can't DoS the guest simply by triggering
1481          * emulation (enclaves are CPL3 only).
1482          */
1483         if (to_vmx(vcpu)->exit_reason.enclave_mode) {
1484                 kvm_queue_exception(vcpu, UD_VECTOR);
1485                 return false;
1486         }
1487         return true;
1488 }
1489
1490 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
1491 {
1492         union vmx_exit_reason exit_reason = to_vmx(vcpu)->exit_reason;
1493         unsigned long rip, orig_rip;
1494         u32 instr_len;
1495
1496         /*
1497          * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
1498          * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
1499          * set when EPT misconfig occurs.  In practice, real hardware updates
1500          * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
1501          * (namely Hyper-V) don't set it due to it being undefined behavior,
1502          * i.e. we end up advancing IP with some random value.
1503          */
1504         if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
1505             exit_reason.basic != EXIT_REASON_EPT_MISCONFIG) {
1506                 instr_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1507
1508                 /*
1509                  * Emulating an enclave's instructions isn't supported as KVM
1510                  * cannot access the enclave's memory or its true RIP, e.g. the
1511                  * vmcs.GUEST_RIP points at the exit point of the enclave, not
1512                  * the RIP that actually triggered the VM-Exit.  But, because
1513                  * most instructions that cause VM-Exit will #UD in an enclave,
1514                  * most instruction-based VM-Exits simply do not occur.
1515                  *
1516                  * There are a few exceptions, notably the debug instructions
1517                  * INT1ICEBRK and INT3, as they are allowed in debug enclaves
1518                  * and generate #DB/#BP as expected, which KVM might intercept.
1519                  * But again, the CPU does the dirty work and saves an instr
1520                  * length of zero so VMMs don't shoot themselves in the foot.
1521                  * WARN if KVM tries to skip a non-zero length instruction on
1522                  * a VM-Exit from an enclave.
1523                  */
1524                 if (!instr_len)
1525                         goto rip_updated;
1526
1527                 WARN(exit_reason.enclave_mode,
1528                      "KVM: skipping instruction after SGX enclave VM-Exit");
1529
1530                 orig_rip = kvm_rip_read(vcpu);
1531                 rip = orig_rip + instr_len;
1532 #ifdef CONFIG_X86_64
1533                 /*
1534                  * We need to mask out the high 32 bits of RIP if not in 64-bit
1535                  * mode, but just finding out that we are in 64-bit mode is
1536                  * quite expensive.  Only do it if there was a carry.
1537                  */
1538                 if (unlikely(((rip ^ orig_rip) >> 31) == 3) && !is_64_bit_mode(vcpu))
1539                         rip = (u32)rip;
1540 #endif
1541                 kvm_rip_write(vcpu, rip);
1542         } else {
1543                 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
1544                         return 0;
1545         }
1546
1547 rip_updated:
1548         /* skipping an emulated instruction also counts */
1549         vmx_set_interrupt_shadow(vcpu, 0);
1550
1551         return 1;
1552 }
1553
1554 /*
1555  * Recognizes a pending MTF VM-exit and records the nested state for later
1556  * delivery.
1557  */
1558 static void vmx_update_emulated_instruction(struct kvm_vcpu *vcpu)
1559 {
1560         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1561         struct vcpu_vmx *vmx = to_vmx(vcpu);
1562
1563         if (!is_guest_mode(vcpu))
1564                 return;
1565
1566         /*
1567          * Per the SDM, MTF takes priority over debug-trap exceptions besides
1568          * T-bit traps. As instruction emulation is completed (i.e. at the
1569          * instruction boundary), any #DB exception pending delivery must be a
1570          * debug-trap. Record the pending MTF state to be delivered in
1571          * vmx_check_nested_events().
1572          */
1573         if (nested_cpu_has_mtf(vmcs12) &&
1574             (!vcpu->arch.exception.pending ||
1575              vcpu->arch.exception.nr == DB_VECTOR))
1576                 vmx->nested.mtf_pending = true;
1577         else
1578                 vmx->nested.mtf_pending = false;
1579 }
1580
1581 static int vmx_skip_emulated_instruction(struct kvm_vcpu *vcpu)
1582 {
1583         vmx_update_emulated_instruction(vcpu);
1584         return skip_emulated_instruction(vcpu);
1585 }
1586
1587 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1588 {
1589         /*
1590          * Ensure that we clear the HLT state in the VMCS.  We don't need to
1591          * explicitly skip the instruction because if the HLT state is set,
1592          * then the instruction is already executing and RIP has already been
1593          * advanced.
1594          */
1595         if (kvm_hlt_in_guest(vcpu->kvm) &&
1596                         vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1597                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1598 }
1599
1600 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
1601 {
1602         struct vcpu_vmx *vmx = to_vmx(vcpu);
1603         unsigned nr = vcpu->arch.exception.nr;
1604         bool has_error_code = vcpu->arch.exception.has_error_code;
1605         u32 error_code = vcpu->arch.exception.error_code;
1606         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1607
1608         kvm_deliver_exception_payload(vcpu);
1609
1610         if (has_error_code) {
1611                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1612                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1613         }
1614
1615         if (vmx->rmode.vm86_active) {
1616                 int inc_eip = 0;
1617                 if (kvm_exception_is_soft(nr))
1618                         inc_eip = vcpu->arch.event_exit_inst_len;
1619                 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
1620                 return;
1621         }
1622
1623         WARN_ON_ONCE(vmx->emulation_required);
1624
1625         if (kvm_exception_is_soft(nr)) {
1626                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1627                              vmx->vcpu.arch.event_exit_inst_len);
1628                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1629         } else
1630                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1631
1632         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1633
1634         vmx_clear_hlt(vcpu);
1635 }
1636
1637 static void vmx_setup_uret_msr(struct vcpu_vmx *vmx, unsigned int msr,
1638                                bool load_into_hardware)
1639 {
1640         struct vmx_uret_msr *uret_msr;
1641
1642         uret_msr = vmx_find_uret_msr(vmx, msr);
1643         if (!uret_msr)
1644                 return;
1645
1646         uret_msr->load_into_hardware = load_into_hardware;
1647 }
1648
1649 /*
1650  * Configuring user return MSRs to automatically save, load, and restore MSRs
1651  * that need to be shoved into hardware when running the guest.  Note, omitting
1652  * an MSR here does _NOT_ mean it's not emulated, only that it will not be
1653  * loaded into hardware when running the guest.
1654  */
1655 static void vmx_setup_uret_msrs(struct vcpu_vmx *vmx)
1656 {
1657 #ifdef CONFIG_X86_64
1658         bool load_syscall_msrs;
1659
1660         /*
1661          * The SYSCALL MSRs are only needed on long mode guests, and only
1662          * when EFER.SCE is set.
1663          */
1664         load_syscall_msrs = is_long_mode(&vmx->vcpu) &&
1665                             (vmx->vcpu.arch.efer & EFER_SCE);
1666
1667         vmx_setup_uret_msr(vmx, MSR_STAR, load_syscall_msrs);
1668         vmx_setup_uret_msr(vmx, MSR_LSTAR, load_syscall_msrs);
1669         vmx_setup_uret_msr(vmx, MSR_SYSCALL_MASK, load_syscall_msrs);
1670 #endif
1671         vmx_setup_uret_msr(vmx, MSR_EFER, update_transition_efer(vmx));
1672
1673         vmx_setup_uret_msr(vmx, MSR_TSC_AUX,
1674                            guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP) ||
1675                            guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDPID));
1676
1677         /*
1678          * hle=0, rtm=0, tsx_ctrl=1 can be found with some combinations of new
1679          * kernel and old userspace.  If those guests run on a tsx=off host, do
1680          * allow guests to use TSX_CTRL, but don't change the value in hardware
1681          * so that TSX remains always disabled.
1682          */
1683         vmx_setup_uret_msr(vmx, MSR_IA32_TSX_CTRL, boot_cpu_has(X86_FEATURE_RTM));
1684
1685         /*
1686          * The set of MSRs to load may have changed, reload MSRs before the
1687          * next VM-Enter.
1688          */
1689         vmx->guest_uret_msrs_loaded = false;
1690 }
1691
1692 u64 vmx_get_l2_tsc_offset(struct kvm_vcpu *vcpu)
1693 {
1694         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1695
1696         if (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETTING))
1697                 return vmcs12->tsc_offset;
1698
1699         return 0;
1700 }
1701
1702 u64 vmx_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu)
1703 {
1704         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1705
1706         if (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETTING) &&
1707             nested_cpu_has2(vmcs12, SECONDARY_EXEC_TSC_SCALING))
1708                 return vmcs12->tsc_multiplier;
1709
1710         return kvm_default_tsc_scaling_ratio;
1711 }
1712
1713 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1714 {
1715         vmcs_write64(TSC_OFFSET, offset);
1716 }
1717
1718 static void vmx_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 multiplier)
1719 {
1720         vmcs_write64(TSC_MULTIPLIER, multiplier);
1721 }
1722
1723 /*
1724  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1725  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1726  * all guests if the "nested" module option is off, and can also be disabled
1727  * for a single guest by disabling its VMX cpuid bit.
1728  */
1729 bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1730 {
1731         return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
1732 }
1733
1734 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1735                                                  uint64_t val)
1736 {
1737         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
1738
1739         return !(val & ~valid_bits);
1740 }
1741
1742 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
1743 {
1744         switch (msr->index) {
1745         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1746                 if (!nested)
1747                         return 1;
1748                 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1749         case MSR_IA32_PERF_CAPABILITIES:
1750                 msr->data = vmx_get_perf_capabilities();
1751                 return 0;
1752         default:
1753                 return KVM_MSR_RET_INVALID;
1754         }
1755 }
1756
1757 /*
1758  * Reads an msr value (of 'msr_index') into 'pdata'.
1759  * Returns 0 on success, non-0 otherwise.
1760  * Assumes vcpu_load() was already called.
1761  */
1762 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1763 {
1764         struct vcpu_vmx *vmx = to_vmx(vcpu);
1765         struct vmx_uret_msr *msr;
1766         u32 index;
1767
1768         switch (msr_info->index) {
1769 #ifdef CONFIG_X86_64
1770         case MSR_FS_BASE:
1771                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
1772                 break;
1773         case MSR_GS_BASE:
1774                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
1775                 break;
1776         case MSR_KERNEL_GS_BASE:
1777                 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
1778                 break;
1779 #endif
1780         case MSR_EFER:
1781                 return kvm_get_msr_common(vcpu, msr_info);
1782         case MSR_IA32_TSX_CTRL:
1783                 if (!msr_info->host_initiated &&
1784                     !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
1785                         return 1;
1786                 goto find_uret_msr;
1787         case MSR_IA32_UMWAIT_CONTROL:
1788                 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1789                         return 1;
1790
1791                 msr_info->data = vmx->msr_ia32_umwait_control;
1792                 break;
1793         case MSR_IA32_SPEC_CTRL:
1794                 if (!msr_info->host_initiated &&
1795                     !guest_has_spec_ctrl_msr(vcpu))
1796                         return 1;
1797
1798                 msr_info->data = to_vmx(vcpu)->spec_ctrl;
1799                 break;
1800         case MSR_IA32_SYSENTER_CS:
1801                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
1802                 break;
1803         case MSR_IA32_SYSENTER_EIP:
1804                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
1805                 break;
1806         case MSR_IA32_SYSENTER_ESP:
1807                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
1808                 break;
1809         case MSR_IA32_BNDCFGS:
1810                 if (!kvm_mpx_supported() ||
1811                     (!msr_info->host_initiated &&
1812                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1813                         return 1;
1814                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
1815                 break;
1816         case MSR_IA32_MCG_EXT_CTL:
1817                 if (!msr_info->host_initiated &&
1818                     !(vmx->msr_ia32_feature_control &
1819                       FEAT_CTL_LMCE_ENABLED))
1820                         return 1;
1821                 msr_info->data = vcpu->arch.mcg_ext_ctl;
1822                 break;
1823         case MSR_IA32_FEAT_CTL:
1824                 msr_info->data = vmx->msr_ia32_feature_control;
1825                 break;
1826         case MSR_IA32_SGXLEPUBKEYHASH0 ... MSR_IA32_SGXLEPUBKEYHASH3:
1827                 if (!msr_info->host_initiated &&
1828                     !guest_cpuid_has(vcpu, X86_FEATURE_SGX_LC))
1829                         return 1;
1830                 msr_info->data = to_vmx(vcpu)->msr_ia32_sgxlepubkeyhash
1831                         [msr_info->index - MSR_IA32_SGXLEPUBKEYHASH0];
1832                 break;
1833         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1834                 if (!nested_vmx_allowed(vcpu))
1835                         return 1;
1836                 if (vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1837                                     &msr_info->data))
1838                         return 1;
1839                 /*
1840                  * Enlightened VMCS v1 doesn't have certain fields, but buggy
1841                  * Hyper-V versions are still trying to use corresponding
1842                  * features when they are exposed. Filter out the essential
1843                  * minimum.
1844                  */
1845                 if (!msr_info->host_initiated &&
1846                     vmx->nested.enlightened_vmcs_enabled)
1847                         nested_evmcs_filter_control_msr(msr_info->index,
1848                                                         &msr_info->data);
1849                 break;
1850         case MSR_IA32_RTIT_CTL:
1851                 if (!vmx_pt_mode_is_host_guest())
1852                         return 1;
1853                 msr_info->data = vmx->pt_desc.guest.ctl;
1854                 break;
1855         case MSR_IA32_RTIT_STATUS:
1856                 if (!vmx_pt_mode_is_host_guest())
1857                         return 1;
1858                 msr_info->data = vmx->pt_desc.guest.status;
1859                 break;
1860         case MSR_IA32_RTIT_CR3_MATCH:
1861                 if (!vmx_pt_mode_is_host_guest() ||
1862                         !intel_pt_validate_cap(vmx->pt_desc.caps,
1863                                                 PT_CAP_cr3_filtering))
1864                         return 1;
1865                 msr_info->data = vmx->pt_desc.guest.cr3_match;
1866                 break;
1867         case MSR_IA32_RTIT_OUTPUT_BASE:
1868                 if (!vmx_pt_mode_is_host_guest() ||
1869                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1870                                         PT_CAP_topa_output) &&
1871                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1872                                         PT_CAP_single_range_output)))
1873                         return 1;
1874                 msr_info->data = vmx->pt_desc.guest.output_base;
1875                 break;
1876         case MSR_IA32_RTIT_OUTPUT_MASK:
1877                 if (!vmx_pt_mode_is_host_guest() ||
1878                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1879                                         PT_CAP_topa_output) &&
1880                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1881                                         PT_CAP_single_range_output)))
1882                         return 1;
1883                 msr_info->data = vmx->pt_desc.guest.output_mask;
1884                 break;
1885         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1886                 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1887                 if (!vmx_pt_mode_is_host_guest() ||
1888                         (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
1889                                         PT_CAP_num_address_ranges)))
1890                         return 1;
1891                 if (index % 2)
1892                         msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1893                 else
1894                         msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1895                 break;
1896         case MSR_IA32_DEBUGCTLMSR:
1897                 msr_info->data = vmcs_read64(GUEST_IA32_DEBUGCTL);
1898                 break;
1899         default:
1900         find_uret_msr:
1901                 msr = vmx_find_uret_msr(vmx, msr_info->index);
1902                 if (msr) {
1903                         msr_info->data = msr->data;
1904                         break;
1905                 }
1906                 return kvm_get_msr_common(vcpu, msr_info);
1907         }
1908
1909         return 0;
1910 }
1911
1912 static u64 nested_vmx_truncate_sysenter_addr(struct kvm_vcpu *vcpu,
1913                                                     u64 data)
1914 {
1915 #ifdef CONFIG_X86_64
1916         if (!guest_cpuid_has(vcpu, X86_FEATURE_LM))
1917                 return (u32)data;
1918 #endif
1919         return (unsigned long)data;
1920 }
1921
1922 static u64 vcpu_supported_debugctl(struct kvm_vcpu *vcpu)
1923 {
1924         u64 debugctl = vmx_supported_debugctl();
1925
1926         if (!intel_pmu_lbr_is_enabled(vcpu))
1927                 debugctl &= ~DEBUGCTLMSR_LBR_MASK;
1928
1929         if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT))
1930                 debugctl &= ~DEBUGCTLMSR_BUS_LOCK_DETECT;
1931
1932         return debugctl;
1933 }
1934
1935 /*
1936  * Writes msr value into the appropriate "register".
1937  * Returns 0 on success, non-0 otherwise.
1938  * Assumes vcpu_load() was already called.
1939  */
1940 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1941 {
1942         struct vcpu_vmx *vmx = to_vmx(vcpu);
1943         struct vmx_uret_msr *msr;
1944         int ret = 0;
1945         u32 msr_index = msr_info->index;
1946         u64 data = msr_info->data;
1947         u32 index;
1948
1949         switch (msr_index) {
1950         case MSR_EFER:
1951                 ret = kvm_set_msr_common(vcpu, msr_info);
1952                 break;
1953 #ifdef CONFIG_X86_64
1954         case MSR_FS_BASE:
1955                 vmx_segment_cache_clear(vmx);
1956                 vmcs_writel(GUEST_FS_BASE, data);
1957                 break;
1958         case MSR_GS_BASE:
1959                 vmx_segment_cache_clear(vmx);
1960                 vmcs_writel(GUEST_GS_BASE, data);
1961                 break;
1962         case MSR_KERNEL_GS_BASE:
1963                 vmx_write_guest_kernel_gs_base(vmx, data);
1964                 break;
1965 #endif
1966         case MSR_IA32_SYSENTER_CS:
1967                 if (is_guest_mode(vcpu))
1968                         get_vmcs12(vcpu)->guest_sysenter_cs = data;
1969                 vmcs_write32(GUEST_SYSENTER_CS, data);
1970                 break;
1971         case MSR_IA32_SYSENTER_EIP:
1972                 if (is_guest_mode(vcpu)) {
1973                         data = nested_vmx_truncate_sysenter_addr(vcpu, data);
1974                         get_vmcs12(vcpu)->guest_sysenter_eip = data;
1975                 }
1976                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1977                 break;
1978         case MSR_IA32_SYSENTER_ESP:
1979                 if (is_guest_mode(vcpu)) {
1980                         data = nested_vmx_truncate_sysenter_addr(vcpu, data);
1981                         get_vmcs12(vcpu)->guest_sysenter_esp = data;
1982                 }
1983                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1984                 break;
1985         case MSR_IA32_DEBUGCTLMSR: {
1986                 u64 invalid = data & ~vcpu_supported_debugctl(vcpu);
1987                 if (invalid & (DEBUGCTLMSR_BTF|DEBUGCTLMSR_LBR)) {
1988                         if (report_ignored_msrs)
1989                                 vcpu_unimpl(vcpu, "%s: BTF|LBR in IA32_DEBUGCTLMSR 0x%llx, nop\n",
1990                                             __func__, data);
1991                         data &= ~(DEBUGCTLMSR_BTF|DEBUGCTLMSR_LBR);
1992                         invalid &= ~(DEBUGCTLMSR_BTF|DEBUGCTLMSR_LBR);
1993                 }
1994
1995                 if (invalid)
1996                         return 1;
1997
1998                 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
1999                                                 VM_EXIT_SAVE_DEBUG_CONTROLS)
2000                         get_vmcs12(vcpu)->guest_ia32_debugctl = data;
2001
2002                 vmcs_write64(GUEST_IA32_DEBUGCTL, data);
2003                 if (intel_pmu_lbr_is_enabled(vcpu) && !to_vmx(vcpu)->lbr_desc.event &&
2004                     (data & DEBUGCTLMSR_LBR))
2005                         intel_pmu_create_guest_lbr_event(vcpu);
2006                 return 0;
2007         }
2008         case MSR_IA32_BNDCFGS:
2009                 if (!kvm_mpx_supported() ||
2010                     (!msr_info->host_initiated &&
2011                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
2012                         return 1;
2013                 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
2014                     (data & MSR_IA32_BNDCFGS_RSVD))
2015                         return 1;
2016                 vmcs_write64(GUEST_BNDCFGS, data);
2017                 break;
2018         case MSR_IA32_UMWAIT_CONTROL:
2019                 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
2020                         return 1;
2021
2022                 /* The reserved bit 1 and non-32 bit [63:32] should be zero */
2023                 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
2024                         return 1;
2025
2026                 vmx->msr_ia32_umwait_control = data;
2027                 break;
2028         case MSR_IA32_SPEC_CTRL:
2029                 if (!msr_info->host_initiated &&
2030                     !guest_has_spec_ctrl_msr(vcpu))
2031                         return 1;
2032
2033                 if (kvm_spec_ctrl_test_value(data))
2034                         return 1;
2035
2036                 vmx->spec_ctrl = data;
2037                 if (!data)
2038                         break;
2039
2040                 /*
2041                  * For non-nested:
2042                  * When it's written (to non-zero) for the first time, pass
2043                  * it through.
2044                  *
2045                  * For nested:
2046                  * The handling of the MSR bitmap for L2 guests is done in
2047                  * nested_vmx_prepare_msr_bitmap. We should not touch the
2048                  * vmcs02.msr_bitmap here since it gets completely overwritten
2049                  * in the merging. We update the vmcs01 here for L1 as well
2050                  * since it will end up touching the MSR anyway now.
2051                  */
2052                 vmx_disable_intercept_for_msr(vcpu,
2053                                               MSR_IA32_SPEC_CTRL,
2054                                               MSR_TYPE_RW);
2055                 break;
2056         case MSR_IA32_TSX_CTRL:
2057                 if (!msr_info->host_initiated &&
2058                     !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
2059                         return 1;
2060                 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR))
2061                         return 1;
2062                 goto find_uret_msr;
2063         case MSR_IA32_PRED_CMD:
2064                 if (!msr_info->host_initiated &&
2065                     !guest_has_pred_cmd_msr(vcpu))
2066                         return 1;
2067
2068                 if (data & ~PRED_CMD_IBPB)
2069                         return 1;
2070                 if (!boot_cpu_has(X86_FEATURE_IBPB))
2071                         return 1;
2072                 if (!data)
2073                         break;
2074
2075                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2076
2077                 /*
2078                  * For non-nested:
2079                  * When it's written (to non-zero) for the first time, pass
2080                  * it through.
2081                  *
2082                  * For nested:
2083                  * The handling of the MSR bitmap for L2 guests is done in
2084                  * nested_vmx_prepare_msr_bitmap. We should not touch the
2085                  * vmcs02.msr_bitmap here since it gets completely overwritten
2086                  * in the merging.
2087                  */
2088                 vmx_disable_intercept_for_msr(vcpu, MSR_IA32_PRED_CMD, MSR_TYPE_W);
2089                 break;
2090         case MSR_IA32_CR_PAT:
2091                 if (!kvm_pat_valid(data))
2092                         return 1;
2093
2094                 if (is_guest_mode(vcpu) &&
2095                     get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
2096                         get_vmcs12(vcpu)->guest_ia32_pat = data;
2097
2098                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2099                         vmcs_write64(GUEST_IA32_PAT, data);
2100                         vcpu->arch.pat = data;
2101                         break;
2102                 }
2103                 ret = kvm_set_msr_common(vcpu, msr_info);
2104                 break;
2105         case MSR_IA32_TSC_ADJUST:
2106                 ret = kvm_set_msr_common(vcpu, msr_info);
2107                 break;
2108         case MSR_IA32_MCG_EXT_CTL:
2109                 if ((!msr_info->host_initiated &&
2110                      !(to_vmx(vcpu)->msr_ia32_feature_control &
2111                        FEAT_CTL_LMCE_ENABLED)) ||
2112                     (data & ~MCG_EXT_CTL_LMCE_EN))
2113                         return 1;
2114                 vcpu->arch.mcg_ext_ctl = data;
2115                 break;
2116         case MSR_IA32_FEAT_CTL:
2117                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
2118                     (to_vmx(vcpu)->msr_ia32_feature_control &
2119                      FEAT_CTL_LOCKED && !msr_info->host_initiated))
2120                         return 1;
2121                 vmx->msr_ia32_feature_control = data;
2122                 if (msr_info->host_initiated && data == 0)
2123                         vmx_leave_nested(vcpu);
2124
2125                 /* SGX may be enabled/disabled by guest's firmware */
2126                 vmx_write_encls_bitmap(vcpu, NULL);
2127                 break;
2128         case MSR_IA32_SGXLEPUBKEYHASH0 ... MSR_IA32_SGXLEPUBKEYHASH3:
2129                 /*
2130                  * On real hardware, the LE hash MSRs are writable before
2131                  * the firmware sets bit 0 in MSR 0x7a ("activating" SGX),
2132                  * at which point SGX related bits in IA32_FEATURE_CONTROL
2133                  * become writable.
2134                  *
2135                  * KVM does not emulate SGX activation for simplicity, so
2136                  * allow writes to the LE hash MSRs if IA32_FEATURE_CONTROL
2137                  * is unlocked.  This is technically not architectural
2138                  * behavior, but it's close enough.
2139                  */
2140                 if (!msr_info->host_initiated &&
2141                     (!guest_cpuid_has(vcpu, X86_FEATURE_SGX_LC) ||
2142                     ((vmx->msr_ia32_feature_control & FEAT_CTL_LOCKED) &&
2143                     !(vmx->msr_ia32_feature_control & FEAT_CTL_SGX_LC_ENABLED))))
2144                         return 1;
2145                 vmx->msr_ia32_sgxlepubkeyhash
2146                         [msr_index - MSR_IA32_SGXLEPUBKEYHASH0] = data;
2147                 break;
2148         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2149                 if (!msr_info->host_initiated)
2150                         return 1; /* they are read-only */
2151                 if (!nested_vmx_allowed(vcpu))
2152                         return 1;
2153                 return vmx_set_vmx_msr(vcpu, msr_index, data);
2154         case MSR_IA32_RTIT_CTL:
2155                 if (!vmx_pt_mode_is_host_guest() ||
2156                         vmx_rtit_ctl_check(vcpu, data) ||
2157                         vmx->nested.vmxon)
2158                         return 1;
2159                 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
2160                 vmx->pt_desc.guest.ctl = data;
2161                 pt_update_intercept_for_msr(vcpu);
2162                 break;
2163         case MSR_IA32_RTIT_STATUS:
2164                 if (!pt_can_write_msr(vmx))
2165                         return 1;
2166                 if (data & MSR_IA32_RTIT_STATUS_MASK)
2167                         return 1;
2168                 vmx->pt_desc.guest.status = data;
2169                 break;
2170         case MSR_IA32_RTIT_CR3_MATCH:
2171                 if (!pt_can_write_msr(vmx))
2172                         return 1;
2173                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2174                                            PT_CAP_cr3_filtering))
2175                         return 1;
2176                 vmx->pt_desc.guest.cr3_match = data;
2177                 break;
2178         case MSR_IA32_RTIT_OUTPUT_BASE:
2179                 if (!pt_can_write_msr(vmx))
2180                         return 1;
2181                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2182                                            PT_CAP_topa_output) &&
2183                     !intel_pt_validate_cap(vmx->pt_desc.caps,
2184                                            PT_CAP_single_range_output))
2185                         return 1;
2186                 if (!pt_output_base_valid(vcpu, data))
2187                         return 1;
2188                 vmx->pt_desc.guest.output_base = data;
2189                 break;
2190         case MSR_IA32_RTIT_OUTPUT_MASK:
2191                 if (!pt_can_write_msr(vmx))
2192                         return 1;
2193                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2194                                            PT_CAP_topa_output) &&
2195                     !intel_pt_validate_cap(vmx->pt_desc.caps,
2196                                            PT_CAP_single_range_output))
2197                         return 1;
2198                 vmx->pt_desc.guest.output_mask = data;
2199                 break;
2200         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2201                 if (!pt_can_write_msr(vmx))
2202                         return 1;
2203                 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2204                 if (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
2205                                                        PT_CAP_num_address_ranges))
2206                         return 1;
2207                 if (is_noncanonical_address(data, vcpu))
2208                         return 1;
2209                 if (index % 2)
2210                         vmx->pt_desc.guest.addr_b[index / 2] = data;
2211                 else
2212                         vmx->pt_desc.guest.addr_a[index / 2] = data;
2213                 break;
2214         case MSR_IA32_PERF_CAPABILITIES:
2215                 if (data && !vcpu_to_pmu(vcpu)->version)
2216                         return 1;
2217                 if (data & PMU_CAP_LBR_FMT) {
2218                         if ((data & PMU_CAP_LBR_FMT) !=
2219                             (vmx_get_perf_capabilities() & PMU_CAP_LBR_FMT))
2220                                 return 1;
2221                         if (!intel_pmu_lbr_is_compatible(vcpu))
2222                                 return 1;
2223                 }
2224                 ret = kvm_set_msr_common(vcpu, msr_info);
2225                 break;
2226
2227         default:
2228         find_uret_msr:
2229                 msr = vmx_find_uret_msr(vmx, msr_index);
2230                 if (msr)
2231                         ret = vmx_set_guest_uret_msr(vmx, msr, data);
2232                 else
2233                         ret = kvm_set_msr_common(vcpu, msr_info);
2234         }
2235
2236         return ret;
2237 }
2238
2239 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2240 {
2241         unsigned long guest_owned_bits;
2242
2243         kvm_register_mark_available(vcpu, reg);
2244
2245         switch (reg) {
2246         case VCPU_REGS_RSP:
2247                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2248                 break;
2249         case VCPU_REGS_RIP:
2250                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2251                 break;
2252         case VCPU_EXREG_PDPTR:
2253                 if (enable_ept)
2254                         ept_save_pdptrs(vcpu);
2255                 break;
2256         case VCPU_EXREG_CR0:
2257                 guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2258
2259                 vcpu->arch.cr0 &= ~guest_owned_bits;
2260                 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & guest_owned_bits;
2261                 break;
2262         case VCPU_EXREG_CR3:
2263                 /*
2264                  * When intercepting CR3 loads, e.g. for shadowing paging, KVM's
2265                  * CR3 is loaded into hardware, not the guest's CR3.
2266                  */
2267                 if (!(exec_controls_get(to_vmx(vcpu)) & CPU_BASED_CR3_LOAD_EXITING))
2268                         vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2269                 break;
2270         case VCPU_EXREG_CR4:
2271                 guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2272
2273                 vcpu->arch.cr4 &= ~guest_owned_bits;
2274                 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & guest_owned_bits;
2275                 break;
2276         default:
2277                 KVM_BUG_ON(1, vcpu->kvm);
2278                 break;
2279         }
2280 }
2281
2282 static __init int cpu_has_kvm_support(void)
2283 {
2284         return cpu_has_vmx();
2285 }
2286
2287 static __init int vmx_disabled_by_bios(void)
2288 {
2289         return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
2290                !boot_cpu_has(X86_FEATURE_VMX);
2291 }
2292
2293 static int kvm_cpu_vmxon(u64 vmxon_pointer)
2294 {
2295         u64 msr;
2296
2297         cr4_set_bits(X86_CR4_VMXE);
2298
2299         asm_volatile_goto("1: vmxon %[vmxon_pointer]\n\t"
2300                           _ASM_EXTABLE(1b, %l[fault])
2301                           : : [vmxon_pointer] "m"(vmxon_pointer)
2302                           : : fault);
2303         return 0;
2304
2305 fault:
2306         WARN_ONCE(1, "VMXON faulted, MSR_IA32_FEAT_CTL (0x3a) = 0x%llx\n",
2307                   rdmsrl_safe(MSR_IA32_FEAT_CTL, &msr) ? 0xdeadbeef : msr);
2308         cr4_clear_bits(X86_CR4_VMXE);
2309
2310         return -EFAULT;
2311 }
2312
2313 static int hardware_enable(void)
2314 {
2315         int cpu = raw_smp_processor_id();
2316         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2317         int r;
2318
2319         if (cr4_read_shadow() & X86_CR4_VMXE)
2320                 return -EBUSY;
2321
2322         /*
2323          * This can happen if we hot-added a CPU but failed to allocate
2324          * VP assist page for it.
2325          */
2326         if (static_branch_unlikely(&enable_evmcs) &&
2327             !hv_get_vp_assist_page(cpu))
2328                 return -EFAULT;
2329
2330         intel_pt_handle_vmx(1);
2331
2332         r = kvm_cpu_vmxon(phys_addr);
2333         if (r) {
2334                 intel_pt_handle_vmx(0);
2335                 return r;
2336         }
2337
2338         if (enable_ept)
2339                 ept_sync_global();
2340
2341         return 0;
2342 }
2343
2344 static void vmclear_local_loaded_vmcss(void)
2345 {
2346         int cpu = raw_smp_processor_id();
2347         struct loaded_vmcs *v, *n;
2348
2349         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2350                                  loaded_vmcss_on_cpu_link)
2351                 __loaded_vmcs_clear(v);
2352 }
2353
2354 static void hardware_disable(void)
2355 {
2356         vmclear_local_loaded_vmcss();
2357
2358         if (cpu_vmxoff())
2359                 kvm_spurious_fault();
2360
2361         intel_pt_handle_vmx(0);
2362 }
2363
2364 /*
2365  * There is no X86_FEATURE for SGX yet, but anyway we need to query CPUID
2366  * directly instead of going through cpu_has(), to ensure KVM is trapping
2367  * ENCLS whenever it's supported in hardware.  It does not matter whether
2368  * the host OS supports or has enabled SGX.
2369  */
2370 static bool cpu_has_sgx(void)
2371 {
2372         return cpuid_eax(0) >= 0x12 && (cpuid_eax(0x12) & BIT(0));
2373 }
2374
2375 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2376                                       u32 msr, u32 *result)
2377 {
2378         u32 vmx_msr_low, vmx_msr_high;
2379         u32 ctl = ctl_min | ctl_opt;
2380
2381         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2382
2383         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2384         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2385
2386         /* Ensure minimum (required) set of control bits are supported. */
2387         if (ctl_min & ~ctl)
2388                 return -EIO;
2389
2390         *result = ctl;
2391         return 0;
2392 }
2393
2394 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2395                                     struct vmx_capability *vmx_cap)
2396 {
2397         u32 vmx_msr_low, vmx_msr_high;
2398         u32 min, opt, min2, opt2;
2399         u32 _pin_based_exec_control = 0;
2400         u32 _cpu_based_exec_control = 0;
2401         u32 _cpu_based_2nd_exec_control = 0;
2402         u32 _vmexit_control = 0;
2403         u32 _vmentry_control = 0;
2404
2405         memset(vmcs_conf, 0, sizeof(*vmcs_conf));
2406         min = CPU_BASED_HLT_EXITING |
2407 #ifdef CONFIG_X86_64
2408               CPU_BASED_CR8_LOAD_EXITING |
2409               CPU_BASED_CR8_STORE_EXITING |
2410 #endif
2411               CPU_BASED_CR3_LOAD_EXITING |
2412               CPU_BASED_CR3_STORE_EXITING |
2413               CPU_BASED_UNCOND_IO_EXITING |
2414               CPU_BASED_MOV_DR_EXITING |
2415               CPU_BASED_USE_TSC_OFFSETTING |
2416               CPU_BASED_MWAIT_EXITING |
2417               CPU_BASED_MONITOR_EXITING |
2418               CPU_BASED_INVLPG_EXITING |
2419               CPU_BASED_RDPMC_EXITING;
2420
2421         opt = CPU_BASED_TPR_SHADOW |
2422               CPU_BASED_USE_MSR_BITMAPS |
2423               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2424         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2425                                 &_cpu_based_exec_control) < 0)
2426                 return -EIO;
2427 #ifdef CONFIG_X86_64
2428         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2429                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2430                                            ~CPU_BASED_CR8_STORE_EXITING;
2431 #endif
2432         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2433                 min2 = 0;
2434                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2435                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2436                         SECONDARY_EXEC_WBINVD_EXITING |
2437                         SECONDARY_EXEC_ENABLE_VPID |
2438                         SECONDARY_EXEC_ENABLE_EPT |
2439                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2440                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2441                         SECONDARY_EXEC_DESC |
2442                         SECONDARY_EXEC_ENABLE_RDTSCP |
2443                         SECONDARY_EXEC_ENABLE_INVPCID |
2444                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2445                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2446                         SECONDARY_EXEC_SHADOW_VMCS |
2447                         SECONDARY_EXEC_XSAVES |
2448                         SECONDARY_EXEC_RDSEED_EXITING |
2449                         SECONDARY_EXEC_RDRAND_EXITING |
2450                         SECONDARY_EXEC_ENABLE_PML |
2451                         SECONDARY_EXEC_TSC_SCALING |
2452                         SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
2453                         SECONDARY_EXEC_PT_USE_GPA |
2454                         SECONDARY_EXEC_PT_CONCEAL_VMX |
2455                         SECONDARY_EXEC_ENABLE_VMFUNC |
2456                         SECONDARY_EXEC_BUS_LOCK_DETECTION;
2457                 if (cpu_has_sgx())
2458                         opt2 |= SECONDARY_EXEC_ENCLS_EXITING;
2459                 if (adjust_vmx_controls(min2, opt2,
2460                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2461                                         &_cpu_based_2nd_exec_control) < 0)
2462                         return -EIO;
2463         }
2464 #ifndef CONFIG_X86_64
2465         if (!(_cpu_based_2nd_exec_control &
2466                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2467                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2468 #endif
2469
2470         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2471                 _cpu_based_2nd_exec_control &= ~(
2472                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2473                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2474                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2475
2476         rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
2477                 &vmx_cap->ept, &vmx_cap->vpid);
2478
2479         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2480                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2481                    enabled */
2482                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2483                                              CPU_BASED_CR3_STORE_EXITING |
2484                                              CPU_BASED_INVLPG_EXITING);
2485         } else if (vmx_cap->ept) {
2486                 vmx_cap->ept = 0;
2487                 pr_warn_once("EPT CAP should not exist if not support "
2488                                 "1-setting enable EPT VM-execution control\n");
2489         }
2490         if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
2491                 vmx_cap->vpid) {
2492                 vmx_cap->vpid = 0;
2493                 pr_warn_once("VPID CAP should not exist if not support "
2494                                 "1-setting enable VPID VM-execution control\n");
2495         }
2496
2497         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
2498 #ifdef CONFIG_X86_64
2499         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2500 #endif
2501         opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2502               VM_EXIT_LOAD_IA32_PAT |
2503               VM_EXIT_LOAD_IA32_EFER |
2504               VM_EXIT_CLEAR_BNDCFGS |
2505               VM_EXIT_PT_CONCEAL_PIP |
2506               VM_EXIT_CLEAR_IA32_RTIT_CTL;
2507         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2508                                 &_vmexit_control) < 0)
2509                 return -EIO;
2510
2511         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2512         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2513                  PIN_BASED_VMX_PREEMPTION_TIMER;
2514         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2515                                 &_pin_based_exec_control) < 0)
2516                 return -EIO;
2517
2518         if (cpu_has_broken_vmx_preemption_timer())
2519                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2520         if (!(_cpu_based_2nd_exec_control &
2521                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
2522                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2523
2524         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2525         opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2526               VM_ENTRY_LOAD_IA32_PAT |
2527               VM_ENTRY_LOAD_IA32_EFER |
2528               VM_ENTRY_LOAD_BNDCFGS |
2529               VM_ENTRY_PT_CONCEAL_PIP |
2530               VM_ENTRY_LOAD_IA32_RTIT_CTL;
2531         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2532                                 &_vmentry_control) < 0)
2533                 return -EIO;
2534
2535         /*
2536          * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2537          * can't be used due to an errata where VM Exit may incorrectly clear
2538          * IA32_PERF_GLOBAL_CTRL[34:32].  Workaround the errata by using the
2539          * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2540          */
2541         if (boot_cpu_data.x86 == 0x6) {
2542                 switch (boot_cpu_data.x86_model) {
2543                 case 26: /* AAK155 */
2544                 case 30: /* AAP115 */
2545                 case 37: /* AAT100 */
2546                 case 44: /* BC86,AAY89,BD102 */
2547                 case 46: /* BA97 */
2548                         _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
2549                         _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2550                         pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2551                                         "does not work properly. Using workaround\n");
2552                         break;
2553                 default:
2554                         break;
2555                 }
2556         }
2557
2558
2559         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2560
2561         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2562         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2563                 return -EIO;
2564
2565 #ifdef CONFIG_X86_64
2566         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2567         if (vmx_msr_high & (1u<<16))
2568                 return -EIO;
2569 #endif
2570
2571         /* Require Write-Back (WB) memory type for VMCS accesses. */
2572         if (((vmx_msr_high >> 18) & 15) != 6)
2573                 return -EIO;
2574
2575         vmcs_conf->size = vmx_msr_high & 0x1fff;
2576         vmcs_conf->order = get_order(vmcs_conf->size);
2577         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
2578
2579         vmcs_conf->revision_id = vmx_msr_low;
2580
2581         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2582         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2583         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2584         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2585         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2586
2587 #if IS_ENABLED(CONFIG_HYPERV)
2588         if (enlightened_vmcs)
2589                 evmcs_sanitize_exec_ctrls(vmcs_conf);
2590 #endif
2591
2592         return 0;
2593 }
2594
2595 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
2596 {
2597         int node = cpu_to_node(cpu);
2598         struct page *pages;
2599         struct vmcs *vmcs;
2600
2601         pages = __alloc_pages_node(node, flags, vmcs_config.order);
2602         if (!pages)
2603                 return NULL;
2604         vmcs = page_address(pages);
2605         memset(vmcs, 0, vmcs_config.size);
2606
2607         /* KVM supports Enlightened VMCS v1 only */
2608         if (static_branch_unlikely(&enable_evmcs))
2609                 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2610         else
2611                 vmcs->hdr.revision_id = vmcs_config.revision_id;
2612
2613         if (shadow)
2614                 vmcs->hdr.shadow_vmcs = 1;
2615         return vmcs;
2616 }
2617
2618 void free_vmcs(struct vmcs *vmcs)
2619 {
2620         free_pages((unsigned long)vmcs, vmcs_config.order);
2621 }
2622
2623 /*
2624  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2625  */
2626 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2627 {
2628         if (!loaded_vmcs->vmcs)
2629                 return;
2630         loaded_vmcs_clear(loaded_vmcs);
2631         free_vmcs(loaded_vmcs->vmcs);
2632         loaded_vmcs->vmcs = NULL;
2633         if (loaded_vmcs->msr_bitmap)
2634                 free_page((unsigned long)loaded_vmcs->msr_bitmap);
2635         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
2636 }
2637
2638 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2639 {
2640         loaded_vmcs->vmcs = alloc_vmcs(false);
2641         if (!loaded_vmcs->vmcs)
2642                 return -ENOMEM;
2643
2644         vmcs_clear(loaded_vmcs->vmcs);
2645
2646         loaded_vmcs->shadow_vmcs = NULL;
2647         loaded_vmcs->hv_timer_soft_disabled = false;
2648         loaded_vmcs->cpu = -1;
2649         loaded_vmcs->launched = 0;
2650
2651         if (cpu_has_vmx_msr_bitmap()) {
2652                 loaded_vmcs->msr_bitmap = (unsigned long *)
2653                                 __get_free_page(GFP_KERNEL_ACCOUNT);
2654                 if (!loaded_vmcs->msr_bitmap)
2655                         goto out_vmcs;
2656                 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
2657
2658                 if (IS_ENABLED(CONFIG_HYPERV) &&
2659                     static_branch_unlikely(&enable_evmcs) &&
2660                     (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2661                         struct hv_enlightened_vmcs *evmcs =
2662                                 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2663
2664                         evmcs->hv_enlightenments_control.msr_bitmap = 1;
2665                 }
2666         }
2667
2668         memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2669         memset(&loaded_vmcs->controls_shadow, 0,
2670                 sizeof(struct vmcs_controls_shadow));
2671
2672         return 0;
2673
2674 out_vmcs:
2675         free_loaded_vmcs(loaded_vmcs);
2676         return -ENOMEM;
2677 }
2678
2679 static void free_kvm_area(void)
2680 {
2681         int cpu;
2682
2683         for_each_possible_cpu(cpu) {
2684                 free_vmcs(per_cpu(vmxarea, cpu));
2685                 per_cpu(vmxarea, cpu) = NULL;
2686         }
2687 }
2688
2689 static __init int alloc_kvm_area(void)
2690 {
2691         int cpu;
2692
2693         for_each_possible_cpu(cpu) {
2694                 struct vmcs *vmcs;
2695
2696                 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
2697                 if (!vmcs) {
2698                         free_kvm_area();
2699                         return -ENOMEM;
2700                 }
2701
2702                 /*
2703                  * When eVMCS is enabled, alloc_vmcs_cpu() sets
2704                  * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2705                  * revision_id reported by MSR_IA32_VMX_BASIC.
2706                  *
2707                  * However, even though not explicitly documented by
2708                  * TLFS, VMXArea passed as VMXON argument should
2709                  * still be marked with revision_id reported by
2710                  * physical CPU.
2711                  */
2712                 if (static_branch_unlikely(&enable_evmcs))
2713                         vmcs->hdr.revision_id = vmcs_config.revision_id;
2714
2715                 per_cpu(vmxarea, cpu) = vmcs;
2716         }
2717         return 0;
2718 }
2719
2720 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2721                 struct kvm_segment *save)
2722 {
2723         if (!emulate_invalid_guest_state) {
2724                 /*
2725                  * CS and SS RPL should be equal during guest entry according
2726                  * to VMX spec, but in reality it is not always so. Since vcpu
2727                  * is in the middle of the transition from real mode to
2728                  * protected mode it is safe to assume that RPL 0 is a good
2729                  * default value.
2730                  */
2731                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2732                         save->selector &= ~SEGMENT_RPL_MASK;
2733                 save->dpl = save->selector & SEGMENT_RPL_MASK;
2734                 save->s = 1;
2735         }
2736         __vmx_set_segment(vcpu, save, seg);
2737 }
2738
2739 static void enter_pmode(struct kvm_vcpu *vcpu)
2740 {
2741         unsigned long flags;
2742         struct vcpu_vmx *vmx = to_vmx(vcpu);
2743
2744         /*
2745          * Update real mode segment cache. It may be not up-to-date if segment
2746          * register was written while vcpu was in a guest mode.
2747          */
2748         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2749         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2750         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2751         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2752         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2753         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2754
2755         vmx->rmode.vm86_active = 0;
2756
2757         __vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2758
2759         flags = vmcs_readl(GUEST_RFLAGS);
2760         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2761         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2762         vmcs_writel(GUEST_RFLAGS, flags);
2763
2764         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2765                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2766
2767         vmx_update_exception_bitmap(vcpu);
2768
2769         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2770         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2771         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2772         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2773         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2774         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2775 }
2776
2777 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2778 {
2779         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2780         struct kvm_segment var = *save;
2781
2782         var.dpl = 0x3;
2783         if (seg == VCPU_SREG_CS)
2784                 var.type = 0x3;
2785
2786         if (!emulate_invalid_guest_state) {
2787                 var.selector = var.base >> 4;
2788                 var.base = var.base & 0xffff0;
2789                 var.limit = 0xffff;
2790                 var.g = 0;
2791                 var.db = 0;
2792                 var.present = 1;
2793                 var.s = 1;
2794                 var.l = 0;
2795                 var.unusable = 0;
2796                 var.type = 0x3;
2797                 var.avl = 0;
2798                 if (save->base & 0xf)
2799                         printk_once(KERN_WARNING "kvm: segment base is not "
2800                                         "paragraph aligned when entering "
2801                                         "protected mode (seg=%d)", seg);
2802         }
2803
2804         vmcs_write16(sf->selector, var.selector);
2805         vmcs_writel(sf->base, var.base);
2806         vmcs_write32(sf->limit, var.limit);
2807         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2808 }
2809
2810 static void enter_rmode(struct kvm_vcpu *vcpu)
2811 {
2812         unsigned long flags;
2813         struct vcpu_vmx *vmx = to_vmx(vcpu);
2814         struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
2815
2816         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2817         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2818         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2819         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2820         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2821         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2822         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2823
2824         vmx->rmode.vm86_active = 1;
2825
2826         /*
2827          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2828          * vcpu. Warn the user that an update is overdue.
2829          */
2830         if (!kvm_vmx->tss_addr)
2831                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2832                              "called before entering vcpu\n");
2833
2834         vmx_segment_cache_clear(vmx);
2835
2836         vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
2837         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2838         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2839
2840         flags = vmcs_readl(GUEST_RFLAGS);
2841         vmx->rmode.save_rflags = flags;
2842
2843         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2844
2845         vmcs_writel(GUEST_RFLAGS, flags);
2846         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2847         vmx_update_exception_bitmap(vcpu);
2848
2849         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2850         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2851         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2852         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2853         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2854         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2855 }
2856
2857 int vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2858 {
2859         struct vcpu_vmx *vmx = to_vmx(vcpu);
2860         struct vmx_uret_msr *msr = vmx_find_uret_msr(vmx, MSR_EFER);
2861
2862         /* Nothing to do if hardware doesn't support EFER. */
2863         if (!msr)
2864                 return 0;
2865
2866         vcpu->arch.efer = efer;
2867         if (efer & EFER_LMA) {
2868                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2869                 msr->data = efer;
2870         } else {
2871                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2872
2873                 msr->data = efer & ~EFER_LME;
2874         }
2875         vmx_setup_uret_msrs(vmx);
2876         return 0;
2877 }
2878
2879 #ifdef CONFIG_X86_64
2880
2881 static void enter_lmode(struct kvm_vcpu *vcpu)
2882 {
2883         u32 guest_tr_ar;
2884
2885         vmx_segment_cache_clear(to_vmx(vcpu));
2886
2887         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2888         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
2889                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2890                                      __func__);
2891                 vmcs_write32(GUEST_TR_AR_BYTES,
2892                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2893                              | VMX_AR_TYPE_BUSY_64_TSS);
2894         }
2895         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2896 }
2897
2898 static void exit_lmode(struct kvm_vcpu *vcpu)
2899 {
2900         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2901         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2902 }
2903
2904 #endif
2905
2906 static void vmx_flush_tlb_all(struct kvm_vcpu *vcpu)
2907 {
2908         struct vcpu_vmx *vmx = to_vmx(vcpu);
2909
2910         /*
2911          * INVEPT must be issued when EPT is enabled, irrespective of VPID, as
2912          * the CPU is not required to invalidate guest-physical mappings on
2913          * VM-Entry, even if VPID is disabled.  Guest-physical mappings are
2914          * associated with the root EPT structure and not any particular VPID
2915          * (INVVPID also isn't required to invalidate guest-physical mappings).
2916          */
2917         if (enable_ept) {
2918                 ept_sync_global();
2919         } else if (enable_vpid) {
2920                 if (cpu_has_vmx_invvpid_global()) {
2921                         vpid_sync_vcpu_global();
2922                 } else {
2923                         vpid_sync_vcpu_single(vmx->vpid);
2924                         vpid_sync_vcpu_single(vmx->nested.vpid02);
2925                 }
2926         }
2927 }
2928
2929 static void vmx_flush_tlb_current(struct kvm_vcpu *vcpu)
2930 {
2931         struct kvm_mmu *mmu = vcpu->arch.mmu;
2932         u64 root_hpa = mmu->root_hpa;
2933
2934         /* No flush required if the current context is invalid. */
2935         if (!VALID_PAGE(root_hpa))
2936                 return;
2937
2938         if (enable_ept)
2939                 ept_sync_context(construct_eptp(vcpu, root_hpa,
2940                                                 mmu->shadow_root_level));
2941         else if (!is_guest_mode(vcpu))
2942                 vpid_sync_context(to_vmx(vcpu)->vpid);
2943         else
2944                 vpid_sync_context(nested_get_vpid02(vcpu));
2945 }
2946
2947 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2948 {
2949         /*
2950          * vpid_sync_vcpu_addr() is a nop if vmx->vpid==0, see the comment in
2951          * vmx_flush_tlb_guest() for an explanation of why this is ok.
2952          */
2953         vpid_sync_vcpu_addr(to_vmx(vcpu)->vpid, addr);
2954 }
2955
2956 static void vmx_flush_tlb_guest(struct kvm_vcpu *vcpu)
2957 {
2958         /*
2959          * vpid_sync_context() is a nop if vmx->vpid==0, e.g. if enable_vpid==0
2960          * or a vpid couldn't be allocated for this vCPU.  VM-Enter and VM-Exit
2961          * are required to flush GVA->{G,H}PA mappings from the TLB if vpid is
2962          * disabled (VM-Enter with vpid enabled and vpid==0 is disallowed),
2963          * i.e. no explicit INVVPID is necessary.
2964          */
2965         vpid_sync_context(to_vmx(vcpu)->vpid);
2966 }
2967
2968 void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu)
2969 {
2970         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2971
2972         if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR))
2973                 return;
2974
2975         if (is_pae_paging(vcpu)) {
2976                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2977                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2978                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2979                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
2980         }
2981 }
2982
2983 void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2984 {
2985         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2986
2987         if (WARN_ON_ONCE(!is_pae_paging(vcpu)))
2988                 return;
2989
2990         mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2991         mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2992         mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2993         mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2994
2995         kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
2996 }
2997
2998 #define CR3_EXITING_BITS (CPU_BASED_CR3_LOAD_EXITING | \
2999                           CPU_BASED_CR3_STORE_EXITING)
3000
3001 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3002 {
3003         struct vcpu_vmx *vmx = to_vmx(vcpu);
3004         unsigned long hw_cr0, old_cr0_pg;
3005         u32 tmp;
3006
3007         old_cr0_pg = kvm_read_cr0_bits(vcpu, X86_CR0_PG);
3008
3009         hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
3010         if (is_unrestricted_guest(vcpu))
3011                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3012         else {
3013                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3014                 if (!enable_ept)
3015                         hw_cr0 |= X86_CR0_WP;
3016
3017                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3018                         enter_pmode(vcpu);
3019
3020                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3021                         enter_rmode(vcpu);
3022         }
3023
3024         vmcs_writel(CR0_READ_SHADOW, cr0);
3025         vmcs_writel(GUEST_CR0, hw_cr0);
3026         vcpu->arch.cr0 = cr0;
3027         kvm_register_mark_available(vcpu, VCPU_EXREG_CR0);
3028
3029 #ifdef CONFIG_X86_64
3030         if (vcpu->arch.efer & EFER_LME) {
3031                 if (!old_cr0_pg && (cr0 & X86_CR0_PG))
3032                         enter_lmode(vcpu);
3033                 else if (old_cr0_pg && !(cr0 & X86_CR0_PG))
3034                         exit_lmode(vcpu);
3035         }
3036 #endif
3037
3038         if (enable_ept && !is_unrestricted_guest(vcpu)) {
3039                 /*
3040                  * Ensure KVM has an up-to-date snapshot of the guest's CR3.  If
3041                  * the below code _enables_ CR3 exiting, vmx_cache_reg() will
3042                  * (correctly) stop reading vmcs.GUEST_CR3 because it thinks
3043                  * KVM's CR3 is installed.
3044                  */
3045                 if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3))
3046                         vmx_cache_reg(vcpu, VCPU_EXREG_CR3);
3047
3048                 /*
3049                  * When running with EPT but not unrestricted guest, KVM must
3050                  * intercept CR3 accesses when paging is _disabled_.  This is
3051                  * necessary because restricted guests can't actually run with
3052                  * paging disabled, and so KVM stuffs its own CR3 in order to
3053                  * run the guest when identity mapped page tables.
3054                  *
3055                  * Do _NOT_ check the old CR0.PG, e.g. to optimize away the
3056                  * update, it may be stale with respect to CR3 interception,
3057                  * e.g. after nested VM-Enter.
3058                  *
3059                  * Lastly, honor L1's desires, i.e. intercept CR3 loads and/or
3060                  * stores to forward them to L1, even if KVM does not need to
3061                  * intercept them to preserve its identity mapped page tables.
3062                  */
3063                 if (!(cr0 & X86_CR0_PG)) {
3064                         exec_controls_setbit(vmx, CR3_EXITING_BITS);
3065                 } else if (!is_guest_mode(vcpu)) {
3066                         exec_controls_clearbit(vmx, CR3_EXITING_BITS);
3067                 } else {
3068                         tmp = exec_controls_get(vmx);
3069                         tmp &= ~CR3_EXITING_BITS;
3070                         tmp |= get_vmcs12(vcpu)->cpu_based_vm_exec_control & CR3_EXITING_BITS;
3071                         exec_controls_set(vmx, tmp);
3072                 }
3073
3074                 /* Note, vmx_set_cr4() consumes the new vcpu->arch.cr0. */
3075                 if ((old_cr0_pg ^ cr0) & X86_CR0_PG)
3076                         vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3077         }
3078
3079         /* depends on vcpu->arch.cr0 to be set to a new value */
3080         vmx->emulation_required = emulation_required(vcpu);
3081 }
3082
3083 static int vmx_get_max_tdp_level(void)
3084 {
3085         if (cpu_has_vmx_ept_5levels())
3086                 return 5;
3087         return 4;
3088 }
3089
3090 u64 construct_eptp(struct kvm_vcpu *vcpu, hpa_t root_hpa, int root_level)
3091 {
3092         u64 eptp = VMX_EPTP_MT_WB;
3093
3094         eptp |= (root_level == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
3095
3096         if (enable_ept_ad_bits &&
3097             (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
3098                 eptp |= VMX_EPTP_AD_ENABLE_BIT;
3099         eptp |= root_hpa;
3100
3101         return eptp;
3102 }
3103
3104 static void vmx_load_mmu_pgd(struct kvm_vcpu *vcpu, hpa_t root_hpa,
3105                              int root_level)
3106 {
3107         struct kvm *kvm = vcpu->kvm;
3108         bool update_guest_cr3 = true;
3109         unsigned long guest_cr3;
3110         u64 eptp;
3111
3112         if (enable_ept) {
3113                 eptp = construct_eptp(vcpu, root_hpa, root_level);
3114                 vmcs_write64(EPT_POINTER, eptp);
3115
3116                 hv_track_root_tdp(vcpu, root_hpa);
3117
3118                 if (!enable_unrestricted_guest && !is_paging(vcpu))
3119                         guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
3120                 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3121                         guest_cr3 = vcpu->arch.cr3;
3122                 else /* vmcs01.GUEST_CR3 is already up-to-date. */
3123                         update_guest_cr3 = false;
3124                 vmx_ept_load_pdptrs(vcpu);
3125         } else {
3126                 guest_cr3 = root_hpa | kvm_get_active_pcid(vcpu);
3127         }
3128
3129         if (update_guest_cr3)
3130                 vmcs_writel(GUEST_CR3, guest_cr3);
3131 }
3132
3133 static bool vmx_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3134 {
3135         /*
3136          * We operate under the default treatment of SMM, so VMX cannot be
3137          * enabled under SMM.  Note, whether or not VMXE is allowed at all is
3138          * handled by kvm_is_valid_cr4().
3139          */
3140         if ((cr4 & X86_CR4_VMXE) && is_smm(vcpu))
3141                 return false;
3142
3143         if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
3144                 return false;
3145
3146         return true;
3147 }
3148
3149 void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3150 {
3151         unsigned long old_cr4 = vcpu->arch.cr4;
3152         struct vcpu_vmx *vmx = to_vmx(vcpu);
3153         /*
3154          * Pass through host's Machine Check Enable value to hw_cr4, which
3155          * is in force while we are in guest mode.  Do not let guests control
3156          * this bit, even if host CR4.MCE == 0.
3157          */
3158         unsigned long hw_cr4;
3159
3160         hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
3161         if (is_unrestricted_guest(vcpu))
3162                 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
3163         else if (vmx->rmode.vm86_active)
3164                 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
3165         else
3166                 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
3167
3168         if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
3169                 if (cr4 & X86_CR4_UMIP) {
3170                         secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
3171                         hw_cr4 &= ~X86_CR4_UMIP;
3172                 } else if (!is_guest_mode(vcpu) ||
3173                         !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
3174                         secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
3175                 }
3176         }
3177
3178         vcpu->arch.cr4 = cr4;
3179         kvm_register_mark_available(vcpu, VCPU_EXREG_CR4);
3180
3181         if (!is_unrestricted_guest(vcpu)) {
3182                 if (enable_ept) {
3183                         if (!is_paging(vcpu)) {
3184                                 hw_cr4 &= ~X86_CR4_PAE;
3185                                 hw_cr4 |= X86_CR4_PSE;
3186                         } else if (!(cr4 & X86_CR4_PAE)) {
3187                                 hw_cr4 &= ~X86_CR4_PAE;
3188                         }
3189                 }
3190
3191                 /*
3192                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3193                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
3194                  * to be manually disabled when guest switches to non-paging
3195                  * mode.
3196                  *
3197                  * If !enable_unrestricted_guest, the CPU is always running
3198                  * with CR0.PG=1 and CR4 needs to be modified.
3199                  * If enable_unrestricted_guest, the CPU automatically
3200                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3201                  */
3202                 if (!is_paging(vcpu))
3203                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3204         }
3205
3206         vmcs_writel(CR4_READ_SHADOW, cr4);
3207         vmcs_writel(GUEST_CR4, hw_cr4);
3208
3209         if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
3210                 kvm_update_cpuid_runtime(vcpu);
3211 }
3212
3213 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3214 {
3215         struct vcpu_vmx *vmx = to_vmx(vcpu);
3216         u32 ar;
3217
3218         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3219                 *var = vmx->rmode.segs[seg];
3220                 if (seg == VCPU_SREG_TR
3221                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3222                         return;
3223                 var->base = vmx_read_guest_seg_base(vmx, seg);
3224                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3225                 return;
3226         }
3227         var->base = vmx_read_guest_seg_base(vmx, seg);
3228         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3229         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3230         ar = vmx_read_guest_seg_ar(vmx, seg);
3231         var->unusable = (ar >> 16) & 1;
3232         var->type = ar & 15;
3233         var->s = (ar >> 4) & 1;
3234         var->dpl = (ar >> 5) & 3;
3235         /*
3236          * Some userspaces do not preserve unusable property. Since usable
3237          * segment has to be present according to VMX spec we can use present
3238          * property to amend userspace bug by making unusable segment always
3239          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3240          * segment as unusable.
3241          */
3242         var->present = !var->unusable;
3243         var->avl = (ar >> 12) & 1;
3244         var->l = (ar >> 13) & 1;
3245         var->db = (ar >> 14) & 1;
3246         var->g = (ar >> 15) & 1;
3247 }
3248
3249 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3250 {
3251         struct kvm_segment s;
3252
3253         if (to_vmx(vcpu)->rmode.vm86_active) {
3254                 vmx_get_segment(vcpu, &s, seg);
3255                 return s.base;
3256         }
3257         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3258 }
3259
3260 int vmx_get_cpl(struct kvm_vcpu *vcpu)
3261 {
3262         struct vcpu_vmx *vmx = to_vmx(vcpu);
3263
3264         if (unlikely(vmx->rmode.vm86_active))
3265                 return 0;
3266         else {
3267                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3268                 return VMX_AR_DPL(ar);
3269         }
3270 }
3271
3272 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3273 {
3274         u32 ar;
3275
3276         if (var->unusable || !var->present)
3277                 ar = 1 << 16;
3278         else {
3279                 ar = var->type & 15;
3280                 ar |= (var->s & 1) << 4;
3281                 ar |= (var->dpl & 3) << 5;
3282                 ar |= (var->present & 1) << 7;
3283                 ar |= (var->avl & 1) << 12;
3284                 ar |= (var->l & 1) << 13;
3285                 ar |= (var->db & 1) << 14;
3286                 ar |= (var->g & 1) << 15;
3287         }
3288
3289         return ar;
3290 }
3291
3292 void __vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3293 {
3294         struct vcpu_vmx *vmx = to_vmx(vcpu);
3295         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3296
3297         vmx_segment_cache_clear(vmx);
3298
3299         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3300                 vmx->rmode.segs[seg] = *var;
3301                 if (seg == VCPU_SREG_TR)
3302                         vmcs_write16(sf->selector, var->selector);
3303                 else if (var->s)
3304                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3305                 return;
3306         }
3307
3308         vmcs_writel(sf->base, var->base);
3309         vmcs_write32(sf->limit, var->limit);
3310         vmcs_write16(sf->selector, var->selector);
3311
3312         /*
3313          *   Fix the "Accessed" bit in AR field of segment registers for older
3314          * qemu binaries.
3315          *   IA32 arch specifies that at the time of processor reset the
3316          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3317          * is setting it to 0 in the userland code. This causes invalid guest
3318          * state vmexit when "unrestricted guest" mode is turned on.
3319          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3320          * tree. Newer qemu binaries with that qemu fix would not need this
3321          * kvm hack.
3322          */
3323         if (is_unrestricted_guest(vcpu) && (seg != VCPU_SREG_LDTR))
3324                 var->type |= 0x1; /* Accessed */
3325
3326         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3327 }
3328
3329 static void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3330 {
3331         __vmx_set_segment(vcpu, var, seg);
3332
3333         to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
3334 }
3335
3336 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3337 {
3338         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3339
3340         *db = (ar >> 14) & 1;
3341         *l = (ar >> 13) & 1;
3342 }
3343
3344 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3345 {
3346         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3347         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3348 }
3349
3350 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3351 {
3352         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3353         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3354 }
3355
3356 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3357 {
3358         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3359         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3360 }
3361
3362 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3363 {
3364         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3365         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3366 }
3367
3368 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3369 {
3370         struct kvm_segment var;
3371         u32 ar;
3372
3373         vmx_get_segment(vcpu, &var, seg);
3374         var.dpl = 0x3;
3375         if (seg == VCPU_SREG_CS)
3376                 var.type = 0x3;
3377         ar = vmx_segment_access_rights(&var);
3378
3379         if (var.base != (var.selector << 4))
3380                 return false;
3381         if (var.limit != 0xffff)
3382                 return false;
3383         if (ar != 0xf3)
3384                 return false;
3385
3386         return true;
3387 }
3388
3389 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3390 {
3391         struct kvm_segment cs;
3392         unsigned int cs_rpl;
3393
3394         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3395         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3396
3397         if (cs.unusable)
3398                 return false;
3399         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3400                 return false;
3401         if (!cs.s)
3402                 return false;
3403         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3404                 if (cs.dpl > cs_rpl)
3405                         return false;
3406         } else {
3407                 if (cs.dpl != cs_rpl)
3408                         return false;
3409         }
3410         if (!cs.present)
3411                 return false;
3412
3413         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3414         return true;
3415 }
3416
3417 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3418 {
3419         struct kvm_segment ss;
3420         unsigned int ss_rpl;
3421
3422         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3423         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3424
3425         if (ss.unusable)
3426                 return true;
3427         if (ss.type != 3 && ss.type != 7)
3428                 return false;
3429         if (!ss.s)
3430                 return false;
3431         if (ss.dpl != ss_rpl) /* DPL != RPL */
3432                 return false;
3433         if (!ss.present)
3434                 return false;
3435
3436         return true;
3437 }
3438
3439 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3440 {
3441         struct kvm_segment var;
3442         unsigned int rpl;
3443
3444         vmx_get_segment(vcpu, &var, seg);
3445         rpl = var.selector & SEGMENT_RPL_MASK;
3446
3447         if (var.unusable)
3448                 return true;
3449         if (!var.s)
3450                 return false;
3451         if (!var.present)
3452                 return false;
3453         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
3454                 if (var.dpl < rpl) /* DPL < RPL */
3455                         return false;
3456         }
3457
3458         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3459          * rights flags
3460          */
3461         return true;
3462 }
3463
3464 static bool tr_valid(struct kvm_vcpu *vcpu)
3465 {
3466         struct kvm_segment tr;
3467
3468         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3469
3470         if (tr.unusable)
3471                 return false;
3472         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
3473                 return false;
3474         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3475                 return false;
3476         if (!tr.present)
3477                 return false;
3478
3479         return true;
3480 }
3481
3482 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3483 {
3484         struct kvm_segment ldtr;
3485
3486         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3487
3488         if (ldtr.unusable)
3489                 return true;
3490         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
3491                 return false;
3492         if (ldtr.type != 2)
3493                 return false;
3494         if (!ldtr.present)
3495                 return false;
3496
3497         return true;
3498 }
3499
3500 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3501 {
3502         struct kvm_segment cs, ss;
3503
3504         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3505         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3506
3507         return ((cs.selector & SEGMENT_RPL_MASK) ==
3508                  (ss.selector & SEGMENT_RPL_MASK));
3509 }
3510
3511 /*
3512  * Check if guest state is valid. Returns true if valid, false if
3513  * not.
3514  * We assume that registers are always usable
3515  */
3516 bool __vmx_guest_state_valid(struct kvm_vcpu *vcpu)
3517 {
3518         /* real mode guest state checks */
3519         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3520                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3521                         return false;
3522                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3523                         return false;
3524                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3525                         return false;
3526                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3527                         return false;
3528                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3529                         return false;
3530                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3531                         return false;
3532         } else {
3533         /* protected mode guest state checks */
3534                 if (!cs_ss_rpl_check(vcpu))
3535                         return false;
3536                 if (!code_segment_valid(vcpu))
3537                         return false;
3538                 if (!stack_segment_valid(vcpu))
3539                         return false;
3540                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3541                         return false;
3542                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3543                         return false;
3544                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3545                         return false;
3546                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3547                         return false;
3548                 if (!tr_valid(vcpu))
3549                         return false;
3550                 if (!ldtr_valid(vcpu))
3551                         return false;
3552         }
3553         /* TODO:
3554          * - Add checks on RIP
3555          * - Add checks on RFLAGS
3556          */
3557
3558         return true;
3559 }
3560
3561 static int init_rmode_tss(struct kvm *kvm, void __user *ua)
3562 {
3563         const void *zero_page = (const void *) __va(page_to_phys(ZERO_PAGE(0)));
3564         u16 data;
3565         int i;
3566
3567         for (i = 0; i < 3; i++) {
3568                 if (__copy_to_user(ua + PAGE_SIZE * i, zero_page, PAGE_SIZE))
3569                         return -EFAULT;
3570         }
3571
3572         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3573         if (__copy_to_user(ua + TSS_IOPB_BASE_OFFSET, &data, sizeof(u16)))
3574                 return -EFAULT;
3575
3576         data = ~0;
3577         if (__copy_to_user(ua + RMODE_TSS_SIZE - 1, &data, sizeof(u8)))
3578                 return -EFAULT;
3579
3580         return 0;
3581 }
3582
3583 static int init_rmode_identity_map(struct kvm *kvm)
3584 {
3585         struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
3586         int i, r = 0;
3587         void __user *uaddr;
3588         u32 tmp;
3589
3590         /* Protect kvm_vmx->ept_identity_pagetable_done. */
3591         mutex_lock(&kvm->slots_lock);
3592
3593         if (likely(kvm_vmx->ept_identity_pagetable_done))
3594                 goto out;
3595
3596         if (!kvm_vmx->ept_identity_map_addr)
3597                 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3598
3599         uaddr = __x86_set_memory_region(kvm,
3600                                         IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
3601                                         kvm_vmx->ept_identity_map_addr,
3602                                         PAGE_SIZE);
3603         if (IS_ERR(uaddr)) {
3604                 r = PTR_ERR(uaddr);
3605                 goto out;
3606         }
3607
3608         /* Set up identity-mapping pagetable for EPT in real mode */
3609         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3610                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3611                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3612                 if (__copy_to_user(uaddr + i * sizeof(tmp), &tmp, sizeof(tmp))) {
3613                         r = -EFAULT;
3614                         goto out;
3615                 }
3616         }
3617         kvm_vmx->ept_identity_pagetable_done = true;
3618
3619 out:
3620         mutex_unlock(&kvm->slots_lock);
3621         return r;
3622 }
3623
3624 static void seg_setup(int seg)
3625 {
3626         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3627         unsigned int ar;
3628
3629         vmcs_write16(sf->selector, 0);
3630         vmcs_writel(sf->base, 0);
3631         vmcs_write32(sf->limit, 0xffff);
3632         ar = 0x93;
3633         if (seg == VCPU_SREG_CS)
3634                 ar |= 0x08; /* code segment */
3635
3636         vmcs_write32(sf->ar_bytes, ar);
3637 }
3638
3639 static int alloc_apic_access_page(struct kvm *kvm)
3640 {
3641         struct page *page;
3642         void __user *hva;
3643         int ret = 0;
3644
3645         mutex_lock(&kvm->slots_lock);
3646         if (kvm->arch.apic_access_memslot_enabled)
3647                 goto out;
3648         hva = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3649                                       APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
3650         if (IS_ERR(hva)) {
3651                 ret = PTR_ERR(hva);
3652                 goto out;
3653         }
3654
3655         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
3656         if (is_error_page(page)) {
3657                 ret = -EFAULT;
3658                 goto out;
3659         }
3660
3661         /*
3662          * Do not pin the page in memory, so that memory hot-unplug
3663          * is able to migrate it.
3664          */
3665         put_page(page);
3666         kvm->arch.apic_access_memslot_enabled = true;
3667 out:
3668         mutex_unlock(&kvm->slots_lock);
3669         return ret;
3670 }
3671
3672 int allocate_vpid(void)
3673 {
3674         int vpid;
3675
3676         if (!enable_vpid)
3677                 return 0;
3678         spin_lock(&vmx_vpid_lock);
3679         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3680         if (vpid < VMX_NR_VPIDS)
3681                 __set_bit(vpid, vmx_vpid_bitmap);
3682         else
3683                 vpid = 0;
3684         spin_unlock(&vmx_vpid_lock);
3685         return vpid;
3686 }
3687
3688 void free_vpid(int vpid)
3689 {
3690         if (!enable_vpid || vpid == 0)
3691                 return;
3692         spin_lock(&vmx_vpid_lock);
3693         __clear_bit(vpid, vmx_vpid_bitmap);
3694         spin_unlock(&vmx_vpid_lock);
3695 }
3696
3697 static void vmx_clear_msr_bitmap_read(ulong *msr_bitmap, u32 msr)
3698 {
3699         int f = sizeof(unsigned long);
3700
3701         if (msr <= 0x1fff)
3702                 __clear_bit(msr, msr_bitmap + 0x000 / f);
3703         else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
3704                 __clear_bit(msr & 0x1fff, msr_bitmap + 0x400 / f);
3705 }
3706
3707 static void vmx_clear_msr_bitmap_write(ulong *msr_bitmap, u32 msr)
3708 {
3709         int f = sizeof(unsigned long);
3710
3711         if (msr <= 0x1fff)
3712                 __clear_bit(msr, msr_bitmap + 0x800 / f);
3713         else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
3714                 __clear_bit(msr & 0x1fff, msr_bitmap + 0xc00 / f);
3715 }
3716
3717 static void vmx_set_msr_bitmap_read(ulong *msr_bitmap, u32 msr)
3718 {
3719         int f = sizeof(unsigned long);
3720
3721         if (msr <= 0x1fff)
3722                 __set_bit(msr, msr_bitmap + 0x000 / f);
3723         else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
3724                 __set_bit(msr & 0x1fff, msr_bitmap + 0x400 / f);
3725 }
3726
3727 static void vmx_set_msr_bitmap_write(ulong *msr_bitmap, u32 msr)
3728 {
3729         int f = sizeof(unsigned long);
3730
3731         if (msr <= 0x1fff)
3732                 __set_bit(msr, msr_bitmap + 0x800 / f);
3733         else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
3734                 __set_bit(msr & 0x1fff, msr_bitmap + 0xc00 / f);
3735 }
3736
3737 void vmx_disable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type)
3738 {
3739         struct vcpu_vmx *vmx = to_vmx(vcpu);
3740         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3741
3742         if (!cpu_has_vmx_msr_bitmap())
3743                 return;
3744
3745         if (static_branch_unlikely(&enable_evmcs))
3746                 evmcs_touch_msr_bitmap();
3747
3748         /*
3749          * Mark the desired intercept state in shadow bitmap, this is needed
3750          * for resync when the MSR filters change.
3751         */
3752         if (is_valid_passthrough_msr(msr)) {
3753                 int idx = possible_passthrough_msr_slot(msr);
3754
3755                 if (idx != -ENOENT) {
3756                         if (type & MSR_TYPE_R)
3757                                 clear_bit(idx, vmx->shadow_msr_intercept.read);
3758                         if (type & MSR_TYPE_W)
3759                                 clear_bit(idx, vmx->shadow_msr_intercept.write);
3760                 }
3761         }
3762
3763         if ((type & MSR_TYPE_R) &&
3764             !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ)) {
3765                 vmx_set_msr_bitmap_read(msr_bitmap, msr);
3766                 type &= ~MSR_TYPE_R;
3767         }
3768
3769         if ((type & MSR_TYPE_W) &&
3770             !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE)) {
3771                 vmx_set_msr_bitmap_write(msr_bitmap, msr);
3772                 type &= ~MSR_TYPE_W;
3773         }
3774
3775         if (type & MSR_TYPE_R)
3776                 vmx_clear_msr_bitmap_read(msr_bitmap, msr);
3777
3778         if (type & MSR_TYPE_W)
3779                 vmx_clear_msr_bitmap_write(msr_bitmap, msr);
3780 }
3781
3782 void vmx_enable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type)
3783 {
3784         struct vcpu_vmx *vmx = to_vmx(vcpu);
3785         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3786
3787         if (!cpu_has_vmx_msr_bitmap())
3788                 return;
3789
3790         if (static_branch_unlikely(&enable_evmcs))
3791                 evmcs_touch_msr_bitmap();
3792
3793         /*
3794          * Mark the desired intercept state in shadow bitmap, this is needed
3795          * for resync when the MSR filter changes.
3796         */
3797         if (is_valid_passthrough_msr(msr)) {
3798                 int idx = possible_passthrough_msr_slot(msr);
3799
3800                 if (idx != -ENOENT) {
3801                         if (type & MSR_TYPE_R)
3802                                 set_bit(idx, vmx->shadow_msr_intercept.read);
3803                         if (type & MSR_TYPE_W)
3804                                 set_bit(idx, vmx->shadow_msr_intercept.write);
3805                 }
3806         }
3807
3808         if (type & MSR_TYPE_R)
3809                 vmx_set_msr_bitmap_read(msr_bitmap, msr);
3810
3811         if (type & MSR_TYPE_W)
3812                 vmx_set_msr_bitmap_write(msr_bitmap, msr);
3813 }
3814
3815 static void vmx_reset_x2apic_msrs(struct kvm_vcpu *vcpu, u8 mode)
3816 {
3817         unsigned long *msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap;
3818         unsigned long read_intercept;
3819         int msr;
3820
3821         read_intercept = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3822
3823         for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3824                 unsigned int read_idx = msr / BITS_PER_LONG;
3825                 unsigned int write_idx = read_idx + (0x800 / sizeof(long));
3826
3827                 msr_bitmap[read_idx] = read_intercept;
3828                 msr_bitmap[write_idx] = ~0ul;
3829         }
3830 }
3831
3832 static void vmx_update_msr_bitmap_x2apic(struct kvm_vcpu *vcpu)
3833 {
3834         struct vcpu_vmx *vmx = to_vmx(vcpu);
3835         u8 mode;
3836
3837         if (!cpu_has_vmx_msr_bitmap())
3838                 return;
3839
3840         if (cpu_has_secondary_exec_ctrls() &&
3841             (secondary_exec_controls_get(vmx) &
3842              SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3843                 mode = MSR_BITMAP_MODE_X2APIC;
3844                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3845                         mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3846         } else {
3847                 mode = 0;
3848         }
3849
3850         if (mode == vmx->x2apic_msr_bitmap_mode)
3851                 return;
3852
3853         vmx->x2apic_msr_bitmap_mode = mode;
3854
3855         vmx_reset_x2apic_msrs(vcpu, mode);
3856
3857         /*
3858          * TPR reads and writes can be virtualized even if virtual interrupt
3859          * delivery is not in use.
3860          */
3861         vmx_set_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW,
3862                                   !(mode & MSR_BITMAP_MODE_X2APIC));
3863
3864         if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3865                 vmx_enable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_RW);
3866                 vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3867                 vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3868         }
3869 }
3870
3871 void pt_update_intercept_for_msr(struct kvm_vcpu *vcpu)
3872 {
3873         struct vcpu_vmx *vmx = to_vmx(vcpu);
3874         bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3875         u32 i;
3876
3877         vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_STATUS, MSR_TYPE_RW, flag);
3878         vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_BASE, MSR_TYPE_RW, flag);
3879         vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_MASK, MSR_TYPE_RW, flag);
3880         vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_CR3_MATCH, MSR_TYPE_RW, flag);
3881         for (i = 0; i < vmx->pt_desc.addr_range; i++) {
3882                 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3883                 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3884         }
3885 }
3886
3887 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3888 {
3889         struct vcpu_vmx *vmx = to_vmx(vcpu);
3890         void *vapic_page;
3891         u32 vppr;
3892         int rvi;
3893
3894         if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3895                 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
3896                 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
3897                 return false;
3898
3899         rvi = vmx_get_rvi();
3900
3901         vapic_page = vmx->nested.virtual_apic_map.hva;
3902         vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
3903
3904         return ((rvi & 0xf0) > (vppr & 0xf0));
3905 }
3906
3907 static void vmx_msr_filter_changed(struct kvm_vcpu *vcpu)
3908 {
3909         struct vcpu_vmx *vmx = to_vmx(vcpu);
3910         u32 i;
3911
3912         /*
3913          * Set intercept permissions for all potentially passed through MSRs
3914          * again. They will automatically get filtered through the MSR filter,
3915          * so we are back in sync after this.
3916          */
3917         for (i = 0; i < ARRAY_SIZE(vmx_possible_passthrough_msrs); i++) {
3918                 u32 msr = vmx_possible_passthrough_msrs[i];
3919                 bool read = test_bit(i, vmx->shadow_msr_intercept.read);
3920                 bool write = test_bit(i, vmx->shadow_msr_intercept.write);
3921
3922                 vmx_set_intercept_for_msr(vcpu, msr, MSR_TYPE_R, read);
3923                 vmx_set_intercept_for_msr(vcpu, msr, MSR_TYPE_W, write);
3924         }
3925
3926         pt_update_intercept_for_msr(vcpu);
3927 }
3928
3929 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3930                                                      bool nested)
3931 {
3932 #ifdef CONFIG_SMP
3933         int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3934
3935         if (vcpu->mode == IN_GUEST_MODE) {
3936                 /*
3937                  * The vector of interrupt to be delivered to vcpu had
3938                  * been set in PIR before this function.
3939                  *
3940                  * Following cases will be reached in this block, and
3941                  * we always send a notification event in all cases as
3942                  * explained below.
3943                  *
3944                  * Case 1: vcpu keeps in non-root mode. Sending a
3945                  * notification event posts the interrupt to vcpu.
3946                  *
3947                  * Case 2: vcpu exits to root mode and is still
3948                  * runnable. PIR will be synced to vIRR before the
3949                  * next vcpu entry. Sending a notification event in
3950                  * this case has no effect, as vcpu is not in root
3951                  * mode.
3952                  *
3953                  * Case 3: vcpu exits to root mode and is blocked.
3954                  * vcpu_block() has already synced PIR to vIRR and
3955                  * never blocks vcpu if vIRR is not cleared. Therefore,
3956                  * a blocked vcpu here does not wait for any requested
3957                  * interrupts in PIR, and sending a notification event
3958                  * which has no effect is safe here.
3959                  */
3960
3961                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
3962                 return true;
3963         }
3964 #endif
3965         return false;
3966 }
3967
3968 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3969                                                 int vector)
3970 {
3971         struct vcpu_vmx *vmx = to_vmx(vcpu);
3972
3973         if (is_guest_mode(vcpu) &&
3974             vector == vmx->nested.posted_intr_nv) {
3975                 /*
3976                  * If a posted intr is not recognized by hardware,
3977                  * we will accomplish it in the next vmentry.
3978                  */
3979                 vmx->nested.pi_pending = true;
3980                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3981                 /* the PIR and ON have been set by L1. */
3982                 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3983                         kvm_vcpu_kick(vcpu);
3984                 return 0;
3985         }
3986         return -1;
3987 }
3988 /*
3989  * Send interrupt to vcpu via posted interrupt way.
3990  * 1. If target vcpu is running(non-root mode), send posted interrupt
3991  * notification to vcpu and hardware will sync PIR to vIRR atomically.
3992  * 2. If target vcpu isn't running(root mode), kick it to pick up the
3993  * interrupt from PIR in next vmentry.
3994  */
3995 static int vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3996 {
3997         struct vcpu_vmx *vmx = to_vmx(vcpu);
3998         int r;
3999
4000         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4001         if (!r)
4002                 return 0;
4003
4004         if (!vcpu->arch.apicv_active)
4005                 return -1;
4006
4007         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4008                 return 0;
4009
4010         /* If a previous notification has sent the IPI, nothing to do.  */
4011         if (pi_test_and_set_on(&vmx->pi_desc))
4012                 return 0;
4013
4014         if (vcpu != kvm_get_running_vcpu() &&
4015             !kvm_vcpu_trigger_posted_interrupt(vcpu, false))
4016                 kvm_vcpu_kick(vcpu);
4017
4018         return 0;
4019 }
4020
4021 /*
4022  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4023  * will not change in the lifetime of the guest.
4024  * Note that host-state that does change is set elsewhere. E.g., host-state
4025  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4026  */
4027 void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4028 {
4029         u32 low32, high32;
4030         unsigned long tmpl;
4031         unsigned long cr0, cr3, cr4;
4032
4033         cr0 = read_cr0();
4034         WARN_ON(cr0 & X86_CR0_TS);
4035         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
4036
4037         /*
4038          * Save the most likely value for this task's CR3 in the VMCS.
4039          * We can't use __get_current_cr3_fast() because we're not atomic.
4040          */
4041         cr3 = __read_cr3();
4042         vmcs_writel(HOST_CR3, cr3);             /* 22.2.3  FIXME: shadow tables */
4043         vmx->loaded_vmcs->host_state.cr3 = cr3;
4044
4045         /* Save the most likely value for this task's CR4 in the VMCS. */
4046         cr4 = cr4_read_shadow();
4047         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4048         vmx->loaded_vmcs->host_state.cr4 = cr4;
4049
4050         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4051 #ifdef CONFIG_X86_64
4052         /*
4053          * Load null selectors, so we can avoid reloading them in
4054          * vmx_prepare_switch_to_host(), in case userspace uses
4055          * the null selectors too (the expected case).
4056          */
4057         vmcs_write16(HOST_DS_SELECTOR, 0);
4058         vmcs_write16(HOST_ES_SELECTOR, 0);
4059 #else
4060         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4061         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4062 #endif
4063         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4064         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4065
4066         vmcs_writel(HOST_IDTR_BASE, host_idt_base);   /* 22.2.4 */
4067
4068         vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
4069
4070         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4071         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4072         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4073         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4074
4075         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4076                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4077                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4078         }
4079
4080         if (cpu_has_load_ia32_efer())
4081                 vmcs_write64(HOST_IA32_EFER, host_efer);
4082 }
4083
4084 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4085 {
4086         struct kvm_vcpu *vcpu = &vmx->vcpu;
4087
4088         vcpu->arch.cr4_guest_owned_bits = KVM_POSSIBLE_CR4_GUEST_BITS &
4089                                           ~vcpu->arch.cr4_guest_rsvd_bits;
4090         if (!enable_ept)
4091                 vcpu->arch.cr4_guest_owned_bits &= ~X86_CR4_PGE;
4092         if (is_guest_mode(&vmx->vcpu))
4093                 vcpu->arch.cr4_guest_owned_bits &=
4094                         ~get_vmcs12(vcpu)->cr4_guest_host_mask;
4095         vmcs_writel(CR4_GUEST_HOST_MASK, ~vcpu->arch.cr4_guest_owned_bits);
4096 }
4097
4098 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4099 {
4100         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4101
4102         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4103                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4104
4105         if (!enable_vnmi)
4106                 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
4107
4108         if (!enable_preemption_timer)
4109                 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4110
4111         return pin_based_exec_ctrl;
4112 }
4113
4114 static u32 vmx_vmentry_ctrl(void)
4115 {
4116         u32 vmentry_ctrl = vmcs_config.vmentry_ctrl;
4117
4118         if (vmx_pt_mode_is_system())
4119                 vmentry_ctrl &= ~(VM_ENTRY_PT_CONCEAL_PIP |
4120                                   VM_ENTRY_LOAD_IA32_RTIT_CTL);
4121         /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
4122         return vmentry_ctrl &
4123                 ~(VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VM_ENTRY_LOAD_IA32_EFER);
4124 }
4125
4126 static u32 vmx_vmexit_ctrl(void)
4127 {
4128         u32 vmexit_ctrl = vmcs_config.vmexit_ctrl;
4129
4130         if (vmx_pt_mode_is_system())
4131                 vmexit_ctrl &= ~(VM_EXIT_PT_CONCEAL_PIP |
4132                                  VM_EXIT_CLEAR_IA32_RTIT_CTL);
4133         /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
4134         return vmexit_ctrl &
4135                 ~(VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | VM_EXIT_LOAD_IA32_EFER);
4136 }
4137
4138 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4139 {
4140         struct vcpu_vmx *vmx = to_vmx(vcpu);
4141
4142         pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4143         if (cpu_has_secondary_exec_ctrls()) {
4144                 if (kvm_vcpu_apicv_active(vcpu))
4145                         secondary_exec_controls_setbit(vmx,
4146                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
4147                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4148                 else
4149                         secondary_exec_controls_clearbit(vmx,
4150                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
4151                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4152         }
4153
4154         vmx_update_msr_bitmap_x2apic(vcpu);
4155 }
4156
4157 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4158 {
4159         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4160
4161         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4162                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4163
4164         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4165                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4166 #ifdef CONFIG_X86_64
4167                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4168                                 CPU_BASED_CR8_LOAD_EXITING;
4169 #endif
4170         }
4171         if (!enable_ept)
4172                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4173                                 CPU_BASED_CR3_LOAD_EXITING  |
4174                                 CPU_BASED_INVLPG_EXITING;
4175         if (kvm_mwait_in_guest(vmx->vcpu.kvm))
4176                 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
4177                                 CPU_BASED_MONITOR_EXITING);
4178         if (kvm_hlt_in_guest(vmx->vcpu.kvm))
4179                 exec_control &= ~CPU_BASED_HLT_EXITING;
4180         return exec_control;
4181 }
4182
4183 /*
4184  * Adjust a single secondary execution control bit to intercept/allow an
4185  * instruction in the guest.  This is usually done based on whether or not a
4186  * feature has been exposed to the guest in order to correctly emulate faults.
4187  */
4188 static inline void
4189 vmx_adjust_secondary_exec_control(struct vcpu_vmx *vmx, u32 *exec_control,
4190                                   u32 control, bool enabled, bool exiting)
4191 {
4192         /*
4193          * If the control is for an opt-in feature, clear the control if the
4194          * feature is not exposed to the guest, i.e. not enabled.  If the
4195          * control is opt-out, i.e. an exiting control, clear the control if
4196          * the feature _is_ exposed to the guest, i.e. exiting/interception is
4197          * disabled for the associated instruction.  Note, the caller is
4198          * responsible presetting exec_control to set all supported bits.
4199          */
4200         if (enabled == exiting)
4201                 *exec_control &= ~control;
4202
4203         /*
4204          * Update the nested MSR settings so that a nested VMM can/can't set
4205          * controls for features that are/aren't exposed to the guest.
4206          */
4207         if (nested) {
4208                 if (enabled)
4209                         vmx->nested.msrs.secondary_ctls_high |= control;
4210                 else
4211                         vmx->nested.msrs.secondary_ctls_high &= ~control;
4212         }
4213 }
4214
4215 /*
4216  * Wrapper macro for the common case of adjusting a secondary execution control
4217  * based on a single guest CPUID bit, with a dedicated feature bit.  This also
4218  * verifies that the control is actually supported by KVM and hardware.
4219  */
4220 #define vmx_adjust_sec_exec_control(vmx, exec_control, name, feat_name, ctrl_name, exiting) \
4221 ({                                                                       \
4222         bool __enabled;                                                  \
4223                                                                          \
4224         if (cpu_has_vmx_##name()) {                                      \
4225                 __enabled = guest_cpuid_has(&(vmx)->vcpu,                \
4226                                             X86_FEATURE_##feat_name);    \
4227                 vmx_adjust_secondary_exec_control(vmx, exec_control,     \
4228                         SECONDARY_EXEC_##ctrl_name, __enabled, exiting); \
4229         }                                                                \
4230 })
4231
4232 /* More macro magic for ENABLE_/opt-in versus _EXITING/opt-out controls. */
4233 #define vmx_adjust_sec_exec_feature(vmx, exec_control, lname, uname) \
4234         vmx_adjust_sec_exec_control(vmx, exec_control, lname, uname, ENABLE_##uname, false)
4235
4236 #define vmx_adjust_sec_exec_exiting(vmx, exec_control, lname, uname) \
4237         vmx_adjust_sec_exec_control(vmx, exec_control, lname, uname, uname##_EXITING, true)
4238
4239 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4240 {
4241         struct kvm_vcpu *vcpu = &vmx->vcpu;
4242
4243         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4244
4245         if (vmx_pt_mode_is_system())
4246                 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
4247         if (!cpu_need_virtualize_apic_accesses(vcpu))
4248                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4249         if (vmx->vpid == 0)
4250                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4251         if (!enable_ept) {
4252                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4253                 enable_unrestricted_guest = 0;
4254         }
4255         if (!enable_unrestricted_guest)
4256                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4257         if (kvm_pause_in_guest(vmx->vcpu.kvm))
4258                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4259         if (!kvm_vcpu_apicv_active(vcpu))
4260                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4261                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4262         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4263
4264         /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
4265          * in vmx_set_cr4.  */
4266         exec_control &= ~SECONDARY_EXEC_DESC;
4267
4268         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4269            (handle_vmptrld).
4270            We can NOT enable shadow_vmcs here because we don't have yet
4271            a current VMCS12
4272         */
4273         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4274
4275         /*
4276          * PML is enabled/disabled when dirty logging of memsmlots changes, but
4277          * it needs to be set here when dirty logging is already active, e.g.
4278          * if this vCPU was created after dirty logging was enabled.
4279          */
4280         if (!vcpu->kvm->arch.cpu_dirty_logging_count)
4281                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4282
4283         if (cpu_has_vmx_xsaves()) {
4284                 /* Exposing XSAVES only when XSAVE is exposed */
4285                 bool xsaves_enabled =
4286                         boot_cpu_has(X86_FEATURE_XSAVE) &&
4287                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4288                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
4289
4290                 vcpu->arch.xsaves_enabled = xsaves_enabled;
4291
4292                 vmx_adjust_secondary_exec_control(vmx, &exec_control,
4293                                                   SECONDARY_EXEC_XSAVES,
4294                                                   xsaves_enabled, false);
4295         }
4296
4297         /*
4298          * RDPID is also gated by ENABLE_RDTSCP, turn on the control if either
4299          * feature is exposed to the guest.  This creates a virtualization hole
4300          * if both are supported in hardware but only one is exposed to the
4301          * guest, but letting the guest execute RDTSCP or RDPID when either one
4302          * is advertised is preferable to emulating the advertised instruction
4303          * in KVM on #UD, and obviously better than incorrectly injecting #UD.
4304          */
4305         if (cpu_has_vmx_rdtscp()) {
4306                 bool rdpid_or_rdtscp_enabled =
4307                         guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) ||
4308                         guest_cpuid_has(vcpu, X86_FEATURE_RDPID);
4309
4310                 vmx_adjust_secondary_exec_control(vmx, &exec_control,
4311                                                   SECONDARY_EXEC_ENABLE_RDTSCP,
4312                                                   rdpid_or_rdtscp_enabled, false);
4313         }
4314         vmx_adjust_sec_exec_feature(vmx, &exec_control, invpcid, INVPCID);
4315
4316         vmx_adjust_sec_exec_exiting(vmx, &exec_control, rdrand, RDRAND);
4317         vmx_adjust_sec_exec_exiting(vmx, &exec_control, rdseed, RDSEED);
4318
4319         vmx_adjust_sec_exec_control(vmx, &exec_control, waitpkg, WAITPKG,
4320                                     ENABLE_USR_WAIT_PAUSE, false);
4321
4322         if (!vcpu->kvm->arch.bus_lock_detection_enabled)
4323                 exec_control &= ~SECONDARY_EXEC_BUS_LOCK_DETECTION;
4324
4325         return exec_control;
4326 }
4327
4328 #define VMX_XSS_EXIT_BITMAP 0
4329
4330 /*
4331  * Noting that the initialization of Guest-state Area of VMCS is in
4332  * vmx_vcpu_reset().
4333  */
4334 static void init_vmcs(struct vcpu_vmx *vmx)
4335 {
4336         if (nested)
4337                 nested_vmx_set_vmcs_shadowing_bitmap();
4338
4339         if (cpu_has_vmx_msr_bitmap())
4340                 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
4341
4342         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4343
4344         /* Control */
4345         pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4346
4347         exec_controls_set(vmx, vmx_exec_control(vmx));
4348
4349         if (cpu_has_secondary_exec_ctrls())
4350                 secondary_exec_controls_set(vmx, vmx_secondary_exec_control(vmx));
4351
4352         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4353                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4354                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4355                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4356                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4357
4358                 vmcs_write16(GUEST_INTR_STATUS, 0);
4359
4360                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4361                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4362         }
4363
4364         if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4365                 vmcs_write32(PLE_GAP, ple_gap);
4366                 vmx->ple_window = ple_window;
4367                 vmx->ple_window_dirty = true;
4368         }
4369
4370         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4371         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4372         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4373
4374         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4375         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4376         vmx_set_constant_host_state(vmx);
4377         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4378         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4379
4380         if (cpu_has_vmx_vmfunc())
4381                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4382
4383         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4384         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4385         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
4386         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4387         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
4388
4389         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4390                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4391
4392         vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
4393
4394         /* 22.2.1, 20.8.1 */
4395         vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
4396
4397         vmx->vcpu.arch.cr0_guest_owned_bits = KVM_POSSIBLE_CR0_GUEST_BITS;
4398         vmcs_writel(CR0_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr0_guest_owned_bits);
4399
4400         set_cr4_guest_host_mask(vmx);
4401
4402         if (vmx->vpid != 0)
4403                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4404
4405         if (cpu_has_vmx_xsaves())
4406                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4407
4408         if (enable_pml) {
4409                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4410                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4411         }
4412
4413         vmx_write_encls_bitmap(&vmx->vcpu, NULL);
4414
4415         if (vmx_pt_mode_is_host_guest()) {
4416                 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4417                 /* Bit[6~0] are forced to 1, writes are ignored. */
4418                 vmx->pt_desc.guest.output_mask = 0x7F;
4419                 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4420         }
4421
4422         vmcs_write32(GUEST_SYSENTER_CS, 0);
4423         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4424         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4425         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4426
4427         if (cpu_has_vmx_tpr_shadow()) {
4428                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4429                 if (cpu_need_tpr_shadow(&vmx->vcpu))
4430                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4431                                      __pa(vmx->vcpu.arch.apic->regs));
4432                 vmcs_write32(TPR_THRESHOLD, 0);
4433         }
4434
4435         vmx_setup_uret_msrs(vmx);
4436 }
4437
4438 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4439 {
4440         struct vcpu_vmx *vmx = to_vmx(vcpu);
4441
4442         vmx->rmode.vm86_active = 0;
4443         vmx->spec_ctrl = 0;
4444
4445         vmx->msr_ia32_umwait_control = 0;
4446
4447         vmx->hv_deadline_tsc = -1;
4448         kvm_set_cr8(vcpu, 0);
4449
4450         vmx_segment_cache_clear(vmx);
4451
4452         seg_setup(VCPU_SREG_CS);
4453         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4454         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4455
4456         seg_setup(VCPU_SREG_DS);
4457         seg_setup(VCPU_SREG_ES);
4458         seg_setup(VCPU_SREG_FS);
4459         seg_setup(VCPU_SREG_GS);
4460         seg_setup(VCPU_SREG_SS);
4461
4462         vmcs_write16(GUEST_TR_SELECTOR, 0);
4463         vmcs_writel(GUEST_TR_BASE, 0);
4464         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4465         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4466
4467         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4468         vmcs_writel(GUEST_LDTR_BASE, 0);
4469         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4470         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4471
4472         vmcs_writel(GUEST_GDTR_BASE, 0);
4473         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4474
4475         vmcs_writel(GUEST_IDTR_BASE, 0);
4476         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4477
4478         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4479         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4480         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4481         if (kvm_mpx_supported())
4482                 vmcs_write64(GUEST_BNDCFGS, 0);
4483
4484         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4485
4486         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4487
4488         vpid_sync_context(vmx->vpid);
4489 }
4490
4491 static void vmx_enable_irq_window(struct kvm_vcpu *vcpu)
4492 {
4493         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
4494 }
4495
4496 static void vmx_enable_nmi_window(struct kvm_vcpu *vcpu)
4497 {
4498         if (!enable_vnmi ||
4499             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4500                 vmx_enable_irq_window(vcpu);
4501                 return;
4502         }
4503
4504         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
4505 }
4506
4507 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4508 {
4509         struct vcpu_vmx *vmx = to_vmx(vcpu);
4510         uint32_t intr;
4511         int irq = vcpu->arch.interrupt.nr;
4512
4513         trace_kvm_inj_virq(irq);
4514
4515         ++vcpu->stat.irq_injections;
4516         if (vmx->rmode.vm86_active) {
4517                 int inc_eip = 0;
4518                 if (vcpu->arch.interrupt.soft)
4519                         inc_eip = vcpu->arch.event_exit_inst_len;
4520                 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
4521                 return;
4522         }
4523         intr = irq | INTR_INFO_VALID_MASK;
4524         if (vcpu->arch.interrupt.soft) {
4525                 intr |= INTR_TYPE_SOFT_INTR;
4526                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4527                              vmx->vcpu.arch.event_exit_inst_len);
4528         } else
4529                 intr |= INTR_TYPE_EXT_INTR;
4530         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4531
4532         vmx_clear_hlt(vcpu);
4533 }
4534
4535 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4536 {
4537         struct vcpu_vmx *vmx = to_vmx(vcpu);
4538
4539         if (!enable_vnmi) {
4540                 /*
4541                  * Tracking the NMI-blocked state in software is built upon
4542                  * finding the next open IRQ window. This, in turn, depends on
4543                  * well-behaving guests: They have to keep IRQs disabled at
4544                  * least as long as the NMI handler runs. Otherwise we may
4545                  * cause NMI nesting, maybe breaking the guest. But as this is
4546                  * highly unlikely, we can live with the residual risk.
4547                  */
4548                 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4549                 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4550         }
4551
4552         ++vcpu->stat.nmi_injections;
4553         vmx->loaded_vmcs->nmi_known_unmasked = false;
4554
4555         if (vmx->rmode.vm86_active) {
4556                 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
4557                 return;
4558         }
4559
4560         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4561                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4562
4563         vmx_clear_hlt(vcpu);
4564 }
4565
4566 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4567 {
4568         struct vcpu_vmx *vmx = to_vmx(vcpu);
4569         bool masked;
4570
4571         if (!enable_vnmi)
4572                 return vmx->loaded_vmcs->soft_vnmi_blocked;
4573         if (vmx->loaded_vmcs->nmi_known_unmasked)
4574                 return false;
4575         masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4576         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4577         return masked;
4578 }
4579
4580 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4581 {
4582         struct vcpu_vmx *vmx = to_vmx(vcpu);
4583
4584         if (!enable_vnmi) {
4585                 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4586                         vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4587                         vmx->loaded_vmcs->vnmi_blocked_time = 0;
4588                 }
4589         } else {
4590                 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4591                 if (masked)
4592                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4593                                       GUEST_INTR_STATE_NMI);
4594                 else
4595                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4596                                         GUEST_INTR_STATE_NMI);
4597         }
4598 }
4599
4600 bool vmx_nmi_blocked(struct kvm_vcpu *vcpu)
4601 {
4602         if (is_guest_mode(vcpu) && nested_exit_on_nmi(vcpu))
4603                 return false;
4604
4605         if (!enable_vnmi && to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4606                 return true;
4607
4608         return (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4609                 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI |
4610                  GUEST_INTR_STATE_NMI));
4611 }
4612
4613 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4614 {
4615         if (to_vmx(vcpu)->nested.nested_run_pending)
4616                 return -EBUSY;
4617
4618         /* An NMI must not be injected into L2 if it's supposed to VM-Exit.  */
4619         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(vcpu))
4620                 return -EBUSY;
4621
4622         return !vmx_nmi_blocked(vcpu);
4623 }
4624
4625 bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu)
4626 {
4627         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4628                 return false;
4629
4630         return !(vmx_get_rflags(vcpu) & X86_EFLAGS_IF) ||
4631                (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4632                 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4633 }
4634
4635 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4636 {
4637         if (to_vmx(vcpu)->nested.nested_run_pending)
4638                 return -EBUSY;
4639
4640        /*
4641         * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
4642         * e.g. if the IRQ arrived asynchronously after checking nested events.
4643         */
4644         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4645                 return -EBUSY;
4646
4647         return !vmx_interrupt_blocked(vcpu);
4648 }
4649
4650 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4651 {
4652         void __user *ret;
4653
4654         if (enable_unrestricted_guest)
4655                 return 0;
4656
4657         mutex_lock(&kvm->slots_lock);
4658         ret = __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4659                                       PAGE_SIZE * 3);
4660         mutex_unlock(&kvm->slots_lock);
4661
4662         if (IS_ERR(ret))
4663                 return PTR_ERR(ret);
4664
4665         to_kvm_vmx(kvm)->tss_addr = addr;
4666
4667         return init_rmode_tss(kvm, ret);
4668 }
4669
4670 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4671 {
4672         to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
4673         return 0;
4674 }
4675
4676 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4677 {
4678         switch (vec) {
4679         case BP_VECTOR:
4680                 /*
4681                  * Update instruction length as we may reinject the exception
4682                  * from user space while in guest debugging mode.
4683                  */
4684                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4685                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4686                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4687                         return false;
4688                 fallthrough;
4689         case DB_VECTOR:
4690                 return !(vcpu->guest_debug &
4691                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP));
4692         case DE_VECTOR:
4693         case OF_VECTOR:
4694         case BR_VECTOR:
4695         case UD_VECTOR:
4696         case DF_VECTOR:
4697         case SS_VECTOR:
4698         case GP_VECTOR:
4699         case MF_VECTOR:
4700                 return true;
4701         }
4702         return false;
4703 }
4704
4705 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4706                                   int vec, u32 err_code)
4707 {
4708         /*
4709          * Instruction with address size override prefix opcode 0x67
4710          * Cause the #SS fault with 0 error code in VM86 mode.
4711          */
4712         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4713                 if (kvm_emulate_instruction(vcpu, 0)) {
4714                         if (vcpu->arch.halt_request) {
4715                                 vcpu->arch.halt_request = 0;
4716                                 return kvm_vcpu_halt(vcpu);
4717                         }
4718                         return 1;
4719                 }
4720                 return 0;
4721         }
4722
4723         /*
4724          * Forward all other exceptions that are valid in real mode.
4725          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4726          *        the required debugging infrastructure rework.
4727          */
4728         kvm_queue_exception(vcpu, vec);
4729         return 1;
4730 }
4731
4732 static int handle_machine_check(struct kvm_vcpu *vcpu)
4733 {
4734         /* handled by vmx_vcpu_run() */
4735         return 1;
4736 }
4737
4738 /*
4739  * If the host has split lock detection disabled, then #AC is
4740  * unconditionally injected into the guest, which is the pre split lock
4741  * detection behaviour.
4742  *
4743  * If the host has split lock detection enabled then #AC is
4744  * only injected into the guest when:
4745  *  - Guest CPL == 3 (user mode)
4746  *  - Guest has #AC detection enabled in CR0
4747  *  - Guest EFLAGS has AC bit set
4748  */
4749 bool vmx_guest_inject_ac(struct kvm_vcpu *vcpu)
4750 {
4751         if (!boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
4752                 return true;
4753
4754         return vmx_get_cpl(vcpu) == 3 && kvm_read_cr0_bits(vcpu, X86_CR0_AM) &&
4755                (kvm_get_rflags(vcpu) & X86_EFLAGS_AC);
4756 }
4757
4758 static int handle_exception_nmi(struct kvm_vcpu *vcpu)
4759 {
4760         struct vcpu_vmx *vmx = to_vmx(vcpu);
4761         struct kvm_run *kvm_run = vcpu->run;
4762         u32 intr_info, ex_no, error_code;
4763         unsigned long cr2, dr6;
4764         u32 vect_info;
4765
4766         vect_info = vmx->idt_vectoring_info;
4767         intr_info = vmx_get_intr_info(vcpu);
4768
4769         if (is_machine_check(intr_info) || is_nmi(intr_info))
4770                 return 1; /* handled by handle_exception_nmi_irqoff() */
4771
4772         if (is_invalid_opcode(intr_info))
4773                 return handle_ud(vcpu);
4774
4775         error_code = 0;
4776         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4777                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4778
4779         if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4780                 WARN_ON_ONCE(!enable_vmware_backdoor);
4781
4782                 /*
4783                  * VMware backdoor emulation on #GP interception only handles
4784                  * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
4785                  * error code on #GP.
4786                  */
4787                 if (error_code) {
4788                         kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4789                         return 1;
4790                 }
4791                 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
4792         }
4793
4794         /*
4795          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4796          * MMIO, it is better to report an internal error.
4797          * See the comments in vmx_handle_exit.
4798          */
4799         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4800             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4801                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4802                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4803                 vcpu->run->internal.ndata = 4;
4804                 vcpu->run->internal.data[0] = vect_info;
4805                 vcpu->run->internal.data[1] = intr_info;
4806                 vcpu->run->internal.data[2] = error_code;
4807                 vcpu->run->internal.data[3] = vcpu->arch.last_vmentry_cpu;
4808                 return 0;
4809         }
4810
4811         if (is_page_fault(intr_info)) {
4812                 cr2 = vmx_get_exit_qual(vcpu);
4813                 if (enable_ept && !vcpu->arch.apf.host_apf_flags) {
4814                         /*
4815                          * EPT will cause page fault only if we need to
4816                          * detect illegal GPAs.
4817                          */
4818                         WARN_ON_ONCE(!allow_smaller_maxphyaddr);
4819                         kvm_fixup_and_inject_pf_error(vcpu, cr2, error_code);
4820                         return 1;
4821                 } else
4822                         return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
4823         }
4824
4825         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4826
4827         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4828                 return handle_rmode_exception(vcpu, ex_no, error_code);
4829
4830         switch (ex_no) {
4831         case DB_VECTOR:
4832                 dr6 = vmx_get_exit_qual(vcpu);
4833                 if (!(vcpu->guest_debug &
4834                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4835                         if (is_icebp(intr_info))
4836                                 WARN_ON(!skip_emulated_instruction(vcpu));
4837
4838                         kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
4839                         return 1;
4840                 }
4841                 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW;
4842                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4843                 fallthrough;
4844         case BP_VECTOR:
4845                 /*
4846                  * Update instruction length as we may reinject #BP from
4847                  * user space while in guest debugging mode. Reading it for
4848                  * #DB as well causes no harm, it is not used in that case.
4849                  */
4850                 vmx->vcpu.arch.event_exit_inst_len =
4851                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4852                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4853                 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
4854                 kvm_run->debug.arch.exception = ex_no;
4855                 break;
4856         case AC_VECTOR:
4857                 if (vmx_guest_inject_ac(vcpu)) {
4858                         kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4859                         return 1;
4860                 }
4861
4862                 /*
4863                  * Handle split lock. Depending on detection mode this will
4864                  * either warn and disable split lock detection for this
4865                  * task or force SIGBUS on it.
4866                  */
4867                 if (handle_guest_split_lock(kvm_rip_read(vcpu)))
4868                         return 1;
4869                 fallthrough;
4870         default:
4871                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4872                 kvm_run->ex.exception = ex_no;
4873                 kvm_run->ex.error_code = error_code;
4874                 break;
4875         }
4876         return 0;
4877 }
4878
4879 static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu)
4880 {
4881         ++vcpu->stat.irq_exits;
4882         return 1;
4883 }
4884
4885 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4886 {
4887         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4888         vcpu->mmio_needed = 0;
4889         return 0;
4890 }
4891
4892 static int handle_io(struct kvm_vcpu *vcpu)
4893 {
4894         unsigned long exit_qualification;
4895         int size, in, string;
4896         unsigned port;
4897
4898         exit_qualification = vmx_get_exit_qual(vcpu);
4899         string = (exit_qualification & 16) != 0;
4900
4901         ++vcpu->stat.io_exits;
4902
4903         if (string)
4904                 return kvm_emulate_instruction(vcpu, 0);
4905
4906         port = exit_qualification >> 16;
4907         size = (exit_qualification & 7) + 1;
4908         in = (exit_qualification & 8) != 0;
4909
4910         return kvm_fast_pio(vcpu, size, port, in);
4911 }
4912
4913 static void
4914 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4915 {
4916         /*
4917          * Patch in the VMCALL instruction:
4918          */
4919         hypercall[0] = 0x0f;
4920         hypercall[1] = 0x01;
4921         hypercall[2] = 0xc1;
4922 }
4923
4924 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4925 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4926 {
4927         if (is_guest_mode(vcpu)) {
4928                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4929                 unsigned long orig_val = val;
4930
4931                 /*
4932                  * We get here when L2 changed cr0 in a way that did not change
4933                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4934                  * but did change L0 shadowed bits. So we first calculate the
4935                  * effective cr0 value that L1 would like to write into the
4936                  * hardware. It consists of the L2-owned bits from the new
4937                  * value combined with the L1-owned bits from L1's guest_cr0.
4938                  */
4939                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4940                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4941
4942                 if (!nested_guest_cr0_valid(vcpu, val))
4943                         return 1;
4944
4945                 if (kvm_set_cr0(vcpu, val))
4946                         return 1;
4947                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4948                 return 0;
4949         } else {
4950                 if (to_vmx(vcpu)->nested.vmxon &&
4951                     !nested_host_cr0_valid(vcpu, val))
4952                         return 1;
4953
4954                 return kvm_set_cr0(vcpu, val);
4955         }
4956 }
4957
4958 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4959 {
4960         if (is_guest_mode(vcpu)) {
4961                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4962                 unsigned long orig_val = val;
4963
4964                 /* analogously to handle_set_cr0 */
4965                 val = (val & ~vmcs12->cr4_guest_host_mask) |
4966                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4967                 if (kvm_set_cr4(vcpu, val))
4968                         return 1;
4969                 vmcs_writel(CR4_READ_SHADOW, orig_val);
4970                 return 0;
4971         } else
4972                 return kvm_set_cr4(vcpu, val);
4973 }
4974
4975 static int handle_desc(struct kvm_vcpu *vcpu)
4976 {
4977         WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
4978         return kvm_emulate_instruction(vcpu, 0);
4979 }
4980
4981 static int handle_cr(struct kvm_vcpu *vcpu)
4982 {
4983         unsigned long exit_qualification, val;
4984         int cr;
4985         int reg;
4986         int err;
4987         int ret;
4988
4989         exit_qualification = vmx_get_exit_qual(vcpu);
4990         cr = exit_qualification & 15;
4991         reg = (exit_qualification >> 8) & 15;
4992         switch ((exit_qualification >> 4) & 3) {
4993         case 0: /* mov to cr */
4994                 val = kvm_register_read(vcpu, reg);
4995                 trace_kvm_cr_write(cr, val);
4996                 switch (cr) {
4997                 case 0:
4998                         err = handle_set_cr0(vcpu, val);
4999                         return kvm_complete_insn_gp(vcpu, err);
5000                 case 3:
5001                         WARN_ON_ONCE(enable_unrestricted_guest);
5002
5003                         err = kvm_set_cr3(vcpu, val);
5004                         return kvm_complete_insn_gp(vcpu, err);
5005                 case 4:
5006                         err = handle_set_cr4(vcpu, val);
5007                         return kvm_complete_insn_gp(vcpu, err);
5008                 case 8: {
5009                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5010                                 u8 cr8 = (u8)val;
5011                                 err = kvm_set_cr8(vcpu, cr8);
5012                                 ret = kvm_complete_insn_gp(vcpu, err);
5013                                 if (lapic_in_kernel(vcpu))
5014                                         return ret;
5015                                 if (cr8_prev <= cr8)
5016                                         return ret;
5017                                 /*
5018                                  * TODO: we might be squashing a
5019                                  * KVM_GUESTDBG_SINGLESTEP-triggered
5020                                  * KVM_EXIT_DEBUG here.
5021                                  */
5022                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5023                                 return 0;
5024                         }
5025                 }
5026                 break;
5027         case 2: /* clts */
5028                 KVM_BUG(1, vcpu->kvm, "Guest always owns CR0.TS");
5029                 return -EIO;
5030         case 1: /*mov from cr*/
5031                 switch (cr) {
5032                 case 3:
5033                         WARN_ON_ONCE(enable_unrestricted_guest);
5034
5035                         val = kvm_read_cr3(vcpu);
5036                         kvm_register_write(vcpu, reg, val);
5037                         trace_kvm_cr_read(cr, val);
5038                         return kvm_skip_emulated_instruction(vcpu);
5039                 case 8:
5040                         val = kvm_get_cr8(vcpu);
5041                         kvm_register_write(vcpu, reg, val);
5042                         trace_kvm_cr_read(cr, val);
5043                         return kvm_skip_emulated_instruction(vcpu);
5044                 }
5045                 break;
5046         case 3: /* lmsw */
5047                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5048                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5049                 kvm_lmsw(vcpu, val);
5050
5051                 return kvm_skip_emulated_instruction(vcpu);
5052         default:
5053                 break;
5054         }
5055         vcpu->run->exit_reason = 0;
5056         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5057                (int)(exit_qualification >> 4) & 3, cr);
5058         return 0;
5059 }
5060
5061 static int handle_dr(struct kvm_vcpu *vcpu)
5062 {
5063         unsigned long exit_qualification;
5064         int dr, dr7, reg;
5065         int err = 1;
5066
5067         exit_qualification = vmx_get_exit_qual(vcpu);
5068         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5069
5070         /* First, if DR does not exist, trigger UD */
5071         if (!kvm_require_dr(vcpu, dr))
5072                 return 1;
5073
5074         if (kvm_x86_ops.get_cpl(vcpu) > 0)
5075                 goto out;
5076
5077         dr7 = vmcs_readl(GUEST_DR7);
5078         if (dr7 & DR7_GD) {
5079                 /*
5080                  * As the vm-exit takes precedence over the debug trap, we
5081                  * need to emulate the latter, either for the host or the
5082                  * guest debugging itself.
5083                  */
5084                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5085                         vcpu->run->debug.arch.dr6 = DR6_BD | DR6_ACTIVE_LOW;
5086                         vcpu->run->debug.arch.dr7 = dr7;
5087                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5088                         vcpu->run->debug.arch.exception = DB_VECTOR;
5089                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5090                         return 0;
5091                 } else {
5092                         kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BD);
5093                         return 1;
5094                 }
5095         }
5096
5097         if (vcpu->guest_debug == 0) {
5098                 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
5099
5100                 /*
5101                  * No more DR vmexits; force a reload of the debug registers
5102                  * and reenter on this instruction.  The next vmexit will
5103                  * retrieve the full state of the debug registers.
5104                  */
5105                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5106                 return 1;
5107         }
5108
5109         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5110         if (exit_qualification & TYPE_MOV_FROM_DR) {
5111                 unsigned long val;
5112
5113                 kvm_get_dr(vcpu, dr, &val);
5114                 kvm_register_write(vcpu, reg, val);
5115                 err = 0;
5116         } else {
5117                 err = kvm_set_dr(vcpu, dr, kvm_register_read(vcpu, reg));
5118         }
5119
5120 out:
5121         return kvm_complete_insn_gp(vcpu, err);
5122 }
5123
5124 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5125 {
5126         get_debugreg(vcpu->arch.db[0], 0);
5127         get_debugreg(vcpu->arch.db[1], 1);
5128         get_debugreg(vcpu->arch.db[2], 2);
5129         get_debugreg(vcpu->arch.db[3], 3);
5130         get_debugreg(vcpu->arch.dr6, 6);
5131         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5132
5133         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5134         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
5135
5136         /*
5137          * exc_debug expects dr6 to be cleared after it runs, avoid that it sees
5138          * a stale dr6 from the guest.
5139          */
5140         set_debugreg(DR6_RESERVED, 6);
5141 }
5142
5143 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5144 {
5145         vmcs_writel(GUEST_DR7, val);
5146 }
5147
5148 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5149 {
5150         kvm_apic_update_ppr(vcpu);
5151         return 1;
5152 }
5153
5154 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5155 {
5156         exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
5157
5158         kvm_make_request(KVM_REQ_EVENT, vcpu);
5159
5160         ++vcpu->stat.irq_window_exits;
5161         return 1;
5162 }
5163
5164 static int handle_invlpg(struct kvm_vcpu *vcpu)
5165 {
5166         unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5167
5168         kvm_mmu_invlpg(vcpu, exit_qualification);
5169         return kvm_skip_emulated_instruction(vcpu);
5170 }
5171
5172 static int handle_apic_access(struct kvm_vcpu *vcpu)
5173 {
5174         if (likely(fasteoi)) {
5175                 unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5176                 int access_type, offset;
5177
5178                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5179                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5180                 /*
5181                  * Sane guest uses MOV to write EOI, with written value
5182                  * not cared. So make a short-circuit here by avoiding
5183                  * heavy instruction emulation.
5184                  */
5185                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5186                     (offset == APIC_EOI)) {
5187                         kvm_lapic_set_eoi(vcpu);
5188                         return kvm_skip_emulated_instruction(vcpu);
5189                 }
5190         }
5191         return kvm_emulate_instruction(vcpu, 0);
5192 }
5193
5194 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5195 {
5196         unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5197         int vector = exit_qualification & 0xff;
5198
5199         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5200         kvm_apic_set_eoi_accelerated(vcpu, vector);
5201         return 1;
5202 }
5203
5204 static int handle_apic_write(struct kvm_vcpu *vcpu)
5205 {
5206         unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5207         u32 offset = exit_qualification & 0xfff;
5208
5209         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5210         kvm_apic_write_nodecode(vcpu, offset);
5211         return 1;
5212 }
5213
5214 static int handle_task_switch(struct kvm_vcpu *vcpu)
5215 {
5216         struct vcpu_vmx *vmx = to_vmx(vcpu);
5217         unsigned long exit_qualification;
5218         bool has_error_code = false;
5219         u32 error_code = 0;
5220         u16 tss_selector;
5221         int reason, type, idt_v, idt_index;
5222
5223         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5224         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5225         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5226
5227         exit_qualification = vmx_get_exit_qual(vcpu);
5228
5229         reason = (u32)exit_qualification >> 30;
5230         if (reason == TASK_SWITCH_GATE && idt_v) {
5231                 switch (type) {
5232                 case INTR_TYPE_NMI_INTR:
5233                         vcpu->arch.nmi_injected = false;
5234                         vmx_set_nmi_mask(vcpu, true);
5235                         break;
5236                 case INTR_TYPE_EXT_INTR:
5237                 case INTR_TYPE_SOFT_INTR:
5238                         kvm_clear_interrupt_queue(vcpu);
5239                         break;
5240                 case INTR_TYPE_HARD_EXCEPTION:
5241                         if (vmx->idt_vectoring_info &
5242                             VECTORING_INFO_DELIVER_CODE_MASK) {
5243                                 has_error_code = true;
5244                                 error_code =
5245                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5246                         }
5247                         fallthrough;
5248                 case INTR_TYPE_SOFT_EXCEPTION:
5249                         kvm_clear_exception_queue(vcpu);
5250                         break;
5251                 default:
5252                         break;
5253                 }
5254         }
5255         tss_selector = exit_qualification;
5256
5257         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5258                        type != INTR_TYPE_EXT_INTR &&
5259                        type != INTR_TYPE_NMI_INTR))
5260                 WARN_ON(!skip_emulated_instruction(vcpu));
5261
5262         /*
5263          * TODO: What about debug traps on tss switch?
5264          *       Are we supposed to inject them and update dr6?
5265          */
5266         return kvm_task_switch(vcpu, tss_selector,
5267                                type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
5268                                reason, has_error_code, error_code);
5269 }
5270
5271 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5272 {
5273         unsigned long exit_qualification;
5274         gpa_t gpa;
5275         u64 error_code;
5276
5277         exit_qualification = vmx_get_exit_qual(vcpu);
5278
5279         /*
5280          * EPT violation happened while executing iret from NMI,
5281          * "blocked by NMI" bit has to be set before next VM entry.
5282          * There are errata that may cause this bit to not be set:
5283          * AAK134, BY25.
5284          */
5285         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5286                         enable_vnmi &&
5287                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5288                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5289
5290         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5291         trace_kvm_page_fault(gpa, exit_qualification);
5292
5293         /* Is it a read fault? */
5294         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
5295                      ? PFERR_USER_MASK : 0;
5296         /* Is it a write fault? */
5297         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
5298                       ? PFERR_WRITE_MASK : 0;
5299         /* Is it a fetch fault? */
5300         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
5301                       ? PFERR_FETCH_MASK : 0;
5302         /* ept page table entry is present? */
5303         error_code |= (exit_qualification &
5304                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5305                         EPT_VIOLATION_EXECUTABLE))
5306                       ? PFERR_PRESENT_MASK : 0;
5307
5308         error_code |= (exit_qualification & EPT_VIOLATION_GVA_TRANSLATED) != 0 ?
5309                PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
5310
5311         vcpu->arch.exit_qualification = exit_qualification;
5312
5313         /*
5314          * Check that the GPA doesn't exceed physical memory limits, as that is
5315          * a guest page fault.  We have to emulate the instruction here, because
5316          * if the illegal address is that of a paging structure, then
5317          * EPT_VIOLATION_ACC_WRITE bit is set.  Alternatively, if supported we
5318          * would also use advanced VM-exit information for EPT violations to
5319          * reconstruct the page fault error code.
5320          */
5321         if (unlikely(allow_smaller_maxphyaddr && kvm_vcpu_is_illegal_gpa(vcpu, gpa)))
5322                 return kvm_emulate_instruction(vcpu, 0);
5323
5324         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5325 }
5326
5327 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5328 {
5329         gpa_t gpa;
5330
5331         if (!vmx_can_emulate_instruction(vcpu, NULL, 0))
5332                 return 1;
5333
5334         /*
5335          * A nested guest cannot optimize MMIO vmexits, because we have an
5336          * nGPA here instead of the required GPA.
5337          */
5338         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5339         if (!is_guest_mode(vcpu) &&
5340             !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5341                 trace_kvm_fast_mmio(gpa);
5342                 return kvm_skip_emulated_instruction(vcpu);
5343         }
5344
5345         return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
5346 }
5347
5348 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5349 {
5350         if (KVM_BUG_ON(!enable_vnmi, vcpu->kvm))
5351                 return -EIO;
5352
5353         exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
5354         ++vcpu->stat.nmi_window_exits;
5355         kvm_make_request(KVM_REQ_EVENT, vcpu);
5356
5357         return 1;
5358 }
5359
5360 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5361 {
5362         struct vcpu_vmx *vmx = to_vmx(vcpu);
5363         bool intr_window_requested;
5364         unsigned count = 130;
5365
5366         intr_window_requested = exec_controls_get(vmx) &
5367                                 CPU_BASED_INTR_WINDOW_EXITING;
5368
5369         while (vmx->emulation_required && count-- != 0) {
5370                 if (intr_window_requested && !vmx_interrupt_blocked(vcpu))
5371                         return handle_interrupt_window(&vmx->vcpu);
5372
5373                 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
5374                         return 1;
5375
5376                 if (!kvm_emulate_instruction(vcpu, 0))
5377                         return 0;
5378
5379                 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5380                     vcpu->arch.exception.pending) {
5381                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5382                         vcpu->run->internal.suberror =
5383                                                 KVM_INTERNAL_ERROR_EMULATION;
5384                         vcpu->run->internal.ndata = 0;
5385                         return 0;
5386                 }
5387
5388                 if (vcpu->arch.halt_request) {
5389                         vcpu->arch.halt_request = 0;
5390                         return kvm_vcpu_halt(vcpu);
5391                 }
5392
5393                 /*
5394                  * Note, return 1 and not 0, vcpu_run() will invoke
5395                  * xfer_to_guest_mode() which will create a proper return
5396                  * code.
5397                  */
5398                 if (__xfer_to_guest_mode_work_pending())
5399                         return 1;
5400         }
5401
5402         return 1;
5403 }
5404
5405 static void grow_ple_window(struct kvm_vcpu *vcpu)
5406 {
5407         struct vcpu_vmx *vmx = to_vmx(vcpu);
5408         unsigned int old = vmx->ple_window;
5409
5410         vmx->ple_window = __grow_ple_window(old, ple_window,
5411                                             ple_window_grow,
5412                                             ple_window_max);
5413
5414         if (vmx->ple_window != old) {
5415                 vmx->ple_window_dirty = true;
5416                 trace_kvm_ple_window_update(vcpu->vcpu_id,
5417                                             vmx->ple_window, old);
5418         }
5419 }
5420
5421 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5422 {
5423         struct vcpu_vmx *vmx = to_vmx(vcpu);
5424         unsigned int old = vmx->ple_window;
5425
5426         vmx->ple_window = __shrink_ple_window(old, ple_window,
5427                                               ple_window_shrink,
5428                                               ple_window);
5429
5430         if (vmx->ple_window != old) {
5431                 vmx->ple_window_dirty = true;
5432                 trace_kvm_ple_window_update(vcpu->vcpu_id,
5433                                             vmx->ple_window, old);
5434         }
5435 }
5436
5437 /*
5438  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5439  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5440  */
5441 static int handle_pause(struct kvm_vcpu *vcpu)
5442 {
5443         if (!kvm_pause_in_guest(vcpu->kvm))
5444                 grow_ple_window(vcpu);
5445
5446         /*
5447          * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5448          * VM-execution control is ignored if CPL > 0. OTOH, KVM
5449          * never set PAUSE_EXITING and just set PLE if supported,
5450          * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5451          */
5452         kvm_vcpu_on_spin(vcpu, true);
5453         return kvm_skip_emulated_instruction(vcpu);
5454 }
5455
5456 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5457 {
5458         return 1;
5459 }
5460
5461 static int handle_invpcid(struct kvm_vcpu *vcpu)
5462 {
5463         u32 vmx_instruction_info;
5464         unsigned long type;
5465         gva_t gva;
5466         struct {
5467                 u64 pcid;
5468                 u64 gla;
5469         } operand;
5470
5471         if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
5472                 kvm_queue_exception(vcpu, UD_VECTOR);
5473                 return 1;
5474         }
5475
5476         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5477         type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
5478
5479         if (type > 3) {
5480                 kvm_inject_gp(vcpu, 0);
5481                 return 1;
5482         }
5483
5484         /* According to the Intel instruction reference, the memory operand
5485          * is read even if it isn't needed (e.g., for type==all)
5486          */
5487         if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu),
5488                                 vmx_instruction_info, false,
5489                                 sizeof(operand), &gva))
5490                 return 1;
5491
5492         return kvm_handle_invpcid(vcpu, type, gva);
5493 }
5494
5495 static int handle_pml_full(struct kvm_vcpu *vcpu)
5496 {
5497         unsigned long exit_qualification;
5498
5499         trace_kvm_pml_full(vcpu->vcpu_id);
5500
5501         exit_qualification = vmx_get_exit_qual(vcpu);
5502
5503         /*
5504          * PML buffer FULL happened while executing iret from NMI,
5505          * "blocked by NMI" bit has to be set before next VM entry.
5506          */
5507         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5508                         enable_vnmi &&
5509                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5510                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5511                                 GUEST_INTR_STATE_NMI);
5512
5513         /*
5514          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5515          * here.., and there's no userspace involvement needed for PML.
5516          */
5517         return 1;
5518 }
5519
5520 static fastpath_t handle_fastpath_preemption_timer(struct kvm_vcpu *vcpu)
5521 {
5522         struct vcpu_vmx *vmx = to_vmx(vcpu);
5523
5524         if (!vmx->req_immediate_exit &&
5525             !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled)) {
5526                 kvm_lapic_expired_hv_timer(vcpu);
5527                 return EXIT_FASTPATH_REENTER_GUEST;
5528         }
5529
5530         return EXIT_FASTPATH_NONE;
5531 }
5532
5533 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
5534 {
5535         handle_fastpath_preemption_timer(vcpu);
5536         return 1;
5537 }
5538
5539 /*
5540  * When nested=0, all VMX instruction VM Exits filter here.  The handlers
5541  * are overwritten by nested_vmx_setup() when nested=1.
5542  */
5543 static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
5544 {
5545         kvm_queue_exception(vcpu, UD_VECTOR);
5546         return 1;
5547 }
5548
5549 #ifndef CONFIG_X86_SGX_KVM
5550 static int handle_encls(struct kvm_vcpu *vcpu)
5551 {
5552         /*
5553          * SGX virtualization is disabled.  There is no software enable bit for
5554          * SGX, so KVM intercepts all ENCLS leafs and injects a #UD to prevent
5555          * the guest from executing ENCLS (when SGX is supported by hardware).
5556          */
5557         kvm_queue_exception(vcpu, UD_VECTOR);
5558         return 1;
5559 }
5560 #endif /* CONFIG_X86_SGX_KVM */
5561
5562 static int handle_bus_lock_vmexit(struct kvm_vcpu *vcpu)
5563 {
5564         vcpu->run->exit_reason = KVM_EXIT_X86_BUS_LOCK;
5565         vcpu->run->flags |= KVM_RUN_X86_BUS_LOCK;
5566         return 0;
5567 }
5568
5569 /*
5570  * The exit handlers return 1 if the exit was handled fully and guest execution
5571  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5572  * to be done to userspace and return 0.
5573  */
5574 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5575         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception_nmi,
5576         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5577         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5578         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5579         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5580         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5581         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5582         [EXIT_REASON_CPUID]                   = kvm_emulate_cpuid,
5583         [EXIT_REASON_MSR_READ]                = kvm_emulate_rdmsr,
5584         [EXIT_REASON_MSR_WRITE]               = kvm_emulate_wrmsr,
5585         [EXIT_REASON_INTERRUPT_WINDOW]        = handle_interrupt_window,
5586         [EXIT_REASON_HLT]                     = kvm_emulate_halt,
5587         [EXIT_REASON_INVD]                    = kvm_emulate_invd,
5588         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5589         [EXIT_REASON_RDPMC]                   = kvm_emulate_rdpmc,
5590         [EXIT_REASON_VMCALL]                  = kvm_emulate_hypercall,
5591         [EXIT_REASON_VMCLEAR]                 = handle_vmx_instruction,
5592         [EXIT_REASON_VMLAUNCH]                = handle_vmx_instruction,
5593         [EXIT_REASON_VMPTRLD]                 = handle_vmx_instruction,
5594         [EXIT_REASON_VMPTRST]                 = handle_vmx_instruction,
5595         [EXIT_REASON_VMREAD]                  = handle_vmx_instruction,
5596         [EXIT_REASON_VMRESUME]                = handle_vmx_instruction,
5597         [EXIT_REASON_VMWRITE]                 = handle_vmx_instruction,
5598         [EXIT_REASON_VMOFF]                   = handle_vmx_instruction,
5599         [EXIT_REASON_VMON]                    = handle_vmx_instruction,
5600         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5601         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5602         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
5603         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
5604         [EXIT_REASON_WBINVD]                  = kvm_emulate_wbinvd,
5605         [EXIT_REASON_XSETBV]                  = kvm_emulate_xsetbv,
5606         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5607         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5608         [EXIT_REASON_GDTR_IDTR]               = handle_desc,
5609         [EXIT_REASON_LDTR_TR]                 = handle_desc,
5610         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5611         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5612         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5613         [EXIT_REASON_MWAIT_INSTRUCTION]       = kvm_emulate_mwait,
5614         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
5615         [EXIT_REASON_MONITOR_INSTRUCTION]     = kvm_emulate_monitor,
5616         [EXIT_REASON_INVEPT]                  = handle_vmx_instruction,
5617         [EXIT_REASON_INVVPID]                 = handle_vmx_instruction,
5618         [EXIT_REASON_RDRAND]                  = kvm_handle_invalid_op,
5619         [EXIT_REASON_RDSEED]                  = kvm_handle_invalid_op,
5620         [EXIT_REASON_PML_FULL]                = handle_pml_full,
5621         [EXIT_REASON_INVPCID]                 = handle_invpcid,
5622         [EXIT_REASON_VMFUNC]                  = handle_vmx_instruction,
5623         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
5624         [EXIT_REASON_ENCLS]                   = handle_encls,
5625         [EXIT_REASON_BUS_LOCK]                = handle_bus_lock_vmexit,
5626 };
5627
5628 static const int kvm_vmx_max_exit_handlers =
5629         ARRAY_SIZE(kvm_vmx_exit_handlers);
5630
5631 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2,
5632                               u32 *intr_info, u32 *error_code)
5633 {
5634         struct vcpu_vmx *vmx = to_vmx(vcpu);
5635
5636         *info1 = vmx_get_exit_qual(vcpu);
5637         if (!(vmx->exit_reason.failed_vmentry)) {
5638                 *info2 = vmx->idt_vectoring_info;
5639                 *intr_info = vmx_get_intr_info(vcpu);
5640                 if (is_exception_with_error_code(*intr_info))
5641                         *error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5642                 else
5643                         *error_code = 0;
5644         } else {
5645                 *info2 = 0;
5646                 *intr_info = 0;
5647                 *error_code = 0;
5648         }
5649 }
5650
5651 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
5652 {
5653         if (vmx->pml_pg) {
5654                 __free_page(vmx->pml_pg);
5655                 vmx->pml_pg = NULL;
5656         }
5657 }
5658
5659 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
5660 {
5661         struct vcpu_vmx *vmx = to_vmx(vcpu);
5662         u64 *pml_buf;
5663         u16 pml_idx;
5664
5665         pml_idx = vmcs_read16(GUEST_PML_INDEX);
5666
5667         /* Do nothing if PML buffer is empty */
5668         if (pml_idx == (PML_ENTITY_NUM - 1))
5669                 return;
5670
5671         /* PML index always points to next available PML buffer entity */
5672         if (pml_idx >= PML_ENTITY_NUM)
5673                 pml_idx = 0;
5674         else
5675                 pml_idx++;
5676
5677         pml_buf = page_address(vmx->pml_pg);
5678         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5679                 u64 gpa;
5680
5681                 gpa = pml_buf[pml_idx];
5682                 WARN_ON(gpa & (PAGE_SIZE - 1));
5683                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5684         }
5685
5686         /* reset PML index */
5687         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5688 }
5689
5690 static void vmx_dump_sel(char *name, uint32_t sel)
5691 {
5692         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5693                name, vmcs_read16(sel),
5694                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5695                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5696                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
5697 }
5698
5699 static void vmx_dump_dtsel(char *name, uint32_t limit)
5700 {
5701         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
5702                name, vmcs_read32(limit),
5703                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
5704 }
5705
5706 static void vmx_dump_msrs(char *name, struct vmx_msrs *m)
5707 {
5708         unsigned int i;
5709         struct vmx_msr_entry *e;
5710
5711         pr_err("MSR %s:\n", name);
5712         for (i = 0, e = m->val; i < m->nr; ++i, ++e)
5713                 pr_err("  %2d: msr=0x%08x value=0x%016llx\n", i, e->index, e->value);
5714 }
5715
5716 void dump_vmcs(struct kvm_vcpu *vcpu)
5717 {
5718         struct vcpu_vmx *vmx = to_vmx(vcpu);
5719         u32 vmentry_ctl, vmexit_ctl;
5720         u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5721         unsigned long cr4;
5722         int efer_slot;
5723
5724         if (!dump_invalid_vmcs) {
5725                 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5726                 return;
5727         }
5728
5729         vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5730         vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5731         cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5732         pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5733         cr4 = vmcs_readl(GUEST_CR4);
5734         secondary_exec_control = 0;
5735         if (cpu_has_secondary_exec_ctrls())
5736                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5737
5738         pr_err("VMCS %p, last attempted VM-entry on CPU %d\n",
5739                vmx->loaded_vmcs->vmcs, vcpu->arch.last_vmentry_cpu);
5740         pr_err("*** Guest State ***\n");
5741         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5742                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5743                vmcs_readl(CR0_GUEST_HOST_MASK));
5744         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5745                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5746         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5747         if (cpu_has_vmx_ept()) {
5748                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
5749                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5750                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
5751                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
5752         }
5753         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
5754                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5755         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
5756                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5757         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5758                vmcs_readl(GUEST_SYSENTER_ESP),
5759                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5760         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
5761         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
5762         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
5763         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
5764         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
5765         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
5766         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5767         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5768         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5769         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
5770         efer_slot = vmx_find_loadstore_msr_slot(&vmx->msr_autoload.guest, MSR_EFER);
5771         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_EFER)
5772                 pr_err("EFER= 0x%016llx\n", vmcs_read64(GUEST_IA32_EFER));
5773         else if (efer_slot >= 0)
5774                 pr_err("EFER= 0x%016llx (autoload)\n",
5775                        vmx->msr_autoload.guest.val[efer_slot].value);
5776         else if (vmentry_ctl & VM_ENTRY_IA32E_MODE)
5777                 pr_err("EFER= 0x%016llx (effective)\n",
5778                        vcpu->arch.efer | (EFER_LMA | EFER_LME));
5779         else
5780                 pr_err("EFER= 0x%016llx (effective)\n",
5781                        vcpu->arch.efer & ~(EFER_LMA | EFER_LME));
5782         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PAT)
5783                 pr_err("PAT = 0x%016llx\n", vmcs_read64(GUEST_IA32_PAT));
5784         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
5785                vmcs_read64(GUEST_IA32_DEBUGCTL),
5786                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5787         if (cpu_has_load_perf_global_ctrl() &&
5788             vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5789                 pr_err("PerfGlobCtl = 0x%016llx\n",
5790                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5791         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5792                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5793         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
5794                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5795                vmcs_read32(GUEST_ACTIVITY_STATE));
5796         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5797                 pr_err("InterruptStatus = %04x\n",
5798                        vmcs_read16(GUEST_INTR_STATUS));
5799         if (vmcs_read32(VM_ENTRY_MSR_LOAD_COUNT) > 0)
5800                 vmx_dump_msrs("guest autoload", &vmx->msr_autoload.guest);
5801         if (vmcs_read32(VM_EXIT_MSR_STORE_COUNT) > 0)
5802                 vmx_dump_msrs("guest autostore", &vmx->msr_autostore.guest);
5803
5804         pr_err("*** Host State ***\n");
5805         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
5806                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5807         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5808                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5809                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5810                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5811                vmcs_read16(HOST_TR_SELECTOR));
5812         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5813                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5814                vmcs_readl(HOST_TR_BASE));
5815         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5816                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5817         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5818                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5819                vmcs_readl(HOST_CR4));
5820         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5821                vmcs_readl(HOST_IA32_SYSENTER_ESP),
5822                vmcs_read32(HOST_IA32_SYSENTER_CS),
5823                vmcs_readl(HOST_IA32_SYSENTER_EIP));
5824         if (vmexit_ctl & VM_EXIT_LOAD_IA32_EFER)
5825                 pr_err("EFER= 0x%016llx\n", vmcs_read64(HOST_IA32_EFER));
5826         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PAT)
5827                 pr_err("PAT = 0x%016llx\n", vmcs_read64(HOST_IA32_PAT));
5828         if (cpu_has_load_perf_global_ctrl() &&
5829             vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5830                 pr_err("PerfGlobCtl = 0x%016llx\n",
5831                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
5832         if (vmcs_read32(VM_EXIT_MSR_LOAD_COUNT) > 0)
5833                 vmx_dump_msrs("host autoload", &vmx->msr_autoload.host);
5834
5835         pr_err("*** Control State ***\n");
5836         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5837                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5838         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5839         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5840                vmcs_read32(EXCEPTION_BITMAP),
5841                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5842                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5843         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5844                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5845                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5846                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5847         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5848                vmcs_read32(VM_EXIT_INTR_INFO),
5849                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5850                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5851         pr_err("        reason=%08x qualification=%016lx\n",
5852                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5853         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5854                vmcs_read32(IDT_VECTORING_INFO_FIELD),
5855                vmcs_read32(IDT_VECTORING_ERROR_CODE));
5856         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5857         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5858                 pr_err("TSC Multiplier = 0x%016llx\n",
5859                        vmcs_read64(TSC_MULTIPLIER));
5860         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5861                 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5862                         u16 status = vmcs_read16(GUEST_INTR_STATUS);
5863                         pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5864                 }
5865                 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
5866                 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5867                         pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
5868                 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
5869         }
5870         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5871                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5872         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5873                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5874         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5875                 pr_err("PLE Gap=%08x Window=%08x\n",
5876                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5877         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5878                 pr_err("Virtual processor ID = 0x%04x\n",
5879                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
5880 }
5881
5882 /*
5883  * The guest has exited.  See if we can fix it or if we need userspace
5884  * assistance.
5885  */
5886 static int __vmx_handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
5887 {
5888         struct vcpu_vmx *vmx = to_vmx(vcpu);
5889         union vmx_exit_reason exit_reason = vmx->exit_reason;
5890         u32 vectoring_info = vmx->idt_vectoring_info;
5891         u16 exit_handler_index;
5892
5893         /*
5894          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5895          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5896          * querying dirty_bitmap, we only need to kick all vcpus out of guest
5897          * mode as if vcpus is in root mode, the PML buffer must has been
5898          * flushed already.  Note, PML is never enabled in hardware while
5899          * running L2.
5900          */
5901         if (enable_pml && !is_guest_mode(vcpu))
5902                 vmx_flush_pml_buffer(vcpu);
5903
5904         /*
5905          * We should never reach this point with a pending nested VM-Enter, and
5906          * more specifically emulation of L2 due to invalid guest state (see
5907          * below) should never happen as that means we incorrectly allowed a
5908          * nested VM-Enter with an invalid vmcs12.
5909          */
5910         if (KVM_BUG_ON(vmx->nested.nested_run_pending, vcpu->kvm))
5911                 return -EIO;
5912
5913         /* If guest state is invalid, start emulating */
5914         if (vmx->emulation_required)
5915                 return handle_invalid_guest_state(vcpu);
5916
5917         if (is_guest_mode(vcpu)) {
5918                 /*
5919                  * PML is never enabled when running L2, bail immediately if a
5920                  * PML full exit occurs as something is horribly wrong.
5921                  */
5922                 if (exit_reason.basic == EXIT_REASON_PML_FULL)
5923                         goto unexpected_vmexit;
5924
5925                 /*
5926                  * The host physical addresses of some pages of guest memory
5927                  * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
5928                  * Page). The CPU may write to these pages via their host
5929                  * physical address while L2 is running, bypassing any
5930                  * address-translation-based dirty tracking (e.g. EPT write
5931                  * protection).
5932                  *
5933                  * Mark them dirty on every exit from L2 to prevent them from
5934                  * getting out of sync with dirty tracking.
5935                  */
5936                 nested_mark_vmcs12_pages_dirty(vcpu);
5937
5938                 if (nested_vmx_reflect_vmexit(vcpu))
5939                         return 1;
5940         }
5941
5942         if (exit_reason.failed_vmentry) {
5943                 dump_vmcs(vcpu);
5944                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5945                 vcpu->run->fail_entry.hardware_entry_failure_reason
5946                         = exit_reason.full;
5947                 vcpu->run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
5948                 return 0;
5949         }
5950
5951         if (unlikely(vmx->fail)) {
5952                 dump_vmcs(vcpu);
5953                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5954                 vcpu->run->fail_entry.hardware_entry_failure_reason
5955                         = vmcs_read32(VM_INSTRUCTION_ERROR);
5956                 vcpu->run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
5957                 return 0;
5958         }
5959
5960         /*
5961          * Note:
5962          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5963          * delivery event since it indicates guest is accessing MMIO.
5964          * The vm-exit can be triggered again after return to guest that
5965          * will cause infinite loop.
5966          */
5967         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5968             (exit_reason.basic != EXIT_REASON_EXCEPTION_NMI &&
5969              exit_reason.basic != EXIT_REASON_EPT_VIOLATION &&
5970              exit_reason.basic != EXIT_REASON_PML_FULL &&
5971              exit_reason.basic != EXIT_REASON_APIC_ACCESS &&
5972              exit_reason.basic != EXIT_REASON_TASK_SWITCH)) {
5973                 int ndata = 3;
5974
5975                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5976                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5977                 vcpu->run->internal.data[0] = vectoring_info;
5978                 vcpu->run->internal.data[1] = exit_reason.full;
5979                 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5980                 if (exit_reason.basic == EXIT_REASON_EPT_MISCONFIG) {
5981                         vcpu->run->internal.data[ndata++] =
5982                                 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5983                 }
5984                 vcpu->run->internal.data[ndata++] = vcpu->arch.last_vmentry_cpu;
5985                 vcpu->run->internal.ndata = ndata;
5986                 return 0;
5987         }
5988
5989         if (unlikely(!enable_vnmi &&
5990                      vmx->loaded_vmcs->soft_vnmi_blocked)) {
5991                 if (!vmx_interrupt_blocked(vcpu)) {
5992                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5993                 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5994                            vcpu->arch.nmi_pending) {
5995                         /*
5996                          * This CPU don't support us in finding the end of an
5997                          * NMI-blocked window if the guest runs with IRQs
5998                          * disabled. So we pull the trigger after 1 s of
5999                          * futile waiting, but inform the user about this.
6000                          */
6001                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6002                                "state on VCPU %d after 1 s timeout\n",
6003                                __func__, vcpu->vcpu_id);
6004                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
6005                 }
6006         }
6007
6008         if (exit_fastpath != EXIT_FASTPATH_NONE)
6009                 return 1;
6010
6011         if (exit_reason.basic >= kvm_vmx_max_exit_handlers)
6012                 goto unexpected_vmexit;
6013 #ifdef CONFIG_RETPOLINE
6014         if (exit_reason.basic == EXIT_REASON_MSR_WRITE)
6015                 return kvm_emulate_wrmsr(vcpu);
6016         else if (exit_reason.basic == EXIT_REASON_PREEMPTION_TIMER)
6017                 return handle_preemption_timer(vcpu);
6018         else if (exit_reason.basic == EXIT_REASON_INTERRUPT_WINDOW)
6019                 return handle_interrupt_window(vcpu);
6020         else if (exit_reason.basic == EXIT_REASON_EXTERNAL_INTERRUPT)
6021                 return handle_external_interrupt(vcpu);
6022         else if (exit_reason.basic == EXIT_REASON_HLT)
6023                 return kvm_emulate_halt(vcpu);
6024         else if (exit_reason.basic == EXIT_REASON_EPT_MISCONFIG)
6025                 return handle_ept_misconfig(vcpu);
6026 #endif
6027
6028         exit_handler_index = array_index_nospec((u16)exit_reason.basic,
6029                                                 kvm_vmx_max_exit_handlers);
6030         if (!kvm_vmx_exit_handlers[exit_handler_index])
6031                 goto unexpected_vmexit;
6032
6033         return kvm_vmx_exit_handlers[exit_handler_index](vcpu);
6034
6035 unexpected_vmexit:
6036         vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
6037                     exit_reason.full);
6038         dump_vmcs(vcpu);
6039         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6040         vcpu->run->internal.suberror =
6041                         KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
6042         vcpu->run->internal.ndata = 2;
6043         vcpu->run->internal.data[0] = exit_reason.full;
6044         vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
6045         return 0;
6046 }
6047
6048 static int vmx_handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
6049 {
6050         int ret = __vmx_handle_exit(vcpu, exit_fastpath);
6051
6052         /*
6053          * Even when current exit reason is handled by KVM internally, we
6054          * still need to exit to user space when bus lock detected to inform
6055          * that there is a bus lock in guest.
6056          */
6057         if (to_vmx(vcpu)->exit_reason.bus_lock_detected) {
6058                 if (ret > 0)
6059                         vcpu->run->exit_reason = KVM_EXIT_X86_BUS_LOCK;
6060
6061                 vcpu->run->flags |= KVM_RUN_X86_BUS_LOCK;
6062                 return 0;
6063         }
6064         return ret;
6065 }
6066
6067 /*
6068  * Software based L1D cache flush which is used when microcode providing
6069  * the cache control MSR is not loaded.
6070  *
6071  * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
6072  * flush it is required to read in 64 KiB because the replacement algorithm
6073  * is not exactly LRU. This could be sized at runtime via topology
6074  * information but as all relevant affected CPUs have 32KiB L1D cache size
6075  * there is no point in doing so.
6076  */
6077 static noinstr void vmx_l1d_flush(struct kvm_vcpu *vcpu)
6078 {
6079         int size = PAGE_SIZE << L1D_CACHE_ORDER;
6080
6081         /*
6082          * This code is only executed when the the flush mode is 'cond' or
6083          * 'always'
6084          */
6085         if (static_branch_likely(&vmx_l1d_flush_cond)) {
6086                 bool flush_l1d;
6087
6088                 /*
6089                  * Clear the per-vcpu flush bit, it gets set again
6090                  * either from vcpu_run() or from one of the unsafe
6091                  * VMEXIT handlers.
6092                  */
6093                 flush_l1d = vcpu->arch.l1tf_flush_l1d;
6094                 vcpu->arch.l1tf_flush_l1d = false;
6095
6096                 /*
6097                  * Clear the per-cpu flush bit, it gets set again from
6098                  * the interrupt handlers.
6099                  */
6100                 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
6101                 kvm_clear_cpu_l1tf_flush_l1d();
6102
6103                 if (!flush_l1d)
6104                         return;
6105         }
6106
6107         vcpu->stat.l1d_flush++;
6108
6109         if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
6110                 native_wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
6111                 return;
6112         }
6113
6114         asm volatile(
6115                 /* First ensure the pages are in the TLB */
6116                 "xorl   %%eax, %%eax\n"
6117                 ".Lpopulate_tlb:\n\t"
6118                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6119                 "addl   $4096, %%eax\n\t"
6120                 "cmpl   %%eax, %[size]\n\t"
6121                 "jne    .Lpopulate_tlb\n\t"
6122                 "xorl   %%eax, %%eax\n\t"
6123                 "cpuid\n\t"
6124                 /* Now fill the cache */
6125                 "xorl   %%eax, %%eax\n"
6126                 ".Lfill_cache:\n"
6127                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6128                 "addl   $64, %%eax\n\t"
6129                 "cmpl   %%eax, %[size]\n\t"
6130                 "jne    .Lfill_cache\n\t"
6131                 "lfence\n"
6132                 :: [flush_pages] "r" (vmx_l1d_flush_pages),
6133                     [size] "r" (size)
6134                 : "eax", "ebx", "ecx", "edx");
6135 }
6136
6137 static void vmx_update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6138 {
6139         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6140         int tpr_threshold;
6141
6142         if (is_guest_mode(vcpu) &&
6143                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
6144                 return;
6145
6146         tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr;
6147         if (is_guest_mode(vcpu))
6148                 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold;
6149         else
6150                 vmcs_write32(TPR_THRESHOLD, tpr_threshold);
6151 }
6152
6153 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
6154 {
6155         struct vcpu_vmx *vmx = to_vmx(vcpu);
6156         u32 sec_exec_control;
6157
6158         if (!lapic_in_kernel(vcpu))
6159                 return;
6160
6161         if (!flexpriority_enabled &&
6162             !cpu_has_vmx_virtualize_x2apic_mode())
6163                 return;
6164
6165         /* Postpone execution until vmcs01 is the current VMCS. */
6166         if (is_guest_mode(vcpu)) {
6167                 vmx->nested.change_vmcs01_virtual_apic_mode = true;
6168                 return;
6169         }
6170
6171         sec_exec_control = secondary_exec_controls_get(vmx);
6172         sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6173                               SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
6174
6175         switch (kvm_get_apic_mode(vcpu)) {
6176         case LAPIC_MODE_INVALID:
6177                 WARN_ONCE(true, "Invalid local APIC state");
6178                 break;
6179         case LAPIC_MODE_DISABLED:
6180                 break;
6181         case LAPIC_MODE_XAPIC:
6182                 if (flexpriority_enabled) {
6183                         sec_exec_control |=
6184                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6185                         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6186
6187                         /*
6188                          * Flush the TLB, reloading the APIC access page will
6189                          * only do so if its physical address has changed, but
6190                          * the guest may have inserted a non-APIC mapping into
6191                          * the TLB while the APIC access page was disabled.
6192                          */
6193                         kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
6194                 }
6195                 break;
6196         case LAPIC_MODE_X2APIC:
6197                 if (cpu_has_vmx_virtualize_x2apic_mode())
6198                         sec_exec_control |=
6199                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6200                 break;
6201         }
6202         secondary_exec_controls_set(vmx, sec_exec_control);
6203
6204         vmx_update_msr_bitmap_x2apic(vcpu);
6205 }
6206
6207 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu)
6208 {
6209         struct page *page;
6210
6211         /* Defer reload until vmcs01 is the current VMCS. */
6212         if (is_guest_mode(vcpu)) {
6213                 to_vmx(vcpu)->nested.reload_vmcs01_apic_access_page = true;
6214                 return;
6215         }
6216
6217         if (!(secondary_exec_controls_get(to_vmx(vcpu)) &
6218             SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
6219                 return;
6220
6221         page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6222         if (is_error_page(page))
6223                 return;
6224
6225         vmcs_write64(APIC_ACCESS_ADDR, page_to_phys(page));
6226         vmx_flush_tlb_current(vcpu);
6227
6228         /*
6229          * Do not pin apic access page in memory, the MMU notifier
6230          * will call us again if it is migrated or swapped out.
6231          */
6232         put_page(page);
6233 }
6234
6235 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6236 {
6237         u16 status;
6238         u8 old;
6239
6240         if (max_isr == -1)
6241                 max_isr = 0;
6242
6243         status = vmcs_read16(GUEST_INTR_STATUS);
6244         old = status >> 8;
6245         if (max_isr != old) {
6246                 status &= 0xff;
6247                 status |= max_isr << 8;
6248                 vmcs_write16(GUEST_INTR_STATUS, status);
6249         }
6250 }
6251
6252 static void vmx_set_rvi(int vector)
6253 {
6254         u16 status;
6255         u8 old;
6256
6257         if (vector == -1)
6258                 vector = 0;
6259
6260         status = vmcs_read16(GUEST_INTR_STATUS);
6261         old = (u8)status & 0xff;
6262         if ((u8)vector != old) {
6263                 status &= ~0xff;
6264                 status |= (u8)vector;
6265                 vmcs_write16(GUEST_INTR_STATUS, status);
6266         }
6267 }
6268
6269 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6270 {
6271         /*
6272          * When running L2, updating RVI is only relevant when
6273          * vmcs12 virtual-interrupt-delivery enabled.
6274          * However, it can be enabled only when L1 also
6275          * intercepts external-interrupts and in that case
6276          * we should not update vmcs02 RVI but instead intercept
6277          * interrupt. Therefore, do nothing when running L2.
6278          */
6279         if (!is_guest_mode(vcpu))
6280                 vmx_set_rvi(max_irr);
6281 }
6282
6283 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6284 {
6285         struct vcpu_vmx *vmx = to_vmx(vcpu);
6286         int max_irr;
6287         bool max_irr_updated;
6288
6289         if (KVM_BUG_ON(!vcpu->arch.apicv_active, vcpu->kvm))
6290                 return -EIO;
6291
6292         if (pi_test_on(&vmx->pi_desc)) {
6293                 pi_clear_on(&vmx->pi_desc);
6294                 /*
6295                  * IOMMU can write to PID.ON, so the barrier matters even on UP.
6296                  * But on x86 this is just a compiler barrier anyway.
6297                  */
6298                 smp_mb__after_atomic();
6299                 max_irr_updated =
6300                         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
6301
6302                 /*
6303                  * If we are running L2 and L1 has a new pending interrupt
6304                  * which can be injected, we should re-evaluate
6305                  * what should be done with this new L1 interrupt.
6306                  * If L1 intercepts external-interrupts, we should
6307                  * exit from L2 to L1. Otherwise, interrupt should be
6308                  * delivered directly to L2.
6309                  */
6310                 if (is_guest_mode(vcpu) && max_irr_updated) {
6311                         if (nested_exit_on_intr(vcpu))
6312                                 kvm_vcpu_exiting_guest_mode(vcpu);
6313                         else
6314                                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6315                 }
6316         } else {
6317                 max_irr = kvm_lapic_find_highest_irr(vcpu);
6318         }
6319         vmx_hwapic_irr_update(vcpu, max_irr);
6320         return max_irr;
6321 }
6322
6323 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6324 {
6325         if (!kvm_vcpu_apicv_active(vcpu))
6326                 return;
6327
6328         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6329         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6330         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6331         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6332 }
6333
6334 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
6335 {
6336         struct vcpu_vmx *vmx = to_vmx(vcpu);
6337
6338         pi_clear_on(&vmx->pi_desc);
6339         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6340 }
6341
6342 void vmx_do_interrupt_nmi_irqoff(unsigned long entry);
6343
6344 static void handle_interrupt_nmi_irqoff(struct kvm_vcpu *vcpu,
6345                                         unsigned long entry)
6346 {
6347         kvm_before_interrupt(vcpu);
6348         vmx_do_interrupt_nmi_irqoff(entry);
6349         kvm_after_interrupt(vcpu);
6350 }
6351
6352 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
6353 {
6354         const unsigned long nmi_entry = (unsigned long)asm_exc_nmi_noist;
6355         u32 intr_info = vmx_get_intr_info(&vmx->vcpu);
6356
6357         /* if exit due to PF check for async PF */
6358         if (is_page_fault(intr_info))
6359                 vmx->vcpu.arch.apf.host_apf_flags = kvm_read_and_reset_apf_flags();
6360         /* Handle machine checks before interrupts are enabled */
6361         else if (is_machine_check(intr_info))
6362                 kvm_machine_check();
6363         /* We need to handle NMIs before interrupts are enabled */
6364         else if (is_nmi(intr_info))
6365                 handle_interrupt_nmi_irqoff(&vmx->vcpu, nmi_entry);
6366 }
6367
6368 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
6369 {
6370         u32 intr_info = vmx_get_intr_info(vcpu);
6371         unsigned int vector = intr_info & INTR_INFO_VECTOR_MASK;
6372         gate_desc *desc = (gate_desc *)host_idt_base + vector;
6373
6374         if (KVM_BUG(!is_external_intr(intr_info), vcpu->kvm,
6375             "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6376                 return;
6377
6378         handle_interrupt_nmi_irqoff(vcpu, gate_offset(desc));
6379 }
6380
6381 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu)
6382 {
6383         struct vcpu_vmx *vmx = to_vmx(vcpu);
6384
6385         if (vmx->emulation_required)
6386                 return;
6387
6388         if (vmx->exit_reason.basic == EXIT_REASON_EXTERNAL_INTERRUPT)
6389                 handle_external_interrupt_irqoff(vcpu);
6390         else if (vmx->exit_reason.basic == EXIT_REASON_EXCEPTION_NMI)
6391                 handle_exception_nmi_irqoff(vmx);
6392 }
6393
6394 /*
6395  * The kvm parameter can be NULL (module initialization, or invocation before
6396  * VM creation). Be sure to check the kvm parameter before using it.
6397  */
6398 static bool vmx_has_emulated_msr(struct kvm *kvm, u32 index)
6399 {
6400         switch (index) {
6401         case MSR_IA32_SMBASE:
6402                 /*
6403                  * We cannot do SMM unless we can run the guest in big
6404                  * real mode.
6405                  */
6406                 return enable_unrestricted_guest || emulate_invalid_guest_state;
6407         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6408                 return nested;
6409         case MSR_AMD64_VIRT_SPEC_CTRL:
6410                 /* This is AMD only.  */
6411                 return false;
6412         default:
6413                 return true;
6414         }
6415 }
6416
6417 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6418 {
6419         u32 exit_intr_info;
6420         bool unblock_nmi;
6421         u8 vector;
6422         bool idtv_info_valid;
6423
6424         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6425
6426         if (enable_vnmi) {
6427                 if (vmx->loaded_vmcs->nmi_known_unmasked)
6428                         return;
6429
6430                 exit_intr_info = vmx_get_intr_info(&vmx->vcpu);
6431                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6432                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6433                 /*
6434                  * SDM 3: 27.7.1.2 (September 2008)
6435                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6436                  * a guest IRET fault.
6437                  * SDM 3: 23.2.2 (September 2008)
6438                  * Bit 12 is undefined in any of the following cases:
6439                  *  If the VM exit sets the valid bit in the IDT-vectoring
6440                  *   information field.
6441                  *  If the VM exit is due to a double fault.
6442                  */
6443                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6444                     vector != DF_VECTOR && !idtv_info_valid)
6445                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6446                                       GUEST_INTR_STATE_NMI);
6447                 else
6448                         vmx->loaded_vmcs->nmi_known_unmasked =
6449                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6450                                   & GUEST_INTR_STATE_NMI);
6451         } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6452                 vmx->loaded_vmcs->vnmi_blocked_time +=
6453                         ktime_to_ns(ktime_sub(ktime_get(),
6454                                               vmx->loaded_vmcs->entry_time));
6455 }
6456
6457 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6458                                       u32 idt_vectoring_info,
6459                                       int instr_len_field,
6460                                       int error_code_field)
6461 {
6462         u8 vector;
6463         int type;
6464         bool idtv_info_valid;
6465
6466         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6467
6468         vcpu->arch.nmi_injected = false;
6469         kvm_clear_exception_queue(vcpu);
6470         kvm_clear_interrupt_queue(vcpu);
6471
6472         if (!idtv_info_valid)
6473                 return;
6474
6475         kvm_make_request(KVM_REQ_EVENT, vcpu);
6476
6477         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6478         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6479
6480         switch (type) {
6481         case INTR_TYPE_NMI_INTR:
6482                 vcpu->arch.nmi_injected = true;
6483                 /*
6484                  * SDM 3: 27.7.1.2 (September 2008)
6485                  * Clear bit "block by NMI" before VM entry if a NMI
6486                  * delivery faulted.
6487                  */
6488                 vmx_set_nmi_mask(vcpu, false);
6489                 break;
6490         case INTR_TYPE_SOFT_EXCEPTION:
6491                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6492                 fallthrough;
6493         case INTR_TYPE_HARD_EXCEPTION:
6494                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6495                         u32 err = vmcs_read32(error_code_field);
6496                         kvm_requeue_exception_e(vcpu, vector, err);
6497                 } else
6498                         kvm_requeue_exception(vcpu, vector);
6499                 break;
6500         case INTR_TYPE_SOFT_INTR:
6501                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6502                 fallthrough;
6503         case INTR_TYPE_EXT_INTR:
6504                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6505                 break;
6506         default:
6507                 break;
6508         }
6509 }
6510
6511 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6512 {
6513         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6514                                   VM_EXIT_INSTRUCTION_LEN,
6515                                   IDT_VECTORING_ERROR_CODE);
6516 }
6517
6518 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6519 {
6520         __vmx_complete_interrupts(vcpu,
6521                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6522                                   VM_ENTRY_INSTRUCTION_LEN,
6523                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6524
6525         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6526 }
6527
6528 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6529 {
6530         int i, nr_msrs;
6531         struct perf_guest_switch_msr *msrs;
6532
6533         /* Note, nr_msrs may be garbage if perf_guest_get_msrs() returns NULL. */
6534         msrs = perf_guest_get_msrs(&nr_msrs);
6535         if (!msrs)
6536                 return;
6537
6538         for (i = 0; i < nr_msrs; i++)
6539                 if (msrs[i].host == msrs[i].guest)
6540                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6541                 else
6542                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6543                                         msrs[i].host, false);
6544 }
6545
6546 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
6547 {
6548         struct vcpu_vmx *vmx = to_vmx(vcpu);
6549         u64 tscl;
6550         u32 delta_tsc;
6551
6552         if (vmx->req_immediate_exit) {
6553                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6554                 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6555         } else if (vmx->hv_deadline_tsc != -1) {
6556                 tscl = rdtsc();
6557                 if (vmx->hv_deadline_tsc > tscl)
6558                         /* set_hv_timer ensures the delta fits in 32-bits */
6559                         delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6560                                 cpu_preemption_timer_multi);
6561                 else
6562                         delta_tsc = 0;
6563
6564                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6565                 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6566         } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6567                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6568                 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
6569         }
6570 }
6571
6572 void noinstr vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
6573 {
6574         if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6575                 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6576                 vmcs_writel(HOST_RSP, host_rsp);
6577         }
6578 }
6579
6580 static fastpath_t vmx_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
6581 {
6582         switch (to_vmx(vcpu)->exit_reason.basic) {
6583         case EXIT_REASON_MSR_WRITE:
6584                 return handle_fastpath_set_msr_irqoff(vcpu);
6585         case EXIT_REASON_PREEMPTION_TIMER:
6586                 return handle_fastpath_preemption_timer(vcpu);
6587         default:
6588                 return EXIT_FASTPATH_NONE;
6589         }
6590 }
6591
6592 static noinstr void vmx_vcpu_enter_exit(struct kvm_vcpu *vcpu,
6593                                         struct vcpu_vmx *vmx)
6594 {
6595         kvm_guest_enter_irqoff();
6596
6597         /* L1D Flush includes CPU buffer clear to mitigate MDS */
6598         if (static_branch_unlikely(&vmx_l1d_should_flush))
6599                 vmx_l1d_flush(vcpu);
6600         else if (static_branch_unlikely(&mds_user_clear))
6601                 mds_clear_cpu_buffers();
6602
6603         if (vcpu->arch.cr2 != native_read_cr2())
6604                 native_write_cr2(vcpu->arch.cr2);
6605
6606         vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6607                                    vmx->loaded_vmcs->launched);
6608
6609         vcpu->arch.cr2 = native_read_cr2();
6610
6611         kvm_guest_exit_irqoff();
6612 }
6613
6614 static fastpath_t vmx_vcpu_run(struct kvm_vcpu *vcpu)
6615 {
6616         struct vcpu_vmx *vmx = to_vmx(vcpu);
6617         unsigned long cr3, cr4;
6618
6619         /* Record the guest's net vcpu time for enforced NMI injections. */
6620         if (unlikely(!enable_vnmi &&
6621                      vmx->loaded_vmcs->soft_vnmi_blocked))
6622                 vmx->loaded_vmcs->entry_time = ktime_get();
6623
6624         /* Don't enter VMX if guest state is invalid, let the exit handler
6625            start emulation until we arrive back to a valid state */
6626         if (vmx->emulation_required)
6627                 return EXIT_FASTPATH_NONE;
6628
6629         trace_kvm_entry(vcpu);
6630
6631         if (vmx->ple_window_dirty) {
6632                 vmx->ple_window_dirty = false;
6633                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6634         }
6635
6636         /*
6637          * We did this in prepare_switch_to_guest, because it needs to
6638          * be within srcu_read_lock.
6639          */
6640         WARN_ON_ONCE(vmx->nested.need_vmcs12_to_shadow_sync);
6641
6642         if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP))
6643                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6644         if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP))
6645                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6646
6647         cr3 = __get_current_cr3_fast();
6648         if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6649                 vmcs_writel(HOST_CR3, cr3);
6650                 vmx->loaded_vmcs->host_state.cr3 = cr3;
6651         }
6652
6653         cr4 = cr4_read_shadow();
6654         if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6655                 vmcs_writel(HOST_CR4, cr4);
6656                 vmx->loaded_vmcs->host_state.cr4 = cr4;
6657         }
6658
6659         /* When KVM_DEBUGREG_WONT_EXIT, dr6 is accessible in guest. */
6660         if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
6661                 set_debugreg(vcpu->arch.dr6, 6);
6662
6663         /* When single-stepping over STI and MOV SS, we must clear the
6664          * corresponding interruptibility bits in the guest state. Otherwise
6665          * vmentry fails as it then expects bit 14 (BS) in pending debug
6666          * exceptions being set, but that's not correct for the guest debugging
6667          * case. */
6668         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6669                 vmx_set_interrupt_shadow(vcpu, 0);
6670
6671         kvm_load_guest_xsave_state(vcpu);
6672
6673         pt_guest_enter(vmx);
6674
6675         atomic_switch_perf_msrs(vmx);
6676         if (intel_pmu_lbr_is_enabled(vcpu))
6677                 vmx_passthrough_lbr_msrs(vcpu);
6678
6679         if (enable_preemption_timer)
6680                 vmx_update_hv_timer(vcpu);
6681
6682         kvm_wait_lapic_expire(vcpu);
6683
6684         /*
6685          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6686          * it's non-zero. Since vmentry is serialising on affected CPUs, there
6687          * is no need to worry about the conditional branch over the wrmsr
6688          * being speculatively taken.
6689          */
6690         x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6691
6692         /* The actual VMENTER/EXIT is in the .noinstr.text section. */
6693         vmx_vcpu_enter_exit(vcpu, vmx);
6694
6695         /*
6696          * We do not use IBRS in the kernel. If this vCPU has used the
6697          * SPEC_CTRL MSR it may have left it on; save the value and
6698          * turn it off. This is much more efficient than blindly adding
6699          * it to the atomic save/restore list. Especially as the former
6700          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6701          *
6702          * For non-nested case:
6703          * If the L01 MSR bitmap does not intercept the MSR, then we need to
6704          * save it.
6705          *
6706          * For nested case:
6707          * If the L02 MSR bitmap does not intercept the MSR, then we need to
6708          * save it.
6709          */
6710         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6711                 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
6712
6713         x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
6714
6715         /* All fields are clean at this point */
6716         if (static_branch_unlikely(&enable_evmcs)) {
6717                 current_evmcs->hv_clean_fields |=
6718                         HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
6719
6720                 current_evmcs->hv_vp_id = kvm_hv_get_vpindex(vcpu);
6721         }
6722
6723         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6724         if (vmx->host_debugctlmsr)
6725                 update_debugctlmsr(vmx->host_debugctlmsr);
6726
6727 #ifndef CONFIG_X86_64
6728         /*
6729          * The sysexit path does not restore ds/es, so we must set them to
6730          * a reasonable value ourselves.
6731          *
6732          * We can't defer this to vmx_prepare_switch_to_host() since that
6733          * function may be executed in interrupt context, which saves and
6734          * restore segments around it, nullifying its effect.
6735          */
6736         loadsegment(ds, __USER_DS);
6737         loadsegment(es, __USER_DS);
6738 #endif
6739
6740         vmx_register_cache_reset(vcpu);
6741
6742         pt_guest_exit(vmx);
6743
6744         kvm_load_host_xsave_state(vcpu);
6745
6746         if (is_guest_mode(vcpu)) {
6747                 /*
6748                  * Track VMLAUNCH/VMRESUME that have made past guest state
6749                  * checking.
6750                  */
6751                 if (vmx->nested.nested_run_pending &&
6752                     !vmx->exit_reason.failed_vmentry)
6753                         ++vcpu->stat.nested_run;
6754
6755                 vmx->nested.nested_run_pending = 0;
6756         }
6757
6758         vmx->idt_vectoring_info = 0;
6759
6760         if (unlikely(vmx->fail)) {
6761                 vmx->exit_reason.full = 0xdead;
6762                 return EXIT_FASTPATH_NONE;
6763         }
6764
6765         vmx->exit_reason.full = vmcs_read32(VM_EXIT_REASON);
6766         if (unlikely((u16)vmx->exit_reason.basic == EXIT_REASON_MCE_DURING_VMENTRY))
6767                 kvm_machine_check();
6768
6769         if (likely(!vmx->exit_reason.failed_vmentry))
6770                 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6771
6772         trace_kvm_exit(vmx->exit_reason.full, vcpu, KVM_ISA_VMX);
6773
6774         if (unlikely(vmx->exit_reason.failed_vmentry))
6775                 return EXIT_FASTPATH_NONE;
6776
6777         vmx->loaded_vmcs->launched = 1;
6778
6779         vmx_recover_nmi_blocking(vmx);
6780         vmx_complete_interrupts(vmx);
6781
6782         if (is_guest_mode(vcpu))
6783                 return EXIT_FASTPATH_NONE;
6784
6785         return vmx_exit_handlers_fastpath(vcpu);
6786 }
6787
6788 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6789 {
6790         struct vcpu_vmx *vmx = to_vmx(vcpu);
6791
6792         if (enable_pml)
6793                 vmx_destroy_pml_buffer(vmx);
6794         free_vpid(vmx->vpid);
6795         nested_vmx_free_vcpu(vcpu);
6796         free_loaded_vmcs(vmx->loaded_vmcs);
6797 }
6798
6799 static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
6800 {
6801         struct vmx_uret_msr *tsx_ctrl;
6802         struct vcpu_vmx *vmx;
6803         int i, cpu, err;
6804
6805         BUILD_BUG_ON(offsetof(struct vcpu_vmx, vcpu) != 0);
6806         vmx = to_vmx(vcpu);
6807
6808         err = -ENOMEM;
6809
6810         vmx->vpid = allocate_vpid();
6811
6812         /*
6813          * If PML is turned on, failure on enabling PML just results in failure
6814          * of creating the vcpu, therefore we can simplify PML logic (by
6815          * avoiding dealing with cases, such as enabling PML partially on vcpus
6816          * for the guest), etc.
6817          */
6818         if (enable_pml) {
6819                 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
6820                 if (!vmx->pml_pg)
6821                         goto free_vpid;
6822         }
6823
6824         for (i = 0; i < kvm_nr_uret_msrs; ++i) {
6825                 vmx->guest_uret_msrs[i].data = 0;
6826                 vmx->guest_uret_msrs[i].mask = -1ull;
6827         }
6828         if (boot_cpu_has(X86_FEATURE_RTM)) {
6829                 /*
6830                  * TSX_CTRL_CPUID_CLEAR is handled in the CPUID interception.
6831                  * Keep the host value unchanged to avoid changing CPUID bits
6832                  * under the host kernel's feet.
6833                  */
6834                 tsx_ctrl = vmx_find_uret_msr(vmx, MSR_IA32_TSX_CTRL);
6835                 if (tsx_ctrl)
6836                         vmx->guest_uret_msrs[i].mask = ~(u64)TSX_CTRL_CPUID_CLEAR;
6837         }
6838
6839         err = alloc_loaded_vmcs(&vmx->vmcs01);
6840         if (err < 0)
6841                 goto free_pml;
6842
6843         /* The MSR bitmap starts with all ones */
6844         bitmap_fill(vmx->shadow_msr_intercept.read, MAX_POSSIBLE_PASSTHROUGH_MSRS);
6845         bitmap_fill(vmx->shadow_msr_intercept.write, MAX_POSSIBLE_PASSTHROUGH_MSRS);
6846
6847         vmx_disable_intercept_for_msr(vcpu, MSR_IA32_TSC, MSR_TYPE_R);
6848 #ifdef CONFIG_X86_64
6849         vmx_disable_intercept_for_msr(vcpu, MSR_FS_BASE, MSR_TYPE_RW);
6850         vmx_disable_intercept_for_msr(vcpu, MSR_GS_BASE, MSR_TYPE_RW);
6851         vmx_disable_intercept_for_msr(vcpu, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6852 #endif
6853         vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6854         vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6855         vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
6856         if (kvm_cstate_in_guest(vcpu->kvm)) {
6857                 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C1_RES, MSR_TYPE_R);
6858                 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6859                 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6860                 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6861         }
6862
6863         vmx->loaded_vmcs = &vmx->vmcs01;
6864         cpu = get_cpu();
6865         vmx_vcpu_load(vcpu, cpu);
6866         vcpu->cpu = cpu;
6867         init_vmcs(vmx);
6868         vmx_vcpu_put(vcpu);
6869         put_cpu();
6870         if (cpu_need_virtualize_apic_accesses(vcpu)) {
6871                 err = alloc_apic_access_page(vcpu->kvm);
6872                 if (err)
6873                         goto free_vmcs;
6874         }
6875
6876         if (enable_ept && !enable_unrestricted_guest) {
6877                 err = init_rmode_identity_map(vcpu->kvm);
6878                 if (err)
6879                         goto free_vmcs;
6880         }
6881
6882         if (nested)
6883                 memcpy(&vmx->nested.msrs, &vmcs_config.nested, sizeof(vmx->nested.msrs));
6884         else
6885                 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
6886
6887         vcpu_setup_sgx_lepubkeyhash(vcpu);
6888
6889         vmx->nested.posted_intr_nv = -1;
6890         vmx->nested.current_vmptr = -1ull;
6891         vmx->nested.hv_evmcs_vmptr = EVMPTR_INVALID;
6892
6893         vcpu->arch.microcode_version = 0x100000000ULL;
6894         vmx->msr_ia32_feature_control_valid_bits = FEAT_CTL_LOCKED;
6895
6896         /*
6897          * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
6898          * or POSTED_INTR_WAKEUP_VECTOR.
6899          */
6900         vmx->pi_desc.nv = POSTED_INTR_VECTOR;
6901         vmx->pi_desc.sn = 1;
6902
6903         return 0;
6904
6905 free_vmcs:
6906         free_loaded_vmcs(vmx->loaded_vmcs);
6907 free_pml:
6908         vmx_destroy_pml_buffer(vmx);
6909 free_vpid:
6910         free_vpid(vmx->vpid);
6911         return err;
6912 }
6913
6914 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6915 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6916
6917 static int vmx_vm_init(struct kvm *kvm)
6918 {
6919         if (!ple_gap)
6920                 kvm->arch.pause_in_guest = true;
6921
6922         if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6923                 switch (l1tf_mitigation) {
6924                 case L1TF_MITIGATION_OFF:
6925                 case L1TF_MITIGATION_FLUSH_NOWARN:
6926                         /* 'I explicitly don't care' is set */
6927                         break;
6928                 case L1TF_MITIGATION_FLUSH:
6929                 case L1TF_MITIGATION_FLUSH_NOSMT:
6930                 case L1TF_MITIGATION_FULL:
6931                         /*
6932                          * Warn upon starting the first VM in a potentially
6933                          * insecure environment.
6934                          */
6935                         if (sched_smt_active())
6936                                 pr_warn_once(L1TF_MSG_SMT);
6937                         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6938                                 pr_warn_once(L1TF_MSG_L1D);
6939                         break;
6940                 case L1TF_MITIGATION_FULL_FORCE:
6941                         /* Flush is enforced */
6942                         break;
6943                 }
6944         }
6945         return 0;
6946 }
6947
6948 static int __init vmx_check_processor_compat(void)
6949 {
6950         struct vmcs_config vmcs_conf;
6951         struct vmx_capability vmx_cap;
6952
6953         if (!this_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
6954             !this_cpu_has(X86_FEATURE_VMX)) {
6955                 pr_err("kvm: VMX is disabled on CPU %d\n", smp_processor_id());
6956                 return -EIO;
6957         }
6958
6959         if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
6960                 return -EIO;
6961         if (nested)
6962                 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept);
6963         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6964                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6965                                 smp_processor_id());
6966                 return -EIO;
6967         }
6968         return 0;
6969 }
6970
6971 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6972 {
6973         u8 cache;
6974         u64 ipat = 0;
6975
6976         /* We wanted to honor guest CD/MTRR/PAT, but doing so could result in
6977          * memory aliases with conflicting memory types and sometimes MCEs.
6978          * We have to be careful as to what are honored and when.
6979          *
6980          * For MMIO, guest CD/MTRR are ignored.  The EPT memory type is set to
6981          * UC.  The effective memory type is UC or WC depending on guest PAT.
6982          * This was historically the source of MCEs and we want to be
6983          * conservative.
6984          *
6985          * When there is no need to deal with noncoherent DMA (e.g., no VT-d
6986          * or VT-d has snoop control), guest CD/MTRR/PAT are all ignored.  The
6987          * EPT memory type is set to WB.  The effective memory type is forced
6988          * WB.
6989          *
6990          * Otherwise, we trust guest.  Guest CD/MTRR/PAT are all honored.  The
6991          * EPT memory type is used to emulate guest CD/MTRR.
6992          */
6993
6994         if (is_mmio) {
6995                 cache = MTRR_TYPE_UNCACHABLE;
6996                 goto exit;
6997         }
6998
6999         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
7000                 ipat = VMX_EPT_IPAT_BIT;
7001                 cache = MTRR_TYPE_WRBACK;
7002                 goto exit;
7003         }
7004
7005         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
7006                 ipat = VMX_EPT_IPAT_BIT;
7007                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
7008                         cache = MTRR_TYPE_WRBACK;
7009                 else
7010                         cache = MTRR_TYPE_UNCACHABLE;
7011                 goto exit;
7012         }
7013
7014         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
7015
7016 exit:
7017         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
7018 }
7019
7020 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx, u32 new_ctl)
7021 {
7022         /*
7023          * These bits in the secondary execution controls field
7024          * are dynamic, the others are mostly based on the hypervisor
7025          * architecture and the guest's CPUID.  Do not touch the
7026          * dynamic bits.
7027          */
7028         u32 mask =
7029                 SECONDARY_EXEC_SHADOW_VMCS |
7030                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
7031                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
7032                 SECONDARY_EXEC_DESC;
7033
7034         u32 cur_ctl = secondary_exec_controls_get(vmx);
7035
7036         secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
7037 }
7038
7039 /*
7040  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
7041  * (indicating "allowed-1") if they are supported in the guest's CPUID.
7042  */
7043 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
7044 {
7045         struct vcpu_vmx *vmx = to_vmx(vcpu);
7046         struct kvm_cpuid_entry2 *entry;
7047
7048         vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
7049         vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
7050
7051 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
7052         if (entry && (entry->_reg & (_cpuid_mask)))                     \
7053                 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask);     \
7054 } while (0)
7055
7056         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
7057         cr4_fixed1_update(X86_CR4_VME,        edx, feature_bit(VME));
7058         cr4_fixed1_update(X86_CR4_PVI,        edx, feature_bit(VME));
7059         cr4_fixed1_update(X86_CR4_TSD,        edx, feature_bit(TSC));
7060         cr4_fixed1_update(X86_CR4_DE,         edx, feature_bit(DE));
7061         cr4_fixed1_update(X86_CR4_PSE,        edx, feature_bit(PSE));
7062         cr4_fixed1_update(X86_CR4_PAE,        edx, feature_bit(PAE));
7063         cr4_fixed1_update(X86_CR4_MCE,        edx, feature_bit(MCE));
7064         cr4_fixed1_update(X86_CR4_PGE,        edx, feature_bit(PGE));
7065         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, feature_bit(FXSR));
7066         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, feature_bit(XMM));
7067         cr4_fixed1_update(X86_CR4_VMXE,       ecx, feature_bit(VMX));
7068         cr4_fixed1_update(X86_CR4_SMXE,       ecx, feature_bit(SMX));
7069         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, feature_bit(PCID));
7070         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, feature_bit(XSAVE));
7071
7072         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7073         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, feature_bit(FSGSBASE));
7074         cr4_fixed1_update(X86_CR4_SMEP,       ebx, feature_bit(SMEP));
7075         cr4_fixed1_update(X86_CR4_SMAP,       ebx, feature_bit(SMAP));
7076         cr4_fixed1_update(X86_CR4_PKE,        ecx, feature_bit(PKU));
7077         cr4_fixed1_update(X86_CR4_UMIP,       ecx, feature_bit(UMIP));
7078         cr4_fixed1_update(X86_CR4_LA57,       ecx, feature_bit(LA57));
7079
7080 #undef cr4_fixed1_update
7081 }
7082
7083 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
7084 {
7085         struct vcpu_vmx *vmx = to_vmx(vcpu);
7086
7087         if (kvm_mpx_supported()) {
7088                 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
7089
7090                 if (mpx_enabled) {
7091                         vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
7092                         vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
7093                 } else {
7094                         vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
7095                         vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
7096                 }
7097         }
7098 }
7099
7100 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
7101 {
7102         struct vcpu_vmx *vmx = to_vmx(vcpu);
7103         struct kvm_cpuid_entry2 *best = NULL;
7104         int i;
7105
7106         for (i = 0; i < PT_CPUID_LEAVES; i++) {
7107                 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
7108                 if (!best)
7109                         return;
7110                 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
7111                 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
7112                 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
7113                 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
7114         }
7115
7116         /* Get the number of configurable Address Ranges for filtering */
7117         vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
7118                                                 PT_CAP_num_address_ranges);
7119
7120         /* Initialize and clear the no dependency bits */
7121         vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
7122                         RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
7123
7124         /*
7125          * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
7126          * will inject an #GP
7127          */
7128         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
7129                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
7130
7131         /*
7132          * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
7133          * PSBFreq can be set
7134          */
7135         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
7136                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
7137                                 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
7138
7139         /*
7140          * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
7141          * MTCFreq can be set
7142          */
7143         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
7144                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
7145                                 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
7146
7147         /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
7148         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
7149                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
7150                                                         RTIT_CTL_PTW_EN);
7151
7152         /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7153         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
7154                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
7155
7156         /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7157         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
7158                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
7159
7160         /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabricEn can be set */
7161         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
7162                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
7163
7164         /* unmask address range configure area */
7165         for (i = 0; i < vmx->pt_desc.addr_range; i++)
7166                 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
7167 }
7168
7169 static void vmx_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
7170 {
7171         struct vcpu_vmx *vmx = to_vmx(vcpu);
7172
7173         /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */
7174         vcpu->arch.xsaves_enabled = false;
7175
7176         vmx_setup_uret_msrs(vmx);
7177
7178         if (cpu_has_secondary_exec_ctrls())
7179                 vmcs_set_secondary_exec_control(vmx,
7180                                                 vmx_secondary_exec_control(vmx));
7181
7182         if (nested_vmx_allowed(vcpu))
7183                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7184                         FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7185                         FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX;
7186         else
7187                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7188                         ~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7189                           FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX);
7190
7191         if (nested_vmx_allowed(vcpu)) {
7192                 nested_vmx_cr_fixed1_bits_update(vcpu);
7193                 nested_vmx_entry_exit_ctls_update(vcpu);
7194         }
7195
7196         if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7197                         guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7198                 update_intel_pt_cfg(vcpu);
7199
7200         if (boot_cpu_has(X86_FEATURE_RTM)) {
7201                 struct vmx_uret_msr *msr;
7202                 msr = vmx_find_uret_msr(vmx, MSR_IA32_TSX_CTRL);
7203                 if (msr) {
7204                         bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM);
7205                         vmx_set_guest_uret_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE);
7206                 }
7207         }
7208
7209         set_cr4_guest_host_mask(vmx);
7210
7211         vmx_write_encls_bitmap(vcpu, NULL);
7212         if (guest_cpuid_has(vcpu, X86_FEATURE_SGX))
7213                 vmx->msr_ia32_feature_control_valid_bits |= FEAT_CTL_SGX_ENABLED;
7214         else
7215                 vmx->msr_ia32_feature_control_valid_bits &= ~FEAT_CTL_SGX_ENABLED;
7216
7217         if (guest_cpuid_has(vcpu, X86_FEATURE_SGX_LC))
7218                 vmx->msr_ia32_feature_control_valid_bits |=
7219                         FEAT_CTL_SGX_LC_ENABLED;
7220         else
7221                 vmx->msr_ia32_feature_control_valid_bits &=
7222                         ~FEAT_CTL_SGX_LC_ENABLED;
7223
7224         /* Refresh #PF interception to account for MAXPHYADDR changes. */
7225         vmx_update_exception_bitmap(vcpu);
7226 }
7227
7228 static __init void vmx_set_cpu_caps(void)
7229 {
7230         kvm_set_cpu_caps();
7231
7232         /* CPUID 0x1 */
7233         if (nested)
7234                 kvm_cpu_cap_set(X86_FEATURE_VMX);
7235
7236         /* CPUID 0x7 */
7237         if (kvm_mpx_supported())
7238                 kvm_cpu_cap_check_and_set(X86_FEATURE_MPX);
7239         if (!cpu_has_vmx_invpcid())
7240                 kvm_cpu_cap_clear(X86_FEATURE_INVPCID);
7241         if (vmx_pt_mode_is_host_guest())
7242                 kvm_cpu_cap_check_and_set(X86_FEATURE_INTEL_PT);
7243
7244         if (!enable_sgx) {
7245                 kvm_cpu_cap_clear(X86_FEATURE_SGX);
7246                 kvm_cpu_cap_clear(X86_FEATURE_SGX_LC);
7247                 kvm_cpu_cap_clear(X86_FEATURE_SGX1);
7248                 kvm_cpu_cap_clear(X86_FEATURE_SGX2);
7249         }
7250
7251         if (vmx_umip_emulated())
7252                 kvm_cpu_cap_set(X86_FEATURE_UMIP);
7253
7254         /* CPUID 0xD.1 */
7255         supported_xss = 0;
7256         if (!cpu_has_vmx_xsaves())
7257                 kvm_cpu_cap_clear(X86_FEATURE_XSAVES);
7258
7259         /* CPUID 0x80000001 and 0x7 (RDPID) */
7260         if (!cpu_has_vmx_rdtscp()) {
7261                 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP);
7262                 kvm_cpu_cap_clear(X86_FEATURE_RDPID);
7263         }
7264
7265         if (cpu_has_vmx_waitpkg())
7266                 kvm_cpu_cap_check_and_set(X86_FEATURE_WAITPKG);
7267 }
7268
7269 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
7270 {
7271         to_vmx(vcpu)->req_immediate_exit = true;
7272 }
7273
7274 static int vmx_check_intercept_io(struct kvm_vcpu *vcpu,
7275                                   struct x86_instruction_info *info)
7276 {
7277         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7278         unsigned short port;
7279         bool intercept;
7280         int size;
7281
7282         if (info->intercept == x86_intercept_in ||
7283             info->intercept == x86_intercept_ins) {
7284                 port = info->src_val;
7285                 size = info->dst_bytes;
7286         } else {
7287                 port = info->dst_val;
7288                 size = info->src_bytes;
7289         }
7290
7291         /*
7292          * If the 'use IO bitmaps' VM-execution control is 0, IO instruction
7293          * VM-exits depend on the 'unconditional IO exiting' VM-execution
7294          * control.
7295          *
7296          * Otherwise, IO instruction VM-exits are controlled by the IO bitmaps.
7297          */
7298         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7299                 intercept = nested_cpu_has(vmcs12,
7300                                            CPU_BASED_UNCOND_IO_EXITING);
7301         else
7302                 intercept = nested_vmx_check_io_bitmaps(vcpu, port, size);
7303
7304         /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED.  */
7305         return intercept ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE;
7306 }
7307
7308 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7309                                struct x86_instruction_info *info,
7310                                enum x86_intercept_stage stage,
7311                                struct x86_exception *exception)
7312 {
7313         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7314
7315         switch (info->intercept) {
7316         /*
7317          * RDPID causes #UD if disabled through secondary execution controls.
7318          * Because it is marked as EmulateOnUD, we need to intercept it here.
7319          * Note, RDPID is hidden behind ENABLE_RDTSCP.
7320          */
7321         case x86_intercept_rdpid:
7322                 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_RDTSCP)) {
7323                         exception->vector = UD_VECTOR;
7324                         exception->error_code_valid = false;
7325                         return X86EMUL_PROPAGATE_FAULT;
7326                 }
7327                 break;
7328
7329         case x86_intercept_in:
7330         case x86_intercept_ins:
7331         case x86_intercept_out:
7332         case x86_intercept_outs:
7333                 return vmx_check_intercept_io(vcpu, info);
7334
7335         case x86_intercept_lgdt:
7336         case x86_intercept_lidt:
7337         case x86_intercept_lldt:
7338         case x86_intercept_ltr:
7339         case x86_intercept_sgdt:
7340         case x86_intercept_sidt:
7341         case x86_intercept_sldt:
7342         case x86_intercept_str:
7343                 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC))
7344                         return X86EMUL_CONTINUE;
7345
7346                 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED.  */
7347                 break;
7348
7349         /* TODO: check more intercepts... */
7350         default:
7351                 break;
7352         }
7353
7354         return X86EMUL_UNHANDLEABLE;
7355 }
7356
7357 #ifdef CONFIG_X86_64
7358 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7359 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7360                                   u64 divisor, u64 *result)
7361 {
7362         u64 low = a << shift, high = a >> (64 - shift);
7363
7364         /* To avoid the overflow on divq */
7365         if (high >= divisor)
7366                 return 1;
7367
7368         /* Low hold the result, high hold rem which is discarded */
7369         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7370             "rm" (divisor), "0" (low), "1" (high));
7371         *result = low;
7372
7373         return 0;
7374 }
7375
7376 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7377                             bool *expired)
7378 {
7379         struct vcpu_vmx *vmx;
7380         u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
7381         struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
7382
7383         vmx = to_vmx(vcpu);
7384         tscl = rdtsc();
7385         guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7386         delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
7387         lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7388                                                     ktimer->timer_advance_ns);
7389
7390         if (delta_tsc > lapic_timer_advance_cycles)
7391                 delta_tsc -= lapic_timer_advance_cycles;
7392         else
7393                 delta_tsc = 0;
7394
7395         /* Convert to host delta tsc if tsc scaling is enabled */
7396         if (vcpu->arch.l1_tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
7397             delta_tsc && u64_shl_div_u64(delta_tsc,
7398                                 kvm_tsc_scaling_ratio_frac_bits,
7399                                 vcpu->arch.l1_tsc_scaling_ratio, &delta_tsc))
7400                 return -ERANGE;
7401
7402         /*
7403          * If the delta tsc can't fit in the 32 bit after the multi shift,
7404          * we can't use the preemption timer.
7405          * It's possible that it fits on later vmentries, but checking
7406          * on every vmentry is costly so we just use an hrtimer.
7407          */
7408         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7409                 return -ERANGE;
7410
7411         vmx->hv_deadline_tsc = tscl + delta_tsc;
7412         *expired = !delta_tsc;
7413         return 0;
7414 }
7415
7416 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7417 {
7418         to_vmx(vcpu)->hv_deadline_tsc = -1;
7419 }
7420 #endif
7421
7422 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
7423 {
7424         if (!kvm_pause_in_guest(vcpu->kvm))
7425                 shrink_ple_window(vcpu);
7426 }
7427
7428 void vmx_update_cpu_dirty_logging(struct kvm_vcpu *vcpu)
7429 {
7430         struct vcpu_vmx *vmx = to_vmx(vcpu);
7431
7432         if (is_guest_mode(vcpu)) {
7433                 vmx->nested.update_vmcs01_cpu_dirty_logging = true;
7434                 return;
7435         }
7436
7437         /*
7438          * Note, cpu_dirty_logging_count can be changed concurrent with this
7439          * code, but in that case another update request will be made and so
7440          * the guest will never run with a stale PML value.
7441          */
7442         if (vcpu->kvm->arch.cpu_dirty_logging_count)
7443                 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_ENABLE_PML);
7444         else
7445                 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_ENABLE_PML);
7446 }
7447
7448 static int vmx_pre_block(struct kvm_vcpu *vcpu)
7449 {
7450         if (pi_pre_block(vcpu))
7451                 return 1;
7452
7453         if (kvm_lapic_hv_timer_in_use(vcpu))
7454                 kvm_lapic_switch_to_sw_timer(vcpu);
7455
7456         return 0;
7457 }
7458
7459 static void vmx_post_block(struct kvm_vcpu *vcpu)
7460 {
7461         if (kvm_x86_ops.set_hv_timer)
7462                 kvm_lapic_switch_to_hv_timer(vcpu);
7463
7464         pi_post_block(vcpu);
7465 }
7466
7467 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7468 {
7469         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7470                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7471                         FEAT_CTL_LMCE_ENABLED;
7472         else
7473                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7474                         ~FEAT_CTL_LMCE_ENABLED;
7475 }
7476
7477 static int vmx_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
7478 {
7479         /* we need a nested vmexit to enter SMM, postpone if run is pending */
7480         if (to_vmx(vcpu)->nested.nested_run_pending)
7481                 return -EBUSY;
7482         return !is_smm(vcpu);
7483 }
7484
7485 static int vmx_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7486 {
7487         struct vcpu_vmx *vmx = to_vmx(vcpu);
7488
7489         vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7490         if (vmx->nested.smm.guest_mode)
7491                 nested_vmx_vmexit(vcpu, -1, 0, 0);
7492
7493         vmx->nested.smm.vmxon = vmx->nested.vmxon;
7494         vmx->nested.vmxon = false;
7495         vmx_clear_hlt(vcpu);
7496         return 0;
7497 }
7498
7499 static int vmx_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
7500 {
7501         struct vcpu_vmx *vmx = to_vmx(vcpu);
7502         int ret;
7503
7504         if (vmx->nested.smm.vmxon) {
7505                 vmx->nested.vmxon = true;
7506                 vmx->nested.smm.vmxon = false;
7507         }
7508
7509         if (vmx->nested.smm.guest_mode) {
7510                 ret = nested_vmx_enter_non_root_mode(vcpu, false);
7511                 if (ret)
7512                         return ret;
7513
7514                 vmx->nested.smm.guest_mode = false;
7515         }
7516         return 0;
7517 }
7518
7519 static void vmx_enable_smi_window(struct kvm_vcpu *vcpu)
7520 {
7521         /* RSM will cause a vmexit anyway.  */
7522 }
7523
7524 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7525 {
7526         return to_vmx(vcpu)->nested.vmxon && !is_guest_mode(vcpu);
7527 }
7528
7529 static void vmx_migrate_timers(struct kvm_vcpu *vcpu)
7530 {
7531         if (is_guest_mode(vcpu)) {
7532                 struct hrtimer *timer = &to_vmx(vcpu)->nested.preemption_timer;
7533
7534                 if (hrtimer_try_to_cancel(timer) == 1)
7535                         hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED);
7536         }
7537 }
7538
7539 static void hardware_unsetup(void)
7540 {
7541         if (nested)
7542                 nested_vmx_hardware_unsetup();
7543
7544         free_kvm_area();
7545 }
7546
7547 static bool vmx_check_apicv_inhibit_reasons(ulong bit)
7548 {
7549         ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) |
7550                           BIT(APICV_INHIBIT_REASON_HYPERV);
7551
7552         return supported & BIT(bit);
7553 }
7554
7555 static struct kvm_x86_ops vmx_x86_ops __initdata = {
7556         .hardware_unsetup = hardware_unsetup,
7557
7558         .hardware_enable = hardware_enable,
7559         .hardware_disable = hardware_disable,
7560         .cpu_has_accelerated_tpr = report_flexpriority,
7561         .has_emulated_msr = vmx_has_emulated_msr,
7562
7563         .vm_size = sizeof(struct kvm_vmx),
7564         .vm_init = vmx_vm_init,
7565
7566         .vcpu_create = vmx_create_vcpu,
7567         .vcpu_free = vmx_free_vcpu,
7568         .vcpu_reset = vmx_vcpu_reset,
7569
7570         .prepare_guest_switch = vmx_prepare_switch_to_guest,
7571         .vcpu_load = vmx_vcpu_load,
7572         .vcpu_put = vmx_vcpu_put,
7573
7574         .update_exception_bitmap = vmx_update_exception_bitmap,
7575         .get_msr_feature = vmx_get_msr_feature,
7576         .get_msr = vmx_get_msr,
7577         .set_msr = vmx_set_msr,
7578         .get_segment_base = vmx_get_segment_base,
7579         .get_segment = vmx_get_segment,
7580         .set_segment = vmx_set_segment,
7581         .get_cpl = vmx_get_cpl,
7582         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7583         .set_cr0 = vmx_set_cr0,
7584         .is_valid_cr4 = vmx_is_valid_cr4,
7585         .set_cr4 = vmx_set_cr4,
7586         .set_efer = vmx_set_efer,
7587         .get_idt = vmx_get_idt,
7588         .set_idt = vmx_set_idt,
7589         .get_gdt = vmx_get_gdt,
7590         .set_gdt = vmx_set_gdt,
7591         .set_dr7 = vmx_set_dr7,
7592         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
7593         .cache_reg = vmx_cache_reg,
7594         .get_rflags = vmx_get_rflags,
7595         .set_rflags = vmx_set_rflags,
7596
7597         .tlb_flush_all = vmx_flush_tlb_all,
7598         .tlb_flush_current = vmx_flush_tlb_current,
7599         .tlb_flush_gva = vmx_flush_tlb_gva,
7600         .tlb_flush_guest = vmx_flush_tlb_guest,
7601
7602         .run = vmx_vcpu_run,
7603         .handle_exit = vmx_handle_exit,
7604         .skip_emulated_instruction = vmx_skip_emulated_instruction,
7605         .update_emulated_instruction = vmx_update_emulated_instruction,
7606         .set_interrupt_shadow = vmx_set_interrupt_shadow,
7607         .get_interrupt_shadow = vmx_get_interrupt_shadow,
7608         .patch_hypercall = vmx_patch_hypercall,
7609         .set_irq = vmx_inject_irq,
7610         .set_nmi = vmx_inject_nmi,
7611         .queue_exception = vmx_queue_exception,
7612         .cancel_injection = vmx_cancel_injection,
7613         .interrupt_allowed = vmx_interrupt_allowed,
7614         .nmi_allowed = vmx_nmi_allowed,
7615         .get_nmi_mask = vmx_get_nmi_mask,
7616         .set_nmi_mask = vmx_set_nmi_mask,
7617         .enable_nmi_window = vmx_enable_nmi_window,
7618         .enable_irq_window = vmx_enable_irq_window,
7619         .update_cr8_intercept = vmx_update_cr8_intercept,
7620         .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
7621         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
7622         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
7623         .load_eoi_exitmap = vmx_load_eoi_exitmap,
7624         .apicv_post_state_restore = vmx_apicv_post_state_restore,
7625         .check_apicv_inhibit_reasons = vmx_check_apicv_inhibit_reasons,
7626         .hwapic_irr_update = vmx_hwapic_irr_update,
7627         .hwapic_isr_update = vmx_hwapic_isr_update,
7628         .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
7629         .sync_pir_to_irr = vmx_sync_pir_to_irr,
7630         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
7631         .dy_apicv_has_pending_interrupt = pi_has_pending_interrupt,
7632
7633         .set_tss_addr = vmx_set_tss_addr,
7634         .set_identity_map_addr = vmx_set_identity_map_addr,
7635         .get_mt_mask = vmx_get_mt_mask,
7636
7637         .get_exit_info = vmx_get_exit_info,
7638
7639         .vcpu_after_set_cpuid = vmx_vcpu_after_set_cpuid,
7640
7641         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7642
7643         .get_l2_tsc_offset = vmx_get_l2_tsc_offset,
7644         .get_l2_tsc_multiplier = vmx_get_l2_tsc_multiplier,
7645         .write_tsc_offset = vmx_write_tsc_offset,
7646         .write_tsc_multiplier = vmx_write_tsc_multiplier,
7647
7648         .load_mmu_pgd = vmx_load_mmu_pgd,
7649
7650         .check_intercept = vmx_check_intercept,
7651         .handle_exit_irqoff = vmx_handle_exit_irqoff,
7652
7653         .request_immediate_exit = vmx_request_immediate_exit,
7654
7655         .sched_in = vmx_sched_in,
7656
7657         .cpu_dirty_log_size = PML_ENTITY_NUM,
7658         .update_cpu_dirty_logging = vmx_update_cpu_dirty_logging,
7659
7660         .pre_block = vmx_pre_block,
7661         .post_block = vmx_post_block,
7662
7663         .pmu_ops = &intel_pmu_ops,
7664         .nested_ops = &vmx_nested_ops,
7665
7666         .update_pi_irte = pi_update_irte,
7667         .start_assignment = vmx_pi_start_assignment,
7668
7669 #ifdef CONFIG_X86_64
7670         .set_hv_timer = vmx_set_hv_timer,
7671         .cancel_hv_timer = vmx_cancel_hv_timer,
7672 #endif
7673
7674         .setup_mce = vmx_setup_mce,
7675
7676         .smi_allowed = vmx_smi_allowed,
7677         .enter_smm = vmx_enter_smm,
7678         .leave_smm = vmx_leave_smm,
7679         .enable_smi_window = vmx_enable_smi_window,
7680
7681         .can_emulate_instruction = vmx_can_emulate_instruction,
7682         .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
7683         .migrate_timers = vmx_migrate_timers,
7684
7685         .msr_filter_changed = vmx_msr_filter_changed,
7686         .complete_emulated_msr = kvm_complete_insn_gp,
7687
7688         .vcpu_deliver_sipi_vector = kvm_vcpu_deliver_sipi_vector,
7689 };
7690
7691 static __init void vmx_setup_user_return_msrs(void)
7692 {
7693
7694         /*
7695          * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
7696          * will emulate SYSCALL in legacy mode if the vendor string in guest
7697          * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
7698          * support this emulation, MSR_STAR is included in the list for i386,
7699          * but is never loaded into hardware.  MSR_CSTAR is also never loaded
7700          * into hardware and is here purely for emulation purposes.
7701          */
7702         const u32 vmx_uret_msrs_list[] = {
7703         #ifdef CONFIG_X86_64
7704                 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
7705         #endif
7706                 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
7707                 MSR_IA32_TSX_CTRL,
7708         };
7709         int i;
7710
7711         BUILD_BUG_ON(ARRAY_SIZE(vmx_uret_msrs_list) != MAX_NR_USER_RETURN_MSRS);
7712
7713         for (i = 0; i < ARRAY_SIZE(vmx_uret_msrs_list); ++i)
7714                 kvm_add_user_return_msr(vmx_uret_msrs_list[i]);
7715 }
7716
7717 static __init int hardware_setup(void)
7718 {
7719         unsigned long host_bndcfgs;
7720         struct desc_ptr dt;
7721         int r, ept_lpage_level;
7722
7723         store_idt(&dt);
7724         host_idt_base = dt.address;
7725
7726         vmx_setup_user_return_msrs();
7727
7728         if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7729                 return -EIO;
7730
7731         if (boot_cpu_has(X86_FEATURE_NX))
7732                 kvm_enable_efer_bits(EFER_NX);
7733
7734         if (boot_cpu_has(X86_FEATURE_MPX)) {
7735                 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7736                 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7737         }
7738
7739         if (!cpu_has_vmx_mpx())
7740                 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS |
7741                                     XFEATURE_MASK_BNDCSR);
7742
7743         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7744             !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7745                 enable_vpid = 0;
7746
7747         if (!cpu_has_vmx_ept() ||
7748             !cpu_has_vmx_ept_4levels() ||
7749             !cpu_has_vmx_ept_mt_wb() ||
7750             !cpu_has_vmx_invept_global())
7751                 enable_ept = 0;
7752
7753         /* NX support is required for shadow paging. */
7754         if (!enable_ept && !boot_cpu_has(X86_FEATURE_NX)) {
7755                 pr_err_ratelimited("kvm: NX (Execute Disable) not supported\n");
7756                 return -EOPNOTSUPP;
7757         }
7758
7759         if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7760                 enable_ept_ad_bits = 0;
7761
7762         if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7763                 enable_unrestricted_guest = 0;
7764
7765         if (!cpu_has_vmx_flexpriority())
7766                 flexpriority_enabled = 0;
7767
7768         if (!cpu_has_virtual_nmis())
7769                 enable_vnmi = 0;
7770
7771         /*
7772          * set_apic_access_page_addr() is used to reload apic access
7773          * page upon invalidation.  No need to do anything if not
7774          * using the APIC_ACCESS_ADDR VMCS field.
7775          */
7776         if (!flexpriority_enabled)
7777                 vmx_x86_ops.set_apic_access_page_addr = NULL;
7778
7779         if (!cpu_has_vmx_tpr_shadow())
7780                 vmx_x86_ops.update_cr8_intercept = NULL;
7781
7782 #if IS_ENABLED(CONFIG_HYPERV)
7783         if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7784             && enable_ept) {
7785                 vmx_x86_ops.tlb_remote_flush = hv_remote_flush_tlb;
7786                 vmx_x86_ops.tlb_remote_flush_with_range =
7787                                 hv_remote_flush_tlb_with_range;
7788         }
7789 #endif
7790
7791         if (!cpu_has_vmx_ple()) {
7792                 ple_gap = 0;
7793                 ple_window = 0;
7794                 ple_window_grow = 0;
7795                 ple_window_max = 0;
7796                 ple_window_shrink = 0;
7797         }
7798
7799         if (!cpu_has_vmx_apicv()) {
7800                 enable_apicv = 0;
7801                 vmx_x86_ops.sync_pir_to_irr = NULL;
7802         }
7803
7804         if (cpu_has_vmx_tsc_scaling()) {
7805                 kvm_has_tsc_control = true;
7806                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7807                 kvm_tsc_scaling_ratio_frac_bits = 48;
7808         }
7809
7810         kvm_has_bus_lock_exit = cpu_has_vmx_bus_lock_detection();
7811
7812         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7813
7814         if (enable_ept)
7815                 kvm_mmu_set_ept_masks(enable_ept_ad_bits,
7816                                       cpu_has_vmx_ept_execute_only());
7817
7818         if (!enable_ept)
7819                 ept_lpage_level = 0;
7820         else if (cpu_has_vmx_ept_1g_page())
7821                 ept_lpage_level = PG_LEVEL_1G;
7822         else if (cpu_has_vmx_ept_2m_page())
7823                 ept_lpage_level = PG_LEVEL_2M;
7824         else
7825                 ept_lpage_level = PG_LEVEL_4K;
7826         kvm_configure_mmu(enable_ept, 0, vmx_get_max_tdp_level(),
7827                           ept_lpage_level);
7828
7829         /*
7830          * Only enable PML when hardware supports PML feature, and both EPT
7831          * and EPT A/D bit features are enabled -- PML depends on them to work.
7832          */
7833         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7834                 enable_pml = 0;
7835
7836         if (!enable_pml)
7837                 vmx_x86_ops.cpu_dirty_log_size = 0;
7838
7839         if (!cpu_has_vmx_preemption_timer())
7840                 enable_preemption_timer = false;
7841
7842         if (enable_preemption_timer) {
7843                 u64 use_timer_freq = 5000ULL * 1000 * 1000;
7844                 u64 vmx_msr;
7845
7846                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7847                 cpu_preemption_timer_multi =
7848                         vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7849
7850                 if (tsc_khz)
7851                         use_timer_freq = (u64)tsc_khz * 1000;
7852                 use_timer_freq >>= cpu_preemption_timer_multi;
7853
7854                 /*
7855                  * KVM "disables" the preemption timer by setting it to its max
7856                  * value.  Don't use the timer if it might cause spurious exits
7857                  * at a rate faster than 0.1 Hz (of uninterrupted guest time).
7858                  */
7859                 if (use_timer_freq > 0xffffffffu / 10)
7860                         enable_preemption_timer = false;
7861         }
7862
7863         if (!enable_preemption_timer) {
7864                 vmx_x86_ops.set_hv_timer = NULL;
7865                 vmx_x86_ops.cancel_hv_timer = NULL;
7866                 vmx_x86_ops.request_immediate_exit = __kvm_request_immediate_exit;
7867         }
7868
7869         kvm_set_posted_intr_wakeup_handler(pi_wakeup_handler);
7870
7871         kvm_mce_cap_supported |= MCG_LMCE_P;
7872
7873         if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
7874                 return -EINVAL;
7875         if (!enable_ept || !cpu_has_vmx_intel_pt())
7876                 pt_mode = PT_MODE_SYSTEM;
7877
7878         setup_default_sgx_lepubkeyhash();
7879
7880         if (nested) {
7881                 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
7882                                            vmx_capability.ept);
7883
7884                 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
7885                 if (r)
7886                         return r;
7887         }
7888
7889         vmx_set_cpu_caps();
7890
7891         r = alloc_kvm_area();
7892         if (r)
7893                 nested_vmx_hardware_unsetup();
7894         return r;
7895 }
7896
7897 static struct kvm_x86_init_ops vmx_init_ops __initdata = {
7898         .cpu_has_kvm_support = cpu_has_kvm_support,
7899         .disabled_by_bios = vmx_disabled_by_bios,
7900         .check_processor_compatibility = vmx_check_processor_compat,
7901         .hardware_setup = hardware_setup,
7902
7903         .runtime_ops = &vmx_x86_ops,
7904 };
7905
7906 static void vmx_cleanup_l1d_flush(void)
7907 {
7908         if (vmx_l1d_flush_pages) {
7909                 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
7910                 vmx_l1d_flush_pages = NULL;
7911         }
7912         /* Restore state so sysfs ignores VMX */
7913         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
7914 }
7915
7916 static void vmx_exit(void)
7917 {
7918 #ifdef CONFIG_KEXEC_CORE
7919         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
7920         synchronize_rcu();
7921 #endif
7922
7923         kvm_exit();
7924
7925 #if IS_ENABLED(CONFIG_HYPERV)
7926         if (static_branch_unlikely(&enable_evmcs)) {
7927                 int cpu;
7928                 struct hv_vp_assist_page *vp_ap;
7929                 /*
7930                  * Reset everything to support using non-enlightened VMCS
7931                  * access later (e.g. when we reload the module with
7932                  * enlightened_vmcs=0)
7933                  */
7934                 for_each_online_cpu(cpu) {
7935                         vp_ap = hv_get_vp_assist_page(cpu);
7936
7937                         if (!vp_ap)
7938                                 continue;
7939
7940                         vp_ap->nested_control.features.directhypercall = 0;
7941                         vp_ap->current_nested_vmcs = 0;
7942                         vp_ap->enlighten_vmentry = 0;
7943                 }
7944
7945                 static_branch_disable(&enable_evmcs);
7946         }
7947 #endif
7948         vmx_cleanup_l1d_flush();
7949
7950         allow_smaller_maxphyaddr = false;
7951 }
7952 module_exit(vmx_exit);
7953
7954 static int __init vmx_init(void)
7955 {
7956         int r, cpu;
7957
7958 #if IS_ENABLED(CONFIG_HYPERV)
7959         /*
7960          * Enlightened VMCS usage should be recommended and the host needs
7961          * to support eVMCS v1 or above. We can also disable eVMCS support
7962          * with module parameter.
7963          */
7964         if (enlightened_vmcs &&
7965             ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
7966             (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
7967             KVM_EVMCS_VERSION) {
7968                 int cpu;
7969
7970                 /* Check that we have assist pages on all online CPUs */
7971                 for_each_online_cpu(cpu) {
7972                         if (!hv_get_vp_assist_page(cpu)) {
7973                                 enlightened_vmcs = false;
7974                                 break;
7975                         }
7976                 }
7977
7978                 if (enlightened_vmcs) {
7979                         pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
7980                         static_branch_enable(&enable_evmcs);
7981                 }
7982
7983                 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
7984                         vmx_x86_ops.enable_direct_tlbflush
7985                                 = hv_enable_direct_tlbflush;
7986
7987         } else {
7988                 enlightened_vmcs = false;
7989         }
7990 #endif
7991
7992         r = kvm_init(&vmx_init_ops, sizeof(struct vcpu_vmx),
7993                      __alignof__(struct vcpu_vmx), THIS_MODULE);
7994         if (r)
7995                 return r;
7996
7997         /*
7998          * Must be called after kvm_init() so enable_ept is properly set
7999          * up. Hand the parameter mitigation value in which was stored in
8000          * the pre module init parser. If no parameter was given, it will
8001          * contain 'auto' which will be turned into the default 'cond'
8002          * mitigation mode.
8003          */
8004         r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
8005         if (r) {
8006                 vmx_exit();
8007                 return r;
8008         }
8009
8010         for_each_possible_cpu(cpu) {
8011                 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8012
8013                 pi_init_cpu(cpu);
8014         }
8015
8016 #ifdef CONFIG_KEXEC_CORE
8017         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8018                            crash_vmclear_local_loaded_vmcss);
8019 #endif
8020         vmx_check_vmcs12_offsets();
8021
8022         /*
8023          * Shadow paging doesn't have a (further) performance penalty
8024          * from GUEST_MAXPHYADDR < HOST_MAXPHYADDR so enable it
8025          * by default
8026          */
8027         if (!enable_ept)
8028                 allow_smaller_maxphyaddr = true;
8029
8030         return 0;
8031 }
8032 module_init(vmx_init);