arch/x86/kvm/vmx/nested.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   3
   4 #include <linux/objtool.h>
   5 #include <linux/percpu.h>
   6
   7 #include <asm/debugreg.h>
   8 #include <asm/mmu_context.h>
   9
  10 #include "cpuid.h"
  11 #include "hyperv.h"
  12 #include "mmu.h"
  13 #include "nested.h"
  14 #include "pmu.h"
  15 #include "sgx.h"
  16 #include "trace.h"
  17 #include "vmx.h"
  18 #include "x86.h"
  19 #include "smm.h"
  20
  21 static bool __read_mostly enable_shadow_vmcs = 1;
  22 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  23
  24 static bool __read_mostly nested_early_check = 0;
  25 module_param(nested_early_check, bool, S_IRUGO);
  26
  27 #define CC KVM_NESTED_VMENTER_CONSISTENCY_CHECK
  28
  29 /*
  30  * Hyper-V requires all of these, so mark them as supported even though
  31  * they are just treated the same as all-context.
  32  */
  33 #define VMX_VPID_EXTENT_SUPPORTED_MASK          \
  34         (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT |  \
  35         VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |    \
  36         VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT |    \
  37         VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
  38
  39 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
  40
  41 enum {
  42         VMX_VMREAD_BITMAP,
  43         VMX_VMWRITE_BITMAP,
  44         VMX_BITMAP_NR
  45 };
  46 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
  47
  48 #define vmx_vmread_bitmap                    (vmx_bitmap[VMX_VMREAD_BITMAP])
  49 #define vmx_vmwrite_bitmap                   (vmx_bitmap[VMX_VMWRITE_BITMAP])
  50
  51 struct shadow_vmcs_field {
  52         u16     encoding;
  53         u16     offset;
  54 };
  55 static struct shadow_vmcs_field shadow_read_only_fields[] = {
  56 #define SHADOW_FIELD_RO(x, y) { x, offsetof(struct vmcs12, y) },
  57 #include "vmcs_shadow_fields.h"
  58 };
  59 static int max_shadow_read_only_fields =
  60         ARRAY_SIZE(shadow_read_only_fields);
  61
  62 static struct shadow_vmcs_field shadow_read_write_fields[] = {
  63 #define SHADOW_FIELD_RW(x, y) { x, offsetof(struct vmcs12, y) },
  64 #include "vmcs_shadow_fields.h"
  65 };
  66 static int max_shadow_read_write_fields =
  67         ARRAY_SIZE(shadow_read_write_fields);
  68
  69 static void init_vmcs_shadow_fields(void)
  70 {
  71         int i, j;
  72
  73         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
  74         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
  75
  76         for (i = j = 0; i < max_shadow_read_only_fields; i++) {
  77                 struct shadow_vmcs_field entry = shadow_read_only_fields[i];
  78                 u16 field = entry.encoding;
  79
  80                 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
  81                     (i + 1 == max_shadow_read_only_fields ||
  82                      shadow_read_only_fields[i + 1].encoding != field + 1))
  83                         pr_err("Missing field from shadow_read_only_field %x\n",
  84                                field + 1);
  85
  86                 clear_bit(field, vmx_vmread_bitmap);
  87                 if (field & 1)
  88 #ifdef CONFIG_X86_64
  89                         continue;
  90 #else
  91                         entry.offset += sizeof(u32);
  92 #endif
  93                 shadow_read_only_fields[j++] = entry;
  94         }
  95         max_shadow_read_only_fields = j;
  96
  97         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
  98                 struct shadow_vmcs_field entry = shadow_read_write_fields[i];
  99                 u16 field = entry.encoding;
 100
 101                 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
 102                     (i + 1 == max_shadow_read_write_fields ||
 103                      shadow_read_write_fields[i + 1].encoding != field + 1))
 104                         pr_err("Missing field from shadow_read_write_field %x\n",
 105                                field + 1);
 106
 107                 WARN_ONCE(field >= GUEST_ES_AR_BYTES &&
 108                           field <= GUEST_TR_AR_BYTES,
 109                           "Update vmcs12_write_any() to drop reserved bits from AR_BYTES");
 110
 111                 /*
 112                  * PML and the preemption timer can be emulated, but the
 113                  * processor cannot vmwrite to fields that don't exist
 114                  * on bare metal.
 115                  */
 116                 switch (field) {
 117                 case GUEST_PML_INDEX:
 118                         if (!cpu_has_vmx_pml())
 119                                 continue;
 120                         break;
 121                 case VMX_PREEMPTION_TIMER_VALUE:
 122                         if (!cpu_has_vmx_preemption_timer())
 123                                 continue;
 124                         break;
 125                 case GUEST_INTR_STATUS:
 126                         if (!cpu_has_vmx_apicv())
 127                                 continue;
 128                         break;
 129                 default:
 130                         break;
 131                 }
 132
 133                 clear_bit(field, vmx_vmwrite_bitmap);
 134                 clear_bit(field, vmx_vmread_bitmap);
 135                 if (field & 1)
 136 #ifdef CONFIG_X86_64
 137                         continue;
 138 #else
 139                         entry.offset += sizeof(u32);
 140 #endif
 141                 shadow_read_write_fields[j++] = entry;
 142         }
 143         max_shadow_read_write_fields = j;
 144 }
 145
 146 /*
 147  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
 148  * set the success or error code of an emulated VMX instruction (as specified
 149  * by Vol 2B, VMX Instruction Reference, "Conventions"), and skip the emulated
 150  * instruction.
 151  */
 152 static int nested_vmx_succeed(struct kvm_vcpu *vcpu)
 153 {
 154         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
 155                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
 156                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
 157         return kvm_skip_emulated_instruction(vcpu);
 158 }
 159
 160 static int nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
 161 {
 162         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
 163                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
 164                             X86_EFLAGS_SF | X86_EFLAGS_OF))
 165                         | X86_EFLAGS_CF);
 166         return kvm_skip_emulated_instruction(vcpu);
 167 }
 168
 169 static int nested_vmx_failValid(struct kvm_vcpu *vcpu,
 170                                 u32 vm_instruction_error)
 171 {
 172         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
 173                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
 174                             X86_EFLAGS_SF | X86_EFLAGS_OF))
 175                         | X86_EFLAGS_ZF);
 176         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
 177         /*
 178          * We don't need to force sync to shadow VMCS because
 179          * VM_INSTRUCTION_ERROR is not shadowed. Enlightened VMCS 'shadows' all
 180          * fields and thus must be synced.
 181          */
 182         if (to_vmx(vcpu)->nested.hv_evmcs_vmptr != EVMPTR_INVALID)
 183                 to_vmx(vcpu)->nested.need_vmcs12_to_shadow_sync = true;
 184
 185         return kvm_skip_emulated_instruction(vcpu);
 186 }
 187
 188 static int nested_vmx_fail(struct kvm_vcpu *vcpu, u32 vm_instruction_error)
 189 {
 190         struct vcpu_vmx *vmx = to_vmx(vcpu);
 191
 192         /*
 193          * failValid writes the error number to the current VMCS, which
 194          * can't be done if there isn't a current VMCS.
 195          */
 196         if (vmx->nested.current_vmptr == INVALID_GPA &&
 197             !evmptr_is_valid(vmx->nested.hv_evmcs_vmptr))
 198                 return nested_vmx_failInvalid(vcpu);
 199
 200         return nested_vmx_failValid(vcpu, vm_instruction_error);
 201 }
 202
 203 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
 204 {
 205         /* TODO: not to reset guest simply here. */
 206         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
 207         pr_debug_ratelimited("nested vmx abort, indicator %d\n", indicator);
 208 }
 209
 210 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
 211 {
 212         return fixed_bits_valid(control, low, high);
 213 }
 214
 215 static inline u64 vmx_control_msr(u32 low, u32 high)
 216 {
 217         return low | ((u64)high << 32);
 218 }
 219
 220 static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx)
 221 {
 222         secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_SHADOW_VMCS);
 223         vmcs_write64(VMCS_LINK_POINTER, INVALID_GPA);
 224         vmx->nested.need_vmcs12_to_shadow_sync = false;
 225 }
 226
 227 static inline void nested_release_evmcs(struct kvm_vcpu *vcpu)
 228 {
 229         struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu);
 230         struct vcpu_vmx *vmx = to_vmx(vcpu);
 231
 232         if (evmptr_is_valid(vmx->nested.hv_evmcs_vmptr)) {
 233                 kvm_vcpu_unmap(vcpu, &vmx->nested.hv_evmcs_map, true);
 234                 vmx->nested.hv_evmcs = NULL;
 235         }
 236
 237         vmx->nested.hv_evmcs_vmptr = EVMPTR_INVALID;
 238
 239         if (hv_vcpu) {
 240                 hv_vcpu->nested.pa_page_gpa = INVALID_GPA;
 241                 hv_vcpu->nested.vm_id = 0;
 242                 hv_vcpu->nested.vp_id = 0;
 243         }
 244 }
 245
 246 static void vmx_sync_vmcs_host_state(struct vcpu_vmx *vmx,
 247                                      struct loaded_vmcs *prev)
 248 {
 249         struct vmcs_host_state *dest, *src;
 250
 251         if (unlikely(!vmx->guest_state_loaded))
 252                 return;
 253
 254         src = &prev->host_state;
 255         dest = &vmx->loaded_vmcs->host_state;
 256
 257         vmx_set_host_fs_gs(dest, src->fs_sel, src->gs_sel, src->fs_base, src->gs_base);
 258         dest->ldt_sel = src->ldt_sel;
 259 #ifdef CONFIG_X86_64
 260         dest->ds_sel = src->ds_sel;
 261         dest->es_sel = src->es_sel;
 262 #endif
 263 }
 264
 265 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
 266 {
 267         struct vcpu_vmx *vmx = to_vmx(vcpu);
 268         struct loaded_vmcs *prev;
 269         int cpu;
 270
 271         if (WARN_ON_ONCE(vmx->loaded_vmcs == vmcs))
 272                 return;
 273
 274         cpu = get_cpu();
 275         prev = vmx->loaded_vmcs;
 276         vmx->loaded_vmcs = vmcs;
 277         vmx_vcpu_load_vmcs(vcpu, cpu, prev);
 278         vmx_sync_vmcs_host_state(vmx, prev);
 279         put_cpu();
 280
 281         vcpu->arch.regs_avail = ~VMX_REGS_LAZY_LOAD_SET;
 282
 283         /*
 284          * All lazily updated registers will be reloaded from VMCS12 on both
 285          * vmentry and vmexit.
 286          */
 287         vcpu->arch.regs_dirty = 0;
 288 }
 289
 290 /*
 291  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
 292  * just stops using VMX.
 293  */
 294 static void free_nested(struct kvm_vcpu *vcpu)
 295 {
 296         struct vcpu_vmx *vmx = to_vmx(vcpu);
 297
 298         if (WARN_ON_ONCE(vmx->loaded_vmcs != &vmx->vmcs01))
 299                 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
 300
 301         if (!vmx->nested.vmxon && !vmx->nested.smm.vmxon)
 302                 return;
 303
 304         kvm_clear_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu);
 305
 306         vmx->nested.vmxon = false;
 307         vmx->nested.smm.vmxon = false;
 308         vmx->nested.vmxon_ptr = INVALID_GPA;
 309         free_vpid(vmx->nested.vpid02);
 310         vmx->nested.posted_intr_nv = -1;
 311         vmx->nested.current_vmptr = INVALID_GPA;
 312         if (enable_shadow_vmcs) {
 313                 vmx_disable_shadow_vmcs(vmx);
 314                 vmcs_clear(vmx->vmcs01.shadow_vmcs);
 315                 free_vmcs(vmx->vmcs01.shadow_vmcs);
 316                 vmx->vmcs01.shadow_vmcs = NULL;
 317         }
 318         kfree(vmx->nested.cached_vmcs12);
 319         vmx->nested.cached_vmcs12 = NULL;
 320         kfree(vmx->nested.cached_shadow_vmcs12);
 321         vmx->nested.cached_shadow_vmcs12 = NULL;
 322         /*
 323          * Unpin physical memory we referred to in the vmcs02.  The APIC access
 324          * page's backing page (yeah, confusing) shouldn't actually be accessed,
 325          * and if it is written, the contents are irrelevant.
 326          */
 327         kvm_vcpu_unmap(vcpu, &vmx->nested.apic_access_page_map, false);
 328         kvm_vcpu_unmap(vcpu, &vmx->nested.virtual_apic_map, true);
 329         kvm_vcpu_unmap(vcpu, &vmx->nested.pi_desc_map, true);
 330         vmx->nested.pi_desc = NULL;
 331
 332         kvm_mmu_free_roots(vcpu->kvm, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL);
 333
 334         nested_release_evmcs(vcpu);
 335
 336         free_loaded_vmcs(&vmx->nested.vmcs02);
 337 }
 338
 339 /*
 340  * Ensure that the current vmcs of the logical processor is the
 341  * vmcs01 of the vcpu before calling free_nested().
 342  */
 343 void nested_vmx_free_vcpu(struct kvm_vcpu *vcpu)
 344 {
 345         vcpu_load(vcpu);
 346         vmx_leave_nested(vcpu);
 347         vcpu_put(vcpu);
 348 }
 349
 350 #define EPTP_PA_MASK   GENMASK_ULL(51, 12)
 351
 352 static bool nested_ept_root_matches(hpa_t root_hpa, u64 root_eptp, u64 eptp)
 353 {
 354         return VALID_PAGE(root_hpa) &&
 355                ((root_eptp & EPTP_PA_MASK) == (eptp & EPTP_PA_MASK));
 356 }
 357
 358 static void nested_ept_invalidate_addr(struct kvm_vcpu *vcpu, gpa_t eptp,
 359                                        gpa_t addr)
 360 {
 361         unsigned long roots = 0;
 362         uint i;
 363         struct kvm_mmu_root_info *cached_root;
 364
 365         WARN_ON_ONCE(!mmu_is_nested(vcpu));
 366
 367         for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
 368                 cached_root = &vcpu->arch.mmu->prev_roots[i];
 369
 370                 if (nested_ept_root_matches(cached_root->hpa, cached_root->pgd,
 371                                             eptp))
 372                         roots |= KVM_MMU_ROOT_PREVIOUS(i);
 373         }
 374         if (roots)
 375                 kvm_mmu_invalidate_addr(vcpu, vcpu->arch.mmu, addr, roots);
 376 }
 377
 378 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
 379                 struct x86_exception *fault)
 380 {
 381         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
 382         struct vcpu_vmx *vmx = to_vmx(vcpu);
 383         u32 vm_exit_reason;
 384         unsigned long exit_qualification = vcpu->arch.exit_qualification;
 385
 386         if (vmx->nested.pml_full) {
 387                 vm_exit_reason = EXIT_REASON_PML_FULL;
 388                 vmx->nested.pml_full = false;
 389                 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
 390         } else {
 391                 if (fault->error_code & PFERR_RSVD_MASK)
 392                         vm_exit_reason = EXIT_REASON_EPT_MISCONFIG;
 393                 else
 394                         vm_exit_reason = EXIT_REASON_EPT_VIOLATION;
 395
 396                 /*
 397                  * Although the caller (kvm_inject_emulated_page_fault) would
 398                  * have already synced the faulting address in the shadow EPT
 399                  * tables for the current EPTP12, we also need to sync it for
 400                  * any other cached EPTP02s based on the same EP4TA, since the
 401                  * TLB associates mappings to the EP4TA rather than the full EPTP.
 402                  */
 403                 nested_ept_invalidate_addr(vcpu, vmcs12->ept_pointer,
 404                                            fault->address);
 405         }
 406
 407         nested_vmx_vmexit(vcpu, vm_exit_reason, 0, exit_qualification);
 408         vmcs12->guest_physical_address = fault->address;
 409 }
 410
 411 static void nested_ept_new_eptp(struct kvm_vcpu *vcpu)
 412 {
 413         struct vcpu_vmx *vmx = to_vmx(vcpu);
 414         bool execonly = vmx->nested.msrs.ept_caps & VMX_EPT_EXECUTE_ONLY_BIT;
 415         int ept_lpage_level = ept_caps_to_lpage_level(vmx->nested.msrs.ept_caps);
 416
 417         kvm_init_shadow_ept_mmu(vcpu, execonly, ept_lpage_level,
 418                                 nested_ept_ad_enabled(vcpu),
 419                                 nested_ept_get_eptp(vcpu));
 420 }
 421
 422 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
 423 {
 424         WARN_ON(mmu_is_nested(vcpu));
 425
 426         vcpu->arch.mmu = &vcpu->arch.guest_mmu;
 427         nested_ept_new_eptp(vcpu);
 428         vcpu->arch.mmu->get_guest_pgd     = nested_ept_get_eptp;
 429         vcpu->arch.mmu->inject_page_fault = nested_ept_inject_page_fault;
 430         vcpu->arch.mmu->get_pdptr         = kvm_pdptr_read;
 431
 432         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
 433 }
 434
 435 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
 436 {
 437         vcpu->arch.mmu = &vcpu->arch.root_mmu;
 438         vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
 439 }
 440
 441 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
 442                                             u16 error_code)
 443 {
 444         bool inequality, bit;
 445
 446         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
 447         inequality =
 448                 (error_code & vmcs12->page_fault_error_code_mask) !=
 449                  vmcs12->page_fault_error_code_match;
 450         return inequality ^ bit;
 451 }
 452
 453 static bool nested_vmx_is_exception_vmexit(struct kvm_vcpu *vcpu, u8 vector,
 454                                            u32 error_code)
 455 {
 456         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
 457
 458         /*
 459          * Drop bits 31:16 of the error code when performing the #PF mask+match
 460          * check.  All VMCS fields involved are 32 bits, but Intel CPUs never
 461          * set bits 31:16 and VMX disallows setting bits 31:16 in the injected
 462          * error code.  Including the to-be-dropped bits in the check might
 463          * result in an "impossible" or missed exit from L1's perspective.
 464          */
 465         if (vector == PF_VECTOR)
 466                 return nested_vmx_is_page_fault_vmexit(vmcs12, (u16)error_code);
 467
 468         return (vmcs12->exception_bitmap & (1u << vector));
 469 }
 470
 471 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu,
 472                                                struct vmcs12 *vmcs12)
 473 {
 474         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
 475                 return 0;
 476
 477         if (CC(!page_address_valid(vcpu, vmcs12->io_bitmap_a)) ||
 478             CC(!page_address_valid(vcpu, vmcs12->io_bitmap_b)))
 479                 return -EINVAL;
 480
 481         return 0;
 482 }
 483
 484 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
 485                                                 struct vmcs12 *vmcs12)
 486 {
 487         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
 488                 return 0;
 489
 490         if (CC(!page_address_valid(vcpu, vmcs12->msr_bitmap)))
 491                 return -EINVAL;
 492
 493         return 0;
 494 }
 495
 496 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu *vcpu,
 497                                                 struct vmcs12 *vmcs12)
 498 {
 499         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
 500                 return 0;
 501
 502         if (CC(!page_address_valid(vcpu, vmcs12->virtual_apic_page_addr)))
 503                 return -EINVAL;
 504
 505         return 0;
 506 }
 507
 508 /*
 509  * For x2APIC MSRs, ignore the vmcs01 bitmap.  L1 can enable x2APIC without L1
 510  * itself utilizing x2APIC.  All MSRs were previously set to be intercepted,
 511  * only the "disable intercept" case needs to be handled.
 512  */
 513 static void nested_vmx_disable_intercept_for_x2apic_msr(unsigned long *msr_bitmap_l1,
 514                                                         unsigned long *msr_bitmap_l0,
 515                                                         u32 msr, int type)
 516 {
 517         if (type & MSR_TYPE_R && !vmx_test_msr_bitmap_read(msr_bitmap_l1, msr))
 518                 vmx_clear_msr_bitmap_read(msr_bitmap_l0, msr);
 519
 520         if (type & MSR_TYPE_W && !vmx_test_msr_bitmap_write(msr_bitmap_l1, msr))
 521                 vmx_clear_msr_bitmap_write(msr_bitmap_l0, msr);
 522 }
 523
 524 static inline void enable_x2apic_msr_intercepts(unsigned long *msr_bitmap)
 525 {
 526         int msr;
 527
 528         for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
 529                 unsigned word = msr / BITS_PER_LONG;
 530
 531                 msr_bitmap[word] = ~0;
 532                 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
 533         }
 534 }
 535
 536 #define BUILD_NVMX_MSR_INTERCEPT_HELPER(rw)                                     \
 537 static inline                                                                   \
 538 void nested_vmx_set_msr_##rw##_intercept(struct vcpu_vmx *vmx,                  \
 539                                          unsigned long *msr_bitmap_l1,          \
 540                                          unsigned long *msr_bitmap_l0, u32 msr) \
 541 {                                                                               \
 542         if (vmx_test_msr_bitmap_##rw(vmx->vmcs01.msr_bitmap, msr) ||            \
 543             vmx_test_msr_bitmap_##rw(msr_bitmap_l1, msr))                       \
 544                 vmx_set_msr_bitmap_##rw(msr_bitmap_l0, msr);                    \
 545         else                                                                    \
 546                 vmx_clear_msr_bitmap_##rw(msr_bitmap_l0, msr);                  \
 547 }
 548 BUILD_NVMX_MSR_INTERCEPT_HELPER(read)
 549 BUILD_NVMX_MSR_INTERCEPT_HELPER(write)
 550
 551 static inline void nested_vmx_set_intercept_for_msr(struct vcpu_vmx *vmx,
 552                                                     unsigned long *msr_bitmap_l1,
 553                                                     unsigned long *msr_bitmap_l0,
 554                                                     u32 msr, int types)
 555 {
 556         if (types & MSR_TYPE_R)
 557                 nested_vmx_set_msr_read_intercept(vmx, msr_bitmap_l1,
 558                                                   msr_bitmap_l0, msr);
 559         if (types & MSR_TYPE_W)
 560                 nested_vmx_set_msr_write_intercept(vmx, msr_bitmap_l1,
 561                                                    msr_bitmap_l0, msr);
 562 }
 563
 564 /*
 565  * Merge L0's and L1's MSR bitmap, return false to indicate that
 566  * we do not use the hardware.
 567  */
 568 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
 569                                                  struct vmcs12 *vmcs12)
 570 {
 571         struct vcpu_vmx *vmx = to_vmx(vcpu);
 572         int msr;
 573         unsigned long *msr_bitmap_l1;
 574         unsigned long *msr_bitmap_l0 = vmx->nested.vmcs02.msr_bitmap;
 575         struct hv_enlightened_vmcs *evmcs = vmx->nested.hv_evmcs;
 576         struct kvm_host_map *map = &vmx->nested.msr_bitmap_map;
 577
 578         /* Nothing to do if the MSR bitmap is not in use.  */
 579         if (!cpu_has_vmx_msr_bitmap() ||
 580             !nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
 581                 return false;
 582
 583         /*
 584          * MSR bitmap update can be skipped when:
 585          * - MSR bitmap for L1 hasn't changed.
 586          * - Nested hypervisor (L1) is attempting to launch the same L2 as
 587          *   before.
 588          * - Nested hypervisor (L1) has enabled 'Enlightened MSR Bitmap' feature
 589          *   and tells KVM (L0) there were no changes in MSR bitmap for L2.
 590          */
 591         if (!vmx->nested.force_msr_bitmap_recalc && evmcs &&
 592             evmcs->hv_enlightenments_control.msr_bitmap &&
 593             evmcs->hv_clean_fields & HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP)
 594                 return true;
 595
 596         if (kvm_vcpu_map(vcpu, gpa_to_gfn(vmcs12->msr_bitmap), map))
 597                 return false;
 598
 599         msr_bitmap_l1 = (unsigned long *)map->hva;
 600
 601         /*
 602          * To keep the control flow simple, pay eight 8-byte writes (sixteen
 603          * 4-byte writes on 32-bit systems) up front to enable intercepts for
 604          * the x2APIC MSR range and selectively toggle those relevant to L2.
 605          */
 606         enable_x2apic_msr_intercepts(msr_bitmap_l0);
 607
 608         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
 609                 if (nested_cpu_has_apic_reg_virt(vmcs12)) {
 610                         /*
 611                          * L0 need not intercept reads for MSRs between 0x800
 612                          * and 0x8ff, it just lets the processor take the value
 613                          * from the virtual-APIC page; take those 256 bits
 614                          * directly from the L1 bitmap.
 615                          */
 616                         for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
 617                                 unsigned word = msr / BITS_PER_LONG;
 618
 619                                 msr_bitmap_l0[word] = msr_bitmap_l1[word];
 620                         }
 621                 }
 622
 623                 nested_vmx_disable_intercept_for_x2apic_msr(
 624                         msr_bitmap_l1, msr_bitmap_l0,
 625                         X2APIC_MSR(APIC_TASKPRI),
 626                         MSR_TYPE_R | MSR_TYPE_W);
 627
 628                 if (nested_cpu_has_vid(vmcs12)) {
 629                         nested_vmx_disable_intercept_for_x2apic_msr(
 630                                 msr_bitmap_l1, msr_bitmap_l0,
 631                                 X2APIC_MSR(APIC_EOI),
 632                                 MSR_TYPE_W);
 633                         nested_vmx_disable_intercept_for_x2apic_msr(
 634                                 msr_bitmap_l1, msr_bitmap_l0,
 635                                 X2APIC_MSR(APIC_SELF_IPI),
 636                                 MSR_TYPE_W);
 637                 }
 638         }
 639
 640         /*
 641          * Always check vmcs01's bitmap to honor userspace MSR filters and any
 642          * other runtime changes to vmcs01's bitmap, e.g. dynamic pass-through.
 643          */
 644 #ifdef CONFIG_X86_64
 645         nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0,
 646                                          MSR_FS_BASE, MSR_TYPE_RW);
 647
 648         nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0,
 649                                          MSR_GS_BASE, MSR_TYPE_RW);
 650
 651         nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0,
 652                                          MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
 653 #endif
 654         nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0,
 655                                          MSR_IA32_SPEC_CTRL, MSR_TYPE_RW);
 656
 657         nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0,
 658                                          MSR_IA32_PRED_CMD, MSR_TYPE_W);
 659
 660         nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0,
 661                                          MSR_IA32_FLUSH_CMD, MSR_TYPE_W);
 662
 663         kvm_vcpu_unmap(vcpu, &vmx->nested.msr_bitmap_map, false);
 664
 665         vmx->nested.force_msr_bitmap_recalc = false;
 666
 667         return true;
 668 }
 669
 670 static void nested_cache_shadow_vmcs12(struct kvm_vcpu *vcpu,
 671                                        struct vmcs12 *vmcs12)
 672 {
 673         struct vcpu_vmx *vmx = to_vmx(vcpu);
 674         struct gfn_to_hva_cache *ghc = &vmx->nested.shadow_vmcs12_cache;
 675
 676         if (!nested_cpu_has_shadow_vmcs(vmcs12) ||
 677             vmcs12->vmcs_link_pointer == INVALID_GPA)
 678                 return;
 679
 680         if (ghc->gpa != vmcs12->vmcs_link_pointer &&
 681             kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc,
 682                                       vmcs12->vmcs_link_pointer, VMCS12_SIZE))
 683                 return;
 684
 685         kvm_read_guest_cached(vmx->vcpu.kvm, ghc, get_shadow_vmcs12(vcpu),
 686                               VMCS12_SIZE);
 687 }
 688
 689 static void nested_flush_cached_shadow_vmcs12(struct kvm_vcpu *vcpu,
 690                                               struct vmcs12 *vmcs12)
 691 {
 692         struct vcpu_vmx *vmx = to_vmx(vcpu);
 693         struct gfn_to_hva_cache *ghc = &vmx->nested.shadow_vmcs12_cache;
 694
 695         if (!nested_cpu_has_shadow_vmcs(vmcs12) ||
 696             vmcs12->vmcs_link_pointer == INVALID_GPA)
 697                 return;
 698
 699         if (ghc->gpa != vmcs12->vmcs_link_pointer &&
 700             kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc,
 701                                       vmcs12->vmcs_link_pointer, VMCS12_SIZE))
 702                 return;
 703
 704         kvm_write_guest_cached(vmx->vcpu.kvm, ghc, get_shadow_vmcs12(vcpu),
 705                                VMCS12_SIZE);
 706 }
 707
 708 /*
 709  * In nested virtualization, check if L1 has set
 710  * VM_EXIT_ACK_INTR_ON_EXIT
 711  */
 712 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
 713 {
 714         return get_vmcs12(vcpu)->vm_exit_controls &
 715                 VM_EXIT_ACK_INTR_ON_EXIT;
 716 }
 717
 718 static int nested_vmx_check_apic_access_controls(struct kvm_vcpu *vcpu,
 719                                           struct vmcs12 *vmcs12)
 720 {
 721         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
 722             CC(!page_address_valid(vcpu, vmcs12->apic_access_addr)))
 723                 return -EINVAL;
 724         else
 725                 return 0;
 726 }
 727
 728 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
 729                                            struct vmcs12 *vmcs12)
 730 {
 731         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
 732             !nested_cpu_has_apic_reg_virt(vmcs12) &&
 733             !nested_cpu_has_vid(vmcs12) &&
 734             !nested_cpu_has_posted_intr(vmcs12))
 735                 return 0;
 736
 737         /*
 738          * If virtualize x2apic mode is enabled,
 739          * virtualize apic access must be disabled.
 740          */
 741         if (CC(nested_cpu_has_virt_x2apic_mode(vmcs12) &&
 742                nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)))
 743                 return -EINVAL;
 744
 745         /*
 746          * If virtual interrupt delivery is enabled,
 747          * we must exit on external interrupts.
 748          */
 749         if (CC(nested_cpu_has_vid(vmcs12) && !nested_exit_on_intr(vcpu)))
 750                 return -EINVAL;
 751
 752         /*
 753          * bits 15:8 should be zero in posted_intr_nv,
 754          * the descriptor address has been already checked
 755          * in nested_get_vmcs12_pages.
 756          *
 757          * bits 5:0 of posted_intr_desc_addr should be zero.
 758          */
 759         if (nested_cpu_has_posted_intr(vmcs12) &&
 760            (CC(!nested_cpu_has_vid(vmcs12)) ||
 761             CC(!nested_exit_intr_ack_set(vcpu)) ||
 762             CC((vmcs12->posted_intr_nv & 0xff00)) ||
 763             CC(!kvm_vcpu_is_legal_aligned_gpa(vcpu, vmcs12->posted_intr_desc_addr, 64))))
 764                 return -EINVAL;
 765
 766         /* tpr shadow is needed by all apicv features. */
 767         if (CC(!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)))
 768                 return -EINVAL;
 769
 770         return 0;
 771 }
 772
 773 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
 774                                        u32 count, u64 addr)
 775 {
 776         if (count == 0)
 777                 return 0;
 778
 779         if (!kvm_vcpu_is_legal_aligned_gpa(vcpu, addr, 16) ||
 780             !kvm_vcpu_is_legal_gpa(vcpu, (addr + count * sizeof(struct vmx_msr_entry) - 1)))
 781                 return -EINVAL;
 782
 783         return 0;
 784 }
 785
 786 static int nested_vmx_check_exit_msr_switch_controls(struct kvm_vcpu *vcpu,
 787                                                      struct vmcs12 *vmcs12)
 788 {
 789         if (CC(nested_vmx_check_msr_switch(vcpu,
 790                                            vmcs12->vm_exit_msr_load_count,
 791                                            vmcs12->vm_exit_msr_load_addr)) ||
 792             CC(nested_vmx_check_msr_switch(vcpu,
 793                                            vmcs12->vm_exit_msr_store_count,
 794                                            vmcs12->vm_exit_msr_store_addr)))
 795                 return -EINVAL;
 796
 797         return 0;
 798 }
 799
 800 static int nested_vmx_check_entry_msr_switch_controls(struct kvm_vcpu *vcpu,
 801                                                       struct vmcs12 *vmcs12)
 802 {
 803         if (CC(nested_vmx_check_msr_switch(vcpu,
 804                                            vmcs12->vm_entry_msr_load_count,
 805                                            vmcs12->vm_entry_msr_load_addr)))
 806                 return -EINVAL;
 807
 808         return 0;
 809 }
 810
 811 static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
 812                                          struct vmcs12 *vmcs12)
 813 {
 814         if (!nested_cpu_has_pml(vmcs12))
 815                 return 0;
 816
 817         if (CC(!nested_cpu_has_ept(vmcs12)) ||
 818             CC(!page_address_valid(vcpu, vmcs12->pml_address)))
 819                 return -EINVAL;
 820
 821         return 0;
 822 }
 823
 824 static int nested_vmx_check_unrestricted_guest_controls(struct kvm_vcpu *vcpu,
 825                                                         struct vmcs12 *vmcs12)
 826 {
 827         if (CC(nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST) &&
 828                !nested_cpu_has_ept(vmcs12)))
 829                 return -EINVAL;
 830         return 0;
 831 }
 832
 833 static int nested_vmx_check_mode_based_ept_exec_controls(struct kvm_vcpu *vcpu,
 834                                                          struct vmcs12 *vmcs12)
 835 {
 836         if (CC(nested_cpu_has2(vmcs12, SECONDARY_EXEC_MODE_BASED_EPT_EXEC) &&
 837                !nested_cpu_has_ept(vmcs12)))
 838                 return -EINVAL;
 839         return 0;
 840 }
 841
 842 static int nested_vmx_check_shadow_vmcs_controls(struct kvm_vcpu *vcpu,
 843                                                  struct vmcs12 *vmcs12)
 844 {
 845         if (!nested_cpu_has_shadow_vmcs(vmcs12))
 846                 return 0;
 847
 848         if (CC(!page_address_valid(vcpu, vmcs12->vmread_bitmap)) ||
 849             CC(!page_address_valid(vcpu, vmcs12->vmwrite_bitmap)))
 850                 return -EINVAL;
 851
 852         return 0;
 853 }
 854
 855 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
 856                                        struct vmx_msr_entry *e)
 857 {
 858         /* x2APIC MSR accesses are not allowed */
 859         if (CC(vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8))
 860                 return -EINVAL;
 861         if (CC(e->index == MSR_IA32_UCODE_WRITE) || /* SDM Table 35-2 */
 862             CC(e->index == MSR_IA32_UCODE_REV))
 863                 return -EINVAL;
 864         if (CC(e->reserved != 0))
 865                 return -EINVAL;
 866         return 0;
 867 }
 868
 869 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
 870                                      struct vmx_msr_entry *e)
 871 {
 872         if (CC(e->index == MSR_FS_BASE) ||
 873             CC(e->index == MSR_GS_BASE) ||
 874             CC(e->index == MSR_IA32_SMM_MONITOR_CTL) || /* SMM is not supported */
 875             nested_vmx_msr_check_common(vcpu, e))
 876                 return -EINVAL;
 877         return 0;
 878 }
 879
 880 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
 881                                       struct vmx_msr_entry *e)
 882 {
 883         if (CC(e->index == MSR_IA32_SMBASE) || /* SMM is not supported */
 884             nested_vmx_msr_check_common(vcpu, e))
 885                 return -EINVAL;
 886         return 0;
 887 }
 888
 889 static u32 nested_vmx_max_atomic_switch_msrs(struct kvm_vcpu *vcpu)
 890 {
 891         struct vcpu_vmx *vmx = to_vmx(vcpu);
 892         u64 vmx_misc = vmx_control_msr(vmx->nested.msrs.misc_low,
 893                                        vmx->nested.msrs.misc_high);
 894
 895         return (vmx_misc_max_msr(vmx_misc) + 1) * VMX_MISC_MSR_LIST_MULTIPLIER;
 896 }
 897
 898 /*
 899  * Load guest's/host's msr at nested entry/exit.
 900  * return 0 for success, entry index for failure.
 901  *
 902  * One of the failure modes for MSR load/store is when a list exceeds the
 903  * virtual hardware's capacity. To maintain compatibility with hardware inasmuch
 904  * as possible, process all valid entries before failing rather than precheck
 905  * for a capacity violation.
 906  */
 907 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
 908 {
 909         u32 i;
 910         struct vmx_msr_entry e;
 911         u32 max_msr_list_size = nested_vmx_max_atomic_switch_msrs(vcpu);
 912
 913         for (i = 0; i < count; i++) {
 914                 if (unlikely(i >= max_msr_list_size))
 915                         goto fail;
 916
 917                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
 918                                         &e, sizeof(e))) {
 919                         pr_debug_ratelimited(
 920                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
 921                                 __func__, i, gpa + i * sizeof(e));
 922                         goto fail;
 923                 }
 924                 if (nested_vmx_load_msr_check(vcpu, &e)) {
 925                         pr_debug_ratelimited(
 926                                 "%s check failed (%u, 0x%x, 0x%x)\n",
 927                                 __func__, i, e.index, e.reserved);
 928                         goto fail;
 929                 }
 930                 if (kvm_set_msr(vcpu, e.index, e.value)) {
 931                         pr_debug_ratelimited(
 932                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
 933                                 __func__, i, e.index, e.value);
 934                         goto fail;
 935                 }
 936         }
 937         return 0;
 938 fail:
 939         /* Note, max_msr_list_size is at most 4096, i.e. this can't wrap. */
 940         return i + 1;
 941 }
 942
 943 static bool nested_vmx_get_vmexit_msr_value(struct kvm_vcpu *vcpu,
 944                                             u32 msr_index,
 945                                             u64 *data)
 946 {
 947         struct vcpu_vmx *vmx = to_vmx(vcpu);
 948
 949         /*
 950          * If the L0 hypervisor stored a more accurate value for the TSC that
 951          * does not include the time taken for emulation of the L2->L1
 952          * VM-exit in L0, use the more accurate value.
 953          */
 954         if (msr_index == MSR_IA32_TSC) {
 955                 int i = vmx_find_loadstore_msr_slot(&vmx->msr_autostore.guest,
 956                                                     MSR_IA32_TSC);
 957
 958                 if (i >= 0) {
 959                         u64 val = vmx->msr_autostore.guest.val[i].value;
 960
 961                         *data = kvm_read_l1_tsc(vcpu, val);
 962                         return true;
 963                 }
 964         }
 965
 966         if (kvm_get_msr(vcpu, msr_index, data)) {
 967                 pr_debug_ratelimited("%s cannot read MSR (0x%x)\n", __func__,
 968                         msr_index);
 969                 return false;
 970         }
 971         return true;
 972 }
 973
 974 static bool read_and_check_msr_entry(struct kvm_vcpu *vcpu, u64 gpa, int i,
 975                                      struct vmx_msr_entry *e)
 976 {
 977         if (kvm_vcpu_read_guest(vcpu,
 978                                 gpa + i * sizeof(*e),
 979                                 e, 2 * sizeof(u32))) {
 980                 pr_debug_ratelimited(
 981                         "%s cannot read MSR entry (%u, 0x%08llx)\n",
 982                         __func__, i, gpa + i * sizeof(*e));
 983                 return false;
 984         }
 985         if (nested_vmx_store_msr_check(vcpu, e)) {
 986                 pr_debug_ratelimited(
 987                         "%s check failed (%u, 0x%x, 0x%x)\n",
 988                         __func__, i, e->index, e->reserved);
 989                 return false;
 990         }
 991         return true;
 992 }
 993
 994 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
 995 {
 996         u64 data;
 997         u32 i;
 998         struct vmx_msr_entry e;
 999         u32 max_msr_list_size = nested_vmx_max_atomic_switch_msrs(vcpu);
1000
1001         for (i = 0; i < count; i++) {
1002                 if (unlikely(i >= max_msr_list_size))
1003                         return -EINVAL;
1004
1005                 if (!read_and_check_msr_entry(vcpu, gpa, i, &e))
1006                         return -EINVAL;
1007
1008                 if (!nested_vmx_get_vmexit_msr_value(vcpu, e.index, &data))
1009                         return -EINVAL;
1010
1011                 if (kvm_vcpu_write_guest(vcpu,
1012                                          gpa + i * sizeof(e) +
1013                                              offsetof(struct vmx_msr_entry, value),
1014                                          &data, sizeof(data))) {
1015                         pr_debug_ratelimited(
1016                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
1017                                 __func__, i, e.index, data);
1018                         return -EINVAL;
1019                 }
1020         }
1021         return 0;
1022 }
1023
1024 static bool nested_msr_store_list_has_msr(struct kvm_vcpu *vcpu, u32 msr_index)
1025 {
1026         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1027         u32 count = vmcs12->vm_exit_msr_store_count;
1028         u64 gpa = vmcs12->vm_exit_msr_store_addr;
1029         struct vmx_msr_entry e;
1030         u32 i;
1031
1032         for (i = 0; i < count; i++) {
1033                 if (!read_and_check_msr_entry(vcpu, gpa, i, &e))
1034                         return false;
1035
1036                 if (e.index == msr_index)
1037                         return true;
1038         }
1039         return false;
1040 }
1041
1042 static void prepare_vmx_msr_autostore_list(struct kvm_vcpu *vcpu,
1043                                            u32 msr_index)
1044 {
1045         struct vcpu_vmx *vmx = to_vmx(vcpu);
1046         struct vmx_msrs *autostore = &vmx->msr_autostore.guest;
1047         bool in_vmcs12_store_list;
1048         int msr_autostore_slot;
1049         bool in_autostore_list;
1050         int last;
1051
1052         msr_autostore_slot = vmx_find_loadstore_msr_slot(autostore, msr_index);
1053         in_autostore_list = msr_autostore_slot >= 0;
1054         in_vmcs12_store_list = nested_msr_store_list_has_msr(vcpu, msr_index);
1055
1056         if (in_vmcs12_store_list && !in_autostore_list) {
1057                 if (autostore->nr == MAX_NR_LOADSTORE_MSRS) {
1058                         /*
1059                          * Emulated VMEntry does not fail here.  Instead a less
1060                          * accurate value will be returned by
1061                          * nested_vmx_get_vmexit_msr_value() using kvm_get_msr()
1062                          * instead of reading the value from the vmcs02 VMExit
1063                          * MSR-store area.
1064                          */
1065                         pr_warn_ratelimited(
1066                                 "Not enough msr entries in msr_autostore.  Can't add msr %x\n",
1067                                 msr_index);
1068                         return;
1069                 }
1070                 last = autostore->nr++;
1071                 autostore->val[last].index = msr_index;
1072         } else if (!in_vmcs12_store_list && in_autostore_list) {
1073                 last = --autostore->nr;
1074                 autostore->val[msr_autostore_slot] = autostore->val[last];
1075         }
1076 }
1077
1078 /*
1079  * Load guest's/host's cr3 at nested entry/exit.  @nested_ept is true if we are
1080  * emulating VM-Entry into a guest with EPT enabled.  On failure, the expected
1081  * Exit Qualification (for a VM-Entry consistency check VM-Exit) is assigned to
1082  * @entry_failure_code.
1083  */
1084 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3,
1085                                bool nested_ept, bool reload_pdptrs,
1086                                enum vm_entry_failure_code *entry_failure_code)
1087 {
1088         if (CC(kvm_vcpu_is_illegal_gpa(vcpu, cr3))) {
1089                 *entry_failure_code = ENTRY_FAIL_DEFAULT;
1090                 return -EINVAL;
1091         }
1092
1093         /*
1094          * If PAE paging and EPT are both on, CR3 is not used by the CPU and
1095          * must not be dereferenced.
1096          */
1097         if (reload_pdptrs && !nested_ept && is_pae_paging(vcpu) &&
1098             CC(!load_pdptrs(vcpu, cr3))) {
1099                 *entry_failure_code = ENTRY_FAIL_PDPTE;
1100                 return -EINVAL;
1101         }
1102
1103         vcpu->arch.cr3 = cr3;
1104         kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
1105
1106         /* Re-initialize the MMU, e.g. to pick up CR4 MMU role changes. */
1107         kvm_init_mmu(vcpu);
1108
1109         if (!nested_ept)
1110                 kvm_mmu_new_pgd(vcpu, cr3);
1111
1112         return 0;
1113 }
1114
1115 /*
1116  * Returns if KVM is able to config CPU to tag TLB entries
1117  * populated by L2 differently than TLB entries populated
1118  * by L1.
1119  *
1120  * If L0 uses EPT, L1 and L2 run with different EPTP because
1121  * guest_mode is part of kvm_mmu_page_role. Thus, TLB entries
1122  * are tagged with different EPTP.
1123  *
1124  * If L1 uses VPID and we allocated a vpid02, TLB entries are tagged
1125  * with different VPID (L1 entries are tagged with vmx->vpid
1126  * while L2 entries are tagged with vmx->nested.vpid02).
1127  */
1128 static bool nested_has_guest_tlb_tag(struct kvm_vcpu *vcpu)
1129 {
1130         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1131
1132         return enable_ept ||
1133                (nested_cpu_has_vpid(vmcs12) && to_vmx(vcpu)->nested.vpid02);
1134 }
1135
1136 static void nested_vmx_transition_tlb_flush(struct kvm_vcpu *vcpu,
1137                                             struct vmcs12 *vmcs12,
1138                                             bool is_vmenter)
1139 {
1140         struct vcpu_vmx *vmx = to_vmx(vcpu);
1141
1142         /*
1143          * KVM_REQ_HV_TLB_FLUSH flushes entries from either L1's VP_ID or
1144          * L2's VP_ID upon request from the guest. Make sure we check for
1145          * pending entries in the right FIFO upon L1/L2 transition as these
1146          * requests are put by other vCPUs asynchronously.
1147          */
1148         if (to_hv_vcpu(vcpu) && enable_ept)
1149                 kvm_make_request(KVM_REQ_HV_TLB_FLUSH, vcpu);
1150
1151         /*
1152          * If vmcs12 doesn't use VPID, L1 expects linear and combined mappings
1153          * for *all* contexts to be flushed on VM-Enter/VM-Exit, i.e. it's a
1154          * full TLB flush from the guest's perspective.  This is required even
1155          * if VPID is disabled in the host as KVM may need to synchronize the
1156          * MMU in response to the guest TLB flush.
1157          *
1158          * Note, using TLB_FLUSH_GUEST is correct even if nested EPT is in use.
1159          * EPT is a special snowflake, as guest-physical mappings aren't
1160          * flushed on VPID invalidations, including VM-Enter or VM-Exit with
1161          * VPID disabled.  As a result, KVM _never_ needs to sync nEPT
1162          * entries on VM-Enter because L1 can't rely on VM-Enter to flush
1163          * those mappings.
1164          */
1165         if (!nested_cpu_has_vpid(vmcs12)) {
1166                 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
1167                 return;
1168         }
1169
1170         /* L2 should never have a VPID if VPID is disabled. */
1171         WARN_ON(!enable_vpid);
1172
1173         /*
1174          * VPID is enabled and in use by vmcs12.  If vpid12 is changing, then
1175          * emulate a guest TLB flush as KVM does not track vpid12 history nor
1176          * is the VPID incorporated into the MMU context.  I.e. KVM must assume
1177          * that the new vpid12 has never been used and thus represents a new
1178          * guest ASID that cannot have entries in the TLB.
1179          */
1180         if (is_vmenter && vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
1181                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
1182                 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
1183                 return;
1184         }
1185
1186         /*
1187          * If VPID is enabled, used by vmc12, and vpid12 is not changing but
1188          * does not have a unique TLB tag (ASID), i.e. EPT is disabled and
1189          * KVM was unable to allocate a VPID for L2, flush the current context
1190          * as the effective ASID is common to both L1 and L2.
1191          */
1192         if (!nested_has_guest_tlb_tag(vcpu))
1193                 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1194 }
1195
1196 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
1197 {
1198         superset &= mask;
1199         subset &= mask;
1200
1201         return (superset | subset) == superset;
1202 }
1203
1204 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
1205 {
1206         const u64 feature_and_reserved =
1207                 /* feature (except bit 48; see below) */
1208                 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
1209                 /* reserved */
1210                 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
1211         u64 vmx_basic = vmcs_config.nested.basic;
1212
1213         if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
1214                 return -EINVAL;
1215
1216         /*
1217          * KVM does not emulate a version of VMX that constrains physical
1218          * addresses of VMX structures (e.g. VMCS) to 32-bits.
1219          */
1220         if (data & BIT_ULL(48))
1221                 return -EINVAL;
1222
1223         if (vmx_basic_vmcs_revision_id(vmx_basic) !=
1224             vmx_basic_vmcs_revision_id(data))
1225                 return -EINVAL;
1226
1227         if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
1228                 return -EINVAL;
1229
1230         vmx->nested.msrs.basic = data;
1231         return 0;
1232 }
1233
1234 static void vmx_get_control_msr(struct nested_vmx_msrs *msrs, u32 msr_index,
1235                                 u32 **low, u32 **high)
1236 {
1237         switch (msr_index) {
1238         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
1239                 *low = &msrs->pinbased_ctls_low;
1240                 *high = &msrs->pinbased_ctls_high;
1241                 break;
1242         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
1243                 *low = &msrs->procbased_ctls_low;
1244                 *high = &msrs->procbased_ctls_high;
1245                 break;
1246         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
1247                 *low = &msrs->exit_ctls_low;
1248                 *high = &msrs->exit_ctls_high;
1249                 break;
1250         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
1251                 *low = &msrs->entry_ctls_low;
1252                 *high = &msrs->entry_ctls_high;
1253                 break;
1254         case MSR_IA32_VMX_PROCBASED_CTLS2:
1255                 *low = &msrs->secondary_ctls_low;
1256                 *high = &msrs->secondary_ctls_high;
1257                 break;
1258         default:
1259                 BUG();
1260         }
1261 }
1262
1263 static int
1264 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
1265 {
1266         u32 *lowp, *highp;
1267         u64 supported;
1268
1269         vmx_get_control_msr(&vmcs_config.nested, msr_index, &lowp, &highp);
1270
1271         supported = vmx_control_msr(*lowp, *highp);
1272
1273         /* Check must-be-1 bits are still 1. */
1274         if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
1275                 return -EINVAL;
1276
1277         /* Check must-be-0 bits are still 0. */
1278         if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
1279                 return -EINVAL;
1280
1281         vmx_get_control_msr(&vmx->nested.msrs, msr_index, &lowp, &highp);
1282         *lowp = data;
1283         *highp = data >> 32;
1284         return 0;
1285 }
1286
1287 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
1288 {
1289         const u64 feature_and_reserved_bits =
1290                 /* feature */
1291                 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
1292                 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
1293                 /* reserved */
1294                 GENMASK_ULL(13, 9) | BIT_ULL(31);
1295         u64 vmx_misc = vmx_control_msr(vmcs_config.nested.misc_low,
1296                                        vmcs_config.nested.misc_high);
1297
1298         if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
1299                 return -EINVAL;
1300
1301         if ((vmx->nested.msrs.pinbased_ctls_high &
1302              PIN_BASED_VMX_PREEMPTION_TIMER) &&
1303             vmx_misc_preemption_timer_rate(data) !=
1304             vmx_misc_preemption_timer_rate(vmx_misc))
1305                 return -EINVAL;
1306
1307         if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
1308                 return -EINVAL;
1309
1310         if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
1311                 return -EINVAL;
1312
1313         if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
1314                 return -EINVAL;
1315
1316         vmx->nested.msrs.misc_low = data;
1317         vmx->nested.msrs.misc_high = data >> 32;
1318
1319         return 0;
1320 }
1321
1322 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
1323 {
1324         u64 vmx_ept_vpid_cap = vmx_control_msr(vmcs_config.nested.ept_caps,
1325                                                vmcs_config.nested.vpid_caps);
1326
1327         /* Every bit is either reserved or a feature bit. */
1328         if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
1329                 return -EINVAL;
1330
1331         vmx->nested.msrs.ept_caps = data;
1332         vmx->nested.msrs.vpid_caps = data >> 32;
1333         return 0;
1334 }
1335
1336 static u64 *vmx_get_fixed0_msr(struct nested_vmx_msrs *msrs, u32 msr_index)
1337 {
1338         switch (msr_index) {
1339         case MSR_IA32_VMX_CR0_FIXED0:
1340                 return &msrs->cr0_fixed0;
1341         case MSR_IA32_VMX_CR4_FIXED0:
1342                 return &msrs->cr4_fixed0;
1343         default:
1344                 BUG();
1345         }
1346 }
1347
1348 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
1349 {
1350         const u64 *msr = vmx_get_fixed0_msr(&vmcs_config.nested, msr_index);
1351
1352         /*
1353          * 1 bits (which indicates bits which "must-be-1" during VMX operation)
1354          * must be 1 in the restored value.
1355          */
1356         if (!is_bitwise_subset(data, *msr, -1ULL))
1357                 return -EINVAL;
1358
1359         *vmx_get_fixed0_msr(&vmx->nested.msrs, msr_index) = data;
1360         return 0;
1361 }
1362
1363 /*
1364  * Called when userspace is restoring VMX MSRs.
1365  *
1366  * Returns 0 on success, non-0 otherwise.
1367  */
1368 int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1369 {
1370         struct vcpu_vmx *vmx = to_vmx(vcpu);
1371
1372         /*
1373          * Don't allow changes to the VMX capability MSRs while the vCPU
1374          * is in VMX operation.
1375          */
1376         if (vmx->nested.vmxon)
1377                 return -EBUSY;
1378
1379         switch (msr_index) {
1380         case MSR_IA32_VMX_BASIC:
1381                 return vmx_restore_vmx_basic(vmx, data);
1382         case MSR_IA32_VMX_PINBASED_CTLS:
1383         case MSR_IA32_VMX_PROCBASED_CTLS:
1384         case MSR_IA32_VMX_EXIT_CTLS:
1385         case MSR_IA32_VMX_ENTRY_CTLS:
1386                 /*
1387                  * The "non-true" VMX capability MSRs are generated from the
1388                  * "true" MSRs, so we do not support restoring them directly.
1389                  *
1390                  * If userspace wants to emulate VMX_BASIC[55]=0, userspace
1391                  * should restore the "true" MSRs with the must-be-1 bits
1392                  * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
1393                  * DEFAULT SETTINGS".
1394                  */
1395                 return -EINVAL;
1396         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
1397         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
1398         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
1399         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
1400         case MSR_IA32_VMX_PROCBASED_CTLS2:
1401                 return vmx_restore_control_msr(vmx, msr_index, data);
1402         case MSR_IA32_VMX_MISC:
1403                 return vmx_restore_vmx_misc(vmx, data);
1404         case MSR_IA32_VMX_CR0_FIXED0:
1405         case MSR_IA32_VMX_CR4_FIXED0:
1406                 return vmx_restore_fixed0_msr(vmx, msr_index, data);
1407         case MSR_IA32_VMX_CR0_FIXED1:
1408         case MSR_IA32_VMX_CR4_FIXED1:
1409                 /*
1410                  * These MSRs are generated based on the vCPU's CPUID, so we
1411                  * do not support restoring them directly.
1412                  */
1413                 return -EINVAL;
1414         case MSR_IA32_VMX_EPT_VPID_CAP:
1415                 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
1416         case MSR_IA32_VMX_VMCS_ENUM:
1417                 vmx->nested.msrs.vmcs_enum = data;
1418                 return 0;
1419         case MSR_IA32_VMX_VMFUNC:
1420                 if (data & ~vmcs_config.nested.vmfunc_controls)
1421                         return -EINVAL;
1422                 vmx->nested.msrs.vmfunc_controls = data;
1423                 return 0;
1424         default:
1425                 /*
1426                  * The rest of the VMX capability MSRs do not support restore.
1427                  */
1428                 return -EINVAL;
1429         }
1430 }
1431
1432 /* Returns 0 on success, non-0 otherwise. */
1433 int vmx_get_vmx_msr(struct nested_vmx_msrs *msrs, u32 msr_index, u64 *pdata)
1434 {
1435         switch (msr_index) {
1436         case MSR_IA32_VMX_BASIC:
1437                 *pdata = msrs->basic;
1438                 break;
1439         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
1440         case MSR_IA32_VMX_PINBASED_CTLS:
1441                 *pdata = vmx_control_msr(
1442                         msrs->pinbased_ctls_low,
1443                         msrs->pinbased_ctls_high);
1444                 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
1445                         *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
1446                 break;
1447         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
1448         case MSR_IA32_VMX_PROCBASED_CTLS:
1449                 *pdata = vmx_control_msr(
1450                         msrs->procbased_ctls_low,
1451                         msrs->procbased_ctls_high);
1452                 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
1453                         *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
1454                 break;
1455         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
1456         case MSR_IA32_VMX_EXIT_CTLS:
1457                 *pdata = vmx_control_msr(
1458                         msrs->exit_ctls_low,
1459                         msrs->exit_ctls_high);
1460                 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
1461                         *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
1462                 break;
1463         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
1464         case MSR_IA32_VMX_ENTRY_CTLS:
1465                 *pdata = vmx_control_msr(
1466                         msrs->entry_ctls_low,
1467                         msrs->entry_ctls_high);
1468                 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
1469                         *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
1470                 break;
1471         case MSR_IA32_VMX_MISC:
1472                 *pdata = vmx_control_msr(
1473                         msrs->misc_low,
1474                         msrs->misc_high);
1475                 break;
1476         case MSR_IA32_VMX_CR0_FIXED0:
1477                 *pdata = msrs->cr0_fixed0;
1478                 break;
1479         case MSR_IA32_VMX_CR0_FIXED1:
1480                 *pdata = msrs->cr0_fixed1;
1481                 break;
1482         case MSR_IA32_VMX_CR4_FIXED0:
1483                 *pdata = msrs->cr4_fixed0;
1484                 break;
1485         case MSR_IA32_VMX_CR4_FIXED1:
1486                 *pdata = msrs->cr4_fixed1;
1487                 break;
1488         case MSR_IA32_VMX_VMCS_ENUM:
1489                 *pdata = msrs->vmcs_enum;
1490                 break;
1491         case MSR_IA32_VMX_PROCBASED_CTLS2:
1492                 *pdata = vmx_control_msr(
1493                         msrs->secondary_ctls_low,
1494                         msrs->secondary_ctls_high);
1495                 break;
1496         case MSR_IA32_VMX_EPT_VPID_CAP:
1497                 *pdata = msrs->ept_caps |
1498                         ((u64)msrs->vpid_caps << 32);
1499                 break;
1500         case MSR_IA32_VMX_VMFUNC:
1501                 *pdata = msrs->vmfunc_controls;
1502                 break;
1503         default:
1504                 return 1;
1505         }
1506
1507         return 0;
1508 }
1509
1510 /*
1511  * Copy the writable VMCS shadow fields back to the VMCS12, in case they have
1512  * been modified by the L1 guest.  Note, "writable" in this context means
1513  * "writable by the guest", i.e. tagged SHADOW_FIELD_RW; the set of
1514  * fields tagged SHADOW_FIELD_RO may or may not align with the "read-only"
1515  * VM-exit information fields (which are actually writable if the vCPU is
1516  * configured to support "VMWRITE to any supported field in the VMCS").
1517  */
1518 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
1519 {
1520         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
1521         struct vmcs12 *vmcs12 = get_vmcs12(&vmx->vcpu);
1522         struct shadow_vmcs_field field;
1523         unsigned long val;
1524         int i;
1525
1526         if (WARN_ON(!shadow_vmcs))
1527                 return;
1528
1529         preempt_disable();
1530
1531         vmcs_load(shadow_vmcs);
1532
1533         for (i = 0; i < max_shadow_read_write_fields; i++) {
1534                 field = shadow_read_write_fields[i];
1535                 val = __vmcs_readl(field.encoding);
1536                 vmcs12_write_any(vmcs12, field.encoding, field.offset, val);
1537         }
1538
1539         vmcs_clear(shadow_vmcs);
1540         vmcs_load(vmx->loaded_vmcs->vmcs);
1541
1542         preempt_enable();
1543 }
1544
1545 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
1546 {
1547         const struct shadow_vmcs_field *fields[] = {
1548                 shadow_read_write_fields,
1549                 shadow_read_only_fields
1550         };
1551         const int max_fields[] = {
1552                 max_shadow_read_write_fields,
1553                 max_shadow_read_only_fields
1554         };
1555         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
1556         struct vmcs12 *vmcs12 = get_vmcs12(&vmx->vcpu);
1557         struct shadow_vmcs_field field;
1558         unsigned long val;
1559         int i, q;
1560
1561         if (WARN_ON(!shadow_vmcs))
1562                 return;
1563
1564         vmcs_load(shadow_vmcs);
1565
1566         for (q = 0; q < ARRAY_SIZE(fields); q++) {
1567                 for (i = 0; i < max_fields[q]; i++) {
1568                         field = fields[q][i];
1569                         val = vmcs12_read_any(vmcs12, field.encoding,
1570                                               field.offset);
1571                         __vmcs_writel(field.encoding, val);
1572                 }
1573         }
1574
1575         vmcs_clear(shadow_vmcs);
1576         vmcs_load(vmx->loaded_vmcs->vmcs);
1577 }
1578
1579 static void copy_enlightened_to_vmcs12(struct vcpu_vmx *vmx, u32 hv_clean_fields)
1580 {
1581         struct vmcs12 *vmcs12 = vmx->nested.cached_vmcs12;
1582         struct hv_enlightened_vmcs *evmcs = vmx->nested.hv_evmcs;
1583         struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(&vmx->vcpu);
1584
1585         /* HV_VMX_ENLIGHTENED_CLEAN_FIELD_NONE */
1586         vmcs12->tpr_threshold = evmcs->tpr_threshold;
1587         vmcs12->guest_rip = evmcs->guest_rip;
1588
1589         if (unlikely(!(hv_clean_fields &
1590                        HV_VMX_ENLIGHTENED_CLEAN_FIELD_ENLIGHTENMENTSCONTROL))) {
1591                 hv_vcpu->nested.pa_page_gpa = evmcs->partition_assist_page;
1592                 hv_vcpu->nested.vm_id = evmcs->hv_vm_id;
1593                 hv_vcpu->nested.vp_id = evmcs->hv_vp_id;
1594         }
1595
1596         if (unlikely(!(hv_clean_fields &
1597                        HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_BASIC))) {
1598                 vmcs12->guest_rsp = evmcs->guest_rsp;
1599                 vmcs12->guest_rflags = evmcs->guest_rflags;
1600                 vmcs12->guest_interruptibility_info =
1601                         evmcs->guest_interruptibility_info;
1602                 /*
1603                  * Not present in struct vmcs12:
1604                  * vmcs12->guest_ssp = evmcs->guest_ssp;
1605                  */
1606         }
1607
1608         if (unlikely(!(hv_clean_fields &
1609                        HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC))) {
1610                 vmcs12->cpu_based_vm_exec_control =
1611                         evmcs->cpu_based_vm_exec_control;
1612         }
1613
1614         if (unlikely(!(hv_clean_fields &
1615                        HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EXCPN))) {
1616                 vmcs12->exception_bitmap = evmcs->exception_bitmap;
1617         }
1618
1619         if (unlikely(!(hv_clean_fields &
1620                        HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY))) {
1621                 vmcs12->vm_entry_controls = evmcs->vm_entry_controls;
1622         }
1623
1624         if (unlikely(!(hv_clean_fields &
1625                        HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT))) {
1626                 vmcs12->vm_entry_intr_info_field =
1627                         evmcs->vm_entry_intr_info_field;
1628                 vmcs12->vm_entry_exception_error_code =
1629                         evmcs->vm_entry_exception_error_code;
1630                 vmcs12->vm_entry_instruction_len =
1631                         evmcs->vm_entry_instruction_len;
1632         }
1633
1634         if (unlikely(!(hv_clean_fields &
1635                        HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1))) {
1636                 vmcs12->host_ia32_pat = evmcs->host_ia32_pat;
1637                 vmcs12->host_ia32_efer = evmcs->host_ia32_efer;
1638                 vmcs12->host_cr0 = evmcs->host_cr0;
1639                 vmcs12->host_cr3 = evmcs->host_cr3;
1640                 vmcs12->host_cr4 = evmcs->host_cr4;
1641                 vmcs12->host_ia32_sysenter_esp = evmcs->host_ia32_sysenter_esp;
1642                 vmcs12->host_ia32_sysenter_eip = evmcs->host_ia32_sysenter_eip;
1643                 vmcs12->host_rip = evmcs->host_rip;
1644                 vmcs12->host_ia32_sysenter_cs = evmcs->host_ia32_sysenter_cs;
1645                 vmcs12->host_es_selector = evmcs->host_es_selector;
1646                 vmcs12->host_cs_selector = evmcs->host_cs_selector;
1647                 vmcs12->host_ss_selector = evmcs->host_ss_selector;
1648                 vmcs12->host_ds_selector = evmcs->host_ds_selector;
1649                 vmcs12->host_fs_selector = evmcs->host_fs_selector;
1650                 vmcs12->host_gs_selector = evmcs->host_gs_selector;
1651                 vmcs12->host_tr_selector = evmcs->host_tr_selector;
1652                 vmcs12->host_ia32_perf_global_ctrl = evmcs->host_ia32_perf_global_ctrl;
1653                 /*
1654                  * Not present in struct vmcs12:
1655                  * vmcs12->host_ia32_s_cet = evmcs->host_ia32_s_cet;
1656                  * vmcs12->host_ssp = evmcs->host_ssp;
1657                  * vmcs12->host_ia32_int_ssp_table_addr = evmcs->host_ia32_int_ssp_table_addr;
1658                  */
1659         }
1660
1661         if (unlikely(!(hv_clean_fields &
1662                        HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP1))) {
1663                 vmcs12->pin_based_vm_exec_control =
1664                         evmcs->pin_based_vm_exec_control;
1665                 vmcs12->vm_exit_controls = evmcs->vm_exit_controls;
1666                 vmcs12->secondary_vm_exec_control =
1667                         evmcs->secondary_vm_exec_control;
1668         }
1669
1670         if (unlikely(!(hv_clean_fields &
1671                        HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP))) {
1672                 vmcs12->io_bitmap_a = evmcs->io_bitmap_a;
1673                 vmcs12->io_bitmap_b = evmcs->io_bitmap_b;
1674         }
1675
1676         if (unlikely(!(hv_clean_fields &
1677                        HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP))) {
1678                 vmcs12->msr_bitmap = evmcs->msr_bitmap;
1679         }
1680
1681         if (unlikely(!(hv_clean_fields &
1682                        HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2))) {
1683                 vmcs12->guest_es_base = evmcs->guest_es_base;
1684                 vmcs12->guest_cs_base = evmcs->guest_cs_base;
1685                 vmcs12->guest_ss_base = evmcs->guest_ss_base;
1686                 vmcs12->guest_ds_base = evmcs->guest_ds_base;
1687                 vmcs12->guest_fs_base = evmcs->guest_fs_base;
1688                 vmcs12->guest_gs_base = evmcs->guest_gs_base;
1689                 vmcs12->guest_ldtr_base = evmcs->guest_ldtr_base;
1690                 vmcs12->guest_tr_base = evmcs->guest_tr_base;
1691                 vmcs12->guest_gdtr_base = evmcs->guest_gdtr_base;
1692                 vmcs12->guest_idtr_base = evmcs->guest_idtr_base;
1693                 vmcs12->guest_es_limit = evmcs->guest_es_limit;
1694                 vmcs12->guest_cs_limit = evmcs->guest_cs_limit;
1695                 vmcs12->guest_ss_limit = evmcs->guest_ss_limit;
1696                 vmcs12->guest_ds_limit = evmcs->guest_ds_limit;
1697                 vmcs12->guest_fs_limit = evmcs->guest_fs_limit;
1698                 vmcs12->guest_gs_limit = evmcs->guest_gs_limit;
1699                 vmcs12->guest_ldtr_limit = evmcs->guest_ldtr_limit;
1700                 vmcs12->guest_tr_limit = evmcs->guest_tr_limit;
1701                 vmcs12->guest_gdtr_limit = evmcs->guest_gdtr_limit;
1702                 vmcs12->guest_idtr_limit = evmcs->guest_idtr_limit;
1703                 vmcs12->guest_es_ar_bytes = evmcs->guest_es_ar_bytes;
1704                 vmcs12->guest_cs_ar_bytes = evmcs->guest_cs_ar_bytes;
1705                 vmcs12->guest_ss_ar_bytes = evmcs->guest_ss_ar_bytes;
1706                 vmcs12->guest_ds_ar_bytes = evmcs->guest_ds_ar_bytes;
1707                 vmcs12->guest_fs_ar_bytes = evmcs->guest_fs_ar_bytes;
1708                 vmcs12->guest_gs_ar_bytes = evmcs->guest_gs_ar_bytes;
1709                 vmcs12->guest_ldtr_ar_bytes = evmcs->guest_ldtr_ar_bytes;
1710                 vmcs12->guest_tr_ar_bytes = evmcs->guest_tr_ar_bytes;
1711                 vmcs12->guest_es_selector = evmcs->guest_es_selector;
1712                 vmcs12->guest_cs_selector = evmcs->guest_cs_selector;
1713                 vmcs12->guest_ss_selector = evmcs->guest_ss_selector;
1714                 vmcs12->guest_ds_selector = evmcs->guest_ds_selector;
1715                 vmcs12->guest_fs_selector = evmcs->guest_fs_selector;
1716                 vmcs12->guest_gs_selector = evmcs->guest_gs_selector;
1717                 vmcs12->guest_ldtr_selector = evmcs->guest_ldtr_selector;
1718                 vmcs12->guest_tr_selector = evmcs->guest_tr_selector;
1719         }
1720
1721         if (unlikely(!(hv_clean_fields &
1722                        HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2))) {
1723                 vmcs12->tsc_offset = evmcs->tsc_offset;
1724                 vmcs12->virtual_apic_page_addr = evmcs->virtual_apic_page_addr;
1725                 vmcs12->xss_exit_bitmap = evmcs->xss_exit_bitmap;
1726                 vmcs12->encls_exiting_bitmap = evmcs->encls_exiting_bitmap;
1727                 vmcs12->tsc_multiplier = evmcs->tsc_multiplier;
1728         }
1729
1730         if (unlikely(!(hv_clean_fields &
1731                        HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR))) {
1732                 vmcs12->cr0_guest_host_mask = evmcs->cr0_guest_host_mask;
1733                 vmcs12->cr4_guest_host_mask = evmcs->cr4_guest_host_mask;
1734                 vmcs12->cr0_read_shadow = evmcs->cr0_read_shadow;
1735                 vmcs12->cr4_read_shadow = evmcs->cr4_read_shadow;
1736                 vmcs12->guest_cr0 = evmcs->guest_cr0;
1737                 vmcs12->guest_cr3 = evmcs->guest_cr3;
1738                 vmcs12->guest_cr4 = evmcs->guest_cr4;
1739                 vmcs12->guest_dr7 = evmcs->guest_dr7;
1740         }
1741
1742         if (unlikely(!(hv_clean_fields &
1743                        HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER))) {
1744                 vmcs12->host_fs_base = evmcs->host_fs_base;
1745                 vmcs12->host_gs_base = evmcs->host_gs_base;
1746                 vmcs12->host_tr_base = evmcs->host_tr_base;
1747                 vmcs12->host_gdtr_base = evmcs->host_gdtr_base;
1748                 vmcs12->host_idtr_base = evmcs->host_idtr_base;
1749                 vmcs12->host_rsp = evmcs->host_rsp;
1750         }
1751
1752         if (unlikely(!(hv_clean_fields &
1753                        HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT))) {
1754                 vmcs12->ept_pointer = evmcs->ept_pointer;
1755                 vmcs12->virtual_processor_id = evmcs->virtual_processor_id;
1756         }
1757
1758         if (unlikely(!(hv_clean_fields &
1759                        HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1))) {
1760                 vmcs12->vmcs_link_pointer = evmcs->vmcs_link_pointer;
1761                 vmcs12->guest_ia32_debugctl = evmcs->guest_ia32_debugctl;
1762                 vmcs12->guest_ia32_pat = evmcs->guest_ia32_pat;
1763                 vmcs12->guest_ia32_efer = evmcs->guest_ia32_efer;
1764                 vmcs12->guest_pdptr0 = evmcs->guest_pdptr0;
1765                 vmcs12->guest_pdptr1 = evmcs->guest_pdptr1;
1766                 vmcs12->guest_pdptr2 = evmcs->guest_pdptr2;
1767                 vmcs12->guest_pdptr3 = evmcs->guest_pdptr3;
1768                 vmcs12->guest_pending_dbg_exceptions =
1769                         evmcs->guest_pending_dbg_exceptions;
1770                 vmcs12->guest_sysenter_esp = evmcs->guest_sysenter_esp;
1771                 vmcs12->guest_sysenter_eip = evmcs->guest_sysenter_eip;
1772                 vmcs12->guest_bndcfgs = evmcs->guest_bndcfgs;
1773                 vmcs12->guest_activity_state = evmcs->guest_activity_state;
1774                 vmcs12->guest_sysenter_cs = evmcs->guest_sysenter_cs;
1775                 vmcs12->guest_ia32_perf_global_ctrl = evmcs->guest_ia32_perf_global_ctrl;
1776                 /*
1777                  * Not present in struct vmcs12:
1778                  * vmcs12->guest_ia32_s_cet = evmcs->guest_ia32_s_cet;
1779                  * vmcs12->guest_ia32_lbr_ctl = evmcs->guest_ia32_lbr_ctl;
1780                  * vmcs12->guest_ia32_int_ssp_table_addr = evmcs->guest_ia32_int_ssp_table_addr;
1781                  */
1782         }
1783
1784         /*
1785          * Not used?
1786          * vmcs12->vm_exit_msr_store_addr = evmcs->vm_exit_msr_store_addr;
1787          * vmcs12->vm_exit_msr_load_addr = evmcs->vm_exit_msr_load_addr;
1788          * vmcs12->vm_entry_msr_load_addr = evmcs->vm_entry_msr_load_addr;
1789          * vmcs12->page_fault_error_code_mask =
1790          *              evmcs->page_fault_error_code_mask;
1791          * vmcs12->page_fault_error_code_match =
1792          *              evmcs->page_fault_error_code_match;
1793          * vmcs12->cr3_target_count = evmcs->cr3_target_count;
1794          * vmcs12->vm_exit_msr_store_count = evmcs->vm_exit_msr_store_count;
1795          * vmcs12->vm_exit_msr_load_count = evmcs->vm_exit_msr_load_count;
1796          * vmcs12->vm_entry_msr_load_count = evmcs->vm_entry_msr_load_count;
1797          */
1798
1799         /*
1800          * Read only fields:
1801          * vmcs12->guest_physical_address = evmcs->guest_physical_address;
1802          * vmcs12->vm_instruction_error = evmcs->vm_instruction_error;
1803          * vmcs12->vm_exit_reason = evmcs->vm_exit_reason;
1804          * vmcs12->vm_exit_intr_info = evmcs->vm_exit_intr_info;
1805          * vmcs12->vm_exit_intr_error_code = evmcs->vm_exit_intr_error_code;
1806          * vmcs12->idt_vectoring_info_field = evmcs->idt_vectoring_info_field;
1807          * vmcs12->idt_vectoring_error_code = evmcs->idt_vectoring_error_code;
1808          * vmcs12->vm_exit_instruction_len = evmcs->vm_exit_instruction_len;
1809          * vmcs12->vmx_instruction_info = evmcs->vmx_instruction_info;
1810          * vmcs12->exit_qualification = evmcs->exit_qualification;
1811          * vmcs12->guest_linear_address = evmcs->guest_linear_address;
1812          *
1813          * Not present in struct vmcs12:
1814          * vmcs12->exit_io_instruction_ecx = evmcs->exit_io_instruction_ecx;
1815          * vmcs12->exit_io_instruction_esi = evmcs->exit_io_instruction_esi;
1816          * vmcs12->exit_io_instruction_edi = evmcs->exit_io_instruction_edi;
1817          * vmcs12->exit_io_instruction_eip = evmcs->exit_io_instruction_eip;
1818          */
1819
1820         return;
1821 }
1822
1823 static void copy_vmcs12_to_enlightened(struct vcpu_vmx *vmx)
1824 {
1825         struct vmcs12 *vmcs12 = vmx->nested.cached_vmcs12;
1826         struct hv_enlightened_vmcs *evmcs = vmx->nested.hv_evmcs;
1827
1828         /*
1829          * Should not be changed by KVM:
1830          *
1831          * evmcs->host_es_selector = vmcs12->host_es_selector;
1832          * evmcs->host_cs_selector = vmcs12->host_cs_selector;
1833          * evmcs->host_ss_selector = vmcs12->host_ss_selector;
1834          * evmcs->host_ds_selector = vmcs12->host_ds_selector;
1835          * evmcs->host_fs_selector = vmcs12->host_fs_selector;
1836          * evmcs->host_gs_selector = vmcs12->host_gs_selector;
1837          * evmcs->host_tr_selector = vmcs12->host_tr_selector;
1838          * evmcs->host_ia32_pat = vmcs12->host_ia32_pat;
1839          * evmcs->host_ia32_efer = vmcs12->host_ia32_efer;
1840          * evmcs->host_cr0 = vmcs12->host_cr0;
1841          * evmcs->host_cr3 = vmcs12->host_cr3;
1842          * evmcs->host_cr4 = vmcs12->host_cr4;
1843          * evmcs->host_ia32_sysenter_esp = vmcs12->host_ia32_sysenter_esp;
1844          * evmcs->host_ia32_sysenter_eip = vmcs12->host_ia32_sysenter_eip;
1845          * evmcs->host_rip = vmcs12->host_rip;
1846          * evmcs->host_ia32_sysenter_cs = vmcs12->host_ia32_sysenter_cs;
1847          * evmcs->host_fs_base = vmcs12->host_fs_base;
1848          * evmcs->host_gs_base = vmcs12->host_gs_base;
1849          * evmcs->host_tr_base = vmcs12->host_tr_base;
1850          * evmcs->host_gdtr_base = vmcs12->host_gdtr_base;
1851          * evmcs->host_idtr_base = vmcs12->host_idtr_base;
1852          * evmcs->host_rsp = vmcs12->host_rsp;
1853          * sync_vmcs02_to_vmcs12() doesn't read these:
1854          * evmcs->io_bitmap_a = vmcs12->io_bitmap_a;
1855          * evmcs->io_bitmap_b = vmcs12->io_bitmap_b;
1856          * evmcs->msr_bitmap = vmcs12->msr_bitmap;
1857          * evmcs->ept_pointer = vmcs12->ept_pointer;
1858          * evmcs->xss_exit_bitmap = vmcs12->xss_exit_bitmap;
1859          * evmcs->vm_exit_msr_store_addr = vmcs12->vm_exit_msr_store_addr;
1860          * evmcs->vm_exit_msr_load_addr = vmcs12->vm_exit_msr_load_addr;
1861          * evmcs->vm_entry_msr_load_addr = vmcs12->vm_entry_msr_load_addr;
1862          * evmcs->tpr_threshold = vmcs12->tpr_threshold;
1863          * evmcs->virtual_processor_id = vmcs12->virtual_processor_id;
1864          * evmcs->exception_bitmap = vmcs12->exception_bitmap;
1865          * evmcs->vmcs_link_pointer = vmcs12->vmcs_link_pointer;
1866          * evmcs->pin_based_vm_exec_control = vmcs12->pin_based_vm_exec_control;
1867          * evmcs->vm_exit_controls = vmcs12->vm_exit_controls;
1868          * evmcs->secondary_vm_exec_control = vmcs12->secondary_vm_exec_control;
1869          * evmcs->page_fault_error_code_mask =
1870          *              vmcs12->page_fault_error_code_mask;
1871          * evmcs->page_fault_error_code_match =
1872          *              vmcs12->page_fault_error_code_match;
1873          * evmcs->cr3_target_count = vmcs12->cr3_target_count;
1874          * evmcs->virtual_apic_page_addr = vmcs12->virtual_apic_page_addr;
1875          * evmcs->tsc_offset = vmcs12->tsc_offset;
1876          * evmcs->guest_ia32_debugctl = vmcs12->guest_ia32_debugctl;
1877          * evmcs->cr0_guest_host_mask = vmcs12->cr0_guest_host_mask;
1878          * evmcs->cr4_guest_host_mask = vmcs12->cr4_guest_host_mask;
1879          * evmcs->cr0_read_shadow = vmcs12->cr0_read_shadow;
1880          * evmcs->cr4_read_shadow = vmcs12->cr4_read_shadow;
1881          * evmcs->vm_exit_msr_store_count = vmcs12->vm_exit_msr_store_count;
1882          * evmcs->vm_exit_msr_load_count = vmcs12->vm_exit_msr_load_count;
1883          * evmcs->vm_entry_msr_load_count = vmcs12->vm_entry_msr_load_count;
1884          * evmcs->guest_ia32_perf_global_ctrl = vmcs12->guest_ia32_perf_global_ctrl;
1885          * evmcs->host_ia32_perf_global_ctrl = vmcs12->host_ia32_perf_global_ctrl;
1886          * evmcs->encls_exiting_bitmap = vmcs12->encls_exiting_bitmap;
1887          * evmcs->tsc_multiplier = vmcs12->tsc_multiplier;
1888          *
1889          * Not present in struct vmcs12:
1890          * evmcs->exit_io_instruction_ecx = vmcs12->exit_io_instruction_ecx;
1891          * evmcs->exit_io_instruction_esi = vmcs12->exit_io_instruction_esi;
1892          * evmcs->exit_io_instruction_edi = vmcs12->exit_io_instruction_edi;
1893          * evmcs->exit_io_instruction_eip = vmcs12->exit_io_instruction_eip;
1894          * evmcs->host_ia32_s_cet = vmcs12->host_ia32_s_cet;
1895          * evmcs->host_ssp = vmcs12->host_ssp;
1896          * evmcs->host_ia32_int_ssp_table_addr = vmcs12->host_ia32_int_ssp_table_addr;
1897          * evmcs->guest_ia32_s_cet = vmcs12->guest_ia32_s_cet;
1898          * evmcs->guest_ia32_lbr_ctl = vmcs12->guest_ia32_lbr_ctl;
1899          * evmcs->guest_ia32_int_ssp_table_addr = vmcs12->guest_ia32_int_ssp_table_addr;
1900          * evmcs->guest_ssp = vmcs12->guest_ssp;
1901          */
1902
1903         evmcs->guest_es_selector = vmcs12->guest_es_selector;
1904         evmcs->guest_cs_selector = vmcs12->guest_cs_selector;
1905         evmcs->guest_ss_selector = vmcs12->guest_ss_selector;
1906         evmcs->guest_ds_selector = vmcs12->guest_ds_selector;
1907         evmcs->guest_fs_selector = vmcs12->guest_fs_selector;
1908         evmcs->guest_gs_selector = vmcs12->guest_gs_selector;
1909         evmcs->guest_ldtr_selector = vmcs12->guest_ldtr_selector;
1910         evmcs->guest_tr_selector = vmcs12->guest_tr_selector;
1911
1912         evmcs->guest_es_limit = vmcs12->guest_es_limit;
1913         evmcs->guest_cs_limit = vmcs12->guest_cs_limit;
1914         evmcs->guest_ss_limit = vmcs12->guest_ss_limit;
1915         evmcs->guest_ds_limit = vmcs12->guest_ds_limit;
1916         evmcs->guest_fs_limit = vmcs12->guest_fs_limit;
1917         evmcs->guest_gs_limit = vmcs12->guest_gs_limit;
1918         evmcs->guest_ldtr_limit = vmcs12->guest_ldtr_limit;
1919         evmcs->guest_tr_limit = vmcs12->guest_tr_limit;
1920         evmcs->guest_gdtr_limit = vmcs12->guest_gdtr_limit;
1921         evmcs->guest_idtr_limit = vmcs12->guest_idtr_limit;
1922
1923         evmcs->guest_es_ar_bytes = vmcs12->guest_es_ar_bytes;
1924         evmcs->guest_cs_ar_bytes = vmcs12->guest_cs_ar_bytes;
1925         evmcs->guest_ss_ar_bytes = vmcs12->guest_ss_ar_bytes;
1926         evmcs->guest_ds_ar_bytes = vmcs12->guest_ds_ar_bytes;
1927         evmcs->guest_fs_ar_bytes = vmcs12->guest_fs_ar_bytes;
1928         evmcs->guest_gs_ar_bytes = vmcs12->guest_gs_ar_bytes;
1929         evmcs->guest_ldtr_ar_bytes = vmcs12->guest_ldtr_ar_bytes;
1930         evmcs->guest_tr_ar_bytes = vmcs12->guest_tr_ar_bytes;
1931
1932         evmcs->guest_es_base = vmcs12->guest_es_base;
1933         evmcs->guest_cs_base = vmcs12->guest_cs_base;
1934         evmcs->guest_ss_base = vmcs12->guest_ss_base;
1935         evmcs->guest_ds_base = vmcs12->guest_ds_base;
1936         evmcs->guest_fs_base = vmcs12->guest_fs_base;
1937         evmcs->guest_gs_base = vmcs12->guest_gs_base;
1938         evmcs->guest_ldtr_base = vmcs12->guest_ldtr_base;
1939         evmcs->guest_tr_base = vmcs12->guest_tr_base;
1940         evmcs->guest_gdtr_base = vmcs12->guest_gdtr_base;
1941         evmcs->guest_idtr_base = vmcs12->guest_idtr_base;
1942
1943         evmcs->guest_ia32_pat = vmcs12->guest_ia32_pat;
1944         evmcs->guest_ia32_efer = vmcs12->guest_ia32_efer;
1945
1946         evmcs->guest_pdptr0 = vmcs12->guest_pdptr0;
1947         evmcs->guest_pdptr1 = vmcs12->guest_pdptr1;
1948         evmcs->guest_pdptr2 = vmcs12->guest_pdptr2;
1949         evmcs->guest_pdptr3 = vmcs12->guest_pdptr3;
1950
1951         evmcs->guest_pending_dbg_exceptions =
1952                 vmcs12->guest_pending_dbg_exceptions;
1953         evmcs->guest_sysenter_esp = vmcs12->guest_sysenter_esp;
1954         evmcs->guest_sysenter_eip = vmcs12->guest_sysenter_eip;
1955
1956         evmcs->guest_activity_state = vmcs12->guest_activity_state;
1957         evmcs->guest_sysenter_cs = vmcs12->guest_sysenter_cs;
1958
1959         evmcs->guest_cr0 = vmcs12->guest_cr0;
1960         evmcs->guest_cr3 = vmcs12->guest_cr3;
1961         evmcs->guest_cr4 = vmcs12->guest_cr4;
1962         evmcs->guest_dr7 = vmcs12->guest_dr7;
1963
1964         evmcs->guest_physical_address = vmcs12->guest_physical_address;
1965
1966         evmcs->vm_instruction_error = vmcs12->vm_instruction_error;
1967         evmcs->vm_exit_reason = vmcs12->vm_exit_reason;
1968         evmcs->vm_exit_intr_info = vmcs12->vm_exit_intr_info;
1969         evmcs->vm_exit_intr_error_code = vmcs12->vm_exit_intr_error_code;
1970         evmcs->idt_vectoring_info_field = vmcs12->idt_vectoring_info_field;
1971         evmcs->idt_vectoring_error_code = vmcs12->idt_vectoring_error_code;
1972         evmcs->vm_exit_instruction_len = vmcs12->vm_exit_instruction_len;
1973         evmcs->vmx_instruction_info = vmcs12->vmx_instruction_info;
1974
1975         evmcs->exit_qualification = vmcs12->exit_qualification;
1976
1977         evmcs->guest_linear_address = vmcs12->guest_linear_address;
1978         evmcs->guest_rsp = vmcs12->guest_rsp;
1979         evmcs->guest_rflags = vmcs12->guest_rflags;
1980
1981         evmcs->guest_interruptibility_info =
1982                 vmcs12->guest_interruptibility_info;
1983         evmcs->cpu_based_vm_exec_control = vmcs12->cpu_based_vm_exec_control;
1984         evmcs->vm_entry_controls = vmcs12->vm_entry_controls;
1985         evmcs->vm_entry_intr_info_field = vmcs12->vm_entry_intr_info_field;
1986         evmcs->vm_entry_exception_error_code =
1987                 vmcs12->vm_entry_exception_error_code;
1988         evmcs->vm_entry_instruction_len = vmcs12->vm_entry_instruction_len;
1989
1990         evmcs->guest_rip = vmcs12->guest_rip;
1991
1992         evmcs->guest_bndcfgs = vmcs12->guest_bndcfgs;
1993
1994         return;
1995 }
1996
1997 /*
1998  * This is an equivalent of the nested hypervisor executing the vmptrld
1999  * instruction.
2000  */
2001 static enum nested_evmptrld_status nested_vmx_handle_enlightened_vmptrld(
2002         struct kvm_vcpu *vcpu, bool from_launch)
2003 {
2004         struct vcpu_vmx *vmx = to_vmx(vcpu);
2005         bool evmcs_gpa_changed = false;
2006         u64 evmcs_gpa;
2007
2008         if (likely(!guest_cpuid_has_evmcs(vcpu)))
2009                 return EVMPTRLD_DISABLED;
2010
2011         evmcs_gpa = nested_get_evmptr(vcpu);
2012         if (!evmptr_is_valid(evmcs_gpa)) {
2013                 nested_release_evmcs(vcpu);
2014                 return EVMPTRLD_DISABLED;
2015         }
2016
2017         if (unlikely(evmcs_gpa != vmx->nested.hv_evmcs_vmptr)) {
2018                 vmx->nested.current_vmptr = INVALID_GPA;
2019
2020                 nested_release_evmcs(vcpu);
2021
2022                 if (kvm_vcpu_map(vcpu, gpa_to_gfn(evmcs_gpa),
2023                                  &vmx->nested.hv_evmcs_map))
2024                         return EVMPTRLD_ERROR;
2025
2026                 vmx->nested.hv_evmcs = vmx->nested.hv_evmcs_map.hva;
2027
2028                 /*
2029                  * Currently, KVM only supports eVMCS version 1
2030                  * (== KVM_EVMCS_VERSION) and thus we expect guest to set this
2031                  * value to first u32 field of eVMCS which should specify eVMCS
2032                  * VersionNumber.
2033                  *
2034                  * Guest should be aware of supported eVMCS versions by host by
2035                  * examining CPUID.0x4000000A.EAX[0:15]. Host userspace VMM is
2036                  * expected to set this CPUID leaf according to the value
2037                  * returned in vmcs_version from nested_enable_evmcs().
2038                  *
2039                  * However, it turns out that Microsoft Hyper-V fails to comply
2040                  * to their own invented interface: When Hyper-V use eVMCS, it
2041                  * just sets first u32 field of eVMCS to revision_id specified
2042                  * in MSR_IA32_VMX_BASIC. Instead of used eVMCS version number
2043                  * which is one of the supported versions specified in
2044                  * CPUID.0x4000000A.EAX[0:15].
2045                  *
2046                  * To overcome Hyper-V bug, we accept here either a supported
2047                  * eVMCS version or VMCS12 revision_id as valid values for first
2048                  * u32 field of eVMCS.
2049                  */
2050                 if ((vmx->nested.hv_evmcs->revision_id != KVM_EVMCS_VERSION) &&
2051                     (vmx->nested.hv_evmcs->revision_id != VMCS12_REVISION)) {
2052                         nested_release_evmcs(vcpu);
2053                         return EVMPTRLD_VMFAIL;
2054                 }
2055
2056                 vmx->nested.hv_evmcs_vmptr = evmcs_gpa;
2057
2058                 evmcs_gpa_changed = true;
2059                 /*
2060                  * Unlike normal vmcs12, enlightened vmcs12 is not fully
2061                  * reloaded from guest's memory (read only fields, fields not
2062                  * present in struct hv_enlightened_vmcs, ...). Make sure there
2063                  * are no leftovers.
2064                  */
2065                 if (from_launch) {
2066                         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2067                         memset(vmcs12, 0, sizeof(*vmcs12));
2068                         vmcs12->hdr.revision_id = VMCS12_REVISION;
2069                 }
2070
2071         }
2072
2073         /*
2074          * Clean fields data can't be used on VMLAUNCH and when we switch
2075          * between different L2 guests as KVM keeps a single VMCS12 per L1.
2076          */
2077         if (from_launch || evmcs_gpa_changed) {
2078                 vmx->nested.hv_evmcs->hv_clean_fields &=
2079                         ~HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
2080
2081                 vmx->nested.force_msr_bitmap_recalc = true;
2082         }
2083
2084         return EVMPTRLD_SUCCEEDED;
2085 }
2086
2087 void nested_sync_vmcs12_to_shadow(struct kvm_vcpu *vcpu)
2088 {
2089         struct vcpu_vmx *vmx = to_vmx(vcpu);
2090
2091         if (evmptr_is_valid(vmx->nested.hv_evmcs_vmptr))
2092                 copy_vmcs12_to_enlightened(vmx);
2093         else
2094                 copy_vmcs12_to_shadow(vmx);
2095
2096         vmx->nested.need_vmcs12_to_shadow_sync = false;
2097 }
2098
2099 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
2100 {
2101         struct vcpu_vmx *vmx =
2102                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
2103
2104         vmx->nested.preemption_timer_expired = true;
2105         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
2106         kvm_vcpu_kick(&vmx->vcpu);
2107
2108         return HRTIMER_NORESTART;
2109 }
2110
2111 static u64 vmx_calc_preemption_timer_value(struct kvm_vcpu *vcpu)
2112 {
2113         struct vcpu_vmx *vmx = to_vmx(vcpu);
2114         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2115
2116         u64 l1_scaled_tsc = kvm_read_l1_tsc(vcpu, rdtsc()) >>
2117                             VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
2118
2119         if (!vmx->nested.has_preemption_timer_deadline) {
2120                 vmx->nested.preemption_timer_deadline =
2121                         vmcs12->vmx_preemption_timer_value + l1_scaled_tsc;
2122                 vmx->nested.has_preemption_timer_deadline = true;
2123         }
2124         return vmx->nested.preemption_timer_deadline - l1_scaled_tsc;
2125 }
2126
2127 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu,
2128                                         u64 preemption_timeout)
2129 {
2130         struct vcpu_vmx *vmx = to_vmx(vcpu);
2131
2132         /*
2133          * A timer value of zero is architecturally guaranteed to cause
2134          * a VMExit prior to executing any instructions in the guest.
2135          */
2136         if (preemption_timeout == 0) {
2137                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
2138                 return;
2139         }
2140
2141         if (vcpu->arch.virtual_tsc_khz == 0)
2142                 return;
2143
2144         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
2145         preemption_timeout *= 1000000;
2146         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
2147         hrtimer_start(&vmx->nested.preemption_timer,
2148                       ktime_add_ns(ktime_get(), preemption_timeout),
2149                       HRTIMER_MODE_ABS_PINNED);
2150 }
2151
2152 static u64 nested_vmx_calc_efer(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12)
2153 {
2154         if (vmx->nested.nested_run_pending &&
2155             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
2156                 return vmcs12->guest_ia32_efer;
2157         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
2158                 return vmx->vcpu.arch.efer | (EFER_LMA | EFER_LME);
2159         else
2160                 return vmx->vcpu.arch.efer & ~(EFER_LMA | EFER_LME);
2161 }
2162
2163 static void prepare_vmcs02_constant_state(struct vcpu_vmx *vmx)
2164 {
2165         struct kvm *kvm = vmx->vcpu.kvm;
2166
2167         /*
2168          * If vmcs02 hasn't been initialized, set the constant vmcs02 state
2169          * according to L0's settings (vmcs12 is irrelevant here).  Host
2170          * fields that come from L0 and are not constant, e.g. HOST_CR3,
2171          * will be set as needed prior to VMLAUNCH/VMRESUME.
2172          */
2173         if (vmx->nested.vmcs02_initialized)
2174                 return;
2175         vmx->nested.vmcs02_initialized = true;
2176
2177         /*
2178          * We don't care what the EPTP value is we just need to guarantee
2179          * it's valid so we don't get a false positive when doing early
2180          * consistency checks.
2181          */
2182         if (enable_ept && nested_early_check)
2183                 vmcs_write64(EPT_POINTER,
2184                              construct_eptp(&vmx->vcpu, 0, PT64_ROOT_4LEVEL));
2185
2186         /* All VMFUNCs are currently emulated through L0 vmexits.  */
2187         if (cpu_has_vmx_vmfunc())
2188                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
2189
2190         if (cpu_has_vmx_posted_intr())
2191                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR);
2192
2193         if (cpu_has_vmx_msr_bitmap())
2194                 vmcs_write64(MSR_BITMAP, __pa(vmx->nested.vmcs02.msr_bitmap));
2195
2196         /*
2197          * PML is emulated for L2, but never enabled in hardware as the MMU
2198          * handles A/D emulation.  Disabling PML for L2 also avoids having to
2199          * deal with filtering out L2 GPAs from the buffer.
2200          */
2201         if (enable_pml) {
2202                 vmcs_write64(PML_ADDRESS, 0);
2203                 vmcs_write16(GUEST_PML_INDEX, -1);
2204         }
2205
2206         if (cpu_has_vmx_encls_vmexit())
2207                 vmcs_write64(ENCLS_EXITING_BITMAP, INVALID_GPA);
2208
2209         if (kvm_notify_vmexit_enabled(kvm))
2210                 vmcs_write32(NOTIFY_WINDOW, kvm->arch.notify_window);
2211
2212         /*
2213          * Set the MSR load/store lists to match L0's settings.  Only the
2214          * addresses are constant (for vmcs02), the counts can change based
2215          * on L2's behavior, e.g. switching to/from long mode.
2216          */
2217         vmcs_write64(VM_EXIT_MSR_STORE_ADDR, __pa(vmx->msr_autostore.guest.val));
2218         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
2219         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
2220
2221         vmx_set_constant_host_state(vmx);
2222 }
2223
2224 static void prepare_vmcs02_early_rare(struct vcpu_vmx *vmx,
2225                                       struct vmcs12 *vmcs12)
2226 {
2227         prepare_vmcs02_constant_state(vmx);
2228
2229         vmcs_write64(VMCS_LINK_POINTER, INVALID_GPA);
2230
2231         if (enable_vpid) {
2232                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02)
2233                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
2234                 else
2235                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2236         }
2237 }
2238
2239 static void prepare_vmcs02_early(struct vcpu_vmx *vmx, struct loaded_vmcs *vmcs01,
2240                                  struct vmcs12 *vmcs12)
2241 {
2242         u32 exec_control;
2243         u64 guest_efer = nested_vmx_calc_efer(vmx, vmcs12);
2244
2245         if (vmx->nested.dirty_vmcs12 || evmptr_is_valid(vmx->nested.hv_evmcs_vmptr))
2246                 prepare_vmcs02_early_rare(vmx, vmcs12);
2247
2248         /*
2249          * PIN CONTROLS
2250          */
2251         exec_control = __pin_controls_get(vmcs01);
2252         exec_control |= (vmcs12->pin_based_vm_exec_control &
2253                          ~PIN_BASED_VMX_PREEMPTION_TIMER);
2254
2255         /* Posted interrupts setting is only taken from vmcs12.  */
2256         vmx->nested.pi_pending = false;
2257         if (nested_cpu_has_posted_intr(vmcs12))
2258                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
2259         else
2260                 exec_control &= ~PIN_BASED_POSTED_INTR;
2261         pin_controls_set(vmx, exec_control);
2262
2263         /*
2264          * EXEC CONTROLS
2265          */
2266         exec_control = __exec_controls_get(vmcs01); /* L0's desires */
2267         exec_control &= ~CPU_BASED_INTR_WINDOW_EXITING;
2268         exec_control &= ~CPU_BASED_NMI_WINDOW_EXITING;
2269         exec_control &= ~CPU_BASED_TPR_SHADOW;
2270         exec_control |= vmcs12->cpu_based_vm_exec_control;
2271
2272         vmx->nested.l1_tpr_threshold = -1;
2273         if (exec_control & CPU_BASED_TPR_SHADOW)
2274                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
2275 #ifdef CONFIG_X86_64
2276         else
2277                 exec_control |= CPU_BASED_CR8_LOAD_EXITING |
2278                                 CPU_BASED_CR8_STORE_EXITING;
2279 #endif
2280
2281         /*
2282          * A vmexit (to either L1 hypervisor or L0 userspace) is always needed
2283          * for I/O port accesses.
2284          */
2285         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
2286         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
2287
2288         /*
2289          * This bit will be computed in nested_get_vmcs12_pages, because
2290          * we do not have access to L1's MSR bitmap yet.  For now, keep
2291          * the same bit as before, hoping to avoid multiple VMWRITEs that
2292          * only set/clear this bit.
2293          */
2294         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
2295         exec_control |= exec_controls_get(vmx) & CPU_BASED_USE_MSR_BITMAPS;
2296
2297         exec_controls_set(vmx, exec_control);
2298
2299         /*
2300          * SECONDARY EXEC CONTROLS
2301          */
2302         if (cpu_has_secondary_exec_ctrls()) {
2303                 exec_control = __secondary_exec_controls_get(vmcs01);
2304
2305                 /* Take the following fields only from vmcs12 */
2306                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2307                                   SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2308                                   SECONDARY_EXEC_ENABLE_INVPCID |
2309                                   SECONDARY_EXEC_ENABLE_RDTSCP |
2310                                   SECONDARY_EXEC_XSAVES |
2311                                   SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
2312                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2313                                   SECONDARY_EXEC_APIC_REGISTER_VIRT |
2314                                   SECONDARY_EXEC_ENABLE_VMFUNC |
2315                                   SECONDARY_EXEC_DESC);
2316
2317                 if (nested_cpu_has(vmcs12,
2318                                    CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
2319                         exec_control |= vmcs12->secondary_vm_exec_control;
2320
2321                 /* PML is emulated and never enabled in hardware for L2. */
2322                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
2323
2324                 /* VMCS shadowing for L2 is emulated for now */
2325                 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
2326
2327                 /*
2328                  * Preset *DT exiting when emulating UMIP, so that vmx_set_cr4()
2329                  * will not have to rewrite the controls just for this bit.
2330                  */
2331                 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated() &&
2332                     (vmcs12->guest_cr4 & X86_CR4_UMIP))
2333                         exec_control |= SECONDARY_EXEC_DESC;
2334
2335                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
2336                         vmcs_write16(GUEST_INTR_STATUS,
2337                                 vmcs12->guest_intr_status);
2338
2339                 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
2340                     exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2341
2342                 if (exec_control & SECONDARY_EXEC_ENCLS_EXITING)
2343                         vmx_write_encls_bitmap(&vmx->vcpu, vmcs12);
2344
2345                 secondary_exec_controls_set(vmx, exec_control);
2346         }
2347
2348         /*
2349          * ENTRY CONTROLS
2350          *
2351          * vmcs12's VM_{ENTRY,EXIT}_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE
2352          * are emulated by vmx_set_efer() in prepare_vmcs02(), but speculate
2353          * on the related bits (if supported by the CPU) in the hope that
2354          * we can avoid VMWrites during vmx_set_efer().
2355          *
2356          * Similarly, take vmcs01's PERF_GLOBAL_CTRL in the hope that if KVM is
2357          * loading PERF_GLOBAL_CTRL via the VMCS for L1, then KVM will want to
2358          * do the same for L2.
2359          */
2360         exec_control = __vm_entry_controls_get(vmcs01);
2361         exec_control |= (vmcs12->vm_entry_controls &
2362                          ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL);
2363         exec_control &= ~(VM_ENTRY_IA32E_MODE | VM_ENTRY_LOAD_IA32_EFER);
2364         if (cpu_has_load_ia32_efer()) {
2365                 if (guest_efer & EFER_LMA)
2366                         exec_control |= VM_ENTRY_IA32E_MODE;
2367                 if (guest_efer != host_efer)
2368                         exec_control |= VM_ENTRY_LOAD_IA32_EFER;
2369         }
2370         vm_entry_controls_set(vmx, exec_control);
2371
2372         /*
2373          * EXIT CONTROLS
2374          *
2375          * L2->L1 exit controls are emulated - the hardware exit is to L0 so
2376          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
2377          * bits may be modified by vmx_set_efer() in prepare_vmcs02().
2378          */
2379         exec_control = __vm_exit_controls_get(vmcs01);
2380         if (cpu_has_load_ia32_efer() && guest_efer != host_efer)
2381                 exec_control |= VM_EXIT_LOAD_IA32_EFER;
2382         else
2383                 exec_control &= ~VM_EXIT_LOAD_IA32_EFER;
2384         vm_exit_controls_set(vmx, exec_control);
2385
2386         /*
2387          * Interrupt/Exception Fields
2388          */
2389         if (vmx->nested.nested_run_pending) {
2390                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2391                              vmcs12->vm_entry_intr_info_field);
2392                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2393                              vmcs12->vm_entry_exception_error_code);
2394                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2395                              vmcs12->vm_entry_instruction_len);
2396                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
2397                              vmcs12->guest_interruptibility_info);
2398                 vmx->loaded_vmcs->nmi_known_unmasked =
2399                         !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI);
2400         } else {
2401                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
2402         }
2403 }
2404
2405 static void prepare_vmcs02_rare(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12)
2406 {
2407         struct hv_enlightened_vmcs *hv_evmcs = vmx->nested.hv_evmcs;
2408
2409         if (!hv_evmcs || !(hv_evmcs->hv_clean_fields &
2410                            HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2)) {
2411                 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
2412                 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
2413                 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
2414                 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
2415                 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
2416                 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
2417                 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
2418                 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
2419                 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
2420                 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
2421                 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
2422                 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
2423                 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
2424                 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
2425                 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
2426                 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
2427                 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
2428                 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
2429                 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
2430                 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
2431                 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
2432                 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
2433                 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
2434                 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
2435                 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
2436                 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
2437                 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
2438                 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
2439                 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
2440                 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
2441                 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
2442                 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
2443                 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
2444                 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
2445                 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
2446                 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
2447
2448                 vmx->segment_cache.bitmask = 0;
2449         }
2450
2451         if (!hv_evmcs || !(hv_evmcs->hv_clean_fields &
2452                            HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1)) {
2453                 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
2454                 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
2455                             vmcs12->guest_pending_dbg_exceptions);
2456                 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
2457                 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
2458
2459                 /*
2460                  * L1 may access the L2's PDPTR, so save them to construct
2461                  * vmcs12
2462                  */
2463                 if (enable_ept) {
2464                         vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
2465                         vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
2466                         vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
2467                         vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
2468                 }
2469
2470                 if (kvm_mpx_supported() && vmx->nested.nested_run_pending &&
2471                     (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS))
2472                         vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
2473         }
2474
2475         if (nested_cpu_has_xsaves(vmcs12))
2476                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
2477
2478         /*
2479          * Whether page-faults are trapped is determined by a combination of
2480          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.  If L0
2481          * doesn't care about page faults then we should set all of these to
2482          * L1's desires. However, if L0 does care about (some) page faults, it
2483          * is not easy (if at all possible?) to merge L0 and L1's desires, we
2484          * simply ask to exit on each and every L2 page fault. This is done by
2485          * setting MASK=MATCH=0 and (see below) EB.PF=1.
2486          * Note that below we don't need special code to set EB.PF beyond the
2487          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
2488          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
2489          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
2490          */
2491         if (vmx_need_pf_intercept(&vmx->vcpu)) {
2492                 /*
2493                  * TODO: if both L0 and L1 need the same MASK and MATCH,
2494                  * go ahead and use it?
2495                  */
2496                 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
2497                 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
2498         } else {
2499                 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, vmcs12->page_fault_error_code_mask);
2500                 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, vmcs12->page_fault_error_code_match);
2501         }
2502
2503         if (cpu_has_vmx_apicv()) {
2504                 vmcs_write64(EOI_EXIT_BITMAP0, vmcs12->eoi_exit_bitmap0);
2505                 vmcs_write64(EOI_EXIT_BITMAP1, vmcs12->eoi_exit_bitmap1);
2506                 vmcs_write64(EOI_EXIT_BITMAP2, vmcs12->eoi_exit_bitmap2);
2507                 vmcs_write64(EOI_EXIT_BITMAP3, vmcs12->eoi_exit_bitmap3);
2508         }
2509
2510         /*
2511          * Make sure the msr_autostore list is up to date before we set the
2512          * count in the vmcs02.
2513          */
2514         prepare_vmx_msr_autostore_list(&vmx->vcpu, MSR_IA32_TSC);
2515
2516         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, vmx->msr_autostore.guest.nr);
2517         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr);
2518         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr);
2519
2520         set_cr4_guest_host_mask(vmx);
2521 }
2522
2523 /*
2524  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
2525  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
2526  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
2527  * guest in a way that will both be appropriate to L1's requests, and our
2528  * needs. In addition to modifying the active vmcs (which is vmcs02), this
2529  * function also has additional necessary side-effects, like setting various
2530  * vcpu->arch fields.
2531  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
2532  * is assigned to entry_failure_code on failure.
2533  */
2534 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
2535                           bool from_vmentry,
2536                           enum vm_entry_failure_code *entry_failure_code)
2537 {
2538         struct vcpu_vmx *vmx = to_vmx(vcpu);
2539         bool load_guest_pdptrs_vmcs12 = false;
2540
2541         if (vmx->nested.dirty_vmcs12 || evmptr_is_valid(vmx->nested.hv_evmcs_vmptr)) {
2542                 prepare_vmcs02_rare(vmx, vmcs12);
2543                 vmx->nested.dirty_vmcs12 = false;
2544
2545                 load_guest_pdptrs_vmcs12 = !evmptr_is_valid(vmx->nested.hv_evmcs_vmptr) ||
2546                         !(vmx->nested.hv_evmcs->hv_clean_fields &
2547                           HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1);
2548         }
2549
2550         if (vmx->nested.nested_run_pending &&
2551             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
2552                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
2553                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
2554         } else {
2555                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
2556                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.pre_vmenter_debugctl);
2557         }
2558         if (kvm_mpx_supported() && (!vmx->nested.nested_run_pending ||
2559             !(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)))
2560                 vmcs_write64(GUEST_BNDCFGS, vmx->nested.pre_vmenter_bndcfgs);
2561         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
2562
2563         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
2564          * bitwise-or of what L1 wants to trap for L2, and what we want to
2565          * trap. Note that CR0.TS also needs updating - we do this later.
2566          */
2567         vmx_update_exception_bitmap(vcpu);
2568         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
2569         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2570
2571         if (vmx->nested.nested_run_pending &&
2572             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
2573                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
2574                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
2575         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2576                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
2577         }
2578
2579         vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset(
2580                         vcpu->arch.l1_tsc_offset,
2581                         vmx_get_l2_tsc_offset(vcpu),
2582                         vmx_get_l2_tsc_multiplier(vcpu));
2583
2584         vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier(
2585                         vcpu->arch.l1_tsc_scaling_ratio,
2586                         vmx_get_l2_tsc_multiplier(vcpu));
2587
2588         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
2589         if (kvm_caps.has_tsc_control)
2590                 vmcs_write64(TSC_MULTIPLIER, vcpu->arch.tsc_scaling_ratio);
2591
2592         nested_vmx_transition_tlb_flush(vcpu, vmcs12, true);
2593
2594         if (nested_cpu_has_ept(vmcs12))
2595                 nested_ept_init_mmu_context(vcpu);
2596
2597         /*
2598          * Override the CR0/CR4 read shadows after setting the effective guest
2599          * CR0/CR4.  The common helpers also set the shadows, but they don't
2600          * account for vmcs12's cr0/4_guest_host_mask.
2601          */
2602         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
2603         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2604
2605         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
2606         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
2607
2608         vcpu->arch.efer = nested_vmx_calc_efer(vmx, vmcs12);
2609         /* Note: may modify VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
2610         vmx_set_efer(vcpu, vcpu->arch.efer);
2611
2612         /*
2613          * Guest state is invalid and unrestricted guest is disabled,
2614          * which means L1 attempted VMEntry to L2 with invalid state.
2615          * Fail the VMEntry.
2616          *
2617          * However when force loading the guest state (SMM exit or
2618          * loading nested state after migration, it is possible to
2619          * have invalid guest state now, which will be later fixed by
2620          * restoring L2 register state
2621          */
2622         if (CC(from_vmentry && !vmx_guest_state_valid(vcpu))) {
2623                 *entry_failure_code = ENTRY_FAIL_DEFAULT;
2624                 return -EINVAL;
2625         }
2626
2627         /* Shadow page tables on either EPT or shadow page tables. */
2628         if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
2629                                 from_vmentry, entry_failure_code))
2630                 return -EINVAL;
2631
2632         /*
2633          * Immediately write vmcs02.GUEST_CR3.  It will be propagated to vmcs12
2634          * on nested VM-Exit, which can occur without actually running L2 and
2635          * thus without hitting vmx_load_mmu_pgd(), e.g. if L1 is entering L2 with
2636          * vmcs12.GUEST_ACTIVITYSTATE=HLT, in which case KVM will intercept the
2637          * transition to HLT instead of running L2.
2638          */
2639         if (enable_ept)
2640                 vmcs_writel(GUEST_CR3, vmcs12->guest_cr3);
2641
2642         /* Late preparation of GUEST_PDPTRs now that EFER and CRs are set. */
2643         if (load_guest_pdptrs_vmcs12 && nested_cpu_has_ept(vmcs12) &&
2644             is_pae_paging(vcpu)) {
2645                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
2646                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
2647                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
2648                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
2649         }
2650
2651         if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) &&
2652             intel_pmu_has_perf_global_ctrl(vcpu_to_pmu(vcpu)) &&
2653             WARN_ON_ONCE(kvm_set_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL,
2654                                      vmcs12->guest_ia32_perf_global_ctrl))) {
2655                 *entry_failure_code = ENTRY_FAIL_DEFAULT;
2656                 return -EINVAL;
2657         }
2658
2659         kvm_rsp_write(vcpu, vmcs12->guest_rsp);
2660         kvm_rip_write(vcpu, vmcs12->guest_rip);
2661
2662         /*
2663          * It was observed that genuine Hyper-V running in L1 doesn't reset
2664          * 'hv_clean_fields' by itself, it only sets the corresponding dirty
2665          * bits when it changes a field in eVMCS. Mark all fields as clean
2666          * here.
2667          */
2668         if (evmptr_is_valid(vmx->nested.hv_evmcs_vmptr))
2669                 vmx->nested.hv_evmcs->hv_clean_fields |=
2670                         HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
2671
2672         return 0;
2673 }
2674
2675 static int nested_vmx_check_nmi_controls(struct vmcs12 *vmcs12)
2676 {
2677         if (CC(!nested_cpu_has_nmi_exiting(vmcs12) &&
2678                nested_cpu_has_virtual_nmis(vmcs12)))
2679                 return -EINVAL;
2680
2681         if (CC(!nested_cpu_has_virtual_nmis(vmcs12) &&
2682                nested_cpu_has(vmcs12, CPU_BASED_NMI_WINDOW_EXITING)))
2683                 return -EINVAL;
2684
2685         return 0;
2686 }
2687
2688 static bool nested_vmx_check_eptp(struct kvm_vcpu *vcpu, u64 new_eptp)
2689 {
2690         struct vcpu_vmx *vmx = to_vmx(vcpu);
2691
2692         /* Check for memory type validity */
2693         switch (new_eptp & VMX_EPTP_MT_MASK) {
2694         case VMX_EPTP_MT_UC:
2695                 if (CC(!(vmx->nested.msrs.ept_caps & VMX_EPTP_UC_BIT)))
2696                         return false;
2697                 break;
2698         case VMX_EPTP_MT_WB:
2699                 if (CC(!(vmx->nested.msrs.ept_caps & VMX_EPTP_WB_BIT)))
2700                         return false;
2701                 break;
2702         default:
2703                 return false;
2704         }
2705
2706         /* Page-walk levels validity. */
2707         switch (new_eptp & VMX_EPTP_PWL_MASK) {
2708         case VMX_EPTP_PWL_5:
2709                 if (CC(!(vmx->nested.msrs.ept_caps & VMX_EPT_PAGE_WALK_5_BIT)))
2710                         return false;
2711                 break;
2712         case VMX_EPTP_PWL_4:
2713                 if (CC(!(vmx->nested.msrs.ept_caps & VMX_EPT_PAGE_WALK_4_BIT)))
2714                         return false;
2715                 break;
2716         default:
2717                 return false;
2718         }
2719
2720         /* Reserved bits should not be set */
2721         if (CC(kvm_vcpu_is_illegal_gpa(vcpu, new_eptp) || ((new_eptp >> 7) & 0x1f)))
2722                 return false;
2723
2724         /* AD, if set, should be supported */
2725         if (new_eptp & VMX_EPTP_AD_ENABLE_BIT) {
2726                 if (CC(!(vmx->nested.msrs.ept_caps & VMX_EPT_AD_BIT)))
2727                         return false;
2728         }
2729
2730         return true;
2731 }
2732
2733 /*
2734  * Checks related to VM-Execution Control Fields
2735  */
2736 static int nested_check_vm_execution_controls(struct kvm_vcpu *vcpu,
2737                                               struct vmcs12 *vmcs12)
2738 {
2739         struct vcpu_vmx *vmx = to_vmx(vcpu);
2740
2741         if (CC(!vmx_control_verify(vmcs12->pin_based_vm_exec_control,
2742                                    vmx->nested.msrs.pinbased_ctls_low,
2743                                    vmx->nested.msrs.pinbased_ctls_high)) ||
2744             CC(!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
2745                                    vmx->nested.msrs.procbased_ctls_low,
2746                                    vmx->nested.msrs.procbased_ctls_high)))
2747                 return -EINVAL;
2748
2749         if (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
2750             CC(!vmx_control_verify(vmcs12->secondary_vm_exec_control,
2751                                    vmx->nested.msrs.secondary_ctls_low,
2752                                    vmx->nested.msrs.secondary_ctls_high)))
2753                 return -EINVAL;
2754
2755         if (CC(vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu)) ||
2756             nested_vmx_check_io_bitmap_controls(vcpu, vmcs12) ||
2757             nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12) ||
2758             nested_vmx_check_tpr_shadow_controls(vcpu, vmcs12) ||
2759             nested_vmx_check_apic_access_controls(vcpu, vmcs12) ||
2760             nested_vmx_check_apicv_controls(vcpu, vmcs12) ||
2761             nested_vmx_check_nmi_controls(vmcs12) ||
2762             nested_vmx_check_pml_controls(vcpu, vmcs12) ||
2763             nested_vmx_check_unrestricted_guest_controls(vcpu, vmcs12) ||
2764             nested_vmx_check_mode_based_ept_exec_controls(vcpu, vmcs12) ||
2765             nested_vmx_check_shadow_vmcs_controls(vcpu, vmcs12) ||
2766             CC(nested_cpu_has_vpid(vmcs12) && !vmcs12->virtual_processor_id))
2767                 return -EINVAL;
2768
2769         if (!nested_cpu_has_preemption_timer(vmcs12) &&
2770             nested_cpu_has_save_preemption_timer(vmcs12))
2771                 return -EINVAL;
2772
2773         if (nested_cpu_has_ept(vmcs12) &&
2774             CC(!nested_vmx_check_eptp(vcpu, vmcs12->ept_pointer)))
2775                 return -EINVAL;
2776
2777         if (nested_cpu_has_vmfunc(vmcs12)) {
2778                 if (CC(vmcs12->vm_function_control &
2779                        ~vmx->nested.msrs.vmfunc_controls))
2780                         return -EINVAL;
2781
2782                 if (nested_cpu_has_eptp_switching(vmcs12)) {
2783                         if (CC(!nested_cpu_has_ept(vmcs12)) ||
2784                             CC(!page_address_valid(vcpu, vmcs12->eptp_list_address)))
2785                                 return -EINVAL;
2786                 }
2787         }
2788
2789         return 0;
2790 }
2791
2792 /*
2793  * Checks related to VM-Exit Control Fields
2794  */
2795 static int nested_check_vm_exit_controls(struct kvm_vcpu *vcpu,
2796                                          struct vmcs12 *vmcs12)
2797 {
2798         struct vcpu_vmx *vmx = to_vmx(vcpu);
2799
2800         if (CC(!vmx_control_verify(vmcs12->vm_exit_controls,
2801                                     vmx->nested.msrs.exit_ctls_low,
2802                                     vmx->nested.msrs.exit_ctls_high)) ||
2803             CC(nested_vmx_check_exit_msr_switch_controls(vcpu, vmcs12)))
2804                 return -EINVAL;
2805
2806         return 0;
2807 }
2808
2809 /*
2810  * Checks related to VM-Entry Control Fields
2811  */
2812 static int nested_check_vm_entry_controls(struct kvm_vcpu *vcpu,
2813                                           struct vmcs12 *vmcs12)
2814 {
2815         struct vcpu_vmx *vmx = to_vmx(vcpu);
2816
2817         if (CC(!vmx_control_verify(vmcs12->vm_entry_controls,
2818                                     vmx->nested.msrs.entry_ctls_low,
2819                                     vmx->nested.msrs.entry_ctls_high)))
2820                 return -EINVAL;
2821
2822         /*
2823          * From the Intel SDM, volume 3:
2824          * Fields relevant to VM-entry event injection must be set properly.
2825          * These fields are the VM-entry interruption-information field, the
2826          * VM-entry exception error code, and the VM-entry instruction length.
2827          */
2828         if (vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK) {
2829                 u32 intr_info = vmcs12->vm_entry_intr_info_field;
2830                 u8 vector = intr_info & INTR_INFO_VECTOR_MASK;
2831                 u32 intr_type = intr_info & INTR_INFO_INTR_TYPE_MASK;
2832                 bool has_error_code = intr_info & INTR_INFO_DELIVER_CODE_MASK;
2833                 bool should_have_error_code;
2834                 bool urg = nested_cpu_has2(vmcs12,
2835                                            SECONDARY_EXEC_UNRESTRICTED_GUEST);
2836                 bool prot_mode = !urg || vmcs12->guest_cr0 & X86_CR0_PE;
2837
2838                 /* VM-entry interruption-info field: interruption type */
2839                 if (CC(intr_type == INTR_TYPE_RESERVED) ||
2840                     CC(intr_type == INTR_TYPE_OTHER_EVENT &&
2841                        !nested_cpu_supports_monitor_trap_flag(vcpu)))
2842                         return -EINVAL;
2843
2844                 /* VM-entry interruption-info field: vector */
2845                 if (CC(intr_type == INTR_TYPE_NMI_INTR && vector != NMI_VECTOR) ||
2846                     CC(intr_type == INTR_TYPE_HARD_EXCEPTION && vector > 31) ||
2847                     CC(intr_type == INTR_TYPE_OTHER_EVENT && vector != 0))
2848                         return -EINVAL;
2849
2850                 /* VM-entry interruption-info field: deliver error code */
2851                 should_have_error_code =
2852                         intr_type == INTR_TYPE_HARD_EXCEPTION && prot_mode &&
2853                         x86_exception_has_error_code(vector);
2854                 if (CC(has_error_code != should_have_error_code))
2855                         return -EINVAL;
2856
2857                 /* VM-entry exception error code */
2858                 if (CC(has_error_code &&
2859                        vmcs12->vm_entry_exception_error_code & GENMASK(31, 16)))
2860                         return -EINVAL;
2861
2862                 /* VM-entry interruption-info field: reserved bits */
2863                 if (CC(intr_info & INTR_INFO_RESVD_BITS_MASK))
2864                         return -EINVAL;
2865
2866                 /* VM-entry instruction length */
2867                 switch (intr_type) {
2868                 case INTR_TYPE_SOFT_EXCEPTION:
2869                 case INTR_TYPE_SOFT_INTR:
2870                 case INTR_TYPE_PRIV_SW_EXCEPTION:
2871                         if (CC(vmcs12->vm_entry_instruction_len > 15) ||
2872                             CC(vmcs12->vm_entry_instruction_len == 0 &&
2873                             CC(!nested_cpu_has_zero_length_injection(vcpu))))
2874                                 return -EINVAL;
2875                 }
2876         }
2877
2878         if (nested_vmx_check_entry_msr_switch_controls(vcpu, vmcs12))
2879                 return -EINVAL;
2880
2881         return 0;
2882 }
2883
2884 static int nested_vmx_check_controls(struct kvm_vcpu *vcpu,
2885                                      struct vmcs12 *vmcs12)
2886 {
2887         if (nested_check_vm_execution_controls(vcpu, vmcs12) ||
2888             nested_check_vm_exit_controls(vcpu, vmcs12) ||
2889             nested_check_vm_entry_controls(vcpu, vmcs12))
2890                 return -EINVAL;
2891
2892         if (guest_cpuid_has_evmcs(vcpu))
2893                 return nested_evmcs_check_controls(vmcs12);
2894
2895         return 0;
2896 }
2897
2898 static int nested_vmx_check_address_space_size(struct kvm_vcpu *vcpu,
2899                                        struct vmcs12 *vmcs12)
2900 {
2901 #ifdef CONFIG_X86_64
2902         if (CC(!!(vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) !=
2903                 !!(vcpu->arch.efer & EFER_LMA)))
2904                 return -EINVAL;
2905 #endif
2906         return 0;
2907 }
2908
2909 static int nested_vmx_check_host_state(struct kvm_vcpu *vcpu,
2910                                        struct vmcs12 *vmcs12)
2911 {
2912         bool ia32e = !!(vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE);
2913
2914         if (CC(!nested_host_cr0_valid(vcpu, vmcs12->host_cr0)) ||
2915             CC(!nested_host_cr4_valid(vcpu, vmcs12->host_cr4)) ||
2916             CC(kvm_vcpu_is_illegal_gpa(vcpu, vmcs12->host_cr3)))
2917                 return -EINVAL;
2918
2919         if (CC(is_noncanonical_address(vmcs12->host_ia32_sysenter_esp, vcpu)) ||
2920             CC(is_noncanonical_address(vmcs12->host_ia32_sysenter_eip, vcpu)))
2921                 return -EINVAL;
2922
2923         if ((vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) &&
2924             CC(!kvm_pat_valid(vmcs12->host_ia32_pat)))
2925                 return -EINVAL;
2926
2927         if ((vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) &&
2928             CC(!kvm_valid_perf_global_ctrl(vcpu_to_pmu(vcpu),
2929                                            vmcs12->host_ia32_perf_global_ctrl)))
2930                 return -EINVAL;
2931
2932         if (ia32e) {
2933                 if (CC(!(vmcs12->host_cr4 & X86_CR4_PAE)))
2934                         return -EINVAL;
2935         } else {
2936                 if (CC(vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) ||
2937                     CC(vmcs12->host_cr4 & X86_CR4_PCIDE) ||
2938                     CC((vmcs12->host_rip) >> 32))
2939                         return -EINVAL;
2940         }
2941
2942         if (CC(vmcs12->host_cs_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) ||
2943             CC(vmcs12->host_ss_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) ||
2944             CC(vmcs12->host_ds_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) ||
2945             CC(vmcs12->host_es_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) ||
2946             CC(vmcs12->host_fs_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) ||
2947             CC(vmcs12->host_gs_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) ||
2948             CC(vmcs12->host_tr_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) ||
2949             CC(vmcs12->host_cs_selector == 0) ||
2950             CC(vmcs12->host_tr_selector == 0) ||
2951             CC(vmcs12->host_ss_selector == 0 && !ia32e))
2952                 return -EINVAL;
2953
2954         if (CC(is_noncanonical_address(vmcs12->host_fs_base, vcpu)) ||
2955             CC(is_noncanonical_address(vmcs12->host_gs_base, vcpu)) ||
2956             CC(is_noncanonical_address(vmcs12->host_gdtr_base, vcpu)) ||
2957             CC(is_noncanonical_address(vmcs12->host_idtr_base, vcpu)) ||
2958             CC(is_noncanonical_address(vmcs12->host_tr_base, vcpu)) ||
2959             CC(is_noncanonical_address(vmcs12->host_rip, vcpu)))
2960                 return -EINVAL;
2961
2962         /*
2963          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
2964          * IA32_EFER MSR must be 0 in the field for that register. In addition,
2965          * the values of the LMA and LME bits in the field must each be that of
2966          * the host address-space size VM-exit control.
2967          */
2968         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
2969                 if (CC(!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer)) ||
2970                     CC(ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA)) ||
2971                     CC(ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)))
2972                         return -EINVAL;
2973         }
2974
2975         return 0;
2976 }
2977
2978 static int nested_vmx_check_vmcs_link_ptr(struct kvm_vcpu *vcpu,
2979                                           struct vmcs12 *vmcs12)
2980 {
2981         struct vcpu_vmx *vmx = to_vmx(vcpu);
2982         struct gfn_to_hva_cache *ghc = &vmx->nested.shadow_vmcs12_cache;
2983         struct vmcs_hdr hdr;
2984
2985         if (vmcs12->vmcs_link_pointer == INVALID_GPA)
2986                 return 0;
2987
2988         if (CC(!page_address_valid(vcpu, vmcs12->vmcs_link_pointer)))
2989                 return -EINVAL;
2990
2991         if (ghc->gpa != vmcs12->vmcs_link_pointer &&
2992             CC(kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc,
2993                                          vmcs12->vmcs_link_pointer, VMCS12_SIZE)))
2994                 return -EINVAL;
2995
2996         if (CC(kvm_read_guest_offset_cached(vcpu->kvm, ghc, &hdr,
2997                                             offsetof(struct vmcs12, hdr),
2998                                             sizeof(hdr))))
2999                 return -EINVAL;
3000
3001         if (CC(hdr.revision_id != VMCS12_REVISION) ||
3002             CC(hdr.shadow_vmcs != nested_cpu_has_shadow_vmcs(vmcs12)))
3003                 return -EINVAL;
3004
3005         return 0;
3006 }
3007
3008 /*
3009  * Checks related to Guest Non-register State
3010  */
3011 static int nested_check_guest_non_reg_state(struct vmcs12 *vmcs12)
3012 {
3013         if (CC(vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
3014                vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT &&
3015                vmcs12->guest_activity_state != GUEST_ACTIVITY_WAIT_SIPI))
3016                 return -EINVAL;
3017
3018         return 0;
3019 }
3020
3021 static int nested_vmx_check_guest_state(struct kvm_vcpu *vcpu,
3022                                         struct vmcs12 *vmcs12,
3023                                         enum vm_entry_failure_code *entry_failure_code)
3024 {
3025         bool ia32e = !!(vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE);
3026
3027         *entry_failure_code = ENTRY_FAIL_DEFAULT;
3028
3029         if (CC(!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0)) ||
3030             CC(!nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4)))
3031                 return -EINVAL;
3032
3033         if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) &&
3034             CC(!kvm_dr7_valid(vmcs12->guest_dr7)))
3035                 return -EINVAL;
3036
3037         if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) &&
3038             CC(!kvm_pat_valid(vmcs12->guest_ia32_pat)))
3039                 return -EINVAL;
3040
3041         if (nested_vmx_check_vmcs_link_ptr(vcpu, vmcs12)) {
3042                 *entry_failure_code = ENTRY_FAIL_VMCS_LINK_PTR;
3043                 return -EINVAL;
3044         }
3045
3046         if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) &&
3047             CC(!kvm_valid_perf_global_ctrl(vcpu_to_pmu(vcpu),
3048                                            vmcs12->guest_ia32_perf_global_ctrl)))
3049                 return -EINVAL;
3050
3051         if (CC((vmcs12->guest_cr0 & (X86_CR0_PG | X86_CR0_PE)) == X86_CR0_PG))
3052                 return -EINVAL;
3053
3054         if (CC(ia32e && !(vmcs12->guest_cr4 & X86_CR4_PAE)) ||
3055             CC(ia32e && !(vmcs12->guest_cr0 & X86_CR0_PG)))
3056                 return -EINVAL;
3057
3058         /*
3059          * If the load IA32_EFER VM-entry control is 1, the following checks
3060          * are performed on the field for the IA32_EFER MSR:
3061          * - Bits reserved in the IA32_EFER MSR must be 0.
3062          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
3063          *   the IA-32e mode guest VM-exit control. It must also be identical
3064          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
3065          *   CR0.PG) is 1.
3066          */
3067         if (to_vmx(vcpu)->nested.nested_run_pending &&
3068             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
3069                 if (CC(!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer)) ||
3070                     CC(ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA)) ||
3071                     CC(((vmcs12->guest_cr0 & X86_CR0_PG) &&
3072                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))))
3073                         return -EINVAL;
3074         }
3075
3076         if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) &&
3077             (CC(is_noncanonical_address(vmcs12->guest_bndcfgs & PAGE_MASK, vcpu)) ||
3078              CC((vmcs12->guest_bndcfgs & MSR_IA32_BNDCFGS_RSVD))))
3079                 return -EINVAL;
3080
3081         if (nested_check_guest_non_reg_state(vmcs12))
3082                 return -EINVAL;
3083
3084         return 0;
3085 }
3086
3087 static int nested_vmx_check_vmentry_hw(struct kvm_vcpu *vcpu)
3088 {
3089         struct vcpu_vmx *vmx = to_vmx(vcpu);
3090         unsigned long cr3, cr4;
3091         bool vm_fail;
3092
3093         if (!nested_early_check)
3094                 return 0;
3095
3096         if (vmx->msr_autoload.host.nr)
3097                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
3098         if (vmx->msr_autoload.guest.nr)
3099                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
3100
3101         preempt_disable();
3102
3103         vmx_prepare_switch_to_guest(vcpu);
3104
3105         /*
3106          * Induce a consistency check VMExit by clearing bit 1 in GUEST_RFLAGS,
3107          * which is reserved to '1' by hardware.  GUEST_RFLAGS is guaranteed to
3108          * be written (by prepare_vmcs02()) before the "real" VMEnter, i.e.
3109          * there is no need to preserve other bits or save/restore the field.
3110          */
3111         vmcs_writel(GUEST_RFLAGS, 0);
3112
3113         cr3 = __get_current_cr3_fast();
3114         if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
3115                 vmcs_writel(HOST_CR3, cr3);
3116                 vmx->loaded_vmcs->host_state.cr3 = cr3;
3117         }
3118
3119         cr4 = cr4_read_shadow();
3120         if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
3121                 vmcs_writel(HOST_CR4, cr4);
3122                 vmx->loaded_vmcs->host_state.cr4 = cr4;
3123         }
3124
3125         vm_fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
3126                                  __vmx_vcpu_run_flags(vmx));
3127
3128         if (vmx->msr_autoload.host.nr)
3129                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr);
3130         if (vmx->msr_autoload.guest.nr)
3131                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr);
3132
3133         if (vm_fail) {
3134                 u32 error = vmcs_read32(VM_INSTRUCTION_ERROR);
3135
3136                 preempt_enable();
3137
3138                 trace_kvm_nested_vmenter_failed(
3139                         "early hardware check VM-instruction error: ", error);
3140                 WARN_ON_ONCE(error != VMXERR_ENTRY_INVALID_CONTROL_FIELD);
3141                 return 1;
3142         }
3143
3144         /*
3145          * VMExit clears RFLAGS.IF and DR7, even on a consistency check.
3146          */
3147         if (hw_breakpoint_active())
3148                 set_debugreg(__this_cpu_read(cpu_dr7), 7);
3149         local_irq_enable();
3150         preempt_enable();
3151
3152         /*
3153          * A non-failing VMEntry means we somehow entered guest mode with
3154          * an illegal RIP, and that's just the tip of the iceberg.  There
3155          * is no telling what memory has been modified or what state has
3156          * been exposed to unknown code.  Hitting this all but guarantees
3157          * a (very critical) hardware issue.
3158          */
3159         WARN_ON(!(vmcs_read32(VM_EXIT_REASON) &
3160                 VMX_EXIT_REASONS_FAILED_VMENTRY));
3161
3162         return 0;
3163 }
3164
3165 static bool nested_get_evmcs_page(struct kvm_vcpu *vcpu)
3166 {
3167         struct vcpu_vmx *vmx = to_vmx(vcpu);
3168
3169         /*
3170          * hv_evmcs may end up being not mapped after migration (when
3171          * L2 was running), map it here to make sure vmcs12 changes are
3172          * properly reflected.
3173          */
3174         if (guest_cpuid_has_evmcs(vcpu) &&
3175             vmx->nested.hv_evmcs_vmptr == EVMPTR_MAP_PENDING) {
3176                 enum nested_evmptrld_status evmptrld_status =
3177                         nested_vmx_handle_enlightened_vmptrld(vcpu, false);
3178
3179                 if (evmptrld_status == EVMPTRLD_VMFAIL ||
3180                     evmptrld_status == EVMPTRLD_ERROR)
3181                         return false;
3182
3183                 /*
3184                  * Post migration VMCS12 always provides the most actual
3185                  * information, copy it to eVMCS upon entry.
3186                  */
3187                 vmx->nested.need_vmcs12_to_shadow_sync = true;
3188         }
3189
3190         return true;
3191 }
3192
3193 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu)
3194 {
3195         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3196         struct vcpu_vmx *vmx = to_vmx(vcpu);
3197         struct kvm_host_map *map;
3198
3199         if (!vcpu->arch.pdptrs_from_userspace &&
3200             !nested_cpu_has_ept(vmcs12) && is_pae_paging(vcpu)) {
3201                 /*
3202                  * Reload the guest's PDPTRs since after a migration
3203                  * the guest CR3 might be restored prior to setting the nested
3204                  * state which can lead to a load of wrong PDPTRs.
3205                  */
3206                 if (CC(!load_pdptrs(vcpu, vcpu->arch.cr3)))
3207                         return false;
3208         }
3209
3210
3211         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
3212                 map = &vmx->nested.apic_access_page_map;
3213
3214                 if (!kvm_vcpu_map(vcpu, gpa_to_gfn(vmcs12->apic_access_addr), map)) {
3215                         vmcs_write64(APIC_ACCESS_ADDR, pfn_to_hpa(map->pfn));
3216                 } else {
3217                         pr_debug_ratelimited("%s: no backing for APIC-access address in vmcs12\n",
3218                                              __func__);
3219                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3220                         vcpu->run->internal.suberror =
3221                                 KVM_INTERNAL_ERROR_EMULATION;
3222                         vcpu->run->internal.ndata = 0;
3223                         return false;
3224                 }
3225         }
3226
3227         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
3228                 map = &vmx->nested.virtual_apic_map;
3229
3230                 if (!kvm_vcpu_map(vcpu, gpa_to_gfn(vmcs12->virtual_apic_page_addr), map)) {
3231                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, pfn_to_hpa(map->pfn));
3232                 } else if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING) &&
3233                            nested_cpu_has(vmcs12, CPU_BASED_CR8_STORE_EXITING) &&
3234                            !nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
3235                         /*
3236                          * The processor will never use the TPR shadow, simply
3237                          * clear the bit from the execution control.  Such a
3238                          * configuration is useless, but it happens in tests.
3239                          * For any other configuration, failing the vm entry is
3240                          * _not_ what the processor does but it's basically the
3241                          * only possibility we have.
3242                          */
3243                         exec_controls_clearbit(vmx, CPU_BASED_TPR_SHADOW);
3244                 } else {
3245                         /*
3246                          * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR to
3247                          * force VM-Entry to fail.
3248                          */
3249                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, INVALID_GPA);
3250                 }
3251         }
3252
3253         if (nested_cpu_has_posted_intr(vmcs12)) {
3254                 map = &vmx->nested.pi_desc_map;
3255
3256                 if (!kvm_vcpu_map(vcpu, gpa_to_gfn(vmcs12->posted_intr_desc_addr), map)) {
3257                         vmx->nested.pi_desc =
3258                                 (struct pi_desc *)(((void *)map->hva) +
3259                                 offset_in_page(vmcs12->posted_intr_desc_addr));
3260                         vmcs_write64(POSTED_INTR_DESC_ADDR,
3261                                      pfn_to_hpa(map->pfn) + offset_in_page(vmcs12->posted_intr_desc_addr));
3262                 } else {
3263                         /*
3264                          * Defer the KVM_INTERNAL_EXIT until KVM tries to
3265                          * access the contents of the VMCS12 posted interrupt
3266                          * descriptor. (Note that KVM may do this when it
3267                          * should not, per the architectural specification.)
3268                          */
3269                         vmx->nested.pi_desc = NULL;
3270                         pin_controls_clearbit(vmx, PIN_BASED_POSTED_INTR);
3271                 }
3272         }
3273         if (nested_vmx_prepare_msr_bitmap(vcpu, vmcs12))
3274                 exec_controls_setbit(vmx, CPU_BASED_USE_MSR_BITMAPS);
3275         else
3276                 exec_controls_clearbit(vmx, CPU_BASED_USE_MSR_BITMAPS);
3277
3278         return true;
3279 }
3280
3281 static bool vmx_get_nested_state_pages(struct kvm_vcpu *vcpu)
3282 {
3283         /*
3284          * Note: nested_get_evmcs_page() also updates 'vp_assist_page' copy
3285          * in 'struct kvm_vcpu_hv' in case eVMCS is in use, this is mandatory
3286          * to make nested_evmcs_l2_tlb_flush_enabled() work correctly post
3287          * migration.
3288          */
3289         if (!nested_get_evmcs_page(vcpu)) {
3290                 pr_debug_ratelimited("%s: enlightened vmptrld failed\n",
3291                                      __func__);
3292                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3293                 vcpu->run->internal.suberror =
3294                         KVM_INTERNAL_ERROR_EMULATION;
3295                 vcpu->run->internal.ndata = 0;
3296
3297                 return false;
3298         }
3299
3300         if (is_guest_mode(vcpu) && !nested_get_vmcs12_pages(vcpu))
3301                 return false;
3302
3303         return true;
3304 }
3305
3306 static int nested_vmx_write_pml_buffer(struct kvm_vcpu *vcpu, gpa_t gpa)
3307 {
3308         struct vmcs12 *vmcs12;
3309         struct vcpu_vmx *vmx = to_vmx(vcpu);
3310         gpa_t dst;
3311
3312         if (WARN_ON_ONCE(!is_guest_mode(vcpu)))
3313                 return 0;
3314
3315         if (WARN_ON_ONCE(vmx->nested.pml_full))
3316                 return 1;
3317
3318         /*
3319          * Check if PML is enabled for the nested guest. Whether eptp bit 6 is
3320          * set is already checked as part of A/D emulation.
3321          */
3322         vmcs12 = get_vmcs12(vcpu);
3323         if (!nested_cpu_has_pml(vmcs12))
3324                 return 0;
3325
3326         if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
3327                 vmx->nested.pml_full = true;
3328                 return 1;
3329         }
3330
3331         gpa &= ~0xFFFull;
3332         dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index;
3333
3334         if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa,
3335                                  offset_in_page(dst), sizeof(gpa)))
3336                 return 0;
3337
3338         vmcs12->guest_pml_index--;
3339
3340         return 0;
3341 }
3342
3343 /*
3344  * Intel's VMX Instruction Reference specifies a common set of prerequisites
3345  * for running VMX instructions (except VMXON, whose prerequisites are
3346  * slightly different). It also specifies what exception to inject otherwise.
3347  * Note that many of these exceptions have priority over VM exits, so they
3348  * don't have to be checked again here.
3349  */
3350 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
3351 {
3352         if (!to_vmx(vcpu)->nested.vmxon) {
3353                 kvm_queue_exception(vcpu, UD_VECTOR);
3354                 return 0;
3355         }
3356
3357         if (vmx_get_cpl(vcpu)) {
3358                 kvm_inject_gp(vcpu, 0);
3359                 return 0;
3360         }
3361
3362         return 1;
3363 }
3364
3365 static u8 vmx_has_apicv_interrupt(struct kvm_vcpu *vcpu)
3366 {
3367         u8 rvi = vmx_get_rvi();
3368         u8 vppr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_PROCPRI);
3369
3370         return ((rvi & 0xf0) > (vppr & 0xf0));
3371 }
3372
3373 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
3374                                    struct vmcs12 *vmcs12);
3375
3376 /*
3377  * If from_vmentry is false, this is being called from state restore (either RSM
3378  * or KVM_SET_NESTED_STATE).  Otherwise it's called from vmlaunch/vmresume.
3379  *
3380  * Returns:
3381  *      NVMX_VMENTRY_SUCCESS: Entered VMX non-root mode
3382  *      NVMX_VMENTRY_VMFAIL:  Consistency check VMFail
3383  *      NVMX_VMENTRY_VMEXIT:  Consistency check VMExit
3384  *      NVMX_VMENTRY_KVM_INTERNAL_ERROR: KVM internal error
3385  */
3386 enum nvmx_vmentry_status nested_vmx_enter_non_root_mode(struct kvm_vcpu *vcpu,
3387                                                         bool from_vmentry)
3388 {
3389         struct vcpu_vmx *vmx = to_vmx(vcpu);
3390         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3391         enum vm_entry_failure_code entry_failure_code;
3392         bool evaluate_pending_interrupts;
3393         union vmx_exit_reason exit_reason = {
3394                 .basic = EXIT_REASON_INVALID_STATE,
3395                 .failed_vmentry = 1,
3396         };
3397         u32 failed_index;
3398
3399         trace_kvm_nested_vmenter(kvm_rip_read(vcpu),
3400                                  vmx->nested.current_vmptr,
3401                                  vmcs12->guest_rip,
3402                                  vmcs12->guest_intr_status,
3403                                  vmcs12->vm_entry_intr_info_field,
3404                                  vmcs12->secondary_vm_exec_control & SECONDARY_EXEC_ENABLE_EPT,
3405                                  vmcs12->ept_pointer,
3406                                  vmcs12->guest_cr3,
3407                                  KVM_ISA_VMX);
3408
3409         kvm_service_local_tlb_flush_requests(vcpu);
3410
3411         evaluate_pending_interrupts = exec_controls_get(vmx) &
3412                 (CPU_BASED_INTR_WINDOW_EXITING | CPU_BASED_NMI_WINDOW_EXITING);
3413         if (likely(!evaluate_pending_interrupts) && kvm_vcpu_apicv_active(vcpu))
3414                 evaluate_pending_interrupts |= vmx_has_apicv_interrupt(vcpu);
3415         if (!evaluate_pending_interrupts)
3416                 evaluate_pending_interrupts |= kvm_apic_has_pending_init_or_sipi(vcpu);
3417
3418         if (!vmx->nested.nested_run_pending ||
3419             !(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
3420                 vmx->nested.pre_vmenter_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
3421         if (kvm_mpx_supported() &&
3422             (!vmx->nested.nested_run_pending ||
3423              !(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)))
3424                 vmx->nested.pre_vmenter_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
3425
3426         /*
3427          * Overwrite vmcs01.GUEST_CR3 with L1's CR3 if EPT is disabled *and*
3428          * nested early checks are disabled.  In the event of a "late" VM-Fail,
3429          * i.e. a VM-Fail detected by hardware but not KVM, KVM must unwind its
3430          * software model to the pre-VMEntry host state.  When EPT is disabled,
3431          * GUEST_CR3 holds KVM's shadow CR3, not L1's "real" CR3, which causes
3432          * nested_vmx_restore_host_state() to corrupt vcpu->arch.cr3.  Stuffing
3433          * vmcs01.GUEST_CR3 results in the unwind naturally setting arch.cr3 to
3434          * the correct value.  Smashing vmcs01.GUEST_CR3 is safe because nested
3435          * VM-Exits, and the unwind, reset KVM's MMU, i.e. vmcs01.GUEST_CR3 is
3436          * guaranteed to be overwritten with a shadow CR3 prior to re-entering
3437          * L1.  Don't stuff vmcs01.GUEST_CR3 when using nested early checks as
3438          * KVM modifies vcpu->arch.cr3 if and only if the early hardware checks
3439          * pass, and early VM-Fails do not reset KVM's MMU, i.e. the VM-Fail
3440          * path would need to manually save/restore vmcs01.GUEST_CR3.
3441          */
3442         if (!enable_ept && !nested_early_check)
3443                 vmcs_writel(GUEST_CR3, vcpu->arch.cr3);
3444
3445         vmx_switch_vmcs(vcpu, &vmx->nested.vmcs02);
3446
3447         prepare_vmcs02_early(vmx, &vmx->vmcs01, vmcs12);
3448
3449         if (from_vmentry) {
3450                 if (unlikely(!nested_get_vmcs12_pages(vcpu))) {
3451                         vmx_switch_vmcs(vcpu, &vmx->vmcs01);
3452                         return NVMX_VMENTRY_KVM_INTERNAL_ERROR;
3453                 }
3454
3455                 if (nested_vmx_check_vmentry_hw(vcpu)) {
3456                         vmx_switch_vmcs(vcpu, &vmx->vmcs01);
3457                         return NVMX_VMENTRY_VMFAIL;
3458                 }
3459
3460                 if (nested_vmx_check_guest_state(vcpu, vmcs12,
3461                                                  &entry_failure_code)) {
3462                         exit_reason.basic = EXIT_REASON_INVALID_STATE;
3463                         vmcs12->exit_qualification = entry_failure_code;
3464                         goto vmentry_fail_vmexit;
3465                 }
3466         }
3467
3468         enter_guest_mode(vcpu);
3469
3470         if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &entry_failure_code)) {
3471                 exit_reason.basic = EXIT_REASON_INVALID_STATE;
3472                 vmcs12->exit_qualification = entry_failure_code;
3473                 goto vmentry_fail_vmexit_guest_mode;
3474         }
3475
3476         if (from_vmentry) {
3477                 failed_index = nested_vmx_load_msr(vcpu,
3478                                                    vmcs12->vm_entry_msr_load_addr,
3479                                                    vmcs12->vm_entry_msr_load_count);
3480                 if (failed_index) {
3481                         exit_reason.basic = EXIT_REASON_MSR_LOAD_FAIL;
3482                         vmcs12->exit_qualification = failed_index;
3483                         goto vmentry_fail_vmexit_guest_mode;
3484                 }
3485         } else {
3486                 /*
3487                  * The MMU is not initialized to point at the right entities yet and
3488                  * "get pages" would need to read data from the guest (i.e. we will
3489                  * need to perform gpa to hpa translation). Request a call
3490                  * to nested_get_vmcs12_pages before the next VM-entry.  The MSRs
3491                  * have already been set at vmentry time and should not be reset.
3492                  */
3493                 kvm_make_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu);
3494         }
3495
3496         /*
3497          * Re-evaluate pending events if L1 had a pending IRQ/NMI/INIT/SIPI
3498          * when it executed VMLAUNCH/VMRESUME, as entering non-root mode can
3499          * effectively unblock various events, e.g. INIT/SIPI cause VM-Exit
3500          * unconditionally.
3501          */
3502         if (unlikely(evaluate_pending_interrupts))
3503                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3504
3505         /*
3506          * Do not start the preemption timer hrtimer until after we know
3507          * we are successful, so that only nested_vmx_vmexit needs to cancel
3508          * the timer.
3509          */
3510         vmx->nested.preemption_timer_expired = false;
3511         if (nested_cpu_has_preemption_timer(vmcs12)) {
3512                 u64 timer_value = vmx_calc_preemption_timer_value(vcpu);
3513                 vmx_start_preemption_timer(vcpu, timer_value);
3514         }
3515
3516         /*
3517          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
3518          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
3519          * returned as far as L1 is concerned. It will only return (and set
3520          * the success flag) when L2 exits (see nested_vmx_vmexit()).
3521          */
3522         return NVMX_VMENTRY_SUCCESS;
3523
3524         /*
3525          * A failed consistency check that leads to a VMExit during L1's
3526          * VMEnter to L2 is a variation of a normal VMexit, as explained in
3527          * 26.7 "VM-entry failures during or after loading guest state".
3528          */
3529 vmentry_fail_vmexit_guest_mode:
3530         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING)
3531                 vcpu->arch.tsc_offset -= vmcs12->tsc_offset;
3532         leave_guest_mode(vcpu);
3533
3534 vmentry_fail_vmexit:
3535         vmx_switch_vmcs(vcpu, &vmx->vmcs01);
3536
3537         if (!from_vmentry)
3538                 return NVMX_VMENTRY_VMEXIT;
3539
3540         load_vmcs12_host_state(vcpu, vmcs12);
3541         vmcs12->vm_exit_reason = exit_reason.full;
3542         if (enable_shadow_vmcs || evmptr_is_valid(vmx->nested.hv_evmcs_vmptr))
3543                 vmx->nested.need_vmcs12_to_shadow_sync = true;
3544         return NVMX_VMENTRY_VMEXIT;
3545 }
3546
3547 /*
3548  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
3549  * for running an L2 nested guest.
3550  */
3551 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
3552 {
3553         struct vmcs12 *vmcs12;
3554         enum nvmx_vmentry_status status;
3555         struct vcpu_vmx *vmx = to_vmx(vcpu);
3556         u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu);
3557         enum nested_evmptrld_status evmptrld_status;
3558
3559         if (!nested_vmx_check_permission(vcpu))
3560                 return 1;
3561
3562         evmptrld_status = nested_vmx_handle_enlightened_vmptrld(vcpu, launch);
3563         if (evmptrld_status == EVMPTRLD_ERROR) {
3564                 kvm_queue_exception(vcpu, UD_VECTOR);
3565                 return 1;
3566         }
3567
3568         kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
3569
3570         if (CC(evmptrld_status == EVMPTRLD_VMFAIL))
3571                 return nested_vmx_failInvalid(vcpu);
3572
3573         if (CC(!evmptr_is_valid(vmx->nested.hv_evmcs_vmptr) &&
3574                vmx->nested.current_vmptr == INVALID_GPA))
3575                 return nested_vmx_failInvalid(vcpu);
3576
3577         vmcs12 = get_vmcs12(vcpu);
3578
3579         /*
3580          * Can't VMLAUNCH or VMRESUME a shadow VMCS. Despite the fact
3581          * that there *is* a valid VMCS pointer, RFLAGS.CF is set
3582          * rather than RFLAGS.ZF, and no error number is stored to the
3583          * VM-instruction error field.
3584          */
3585         if (CC(vmcs12->hdr.shadow_vmcs))
3586                 return nested_vmx_failInvalid(vcpu);
3587
3588         if (evmptr_is_valid(vmx->nested.hv_evmcs_vmptr)) {
3589                 copy_enlightened_to_vmcs12(vmx, vmx->nested.hv_evmcs->hv_clean_fields);
3590                 /* Enlightened VMCS doesn't have launch state */
3591                 vmcs12->launch_state = !launch;
3592         } else if (enable_shadow_vmcs) {
3593                 copy_shadow_to_vmcs12(vmx);
3594         }
3595
3596         /*
3597          * The nested entry process starts with enforcing various prerequisites
3598          * on vmcs12 as required by the Intel SDM, and act appropriately when
3599          * they fail: As the SDM explains, some conditions should cause the
3600          * instruction to fail, while others will cause the instruction to seem
3601          * to succeed, but return an EXIT_REASON_INVALID_STATE.
3602          * To speed up the normal (success) code path, we should avoid checking
3603          * for misconfigurations which will anyway be caught by the processor
3604          * when using the merged vmcs02.
3605          */
3606         if (CC(interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS))
3607                 return nested_vmx_fail(vcpu, VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS);
3608
3609         if (CC(vmcs12->launch_state == launch))
3610                 return nested_vmx_fail(vcpu,
3611                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
3612                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
3613
3614         if (nested_vmx_check_controls(vcpu, vmcs12))
3615                 return nested_vmx_fail(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
3616
3617         if (nested_vmx_check_address_space_size(vcpu, vmcs12))
3618                 return nested_vmx_fail(vcpu, VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
3619
3620         if (nested_vmx_check_host_state(vcpu, vmcs12))
3621                 return nested_vmx_fail(vcpu, VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
3622
3623         /*
3624          * We're finally done with prerequisite checking, and can start with
3625          * the nested entry.
3626          */
3627         vmx->nested.nested_run_pending = 1;
3628         vmx->nested.has_preemption_timer_deadline = false;
3629         status = nested_vmx_enter_non_root_mode(vcpu, true);
3630         if (unlikely(status != NVMX_VMENTRY_SUCCESS))
3631                 goto vmentry_failed;
3632
3633         /* Emulate processing of posted interrupts on VM-Enter. */
3634         if (nested_cpu_has_posted_intr(vmcs12) &&
3635             kvm_apic_has_interrupt(vcpu) == vmx->nested.posted_intr_nv) {
3636                 vmx->nested.pi_pending = true;
3637                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3638                 kvm_apic_clear_irr(vcpu, vmx->nested.posted_intr_nv);
3639         }
3640
3641         /* Hide L1D cache contents from the nested guest.  */
3642         vmx->vcpu.arch.l1tf_flush_l1d = true;
3643
3644         /*
3645          * Must happen outside of nested_vmx_enter_non_root_mode() as it will
3646          * also be used as part of restoring nVMX state for
3647          * snapshot restore (migration).
3648          *
3649          * In this flow, it is assumed that vmcs12 cache was
3650          * transferred as part of captured nVMX state and should
3651          * therefore not be read from guest memory (which may not
3652          * exist on destination host yet).
3653          */
3654         nested_cache_shadow_vmcs12(vcpu, vmcs12);
3655
3656         switch (vmcs12->guest_activity_state) {
3657         case GUEST_ACTIVITY_HLT:
3658                 /*
3659                  * If we're entering a halted L2 vcpu and the L2 vcpu won't be
3660                  * awakened by event injection or by an NMI-window VM-exit or
3661                  * by an interrupt-window VM-exit, halt the vcpu.
3662                  */
3663                 if (!(vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK) &&
3664                     !nested_cpu_has(vmcs12, CPU_BASED_NMI_WINDOW_EXITING) &&
3665                     !(nested_cpu_has(vmcs12, CPU_BASED_INTR_WINDOW_EXITING) &&
3666                       (vmcs12->guest_rflags & X86_EFLAGS_IF))) {
3667                         vmx->nested.nested_run_pending = 0;
3668                         return kvm_emulate_halt_noskip(vcpu);
3669                 }
3670                 break;
3671         case GUEST_ACTIVITY_WAIT_SIPI:
3672                 vmx->nested.nested_run_pending = 0;
3673                 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
3674                 break;
3675         default:
3676                 break;
3677         }
3678
3679         return 1;
3680
3681 vmentry_failed:
3682         vmx->nested.nested_run_pending = 0;
3683         if (status == NVMX_VMENTRY_KVM_INTERNAL_ERROR)
3684                 return 0;
3685         if (status == NVMX_VMENTRY_VMEXIT)
3686                 return 1;
3687         WARN_ON_ONCE(status != NVMX_VMENTRY_VMFAIL);
3688         return nested_vmx_fail(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
3689 }
3690
3691 /*
3692  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
3693  * because L2 may have changed some cr0 bits directly (CR0_GUEST_HOST_MASK).
3694  * This function returns the new value we should put in vmcs12.guest_cr0.
3695  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
3696  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
3697  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
3698  *     didn't trap the bit, because if L1 did, so would L0).
3699  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
3700  *     been modified by L2, and L1 knows it. So just leave the old value of
3701  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
3702  *     isn't relevant, because if L0 traps this bit it can set it to anything.
3703  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
3704  *     changed these bits, and therefore they need to be updated, but L0
3705  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
3706  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
3707  */
3708 static inline unsigned long
3709 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
3710 {
3711         return
3712         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
3713         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
3714         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
3715                         vcpu->arch.cr0_guest_owned_bits));
3716 }
3717
3718 static inline unsigned long
3719 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
3720 {
3721         return
3722         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
3723         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
3724         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
3725                         vcpu->arch.cr4_guest_owned_bits));
3726 }
3727
3728 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
3729                                       struct vmcs12 *vmcs12,
3730                                       u32 vm_exit_reason, u32 exit_intr_info)
3731 {
3732         u32 idt_vectoring;
3733         unsigned int nr;
3734
3735         /*
3736          * Per the SDM, VM-Exits due to double and triple faults are never
3737          * considered to occur during event delivery, even if the double/triple
3738          * fault is the result of an escalating vectoring issue.
3739          *
3740          * Note, the SDM qualifies the double fault behavior with "The original
3741          * event results in a double-fault exception".  It's unclear why the
3742          * qualification exists since exits due to double fault can occur only
3743          * while vectoring a different exception (injected events are never
3744          * subject to interception), i.e. there's _always_ an original event.
3745          *
3746          * The SDM also uses NMI as a confusing example for the "original event
3747          * causes the VM exit directly" clause.  NMI isn't special in any way,
3748          * the same rule applies to all events that cause an exit directly.
3749          * NMI is an odd choice for the example because NMIs can only occur on
3750          * instruction boundaries, i.e. they _can't_ occur during vectoring.
3751          */
3752         if ((u16)vm_exit_reason == EXIT_REASON_TRIPLE_FAULT ||
3753             ((u16)vm_exit_reason == EXIT_REASON_EXCEPTION_NMI &&
3754              is_double_fault(exit_intr_info))) {
3755                 vmcs12->idt_vectoring_info_field = 0;
3756         } else if (vcpu->arch.exception.injected) {
3757                 nr = vcpu->arch.exception.vector;
3758                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
3759
3760                 if (kvm_exception_is_soft(nr)) {
3761                         vmcs12->vm_exit_instruction_len =
3762                                 vcpu->arch.event_exit_inst_len;
3763                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
3764                 } else
3765                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
3766
3767                 if (vcpu->arch.exception.has_error_code) {
3768                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
3769                         vmcs12->idt_vectoring_error_code =
3770                                 vcpu->arch.exception.error_code;
3771                 }
3772
3773                 vmcs12->idt_vectoring_info_field = idt_vectoring;
3774         } else if (vcpu->arch.nmi_injected) {
3775                 vmcs12->idt_vectoring_info_field =
3776                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
3777         } else if (vcpu->arch.interrupt.injected) {
3778                 nr = vcpu->arch.interrupt.nr;
3779                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
3780
3781                 if (vcpu->arch.interrupt.soft) {
3782                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
3783                         vmcs12->vm_entry_instruction_len =
3784                                 vcpu->arch.event_exit_inst_len;
3785                 } else
3786                         idt_vectoring |= INTR_TYPE_EXT_INTR;
3787
3788                 vmcs12->idt_vectoring_info_field = idt_vectoring;
3789         } else {
3790                 vmcs12->idt_vectoring_info_field = 0;
3791         }
3792 }
3793
3794
3795 void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu)
3796 {
3797         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3798         gfn_t gfn;
3799
3800         /*
3801          * Don't need to mark the APIC access page dirty; it is never
3802          * written to by the CPU during APIC virtualization.
3803          */
3804
3805         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
3806                 gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT;
3807                 kvm_vcpu_mark_page_dirty(vcpu, gfn);
3808         }
3809
3810         if (nested_cpu_has_posted_intr(vmcs12)) {
3811                 gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT;
3812                 kvm_vcpu_mark_page_dirty(vcpu, gfn);
3813         }
3814 }
3815
3816 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
3817 {
3818         struct vcpu_vmx *vmx = to_vmx(vcpu);
3819         int max_irr;
3820         void *vapic_page;
3821         u16 status;
3822
3823         if (!vmx->nested.pi_pending)
3824                 return 0;
3825
3826         if (!vmx->nested.pi_desc)
3827                 goto mmio_needed;
3828
3829         vmx->nested.pi_pending = false;
3830
3831         if (!pi_test_and_clear_on(vmx->nested.pi_desc))
3832                 return 0;
3833
3834         max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256);
3835         if (max_irr != 256) {
3836                 vapic_page = vmx->nested.virtual_apic_map.hva;
3837                 if (!vapic_page)
3838                         goto mmio_needed;
3839
3840                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir,
3841                         vapic_page, &max_irr);
3842                 status = vmcs_read16(GUEST_INTR_STATUS);
3843                 if ((u8)max_irr > ((u8)status & 0xff)) {
3844                         status &= ~0xff;
3845                         status |= (u8)max_irr;
3846                         vmcs_write16(GUEST_INTR_STATUS, status);
3847                 }
3848         }
3849
3850         nested_mark_vmcs12_pages_dirty(vcpu);
3851         return 0;
3852
3853 mmio_needed:
3854         kvm_handle_memory_failure(vcpu, X86EMUL_IO_NEEDED, NULL);
3855         return -ENXIO;
3856 }
3857
3858 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu)
3859 {
3860         struct kvm_queued_exception *ex = &vcpu->arch.exception_vmexit;
3861         u32 intr_info = ex->vector | INTR_INFO_VALID_MASK;
3862         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3863         unsigned long exit_qual;
3864
3865         if (ex->has_payload) {
3866                 exit_qual = ex->payload;
3867         } else if (ex->vector == PF_VECTOR) {
3868                 exit_qual = vcpu->arch.cr2;
3869         } else if (ex->vector == DB_VECTOR) {
3870                 exit_qual = vcpu->arch.dr6;
3871                 exit_qual &= ~DR6_BT;
3872                 exit_qual ^= DR6_ACTIVE_LOW;
3873         } else {
3874                 exit_qual = 0;
3875         }
3876
3877         if (ex->has_error_code) {
3878                 /*
3879                  * Intel CPUs do not generate error codes with bits 31:16 set,
3880                  * and more importantly VMX disallows setting bits 31:16 in the
3881                  * injected error code for VM-Entry.  Drop the bits to mimic
3882                  * hardware and avoid inducing failure on nested VM-Entry if L1
3883                  * chooses to inject the exception back to L2.  AMD CPUs _do_
3884                  * generate "full" 32-bit error codes, so KVM allows userspace
3885                  * to inject exception error codes with bits 31:16 set.
3886                  */
3887                 vmcs12->vm_exit_intr_error_code = (u16)ex->error_code;
3888                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
3889         }
3890
3891         if (kvm_exception_is_soft(ex->vector))
3892                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
3893         else
3894                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
3895
3896         if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) &&
3897             vmx_get_nmi_mask(vcpu))
3898                 intr_info |= INTR_INFO_UNBLOCK_NMI;
3899
3900         nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual);
3901 }
3902
3903 /*
3904  * Returns true if a debug trap is (likely) pending delivery.  Infer the class
3905  * of a #DB (trap-like vs. fault-like) from the exception payload (to-be-DR6).
3906  * Using the payload is flawed because code breakpoints (fault-like) and data
3907  * breakpoints (trap-like) set the same bits in DR6 (breakpoint detected), i.e.
3908  * this will return false positives if a to-be-injected code breakpoint #DB is
3909  * pending (from KVM's perspective, but not "pending" across an instruction
3910  * boundary).  ICEBP, a.k.a. INT1, is also not reflected here even though it
3911  * too is trap-like.
3912  *
3913  * KVM "works" despite these flaws as ICEBP isn't currently supported by the
3914  * emulator, Monitor Trap Flag is not marked pending on intercepted #DBs (the
3915  * #DB has already happened), and MTF isn't marked pending on code breakpoints
3916  * from the emulator (because such #DBs are fault-like and thus don't trigger
3917  * actions that fire on instruction retire).
3918  */
3919 static unsigned long vmx_get_pending_dbg_trap(struct kvm_queued_exception *ex)
3920 {
3921         if (!ex->pending || ex->vector != DB_VECTOR)
3922                 return 0;
3923
3924         /* General Detect #DBs are always fault-like. */
3925         return ex->payload & ~DR6_BD;
3926 }
3927
3928 /*
3929  * Returns true if there's a pending #DB exception that is lower priority than
3930  * a pending Monitor Trap Flag VM-Exit.  TSS T-flag #DBs are not emulated by
3931  * KVM, but could theoretically be injected by userspace.  Note, this code is
3932  * imperfect, see above.
3933  */
3934 static bool vmx_is_low_priority_db_trap(struct kvm_queued_exception *ex)
3935 {
3936         return vmx_get_pending_dbg_trap(ex) & ~DR6_BT;
3937 }
3938
3939 /*
3940  * Certain VM-exits set the 'pending debug exceptions' field to indicate a
3941  * recognized #DB (data or single-step) that has yet to be delivered. Since KVM
3942  * represents these debug traps with a payload that is said to be compatible
3943  * with the 'pending debug exceptions' field, write the payload to the VMCS
3944  * field if a VM-exit is delivered before the debug trap.
3945  */
3946 static void nested_vmx_update_pending_dbg(struct kvm_vcpu *vcpu)
3947 {
3948         unsigned long pending_dbg;
3949
3950         pending_dbg = vmx_get_pending_dbg_trap(&vcpu->arch.exception);
3951         if (pending_dbg)
3952                 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, pending_dbg);
3953 }
3954
3955 static bool nested_vmx_preemption_timer_pending(struct kvm_vcpu *vcpu)
3956 {
3957         return nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
3958                to_vmx(vcpu)->nested.preemption_timer_expired;
3959 }
3960
3961 static bool vmx_has_nested_events(struct kvm_vcpu *vcpu)
3962 {
3963         return nested_vmx_preemption_timer_pending(vcpu) ||
3964                to_vmx(vcpu)->nested.mtf_pending;
3965 }
3966
3967 /*
3968  * Per the Intel SDM's table "Priority Among Concurrent Events", with minor
3969  * edits to fill in missing examples, e.g. #DB due to split-lock accesses,
3970  * and less minor edits to splice in the priority of VMX Non-Root specific
3971  * events, e.g. MTF and NMI/INTR-window exiting.
3972  *
3973  * 1 Hardware Reset and Machine Checks
3974  *      - RESET
3975  *      - Machine Check
3976  *
3977  * 2 Trap on Task Switch
3978  *      - T flag in TSS is set (on task switch)
3979  *
3980  * 3 External Hardware Interventions
3981  *      - FLUSH
3982  *      - STOPCLK
3983  *      - SMI
3984  *      - INIT
3985  *
3986  * 3.5 Monitor Trap Flag (MTF) VM-exit[1]
3987  *
3988  * 4 Traps on Previous Instruction
3989  *      - Breakpoints
3990  *      - Trap-class Debug Exceptions (#DB due to TF flag set, data/I-O
3991  *        breakpoint, or #DB due to a split-lock access)
3992  *
3993  * 4.3  VMX-preemption timer expired VM-exit
3994  *
3995  * 4.6  NMI-window exiting VM-exit[2]
3996  *
3997  * 5 Nonmaskable Interrupts (NMI)
3998  *
3999  * 5.5 Interrupt-window exiting VM-exit and Virtual-interrupt delivery
4000  *
4001  * 6 Maskable Hardware Interrupts
4002  *
4003  * 7 Code Breakpoint Fault
4004  *
4005  * 8 Faults from Fetching Next Instruction
4006  *      - Code-Segment Limit Violation
4007  *      - Code Page Fault
4008  *      - Control protection exception (missing ENDBRANCH at target of indirect
4009  *                                      call or jump)
4010  *
4011  * 9 Faults from Decoding Next Instruction
4012  *      - Instruction length > 15 bytes
4013  *      - Invalid Opcode
4014  *      - Coprocessor Not Available
4015  *
4016  *10 Faults on Executing Instruction
4017  *      - Overflow
4018  *      - Bound error
4019  *      - Invalid TSS
4020  *      - Segment Not Present
4021  *      - Stack fault
4022  *      - General Protection
4023  *      - Data Page Fault
4024  *      - Alignment Check
4025  *      - x86 FPU Floating-point exception
4026  *      - SIMD floating-point exception
4027  *      - Virtualization exception
4028  *      - Control protection exception
4029  *
4030  * [1] Per the "Monitor Trap Flag" section: System-management interrupts (SMIs),
4031  *     INIT signals, and higher priority events take priority over MTF VM exits.
4032  *     MTF VM exits take priority over debug-trap exceptions and lower priority
4033  *     events.
4034  *
4035  * [2] Debug-trap exceptions and higher priority events take priority over VM exits
4036  *     caused by the VMX-preemption timer.  VM exits caused by the VMX-preemption
4037  *     timer take priority over VM exits caused by the "NMI-window exiting"
4038  *     VM-execution control and lower priority events.
4039  *
4040  * [3] Debug-trap exceptions and higher priority events take priority over VM exits
4041  *     caused by "NMI-window exiting".  VM exits caused by this control take
4042  *     priority over non-maskable interrupts (NMIs) and lower priority events.
4043  *
4044  * [4] Virtual-interrupt delivery has the same priority as that of VM exits due to
4045  *     the 1-setting of the "interrupt-window exiting" VM-execution control.  Thus,
4046  *     non-maskable interrupts (NMIs) and higher priority events take priority over
4047  *     delivery of a virtual interrupt; delivery of a virtual interrupt takes
4048  *     priority over external interrupts and lower priority events.
4049  */
4050 static int vmx_check_nested_events(struct kvm_vcpu *vcpu)
4051 {
4052         struct kvm_lapic *apic = vcpu->arch.apic;
4053         struct vcpu_vmx *vmx = to_vmx(vcpu);
4054         /*
4055          * Only a pending nested run blocks a pending exception.  If there is a
4056          * previously injected event, the pending exception occurred while said
4057          * event was being delivered and thus needs to be handled.
4058          */
4059         bool block_nested_exceptions = vmx->nested.nested_run_pending;
4060         /*
4061          * New events (not exceptions) are only recognized at instruction
4062          * boundaries.  If an event needs reinjection, then KVM is handling a
4063          * VM-Exit that occurred _during_ instruction execution; new events are
4064          * blocked until the instruction completes.
4065          */
4066         bool block_nested_events = block_nested_exceptions ||
4067                                    kvm_event_needs_reinjection(vcpu);
4068
4069         if (lapic_in_kernel(vcpu) &&
4070                 test_bit(KVM_APIC_INIT, &apic->pending_events)) {
4071                 if (block_nested_events)
4072                         return -EBUSY;
4073                 nested_vmx_update_pending_dbg(vcpu);
4074                 clear_bit(KVM_APIC_INIT, &apic->pending_events);
4075                 if (vcpu->arch.mp_state != KVM_MP_STATE_INIT_RECEIVED)
4076                         nested_vmx_vmexit(vcpu, EXIT_REASON_INIT_SIGNAL, 0, 0);
4077
4078                 /* MTF is discarded if the vCPU is in WFS. */
4079                 vmx->nested.mtf_pending = false;
4080                 return 0;
4081         }
4082
4083         if (lapic_in_kernel(vcpu) &&
4084             test_bit(KVM_APIC_SIPI, &apic->pending_events)) {
4085                 if (block_nested_events)
4086                         return -EBUSY;
4087
4088                 clear_bit(KVM_APIC_SIPI, &apic->pending_events);
4089                 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
4090                         nested_vmx_vmexit(vcpu, EXIT_REASON_SIPI_SIGNAL, 0,
4091                                                 apic->sipi_vector & 0xFFUL);
4092                         return 0;
4093                 }
4094                 /* Fallthrough, the SIPI is completely ignored. */
4095         }
4096
4097         /*
4098          * Process exceptions that are higher priority than Monitor Trap Flag:
4099          * fault-like exceptions, TSS T flag #DB (not emulated by KVM, but
4100          * could theoretically come in from userspace), and ICEBP (INT1).
4101          *
4102          * TODO: SMIs have higher priority than MTF and trap-like #DBs (except
4103          * for TSS T flag #DBs).  KVM also doesn't save/restore pending MTF
4104          * across SMI/RSM as it should; that needs to be addressed in order to
4105          * prioritize SMI over MTF and trap-like #DBs.
4106          */
4107         if (vcpu->arch.exception_vmexit.pending &&
4108             !vmx_is_low_priority_db_trap(&vcpu->arch.exception_vmexit)) {
4109                 if (block_nested_exceptions)
4110                         return -EBUSY;
4111
4112                 nested_vmx_inject_exception_vmexit(vcpu);
4113                 return 0;
4114         }
4115
4116         if (vcpu->arch.exception.pending &&
4117             !vmx_is_low_priority_db_trap(&vcpu->arch.exception)) {
4118                 if (block_nested_exceptions)
4119                         return -EBUSY;
4120                 goto no_vmexit;
4121         }
4122
4123         if (vmx->nested.mtf_pending) {
4124                 if (block_nested_events)
4125                         return -EBUSY;
4126                 nested_vmx_update_pending_dbg(vcpu);
4127                 nested_vmx_vmexit(vcpu, EXIT_REASON_MONITOR_TRAP_FLAG, 0, 0);
4128                 return 0;
4129         }
4130
4131         if (vcpu->arch.exception_vmexit.pending) {
4132                 if (block_nested_exceptions)
4133                         return -EBUSY;
4134
4135                 nested_vmx_inject_exception_vmexit(vcpu);
4136                 return 0;
4137         }
4138
4139         if (vcpu->arch.exception.pending) {
4140                 if (block_nested_exceptions)
4141                         return -EBUSY;
4142                 goto no_vmexit;
4143         }
4144
4145         if (nested_vmx_preemption_timer_pending(vcpu)) {
4146                 if (block_nested_events)
4147                         return -EBUSY;
4148                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
4149                 return 0;
4150         }
4151
4152         if (vcpu->arch.smi_pending && !is_smm(vcpu)) {
4153                 if (block_nested_events)
4154                         return -EBUSY;
4155                 goto no_vmexit;
4156         }
4157
4158         if (vcpu->arch.nmi_pending && !vmx_nmi_blocked(vcpu)) {
4159                 if (block_nested_events)
4160                         return -EBUSY;
4161                 if (!nested_exit_on_nmi(vcpu))
4162                         goto no_vmexit;
4163
4164                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
4165                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
4166                                   INTR_INFO_VALID_MASK, 0);
4167                 /*
4168                  * The NMI-triggered VM exit counts as injection:
4169                  * clear this one and block further NMIs.
4170                  */
4171                 vcpu->arch.nmi_pending = 0;
4172                 vmx_set_nmi_mask(vcpu, true);
4173                 return 0;
4174         }
4175
4176         if (kvm_cpu_has_interrupt(vcpu) && !vmx_interrupt_blocked(vcpu)) {
4177                 if (block_nested_events)
4178                         return -EBUSY;
4179                 if (!nested_exit_on_intr(vcpu))
4180                         goto no_vmexit;
4181                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
4182                 return 0;
4183         }
4184
4185 no_vmexit:
4186         return vmx_complete_nested_posted_interrupt(vcpu);
4187 }
4188
4189 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
4190 {
4191         ktime_t remaining =
4192                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
4193         u64 value;
4194
4195         if (ktime_to_ns(remaining) <= 0)
4196                 return 0;
4197
4198         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
4199         do_div(value, 1000000);
4200         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
4201 }
4202
4203 static bool is_vmcs12_ext_field(unsigned long field)
4204 {
4205         switch (field) {
4206         case GUEST_ES_SELECTOR:
4207         case GUEST_CS_SELECTOR:
4208         case GUEST_SS_SELECTOR:
4209         case GUEST_DS_SELECTOR:
4210         case GUEST_FS_SELECTOR:
4211         case GUEST_GS_SELECTOR:
4212         case GUEST_LDTR_SELECTOR:
4213         case GUEST_TR_SELECTOR:
4214         case GUEST_ES_LIMIT:
4215         case GUEST_CS_LIMIT:
4216         case GUEST_SS_LIMIT:
4217         case GUEST_DS_LIMIT:
4218         case GUEST_FS_LIMIT:
4219         case GUEST_GS_LIMIT:
4220         case GUEST_LDTR_LIMIT:
4221         case GUEST_TR_LIMIT:
4222         case GUEST_GDTR_LIMIT:
4223         case GUEST_IDTR_LIMIT:
4224         case GUEST_ES_AR_BYTES:
4225         case GUEST_DS_AR_BYTES:
4226         case GUEST_FS_AR_BYTES:
4227         case GUEST_GS_AR_BYTES:
4228         case GUEST_LDTR_AR_BYTES:
4229         case GUEST_TR_AR_BYTES:
4230         case GUEST_ES_BASE:
4231         case GUEST_CS_BASE:
4232         case GUEST_SS_BASE:
4233         case GUEST_DS_BASE:
4234         case GUEST_FS_BASE:
4235         case GUEST_GS_BASE:
4236         case GUEST_LDTR_BASE:
4237         case GUEST_TR_BASE:
4238         case GUEST_GDTR_BASE:
4239         case GUEST_IDTR_BASE:
4240         case GUEST_PENDING_DBG_EXCEPTIONS:
4241         case GUEST_BNDCFGS:
4242                 return true;
4243         default:
4244                 break;
4245         }
4246
4247         return false;
4248 }
4249
4250 static void sync_vmcs02_to_vmcs12_rare(struct kvm_vcpu *vcpu,
4251                                        struct vmcs12 *vmcs12)
4252 {
4253         struct vcpu_vmx *vmx = to_vmx(vcpu);
4254
4255         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
4256         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
4257         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
4258         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
4259         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
4260         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
4261         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
4262         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
4263         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
4264         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
4265         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
4266         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
4267         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
4268         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
4269         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
4270         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
4271         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
4272         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
4273         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
4274         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
4275         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
4276         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
4277         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
4278         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
4279         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
4280         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
4281         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
4282         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
4283         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
4284         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
4285         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
4286         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
4287         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
4288         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
4289         vmcs12->guest_pending_dbg_exceptions =
4290                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
4291
4292         vmx->nested.need_sync_vmcs02_to_vmcs12_rare = false;
4293 }
4294
4295 static void copy_vmcs02_to_vmcs12_rare(struct kvm_vcpu *vcpu,
4296                                        struct vmcs12 *vmcs12)
4297 {
4298         struct vcpu_vmx *vmx = to_vmx(vcpu);
4299         int cpu;
4300
4301         if (!vmx->nested.need_sync_vmcs02_to_vmcs12_rare)
4302                 return;
4303
4304
4305         WARN_ON_ONCE(vmx->loaded_vmcs != &vmx->vmcs01);
4306
4307         cpu = get_cpu();
4308         vmx->loaded_vmcs = &vmx->nested.vmcs02;
4309         vmx_vcpu_load_vmcs(vcpu, cpu, &vmx->vmcs01);
4310
4311         sync_vmcs02_to_vmcs12_rare(vcpu, vmcs12);
4312
4313         vmx->loaded_vmcs = &vmx->vmcs01;
4314         vmx_vcpu_load_vmcs(vcpu, cpu, &vmx->nested.vmcs02);
4315         put_cpu();
4316 }
4317
4318 /*
4319  * Update the guest state fields of vmcs12 to reflect changes that
4320  * occurred while L2 was running. (The "IA-32e mode guest" bit of the
4321  * VM-entry controls is also updated, since this is really a guest
4322  * state bit.)
4323  */
4324 static void sync_vmcs02_to_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
4325 {
4326         struct vcpu_vmx *vmx = to_vmx(vcpu);
4327
4328         if (evmptr_is_valid(vmx->nested.hv_evmcs_vmptr))
4329                 sync_vmcs02_to_vmcs12_rare(vcpu, vmcs12);
4330
4331         vmx->nested.need_sync_vmcs02_to_vmcs12_rare =
4332                 !evmptr_is_valid(vmx->nested.hv_evmcs_vmptr);
4333
4334         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
4335         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
4336
4337         vmcs12->guest_rsp = kvm_rsp_read(vcpu);
4338         vmcs12->guest_rip = kvm_rip_read(vcpu);
4339         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
4340
4341         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
4342         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
4343
4344         vmcs12->guest_interruptibility_info =
4345                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
4346
4347         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
4348                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
4349         else if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
4350                 vmcs12->guest_activity_state = GUEST_ACTIVITY_WAIT_SIPI;
4351         else
4352                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4353
4354         if (nested_cpu_has_preemption_timer(vmcs12) &&
4355             vmcs12->vm_exit_controls & VM_EXIT_SAVE_VMX_PREEMPTION_TIMER &&
4356             !vmx->nested.nested_run_pending)
4357                 vmcs12->vmx_preemption_timer_value =
4358                         vmx_get_preemption_timer_value(vcpu);
4359
4360         /*
4361          * In some cases (usually, nested EPT), L2 is allowed to change its
4362          * own CR3 without exiting. If it has changed it, we must keep it.
4363          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
4364          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
4365          *
4366          * Additionally, restore L2's PDPTR to vmcs12.
4367          */
4368         if (enable_ept) {
4369                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
4370                 if (nested_cpu_has_ept(vmcs12) && is_pae_paging(vcpu)) {
4371                         vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
4372                         vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
4373                         vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
4374                         vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
4375                 }
4376         }
4377
4378         vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
4379
4380         if (nested_cpu_has_vid(vmcs12))
4381                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
4382
4383         vmcs12->vm_entry_controls =
4384                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
4385                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
4386
4387         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS)
4388                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
4389
4390         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
4391                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4392 }
4393
4394 /*
4395  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
4396  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
4397  * and this function updates it to reflect the changes to the guest state while
4398  * L2 was running (and perhaps made some exits which were handled directly by L0
4399  * without going back to L1), and to reflect the exit reason.
4400  * Note that we do not have to copy here all VMCS fields, just those that
4401  * could have changed by the L2 guest or the exit - i.e., the guest-state and
4402  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
4403  * which already writes to vmcs12 directly.
4404  */
4405 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
4406                            u32 vm_exit_reason, u32 exit_intr_info,
4407                            unsigned long exit_qualification)
4408 {
4409         /* update exit information fields: */
4410         vmcs12->vm_exit_reason = vm_exit_reason;
4411         if (to_vmx(vcpu)->exit_reason.enclave_mode)
4412                 vmcs12->vm_exit_reason |= VMX_EXIT_REASONS_SGX_ENCLAVE_MODE;
4413         vmcs12->exit_qualification = exit_qualification;
4414
4415         /*
4416          * On VM-Exit due to a failed VM-Entry, the VMCS isn't marked launched
4417          * and only EXIT_REASON and EXIT_QUALIFICATION are updated, all other
4418          * exit info fields are unmodified.
4419          */
4420         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
4421                 vmcs12->launch_state = 1;
4422
4423                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
4424                  * instead of reading the real value. */
4425                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
4426
4427                 /*
4428                  * Transfer the event that L0 or L1 may wanted to inject into
4429                  * L2 to IDT_VECTORING_INFO_FIELD.
4430                  */
4431                 vmcs12_save_pending_event(vcpu, vmcs12,
4432                                           vm_exit_reason, exit_intr_info);
4433
4434                 vmcs12->vm_exit_intr_info = exit_intr_info;
4435                 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4436                 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
4437
4438                 /*
4439                  * According to spec, there's no need to store the guest's
4440                  * MSRs if the exit is due to a VM-entry failure that occurs
4441                  * during or after loading the guest state. Since this exit
4442                  * does not fall in that category, we need to save the MSRs.
4443                  */
4444                 if (nested_vmx_store_msr(vcpu,
4445                                          vmcs12->vm_exit_msr_store_addr,
4446                                          vmcs12->vm_exit_msr_store_count))
4447                         nested_vmx_abort(vcpu,
4448                                          VMX_ABORT_SAVE_GUEST_MSR_FAIL);
4449         }
4450 }
4451
4452 /*
4453  * A part of what we need to when the nested L2 guest exits and we want to
4454  * run its L1 parent, is to reset L1's guest state to the host state specified
4455  * in vmcs12.
4456  * This function is to be called not only on normal nested exit, but also on
4457  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
4458  * Failures During or After Loading Guest State").
4459  * This function should be called when the active VMCS is L1's (vmcs01).
4460  */
4461 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
4462                                    struct vmcs12 *vmcs12)
4463 {
4464         enum vm_entry_failure_code ignored;
4465         struct kvm_segment seg;
4466
4467         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
4468                 vcpu->arch.efer = vmcs12->host_ia32_efer;
4469         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4470                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
4471         else
4472                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
4473         vmx_set_efer(vcpu, vcpu->arch.efer);
4474
4475         kvm_rsp_write(vcpu, vmcs12->host_rsp);
4476         kvm_rip_write(vcpu, vmcs12->host_rip);
4477         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4478         vmx_set_interrupt_shadow(vcpu, 0);
4479
4480         /*
4481          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
4482          * actually changed, because vmx_set_cr0 refers to efer set above.
4483          *
4484          * CR0_GUEST_HOST_MASK is already set in the original vmcs01
4485          * (KVM doesn't change it);
4486          */
4487         vcpu->arch.cr0_guest_owned_bits = vmx_l1_guest_owned_cr0_bits();
4488         vmx_set_cr0(vcpu, vmcs12->host_cr0);
4489
4490         /* Same as above - no reason to call set_cr4_guest_host_mask().  */
4491         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
4492         vmx_set_cr4(vcpu, vmcs12->host_cr4);
4493
4494         nested_ept_uninit_mmu_context(vcpu);
4495
4496         /*
4497          * Only PDPTE load can fail as the value of cr3 was checked on entry and
4498          * couldn't have changed.
4499          */
4500         if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, true, &ignored))
4501                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
4502
4503         nested_vmx_transition_tlb_flush(vcpu, vmcs12, false);
4504
4505         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
4506         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
4507         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
4508         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
4509         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4510         vmcs_write32(GUEST_IDTR_LIMIT, 0xFFFF);
4511         vmcs_write32(GUEST_GDTR_LIMIT, 0xFFFF);
4512
4513         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
4514         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
4515                 vmcs_write64(GUEST_BNDCFGS, 0);
4516
4517         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4518                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
4519                 vcpu->arch.pat = vmcs12->host_ia32_pat;
4520         }
4521         if ((vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) &&
4522             intel_pmu_has_perf_global_ctrl(vcpu_to_pmu(vcpu)))
4523                 WARN_ON_ONCE(kvm_set_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL,
4524                                          vmcs12->host_ia32_perf_global_ctrl));
4525
4526         /* Set L1 segment info according to Intel SDM
4527             27.5.2 Loading Host Segment and Descriptor-Table Registers */
4528         seg = (struct kvm_segment) {
4529                 .base = 0,
4530                 .limit = 0xFFFFFFFF,
4531                 .selector = vmcs12->host_cs_selector,
4532                 .type = 11,
4533                 .present = 1,
4534                 .s = 1,
4535                 .g = 1
4536         };
4537         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4538                 seg.l = 1;
4539         else
4540                 seg.db = 1;
4541         __vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
4542         seg = (struct kvm_segment) {
4543                 .base = 0,
4544                 .limit = 0xFFFFFFFF,
4545                 .type = 3,
4546                 .present = 1,
4547                 .s = 1,
4548                 .db = 1,
4549                 .g = 1
4550         };
4551         seg.selector = vmcs12->host_ds_selector;
4552         __vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
4553         seg.selector = vmcs12->host_es_selector;
4554         __vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
4555         seg.selector = vmcs12->host_ss_selector;
4556         __vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
4557         seg.selector = vmcs12->host_fs_selector;
4558         seg.base = vmcs12->host_fs_base;
4559         __vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
4560         seg.selector = vmcs12->host_gs_selector;
4561         seg.base = vmcs12->host_gs_base;
4562         __vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
4563         seg = (struct kvm_segment) {
4564                 .base = vmcs12->host_tr_base,
4565                 .limit = 0x67,
4566                 .selector = vmcs12->host_tr_selector,
4567                 .type = 11,
4568                 .present = 1
4569         };
4570         __vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
4571
4572         memset(&seg, 0, sizeof(seg));
4573         seg.unusable = 1;
4574         __vmx_set_segment(vcpu, &seg, VCPU_SREG_LDTR);
4575
4576         kvm_set_dr(vcpu, 7, 0x400);
4577         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4578
4579         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
4580                                 vmcs12->vm_exit_msr_load_count))
4581                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
4582
4583         to_vmx(vcpu)->emulation_required = vmx_emulation_required(vcpu);
4584 }
4585
4586 static inline u64 nested_vmx_get_vmcs01_guest_efer(struct vcpu_vmx *vmx)
4587 {
4588         struct vmx_uret_msr *efer_msr;
4589         unsigned int i;
4590
4591         if (vm_entry_controls_get(vmx) & VM_ENTRY_LOAD_IA32_EFER)
4592                 return vmcs_read64(GUEST_IA32_EFER);
4593
4594         if (cpu_has_load_ia32_efer())
4595                 return host_efer;
4596
4597         for (i = 0; i < vmx->msr_autoload.guest.nr; ++i) {
4598                 if (vmx->msr_autoload.guest.val[i].index == MSR_EFER)
4599                         return vmx->msr_autoload.guest.val[i].value;
4600         }
4601
4602         efer_msr = vmx_find_uret_msr(vmx, MSR_EFER);
4603         if (efer_msr)
4604                 return efer_msr->data;
4605
4606         return host_efer;
4607 }
4608
4609 static void nested_vmx_restore_host_state(struct kvm_vcpu *vcpu)
4610 {
4611         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4612         struct vcpu_vmx *vmx = to_vmx(vcpu);
4613         struct vmx_msr_entry g, h;
4614         gpa_t gpa;
4615         u32 i, j;
4616
4617         vcpu->arch.pat = vmcs_read64(GUEST_IA32_PAT);
4618
4619         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
4620                 /*
4621                  * L1's host DR7 is lost if KVM_GUESTDBG_USE_HW_BP is set
4622                  * as vmcs01.GUEST_DR7 contains a userspace defined value
4623                  * and vcpu->arch.dr7 is not squirreled away before the
4624                  * nested VMENTER (not worth adding a variable in nested_vmx).
4625                  */
4626                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
4627                         kvm_set_dr(vcpu, 7, DR7_FIXED_1);
4628                 else
4629                         WARN_ON(kvm_set_dr(vcpu, 7, vmcs_readl(GUEST_DR7)));
4630         }
4631
4632         /*
4633          * Note that calling vmx_set_{efer,cr0,cr4} is important as they
4634          * handle a variety of side effects to KVM's software model.
4635          */
4636         vmx_set_efer(vcpu, nested_vmx_get_vmcs01_guest_efer(vmx));
4637
4638         vcpu->arch.cr0_guest_owned_bits = vmx_l1_guest_owned_cr0_bits();
4639         vmx_set_cr0(vcpu, vmcs_readl(CR0_READ_SHADOW));
4640
4641         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
4642         vmx_set_cr4(vcpu, vmcs_readl(CR4_READ_SHADOW));
4643
4644         nested_ept_uninit_mmu_context(vcpu);
4645         vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4646         kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
4647
4648         /*
4649          * Use ept_save_pdptrs(vcpu) to load the MMU's cached PDPTRs
4650          * from vmcs01 (if necessary).  The PDPTRs are not loaded on
4651          * VMFail, like everything else we just need to ensure our
4652          * software model is up-to-date.
4653          */
4654         if (enable_ept && is_pae_paging(vcpu))
4655                 ept_save_pdptrs(vcpu);
4656
4657         kvm_mmu_reset_context(vcpu);
4658
4659         /*
4660          * This nasty bit of open coding is a compromise between blindly
4661          * loading L1's MSRs using the exit load lists (incorrect emulation
4662          * of VMFail), leaving the nested VM's MSRs in the software model
4663          * (incorrect behavior) and snapshotting the modified MSRs (too
4664          * expensive since the lists are unbound by hardware).  For each
4665          * MSR that was (prematurely) loaded from the nested VMEntry load
4666          * list, reload it from the exit load list if it exists and differs
4667          * from the guest value.  The intent is to stuff host state as
4668          * silently as possible, not to fully process the exit load list.
4669          */
4670         for (i = 0; i < vmcs12->vm_entry_msr_load_count; i++) {
4671                 gpa = vmcs12->vm_entry_msr_load_addr + (i * sizeof(g));
4672                 if (kvm_vcpu_read_guest(vcpu, gpa, &g, sizeof(g))) {
4673                         pr_debug_ratelimited(
4674                                 "%s read MSR index failed (%u, 0x%08llx)\n",
4675                                 __func__, i, gpa);
4676                         goto vmabort;
4677                 }
4678
4679                 for (j = 0; j < vmcs12->vm_exit_msr_load_count; j++) {
4680                         gpa = vmcs12->vm_exit_msr_load_addr + (j * sizeof(h));
4681                         if (kvm_vcpu_read_guest(vcpu, gpa, &h, sizeof(h))) {
4682                                 pr_debug_ratelimited(
4683                                         "%s read MSR failed (%u, 0x%08llx)\n",
4684                                         __func__, j, gpa);
4685                                 goto vmabort;
4686                         }
4687                         if (h.index != g.index)
4688                                 continue;
4689                         if (h.value == g.value)
4690                                 break;
4691
4692                         if (nested_vmx_load_msr_check(vcpu, &h)) {
4693                                 pr_debug_ratelimited(
4694                                         "%s check failed (%u, 0x%x, 0x%x)\n",
4695                                         __func__, j, h.index, h.reserved);
4696                                 goto vmabort;
4697                         }
4698
4699                         if (kvm_set_msr(vcpu, h.index, h.value)) {
4700                                 pr_debug_ratelimited(
4701                                         "%s WRMSR failed (%u, 0x%x, 0x%llx)\n",
4702                                         __func__, j, h.index, h.value);
4703                                 goto vmabort;
4704                         }
4705                 }
4706         }
4707
4708         return;
4709
4710 vmabort:
4711         nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
4712 }
4713
4714 /*
4715  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
4716  * and modify vmcs12 to make it see what it would expect to see there if
4717  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
4718  */
4719 void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 vm_exit_reason,
4720                        u32 exit_intr_info, unsigned long exit_qualification)
4721 {
4722         struct vcpu_vmx *vmx = to_vmx(vcpu);
4723         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4724
4725         /* Pending MTF traps are discarded on VM-Exit. */
4726         vmx->nested.mtf_pending = false;
4727
4728         /* trying to cancel vmlaunch/vmresume is a bug */
4729         WARN_ON_ONCE(vmx->nested.nested_run_pending);
4730
4731         if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) {
4732                 /*
4733                  * KVM_REQ_GET_NESTED_STATE_PAGES is also used to map
4734                  * Enlightened VMCS after migration and we still need to
4735                  * do that when something is forcing L2->L1 exit prior to
4736                  * the first L2 run.
4737                  */
4738                 (void)nested_get_evmcs_page(vcpu);
4739         }
4740
4741         /* Service pending TLB flush requests for L2 before switching to L1. */
4742         kvm_service_local_tlb_flush_requests(vcpu);
4743
4744         /*
4745          * VCPU_EXREG_PDPTR will be clobbered in arch/x86/kvm/vmx/vmx.h between
4746          * now and the new vmentry.  Ensure that the VMCS02 PDPTR fields are
4747          * up-to-date before switching to L1.
4748          */
4749         if (enable_ept && is_pae_paging(vcpu))
4750                 vmx_ept_load_pdptrs(vcpu);
4751
4752         leave_guest_mode(vcpu);
4753
4754         if (nested_cpu_has_preemption_timer(vmcs12))
4755                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
4756
4757         if (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETTING)) {
4758                 vcpu->arch.tsc_offset = vcpu->arch.l1_tsc_offset;
4759                 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_TSC_SCALING))
4760                         vcpu->arch.tsc_scaling_ratio = vcpu->arch.l1_tsc_scaling_ratio;
4761         }
4762
4763         if (likely(!vmx->fail)) {
4764                 sync_vmcs02_to_vmcs12(vcpu, vmcs12);
4765
4766                 if (vm_exit_reason != -1)
4767                         prepare_vmcs12(vcpu, vmcs12, vm_exit_reason,
4768                                        exit_intr_info, exit_qualification);
4769
4770                 /*
4771                  * Must happen outside of sync_vmcs02_to_vmcs12() as it will
4772                  * also be used to capture vmcs12 cache as part of
4773                  * capturing nVMX state for snapshot (migration).
4774                  *
4775                  * Otherwise, this flush will dirty guest memory at a
4776                  * point it is already assumed by user-space to be
4777                  * immutable.
4778                  */
4779                 nested_flush_cached_shadow_vmcs12(vcpu, vmcs12);
4780         } else {
4781                 /*
4782                  * The only expected VM-instruction error is "VM entry with
4783                  * invalid control field(s)." Anything else indicates a
4784                  * problem with L0.  And we should never get here with a
4785                  * VMFail of any type if early consistency checks are enabled.
4786                  */
4787                 WARN_ON_ONCE(vmcs_read32(VM_INSTRUCTION_ERROR) !=
4788                              VMXERR_ENTRY_INVALID_CONTROL_FIELD);
4789                 WARN_ON_ONCE(nested_early_check);
4790         }
4791
4792         /*
4793          * Drop events/exceptions that were queued for re-injection to L2
4794          * (picked up via vmx_complete_interrupts()), as well as exceptions
4795          * that were pending for L2.  Note, this must NOT be hoisted above
4796          * prepare_vmcs12(), events/exceptions queued for re-injection need to
4797          * be captured in vmcs12 (see vmcs12_save_pending_event()).
4798          */
4799         vcpu->arch.nmi_injected = false;
4800         kvm_clear_exception_queue(vcpu);
4801         kvm_clear_interrupt_queue(vcpu);
4802
4803         vmx_switch_vmcs(vcpu, &vmx->vmcs01);
4804
4805         /*
4806          * If IBRS is advertised to the vCPU, KVM must flush the indirect
4807          * branch predictors when transitioning from L2 to L1, as L1 expects
4808          * hardware (KVM in this case) to provide separate predictor modes.
4809          * Bare metal isolates VMX root (host) from VMX non-root (guest), but
4810          * doesn't isolate different VMCSs, i.e. in this case, doesn't provide
4811          * separate modes for L2 vs L1.
4812          */
4813         if (guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
4814                 indirect_branch_prediction_barrier();
4815
4816         /* Update any VMCS fields that might have changed while L2 ran */
4817         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr);
4818         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr);
4819         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
4820         if (kvm_caps.has_tsc_control)
4821                 vmcs_write64(TSC_MULTIPLIER, vcpu->arch.tsc_scaling_ratio);
4822
4823         if (vmx->nested.l1_tpr_threshold != -1)
4824                 vmcs_write32(TPR_THRESHOLD, vmx->nested.l1_tpr_threshold);
4825
4826         if (vmx->nested.change_vmcs01_virtual_apic_mode) {
4827                 vmx->nested.change_vmcs01_virtual_apic_mode = false;
4828                 vmx_set_virtual_apic_mode(vcpu);
4829         }
4830
4831         if (vmx->nested.update_vmcs01_cpu_dirty_logging) {
4832                 vmx->nested.update_vmcs01_cpu_dirty_logging = false;
4833                 vmx_update_cpu_dirty_logging(vcpu);
4834         }
4835
4836         /* Unpin physical memory we referred to in vmcs02 */
4837         kvm_vcpu_unmap(vcpu, &vmx->nested.apic_access_page_map, false);
4838         kvm_vcpu_unmap(vcpu, &vmx->nested.virtual_apic_map, true);
4839         kvm_vcpu_unmap(vcpu, &vmx->nested.pi_desc_map, true);
4840         vmx->nested.pi_desc = NULL;
4841
4842         if (vmx->nested.reload_vmcs01_apic_access_page) {
4843                 vmx->nested.reload_vmcs01_apic_access_page = false;
4844                 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4845         }
4846
4847         if (vmx->nested.update_vmcs01_apicv_status) {
4848                 vmx->nested.update_vmcs01_apicv_status = false;
4849                 kvm_make_request(KVM_REQ_APICV_UPDATE, vcpu);
4850         }
4851
4852         if ((vm_exit_reason != -1) &&
4853             (enable_shadow_vmcs || evmptr_is_valid(vmx->nested.hv_evmcs_vmptr)))
4854                 vmx->nested.need_vmcs12_to_shadow_sync = true;
4855
4856         /* in case we halted in L2 */
4857         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4858
4859         if (likely(!vmx->fail)) {
4860                 if ((u16)vm_exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT &&
4861                     nested_exit_intr_ack_set(vcpu)) {
4862                         int irq = kvm_cpu_get_interrupt(vcpu);
4863                         WARN_ON(irq < 0);
4864                         vmcs12->vm_exit_intr_info = irq |
4865                                 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
4866                 }
4867
4868                 if (vm_exit_reason != -1)
4869                         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
4870                                                        vmcs12->exit_qualification,
4871                                                        vmcs12->idt_vectoring_info_field,
4872                                                        vmcs12->vm_exit_intr_info,
4873                                                        vmcs12->vm_exit_intr_error_code,
4874                                                        KVM_ISA_VMX);
4875
4876                 load_vmcs12_host_state(vcpu, vmcs12);
4877
4878                 return;
4879         }
4880
4881         /*
4882          * After an early L2 VM-entry failure, we're now back
4883          * in L1 which thinks it just finished a VMLAUNCH or
4884          * VMRESUME instruction, so we need to set the failure
4885          * flag and the VM-instruction error field of the VMCS
4886          * accordingly, and skip the emulated instruction.
4887          */
4888         (void)nested_vmx_fail(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
4889
4890         /*
4891          * Restore L1's host state to KVM's software model.  We're here
4892          * because a consistency check was caught by hardware, which
4893          * means some amount of guest state has been propagated to KVM's
4894          * model and needs to be unwound to the host's state.
4895          */
4896         nested_vmx_restore_host_state(vcpu);
4897
4898         vmx->fail = 0;
4899 }
4900
4901 static void nested_vmx_triple_fault(struct kvm_vcpu *vcpu)
4902 {
4903         kvm_clear_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4904         nested_vmx_vmexit(vcpu, EXIT_REASON_TRIPLE_FAULT, 0, 0);
4905 }
4906
4907 /*
4908  * Decode the memory-address operand of a vmx instruction, as recorded on an
4909  * exit caused by such an instruction (run by a guest hypervisor).
4910  * On success, returns 0. When the operand is invalid, returns 1 and throws
4911  * #UD, #GP, or #SS.
4912  */
4913 int get_vmx_mem_address(struct kvm_vcpu *vcpu, unsigned long exit_qualification,
4914                         u32 vmx_instruction_info, bool wr, int len, gva_t *ret)
4915 {
4916         gva_t off;
4917         bool exn;
4918         struct kvm_segment s;
4919
4920         /*
4921          * According to Vol. 3B, "Information for VM Exits Due to Instruction
4922          * Execution", on an exit, vmx_instruction_info holds most of the
4923          * addressing components of the operand. Only the displacement part
4924          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
4925          * For how an actual address is calculated from all these components,
4926          * refer to Vol. 1, "Operand Addressing".
4927          */
4928         int  scaling = vmx_instruction_info & 3;
4929         int  addr_size = (vmx_instruction_info >> 7) & 7;
4930         bool is_reg = vmx_instruction_info & (1u << 10);
4931         int  seg_reg = (vmx_instruction_info >> 15) & 7;
4932         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
4933         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
4934         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
4935         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
4936
4937         if (is_reg) {
4938                 kvm_queue_exception(vcpu, UD_VECTOR);
4939                 return 1;
4940         }
4941
4942         /* Addr = segment_base + offset */
4943         /* offset = base + [index * scale] + displacement */
4944         off = exit_qualification; /* holds the displacement */
4945         if (addr_size == 1)
4946                 off = (gva_t)sign_extend64(off, 31);
4947         else if (addr_size == 0)
4948                 off = (gva_t)sign_extend64(off, 15);
4949         if (base_is_valid)
4950                 off += kvm_register_read(vcpu, base_reg);
4951         if (index_is_valid)
4952                 off += kvm_register_read(vcpu, index_reg) << scaling;
4953         vmx_get_segment(vcpu, &s, seg_reg);
4954
4955         /*
4956          * The effective address, i.e. @off, of a memory operand is truncated
4957          * based on the address size of the instruction.  Note that this is
4958          * the *effective address*, i.e. the address prior to accounting for
4959          * the segment's base.
4960          */
4961         if (addr_size == 1) /* 32 bit */
4962                 off &= 0xffffffff;
4963         else if (addr_size == 0) /* 16 bit */
4964                 off &= 0xffff;
4965
4966         /* Checks for #GP/#SS exceptions. */
4967         exn = false;
4968         if (is_long_mode(vcpu)) {
4969                 /*
4970                  * The virtual/linear address is never truncated in 64-bit
4971                  * mode, e.g. a 32-bit address size can yield a 64-bit virtual
4972                  * address when using FS/GS with a non-zero base.
4973                  */
4974                 if (seg_reg == VCPU_SREG_FS || seg_reg == VCPU_SREG_GS)
4975                         *ret = s.base + off;
4976                 else
4977                         *ret = off;
4978
4979                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
4980                  * non-canonical form. This is the only check on the memory
4981                  * destination for long mode!
4982                  */
4983                 exn = is_noncanonical_address(*ret, vcpu);
4984         } else {
4985                 /*
4986                  * When not in long mode, the virtual/linear address is
4987                  * unconditionally truncated to 32 bits regardless of the
4988                  * address size.
4989                  */
4990                 *ret = (s.base + off) & 0xffffffff;
4991
4992                 /* Protected mode: apply checks for segment validity in the
4993                  * following order:
4994                  * - segment type check (#GP(0) may be thrown)
4995                  * - usability check (#GP(0)/#SS(0))
4996                  * - limit check (#GP(0)/#SS(0))
4997                  */
4998                 if (wr)
4999                         /* #GP(0) if the destination operand is located in a
5000                          * read-only data segment or any code segment.
5001                          */
5002                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
5003                 else
5004                         /* #GP(0) if the source operand is located in an
5005                          * execute-only code segment
5006                          */
5007                         exn = ((s.type & 0xa) == 8);
5008                 if (exn) {
5009                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
5010                         return 1;
5011                 }
5012                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
5013                  */
5014                 exn = (s.unusable != 0);
5015
5016                 /*
5017                  * Protected mode: #GP(0)/#SS(0) if the memory operand is
5018                  * outside the segment limit.  All CPUs that support VMX ignore
5019                  * limit checks for flat segments, i.e. segments with base==0,
5020                  * limit==0xffffffff and of type expand-up data or code.
5021                  */
5022                 if (!(s.base == 0 && s.limit == 0xffffffff &&
5023                      ((s.type & 8) || !(s.type & 4))))
5024                         exn = exn || ((u64)off + len - 1 > s.limit);
5025         }
5026         if (exn) {
5027                 kvm_queue_exception_e(vcpu,
5028                                       seg_reg == VCPU_SREG_SS ?
5029                                                 SS_VECTOR : GP_VECTOR,
5030                                       0);
5031                 return 1;
5032         }
5033
5034         return 0;
5035 }
5036
5037 static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer,
5038                                 int *ret)
5039 {
5040         gva_t gva;
5041         struct x86_exception e;
5042         int r;
5043
5044         if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu),
5045                                 vmcs_read32(VMX_INSTRUCTION_INFO), false,
5046                                 sizeof(*vmpointer), &gva)) {
5047                 *ret = 1;
5048                 return -EINVAL;
5049         }
5050
5051         r = kvm_read_guest_virt(vcpu, gva, vmpointer, sizeof(*vmpointer), &e);
5052         if (r != X86EMUL_CONTINUE) {
5053                 *ret = kvm_handle_memory_failure(vcpu, r, &e);
5054                 return -EINVAL;
5055         }
5056
5057         return 0;
5058 }
5059
5060 /*
5061  * Allocate a shadow VMCS and associate it with the currently loaded
5062  * VMCS, unless such a shadow VMCS already exists. The newly allocated
5063  * VMCS is also VMCLEARed, so that it is ready for use.
5064  */
5065 static struct vmcs *alloc_shadow_vmcs(struct kvm_vcpu *vcpu)
5066 {
5067         struct vcpu_vmx *vmx = to_vmx(vcpu);
5068         struct loaded_vmcs *loaded_vmcs = vmx->loaded_vmcs;
5069
5070         /*
5071          * KVM allocates a shadow VMCS only when L1 executes VMXON and frees it
5072          * when L1 executes VMXOFF or the vCPU is forced out of nested
5073          * operation.  VMXON faults if the CPU is already post-VMXON, so it
5074          * should be impossible to already have an allocated shadow VMCS.  KVM
5075          * doesn't support virtualization of VMCS shadowing, so vmcs01 should
5076          * always be the loaded VMCS.
5077          */
5078         if (WARN_ON(loaded_vmcs != &vmx->vmcs01 || loaded_vmcs->shadow_vmcs))
5079                 return loaded_vmcs->shadow_vmcs;
5080
5081         loaded_vmcs->shadow_vmcs = alloc_vmcs(true);
5082         if (loaded_vmcs->shadow_vmcs)
5083                 vmcs_clear(loaded_vmcs->shadow_vmcs);
5084
5085         return loaded_vmcs->shadow_vmcs;
5086 }
5087
5088 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
5089 {
5090         struct vcpu_vmx *vmx = to_vmx(vcpu);
5091         int r;
5092
5093         r = alloc_loaded_vmcs(&vmx->nested.vmcs02);
5094         if (r < 0)
5095                 goto out_vmcs02;
5096
5097         vmx->nested.cached_vmcs12 = kzalloc(VMCS12_SIZE, GFP_KERNEL_ACCOUNT);
5098         if (!vmx->nested.cached_vmcs12)
5099                 goto out_cached_vmcs12;
5100
5101         vmx->nested.shadow_vmcs12_cache.gpa = INVALID_GPA;
5102         vmx->nested.cached_shadow_vmcs12 = kzalloc(VMCS12_SIZE, GFP_KERNEL_ACCOUNT);
5103         if (!vmx->nested.cached_shadow_vmcs12)
5104                 goto out_cached_shadow_vmcs12;
5105
5106         if (enable_shadow_vmcs && !alloc_shadow_vmcs(vcpu))
5107                 goto out_shadow_vmcs;
5108
5109         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
5110                      HRTIMER_MODE_ABS_PINNED);
5111         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
5112
5113         vmx->nested.vpid02 = allocate_vpid();
5114
5115         vmx->nested.vmcs02_initialized = false;
5116         vmx->nested.vmxon = true;
5117
5118         if (vmx_pt_mode_is_host_guest()) {
5119                 vmx->pt_desc.guest.ctl = 0;
5120                 pt_update_intercept_for_msr(vcpu);
5121         }
5122
5123         return 0;
5124
5125 out_shadow_vmcs:
5126         kfree(vmx->nested.cached_shadow_vmcs12);
5127
5128 out_cached_shadow_vmcs12:
5129         kfree(vmx->nested.cached_vmcs12);
5130
5131 out_cached_vmcs12:
5132         free_loaded_vmcs(&vmx->nested.vmcs02);
5133
5134 out_vmcs02:
5135         return -ENOMEM;
5136 }
5137
5138 /* Emulate the VMXON instruction. */
5139 static int handle_vmxon(struct kvm_vcpu *vcpu)
5140 {
5141         int ret;
5142         gpa_t vmptr;
5143         uint32_t revision;
5144         struct vcpu_vmx *vmx = to_vmx(vcpu);
5145         const u64 VMXON_NEEDED_FEATURES = FEAT_CTL_LOCKED
5146                 | FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX;
5147
5148         /*
5149          * Manually check CR4.VMXE checks, KVM must force CR4.VMXE=1 to enter
5150          * the guest and so cannot rely on hardware to perform the check,
5151          * which has higher priority than VM-Exit (see Intel SDM's pseudocode
5152          * for VMXON).
5153          *
5154          * Rely on hardware for the other pre-VM-Exit checks, CR0.PE=1, !VM86
5155          * and !COMPATIBILITY modes.  For an unrestricted guest, KVM doesn't
5156          * force any of the relevant guest state.  For a restricted guest, KVM
5157          * does force CR0.PE=1, but only to also force VM86 in order to emulate
5158          * Real Mode, and so there's no need to check CR0.PE manually.
5159          */
5160         if (!kvm_is_cr4_bit_set(vcpu, X86_CR4_VMXE)) {
5161                 kvm_queue_exception(vcpu, UD_VECTOR);
5162                 return 1;
5163         }
5164
5165         /*
5166          * The CPL is checked for "not in VMX operation" and for "in VMX root",
5167          * and has higher priority than the VM-Fail due to being post-VMXON,
5168          * i.e. VMXON #GPs outside of VMX non-root if CPL!=0.  In VMX non-root,
5169          * VMXON causes VM-Exit and KVM unconditionally forwards VMXON VM-Exits
5170          * from L2 to L1, i.e. there's no need to check for the vCPU being in
5171          * VMX non-root.
5172          *
5173          * Forwarding the VM-Exit unconditionally, i.e. without performing the
5174          * #UD checks (see above), is functionally ok because KVM doesn't allow
5175          * L1 to run L2 without CR4.VMXE=0, and because KVM never modifies L2's
5176          * CR0 or CR4, i.e. it's L2's responsibility to emulate #UDs that are
5177          * missed by hardware due to shadowing CR0 and/or CR4.
5178          */
5179         if (vmx_get_cpl(vcpu)) {
5180                 kvm_inject_gp(vcpu, 0);
5181                 return 1;
5182         }
5183
5184         if (vmx->nested.vmxon)
5185                 return nested_vmx_fail(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5186
5187         /*
5188          * Invalid CR0/CR4 generates #GP.  These checks are performed if and
5189          * only if the vCPU isn't already in VMX operation, i.e. effectively
5190          * have lower priority than the VM-Fail above.
5191          */
5192         if (!nested_host_cr0_valid(vcpu, kvm_read_cr0(vcpu)) ||
5193             !nested_host_cr4_valid(vcpu, kvm_read_cr4(vcpu))) {
5194                 kvm_inject_gp(vcpu, 0);
5195                 return 1;
5196         }
5197
5198         if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5199                         != VMXON_NEEDED_FEATURES) {
5200                 kvm_inject_gp(vcpu, 0);
5201                 return 1;
5202         }
5203
5204         if (nested_vmx_get_vmptr(vcpu, &vmptr, &ret))
5205                 return ret;
5206
5207         /*
5208          * SDM 3: 24.11.5
5209          * The first 4 bytes of VMXON region contain the supported
5210          * VMCS revision identifier
5211          *
5212          * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
5213          * which replaces physical address width with 32
5214          */
5215         if (!page_address_valid(vcpu, vmptr))
5216                 return nested_vmx_failInvalid(vcpu);
5217
5218         if (kvm_read_guest(vcpu->kvm, vmptr, &revision, sizeof(revision)) ||
5219             revision != VMCS12_REVISION)
5220                 return nested_vmx_failInvalid(vcpu);
5221
5222         vmx->nested.vmxon_ptr = vmptr;
5223         ret = enter_vmx_operation(vcpu);
5224         if (ret)
5225                 return ret;
5226
5227         return nested_vmx_succeed(vcpu);
5228 }
5229
5230 static inline void nested_release_vmcs12(struct kvm_vcpu *vcpu)
5231 {
5232         struct vcpu_vmx *vmx = to_vmx(vcpu);
5233
5234         if (vmx->nested.current_vmptr == INVALID_GPA)
5235                 return;
5236
5237         copy_vmcs02_to_vmcs12_rare(vcpu, get_vmcs12(vcpu));
5238
5239         if (enable_shadow_vmcs) {
5240                 /* copy to memory all shadowed fields in case
5241                    they were modified */
5242                 copy_shadow_to_vmcs12(vmx);
5243                 vmx_disable_shadow_vmcs(vmx);
5244         }
5245         vmx->nested.posted_intr_nv = -1;
5246
5247         /* Flush VMCS12 to guest memory */
5248         kvm_vcpu_write_guest_page(vcpu,
5249                                   vmx->nested.current_vmptr >> PAGE_SHIFT,
5250                                   vmx->nested.cached_vmcs12, 0, VMCS12_SIZE);
5251
5252         kvm_mmu_free_roots(vcpu->kvm, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL);
5253
5254         vmx->nested.current_vmptr = INVALID_GPA;
5255 }
5256
5257 /* Emulate the VMXOFF instruction */
5258 static int handle_vmxoff(struct kvm_vcpu *vcpu)
5259 {
5260         if (!nested_vmx_check_permission(vcpu))
5261                 return 1;
5262
5263         free_nested(vcpu);
5264
5265         if (kvm_apic_has_pending_init_or_sipi(vcpu))
5266                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5267
5268         return nested_vmx_succeed(vcpu);
5269 }
5270
5271 /* Emulate the VMCLEAR instruction */
5272 static int handle_vmclear(struct kvm_vcpu *vcpu)
5273 {
5274         struct vcpu_vmx *vmx = to_vmx(vcpu);
5275         u32 zero = 0;
5276         gpa_t vmptr;
5277         int r;
5278
5279         if (!nested_vmx_check_permission(vcpu))
5280                 return 1;
5281
5282         if (nested_vmx_get_vmptr(vcpu, &vmptr, &r))
5283                 return r;
5284
5285         if (!page_address_valid(vcpu, vmptr))
5286                 return nested_vmx_fail(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5287
5288         if (vmptr == vmx->nested.vmxon_ptr)
5289                 return nested_vmx_fail(vcpu, VMXERR_VMCLEAR_VMXON_POINTER);
5290
5291         /*
5292          * When Enlightened VMEntry is enabled on the calling CPU we treat
5293          * memory area pointer by vmptr as Enlightened VMCS (as there's no good
5294          * way to distinguish it from VMCS12) and we must not corrupt it by
5295          * writing to the non-existent 'launch_state' field. The area doesn't
5296          * have to be the currently active EVMCS on the calling CPU and there's
5297          * nothing KVM has to do to transition it from 'active' to 'non-active'
5298          * state. It is possible that the area will stay mapped as
5299          * vmx->nested.hv_evmcs but this shouldn't be a problem.
5300          */
5301         if (likely(!guest_cpuid_has_evmcs(vcpu) ||
5302                    !evmptr_is_valid(nested_get_evmptr(vcpu)))) {
5303                 if (vmptr == vmx->nested.current_vmptr)
5304                         nested_release_vmcs12(vcpu);
5305
5306                 /*
5307                  * Silently ignore memory errors on VMCLEAR, Intel's pseudocode
5308                  * for VMCLEAR includes a "ensure that data for VMCS referenced
5309                  * by the operand is in memory" clause that guards writes to
5310                  * memory, i.e. doing nothing for I/O is architecturally valid.
5311                  *
5312                  * FIXME: Suppress failures if and only if no memslot is found,
5313                  * i.e. exit to userspace if __copy_to_user() fails.
5314                  */
5315                 (void)kvm_vcpu_write_guest(vcpu,
5316                                            vmptr + offsetof(struct vmcs12,
5317                                                             launch_state),
5318                                            &zero, sizeof(zero));
5319         } else if (vmx->nested.hv_evmcs && vmptr == vmx->nested.hv_evmcs_vmptr) {
5320                 nested_release_evmcs(vcpu);
5321         }
5322
5323         return nested_vmx_succeed(vcpu);
5324 }
5325
5326 /* Emulate the VMLAUNCH instruction */
5327 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5328 {
5329         return nested_vmx_run(vcpu, true);
5330 }
5331
5332 /* Emulate the VMRESUME instruction */
5333 static int handle_vmresume(struct kvm_vcpu *vcpu)
5334 {
5335
5336         return nested_vmx_run(vcpu, false);
5337 }
5338
5339 static int handle_vmread(struct kvm_vcpu *vcpu)
5340 {
5341         struct vmcs12 *vmcs12 = is_guest_mode(vcpu) ? get_shadow_vmcs12(vcpu)
5342                                                     : get_vmcs12(vcpu);
5343         unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5344         u32 instr_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5345         struct vcpu_vmx *vmx = to_vmx(vcpu);
5346         struct x86_exception e;
5347         unsigned long field;
5348         u64 value;
5349         gva_t gva = 0;
5350         short offset;
5351         int len, r;
5352
5353         if (!nested_vmx_check_permission(vcpu))
5354                 return 1;
5355
5356         /* Decode instruction info and find the field to read */
5357         field = kvm_register_read(vcpu, (((instr_info) >> 28) & 0xf));
5358
5359         if (!evmptr_is_valid(vmx->nested.hv_evmcs_vmptr)) {
5360                 /*
5361                  * In VMX non-root operation, when the VMCS-link pointer is INVALID_GPA,
5362                  * any VMREAD sets the ALU flags for VMfailInvalid.
5363                  */
5364                 if (vmx->nested.current_vmptr == INVALID_GPA ||
5365                     (is_guest_mode(vcpu) &&
5366                      get_vmcs12(vcpu)->vmcs_link_pointer == INVALID_GPA))
5367                         return nested_vmx_failInvalid(vcpu);
5368
5369                 offset = get_vmcs12_field_offset(field);
5370                 if (offset < 0)
5371                         return nested_vmx_fail(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5372
5373                 if (!is_guest_mode(vcpu) && is_vmcs12_ext_field(field))
5374                         copy_vmcs02_to_vmcs12_rare(vcpu, vmcs12);
5375
5376                 /* Read the field, zero-extended to a u64 value */
5377                 value = vmcs12_read_any(vmcs12, field, offset);
5378         } else {
5379                 /*
5380                  * Hyper-V TLFS (as of 6.0b) explicitly states, that while an
5381                  * enlightened VMCS is active VMREAD/VMWRITE instructions are
5382                  * unsupported. Unfortunately, certain versions of Windows 11
5383                  * don't comply with this requirement which is not enforced in
5384                  * genuine Hyper-V. Allow VMREAD from an enlightened VMCS as a
5385                  * workaround, as misbehaving guests will panic on VM-Fail.
5386                  * Note, enlightened VMCS is incompatible with shadow VMCS so
5387                  * all VMREADs from L2 should go to L1.
5388                  */
5389                 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
5390                         return nested_vmx_failInvalid(vcpu);
5391
5392                 offset = evmcs_field_offset(field, NULL);
5393                 if (offset < 0)
5394                         return nested_vmx_fail(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5395
5396                 /* Read the field, zero-extended to a u64 value */
5397                 value = evmcs_read_any(vmx->nested.hv_evmcs, field, offset);
5398         }
5399
5400         /*
5401          * Now copy part of this value to register or memory, as requested.
5402          * Note that the number of bits actually copied is 32 or 64 depending
5403          * on the guest's mode (32 or 64 bit), not on the given field's length.
5404          */
5405         if (instr_info & BIT(10)) {
5406                 kvm_register_write(vcpu, (((instr_info) >> 3) & 0xf), value);
5407         } else {
5408                 len = is_64_bit_mode(vcpu) ? 8 : 4;
5409                 if (get_vmx_mem_address(vcpu, exit_qualification,
5410                                         instr_info, true, len, &gva))
5411                         return 1;
5412                 /* _system ok, nested_vmx_check_permission has verified cpl=0 */
5413                 r = kvm_write_guest_virt_system(vcpu, gva, &value, len, &e);
5414                 if (r != X86EMUL_CONTINUE)
5415                         return kvm_handle_memory_failure(vcpu, r, &e);
5416         }
5417
5418         return nested_vmx_succeed(vcpu);
5419 }
5420
5421 static bool is_shadow_field_rw(unsigned long field)
5422 {
5423         switch (field) {
5424 #define SHADOW_FIELD_RW(x, y) case x:
5425 #include "vmcs_shadow_fields.h"
5426                 return true;
5427         default:
5428                 break;
5429         }
5430         return false;
5431 }
5432
5433 static bool is_shadow_field_ro(unsigned long field)
5434 {
5435         switch (field) {
5436 #define SHADOW_FIELD_RO(x, y) case x:
5437 #include "vmcs_shadow_fields.h"
5438                 return true;
5439         default:
5440                 break;
5441         }
5442         return false;
5443 }
5444
5445 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5446 {
5447         struct vmcs12 *vmcs12 = is_guest_mode(vcpu) ? get_shadow_vmcs12(vcpu)
5448                                                     : get_vmcs12(vcpu);
5449         unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5450         u32 instr_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5451         struct vcpu_vmx *vmx = to_vmx(vcpu);
5452         struct x86_exception e;
5453         unsigned long field;
5454         short offset;
5455         gva_t gva;
5456         int len, r;
5457
5458         /*
5459          * The value to write might be 32 or 64 bits, depending on L1's long
5460          * mode, and eventually we need to write that into a field of several
5461          * possible lengths. The code below first zero-extends the value to 64
5462          * bit (value), and then copies only the appropriate number of
5463          * bits into the vmcs12 field.
5464          */
5465         u64 value = 0;
5466
5467         if (!nested_vmx_check_permission(vcpu))
5468                 return 1;
5469
5470         /*
5471          * In VMX non-root operation, when the VMCS-link pointer is INVALID_GPA,
5472          * any VMWRITE sets the ALU flags for VMfailInvalid.
5473          */
5474         if (vmx->nested.current_vmptr == INVALID_GPA ||
5475             (is_guest_mode(vcpu) &&
5476              get_vmcs12(vcpu)->vmcs_link_pointer == INVALID_GPA))
5477                 return nested_vmx_failInvalid(vcpu);
5478
5479         if (instr_info & BIT(10))
5480                 value = kvm_register_read(vcpu, (((instr_info) >> 3) & 0xf));
5481         else {
5482                 len = is_64_bit_mode(vcpu) ? 8 : 4;
5483                 if (get_vmx_mem_address(vcpu, exit_qualification,
5484                                         instr_info, false, len, &gva))
5485                         return 1;
5486                 r = kvm_read_guest_virt(vcpu, gva, &value, len, &e);
5487                 if (r != X86EMUL_CONTINUE)
5488                         return kvm_handle_memory_failure(vcpu, r, &e);
5489         }
5490
5491         field = kvm_register_read(vcpu, (((instr_info) >> 28) & 0xf));
5492
5493         offset = get_vmcs12_field_offset(field);
5494         if (offset < 0)
5495                 return nested_vmx_fail(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5496
5497         /*
5498          * If the vCPU supports "VMWRITE to any supported field in the
5499          * VMCS," then the "read-only" fields are actually read/write.
5500          */
5501         if (vmcs_field_readonly(field) &&
5502             !nested_cpu_has_vmwrite_any_field(vcpu))
5503                 return nested_vmx_fail(vcpu, VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5504
5505         /*
5506          * Ensure vmcs12 is up-to-date before any VMWRITE that dirties
5507          * vmcs12, else we may crush a field or consume a stale value.
5508          */
5509         if (!is_guest_mode(vcpu) && !is_shadow_field_rw(field))
5510                 copy_vmcs02_to_vmcs12_rare(vcpu, vmcs12);
5511
5512         /*
5513          * Some Intel CPUs intentionally drop the reserved bits of the AR byte
5514          * fields on VMWRITE.  Emulate this behavior to ensure consistent KVM
5515          * behavior regardless of the underlying hardware, e.g. if an AR_BYTE
5516          * field is intercepted for VMWRITE but not VMREAD (in L1), then VMREAD
5517          * from L1 will return a different value than VMREAD from L2 (L1 sees
5518          * the stripped down value, L2 sees the full value as stored by KVM).
5519          */
5520         if (field >= GUEST_ES_AR_BYTES && field <= GUEST_TR_AR_BYTES)
5521                 value &= 0x1f0ff;
5522
5523         vmcs12_write_any(vmcs12, field, offset, value);
5524
5525         /*
5526          * Do not track vmcs12 dirty-state if in guest-mode as we actually
5527          * dirty shadow vmcs12 instead of vmcs12.  Fields that can be updated
5528          * by L1 without a vmexit are always updated in the vmcs02, i.e. don't
5529          * "dirty" vmcs12, all others go down the prepare_vmcs02() slow path.
5530          */
5531         if (!is_guest_mode(vcpu) && !is_shadow_field_rw(field)) {
5532                 /*
5533                  * L1 can read these fields without exiting, ensure the
5534                  * shadow VMCS is up-to-date.
5535                  */
5536                 if (enable_shadow_vmcs && is_shadow_field_ro(field)) {
5537                         preempt_disable();
5538                         vmcs_load(vmx->vmcs01.shadow_vmcs);
5539
5540                         __vmcs_writel(field, value);
5541
5542                         vmcs_clear(vmx->vmcs01.shadow_vmcs);
5543                         vmcs_load(vmx->loaded_vmcs->vmcs);
5544                         preempt_enable();
5545                 }
5546                 vmx->nested.dirty_vmcs12 = true;
5547         }
5548
5549         return nested_vmx_succeed(vcpu);
5550 }
5551
5552 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
5553 {
5554         vmx->nested.current_vmptr = vmptr;
5555         if (enable_shadow_vmcs) {
5556                 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_SHADOW_VMCS);
5557                 vmcs_write64(VMCS_LINK_POINTER,
5558                              __pa(vmx->vmcs01.shadow_vmcs));
5559                 vmx->nested.need_vmcs12_to_shadow_sync = true;
5560         }
5561         vmx->nested.dirty_vmcs12 = true;
5562         vmx->nested.force_msr_bitmap_recalc = true;
5563 }
5564
5565 /* Emulate the VMPTRLD instruction */
5566 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5567 {
5568         struct vcpu_vmx *vmx = to_vmx(vcpu);
5569         gpa_t vmptr;
5570         int r;
5571
5572         if (!nested_vmx_check_permission(vcpu))
5573                 return 1;
5574
5575         if (nested_vmx_get_vmptr(vcpu, &vmptr, &r))
5576                 return r;
5577
5578         if (!page_address_valid(vcpu, vmptr))
5579                 return nested_vmx_fail(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5580
5581         if (vmptr == vmx->nested.vmxon_ptr)
5582                 return nested_vmx_fail(vcpu, VMXERR_VMPTRLD_VMXON_POINTER);
5583
5584         /* Forbid normal VMPTRLD if Enlightened version was used */
5585         if (evmptr_is_valid(vmx->nested.hv_evmcs_vmptr))
5586                 return 1;
5587
5588         if (vmx->nested.current_vmptr != vmptr) {
5589                 struct gfn_to_hva_cache *ghc = &vmx->nested.vmcs12_cache;
5590                 struct vmcs_hdr hdr;
5591
5592                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, vmptr, VMCS12_SIZE)) {
5593                         /*
5594                          * Reads from an unbacked page return all 1s,
5595                          * which means that the 32 bits located at the
5596                          * given physical address won't match the required
5597                          * VMCS12_REVISION identifier.
5598                          */
5599                         return nested_vmx_fail(vcpu,
5600                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5601                 }
5602
5603                 if (kvm_read_guest_offset_cached(vcpu->kvm, ghc, &hdr,
5604                                                  offsetof(struct vmcs12, hdr),
5605                                                  sizeof(hdr))) {
5606                         return nested_vmx_fail(vcpu,
5607                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5608                 }
5609
5610                 if (hdr.revision_id != VMCS12_REVISION ||
5611                     (hdr.shadow_vmcs &&
5612                      !nested_cpu_has_vmx_shadow_vmcs(vcpu))) {
5613                         return nested_vmx_fail(vcpu,
5614                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5615                 }
5616
5617                 nested_release_vmcs12(vcpu);
5618
5619                 /*
5620                  * Load VMCS12 from guest memory since it is not already
5621                  * cached.
5622                  */
5623                 if (kvm_read_guest_cached(vcpu->kvm, ghc, vmx->nested.cached_vmcs12,
5624                                           VMCS12_SIZE)) {
5625                         return nested_vmx_fail(vcpu,
5626                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5627                 }
5628
5629                 set_current_vmptr(vmx, vmptr);
5630         }
5631
5632         return nested_vmx_succeed(vcpu);
5633 }
5634
5635 /* Emulate the VMPTRST instruction */
5636 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5637 {
5638         unsigned long exit_qual = vmx_get_exit_qual(vcpu);
5639         u32 instr_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5640         gpa_t current_vmptr = to_vmx(vcpu)->nested.current_vmptr;
5641         struct x86_exception e;
5642         gva_t gva;
5643         int r;
5644
5645         if (!nested_vmx_check_permission(vcpu))
5646                 return 1;
5647
5648         if (unlikely(evmptr_is_valid(to_vmx(vcpu)->nested.hv_evmcs_vmptr)))
5649                 return 1;
5650
5651         if (get_vmx_mem_address(vcpu, exit_qual, instr_info,
5652                                 true, sizeof(gpa_t), &gva))
5653                 return 1;
5654         /* *_system ok, nested_vmx_check_permission has verified cpl=0 */
5655         r = kvm_write_guest_virt_system(vcpu, gva, (void *)&current_vmptr,
5656                                         sizeof(gpa_t), &e);
5657         if (r != X86EMUL_CONTINUE)
5658                 return kvm_handle_memory_failure(vcpu, r, &e);
5659
5660         return nested_vmx_succeed(vcpu);
5661 }
5662
5663 /* Emulate the INVEPT instruction */
5664 static int handle_invept(struct kvm_vcpu *vcpu)
5665 {
5666         struct vcpu_vmx *vmx = to_vmx(vcpu);
5667         u32 vmx_instruction_info, types;
5668         unsigned long type, roots_to_free;
5669         struct kvm_mmu *mmu;
5670         gva_t gva;
5671         struct x86_exception e;
5672         struct {
5673                 u64 eptp, gpa;
5674         } operand;
5675         int i, r, gpr_index;
5676
5677         if (!(vmx->nested.msrs.secondary_ctls_high &
5678               SECONDARY_EXEC_ENABLE_EPT) ||
5679             !(vmx->nested.msrs.ept_caps & VMX_EPT_INVEPT_BIT)) {
5680                 kvm_queue_exception(vcpu, UD_VECTOR);
5681                 return 1;
5682         }
5683
5684         if (!nested_vmx_check_permission(vcpu))
5685                 return 1;
5686
5687         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5688         gpr_index = vmx_get_instr_info_reg2(vmx_instruction_info);
5689         type = kvm_register_read(vcpu, gpr_index);
5690
5691         types = (vmx->nested.msrs.ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
5692
5693         if (type >= 32 || !(types & (1 << type)))
5694                 return nested_vmx_fail(vcpu, VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
5695
5696         /* According to the Intel VMX instruction reference, the memory
5697          * operand is read even if it isn't needed (e.g., for type==global)
5698          */
5699         if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu),
5700                         vmx_instruction_info, false, sizeof(operand), &gva))
5701                 return 1;
5702         r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e);
5703         if (r != X86EMUL_CONTINUE)
5704                 return kvm_handle_memory_failure(vcpu, r, &e);
5705
5706         /*
5707          * Nested EPT roots are always held through guest_mmu,
5708          * not root_mmu.
5709          */
5710         mmu = &vcpu->arch.guest_mmu;
5711
5712         switch (type) {
5713         case VMX_EPT_EXTENT_CONTEXT:
5714                 if (!nested_vmx_check_eptp(vcpu, operand.eptp))
5715                         return nested_vmx_fail(vcpu,
5716                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
5717
5718                 roots_to_free = 0;
5719                 if (nested_ept_root_matches(mmu->root.hpa, mmu->root.pgd,
5720                                             operand.eptp))
5721                         roots_to_free |= KVM_MMU_ROOT_CURRENT;
5722
5723                 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
5724                         if (nested_ept_root_matches(mmu->prev_roots[i].hpa,
5725                                                     mmu->prev_roots[i].pgd,
5726                                                     operand.eptp))
5727                                 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
5728                 }
5729                 break;
5730         case VMX_EPT_EXTENT_GLOBAL:
5731                 roots_to_free = KVM_MMU_ROOTS_ALL;
5732                 break;
5733         default:
5734                 BUG();
5735                 break;
5736         }
5737
5738         if (roots_to_free)
5739                 kvm_mmu_free_roots(vcpu->kvm, mmu, roots_to_free);
5740
5741         return nested_vmx_succeed(vcpu);
5742 }
5743
5744 static int handle_invvpid(struct kvm_vcpu *vcpu)
5745 {
5746         struct vcpu_vmx *vmx = to_vmx(vcpu);
5747         u32 vmx_instruction_info;
5748         unsigned long type, types;
5749         gva_t gva;
5750         struct x86_exception e;
5751         struct {
5752                 u64 vpid;
5753                 u64 gla;
5754         } operand;
5755         u16 vpid02;
5756         int r, gpr_index;
5757
5758         if (!(vmx->nested.msrs.secondary_ctls_high &
5759               SECONDARY_EXEC_ENABLE_VPID) ||
5760                         !(vmx->nested.msrs.vpid_caps & VMX_VPID_INVVPID_BIT)) {
5761                 kvm_queue_exception(vcpu, UD_VECTOR);
5762                 return 1;
5763         }
5764
5765         if (!nested_vmx_check_permission(vcpu))
5766                 return 1;
5767
5768         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5769         gpr_index = vmx_get_instr_info_reg2(vmx_instruction_info);
5770         type = kvm_register_read(vcpu, gpr_index);
5771
5772         types = (vmx->nested.msrs.vpid_caps &
5773                         VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
5774
5775         if (type >= 32 || !(types & (1 << type)))
5776                 return nested_vmx_fail(vcpu,
5777                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
5778
5779         /* according to the intel vmx instruction reference, the memory
5780          * operand is read even if it isn't needed (e.g., for type==global)
5781          */
5782         if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu),
5783                         vmx_instruction_info, false, sizeof(operand), &gva))
5784                 return 1;
5785         r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e);
5786         if (r != X86EMUL_CONTINUE)
5787                 return kvm_handle_memory_failure(vcpu, r, &e);
5788
5789         if (operand.vpid >> 16)
5790                 return nested_vmx_fail(vcpu,
5791                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
5792
5793         vpid02 = nested_get_vpid02(vcpu);
5794         switch (type) {
5795         case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
5796                 if (!operand.vpid ||
5797                     is_noncanonical_address(operand.gla, vcpu))
5798                         return nested_vmx_fail(vcpu,
5799                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
5800                 vpid_sync_vcpu_addr(vpid02, operand.gla);
5801                 break;
5802         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
5803         case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
5804                 if (!operand.vpid)
5805                         return nested_vmx_fail(vcpu,
5806                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
5807                 vpid_sync_context(vpid02);
5808                 break;
5809         case VMX_VPID_EXTENT_ALL_CONTEXT:
5810                 vpid_sync_context(vpid02);
5811                 break;
5812         default:
5813                 WARN_ON_ONCE(1);
5814                 return kvm_skip_emulated_instruction(vcpu);
5815         }
5816
5817         /*
5818          * Sync the shadow page tables if EPT is disabled, L1 is invalidating
5819          * linear mappings for L2 (tagged with L2's VPID).  Free all guest
5820          * roots as VPIDs are not tracked in the MMU role.
5821          *
5822          * Note, this operates on root_mmu, not guest_mmu, as L1 and L2 share
5823          * an MMU when EPT is disabled.
5824          *
5825          * TODO: sync only the affected SPTEs for INVDIVIDUAL_ADDR.
5826          */
5827         if (!enable_ept)
5828                 kvm_mmu_free_guest_mode_roots(vcpu->kvm, &vcpu->arch.root_mmu);
5829
5830         return nested_vmx_succeed(vcpu);
5831 }
5832
5833 static int nested_vmx_eptp_switching(struct kvm_vcpu *vcpu,
5834                                      struct vmcs12 *vmcs12)
5835 {
5836         u32 index = kvm_rcx_read(vcpu);
5837         u64 new_eptp;
5838
5839         if (WARN_ON_ONCE(!nested_cpu_has_ept(vmcs12)))
5840                 return 1;
5841         if (index >= VMFUNC_EPTP_ENTRIES)
5842                 return 1;
5843
5844         if (kvm_vcpu_read_guest_page(vcpu, vmcs12->eptp_list_address >> PAGE_SHIFT,
5845                                      &new_eptp, index * 8, 8))
5846                 return 1;
5847
5848         /*
5849          * If the (L2) guest does a vmfunc to the currently
5850          * active ept pointer, we don't have to do anything else
5851          */
5852         if (vmcs12->ept_pointer != new_eptp) {
5853                 if (!nested_vmx_check_eptp(vcpu, new_eptp))
5854                         return 1;
5855
5856                 vmcs12->ept_pointer = new_eptp;
5857                 nested_ept_new_eptp(vcpu);
5858
5859                 if (!nested_cpu_has_vpid(vmcs12))
5860                         kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
5861         }
5862
5863         return 0;
5864 }
5865
5866 static int handle_vmfunc(struct kvm_vcpu *vcpu)
5867 {
5868         struct vcpu_vmx *vmx = to_vmx(vcpu);
5869         struct vmcs12 *vmcs12;
5870         u32 function = kvm_rax_read(vcpu);
5871
5872         /*
5873          * VMFUNC should never execute cleanly while L1 is active; KVM supports
5874          * VMFUNC for nested VMs, but not for L1.
5875          */
5876         if (WARN_ON_ONCE(!is_guest_mode(vcpu))) {
5877                 kvm_queue_exception(vcpu, UD_VECTOR);
5878                 return 1;
5879         }
5880
5881         vmcs12 = get_vmcs12(vcpu);
5882
5883         /*
5884          * #UD on out-of-bounds function has priority over VM-Exit, and VMFUNC
5885          * is enabled in vmcs02 if and only if it's enabled in vmcs12.
5886          */
5887         if (WARN_ON_ONCE((function > 63) || !nested_cpu_has_vmfunc(vmcs12))) {
5888                 kvm_queue_exception(vcpu, UD_VECTOR);
5889                 return 1;
5890         }
5891
5892         if (!(vmcs12->vm_function_control & BIT_ULL(function)))
5893                 goto fail;
5894
5895         switch (function) {
5896         case 0:
5897                 if (nested_vmx_eptp_switching(vcpu, vmcs12))
5898                         goto fail;
5899                 break;
5900         default:
5901                 goto fail;
5902         }
5903         return kvm_skip_emulated_instruction(vcpu);
5904
5905 fail:
5906         /*
5907          * This is effectively a reflected VM-Exit, as opposed to a synthesized
5908          * nested VM-Exit.  Pass the original exit reason, i.e. don't hardcode
5909          * EXIT_REASON_VMFUNC as the exit reason.
5910          */
5911         nested_vmx_vmexit(vcpu, vmx->exit_reason.full,
5912                           vmx_get_intr_info(vcpu),
5913                           vmx_get_exit_qual(vcpu));
5914         return 1;
5915 }
5916
5917 /*
5918  * Return true if an IO instruction with the specified port and size should cause
5919  * a VM-exit into L1.
5920  */
5921 bool nested_vmx_check_io_bitmaps(struct kvm_vcpu *vcpu, unsigned int port,
5922                                  int size)
5923 {
5924         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5925         gpa_t bitmap, last_bitmap;
5926         u8 b;
5927
5928         last_bitmap = INVALID_GPA;
5929         b = -1;
5930
5931         while (size > 0) {
5932                 if (port < 0x8000)
5933                         bitmap = vmcs12->io_bitmap_a;
5934                 else if (port < 0x10000)
5935                         bitmap = vmcs12->io_bitmap_b;
5936                 else
5937                         return true;
5938                 bitmap += (port & 0x7fff) / 8;
5939
5940                 if (last_bitmap != bitmap)
5941                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
5942                                 return true;
5943                 if (b & (1 << (port & 7)))
5944                         return true;
5945
5946                 port++;
5947                 size--;
5948                 last_bitmap = bitmap;
5949         }
5950
5951         return false;
5952 }
5953
5954 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
5955                                        struct vmcs12 *vmcs12)
5956 {
5957         unsigned long exit_qualification;
5958         unsigned short port;
5959         int size;
5960
5961         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
5962                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
5963
5964         exit_qualification = vmx_get_exit_qual(vcpu);
5965
5966         port = exit_qualification >> 16;
5967         size = (exit_qualification & 7) + 1;
5968
5969         return nested_vmx_check_io_bitmaps(vcpu, port, size);
5970 }
5971
5972 /*
5973  * Return 1 if we should exit from L2 to L1 to handle an MSR access,
5974  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5975  * disinterest in the current event (read or write a specific MSR) by using an
5976  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5977  */
5978 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5979                                         struct vmcs12 *vmcs12,
5980                                         union vmx_exit_reason exit_reason)
5981 {
5982         u32 msr_index = kvm_rcx_read(vcpu);
5983         gpa_t bitmap;
5984
5985         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
5986                 return true;
5987
5988         /*
5989          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5990          * for the four combinations of read/write and low/high MSR numbers.
5991          * First we need to figure out which of the four to use:
5992          */
5993         bitmap = vmcs12->msr_bitmap;
5994         if (exit_reason.basic == EXIT_REASON_MSR_WRITE)
5995                 bitmap += 2048;
5996         if (msr_index >= 0xc0000000) {
5997                 msr_index -= 0xc0000000;
5998                 bitmap += 1024;
5999         }
6000
6001         /* Then read the msr_index'th bit from this bitmap: */
6002         if (msr_index < 1024*8) {
6003                 unsigned char b;
6004                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
6005                         return true;
6006                 return 1 & (b >> (msr_index & 7));
6007         } else
6008                 return true; /* let L1 handle the wrong parameter */
6009 }
6010
6011 /*
6012  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6013  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6014  * intercept (via guest_host_mask etc.) the current event.
6015  */
6016 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6017         struct vmcs12 *vmcs12)
6018 {
6019         unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
6020         int cr = exit_qualification & 15;
6021         int reg;
6022         unsigned long val;
6023
6024         switch ((exit_qualification >> 4) & 3) {
6025         case 0: /* mov to cr */
6026                 reg = (exit_qualification >> 8) & 15;
6027                 val = kvm_register_read(vcpu, reg);
6028                 switch (cr) {
6029                 case 0:
6030                         if (vmcs12->cr0_guest_host_mask &
6031                             (val ^ vmcs12->cr0_read_shadow))
6032                                 return true;
6033                         break;
6034                 case 3:
6035                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6036                                 return true;
6037                         break;
6038                 case 4:
6039                         if (vmcs12->cr4_guest_host_mask &
6040                             (vmcs12->cr4_read_shadow ^ val))
6041                                 return true;
6042                         break;
6043                 case 8:
6044                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6045                                 return true;
6046                         break;
6047                 }
6048                 break;
6049         case 2: /* clts */
6050                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6051                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
6052                         return true;
6053                 break;
6054         case 1: /* mov from cr */
6055                 switch (cr) {
6056                 case 3:
6057                         if (vmcs12->cpu_based_vm_exec_control &
6058                             CPU_BASED_CR3_STORE_EXITING)
6059                                 return true;
6060                         break;
6061                 case 8:
6062                         if (vmcs12->cpu_based_vm_exec_control &
6063                             CPU_BASED_CR8_STORE_EXITING)
6064                                 return true;
6065                         break;
6066                 }
6067                 break;
6068         case 3: /* lmsw */
6069                 /*
6070                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6071                  * cr0. Other attempted changes are ignored, with no exit.
6072                  */
6073                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
6074                 if (vmcs12->cr0_guest_host_mask & 0xe &
6075                     (val ^ vmcs12->cr0_read_shadow))
6076                         return true;
6077                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6078                     !(vmcs12->cr0_read_shadow & 0x1) &&
6079                     (val & 0x1))
6080                         return true;
6081                 break;
6082         }
6083         return false;
6084 }
6085
6086 static bool nested_vmx_exit_handled_encls(struct kvm_vcpu *vcpu,
6087                                           struct vmcs12 *vmcs12)
6088 {
6089         u32 encls_leaf;
6090
6091         if (!guest_cpuid_has(vcpu, X86_FEATURE_SGX) ||
6092             !nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENCLS_EXITING))
6093                 return false;
6094
6095         encls_leaf = kvm_rax_read(vcpu);
6096         if (encls_leaf > 62)
6097                 encls_leaf = 63;
6098         return vmcs12->encls_exiting_bitmap & BIT_ULL(encls_leaf);
6099 }
6100
6101 static bool nested_vmx_exit_handled_vmcs_access(struct kvm_vcpu *vcpu,
6102         struct vmcs12 *vmcs12, gpa_t bitmap)
6103 {
6104         u32 vmx_instruction_info;
6105         unsigned long field;
6106         u8 b;
6107
6108         if (!nested_cpu_has_shadow_vmcs(vmcs12))
6109                 return true;
6110
6111         /* Decode instruction info and find the field to access */
6112         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6113         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6114
6115         /* Out-of-range fields always cause a VM exit from L2 to L1 */
6116         if (field >> 15)
6117                 return true;
6118
6119         if (kvm_vcpu_read_guest(vcpu, bitmap + field/8, &b, 1))
6120                 return true;
6121
6122         return 1 & (b >> (field & 7));
6123 }
6124
6125 static bool nested_vmx_exit_handled_mtf(struct vmcs12 *vmcs12)
6126 {
6127         u32 entry_intr_info = vmcs12->vm_entry_intr_info_field;
6128
6129         if (nested_cpu_has_mtf(vmcs12))
6130                 return true;
6131
6132         /*
6133          * An MTF VM-exit may be injected into the guest by setting the
6134          * interruption-type to 7 (other event) and the vector field to 0. Such
6135          * is the case regardless of the 'monitor trap flag' VM-execution
6136          * control.
6137          */
6138         return entry_intr_info == (INTR_INFO_VALID_MASK
6139                                    | INTR_TYPE_OTHER_EVENT);
6140 }
6141
6142 /*
6143  * Return true if L0 wants to handle an exit from L2 regardless of whether or not
6144  * L1 wants the exit.  Only call this when in is_guest_mode (L2).
6145  */
6146 static bool nested_vmx_l0_wants_exit(struct kvm_vcpu *vcpu,
6147                                      union vmx_exit_reason exit_reason)
6148 {
6149         u32 intr_info;
6150
6151         switch ((u16)exit_reason.basic) {
6152         case EXIT_REASON_EXCEPTION_NMI:
6153                 intr_info = vmx_get_intr_info(vcpu);
6154                 if (is_nmi(intr_info))
6155                         return true;
6156                 else if (is_page_fault(intr_info))
6157                         return vcpu->arch.apf.host_apf_flags ||
6158                                vmx_need_pf_intercept(vcpu);
6159                 else if (is_debug(intr_info) &&
6160                          vcpu->guest_debug &
6161                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
6162                         return true;
6163                 else if (is_breakpoint(intr_info) &&
6164                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
6165                         return true;
6166                 else if (is_alignment_check(intr_info) &&
6167                          !vmx_guest_inject_ac(vcpu))
6168                         return true;
6169                 return false;
6170         case EXIT_REASON_EXTERNAL_INTERRUPT:
6171                 return true;
6172         case EXIT_REASON_MCE_DURING_VMENTRY:
6173                 return true;
6174         case EXIT_REASON_EPT_VIOLATION:
6175                 /*
6176                  * L0 always deals with the EPT violation. If nested EPT is
6177                  * used, and the nested mmu code discovers that the address is
6178                  * missing in the guest EPT table (EPT12), the EPT violation
6179                  * will be injected with nested_ept_inject_page_fault()
6180                  */
6181                 return true;
6182         case EXIT_REASON_EPT_MISCONFIG:
6183                 /*
6184                  * L2 never uses directly L1's EPT, but rather L0's own EPT
6185                  * table (shadow on EPT) or a merged EPT table that L0 built
6186                  * (EPT on EPT). So any problems with the structure of the
6187                  * table is L0's fault.
6188                  */
6189                 return true;
6190         case EXIT_REASON_PREEMPTION_TIMER:
6191                 return true;
6192         case EXIT_REASON_PML_FULL:
6193                 /*
6194                  * PML is emulated for an L1 VMM and should never be enabled in
6195                  * vmcs02, always "handle" PML_FULL by exiting to userspace.
6196                  */
6197                 return true;
6198         case EXIT_REASON_VMFUNC:
6199                 /* VM functions are emulated through L2->L0 vmexits. */
6200                 return true;
6201         case EXIT_REASON_BUS_LOCK:
6202                 /*
6203                  * At present, bus lock VM exit is never exposed to L1.
6204                  * Handle L2's bus locks in L0 directly.
6205                  */
6206                 return true;
6207         case EXIT_REASON_VMCALL:
6208                 /* Hyper-V L2 TLB flush hypercall is handled by L0 */
6209                 return guest_hv_cpuid_has_l2_tlb_flush(vcpu) &&
6210                         nested_evmcs_l2_tlb_flush_enabled(vcpu) &&
6211                         kvm_hv_is_tlb_flush_hcall(vcpu);
6212         default:
6213                 break;
6214         }
6215         return false;
6216 }
6217
6218 /*
6219  * Return 1 if L1 wants to intercept an exit from L2.  Only call this when in
6220  * is_guest_mode (L2).
6221  */
6222 static bool nested_vmx_l1_wants_exit(struct kvm_vcpu *vcpu,
6223                                      union vmx_exit_reason exit_reason)
6224 {
6225         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6226         u32 intr_info;
6227
6228         switch ((u16)exit_reason.basic) {
6229         case EXIT_REASON_EXCEPTION_NMI:
6230                 intr_info = vmx_get_intr_info(vcpu);
6231                 if (is_nmi(intr_info))
6232                         return true;
6233                 else if (is_page_fault(intr_info))
6234                         return true;
6235                 return vmcs12->exception_bitmap &
6236                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6237         case EXIT_REASON_EXTERNAL_INTERRUPT:
6238                 return nested_exit_on_intr(vcpu);
6239         case EXIT_REASON_TRIPLE_FAULT:
6240                 return true;
6241         case EXIT_REASON_INTERRUPT_WINDOW:
6242                 return nested_cpu_has(vmcs12, CPU_BASED_INTR_WINDOW_EXITING);
6243         case EXIT_REASON_NMI_WINDOW:
6244                 return nested_cpu_has(vmcs12, CPU_BASED_NMI_WINDOW_EXITING);
6245         case EXIT_REASON_TASK_SWITCH:
6246                 return true;
6247         case EXIT_REASON_CPUID:
6248                 return true;
6249         case EXIT_REASON_HLT:
6250                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6251         case EXIT_REASON_INVD:
6252                 return true;
6253         case EXIT_REASON_INVLPG:
6254                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6255         case EXIT_REASON_RDPMC:
6256                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6257         case EXIT_REASON_RDRAND:
6258                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND_EXITING);
6259         case EXIT_REASON_RDSEED:
6260                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED_EXITING);
6261         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
6262                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6263         case EXIT_REASON_VMREAD:
6264                 return nested_vmx_exit_handled_vmcs_access(vcpu, vmcs12,
6265                         vmcs12->vmread_bitmap);
6266         case EXIT_REASON_VMWRITE:
6267                 return nested_vmx_exit_handled_vmcs_access(vcpu, vmcs12,
6268                         vmcs12->vmwrite_bitmap);
6269         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6270         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6271         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMRESUME:
6272         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6273         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
6274                 /*
6275                  * VMX instructions trap unconditionally. This allows L1 to
6276                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
6277                  */
6278                 return true;
6279         case EXIT_REASON_CR_ACCESS:
6280                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6281         case EXIT_REASON_DR_ACCESS:
6282                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6283         case EXIT_REASON_IO_INSTRUCTION:
6284                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
6285         case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
6286                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
6287         case EXIT_REASON_MSR_READ:
6288         case EXIT_REASON_MSR_WRITE:
6289                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6290         case EXIT_REASON_INVALID_STATE:
6291                 return true;
6292         case EXIT_REASON_MWAIT_INSTRUCTION:
6293                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6294         case EXIT_REASON_MONITOR_TRAP_FLAG:
6295                 return nested_vmx_exit_handled_mtf(vmcs12);
6296         case EXIT_REASON_MONITOR_INSTRUCTION:
6297                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6298         case EXIT_REASON_PAUSE_INSTRUCTION:
6299                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6300                         nested_cpu_has2(vmcs12,
6301                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6302         case EXIT_REASON_MCE_DURING_VMENTRY:
6303                 return true;
6304         case EXIT_REASON_TPR_BELOW_THRESHOLD:
6305                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
6306         case EXIT_REASON_APIC_ACCESS:
6307         case EXIT_REASON_APIC_WRITE:
6308         case EXIT_REASON_EOI_INDUCED:
6309                 /*
6310                  * The controls for "virtualize APIC accesses," "APIC-
6311                  * register virtualization," and "virtual-interrupt
6312                  * delivery" only come from vmcs12.
6313                  */
6314                 return true;
6315         case EXIT_REASON_INVPCID:
6316                 return
6317                         nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_INVPCID) &&
6318                         nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6319         case EXIT_REASON_WBINVD:
6320                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6321         case EXIT_REASON_XSETBV:
6322                 return true;
6323         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
6324                 /*
6325                  * This should never happen, since it is not possible to
6326                  * set XSS to a non-zero value---neither in L1 nor in L2.
6327                  * If if it were, XSS would have to be checked against
6328                  * the XSS exit bitmap in vmcs12.
6329                  */
6330                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
6331         case EXIT_REASON_UMWAIT:
6332         case EXIT_REASON_TPAUSE:
6333                 return nested_cpu_has2(vmcs12,
6334                         SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE);
6335         case EXIT_REASON_ENCLS:
6336                 return nested_vmx_exit_handled_encls(vcpu, vmcs12);
6337         case EXIT_REASON_NOTIFY:
6338                 /* Notify VM exit is not exposed to L1 */
6339                 return false;
6340         default:
6341                 return true;
6342         }
6343 }
6344
6345 /*
6346  * Conditionally reflect a VM-Exit into L1.  Returns %true if the VM-Exit was
6347  * reflected into L1.
6348  */
6349 bool nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu)
6350 {
6351         struct vcpu_vmx *vmx = to_vmx(vcpu);
6352         union vmx_exit_reason exit_reason = vmx->exit_reason;
6353         unsigned long exit_qual;
6354         u32 exit_intr_info;
6355
6356         WARN_ON_ONCE(vmx->nested.nested_run_pending);
6357
6358         /*
6359          * Late nested VM-Fail shares the same flow as nested VM-Exit since KVM
6360          * has already loaded L2's state.
6361          */
6362         if (unlikely(vmx->fail)) {
6363                 trace_kvm_nested_vmenter_failed(
6364                         "hardware VM-instruction error: ",
6365                         vmcs_read32(VM_INSTRUCTION_ERROR));
6366                 exit_intr_info = 0;
6367                 exit_qual = 0;
6368                 goto reflect_vmexit;
6369         }
6370
6371         trace_kvm_nested_vmexit(vcpu, KVM_ISA_VMX);
6372
6373         /* If L0 (KVM) wants the exit, it trumps L1's desires. */
6374         if (nested_vmx_l0_wants_exit(vcpu, exit_reason))
6375                 return false;
6376
6377         /* If L1 doesn't want the exit, handle it in L0. */
6378         if (!nested_vmx_l1_wants_exit(vcpu, exit_reason))
6379                 return false;
6380
6381         /*
6382          * vmcs.VM_EXIT_INTR_INFO is only valid for EXCEPTION_NMI exits.  For
6383          * EXTERNAL_INTERRUPT, the value for vmcs12->vm_exit_intr_info would
6384          * need to be synthesized by querying the in-kernel LAPIC, but external
6385          * interrupts are never reflected to L1 so it's a non-issue.
6386          */
6387         exit_intr_info = vmx_get_intr_info(vcpu);
6388         if (is_exception_with_error_code(exit_intr_info)) {
6389                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6390
6391                 vmcs12->vm_exit_intr_error_code =
6392                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6393         }
6394         exit_qual = vmx_get_exit_qual(vcpu);
6395
6396 reflect_vmexit:
6397         nested_vmx_vmexit(vcpu, exit_reason.full, exit_intr_info, exit_qual);
6398         return true;
6399 }
6400
6401 static int vmx_get_nested_state(struct kvm_vcpu *vcpu,
6402                                 struct kvm_nested_state __user *user_kvm_nested_state,
6403                                 u32 user_data_size)
6404 {
6405         struct vcpu_vmx *vmx;
6406         struct vmcs12 *vmcs12;
6407         struct kvm_nested_state kvm_state = {
6408                 .flags = 0,
6409                 .format = KVM_STATE_NESTED_FORMAT_VMX,
6410                 .size = sizeof(kvm_state),
6411                 .hdr.vmx.flags = 0,
6412                 .hdr.vmx.vmxon_pa = INVALID_GPA,
6413                 .hdr.vmx.vmcs12_pa = INVALID_GPA,
6414                 .hdr.vmx.preemption_timer_deadline = 0,
6415         };
6416         struct kvm_vmx_nested_state_data __user *user_vmx_nested_state =
6417                 &user_kvm_nested_state->data.vmx[0];
6418
6419         if (!vcpu)
6420                 return kvm_state.size + sizeof(*user_vmx_nested_state);
6421
6422         vmx = to_vmx(vcpu);
6423         vmcs12 = get_vmcs12(vcpu);
6424
6425         if (nested_vmx_allowed(vcpu) &&
6426             (vmx->nested.vmxon || vmx->nested.smm.vmxon)) {
6427                 kvm_state.hdr.vmx.vmxon_pa = vmx->nested.vmxon_ptr;
6428                 kvm_state.hdr.vmx.vmcs12_pa = vmx->nested.current_vmptr;
6429
6430                 if (vmx_has_valid_vmcs12(vcpu)) {
6431                         kvm_state.size += sizeof(user_vmx_nested_state->vmcs12);
6432
6433                         /* 'hv_evmcs_vmptr' can also be EVMPTR_MAP_PENDING here */
6434                         if (vmx->nested.hv_evmcs_vmptr != EVMPTR_INVALID)
6435                                 kvm_state.flags |= KVM_STATE_NESTED_EVMCS;
6436
6437                         if (is_guest_mode(vcpu) &&
6438                             nested_cpu_has_shadow_vmcs(vmcs12) &&
6439                             vmcs12->vmcs_link_pointer != INVALID_GPA)
6440                                 kvm_state.size += sizeof(user_vmx_nested_state->shadow_vmcs12);
6441                 }
6442
6443                 if (vmx->nested.smm.vmxon)
6444                         kvm_state.hdr.vmx.smm.flags |= KVM_STATE_NESTED_SMM_VMXON;
6445
6446                 if (vmx->nested.smm.guest_mode)
6447                         kvm_state.hdr.vmx.smm.flags |= KVM_STATE_NESTED_SMM_GUEST_MODE;
6448
6449                 if (is_guest_mode(vcpu)) {
6450                         kvm_state.flags |= KVM_STATE_NESTED_GUEST_MODE;
6451
6452                         if (vmx->nested.nested_run_pending)
6453                                 kvm_state.flags |= KVM_STATE_NESTED_RUN_PENDING;
6454
6455                         if (vmx->nested.mtf_pending)
6456                                 kvm_state.flags |= KVM_STATE_NESTED_MTF_PENDING;
6457
6458                         if (nested_cpu_has_preemption_timer(vmcs12) &&
6459                             vmx->nested.has_preemption_timer_deadline) {
6460                                 kvm_state.hdr.vmx.flags |=
6461                                         KVM_STATE_VMX_PREEMPTION_TIMER_DEADLINE;
6462                                 kvm_state.hdr.vmx.preemption_timer_deadline =
6463                                         vmx->nested.preemption_timer_deadline;
6464                         }
6465                 }
6466         }
6467
6468         if (user_data_size < kvm_state.size)
6469                 goto out;
6470
6471         if (copy_to_user(user_kvm_nested_state, &kvm_state, sizeof(kvm_state)))
6472                 return -EFAULT;
6473
6474         if (!vmx_has_valid_vmcs12(vcpu))
6475                 goto out;
6476
6477         /*
6478          * When running L2, the authoritative vmcs12 state is in the
6479          * vmcs02. When running L1, the authoritative vmcs12 state is
6480          * in the shadow or enlightened vmcs linked to vmcs01, unless
6481          * need_vmcs12_to_shadow_sync is set, in which case, the authoritative
6482          * vmcs12 state is in the vmcs12 already.
6483          */
6484         if (is_guest_mode(vcpu)) {
6485                 sync_vmcs02_to_vmcs12(vcpu, vmcs12);
6486                 sync_vmcs02_to_vmcs12_rare(vcpu, vmcs12);
6487         } else  {
6488                 copy_vmcs02_to_vmcs12_rare(vcpu, get_vmcs12(vcpu));
6489                 if (!vmx->nested.need_vmcs12_to_shadow_sync) {
6490                         if (evmptr_is_valid(vmx->nested.hv_evmcs_vmptr))
6491                                 /*
6492                                  * L1 hypervisor is not obliged to keep eVMCS
6493                                  * clean fields data always up-to-date while
6494                                  * not in guest mode, 'hv_clean_fields' is only
6495                                  * supposed to be actual upon vmentry so we need
6496                                  * to ignore it here and do full copy.
6497                                  */
6498                                 copy_enlightened_to_vmcs12(vmx, 0);
6499                         else if (enable_shadow_vmcs)
6500                                 copy_shadow_to_vmcs12(vmx);
6501                 }
6502         }
6503
6504         BUILD_BUG_ON(sizeof(user_vmx_nested_state->vmcs12) < VMCS12_SIZE);
6505         BUILD_BUG_ON(sizeof(user_vmx_nested_state->shadow_vmcs12) < VMCS12_SIZE);
6506
6507         /*
6508          * Copy over the full allocated size of vmcs12 rather than just the size
6509          * of the struct.
6510          */
6511         if (copy_to_user(user_vmx_nested_state->vmcs12, vmcs12, VMCS12_SIZE))
6512                 return -EFAULT;
6513
6514         if (nested_cpu_has_shadow_vmcs(vmcs12) &&
6515             vmcs12->vmcs_link_pointer != INVALID_GPA) {
6516                 if (copy_to_user(user_vmx_nested_state->shadow_vmcs12,
6517                                  get_shadow_vmcs12(vcpu), VMCS12_SIZE))
6518                         return -EFAULT;
6519         }
6520 out:
6521         return kvm_state.size;
6522 }
6523
6524 void vmx_leave_nested(struct kvm_vcpu *vcpu)
6525 {
6526         if (is_guest_mode(vcpu)) {
6527                 to_vmx(vcpu)->nested.nested_run_pending = 0;
6528                 nested_vmx_vmexit(vcpu, -1, 0, 0);
6529         }
6530         free_nested(vcpu);
6531 }
6532
6533 static int vmx_set_nested_state(struct kvm_vcpu *vcpu,
6534                                 struct kvm_nested_state __user *user_kvm_nested_state,
6535                                 struct kvm_nested_state *kvm_state)
6536 {
6537         struct vcpu_vmx *vmx = to_vmx(vcpu);
6538         struct vmcs12 *vmcs12;
6539         enum vm_entry_failure_code ignored;
6540         struct kvm_vmx_nested_state_data __user *user_vmx_nested_state =
6541                 &user_kvm_nested_state->data.vmx[0];
6542         int ret;
6543
6544         if (kvm_state->format != KVM_STATE_NESTED_FORMAT_VMX)
6545                 return -EINVAL;
6546
6547         if (kvm_state->hdr.vmx.vmxon_pa == INVALID_GPA) {
6548                 if (kvm_state->hdr.vmx.smm.flags)
6549                         return -EINVAL;
6550
6551                 if (kvm_state->hdr.vmx.vmcs12_pa != INVALID_GPA)
6552                         return -EINVAL;
6553
6554                 /*
6555                  * KVM_STATE_NESTED_EVMCS used to signal that KVM should
6556                  * enable eVMCS capability on vCPU. However, since then
6557                  * code was changed such that flag signals vmcs12 should
6558                  * be copied into eVMCS in guest memory.
6559                  *
6560                  * To preserve backwards compatability, allow user
6561                  * to set this flag even when there is no VMXON region.
6562                  */
6563                 if (kvm_state->flags & ~KVM_STATE_NESTED_EVMCS)
6564                         return -EINVAL;
6565         } else {
6566                 if (!nested_vmx_allowed(vcpu))
6567                         return -EINVAL;
6568
6569                 if (!page_address_valid(vcpu, kvm_state->hdr.vmx.vmxon_pa))
6570                         return -EINVAL;
6571         }
6572
6573         if ((kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_GUEST_MODE) &&
6574             (kvm_state->flags & KVM_STATE_NESTED_GUEST_MODE))
6575                 return -EINVAL;
6576
6577         if (kvm_state->hdr.vmx.smm.flags &
6578             ~(KVM_STATE_NESTED_SMM_GUEST_MODE | KVM_STATE_NESTED_SMM_VMXON))
6579                 return -EINVAL;
6580
6581         if (kvm_state->hdr.vmx.flags & ~KVM_STATE_VMX_PREEMPTION_TIMER_DEADLINE)
6582                 return -EINVAL;
6583
6584         /*
6585          * SMM temporarily disables VMX, so we cannot be in guest mode,
6586          * nor can VMLAUNCH/VMRESUME be pending.  Outside SMM, SMM flags
6587          * must be zero.
6588          */
6589         if (is_smm(vcpu) ?
6590                 (kvm_state->flags &
6591                  (KVM_STATE_NESTED_GUEST_MODE | KVM_STATE_NESTED_RUN_PENDING))
6592                 : kvm_state->hdr.vmx.smm.flags)
6593                 return -EINVAL;
6594
6595         if ((kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_GUEST_MODE) &&
6596             !(kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_VMXON))
6597                 return -EINVAL;
6598
6599         if ((kvm_state->flags & KVM_STATE_NESTED_EVMCS) &&
6600                 (!nested_vmx_allowed(vcpu) || !vmx->nested.enlightened_vmcs_enabled))
6601                         return -EINVAL;
6602
6603         vmx_leave_nested(vcpu);
6604
6605         if (kvm_state->hdr.vmx.vmxon_pa == INVALID_GPA)
6606                 return 0;
6607
6608         vmx->nested.vmxon_ptr = kvm_state->hdr.vmx.vmxon_pa;
6609         ret = enter_vmx_operation(vcpu);
6610         if (ret)
6611                 return ret;
6612
6613         /* Empty 'VMXON' state is permitted if no VMCS loaded */
6614         if (kvm_state->size < sizeof(*kvm_state) + sizeof(*vmcs12)) {
6615                 /* See vmx_has_valid_vmcs12.  */
6616                 if ((kvm_state->flags & KVM_STATE_NESTED_GUEST_MODE) ||
6617                     (kvm_state->flags & KVM_STATE_NESTED_EVMCS) ||
6618                     (kvm_state->hdr.vmx.vmcs12_pa != INVALID_GPA))
6619                         return -EINVAL;
6620                 else
6621                         return 0;
6622         }
6623
6624         if (kvm_state->hdr.vmx.vmcs12_pa != INVALID_GPA) {
6625                 if (kvm_state->hdr.vmx.vmcs12_pa == kvm_state->hdr.vmx.vmxon_pa ||
6626                     !page_address_valid(vcpu, kvm_state->hdr.vmx.vmcs12_pa))
6627                         return -EINVAL;
6628
6629                 set_current_vmptr(vmx, kvm_state->hdr.vmx.vmcs12_pa);
6630         } else if (kvm_state->flags & KVM_STATE_NESTED_EVMCS) {
6631                 /*
6632                  * nested_vmx_handle_enlightened_vmptrld() cannot be called
6633                  * directly from here as HV_X64_MSR_VP_ASSIST_PAGE may not be
6634                  * restored yet. EVMCS will be mapped from
6635                  * nested_get_vmcs12_pages().
6636                  */
6637                 vmx->nested.hv_evmcs_vmptr = EVMPTR_MAP_PENDING;
6638                 kvm_make_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu);
6639         } else {
6640                 return -EINVAL;
6641         }
6642
6643         if (kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_VMXON) {
6644                 vmx->nested.smm.vmxon = true;
6645                 vmx->nested.vmxon = false;
6646
6647                 if (kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_GUEST_MODE)
6648                         vmx->nested.smm.guest_mode = true;
6649         }
6650
6651         vmcs12 = get_vmcs12(vcpu);
6652         if (copy_from_user(vmcs12, user_vmx_nested_state->vmcs12, sizeof(*vmcs12)))
6653                 return -EFAULT;
6654
6655         if (vmcs12->hdr.revision_id != VMCS12_REVISION)
6656                 return -EINVAL;
6657
6658         if (!(kvm_state->flags & KVM_STATE_NESTED_GUEST_MODE))
6659                 return 0;
6660
6661         vmx->nested.nested_run_pending =
6662                 !!(kvm_state->flags & KVM_STATE_NESTED_RUN_PENDING);
6663
6664         vmx->nested.mtf_pending =
6665                 !!(kvm_state->flags & KVM_STATE_NESTED_MTF_PENDING);
6666
6667         ret = -EINVAL;
6668         if (nested_cpu_has_shadow_vmcs(vmcs12) &&
6669             vmcs12->vmcs_link_pointer != INVALID_GPA) {
6670                 struct vmcs12 *shadow_vmcs12 = get_shadow_vmcs12(vcpu);
6671
6672                 if (kvm_state->size <
6673                     sizeof(*kvm_state) +
6674                     sizeof(user_vmx_nested_state->vmcs12) + sizeof(*shadow_vmcs12))
6675                         goto error_guest_mode;
6676
6677                 if (copy_from_user(shadow_vmcs12,
6678                                    user_vmx_nested_state->shadow_vmcs12,
6679                                    sizeof(*shadow_vmcs12))) {
6680                         ret = -EFAULT;
6681                         goto error_guest_mode;
6682                 }
6683
6684                 if (shadow_vmcs12->hdr.revision_id != VMCS12_REVISION ||
6685                     !shadow_vmcs12->hdr.shadow_vmcs)
6686                         goto error_guest_mode;
6687         }
6688
6689         vmx->nested.has_preemption_timer_deadline = false;
6690         if (kvm_state->hdr.vmx.flags & KVM_STATE_VMX_PREEMPTION_TIMER_DEADLINE) {
6691                 vmx->nested.has_preemption_timer_deadline = true;
6692                 vmx->nested.preemption_timer_deadline =
6693                         kvm_state->hdr.vmx.preemption_timer_deadline;
6694         }
6695
6696         if (nested_vmx_check_controls(vcpu, vmcs12) ||
6697             nested_vmx_check_host_state(vcpu, vmcs12) ||
6698             nested_vmx_check_guest_state(vcpu, vmcs12, &ignored))
6699                 goto error_guest_mode;
6700
6701         vmx->nested.dirty_vmcs12 = true;
6702         vmx->nested.force_msr_bitmap_recalc = true;
6703         ret = nested_vmx_enter_non_root_mode(vcpu, false);
6704         if (ret)
6705                 goto error_guest_mode;
6706
6707         if (vmx->nested.mtf_pending)
6708                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6709
6710         return 0;
6711
6712 error_guest_mode:
6713         vmx->nested.nested_run_pending = 0;
6714         return ret;
6715 }
6716
6717 void nested_vmx_set_vmcs_shadowing_bitmap(void)
6718 {
6719         if (enable_shadow_vmcs) {
6720                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
6721                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
6722         }
6723 }
6724
6725 /*
6726  * Indexing into the vmcs12 uses the VMCS encoding rotated left by 6.  Undo
6727  * that madness to get the encoding for comparison.
6728  */
6729 #define VMCS12_IDX_TO_ENC(idx) ((u16)(((u16)(idx) >> 6) | ((u16)(idx) << 10)))
6730
6731 static u64 nested_vmx_calc_vmcs_enum_msr(void)
6732 {
6733         /*
6734          * Note these are the so called "index" of the VMCS field encoding, not
6735          * the index into vmcs12.
6736          */
6737         unsigned int max_idx, idx;
6738         int i;
6739
6740         /*
6741          * For better or worse, KVM allows VMREAD/VMWRITE to all fields in
6742          * vmcs12, regardless of whether or not the associated feature is
6743          * exposed to L1.  Simply find the field with the highest index.
6744          */
6745         max_idx = 0;
6746         for (i = 0; i < nr_vmcs12_fields; i++) {
6747                 /* The vmcs12 table is very, very sparsely populated. */
6748                 if (!vmcs12_field_offsets[i])
6749                         continue;
6750
6751                 idx = vmcs_field_index(VMCS12_IDX_TO_ENC(i));
6752                 if (idx > max_idx)
6753                         max_idx = idx;
6754         }
6755
6756         return (u64)max_idx << VMCS_FIELD_INDEX_SHIFT;
6757 }
6758
6759 /*
6760  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
6761  * returned for the various VMX controls MSRs when nested VMX is enabled.
6762  * The same values should also be used to verify that vmcs12 control fields are
6763  * valid during nested entry from L1 to L2.
6764  * Each of these control msrs has a low and high 32-bit half: A low bit is on
6765  * if the corresponding bit in the (32-bit) control field *must* be on, and a
6766  * bit in the high half is on if the corresponding bit in the control field
6767  * may be on. See also vmx_control_verify().
6768  */
6769 void nested_vmx_setup_ctls_msrs(struct vmcs_config *vmcs_conf, u32 ept_caps)
6770 {
6771         struct nested_vmx_msrs *msrs = &vmcs_conf->nested;
6772
6773         /*
6774          * Note that as a general rule, the high half of the MSRs (bits in
6775          * the control fields which may be 1) should be initialized by the
6776          * intersection of the underlying hardware's MSR (i.e., features which
6777          * can be supported) and the list of features we want to expose -
6778          * because they are known to be properly supported in our code.
6779          * Also, usually, the low half of the MSRs (bits which must be 1) can
6780          * be set to 0, meaning that L1 may turn off any of these bits. The
6781          * reason is that if one of these bits is necessary, it will appear
6782          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
6783          * fields of vmcs01 and vmcs02, will turn these bits off - and
6784          * nested_vmx_l1_wants_exit() will not pass related exits to L1.
6785          * These rules have exceptions below.
6786          */
6787
6788         /* pin-based controls */
6789         msrs->pinbased_ctls_low =
6790                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
6791
6792         msrs->pinbased_ctls_high = vmcs_conf->pin_based_exec_ctrl;
6793         msrs->pinbased_ctls_high &=
6794                 PIN_BASED_EXT_INTR_MASK |
6795                 PIN_BASED_NMI_EXITING |
6796                 PIN_BASED_VIRTUAL_NMIS |
6797                 (enable_apicv ? PIN_BASED_POSTED_INTR : 0);
6798         msrs->pinbased_ctls_high |=
6799                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
6800                 PIN_BASED_VMX_PREEMPTION_TIMER;
6801
6802         /* exit controls */
6803         msrs->exit_ctls_low =
6804                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
6805
6806         msrs->exit_ctls_high = vmcs_conf->vmexit_ctrl;
6807         msrs->exit_ctls_high &=
6808 #ifdef CONFIG_X86_64
6809                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
6810 #endif
6811                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT |
6812                 VM_EXIT_CLEAR_BNDCFGS;
6813         msrs->exit_ctls_high |=
6814                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
6815                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
6816                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT |
6817                 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
6818
6819         /* We support free control of debug control saving. */
6820         msrs->exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
6821
6822         /* entry controls */
6823         msrs->entry_ctls_low =
6824                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
6825
6826         msrs->entry_ctls_high = vmcs_conf->vmentry_ctrl;
6827         msrs->entry_ctls_high &=
6828 #ifdef CONFIG_X86_64
6829                 VM_ENTRY_IA32E_MODE |
6830 #endif
6831                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
6832         msrs->entry_ctls_high |=
6833                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER |
6834                  VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL);
6835
6836         /* We support free control of debug control loading. */
6837         msrs->entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
6838
6839         /* cpu-based controls */
6840         msrs->procbased_ctls_low =
6841                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
6842
6843         msrs->procbased_ctls_high = vmcs_conf->cpu_based_exec_ctrl;
6844         msrs->procbased_ctls_high &=
6845                 CPU_BASED_INTR_WINDOW_EXITING |
6846                 CPU_BASED_NMI_WINDOW_EXITING | CPU_BASED_USE_TSC_OFFSETTING |
6847                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
6848                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
6849                 CPU_BASED_CR3_STORE_EXITING |
6850 #ifdef CONFIG_X86_64
6851                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
6852 #endif
6853                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
6854                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
6855                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
6856                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
6857                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
6858         /*
6859          * We can allow some features even when not supported by the
6860          * hardware. For example, L1 can specify an MSR bitmap - and we
6861          * can use it to avoid exits to L1 - even when L0 runs L2
6862          * without MSR bitmaps.
6863          */
6864         msrs->procbased_ctls_high |=
6865                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
6866                 CPU_BASED_USE_MSR_BITMAPS;
6867
6868         /* We support free control of CR3 access interception. */
6869         msrs->procbased_ctls_low &=
6870                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
6871
6872         /*
6873          * secondary cpu-based controls.  Do not include those that
6874          * depend on CPUID bits, they are added later by
6875          * vmx_vcpu_after_set_cpuid.
6876          */
6877         msrs->secondary_ctls_low = 0;
6878
6879         msrs->secondary_ctls_high = vmcs_conf->cpu_based_2nd_exec_ctrl;
6880         msrs->secondary_ctls_high &=
6881                 SECONDARY_EXEC_DESC |
6882                 SECONDARY_EXEC_ENABLE_RDTSCP |
6883                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
6884                 SECONDARY_EXEC_WBINVD_EXITING |
6885                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
6886                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
6887                 SECONDARY_EXEC_RDRAND_EXITING |
6888                 SECONDARY_EXEC_ENABLE_INVPCID |
6889                 SECONDARY_EXEC_ENABLE_VMFUNC |
6890                 SECONDARY_EXEC_RDSEED_EXITING |
6891                 SECONDARY_EXEC_XSAVES |
6892                 SECONDARY_EXEC_TSC_SCALING |
6893                 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
6894
6895         /*
6896          * We can emulate "VMCS shadowing," even if the hardware
6897          * doesn't support it.
6898          */
6899         msrs->secondary_ctls_high |=
6900                 SECONDARY_EXEC_SHADOW_VMCS;
6901
6902         if (enable_ept) {
6903                 /* nested EPT: emulate EPT also to L1 */
6904                 msrs->secondary_ctls_high |=
6905                         SECONDARY_EXEC_ENABLE_EPT;
6906                 msrs->ept_caps =
6907                         VMX_EPT_PAGE_WALK_4_BIT |
6908                         VMX_EPT_PAGE_WALK_5_BIT |
6909                         VMX_EPTP_WB_BIT |
6910                         VMX_EPT_INVEPT_BIT |
6911                         VMX_EPT_EXECUTE_ONLY_BIT;
6912
6913                 msrs->ept_caps &= ept_caps;
6914                 msrs->ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
6915                         VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
6916                         VMX_EPT_1GB_PAGE_BIT;
6917                 if (enable_ept_ad_bits) {
6918                         msrs->secondary_ctls_high |=
6919                                 SECONDARY_EXEC_ENABLE_PML;
6920                         msrs->ept_caps |= VMX_EPT_AD_BIT;
6921                 }
6922
6923                 /*
6924                  * Advertise EPTP switching irrespective of hardware support,
6925                  * KVM emulates it in software so long as VMFUNC is supported.
6926                  */
6927                 if (cpu_has_vmx_vmfunc())
6928                         msrs->vmfunc_controls = VMX_VMFUNC_EPTP_SWITCHING;
6929         }
6930
6931         /*
6932          * Old versions of KVM use the single-context version without
6933          * checking for support, so declare that it is supported even
6934          * though it is treated as global context.  The alternative is
6935          * not failing the single-context invvpid, and it is worse.
6936          */
6937         if (enable_vpid) {
6938                 msrs->secondary_ctls_high |=
6939                         SECONDARY_EXEC_ENABLE_VPID;
6940                 msrs->vpid_caps = VMX_VPID_INVVPID_BIT |
6941                         VMX_VPID_EXTENT_SUPPORTED_MASK;
6942         }
6943
6944         if (enable_unrestricted_guest)
6945                 msrs->secondary_ctls_high |=
6946                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
6947
6948         if (flexpriority_enabled)
6949                 msrs->secondary_ctls_high |=
6950                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6951
6952         if (enable_sgx)
6953                 msrs->secondary_ctls_high |= SECONDARY_EXEC_ENCLS_EXITING;
6954
6955         /* miscellaneous data */
6956         msrs->misc_low = (u32)vmcs_conf->misc & VMX_MISC_SAVE_EFER_LMA;
6957         msrs->misc_low |=
6958                 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS |
6959                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
6960                 VMX_MISC_ACTIVITY_HLT |
6961                 VMX_MISC_ACTIVITY_WAIT_SIPI;
6962         msrs->misc_high = 0;
6963
6964         /*
6965          * This MSR reports some information about VMX support. We
6966          * should return information about the VMX we emulate for the
6967          * guest, and the VMCS structure we give it - not about the
6968          * VMX support of the underlying hardware.
6969          */
6970         msrs->basic =
6971                 VMCS12_REVISION |
6972                 VMX_BASIC_TRUE_CTLS |
6973                 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
6974                 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
6975
6976         if (cpu_has_vmx_basic_inout())
6977                 msrs->basic |= VMX_BASIC_INOUT;
6978
6979         /*
6980          * These MSRs specify bits which the guest must keep fixed on
6981          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
6982          * We picked the standard core2 setting.
6983          */
6984 #define VMXON_CR0_ALWAYSON     (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
6985 #define VMXON_CR4_ALWAYSON     X86_CR4_VMXE
6986         msrs->cr0_fixed0 = VMXON_CR0_ALWAYSON;
6987         msrs->cr4_fixed0 = VMXON_CR4_ALWAYSON;
6988
6989         /* These MSRs specify bits which the guest must keep fixed off. */
6990         rdmsrl(MSR_IA32_VMX_CR0_FIXED1, msrs->cr0_fixed1);
6991         rdmsrl(MSR_IA32_VMX_CR4_FIXED1, msrs->cr4_fixed1);
6992
6993         if (vmx_umip_emulated())
6994                 msrs->cr4_fixed1 |= X86_CR4_UMIP;
6995
6996         msrs->vmcs_enum = nested_vmx_calc_vmcs_enum_msr();
6997 }
6998
6999 void nested_vmx_hardware_unsetup(void)
7000 {
7001         int i;
7002
7003         if (enable_shadow_vmcs) {
7004                 for (i = 0; i < VMX_BITMAP_NR; i++)
7005                         free_page((unsigned long)vmx_bitmap[i]);
7006         }
7007 }
7008
7009 __init int nested_vmx_hardware_setup(int (*exit_handlers[])(struct kvm_vcpu *))
7010 {
7011         int i;
7012
7013         if (!cpu_has_vmx_shadow_vmcs())
7014                 enable_shadow_vmcs = 0;
7015         if (enable_shadow_vmcs) {
7016                 for (i = 0; i < VMX_BITMAP_NR; i++) {
7017                         /*
7018                          * The vmx_bitmap is not tied to a VM and so should
7019                          * not be charged to a memcg.
7020                          */
7021                         vmx_bitmap[i] = (unsigned long *)
7022                                 __get_free_page(GFP_KERNEL);
7023                         if (!vmx_bitmap[i]) {
7024                                 nested_vmx_hardware_unsetup();
7025                                 return -ENOMEM;
7026                         }
7027                 }
7028
7029                 init_vmcs_shadow_fields();
7030         }
7031
7032         exit_handlers[EXIT_REASON_VMCLEAR]      = handle_vmclear;
7033         exit_handlers[EXIT_REASON_VMLAUNCH]     = handle_vmlaunch;
7034         exit_handlers[EXIT_REASON_VMPTRLD]      = handle_vmptrld;
7035         exit_handlers[EXIT_REASON_VMPTRST]      = handle_vmptrst;
7036         exit_handlers[EXIT_REASON_VMREAD]       = handle_vmread;
7037         exit_handlers[EXIT_REASON_VMRESUME]     = handle_vmresume;
7038         exit_handlers[EXIT_REASON_VMWRITE]      = handle_vmwrite;
7039         exit_handlers[EXIT_REASON_VMOFF]        = handle_vmxoff;
7040         exit_handlers[EXIT_REASON_VMON]         = handle_vmxon;
7041         exit_handlers[EXIT_REASON_INVEPT]       = handle_invept;
7042         exit_handlers[EXIT_REASON_INVVPID]      = handle_invvpid;
7043         exit_handlers[EXIT_REASON_VMFUNC]       = handle_vmfunc;
7044
7045         return 0;
7046 }
7047
7048 struct kvm_x86_nested_ops vmx_nested_ops = {
7049         .leave_nested = vmx_leave_nested,
7050         .is_exception_vmexit = nested_vmx_is_exception_vmexit,
7051         .check_events = vmx_check_nested_events,
7052         .has_events = vmx_has_nested_events,
7053         .triple_fault = nested_vmx_triple_fault,
7054         .get_state = vmx_get_nested_state,
7055         .set_state = vmx_set_nested_state,
7056         .get_nested_state_pages = vmx_get_nested_state_pages,
7057         .write_log_dirty = nested_vmx_write_pml_buffer,
7058         .enable_evmcs = nested_enable_evmcs,
7059         .get_evmcs_version = nested_get_evmcs_version,
7060         .hv_inject_synthetic_vmexit_post_tlb_flush = vmx_hv_inject_synthetic_vmexit_post_tlb_flush,
7061 };