arch/x86/kvm/svm.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Kernel-based Virtual Machine driver for Linux
   4  *
   5  * AMD SVM support
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *   Avi Kivity   <avi@qumranet.com>
  13  */
  14
  15 #define pr_fmt(fmt) "SVM: " fmt
  16
  17 #include <linux/kvm_host.h>
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "kvm_cache_regs.h"
  22 #include "x86.h"
  23 #include "cpuid.h"
  24 #include "pmu.h"
  25
  26 #include <linux/module.h>
  27 #include <linux/mod_devicetable.h>
  28 #include <linux/kernel.h>
  29 #include <linux/vmalloc.h>
  30 #include <linux/highmem.h>
  31 #include <linux/sched.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/amd-iommu.h>
  35 #include <linux/hashtable.h>
  36 #include <linux/frame.h>
  37 #include <linux/psp-sev.h>
  38 #include <linux/file.h>
  39 #include <linux/pagemap.h>
  40 #include <linux/swap.h>
  41
  42 #include <asm/apic.h>
  43 #include <asm/perf_event.h>
  44 #include <asm/tlbflush.h>
  45 #include <asm/desc.h>
  46 #include <asm/debugreg.h>
  47 #include <asm/kvm_para.h>
  48 #include <asm/irq_remapping.h>
  49 #include <asm/spec-ctrl.h>
  50
  51 #include <asm/virtext.h>
  52 #include "trace.h"
  53
  54 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  55
  56 MODULE_AUTHOR("Qumranet");
  57 MODULE_LICENSE("GPL");
  58
  59 static const struct x86_cpu_id svm_cpu_id[] = {
  60         X86_FEATURE_MATCH(X86_FEATURE_SVM),
  61         {}
  62 };
  63 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  64
  65 #define IOPM_ALLOC_ORDER 2
  66 #define MSRPM_ALLOC_ORDER 1
  67
  68 #define SEG_TYPE_LDT 2
  69 #define SEG_TYPE_BUSY_TSS16 3
  70
  71 #define SVM_FEATURE_LBRV           (1 <<  1)
  72 #define SVM_FEATURE_SVML           (1 <<  2)
  73 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  74 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  75 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  76 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  77 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  78
  79 #define SVM_AVIC_DOORBELL       0xc001011b
  80
  81 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  82 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  83 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  84
  85 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  86
  87 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  88 #define TSC_RATIO_MIN           0x0000000000000001ULL
  89 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  90
  91 #define AVIC_HPA_MASK   ~((0xFFFULL << 52) | 0xFFF)
  92
  93 /*
  94  * 0xff is broadcast, so the max index allowed for physical APIC ID
  95  * table is 0xfe.  APIC IDs above 0xff are reserved.
  96  */
  97 #define AVIC_MAX_PHYSICAL_ID_COUNT      255
  98
  99 #define AVIC_UNACCEL_ACCESS_WRITE_MASK          1
 100 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK         0xFF0
 101 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK         0xFFFFFFFF
 102
 103 /* AVIC GATAG is encoded using VM and VCPU IDs */
 104 #define AVIC_VCPU_ID_BITS               8
 105 #define AVIC_VCPU_ID_MASK               ((1 << AVIC_VCPU_ID_BITS) - 1)
 106
 107 #define AVIC_VM_ID_BITS                 24
 108 #define AVIC_VM_ID_NR                   (1 << AVIC_VM_ID_BITS)
 109 #define AVIC_VM_ID_MASK                 ((1 << AVIC_VM_ID_BITS) - 1)
 110
 111 #define AVIC_GATAG(x, y)                (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
 112                                                 (y & AVIC_VCPU_ID_MASK))
 113 #define AVIC_GATAG_TO_VMID(x)           ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
 114 #define AVIC_GATAG_TO_VCPUID(x)         (x & AVIC_VCPU_ID_MASK)
 115
 116 static bool erratum_383_found __read_mostly;
 117
 118 static const u32 host_save_user_msrs[] = {
 119 #ifdef CONFIG_X86_64
 120         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
 121         MSR_FS_BASE,
 122 #endif
 123         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
 124         MSR_TSC_AUX,
 125 };
 126
 127 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
 128
 129 struct kvm_sev_info {
 130         bool active;            /* SEV enabled guest */
 131         unsigned int asid;      /* ASID used for this guest */
 132         unsigned int handle;    /* SEV firmware handle */
 133         int fd;                 /* SEV device fd */
 134         unsigned long pages_locked; /* Number of pages locked */
 135         struct list_head regions_list;  /* List of registered regions */
 136 };
 137
 138 struct kvm_svm {
 139         struct kvm kvm;
 140
 141         /* Struct members for AVIC */
 142         u32 avic_vm_id;
 143         struct page *avic_logical_id_table_page;
 144         struct page *avic_physical_id_table_page;
 145         struct hlist_node hnode;
 146
 147         struct kvm_sev_info sev_info;
 148 };
 149
 150 struct kvm_vcpu;
 151
 152 struct nested_state {
 153         struct vmcb *hsave;
 154         u64 hsave_msr;
 155         u64 vm_cr_msr;
 156         u64 vmcb;
 157
 158         /* These are the merged vectors */
 159         u32 *msrpm;
 160
 161         /* gpa pointers to the real vectors */
 162         u64 vmcb_msrpm;
 163         u64 vmcb_iopm;
 164
 165         /* A VMEXIT is required but not yet emulated */
 166         bool exit_required;
 167
 168         /* cache for intercepts of the guest */
 169         u32 intercept_cr;
 170         u32 intercept_dr;
 171         u32 intercept_exceptions;
 172         u64 intercept;
 173
 174         /* Nested Paging related state */
 175         u64 nested_cr3;
 176 };
 177
 178 #define MSRPM_OFFSETS   16
 179 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 180
 181 /*
 182  * Set osvw_len to higher value when updated Revision Guides
 183  * are published and we know what the new status bits are
 184  */
 185 static uint64_t osvw_len = 4, osvw_status;
 186
 187 struct vcpu_svm {
 188         struct kvm_vcpu vcpu;
 189         struct vmcb *vmcb;
 190         unsigned long vmcb_pa;
 191         struct svm_cpu_data *svm_data;
 192         uint64_t asid_generation;
 193         uint64_t sysenter_esp;
 194         uint64_t sysenter_eip;
 195         uint64_t tsc_aux;
 196
 197         u64 msr_decfg;
 198
 199         u64 next_rip;
 200
 201         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 202         struct {
 203                 u16 fs;
 204                 u16 gs;
 205                 u16 ldt;
 206                 u64 gs_base;
 207         } host;
 208
 209         u64 spec_ctrl;
 210         /*
 211          * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
 212          * translated into the appropriate L2_CFG bits on the host to
 213          * perform speculative control.
 214          */
 215         u64 virt_spec_ctrl;
 216
 217         u32 *msrpm;
 218
 219         ulong nmi_iret_rip;
 220
 221         struct nested_state nested;
 222
 223         bool nmi_singlestep;
 224         u64 nmi_singlestep_guest_rflags;
 225
 226         unsigned int3_injected;
 227         unsigned long int3_rip;
 228
 229         /* cached guest cpuid flags for faster access */
 230         bool nrips_enabled      : 1;
 231
 232         u32 ldr_reg;
 233         u32 dfr_reg;
 234         struct page *avic_backing_page;
 235         u64 *avic_physical_id_cache;
 236         bool avic_is_running;
 237
 238         /*
 239          * Per-vcpu list of struct amd_svm_iommu_ir:
 240          * This is used mainly to store interrupt remapping information used
 241          * when update the vcpu affinity. This avoids the need to scan for
 242          * IRTE and try to match ga_tag in the IOMMU driver.
 243          */
 244         struct list_head ir_list;
 245         spinlock_t ir_list_lock;
 246
 247         /* which host CPU was used for running this vcpu */
 248         unsigned int last_cpu;
 249 };
 250
 251 /*
 252  * This is a wrapper of struct amd_iommu_ir_data.
 253  */
 254 struct amd_svm_iommu_ir {
 255         struct list_head node;  /* Used by SVM for per-vcpu ir_list */
 256         void *data;             /* Storing pointer to struct amd_ir_data */
 257 };
 258
 259 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK    (0xFF)
 260 #define AVIC_LOGICAL_ID_ENTRY_VALID_BIT                 31
 261 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK                (1 << 31)
 262
 263 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK    (0xFFULL)
 264 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK        (0xFFFFFFFFFFULL << 12)
 265 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK          (1ULL << 62)
 266 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK               (1ULL << 63)
 267
 268 static DEFINE_PER_CPU(u64, current_tsc_ratio);
 269 #define TSC_RATIO_DEFAULT       0x0100000000ULL
 270
 271 #define MSR_INVALID                     0xffffffffU
 272
 273 static const struct svm_direct_access_msrs {
 274         u32 index;   /* Index of the MSR */
 275         bool always; /* True if intercept is always on */
 276 } direct_access_msrs[] = {
 277         { .index = MSR_STAR,                            .always = true  },
 278         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 279 #ifdef CONFIG_X86_64
 280         { .index = MSR_GS_BASE,                         .always = true  },
 281         { .index = MSR_FS_BASE,                         .always = true  },
 282         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 283         { .index = MSR_LSTAR,                           .always = true  },
 284         { .index = MSR_CSTAR,                           .always = true  },
 285         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 286 #endif
 287         { .index = MSR_IA32_SPEC_CTRL,                  .always = false },
 288         { .index = MSR_IA32_PRED_CMD,                   .always = false },
 289         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 290         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 291         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 292         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 293         { .index = MSR_INVALID,                         .always = false },
 294 };
 295
 296 /* enable NPT for AMD64 and X86 with PAE */
 297 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 298 static bool npt_enabled = true;
 299 #else
 300 static bool npt_enabled;
 301 #endif
 302
 303 /*
 304  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 305  * pause_filter_count: On processors that support Pause filtering(indicated
 306  *      by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
 307  *      count value. On VMRUN this value is loaded into an internal counter.
 308  *      Each time a pause instruction is executed, this counter is decremented
 309  *      until it reaches zero at which time a #VMEXIT is generated if pause
 310  *      intercept is enabled. Refer to  AMD APM Vol 2 Section 15.14.4 Pause
 311  *      Intercept Filtering for more details.
 312  *      This also indicate if ple logic enabled.
 313  *
 314  * pause_filter_thresh: In addition, some processor families support advanced
 315  *      pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
 316  *      the amount of time a guest is allowed to execute in a pause loop.
 317  *      In this mode, a 16-bit pause filter threshold field is added in the
 318  *      VMCB. The threshold value is a cycle count that is used to reset the
 319  *      pause counter. As with simple pause filtering, VMRUN loads the pause
 320  *      count value from VMCB into an internal counter. Then, on each pause
 321  *      instruction the hardware checks the elapsed number of cycles since
 322  *      the most recent pause instruction against the pause filter threshold.
 323  *      If the elapsed cycle count is greater than the pause filter threshold,
 324  *      then the internal pause count is reloaded from the VMCB and execution
 325  *      continues. If the elapsed cycle count is less than the pause filter
 326  *      threshold, then the internal pause count is decremented. If the count
 327  *      value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
 328  *      triggered. If advanced pause filtering is supported and pause filter
 329  *      threshold field is set to zero, the filter will operate in the simpler,
 330  *      count only mode.
 331  */
 332
 333 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
 334 module_param(pause_filter_thresh, ushort, 0444);
 335
 336 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
 337 module_param(pause_filter_count, ushort, 0444);
 338
 339 /* Default doubles per-vcpu window every exit. */
 340 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 341 module_param(pause_filter_count_grow, ushort, 0444);
 342
 343 /* Default resets per-vcpu window every exit to pause_filter_count. */
 344 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 345 module_param(pause_filter_count_shrink, ushort, 0444);
 346
 347 /* Default is to compute the maximum so we can never overflow. */
 348 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
 349 module_param(pause_filter_count_max, ushort, 0444);
 350
 351 /* allow nested paging (virtualized MMU) for all guests */
 352 static int npt = true;
 353 module_param(npt, int, S_IRUGO);
 354
 355 /* allow nested virtualization in KVM/SVM */
 356 static int nested = true;
 357 module_param(nested, int, S_IRUGO);
 358
 359 /* enable / disable AVIC */
 360 static int avic;
 361 #ifdef CONFIG_X86_LOCAL_APIC
 362 module_param(avic, int, S_IRUGO);
 363 #endif
 364
 365 /* enable/disable Next RIP Save */
 366 static int nrips = true;
 367 module_param(nrips, int, 0444);
 368
 369 /* enable/disable Virtual VMLOAD VMSAVE */
 370 static int vls = true;
 371 module_param(vls, int, 0444);
 372
 373 /* enable/disable Virtual GIF */
 374 static int vgif = true;
 375 module_param(vgif, int, 0444);
 376
 377 /* enable/disable SEV support */
 378 static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
 379 module_param(sev, int, 0444);
 380
 381 static bool __read_mostly dump_invalid_vmcb = 0;
 382 module_param(dump_invalid_vmcb, bool, 0644);
 383
 384 static u8 rsm_ins_bytes[] = "\x0f\xaa";
 385
 386 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
 387 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa);
 388 static void svm_complete_interrupts(struct vcpu_svm *svm);
 389
 390 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 391 static int nested_svm_intercept(struct vcpu_svm *svm);
 392 static int nested_svm_vmexit(struct vcpu_svm *svm);
 393 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 394                                       bool has_error_code, u32 error_code);
 395
 396 enum {
 397         VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
 398                             pause filter count */
 399         VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
 400         VMCB_ASID,       /* ASID */
 401         VMCB_INTR,       /* int_ctl, int_vector */
 402         VMCB_NPT,        /* npt_en, nCR3, gPAT */
 403         VMCB_CR,         /* CR0, CR3, CR4, EFER */
 404         VMCB_DR,         /* DR6, DR7 */
 405         VMCB_DT,         /* GDT, IDT */
 406         VMCB_SEG,        /* CS, DS, SS, ES, CPL */
 407         VMCB_CR2,        /* CR2 only */
 408         VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
 409         VMCB_AVIC,       /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
 410                           * AVIC PHYSICAL_TABLE pointer,
 411                           * AVIC LOGICAL_TABLE pointer
 412                           */
 413         VMCB_DIRTY_MAX,
 414 };
 415
 416 /* TPR and CR2 are always written before VMRUN */
 417 #define VMCB_ALWAYS_DIRTY_MASK  ((1U << VMCB_INTR) | (1U << VMCB_CR2))
 418
 419 #define VMCB_AVIC_APIC_BAR_MASK         0xFFFFFFFFFF000ULL
 420
 421 static unsigned int max_sev_asid;
 422 static unsigned int min_sev_asid;
 423 static unsigned long *sev_asid_bitmap;
 424 #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT)
 425
 426 struct enc_region {
 427         struct list_head list;
 428         unsigned long npages;
 429         struct page **pages;
 430         unsigned long uaddr;
 431         unsigned long size;
 432 };
 433
 434
 435 static inline struct kvm_svm *to_kvm_svm(struct kvm *kvm)
 436 {
 437         return container_of(kvm, struct kvm_svm, kvm);
 438 }
 439
 440 static inline bool svm_sev_enabled(void)
 441 {
 442         return IS_ENABLED(CONFIG_KVM_AMD_SEV) ? max_sev_asid : 0;
 443 }
 444
 445 static inline bool sev_guest(struct kvm *kvm)
 446 {
 447 #ifdef CONFIG_KVM_AMD_SEV
 448         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
 449
 450         return sev->active;
 451 #else
 452         return false;
 453 #endif
 454 }
 455
 456 static inline int sev_get_asid(struct kvm *kvm)
 457 {
 458         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
 459
 460         return sev->asid;
 461 }
 462
 463 static inline void mark_all_dirty(struct vmcb *vmcb)
 464 {
 465         vmcb->control.clean = 0;
 466 }
 467
 468 static inline void mark_all_clean(struct vmcb *vmcb)
 469 {
 470         vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
 471                                & ~VMCB_ALWAYS_DIRTY_MASK;
 472 }
 473
 474 static inline void mark_dirty(struct vmcb *vmcb, int bit)
 475 {
 476         vmcb->control.clean &= ~(1 << bit);
 477 }
 478
 479 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 480 {
 481         return container_of(vcpu, struct vcpu_svm, vcpu);
 482 }
 483
 484 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
 485 {
 486         svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
 487         mark_dirty(svm->vmcb, VMCB_AVIC);
 488 }
 489
 490 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
 491 {
 492         struct vcpu_svm *svm = to_svm(vcpu);
 493         u64 *entry = svm->avic_physical_id_cache;
 494
 495         if (!entry)
 496                 return false;
 497
 498         return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
 499 }
 500
 501 static void recalc_intercepts(struct vcpu_svm *svm)
 502 {
 503         struct vmcb_control_area *c, *h;
 504         struct nested_state *g;
 505
 506         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 507
 508         if (!is_guest_mode(&svm->vcpu))
 509                 return;
 510
 511         c = &svm->vmcb->control;
 512         h = &svm->nested.hsave->control;
 513         g = &svm->nested;
 514
 515         c->intercept_cr = h->intercept_cr | g->intercept_cr;
 516         c->intercept_dr = h->intercept_dr | g->intercept_dr;
 517         c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
 518         c->intercept = h->intercept | g->intercept;
 519 }
 520
 521 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
 522 {
 523         if (is_guest_mode(&svm->vcpu))
 524                 return svm->nested.hsave;
 525         else
 526                 return svm->vmcb;
 527 }
 528
 529 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
 530 {
 531         struct vmcb *vmcb = get_host_vmcb(svm);
 532
 533         vmcb->control.intercept_cr |= (1U << bit);
 534
 535         recalc_intercepts(svm);
 536 }
 537
 538 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
 539 {
 540         struct vmcb *vmcb = get_host_vmcb(svm);
 541
 542         vmcb->control.intercept_cr &= ~(1U << bit);
 543
 544         recalc_intercepts(svm);
 545 }
 546
 547 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
 548 {
 549         struct vmcb *vmcb = get_host_vmcb(svm);
 550
 551         return vmcb->control.intercept_cr & (1U << bit);
 552 }
 553
 554 static inline void set_dr_intercepts(struct vcpu_svm *svm)
 555 {
 556         struct vmcb *vmcb = get_host_vmcb(svm);
 557
 558         vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
 559                 | (1 << INTERCEPT_DR1_READ)
 560                 | (1 << INTERCEPT_DR2_READ)
 561                 | (1 << INTERCEPT_DR3_READ)
 562                 | (1 << INTERCEPT_DR4_READ)
 563                 | (1 << INTERCEPT_DR5_READ)
 564                 | (1 << INTERCEPT_DR6_READ)
 565                 | (1 << INTERCEPT_DR7_READ)
 566                 | (1 << INTERCEPT_DR0_WRITE)
 567                 | (1 << INTERCEPT_DR1_WRITE)
 568                 | (1 << INTERCEPT_DR2_WRITE)
 569                 | (1 << INTERCEPT_DR3_WRITE)
 570                 | (1 << INTERCEPT_DR4_WRITE)
 571                 | (1 << INTERCEPT_DR5_WRITE)
 572                 | (1 << INTERCEPT_DR6_WRITE)
 573                 | (1 << INTERCEPT_DR7_WRITE);
 574
 575         recalc_intercepts(svm);
 576 }
 577
 578 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
 579 {
 580         struct vmcb *vmcb = get_host_vmcb(svm);
 581
 582         vmcb->control.intercept_dr = 0;
 583
 584         recalc_intercepts(svm);
 585 }
 586
 587 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
 588 {
 589         struct vmcb *vmcb = get_host_vmcb(svm);
 590
 591         vmcb->control.intercept_exceptions |= (1U << bit);
 592
 593         recalc_intercepts(svm);
 594 }
 595
 596 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
 597 {
 598         struct vmcb *vmcb = get_host_vmcb(svm);
 599
 600         vmcb->control.intercept_exceptions &= ~(1U << bit);
 601
 602         recalc_intercepts(svm);
 603 }
 604
 605 static inline void set_intercept(struct vcpu_svm *svm, int bit)
 606 {
 607         struct vmcb *vmcb = get_host_vmcb(svm);
 608
 609         vmcb->control.intercept |= (1ULL << bit);
 610
 611         recalc_intercepts(svm);
 612 }
 613
 614 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
 615 {
 616         struct vmcb *vmcb = get_host_vmcb(svm);
 617
 618         vmcb->control.intercept &= ~(1ULL << bit);
 619
 620         recalc_intercepts(svm);
 621 }
 622
 623 static inline bool vgif_enabled(struct vcpu_svm *svm)
 624 {
 625         return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
 626 }
 627
 628 static inline void enable_gif(struct vcpu_svm *svm)
 629 {
 630         if (vgif_enabled(svm))
 631                 svm->vmcb->control.int_ctl |= V_GIF_MASK;
 632         else
 633                 svm->vcpu.arch.hflags |= HF_GIF_MASK;
 634 }
 635
 636 static inline void disable_gif(struct vcpu_svm *svm)
 637 {
 638         if (vgif_enabled(svm))
 639                 svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
 640         else
 641                 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 642 }
 643
 644 static inline bool gif_set(struct vcpu_svm *svm)
 645 {
 646         if (vgif_enabled(svm))
 647                 return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
 648         else
 649                 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 650 }
 651
 652 static unsigned long iopm_base;
 653
 654 struct kvm_ldttss_desc {
 655         u16 limit0;
 656         u16 base0;
 657         unsigned base1:8, type:5, dpl:2, p:1;
 658         unsigned limit1:4, zero0:3, g:1, base2:8;
 659         u32 base3;
 660         u32 zero1;
 661 } __attribute__((packed));
 662
 663 struct svm_cpu_data {
 664         int cpu;
 665
 666         u64 asid_generation;
 667         u32 max_asid;
 668         u32 next_asid;
 669         u32 min_asid;
 670         struct kvm_ldttss_desc *tss_desc;
 671
 672         struct page *save_area;
 673         struct vmcb *current_vmcb;
 674
 675         /* index = sev_asid, value = vmcb pointer */
 676         struct vmcb **sev_vmcbs;
 677 };
 678
 679 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 680
 681 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 682
 683 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 684 #define MSRS_RANGE_SIZE 2048
 685 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 686
 687 static u32 svm_msrpm_offset(u32 msr)
 688 {
 689         u32 offset;
 690         int i;
 691
 692         for (i = 0; i < NUM_MSR_MAPS; i++) {
 693                 if (msr < msrpm_ranges[i] ||
 694                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 695                         continue;
 696
 697                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 698                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 699
 700                 /* Now we have the u8 offset - but need the u32 offset */
 701                 return offset / 4;
 702         }
 703
 704         /* MSR not in any range */
 705         return MSR_INVALID;
 706 }
 707
 708 #define MAX_INST_SIZE 15
 709
 710 static inline void clgi(void)
 711 {
 712         asm volatile (__ex("clgi"));
 713 }
 714
 715 static inline void stgi(void)
 716 {
 717         asm volatile (__ex("stgi"));
 718 }
 719
 720 static inline void invlpga(unsigned long addr, u32 asid)
 721 {
 722         asm volatile (__ex("invlpga %1, %0") : : "c"(asid), "a"(addr));
 723 }
 724
 725 static int get_npt_level(struct kvm_vcpu *vcpu)
 726 {
 727 #ifdef CONFIG_X86_64
 728         return PT64_ROOT_4LEVEL;
 729 #else
 730         return PT32E_ROOT_LEVEL;
 731 #endif
 732 }
 733
 734 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 735 {
 736         vcpu->arch.efer = efer;
 737
 738         if (!npt_enabled) {
 739                 /* Shadow paging assumes NX to be available.  */
 740                 efer |= EFER_NX;
 741
 742                 if (!(efer & EFER_LMA))
 743                         efer &= ~EFER_LME;
 744         }
 745
 746         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 747         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
 748 }
 749
 750 static int is_external_interrupt(u32 info)
 751 {
 752         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 753         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 754 }
 755
 756 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
 757 {
 758         struct vcpu_svm *svm = to_svm(vcpu);
 759         u32 ret = 0;
 760
 761         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 762                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 763         return ret;
 764 }
 765
 766 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 767 {
 768         struct vcpu_svm *svm = to_svm(vcpu);
 769
 770         if (mask == 0)
 771                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 772         else
 773                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 774
 775 }
 776
 777 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
 778 {
 779         struct vcpu_svm *svm = to_svm(vcpu);
 780
 781         if (nrips && svm->vmcb->control.next_rip != 0) {
 782                 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
 783                 svm->next_rip = svm->vmcb->control.next_rip;
 784         }
 785
 786         if (!svm->next_rip) {
 787                 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
 788                         return 0;
 789         } else {
 790                 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 791                         pr_err("%s: ip 0x%lx next 0x%llx\n",
 792                                __func__, kvm_rip_read(vcpu), svm->next_rip);
 793                 kvm_rip_write(vcpu, svm->next_rip);
 794         }
 795         svm_set_interrupt_shadow(vcpu, 0);
 796
 797         return 1;
 798 }
 799
 800 static void svm_queue_exception(struct kvm_vcpu *vcpu)
 801 {
 802         struct vcpu_svm *svm = to_svm(vcpu);
 803         unsigned nr = vcpu->arch.exception.nr;
 804         bool has_error_code = vcpu->arch.exception.has_error_code;
 805         bool reinject = vcpu->arch.exception.injected;
 806         u32 error_code = vcpu->arch.exception.error_code;
 807
 808         /*
 809          * If we are within a nested VM we'd better #VMEXIT and let the guest
 810          * handle the exception
 811          */
 812         if (!reinject &&
 813             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 814                 return;
 815
 816         kvm_deliver_exception_payload(&svm->vcpu);
 817
 818         if (nr == BP_VECTOR && !nrips) {
 819                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 820
 821                 /*
 822                  * For guest debugging where we have to reinject #BP if some
 823                  * INT3 is guest-owned:
 824                  * Emulate nRIP by moving RIP forward. Will fail if injection
 825                  * raises a fault that is not intercepted. Still better than
 826                  * failing in all cases.
 827                  */
 828                 (void)skip_emulated_instruction(&svm->vcpu);
 829                 rip = kvm_rip_read(&svm->vcpu);
 830                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 831                 svm->int3_injected = rip - old_rip;
 832         }
 833
 834         svm->vmcb->control.event_inj = nr
 835                 | SVM_EVTINJ_VALID
 836                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 837                 | SVM_EVTINJ_TYPE_EXEPT;
 838         svm->vmcb->control.event_inj_err = error_code;
 839 }
 840
 841 static void svm_init_erratum_383(void)
 842 {
 843         u32 low, high;
 844         int err;
 845         u64 val;
 846
 847         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 848                 return;
 849
 850         /* Use _safe variants to not break nested virtualization */
 851         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 852         if (err)
 853                 return;
 854
 855         val |= (1ULL << 47);
 856
 857         low  = lower_32_bits(val);
 858         high = upper_32_bits(val);
 859
 860         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 861
 862         erratum_383_found = true;
 863 }
 864
 865 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 866 {
 867         /*
 868          * Guests should see errata 400 and 415 as fixed (assuming that
 869          * HLT and IO instructions are intercepted).
 870          */
 871         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 872         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 873
 874         /*
 875          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 876          * all osvw.status bits inside that length, including bit 0 (which is
 877          * reserved for erratum 298), are valid. However, if host processor's
 878          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 879          * be conservative here and therefore we tell the guest that erratum 298
 880          * is present (because we really don't know).
 881          */
 882         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 883                 vcpu->arch.osvw.status |= 1;
 884 }
 885
 886 static int has_svm(void)
 887 {
 888         const char *msg;
 889
 890         if (!cpu_has_svm(&msg)) {
 891                 printk(KERN_INFO "has_svm: %s\n", msg);
 892                 return 0;
 893         }
 894
 895         return 1;
 896 }
 897
 898 static void svm_hardware_disable(void)
 899 {
 900         /* Make sure we clean up behind us */
 901         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 902                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 903
 904         cpu_svm_disable();
 905
 906         amd_pmu_disable_virt();
 907 }
 908
 909 static int svm_hardware_enable(void)
 910 {
 911
 912         struct svm_cpu_data *sd;
 913         uint64_t efer;
 914         struct desc_struct *gdt;
 915         int me = raw_smp_processor_id();
 916
 917         rdmsrl(MSR_EFER, efer);
 918         if (efer & EFER_SVME)
 919                 return -EBUSY;
 920
 921         if (!has_svm()) {
 922                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 923                 return -EINVAL;
 924         }
 925         sd = per_cpu(svm_data, me);
 926         if (!sd) {
 927                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 928                 return -EINVAL;
 929         }
 930
 931         sd->asid_generation = 1;
 932         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 933         sd->next_asid = sd->max_asid + 1;
 934         sd->min_asid = max_sev_asid + 1;
 935
 936         gdt = get_current_gdt_rw();
 937         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 938
 939         wrmsrl(MSR_EFER, efer | EFER_SVME);
 940
 941         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 942
 943         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 944                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 945                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
 946         }
 947
 948
 949         /*
 950          * Get OSVW bits.
 951          *
 952          * Note that it is possible to have a system with mixed processor
 953          * revisions and therefore different OSVW bits. If bits are not the same
 954          * on different processors then choose the worst case (i.e. if erratum
 955          * is present on one processor and not on another then assume that the
 956          * erratum is present everywhere).
 957          */
 958         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 959                 uint64_t len, status = 0;
 960                 int err;
 961
 962                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 963                 if (!err)
 964                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 965                                                       &err);
 966
 967                 if (err)
 968                         osvw_status = osvw_len = 0;
 969                 else {
 970                         if (len < osvw_len)
 971                                 osvw_len = len;
 972                         osvw_status |= status;
 973                         osvw_status &= (1ULL << osvw_len) - 1;
 974                 }
 975         } else
 976                 osvw_status = osvw_len = 0;
 977
 978         svm_init_erratum_383();
 979
 980         amd_pmu_enable_virt();
 981
 982         return 0;
 983 }
 984
 985 static void svm_cpu_uninit(int cpu)
 986 {
 987         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 988
 989         if (!sd)
 990                 return;
 991
 992         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 993         kfree(sd->sev_vmcbs);
 994         __free_page(sd->save_area);
 995         kfree(sd);
 996 }
 997
 998 static int svm_cpu_init(int cpu)
 999 {
1000         struct svm_cpu_data *sd;
1001         int r;
1002
1003         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
1004         if (!sd)
1005                 return -ENOMEM;
1006         sd->cpu = cpu;
1007         r = -ENOMEM;
1008         sd->save_area = alloc_page(GFP_KERNEL);
1009         if (!sd->save_area)
1010                 goto err_1;
1011
1012         if (svm_sev_enabled()) {
1013                 r = -ENOMEM;
1014                 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
1015                                               sizeof(void *),
1016                                               GFP_KERNEL);
1017                 if (!sd->sev_vmcbs)
1018                         goto err_1;
1019         }
1020
1021         per_cpu(svm_data, cpu) = sd;
1022
1023         return 0;
1024
1025 err_1:
1026         kfree(sd);
1027         return r;
1028
1029 }
1030
1031 static bool valid_msr_intercept(u32 index)
1032 {
1033         int i;
1034
1035         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
1036                 if (direct_access_msrs[i].index == index)
1037                         return true;
1038
1039         return false;
1040 }
1041
1042 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, unsigned msr)
1043 {
1044         u8 bit_write;
1045         unsigned long tmp;
1046         u32 offset;
1047         u32 *msrpm;
1048
1049         msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
1050                                       to_svm(vcpu)->msrpm;
1051
1052         offset    = svm_msrpm_offset(msr);
1053         bit_write = 2 * (msr & 0x0f) + 1;
1054         tmp       = msrpm[offset];
1055
1056         BUG_ON(offset == MSR_INVALID);
1057
1058         return !!test_bit(bit_write,  &tmp);
1059 }
1060
1061 static void set_msr_interception(u32 *msrpm, unsigned msr,
1062                                  int read, int write)
1063 {
1064         u8 bit_read, bit_write;
1065         unsigned long tmp;
1066         u32 offset;
1067
1068         /*
1069          * If this warning triggers extend the direct_access_msrs list at the
1070          * beginning of the file
1071          */
1072         WARN_ON(!valid_msr_intercept(msr));
1073
1074         offset    = svm_msrpm_offset(msr);
1075         bit_read  = 2 * (msr & 0x0f);
1076         bit_write = 2 * (msr & 0x0f) + 1;
1077         tmp       = msrpm[offset];
1078
1079         BUG_ON(offset == MSR_INVALID);
1080
1081         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
1082         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
1083
1084         msrpm[offset] = tmp;
1085 }
1086
1087 static void svm_vcpu_init_msrpm(u32 *msrpm)
1088 {
1089         int i;
1090
1091         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
1092
1093         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1094                 if (!direct_access_msrs[i].always)
1095                         continue;
1096
1097                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
1098         }
1099 }
1100
1101 static void add_msr_offset(u32 offset)
1102 {
1103         int i;
1104
1105         for (i = 0; i < MSRPM_OFFSETS; ++i) {
1106
1107                 /* Offset already in list? */
1108                 if (msrpm_offsets[i] == offset)
1109                         return;
1110
1111                 /* Slot used by another offset? */
1112                 if (msrpm_offsets[i] != MSR_INVALID)
1113                         continue;
1114
1115                 /* Add offset to list */
1116                 msrpm_offsets[i] = offset;
1117
1118                 return;
1119         }
1120
1121         /*
1122          * If this BUG triggers the msrpm_offsets table has an overflow. Just
1123          * increase MSRPM_OFFSETS in this case.
1124          */
1125         BUG();
1126 }
1127
1128 static void init_msrpm_offsets(void)
1129 {
1130         int i;
1131
1132         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
1133
1134         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1135                 u32 offset;
1136
1137                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
1138                 BUG_ON(offset == MSR_INVALID);
1139
1140                 add_msr_offset(offset);
1141         }
1142 }
1143
1144 static void svm_enable_lbrv(struct vcpu_svm *svm)
1145 {
1146         u32 *msrpm = svm->msrpm;
1147
1148         svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
1149         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
1150         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
1151         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
1152         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
1153 }
1154
1155 static void svm_disable_lbrv(struct vcpu_svm *svm)
1156 {
1157         u32 *msrpm = svm->msrpm;
1158
1159         svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
1160         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
1161         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
1162         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
1163         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
1164 }
1165
1166 static void disable_nmi_singlestep(struct vcpu_svm *svm)
1167 {
1168         svm->nmi_singlestep = false;
1169
1170         if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
1171                 /* Clear our flags if they were not set by the guest */
1172                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1173                         svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
1174                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1175                         svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
1176         }
1177 }
1178
1179 /* Note:
1180  * This hash table is used to map VM_ID to a struct kvm_svm,
1181  * when handling AMD IOMMU GALOG notification to schedule in
1182  * a particular vCPU.
1183  */
1184 #define SVM_VM_DATA_HASH_BITS   8
1185 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
1186 static u32 next_vm_id = 0;
1187 static bool next_vm_id_wrapped = 0;
1188 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
1189
1190 /* Note:
1191  * This function is called from IOMMU driver to notify
1192  * SVM to schedule in a particular vCPU of a particular VM.
1193  */
1194 static int avic_ga_log_notifier(u32 ga_tag)
1195 {
1196         unsigned long flags;
1197         struct kvm_svm *kvm_svm;
1198         struct kvm_vcpu *vcpu = NULL;
1199         u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
1200         u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
1201
1202         pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
1203
1204         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1205         hash_for_each_possible(svm_vm_data_hash, kvm_svm, hnode, vm_id) {
1206                 if (kvm_svm->avic_vm_id != vm_id)
1207                         continue;
1208                 vcpu = kvm_get_vcpu_by_id(&kvm_svm->kvm, vcpu_id);
1209                 break;
1210         }
1211         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1212
1213         /* Note:
1214          * At this point, the IOMMU should have already set the pending
1215          * bit in the vAPIC backing page. So, we just need to schedule
1216          * in the vcpu.
1217          */
1218         if (vcpu)
1219                 kvm_vcpu_wake_up(vcpu);
1220
1221         return 0;
1222 }
1223
1224 static __init int sev_hardware_setup(void)
1225 {
1226         struct sev_user_data_status *status;
1227         int rc;
1228
1229         /* Maximum number of encrypted guests supported simultaneously */
1230         max_sev_asid = cpuid_ecx(0x8000001F);
1231
1232         if (!max_sev_asid)
1233                 return 1;
1234
1235         /* Minimum ASID value that should be used for SEV guest */
1236         min_sev_asid = cpuid_edx(0x8000001F);
1237
1238         /* Initialize SEV ASID bitmap */
1239         sev_asid_bitmap = bitmap_zalloc(max_sev_asid, GFP_KERNEL);
1240         if (!sev_asid_bitmap)
1241                 return 1;
1242
1243         status = kmalloc(sizeof(*status), GFP_KERNEL);
1244         if (!status)
1245                 return 1;
1246
1247         /*
1248          * Check SEV platform status.
1249          *
1250          * PLATFORM_STATUS can be called in any state, if we failed to query
1251          * the PLATFORM status then either PSP firmware does not support SEV
1252          * feature or SEV firmware is dead.
1253          */
1254         rc = sev_platform_status(status, NULL);
1255         if (rc)
1256                 goto err;
1257
1258         pr_info("SEV supported\n");
1259
1260 err:
1261         kfree(status);
1262         return rc;
1263 }
1264
1265 static void grow_ple_window(struct kvm_vcpu *vcpu)
1266 {
1267         struct vcpu_svm *svm = to_svm(vcpu);
1268         struct vmcb_control_area *control = &svm->vmcb->control;
1269         int old = control->pause_filter_count;
1270
1271         control->pause_filter_count = __grow_ple_window(old,
1272                                                         pause_filter_count,
1273                                                         pause_filter_count_grow,
1274                                                         pause_filter_count_max);
1275
1276         if (control->pause_filter_count != old) {
1277                 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1278                 trace_kvm_ple_window_update(vcpu->vcpu_id,
1279                                             control->pause_filter_count, old);
1280         }
1281 }
1282
1283 static void shrink_ple_window(struct kvm_vcpu *vcpu)
1284 {
1285         struct vcpu_svm *svm = to_svm(vcpu);
1286         struct vmcb_control_area *control = &svm->vmcb->control;
1287         int old = control->pause_filter_count;
1288
1289         control->pause_filter_count =
1290                                 __shrink_ple_window(old,
1291                                                     pause_filter_count,
1292                                                     pause_filter_count_shrink,
1293                                                     pause_filter_count);
1294         if (control->pause_filter_count != old) {
1295                 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1296                 trace_kvm_ple_window_update(vcpu->vcpu_id,
1297                                             control->pause_filter_count, old);
1298         }
1299 }
1300
1301 static __init int svm_hardware_setup(void)
1302 {
1303         int cpu;
1304         struct page *iopm_pages;
1305         void *iopm_va;
1306         int r;
1307
1308         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1309
1310         if (!iopm_pages)
1311                 return -ENOMEM;
1312
1313         iopm_va = page_address(iopm_pages);
1314         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1315         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1316
1317         init_msrpm_offsets();
1318
1319         if (boot_cpu_has(X86_FEATURE_NX))
1320                 kvm_enable_efer_bits(EFER_NX);
1321
1322         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1323                 kvm_enable_efer_bits(EFER_FFXSR);
1324
1325         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1326                 kvm_has_tsc_control = true;
1327                 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1328                 kvm_tsc_scaling_ratio_frac_bits = 32;
1329         }
1330
1331         /* Check for pause filtering support */
1332         if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1333                 pause_filter_count = 0;
1334                 pause_filter_thresh = 0;
1335         } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
1336                 pause_filter_thresh = 0;
1337         }
1338
1339         if (nested) {
1340                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1341                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1342         }
1343
1344         if (sev) {
1345                 if (boot_cpu_has(X86_FEATURE_SEV) &&
1346                     IS_ENABLED(CONFIG_KVM_AMD_SEV)) {
1347                         r = sev_hardware_setup();
1348                         if (r)
1349                                 sev = false;
1350                 } else {
1351                         sev = false;
1352                 }
1353         }
1354
1355         for_each_possible_cpu(cpu) {
1356                 r = svm_cpu_init(cpu);
1357                 if (r)
1358                         goto err;
1359         }
1360
1361         if (!boot_cpu_has(X86_FEATURE_NPT))
1362                 npt_enabled = false;
1363
1364         if (npt_enabled && !npt) {
1365                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1366                 npt_enabled = false;
1367         }
1368
1369         if (npt_enabled) {
1370                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1371                 kvm_enable_tdp();
1372         } else
1373                 kvm_disable_tdp();
1374
1375         if (nrips) {
1376                 if (!boot_cpu_has(X86_FEATURE_NRIPS))
1377                         nrips = false;
1378         }
1379
1380         if (avic) {
1381                 if (!npt_enabled ||
1382                     !boot_cpu_has(X86_FEATURE_AVIC) ||
1383                     !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1384                         avic = false;
1385                 } else {
1386                         pr_info("AVIC enabled\n");
1387
1388                         amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1389                 }
1390         }
1391
1392         if (vls) {
1393                 if (!npt_enabled ||
1394                     !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1395                     !IS_ENABLED(CONFIG_X86_64)) {
1396                         vls = false;
1397                 } else {
1398                         pr_info("Virtual VMLOAD VMSAVE supported\n");
1399                 }
1400         }
1401
1402         if (vgif) {
1403                 if (!boot_cpu_has(X86_FEATURE_VGIF))
1404                         vgif = false;
1405                 else
1406                         pr_info("Virtual GIF supported\n");
1407         }
1408
1409         return 0;
1410
1411 err:
1412         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1413         iopm_base = 0;
1414         return r;
1415 }
1416
1417 static __exit void svm_hardware_unsetup(void)
1418 {
1419         int cpu;
1420
1421         if (svm_sev_enabled())
1422                 bitmap_free(sev_asid_bitmap);
1423
1424         for_each_possible_cpu(cpu)
1425                 svm_cpu_uninit(cpu);
1426
1427         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1428         iopm_base = 0;
1429 }
1430
1431 static void init_seg(struct vmcb_seg *seg)
1432 {
1433         seg->selector = 0;
1434         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1435                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1436         seg->limit = 0xffff;
1437         seg->base = 0;
1438 }
1439
1440 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1441 {
1442         seg->selector = 0;
1443         seg->attrib = SVM_SELECTOR_P_MASK | type;
1444         seg->limit = 0xffff;
1445         seg->base = 0;
1446 }
1447
1448 static u64 svm_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1449 {
1450         struct vcpu_svm *svm = to_svm(vcpu);
1451
1452         if (is_guest_mode(vcpu))
1453                 return svm->nested.hsave->control.tsc_offset;
1454
1455         return vcpu->arch.tsc_offset;
1456 }
1457
1458 static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1459 {
1460         struct vcpu_svm *svm = to_svm(vcpu);
1461         u64 g_tsc_offset = 0;
1462
1463         if (is_guest_mode(vcpu)) {
1464                 /* Write L1's TSC offset.  */
1465                 g_tsc_offset = svm->vmcb->control.tsc_offset -
1466                                svm->nested.hsave->control.tsc_offset;
1467                 svm->nested.hsave->control.tsc_offset = offset;
1468         }
1469
1470         trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1471                                    svm->vmcb->control.tsc_offset - g_tsc_offset,
1472                                    offset);
1473
1474         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1475
1476         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1477         return svm->vmcb->control.tsc_offset;
1478 }
1479
1480 static void avic_init_vmcb(struct vcpu_svm *svm)
1481 {
1482         struct vmcb *vmcb = svm->vmcb;
1483         struct kvm_svm *kvm_svm = to_kvm_svm(svm->vcpu.kvm);
1484         phys_addr_t bpa = __sme_set(page_to_phys(svm->avic_backing_page));
1485         phys_addr_t lpa = __sme_set(page_to_phys(kvm_svm->avic_logical_id_table_page));
1486         phys_addr_t ppa = __sme_set(page_to_phys(kvm_svm->avic_physical_id_table_page));
1487
1488         vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1489         vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1490         vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1491         vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1492         vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1493 }
1494
1495 static void init_vmcb(struct vcpu_svm *svm)
1496 {
1497         struct vmcb_control_area *control = &svm->vmcb->control;
1498         struct vmcb_save_area *save = &svm->vmcb->save;
1499
1500         svm->vcpu.arch.hflags = 0;
1501
1502         set_cr_intercept(svm, INTERCEPT_CR0_READ);
1503         set_cr_intercept(svm, INTERCEPT_CR3_READ);
1504         set_cr_intercept(svm, INTERCEPT_CR4_READ);
1505         set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1506         set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1507         set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1508         if (!kvm_vcpu_apicv_active(&svm->vcpu))
1509                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1510
1511         set_dr_intercepts(svm);
1512
1513         set_exception_intercept(svm, PF_VECTOR);
1514         set_exception_intercept(svm, UD_VECTOR);
1515         set_exception_intercept(svm, MC_VECTOR);
1516         set_exception_intercept(svm, AC_VECTOR);
1517         set_exception_intercept(svm, DB_VECTOR);
1518         /*
1519          * Guest access to VMware backdoor ports could legitimately
1520          * trigger #GP because of TSS I/O permission bitmap.
1521          * We intercept those #GP and allow access to them anyway
1522          * as VMware does.
1523          */
1524         if (enable_vmware_backdoor)
1525                 set_exception_intercept(svm, GP_VECTOR);
1526
1527         set_intercept(svm, INTERCEPT_INTR);
1528         set_intercept(svm, INTERCEPT_NMI);
1529         set_intercept(svm, INTERCEPT_SMI);
1530         set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1531         set_intercept(svm, INTERCEPT_RDPMC);
1532         set_intercept(svm, INTERCEPT_CPUID);
1533         set_intercept(svm, INTERCEPT_INVD);
1534         set_intercept(svm, INTERCEPT_INVLPG);
1535         set_intercept(svm, INTERCEPT_INVLPGA);
1536         set_intercept(svm, INTERCEPT_IOIO_PROT);
1537         set_intercept(svm, INTERCEPT_MSR_PROT);
1538         set_intercept(svm, INTERCEPT_TASK_SWITCH);
1539         set_intercept(svm, INTERCEPT_SHUTDOWN);
1540         set_intercept(svm, INTERCEPT_VMRUN);
1541         set_intercept(svm, INTERCEPT_VMMCALL);
1542         set_intercept(svm, INTERCEPT_VMLOAD);
1543         set_intercept(svm, INTERCEPT_VMSAVE);
1544         set_intercept(svm, INTERCEPT_STGI);
1545         set_intercept(svm, INTERCEPT_CLGI);
1546         set_intercept(svm, INTERCEPT_SKINIT);
1547         set_intercept(svm, INTERCEPT_WBINVD);
1548         set_intercept(svm, INTERCEPT_XSETBV);
1549         set_intercept(svm, INTERCEPT_RDPRU);
1550         set_intercept(svm, INTERCEPT_RSM);
1551
1552         if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1553                 set_intercept(svm, INTERCEPT_MONITOR);
1554                 set_intercept(svm, INTERCEPT_MWAIT);
1555         }
1556
1557         if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1558                 set_intercept(svm, INTERCEPT_HLT);
1559
1560         control->iopm_base_pa = __sme_set(iopm_base);
1561         control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1562         control->int_ctl = V_INTR_MASKING_MASK;
1563
1564         init_seg(&save->es);
1565         init_seg(&save->ss);
1566         init_seg(&save->ds);
1567         init_seg(&save->fs);
1568         init_seg(&save->gs);
1569
1570         save->cs.selector = 0xf000;
1571         save->cs.base = 0xffff0000;
1572         /* Executable/Readable Code Segment */
1573         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1574                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1575         save->cs.limit = 0xffff;
1576
1577         save->gdtr.limit = 0xffff;
1578         save->idtr.limit = 0xffff;
1579
1580         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1581         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1582
1583         svm_set_efer(&svm->vcpu, 0);
1584         save->dr6 = 0xffff0ff0;
1585         kvm_set_rflags(&svm->vcpu, 2);
1586         save->rip = 0x0000fff0;
1587         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1588
1589         /*
1590          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1591          * It also updates the guest-visible cr0 value.
1592          */
1593         svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1594         kvm_mmu_reset_context(&svm->vcpu);
1595
1596         save->cr4 = X86_CR4_PAE;
1597         /* rdx = ?? */
1598
1599         if (npt_enabled) {
1600                 /* Setup VMCB for Nested Paging */
1601                 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1602                 clr_intercept(svm, INTERCEPT_INVLPG);
1603                 clr_exception_intercept(svm, PF_VECTOR);
1604                 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1605                 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1606                 save->g_pat = svm->vcpu.arch.pat;
1607                 save->cr3 = 0;
1608                 save->cr4 = 0;
1609         }
1610         svm->asid_generation = 0;
1611
1612         svm->nested.vmcb = 0;
1613         svm->vcpu.arch.hflags = 0;
1614
1615         if (pause_filter_count) {
1616                 control->pause_filter_count = pause_filter_count;
1617                 if (pause_filter_thresh)
1618                         control->pause_filter_thresh = pause_filter_thresh;
1619                 set_intercept(svm, INTERCEPT_PAUSE);
1620         } else {
1621                 clr_intercept(svm, INTERCEPT_PAUSE);
1622         }
1623
1624         if (kvm_vcpu_apicv_active(&svm->vcpu))
1625                 avic_init_vmcb(svm);
1626
1627         /*
1628          * If hardware supports Virtual VMLOAD VMSAVE then enable it
1629          * in VMCB and clear intercepts to avoid #VMEXIT.
1630          */
1631         if (vls) {
1632                 clr_intercept(svm, INTERCEPT_VMLOAD);
1633                 clr_intercept(svm, INTERCEPT_VMSAVE);
1634                 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1635         }
1636
1637         if (vgif) {
1638                 clr_intercept(svm, INTERCEPT_STGI);
1639                 clr_intercept(svm, INTERCEPT_CLGI);
1640                 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1641         }
1642
1643         if (sev_guest(svm->vcpu.kvm)) {
1644                 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1645                 clr_exception_intercept(svm, UD_VECTOR);
1646         }
1647
1648         mark_all_dirty(svm->vmcb);
1649
1650         enable_gif(svm);
1651
1652 }
1653
1654 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu,
1655                                        unsigned int index)
1656 {
1657         u64 *avic_physical_id_table;
1658         struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
1659
1660         if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1661                 return NULL;
1662
1663         avic_physical_id_table = page_address(kvm_svm->avic_physical_id_table_page);
1664
1665         return &avic_physical_id_table[index];
1666 }
1667
1668 /**
1669  * Note:
1670  * AVIC hardware walks the nested page table to check permissions,
1671  * but does not use the SPA address specified in the leaf page
1672  * table entry since it uses  address in the AVIC_BACKING_PAGE pointer
1673  * field of the VMCB. Therefore, we set up the
1674  * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1675  */
1676 static int avic_init_access_page(struct kvm_vcpu *vcpu)
1677 {
1678         struct kvm *kvm = vcpu->kvm;
1679         int ret = 0;
1680
1681         mutex_lock(&kvm->slots_lock);
1682         if (kvm->arch.apic_access_page_done)
1683                 goto out;
1684
1685         ret = __x86_set_memory_region(kvm,
1686                                       APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1687                                       APIC_DEFAULT_PHYS_BASE,
1688                                       PAGE_SIZE);
1689         if (ret)
1690                 goto out;
1691
1692         kvm->arch.apic_access_page_done = true;
1693 out:
1694         mutex_unlock(&kvm->slots_lock);
1695         return ret;
1696 }
1697
1698 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1699 {
1700         int ret;
1701         u64 *entry, new_entry;
1702         int id = vcpu->vcpu_id;
1703         struct vcpu_svm *svm = to_svm(vcpu);
1704
1705         ret = avic_init_access_page(vcpu);
1706         if (ret)
1707                 return ret;
1708
1709         if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1710                 return -EINVAL;
1711
1712         if (!svm->vcpu.arch.apic->regs)
1713                 return -EINVAL;
1714
1715         svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1716
1717         /* Setting AVIC backing page address in the phy APIC ID table */
1718         entry = avic_get_physical_id_entry(vcpu, id);
1719         if (!entry)
1720                 return -EINVAL;
1721
1722         new_entry = __sme_set((page_to_phys(svm->avic_backing_page) &
1723                               AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1724                               AVIC_PHYSICAL_ID_ENTRY_VALID_MASK);
1725         WRITE_ONCE(*entry, new_entry);
1726
1727         svm->avic_physical_id_cache = entry;
1728
1729         return 0;
1730 }
1731
1732 static void __sev_asid_free(int asid)
1733 {
1734         struct svm_cpu_data *sd;
1735         int cpu, pos;
1736
1737         pos = asid - 1;
1738         clear_bit(pos, sev_asid_bitmap);
1739
1740         for_each_possible_cpu(cpu) {
1741                 sd = per_cpu(svm_data, cpu);
1742                 sd->sev_vmcbs[pos] = NULL;
1743         }
1744 }
1745
1746 static void sev_asid_free(struct kvm *kvm)
1747 {
1748         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1749
1750         __sev_asid_free(sev->asid);
1751 }
1752
1753 static void sev_unbind_asid(struct kvm *kvm, unsigned int handle)
1754 {
1755         struct sev_data_decommission *decommission;
1756         struct sev_data_deactivate *data;
1757
1758         if (!handle)
1759                 return;
1760
1761         data = kzalloc(sizeof(*data), GFP_KERNEL);
1762         if (!data)
1763                 return;
1764
1765         /* deactivate handle */
1766         data->handle = handle;
1767         sev_guest_deactivate(data, NULL);
1768
1769         wbinvd_on_all_cpus();
1770         sev_guest_df_flush(NULL);
1771         kfree(data);
1772
1773         decommission = kzalloc(sizeof(*decommission), GFP_KERNEL);
1774         if (!decommission)
1775                 return;
1776
1777         /* decommission handle */
1778         decommission->handle = handle;
1779         sev_guest_decommission(decommission, NULL);
1780
1781         kfree(decommission);
1782 }
1783
1784 static struct page **sev_pin_memory(struct kvm *kvm, unsigned long uaddr,
1785                                     unsigned long ulen, unsigned long *n,
1786                                     int write)
1787 {
1788         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1789         unsigned long npages, npinned, size;
1790         unsigned long locked, lock_limit;
1791         struct page **pages;
1792         unsigned long first, last;
1793
1794         if (ulen == 0 || uaddr + ulen < uaddr)
1795                 return NULL;
1796
1797         /* Calculate number of pages. */
1798         first = (uaddr & PAGE_MASK) >> PAGE_SHIFT;
1799         last = ((uaddr + ulen - 1) & PAGE_MASK) >> PAGE_SHIFT;
1800         npages = (last - first + 1);
1801
1802         locked = sev->pages_locked + npages;
1803         lock_limit = rlimit(RLIMIT_MEMLOCK) >> PAGE_SHIFT;
1804         if (locked > lock_limit && !capable(CAP_IPC_LOCK)) {
1805                 pr_err("SEV: %lu locked pages exceed the lock limit of %lu.\n", locked, lock_limit);
1806                 return NULL;
1807         }
1808
1809         /* Avoid using vmalloc for smaller buffers. */
1810         size = npages * sizeof(struct page *);
1811         if (size > PAGE_SIZE)
1812                 pages = __vmalloc(size, GFP_KERNEL_ACCOUNT | __GFP_ZERO,
1813                                   PAGE_KERNEL);
1814         else
1815                 pages = kmalloc(size, GFP_KERNEL_ACCOUNT);
1816
1817         if (!pages)
1818                 return NULL;
1819
1820         /* Pin the user virtual address. */
1821         npinned = get_user_pages_fast(uaddr, npages, FOLL_WRITE, pages);
1822         if (npinned != npages) {
1823                 pr_err("SEV: Failure locking %lu pages.\n", npages);
1824                 goto err;
1825         }
1826
1827         *n = npages;
1828         sev->pages_locked = locked;
1829
1830         return pages;
1831
1832 err:
1833         if (npinned > 0)
1834                 release_pages(pages, npinned);
1835
1836         kvfree(pages);
1837         return NULL;
1838 }
1839
1840 static void sev_unpin_memory(struct kvm *kvm, struct page **pages,
1841                              unsigned long npages)
1842 {
1843         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1844
1845         release_pages(pages, npages);
1846         kvfree(pages);
1847         sev->pages_locked -= npages;
1848 }
1849
1850 static void sev_clflush_pages(struct page *pages[], unsigned long npages)
1851 {
1852         uint8_t *page_virtual;
1853         unsigned long i;
1854
1855         if (npages == 0 || pages == NULL)
1856                 return;
1857
1858         for (i = 0; i < npages; i++) {
1859                 page_virtual = kmap_atomic(pages[i]);
1860                 clflush_cache_range(page_virtual, PAGE_SIZE);
1861                 kunmap_atomic(page_virtual);
1862         }
1863 }
1864
1865 static void __unregister_enc_region_locked(struct kvm *kvm,
1866                                            struct enc_region *region)
1867 {
1868         /*
1869          * The guest may change the memory encryption attribute from C=0 -> C=1
1870          * or vice versa for this memory range. Lets make sure caches are
1871          * flushed to ensure that guest data gets written into memory with
1872          * correct C-bit.
1873          */
1874         sev_clflush_pages(region->pages, region->npages);
1875
1876         sev_unpin_memory(kvm, region->pages, region->npages);
1877         list_del(&region->list);
1878         kfree(region);
1879 }
1880
1881 static struct kvm *svm_vm_alloc(void)
1882 {
1883         struct kvm_svm *kvm_svm = __vmalloc(sizeof(struct kvm_svm),
1884                                             GFP_KERNEL_ACCOUNT | __GFP_ZERO,
1885                                             PAGE_KERNEL);
1886         return &kvm_svm->kvm;
1887 }
1888
1889 static void svm_vm_free(struct kvm *kvm)
1890 {
1891         vfree(to_kvm_svm(kvm));
1892 }
1893
1894 static void sev_vm_destroy(struct kvm *kvm)
1895 {
1896         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1897         struct list_head *head = &sev->regions_list;
1898         struct list_head *pos, *q;
1899
1900         if (!sev_guest(kvm))
1901                 return;
1902
1903         mutex_lock(&kvm->lock);
1904
1905         /*
1906          * if userspace was terminated before unregistering the memory regions
1907          * then lets unpin all the registered memory.
1908          */
1909         if (!list_empty(head)) {
1910                 list_for_each_safe(pos, q, head) {
1911                         __unregister_enc_region_locked(kvm,
1912                                 list_entry(pos, struct enc_region, list));
1913                 }
1914         }
1915
1916         mutex_unlock(&kvm->lock);
1917
1918         sev_unbind_asid(kvm, sev->handle);
1919         sev_asid_free(kvm);
1920 }
1921
1922 static void avic_vm_destroy(struct kvm *kvm)
1923 {
1924         unsigned long flags;
1925         struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1926
1927         if (!avic)
1928                 return;
1929
1930         if (kvm_svm->avic_logical_id_table_page)
1931                 __free_page(kvm_svm->avic_logical_id_table_page);
1932         if (kvm_svm->avic_physical_id_table_page)
1933                 __free_page(kvm_svm->avic_physical_id_table_page);
1934
1935         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1936         hash_del(&kvm_svm->hnode);
1937         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1938 }
1939
1940 static void svm_vm_destroy(struct kvm *kvm)
1941 {
1942         avic_vm_destroy(kvm);
1943         sev_vm_destroy(kvm);
1944 }
1945
1946 static int avic_vm_init(struct kvm *kvm)
1947 {
1948         unsigned long flags;
1949         int err = -ENOMEM;
1950         struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1951         struct kvm_svm *k2;
1952         struct page *p_page;
1953         struct page *l_page;
1954         u32 vm_id;
1955
1956         if (!avic)
1957                 return 0;
1958
1959         /* Allocating physical APIC ID table (4KB) */
1960         p_page = alloc_page(GFP_KERNEL_ACCOUNT);
1961         if (!p_page)
1962                 goto free_avic;
1963
1964         kvm_svm->avic_physical_id_table_page = p_page;
1965         clear_page(page_address(p_page));
1966
1967         /* Allocating logical APIC ID table (4KB) */
1968         l_page = alloc_page(GFP_KERNEL_ACCOUNT);
1969         if (!l_page)
1970                 goto free_avic;
1971
1972         kvm_svm->avic_logical_id_table_page = l_page;
1973         clear_page(page_address(l_page));
1974
1975         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1976  again:
1977         vm_id = next_vm_id = (next_vm_id + 1) & AVIC_VM_ID_MASK;
1978         if (vm_id == 0) { /* id is 1-based, zero is not okay */
1979                 next_vm_id_wrapped = 1;
1980                 goto again;
1981         }
1982         /* Is it still in use? Only possible if wrapped at least once */
1983         if (next_vm_id_wrapped) {
1984                 hash_for_each_possible(svm_vm_data_hash, k2, hnode, vm_id) {
1985                         if (k2->avic_vm_id == vm_id)
1986                                 goto again;
1987                 }
1988         }
1989         kvm_svm->avic_vm_id = vm_id;
1990         hash_add(svm_vm_data_hash, &kvm_svm->hnode, kvm_svm->avic_vm_id);
1991         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1992
1993         return 0;
1994
1995 free_avic:
1996         avic_vm_destroy(kvm);
1997         return err;
1998 }
1999
2000 static inline int
2001 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
2002 {
2003         int ret = 0;
2004         unsigned long flags;
2005         struct amd_svm_iommu_ir *ir;
2006         struct vcpu_svm *svm = to_svm(vcpu);
2007
2008         if (!kvm_arch_has_assigned_device(vcpu->kvm))
2009                 return 0;
2010
2011         /*
2012          * Here, we go through the per-vcpu ir_list to update all existing
2013          * interrupt remapping table entry targeting this vcpu.
2014          */
2015         spin_lock_irqsave(&svm->ir_list_lock, flags);
2016
2017         if (list_empty(&svm->ir_list))
2018                 goto out;
2019
2020         list_for_each_entry(ir, &svm->ir_list, node) {
2021                 ret = amd_iommu_update_ga(cpu, r, ir->data);
2022                 if (ret)
2023                         break;
2024         }
2025 out:
2026         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
2027         return ret;
2028 }
2029
2030 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2031 {
2032         u64 entry;
2033         /* ID = 0xff (broadcast), ID > 0xff (reserved) */
2034         int h_physical_id = kvm_cpu_get_apicid(cpu);
2035         struct vcpu_svm *svm = to_svm(vcpu);
2036
2037         if (!kvm_vcpu_apicv_active(vcpu))
2038                 return;
2039
2040         /*
2041          * Since the host physical APIC id is 8 bits,
2042          * we can support host APIC ID upto 255.
2043          */
2044         if (WARN_ON(h_physical_id > AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK))
2045                 return;
2046
2047         entry = READ_ONCE(*(svm->avic_physical_id_cache));
2048         WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
2049
2050         entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
2051         entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
2052
2053         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2054         if (svm->avic_is_running)
2055                 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2056
2057         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2058         avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
2059                                         svm->avic_is_running);
2060 }
2061
2062 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
2063 {
2064         u64 entry;
2065         struct vcpu_svm *svm = to_svm(vcpu);
2066
2067         if (!kvm_vcpu_apicv_active(vcpu))
2068                 return;
2069
2070         entry = READ_ONCE(*(svm->avic_physical_id_cache));
2071         if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
2072                 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
2073
2074         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2075         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2076 }
2077
2078 /**
2079  * This function is called during VCPU halt/unhalt.
2080  */
2081 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
2082 {
2083         struct vcpu_svm *svm = to_svm(vcpu);
2084
2085         svm->avic_is_running = is_run;
2086         if (is_run)
2087                 avic_vcpu_load(vcpu, vcpu->cpu);
2088         else
2089                 avic_vcpu_put(vcpu);
2090 }
2091
2092 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
2093 {
2094         struct vcpu_svm *svm = to_svm(vcpu);
2095         u32 dummy;
2096         u32 eax = 1;
2097
2098         vcpu->arch.microcode_version = 0x01000065;
2099         svm->spec_ctrl = 0;
2100         svm->virt_spec_ctrl = 0;
2101
2102         if (!init_event) {
2103                 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
2104                                            MSR_IA32_APICBASE_ENABLE;
2105                 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
2106                         svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
2107         }
2108         init_vmcb(svm);
2109
2110         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, true);
2111         kvm_rdx_write(vcpu, eax);
2112
2113         if (kvm_vcpu_apicv_active(vcpu) && !init_event)
2114                 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
2115 }
2116
2117 static int avic_init_vcpu(struct vcpu_svm *svm)
2118 {
2119         int ret;
2120
2121         if (!kvm_vcpu_apicv_active(&svm->vcpu))
2122                 return 0;
2123
2124         ret = avic_init_backing_page(&svm->vcpu);
2125         if (ret)
2126                 return ret;
2127
2128         INIT_LIST_HEAD(&svm->ir_list);
2129         spin_lock_init(&svm->ir_list_lock);
2130         svm->dfr_reg = APIC_DFR_FLAT;
2131
2132         return ret;
2133 }
2134
2135 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
2136 {
2137         struct vcpu_svm *svm;
2138         struct page *page;
2139         struct page *msrpm_pages;
2140         struct page *hsave_page;
2141         struct page *nested_msrpm_pages;
2142         int err;
2143
2144         BUILD_BUG_ON_MSG(offsetof(struct vcpu_svm, vcpu) != 0,
2145                 "struct kvm_vcpu must be at offset 0 for arch usercopy region");
2146
2147         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL_ACCOUNT);
2148         if (!svm) {
2149                 err = -ENOMEM;
2150                 goto out;
2151         }
2152
2153         svm->vcpu.arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
2154                                                      GFP_KERNEL_ACCOUNT);
2155         if (!svm->vcpu.arch.user_fpu) {
2156                 printk(KERN_ERR "kvm: failed to allocate kvm userspace's fpu\n");
2157                 err = -ENOMEM;
2158                 goto free_partial_svm;
2159         }
2160
2161         svm->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
2162                                                      GFP_KERNEL_ACCOUNT);
2163         if (!svm->vcpu.arch.guest_fpu) {
2164                 printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n");
2165                 err = -ENOMEM;
2166                 goto free_user_fpu;
2167         }
2168
2169         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
2170         if (err)
2171                 goto free_svm;
2172
2173         err = -ENOMEM;
2174         page = alloc_page(GFP_KERNEL_ACCOUNT);
2175         if (!page)
2176                 goto uninit;
2177
2178         msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
2179         if (!msrpm_pages)
2180                 goto free_page1;
2181
2182         nested_msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
2183         if (!nested_msrpm_pages)
2184                 goto free_page2;
2185
2186         hsave_page = alloc_page(GFP_KERNEL_ACCOUNT);
2187         if (!hsave_page)
2188                 goto free_page3;
2189
2190         err = avic_init_vcpu(svm);
2191         if (err)
2192                 goto free_page4;
2193
2194         /* We initialize this flag to true to make sure that the is_running
2195          * bit would be set the first time the vcpu is loaded.
2196          */
2197         svm->avic_is_running = true;
2198
2199         svm->nested.hsave = page_address(hsave_page);
2200
2201         svm->msrpm = page_address(msrpm_pages);
2202         svm_vcpu_init_msrpm(svm->msrpm);
2203
2204         svm->nested.msrpm = page_address(nested_msrpm_pages);
2205         svm_vcpu_init_msrpm(svm->nested.msrpm);
2206
2207         svm->vmcb = page_address(page);
2208         clear_page(svm->vmcb);
2209         svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT);
2210         svm->asid_generation = 0;
2211         init_vmcb(svm);
2212
2213         svm_init_osvw(&svm->vcpu);
2214
2215         return &svm->vcpu;
2216
2217 free_page4:
2218         __free_page(hsave_page);
2219 free_page3:
2220         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
2221 free_page2:
2222         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
2223 free_page1:
2224         __free_page(page);
2225 uninit:
2226         kvm_vcpu_uninit(&svm->vcpu);
2227 free_svm:
2228         kmem_cache_free(x86_fpu_cache, svm->vcpu.arch.guest_fpu);
2229 free_user_fpu:
2230         kmem_cache_free(x86_fpu_cache, svm->vcpu.arch.user_fpu);
2231 free_partial_svm:
2232         kmem_cache_free(kvm_vcpu_cache, svm);
2233 out:
2234         return ERR_PTR(err);
2235 }
2236
2237 static void svm_clear_current_vmcb(struct vmcb *vmcb)
2238 {
2239         int i;
2240
2241         for_each_online_cpu(i)
2242                 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
2243 }
2244
2245 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
2246 {
2247         struct vcpu_svm *svm = to_svm(vcpu);
2248
2249         /*
2250          * The vmcb page can be recycled, causing a false negative in
2251          * svm_vcpu_load(). So, ensure that no logical CPU has this
2252          * vmcb page recorded as its current vmcb.
2253          */
2254         svm_clear_current_vmcb(svm->vmcb);
2255
2256         __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
2257         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
2258         __free_page(virt_to_page(svm->nested.hsave));
2259         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
2260         kvm_vcpu_uninit(vcpu);
2261         kmem_cache_free(x86_fpu_cache, svm->vcpu.arch.user_fpu);
2262         kmem_cache_free(x86_fpu_cache, svm->vcpu.arch.guest_fpu);
2263         kmem_cache_free(kvm_vcpu_cache, svm);
2264 }
2265
2266 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2267 {
2268         struct vcpu_svm *svm = to_svm(vcpu);
2269         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2270         int i;
2271
2272         if (unlikely(cpu != vcpu->cpu)) {
2273                 svm->asid_generation = 0;
2274                 mark_all_dirty(svm->vmcb);
2275         }
2276
2277 #ifdef CONFIG_X86_64
2278         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
2279 #endif
2280         savesegment(fs, svm->host.fs);
2281         savesegment(gs, svm->host.gs);
2282         svm->host.ldt = kvm_read_ldt();
2283
2284         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2285                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2286
2287         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
2288                 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2289                 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
2290                         __this_cpu_write(current_tsc_ratio, tsc_ratio);
2291                         wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
2292                 }
2293         }
2294         /* This assumes that the kernel never uses MSR_TSC_AUX */
2295         if (static_cpu_has(X86_FEATURE_RDTSCP))
2296                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2297
2298         if (sd->current_vmcb != svm->vmcb) {
2299                 sd->current_vmcb = svm->vmcb;
2300                 indirect_branch_prediction_barrier();
2301         }
2302         avic_vcpu_load(vcpu, cpu);
2303 }
2304
2305 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
2306 {
2307         struct vcpu_svm *svm = to_svm(vcpu);
2308         int i;
2309
2310         avic_vcpu_put(vcpu);
2311
2312         ++vcpu->stat.host_state_reload;
2313         kvm_load_ldt(svm->host.ldt);
2314 #ifdef CONFIG_X86_64
2315         loadsegment(fs, svm->host.fs);
2316         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
2317         load_gs_index(svm->host.gs);
2318 #else
2319 #ifdef CONFIG_X86_32_LAZY_GS
2320         loadsegment(gs, svm->host.gs);
2321 #endif
2322 #endif
2323         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2324                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2325 }
2326
2327 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
2328 {
2329         avic_set_running(vcpu, false);
2330 }
2331
2332 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
2333 {
2334         avic_set_running(vcpu, true);
2335 }
2336
2337 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
2338 {
2339         struct vcpu_svm *svm = to_svm(vcpu);
2340         unsigned long rflags = svm->vmcb->save.rflags;
2341
2342         if (svm->nmi_singlestep) {
2343                 /* Hide our flags if they were not set by the guest */
2344                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
2345                         rflags &= ~X86_EFLAGS_TF;
2346                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
2347                         rflags &= ~X86_EFLAGS_RF;
2348         }
2349         return rflags;
2350 }
2351
2352 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2353 {
2354         if (to_svm(vcpu)->nmi_singlestep)
2355                 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2356
2357        /*
2358         * Any change of EFLAGS.VM is accompanied by a reload of SS
2359         * (caused by either a task switch or an inter-privilege IRET),
2360         * so we do not need to update the CPL here.
2361         */
2362         to_svm(vcpu)->vmcb->save.rflags = rflags;
2363 }
2364
2365 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2366 {
2367         switch (reg) {
2368         case VCPU_EXREG_PDPTR:
2369                 BUG_ON(!npt_enabled);
2370                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
2371                 break;
2372         default:
2373                 BUG();
2374         }
2375 }
2376
2377 static void svm_set_vintr(struct vcpu_svm *svm)
2378 {
2379         set_intercept(svm, INTERCEPT_VINTR);
2380 }
2381
2382 static void svm_clear_vintr(struct vcpu_svm *svm)
2383 {
2384         clr_intercept(svm, INTERCEPT_VINTR);
2385 }
2386
2387 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
2388 {
2389         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2390
2391         switch (seg) {
2392         case VCPU_SREG_CS: return &save->cs;
2393         case VCPU_SREG_DS: return &save->ds;
2394         case VCPU_SREG_ES: return &save->es;
2395         case VCPU_SREG_FS: return &save->fs;
2396         case VCPU_SREG_GS: return &save->gs;
2397         case VCPU_SREG_SS: return &save->ss;
2398         case VCPU_SREG_TR: return &save->tr;
2399         case VCPU_SREG_LDTR: return &save->ldtr;
2400         }
2401         BUG();
2402         return NULL;
2403 }
2404
2405 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2406 {
2407         struct vmcb_seg *s = svm_seg(vcpu, seg);
2408
2409         return s->base;
2410 }
2411
2412 static void svm_get_segment(struct kvm_vcpu *vcpu,
2413                             struct kvm_segment *var, int seg)
2414 {
2415         struct vmcb_seg *s = svm_seg(vcpu, seg);
2416
2417         var->base = s->base;
2418         var->limit = s->limit;
2419         var->selector = s->selector;
2420         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
2421         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
2422         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
2423         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
2424         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
2425         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
2426         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
2427
2428         /*
2429          * AMD CPUs circa 2014 track the G bit for all segments except CS.
2430          * However, the SVM spec states that the G bit is not observed by the
2431          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
2432          * So let's synthesize a legal G bit for all segments, this helps
2433          * running KVM nested. It also helps cross-vendor migration, because
2434          * Intel's vmentry has a check on the 'G' bit.
2435          */
2436         var->g = s->limit > 0xfffff;
2437
2438         /*
2439          * AMD's VMCB does not have an explicit unusable field, so emulate it
2440          * for cross vendor migration purposes by "not present"
2441          */
2442         var->unusable = !var->present;
2443
2444         switch (seg) {
2445         case VCPU_SREG_TR:
2446                 /*
2447                  * Work around a bug where the busy flag in the tr selector
2448                  * isn't exposed
2449                  */
2450                 var->type |= 0x2;
2451                 break;
2452         case VCPU_SREG_DS:
2453         case VCPU_SREG_ES:
2454         case VCPU_SREG_FS:
2455         case VCPU_SREG_GS:
2456                 /*
2457                  * The accessed bit must always be set in the segment
2458                  * descriptor cache, although it can be cleared in the
2459                  * descriptor, the cached bit always remains at 1. Since
2460                  * Intel has a check on this, set it here to support
2461                  * cross-vendor migration.
2462                  */
2463                 if (!var->unusable)
2464                         var->type |= 0x1;
2465                 break;
2466         case VCPU_SREG_SS:
2467                 /*
2468                  * On AMD CPUs sometimes the DB bit in the segment
2469                  * descriptor is left as 1, although the whole segment has
2470                  * been made unusable. Clear it here to pass an Intel VMX
2471                  * entry check when cross vendor migrating.
2472                  */
2473                 if (var->unusable)
2474                         var->db = 0;
2475                 /* This is symmetric with svm_set_segment() */
2476                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
2477                 break;
2478         }
2479 }
2480
2481 static int svm_get_cpl(struct kvm_vcpu *vcpu)
2482 {
2483         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2484
2485         return save->cpl;
2486 }
2487
2488 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2489 {
2490         struct vcpu_svm *svm = to_svm(vcpu);
2491
2492         dt->size = svm->vmcb->save.idtr.limit;
2493         dt->address = svm->vmcb->save.idtr.base;
2494 }
2495
2496 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2497 {
2498         struct vcpu_svm *svm = to_svm(vcpu);
2499
2500         svm->vmcb->save.idtr.limit = dt->size;
2501         svm->vmcb->save.idtr.base = dt->address ;
2502         mark_dirty(svm->vmcb, VMCB_DT);
2503 }
2504
2505 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2506 {
2507         struct vcpu_svm *svm = to_svm(vcpu);
2508
2509         dt->size = svm->vmcb->save.gdtr.limit;
2510         dt->address = svm->vmcb->save.gdtr.base;
2511 }
2512
2513 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2514 {
2515         struct vcpu_svm *svm = to_svm(vcpu);
2516
2517         svm->vmcb->save.gdtr.limit = dt->size;
2518         svm->vmcb->save.gdtr.base = dt->address ;
2519         mark_dirty(svm->vmcb, VMCB_DT);
2520 }
2521
2522 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2523 {
2524 }
2525
2526 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
2527 {
2528 }
2529
2530 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2531 {
2532 }
2533
2534 static void update_cr0_intercept(struct vcpu_svm *svm)
2535 {
2536         ulong gcr0 = svm->vcpu.arch.cr0;
2537         u64 *hcr0 = &svm->vmcb->save.cr0;
2538
2539         *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
2540                 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
2541
2542         mark_dirty(svm->vmcb, VMCB_CR);
2543
2544         if (gcr0 == *hcr0) {
2545                 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
2546                 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2547         } else {
2548                 set_cr_intercept(svm, INTERCEPT_CR0_READ);
2549                 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2550         }
2551 }
2552
2553 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2554 {
2555         struct vcpu_svm *svm = to_svm(vcpu);
2556
2557 #ifdef CONFIG_X86_64
2558         if (vcpu->arch.efer & EFER_LME) {
2559                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
2560                         vcpu->arch.efer |= EFER_LMA;
2561                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
2562                 }
2563
2564                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
2565                         vcpu->arch.efer &= ~EFER_LMA;
2566                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
2567                 }
2568         }
2569 #endif
2570         vcpu->arch.cr0 = cr0;
2571
2572         if (!npt_enabled)
2573                 cr0 |= X86_CR0_PG | X86_CR0_WP;
2574
2575         /*
2576          * re-enable caching here because the QEMU bios
2577          * does not do it - this results in some delay at
2578          * reboot
2579          */
2580         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
2581                 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
2582         svm->vmcb->save.cr0 = cr0;
2583         mark_dirty(svm->vmcb, VMCB_CR);
2584         update_cr0_intercept(svm);
2585 }
2586
2587 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2588 {
2589         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
2590         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
2591
2592         if (cr4 & X86_CR4_VMXE)
2593                 return 1;
2594
2595         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
2596                 svm_flush_tlb(vcpu, true);
2597
2598         vcpu->arch.cr4 = cr4;
2599         if (!npt_enabled)
2600                 cr4 |= X86_CR4_PAE;
2601         cr4 |= host_cr4_mce;
2602         to_svm(vcpu)->vmcb->save.cr4 = cr4;
2603         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
2604         return 0;
2605 }
2606
2607 static void svm_set_segment(struct kvm_vcpu *vcpu,
2608                             struct kvm_segment *var, int seg)
2609 {
2610         struct vcpu_svm *svm = to_svm(vcpu);
2611         struct vmcb_seg *s = svm_seg(vcpu, seg);
2612
2613         s->base = var->base;
2614         s->limit = var->limit;
2615         s->selector = var->selector;
2616         s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
2617         s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
2618         s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
2619         s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
2620         s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
2621         s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
2622         s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
2623         s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
2624
2625         /*
2626          * This is always accurate, except if SYSRET returned to a segment
2627          * with SS.DPL != 3.  Intel does not have this quirk, and always
2628          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2629          * would entail passing the CPL to userspace and back.
2630          */
2631         if (seg == VCPU_SREG_SS)
2632                 /* This is symmetric with svm_get_segment() */
2633                 svm->vmcb->save.cpl = (var->dpl & 3);
2634
2635         mark_dirty(svm->vmcb, VMCB_SEG);
2636 }
2637
2638 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2639 {
2640         struct vcpu_svm *svm = to_svm(vcpu);
2641
2642         clr_exception_intercept(svm, BP_VECTOR);
2643
2644         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2645                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2646                         set_exception_intercept(svm, BP_VECTOR);
2647         } else
2648                 vcpu->guest_debug = 0;
2649 }
2650
2651 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2652 {
2653         if (sd->next_asid > sd->max_asid) {
2654                 ++sd->asid_generation;
2655                 sd->next_asid = sd->min_asid;
2656                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2657         }
2658
2659         svm->asid_generation = sd->asid_generation;
2660         svm->vmcb->control.asid = sd->next_asid++;
2661
2662         mark_dirty(svm->vmcb, VMCB_ASID);
2663 }
2664
2665 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2666 {
2667         return to_svm(vcpu)->vmcb->save.dr6;
2668 }
2669
2670 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2671 {
2672         struct vcpu_svm *svm = to_svm(vcpu);
2673
2674         svm->vmcb->save.dr6 = value;
2675         mark_dirty(svm->vmcb, VMCB_DR);
2676 }
2677
2678 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2679 {
2680         struct vcpu_svm *svm = to_svm(vcpu);
2681
2682         get_debugreg(vcpu->arch.db[0], 0);
2683         get_debugreg(vcpu->arch.db[1], 1);
2684         get_debugreg(vcpu->arch.db[2], 2);
2685         get_debugreg(vcpu->arch.db[3], 3);
2686         vcpu->arch.dr6 = svm_get_dr6(vcpu);
2687         vcpu->arch.dr7 = svm->vmcb->save.dr7;
2688
2689         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2690         set_dr_intercepts(svm);
2691 }
2692
2693 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2694 {
2695         struct vcpu_svm *svm = to_svm(vcpu);
2696
2697         svm->vmcb->save.dr7 = value;
2698         mark_dirty(svm->vmcb, VMCB_DR);
2699 }
2700
2701 static int pf_interception(struct vcpu_svm *svm)
2702 {
2703         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2704         u64 error_code = svm->vmcb->control.exit_info_1;
2705
2706         return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
2707                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2708                         svm->vmcb->control.insn_bytes : NULL,
2709                         svm->vmcb->control.insn_len);
2710 }
2711
2712 static int npf_interception(struct vcpu_svm *svm)
2713 {
2714         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2715         u64 error_code = svm->vmcb->control.exit_info_1;
2716
2717         trace_kvm_page_fault(fault_address, error_code);
2718         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
2719                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2720                         svm->vmcb->control.insn_bytes : NULL,
2721                         svm->vmcb->control.insn_len);
2722 }
2723
2724 static int db_interception(struct vcpu_svm *svm)
2725 {
2726         struct kvm_run *kvm_run = svm->vcpu.run;
2727         struct kvm_vcpu *vcpu = &svm->vcpu;
2728
2729         if (!(svm->vcpu.guest_debug &
2730               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2731                 !svm->nmi_singlestep) {
2732                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2733                 return 1;
2734         }
2735
2736         if (svm->nmi_singlestep) {
2737                 disable_nmi_singlestep(svm);
2738                 /* Make sure we check for pending NMIs upon entry */
2739                 kvm_make_request(KVM_REQ_EVENT, vcpu);
2740         }
2741
2742         if (svm->vcpu.guest_debug &
2743             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2744                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2745                 kvm_run->debug.arch.pc =
2746                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2747                 kvm_run->debug.arch.exception = DB_VECTOR;
2748                 return 0;
2749         }
2750
2751         return 1;
2752 }
2753
2754 static int bp_interception(struct vcpu_svm *svm)
2755 {
2756         struct kvm_run *kvm_run = svm->vcpu.run;
2757
2758         kvm_run->exit_reason = KVM_EXIT_DEBUG;
2759         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2760         kvm_run->debug.arch.exception = BP_VECTOR;
2761         return 0;
2762 }
2763
2764 static int ud_interception(struct vcpu_svm *svm)
2765 {
2766         return handle_ud(&svm->vcpu);
2767 }
2768
2769 static int ac_interception(struct vcpu_svm *svm)
2770 {
2771         kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2772         return 1;
2773 }
2774
2775 static int gp_interception(struct vcpu_svm *svm)
2776 {
2777         struct kvm_vcpu *vcpu = &svm->vcpu;
2778         u32 error_code = svm->vmcb->control.exit_info_1;
2779
2780         WARN_ON_ONCE(!enable_vmware_backdoor);
2781
2782         /*
2783          * VMware backdoor emulation on #GP interception only handles IN{S},
2784          * OUT{S}, and RDPMC, none of which generate a non-zero error code.
2785          */
2786         if (error_code) {
2787                 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2788                 return 1;
2789         }
2790         return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
2791 }
2792
2793 static bool is_erratum_383(void)
2794 {
2795         int err, i;
2796         u64 value;
2797
2798         if (!erratum_383_found)
2799                 return false;
2800
2801         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2802         if (err)
2803                 return false;
2804
2805         /* Bit 62 may or may not be set for this mce */
2806         value &= ~(1ULL << 62);
2807
2808         if (value != 0xb600000000010015ULL)
2809                 return false;
2810
2811         /* Clear MCi_STATUS registers */
2812         for (i = 0; i < 6; ++i)
2813                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2814
2815         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2816         if (!err) {
2817                 u32 low, high;
2818
2819                 value &= ~(1ULL << 2);
2820                 low    = lower_32_bits(value);
2821                 high   = upper_32_bits(value);
2822
2823                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2824         }
2825
2826         /* Flush tlb to evict multi-match entries */
2827         __flush_tlb_all();
2828
2829         return true;
2830 }
2831
2832 static void svm_handle_mce(struct vcpu_svm *svm)
2833 {
2834         if (is_erratum_383()) {
2835                 /*
2836                  * Erratum 383 triggered. Guest state is corrupt so kill the
2837                  * guest.
2838                  */
2839                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2840
2841                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2842
2843                 return;
2844         }
2845
2846         /*
2847          * On an #MC intercept the MCE handler is not called automatically in
2848          * the host. So do it by hand here.
2849          */
2850         asm volatile (
2851                 "int $0x12\n");
2852         /* not sure if we ever come back to this point */
2853
2854         return;
2855 }
2856
2857 static int mc_interception(struct vcpu_svm *svm)
2858 {
2859         return 1;
2860 }
2861
2862 static int shutdown_interception(struct vcpu_svm *svm)
2863 {
2864         struct kvm_run *kvm_run = svm->vcpu.run;
2865
2866         /*
2867          * VMCB is undefined after a SHUTDOWN intercept
2868          * so reinitialize it.
2869          */
2870         clear_page(svm->vmcb);
2871         init_vmcb(svm);
2872
2873         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2874         return 0;
2875 }
2876
2877 static int io_interception(struct vcpu_svm *svm)
2878 {
2879         struct kvm_vcpu *vcpu = &svm->vcpu;
2880         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2881         int size, in, string;
2882         unsigned port;
2883
2884         ++svm->vcpu.stat.io_exits;
2885         string = (io_info & SVM_IOIO_STR_MASK) != 0;
2886         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2887         if (string)
2888                 return kvm_emulate_instruction(vcpu, 0);
2889
2890         port = io_info >> 16;
2891         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2892         svm->next_rip = svm->vmcb->control.exit_info_2;
2893
2894         return kvm_fast_pio(&svm->vcpu, size, port, in);
2895 }
2896
2897 static int nmi_interception(struct vcpu_svm *svm)
2898 {
2899         return 1;
2900 }
2901
2902 static int intr_interception(struct vcpu_svm *svm)
2903 {
2904         ++svm->vcpu.stat.irq_exits;
2905         return 1;
2906 }
2907
2908 static int nop_on_interception(struct vcpu_svm *svm)
2909 {
2910         return 1;
2911 }
2912
2913 static int halt_interception(struct vcpu_svm *svm)
2914 {
2915         return kvm_emulate_halt(&svm->vcpu);
2916 }
2917
2918 static int vmmcall_interception(struct vcpu_svm *svm)
2919 {
2920         return kvm_emulate_hypercall(&svm->vcpu);
2921 }
2922
2923 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2924 {
2925         struct vcpu_svm *svm = to_svm(vcpu);
2926
2927         return svm->nested.nested_cr3;
2928 }
2929
2930 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2931 {
2932         struct vcpu_svm *svm = to_svm(vcpu);
2933         u64 cr3 = svm->nested.nested_cr3;
2934         u64 pdpte;
2935         int ret;
2936
2937         ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(__sme_clr(cr3)), &pdpte,
2938                                        offset_in_page(cr3) + index * 8, 8);
2939         if (ret)
2940                 return 0;
2941         return pdpte;
2942 }
2943
2944 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2945                                    unsigned long root)
2946 {
2947         struct vcpu_svm *svm = to_svm(vcpu);
2948
2949         svm->vmcb->control.nested_cr3 = __sme_set(root);
2950         mark_dirty(svm->vmcb, VMCB_NPT);
2951 }
2952
2953 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2954                                        struct x86_exception *fault)
2955 {
2956         struct vcpu_svm *svm = to_svm(vcpu);
2957
2958         if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2959                 /*
2960                  * TODO: track the cause of the nested page fault, and
2961                  * correctly fill in the high bits of exit_info_1.
2962                  */
2963                 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2964                 svm->vmcb->control.exit_code_hi = 0;
2965                 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2966                 svm->vmcb->control.exit_info_2 = fault->address;
2967         }
2968
2969         svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2970         svm->vmcb->control.exit_info_1 |= fault->error_code;
2971
2972         /*
2973          * The present bit is always zero for page structure faults on real
2974          * hardware.
2975          */
2976         if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2977                 svm->vmcb->control.exit_info_1 &= ~1;
2978
2979         nested_svm_vmexit(svm);
2980 }
2981
2982 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2983 {
2984         WARN_ON(mmu_is_nested(vcpu));
2985
2986         vcpu->arch.mmu = &vcpu->arch.guest_mmu;
2987         kvm_init_shadow_mmu(vcpu);
2988         vcpu->arch.mmu->set_cr3           = nested_svm_set_tdp_cr3;
2989         vcpu->arch.mmu->get_cr3           = nested_svm_get_tdp_cr3;
2990         vcpu->arch.mmu->get_pdptr         = nested_svm_get_tdp_pdptr;
2991         vcpu->arch.mmu->inject_page_fault = nested_svm_inject_npf_exit;
2992         vcpu->arch.mmu->shadow_root_level = get_npt_level(vcpu);
2993         reset_shadow_zero_bits_mask(vcpu, vcpu->arch.mmu);
2994         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
2995 }
2996
2997 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2998 {
2999         vcpu->arch.mmu = &vcpu->arch.root_mmu;
3000         vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
3001 }
3002
3003 static int nested_svm_check_permissions(struct vcpu_svm *svm)
3004 {
3005         if (!(svm->vcpu.arch.efer & EFER_SVME) ||
3006             !is_paging(&svm->vcpu)) {
3007                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3008                 return 1;
3009         }
3010
3011         if (svm->vmcb->save.cpl) {
3012                 kvm_inject_gp(&svm->vcpu, 0);
3013                 return 1;
3014         }
3015
3016         return 0;
3017 }
3018
3019 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
3020                                       bool has_error_code, u32 error_code)
3021 {
3022         int vmexit;
3023
3024         if (!is_guest_mode(&svm->vcpu))
3025                 return 0;
3026
3027         vmexit = nested_svm_intercept(svm);
3028         if (vmexit != NESTED_EXIT_DONE)
3029                 return 0;
3030
3031         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
3032         svm->vmcb->control.exit_code_hi = 0;
3033         svm->vmcb->control.exit_info_1 = error_code;
3034
3035         /*
3036          * EXITINFO2 is undefined for all exception intercepts other
3037          * than #PF.
3038          */
3039         if (svm->vcpu.arch.exception.nested_apf)
3040                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.apf.nested_apf_token;
3041         else if (svm->vcpu.arch.exception.has_payload)
3042                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.exception.payload;
3043         else
3044                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
3045
3046         svm->nested.exit_required = true;
3047         return vmexit;
3048 }
3049
3050 /* This function returns true if it is save to enable the irq window */
3051 static inline bool nested_svm_intr(struct vcpu_svm *svm)
3052 {
3053         if (!is_guest_mode(&svm->vcpu))
3054                 return true;
3055
3056         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3057                 return true;
3058
3059         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
3060                 return false;
3061
3062         /*
3063          * if vmexit was already requested (by intercepted exception
3064          * for instance) do not overwrite it with "external interrupt"
3065          * vmexit.
3066          */
3067         if (svm->nested.exit_required)
3068                 return false;
3069
3070         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
3071         svm->vmcb->control.exit_info_1 = 0;
3072         svm->vmcb->control.exit_info_2 = 0;
3073
3074         if (svm->nested.intercept & 1ULL) {
3075                 /*
3076                  * The #vmexit can't be emulated here directly because this
3077                  * code path runs with irqs and preemption disabled. A
3078                  * #vmexit emulation might sleep. Only signal request for
3079                  * the #vmexit here.
3080                  */
3081                 svm->nested.exit_required = true;
3082                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
3083                 return false;
3084         }
3085
3086         return true;
3087 }
3088
3089 /* This function returns true if it is save to enable the nmi window */
3090 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
3091 {
3092         if (!is_guest_mode(&svm->vcpu))
3093                 return true;
3094
3095         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
3096                 return true;
3097
3098         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
3099         svm->nested.exit_required = true;
3100
3101         return false;
3102 }
3103
3104 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
3105 {
3106         unsigned port, size, iopm_len;
3107         u16 val, mask;
3108         u8 start_bit;
3109         u64 gpa;
3110
3111         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
3112                 return NESTED_EXIT_HOST;
3113
3114         port = svm->vmcb->control.exit_info_1 >> 16;
3115         size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
3116                 SVM_IOIO_SIZE_SHIFT;
3117         gpa  = svm->nested.vmcb_iopm + (port / 8);
3118         start_bit = port % 8;
3119         iopm_len = (start_bit + size > 8) ? 2 : 1;
3120         mask = (0xf >> (4 - size)) << start_bit;
3121         val = 0;
3122
3123         if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
3124                 return NESTED_EXIT_DONE;
3125
3126         return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3127 }
3128
3129 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
3130 {
3131         u32 offset, msr, value;
3132         int write, mask;
3133
3134         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3135                 return NESTED_EXIT_HOST;
3136
3137         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3138         offset = svm_msrpm_offset(msr);
3139         write  = svm->vmcb->control.exit_info_1 & 1;
3140         mask   = 1 << ((2 * (msr & 0xf)) + write);
3141
3142         if (offset == MSR_INVALID)
3143                 return NESTED_EXIT_DONE;
3144
3145         /* Offset is in 32 bit units but need in 8 bit units */
3146         offset *= 4;
3147
3148         if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
3149                 return NESTED_EXIT_DONE;
3150
3151         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3152 }
3153
3154 /* DB exceptions for our internal use must not cause vmexit */
3155 static int nested_svm_intercept_db(struct vcpu_svm *svm)
3156 {
3157         unsigned long dr6;
3158
3159         /* if we're not singlestepping, it's not ours */
3160         if (!svm->nmi_singlestep)
3161                 return NESTED_EXIT_DONE;
3162
3163         /* if it's not a singlestep exception, it's not ours */
3164         if (kvm_get_dr(&svm->vcpu, 6, &dr6))
3165                 return NESTED_EXIT_DONE;
3166         if (!(dr6 & DR6_BS))
3167                 return NESTED_EXIT_DONE;
3168
3169         /* if the guest is singlestepping, it should get the vmexit */
3170         if (svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF) {
3171                 disable_nmi_singlestep(svm);
3172                 return NESTED_EXIT_DONE;
3173         }
3174
3175         /* it's ours, the nested hypervisor must not see this one */
3176         return NESTED_EXIT_HOST;
3177 }
3178
3179 static int nested_svm_exit_special(struct vcpu_svm *svm)
3180 {
3181         u32 exit_code = svm->vmcb->control.exit_code;
3182
3183         switch (exit_code) {
3184         case SVM_EXIT_INTR:
3185         case SVM_EXIT_NMI:
3186         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
3187                 return NESTED_EXIT_HOST;
3188         case SVM_EXIT_NPF:
3189                 /* For now we are always handling NPFs when using them */
3190                 if (npt_enabled)
3191                         return NESTED_EXIT_HOST;
3192                 break;
3193         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
3194                 /* When we're shadowing, trap PFs, but not async PF */
3195                 if (!npt_enabled && svm->vcpu.arch.apf.host_apf_reason == 0)
3196                         return NESTED_EXIT_HOST;
3197                 break;
3198         default:
3199                 break;
3200         }
3201
3202         return NESTED_EXIT_CONTINUE;
3203 }
3204
3205 /*
3206  * If this function returns true, this #vmexit was already handled
3207  */
3208 static int nested_svm_intercept(struct vcpu_svm *svm)
3209 {
3210         u32 exit_code = svm->vmcb->control.exit_code;
3211         int vmexit = NESTED_EXIT_HOST;
3212
3213         switch (exit_code) {
3214         case SVM_EXIT_MSR:
3215                 vmexit = nested_svm_exit_handled_msr(svm);
3216                 break;
3217         case SVM_EXIT_IOIO:
3218                 vmexit = nested_svm_intercept_ioio(svm);
3219                 break;
3220         case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
3221                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
3222                 if (svm->nested.intercept_cr & bit)
3223                         vmexit = NESTED_EXIT_DONE;
3224                 break;
3225         }
3226         case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
3227                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
3228                 if (svm->nested.intercept_dr & bit)
3229                         vmexit = NESTED_EXIT_DONE;
3230                 break;
3231         }
3232         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
3233                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
3234                 if (svm->nested.intercept_exceptions & excp_bits) {
3235                         if (exit_code == SVM_EXIT_EXCP_BASE + DB_VECTOR)
3236                                 vmexit = nested_svm_intercept_db(svm);
3237                         else
3238                                 vmexit = NESTED_EXIT_DONE;
3239                 }
3240                 /* async page fault always cause vmexit */
3241                 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
3242                          svm->vcpu.arch.exception.nested_apf != 0)
3243                         vmexit = NESTED_EXIT_DONE;
3244                 break;
3245         }
3246         case SVM_EXIT_ERR: {
3247                 vmexit = NESTED_EXIT_DONE;
3248                 break;
3249         }
3250         default: {
3251                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
3252                 if (svm->nested.intercept & exit_bits)
3253                         vmexit = NESTED_EXIT_DONE;
3254         }
3255         }
3256
3257         return vmexit;
3258 }
3259
3260 static int nested_svm_exit_handled(struct vcpu_svm *svm)
3261 {
3262         int vmexit;
3263
3264         vmexit = nested_svm_intercept(svm);
3265
3266         if (vmexit == NESTED_EXIT_DONE)
3267                 nested_svm_vmexit(svm);
3268
3269         return vmexit;
3270 }
3271
3272 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
3273 {
3274         struct vmcb_control_area *dst  = &dst_vmcb->control;
3275         struct vmcb_control_area *from = &from_vmcb->control;
3276
3277         dst->intercept_cr         = from->intercept_cr;
3278         dst->intercept_dr         = from->intercept_dr;
3279         dst->intercept_exceptions = from->intercept_exceptions;
3280         dst->intercept            = from->intercept;
3281         dst->iopm_base_pa         = from->iopm_base_pa;
3282         dst->msrpm_base_pa        = from->msrpm_base_pa;
3283         dst->tsc_offset           = from->tsc_offset;
3284         dst->asid                 = from->asid;
3285         dst->tlb_ctl              = from->tlb_ctl;
3286         dst->int_ctl              = from->int_ctl;
3287         dst->int_vector           = from->int_vector;
3288         dst->int_state            = from->int_state;
3289         dst->exit_code            = from->exit_code;
3290         dst->exit_code_hi         = from->exit_code_hi;
3291         dst->exit_info_1          = from->exit_info_1;
3292         dst->exit_info_2          = from->exit_info_2;
3293         dst->exit_int_info        = from->exit_int_info;
3294         dst->exit_int_info_err    = from->exit_int_info_err;
3295         dst->nested_ctl           = from->nested_ctl;
3296         dst->event_inj            = from->event_inj;
3297         dst->event_inj_err        = from->event_inj_err;
3298         dst->nested_cr3           = from->nested_cr3;
3299         dst->virt_ext              = from->virt_ext;
3300         dst->pause_filter_count   = from->pause_filter_count;
3301         dst->pause_filter_thresh  = from->pause_filter_thresh;
3302 }
3303
3304 static int nested_svm_vmexit(struct vcpu_svm *svm)
3305 {
3306         int rc;
3307         struct vmcb *nested_vmcb;
3308         struct vmcb *hsave = svm->nested.hsave;
3309         struct vmcb *vmcb = svm->vmcb;
3310         struct kvm_host_map map;
3311
3312         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
3313                                        vmcb->control.exit_info_1,
3314                                        vmcb->control.exit_info_2,
3315                                        vmcb->control.exit_int_info,
3316                                        vmcb->control.exit_int_info_err,
3317                                        KVM_ISA_SVM);
3318
3319         rc = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->nested.vmcb), &map);
3320         if (rc) {
3321                 if (rc == -EINVAL)
3322                         kvm_inject_gp(&svm->vcpu, 0);
3323                 return 1;
3324         }
3325
3326         nested_vmcb = map.hva;
3327
3328         /* Exit Guest-Mode */
3329         leave_guest_mode(&svm->vcpu);
3330         svm->nested.vmcb = 0;
3331
3332         /* Give the current vmcb to the guest */
3333         disable_gif(svm);
3334
3335         nested_vmcb->save.es     = vmcb->save.es;
3336         nested_vmcb->save.cs     = vmcb->save.cs;
3337         nested_vmcb->save.ss     = vmcb->save.ss;
3338         nested_vmcb->save.ds     = vmcb->save.ds;
3339         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
3340         nested_vmcb->save.idtr   = vmcb->save.idtr;
3341         nested_vmcb->save.efer   = svm->vcpu.arch.efer;
3342         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
3343         nested_vmcb->save.cr3    = kvm_read_cr3(&svm->vcpu);
3344         nested_vmcb->save.cr2    = vmcb->save.cr2;
3345         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
3346         nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
3347         nested_vmcb->save.rip    = vmcb->save.rip;
3348         nested_vmcb->save.rsp    = vmcb->save.rsp;
3349         nested_vmcb->save.rax    = vmcb->save.rax;
3350         nested_vmcb->save.dr7    = vmcb->save.dr7;
3351         nested_vmcb->save.dr6    = vmcb->save.dr6;
3352         nested_vmcb->save.cpl    = vmcb->save.cpl;
3353
3354         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
3355         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
3356         nested_vmcb->control.int_state         = vmcb->control.int_state;
3357         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
3358         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
3359         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
3360         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
3361         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
3362         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
3363
3364         if (svm->nrips_enabled)
3365                 nested_vmcb->control.next_rip  = vmcb->control.next_rip;
3366
3367         /*
3368          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
3369          * to make sure that we do not lose injected events. So check event_inj
3370          * here and copy it to exit_int_info if it is valid.
3371          * Exit_int_info and event_inj can't be both valid because the case
3372          * below only happens on a VMRUN instruction intercept which has
3373          * no valid exit_int_info set.
3374          */
3375         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
3376                 struct vmcb_control_area *nc = &nested_vmcb->control;
3377
3378                 nc->exit_int_info     = vmcb->control.event_inj;
3379                 nc->exit_int_info_err = vmcb->control.event_inj_err;
3380         }
3381
3382         nested_vmcb->control.tlb_ctl           = 0;
3383         nested_vmcb->control.event_inj         = 0;
3384         nested_vmcb->control.event_inj_err     = 0;
3385
3386         nested_vmcb->control.pause_filter_count =
3387                 svm->vmcb->control.pause_filter_count;
3388         nested_vmcb->control.pause_filter_thresh =
3389                 svm->vmcb->control.pause_filter_thresh;
3390
3391         /* We always set V_INTR_MASKING and remember the old value in hflags */
3392         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3393                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
3394
3395         /* Restore the original control entries */
3396         copy_vmcb_control_area(vmcb, hsave);
3397
3398         svm->vcpu.arch.tsc_offset = svm->vmcb->control.tsc_offset;
3399         kvm_clear_exception_queue(&svm->vcpu);
3400         kvm_clear_interrupt_queue(&svm->vcpu);
3401
3402         svm->nested.nested_cr3 = 0;
3403
3404         /* Restore selected save entries */
3405         svm->vmcb->save.es = hsave->save.es;
3406         svm->vmcb->save.cs = hsave->save.cs;
3407         svm->vmcb->save.ss = hsave->save.ss;
3408         svm->vmcb->save.ds = hsave->save.ds;
3409         svm->vmcb->save.gdtr = hsave->save.gdtr;
3410         svm->vmcb->save.idtr = hsave->save.idtr;
3411         kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
3412         svm_set_efer(&svm->vcpu, hsave->save.efer);
3413         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
3414         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
3415         if (npt_enabled) {
3416                 svm->vmcb->save.cr3 = hsave->save.cr3;
3417                 svm->vcpu.arch.cr3 = hsave->save.cr3;
3418         } else {
3419                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
3420         }
3421         kvm_rax_write(&svm->vcpu, hsave->save.rax);
3422         kvm_rsp_write(&svm->vcpu, hsave->save.rsp);
3423         kvm_rip_write(&svm->vcpu, hsave->save.rip);
3424         svm->vmcb->save.dr7 = 0;
3425         svm->vmcb->save.cpl = 0;
3426         svm->vmcb->control.exit_int_info = 0;
3427
3428         mark_all_dirty(svm->vmcb);
3429
3430         kvm_vcpu_unmap(&svm->vcpu, &map, true);
3431
3432         nested_svm_uninit_mmu_context(&svm->vcpu);
3433         kvm_mmu_reset_context(&svm->vcpu);
3434         kvm_mmu_load(&svm->vcpu);
3435
3436         /*
3437          * Drop what we picked up for L2 via svm_complete_interrupts() so it
3438          * doesn't end up in L1.
3439          */
3440         svm->vcpu.arch.nmi_injected = false;
3441         kvm_clear_exception_queue(&svm->vcpu);
3442         kvm_clear_interrupt_queue(&svm->vcpu);
3443
3444         return 0;
3445 }
3446
3447 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3448 {
3449         /*
3450          * This function merges the msr permission bitmaps of kvm and the
3451          * nested vmcb. It is optimized in that it only merges the parts where
3452          * the kvm msr permission bitmap may contain zero bits
3453          */
3454         int i;
3455
3456         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3457                 return true;
3458
3459         for (i = 0; i < MSRPM_OFFSETS; i++) {
3460                 u32 value, p;
3461                 u64 offset;
3462
3463                 if (msrpm_offsets[i] == 0xffffffff)
3464                         break;
3465
3466                 p      = msrpm_offsets[i];
3467                 offset = svm->nested.vmcb_msrpm + (p * 4);
3468
3469                 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
3470                         return false;
3471
3472                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
3473         }
3474
3475         svm->vmcb->control.msrpm_base_pa = __sme_set(__pa(svm->nested.msrpm));
3476
3477         return true;
3478 }
3479
3480 static bool nested_vmcb_checks(struct vmcb *vmcb)
3481 {
3482         if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
3483                 return false;
3484
3485         if (vmcb->control.asid == 0)
3486                 return false;
3487
3488         if ((vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) &&
3489             !npt_enabled)
3490                 return false;
3491
3492         return true;
3493 }
3494
3495 static void enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa,
3496                                  struct vmcb *nested_vmcb, struct kvm_host_map *map)
3497 {
3498         if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
3499                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
3500         else
3501                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
3502
3503         if (nested_vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) {
3504                 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
3505                 nested_svm_init_mmu_context(&svm->vcpu);
3506         }
3507
3508         /* Load the nested guest state */
3509         svm->vmcb->save.es = nested_vmcb->save.es;
3510         svm->vmcb->save.cs = nested_vmcb->save.cs;
3511         svm->vmcb->save.ss = nested_vmcb->save.ss;
3512         svm->vmcb->save.ds = nested_vmcb->save.ds;
3513         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
3514         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
3515         kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
3516         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
3517         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
3518         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
3519         if (npt_enabled) {
3520                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
3521                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
3522         } else
3523                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
3524
3525         /* Guest paging mode is active - reset mmu */
3526         kvm_mmu_reset_context(&svm->vcpu);
3527
3528         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3529         kvm_rax_write(&svm->vcpu, nested_vmcb->save.rax);
3530         kvm_rsp_write(&svm->vcpu, nested_vmcb->save.rsp);
3531         kvm_rip_write(&svm->vcpu, nested_vmcb->save.rip);
3532
3533         /* In case we don't even reach vcpu_run, the fields are not updated */
3534         svm->vmcb->save.rax = nested_vmcb->save.rax;
3535         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
3536         svm->vmcb->save.rip = nested_vmcb->save.rip;
3537         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
3538         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
3539         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
3540
3541         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
3542         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
3543
3544         /* cache intercepts */
3545         svm->nested.intercept_cr         = nested_vmcb->control.intercept_cr;
3546         svm->nested.intercept_dr         = nested_vmcb->control.intercept_dr;
3547         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
3548         svm->nested.intercept            = nested_vmcb->control.intercept;
3549
3550         svm_flush_tlb(&svm->vcpu, true);
3551         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3552         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
3553                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
3554         else
3555                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
3556
3557         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
3558                 /* We only want the cr8 intercept bits of the guest */
3559                 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
3560                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3561         }
3562
3563         /* We don't want to see VMMCALLs from a nested guest */
3564         clr_intercept(svm, INTERCEPT_VMMCALL);
3565
3566         svm->vcpu.arch.tsc_offset += nested_vmcb->control.tsc_offset;
3567         svm->vmcb->control.tsc_offset = svm->vcpu.arch.tsc_offset;
3568
3569         svm->vmcb->control.virt_ext = nested_vmcb->control.virt_ext;
3570         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
3571         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
3572         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
3573         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
3574
3575         svm->vmcb->control.pause_filter_count =
3576                 nested_vmcb->control.pause_filter_count;
3577         svm->vmcb->control.pause_filter_thresh =
3578                 nested_vmcb->control.pause_filter_thresh;
3579
3580         kvm_vcpu_unmap(&svm->vcpu, map, true);
3581
3582         /* Enter Guest-Mode */
3583         enter_guest_mode(&svm->vcpu);
3584
3585         /*
3586          * Merge guest and host intercepts - must be called  with vcpu in
3587          * guest-mode to take affect here
3588          */
3589         recalc_intercepts(svm);
3590
3591         svm->nested.vmcb = vmcb_gpa;
3592
3593         enable_gif(svm);
3594
3595         mark_all_dirty(svm->vmcb);
3596 }
3597
3598 static int nested_svm_vmrun(struct vcpu_svm *svm)
3599 {
3600         int ret;
3601         struct vmcb *nested_vmcb;
3602         struct vmcb *hsave = svm->nested.hsave;
3603         struct vmcb *vmcb = svm->vmcb;
3604         struct kvm_host_map map;
3605         u64 vmcb_gpa;
3606
3607         vmcb_gpa = svm->vmcb->save.rax;
3608
3609         ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(vmcb_gpa), &map);
3610         if (ret == -EINVAL) {
3611                 kvm_inject_gp(&svm->vcpu, 0);
3612                 return 1;
3613         } else if (ret) {
3614                 return kvm_skip_emulated_instruction(&svm->vcpu);
3615         }
3616
3617         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3618
3619         nested_vmcb = map.hva;
3620
3621         if (!nested_vmcb_checks(nested_vmcb)) {
3622                 nested_vmcb->control.exit_code    = SVM_EXIT_ERR;
3623                 nested_vmcb->control.exit_code_hi = 0;
3624                 nested_vmcb->control.exit_info_1  = 0;
3625                 nested_vmcb->control.exit_info_2  = 0;
3626
3627                 kvm_vcpu_unmap(&svm->vcpu, &map, true);
3628
3629                 return ret;
3630         }
3631
3632         trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
3633                                nested_vmcb->save.rip,
3634                                nested_vmcb->control.int_ctl,
3635                                nested_vmcb->control.event_inj,
3636                                nested_vmcb->control.nested_ctl);
3637
3638         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
3639                                     nested_vmcb->control.intercept_cr >> 16,
3640                                     nested_vmcb->control.intercept_exceptions,
3641                                     nested_vmcb->control.intercept);
3642
3643         /* Clear internal status */
3644         kvm_clear_exception_queue(&svm->vcpu);
3645         kvm_clear_interrupt_queue(&svm->vcpu);
3646
3647         /*
3648          * Save the old vmcb, so we don't need to pick what we save, but can
3649          * restore everything when a VMEXIT occurs
3650          */
3651         hsave->save.es     = vmcb->save.es;
3652         hsave->save.cs     = vmcb->save.cs;
3653         hsave->save.ss     = vmcb->save.ss;
3654         hsave->save.ds     = vmcb->save.ds;
3655         hsave->save.gdtr   = vmcb->save.gdtr;
3656         hsave->save.idtr   = vmcb->save.idtr;
3657         hsave->save.efer   = svm->vcpu.arch.efer;
3658         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
3659         hsave->save.cr4    = svm->vcpu.arch.cr4;
3660         hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
3661         hsave->save.rip    = kvm_rip_read(&svm->vcpu);
3662         hsave->save.rsp    = vmcb->save.rsp;
3663         hsave->save.rax    = vmcb->save.rax;
3664         if (npt_enabled)
3665                 hsave->save.cr3    = vmcb->save.cr3;
3666         else
3667                 hsave->save.cr3    = kvm_read_cr3(&svm->vcpu);
3668
3669         copy_vmcb_control_area(hsave, vmcb);
3670
3671         enter_svm_guest_mode(svm, vmcb_gpa, nested_vmcb, &map);
3672
3673         if (!nested_svm_vmrun_msrpm(svm)) {
3674                 svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
3675                 svm->vmcb->control.exit_code_hi = 0;
3676                 svm->vmcb->control.exit_info_1  = 0;
3677                 svm->vmcb->control.exit_info_2  = 0;
3678
3679                 nested_svm_vmexit(svm);
3680         }
3681
3682         return ret;
3683 }
3684
3685 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
3686 {
3687         to_vmcb->save.fs = from_vmcb->save.fs;
3688         to_vmcb->save.gs = from_vmcb->save.gs;
3689         to_vmcb->save.tr = from_vmcb->save.tr;
3690         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
3691         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
3692         to_vmcb->save.star = from_vmcb->save.star;
3693         to_vmcb->save.lstar = from_vmcb->save.lstar;
3694         to_vmcb->save.cstar = from_vmcb->save.cstar;
3695         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
3696         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
3697         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
3698         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
3699 }
3700
3701 static int vmload_interception(struct vcpu_svm *svm)
3702 {
3703         struct vmcb *nested_vmcb;
3704         struct kvm_host_map map;
3705         int ret;
3706
3707         if (nested_svm_check_permissions(svm))
3708                 return 1;
3709
3710         ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
3711         if (ret) {
3712                 if (ret == -EINVAL)
3713                         kvm_inject_gp(&svm->vcpu, 0);
3714                 return 1;
3715         }
3716
3717         nested_vmcb = map.hva;
3718
3719         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3720
3721         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3722         kvm_vcpu_unmap(&svm->vcpu, &map, true);
3723
3724         return ret;
3725 }
3726
3727 static int vmsave_interception(struct vcpu_svm *svm)
3728 {
3729         struct vmcb *nested_vmcb;
3730         struct kvm_host_map map;
3731         int ret;
3732
3733         if (nested_svm_check_permissions(svm))
3734                 return 1;
3735
3736         ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
3737         if (ret) {
3738                 if (ret == -EINVAL)
3739                         kvm_inject_gp(&svm->vcpu, 0);
3740                 return 1;
3741         }
3742
3743         nested_vmcb = map.hva;
3744
3745         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3746
3747         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3748         kvm_vcpu_unmap(&svm->vcpu, &map, true);
3749
3750         return ret;
3751 }
3752
3753 static int vmrun_interception(struct vcpu_svm *svm)
3754 {
3755         if (nested_svm_check_permissions(svm))
3756                 return 1;
3757
3758         return nested_svm_vmrun(svm);
3759 }
3760
3761 static int stgi_interception(struct vcpu_svm *svm)
3762 {
3763         int ret;
3764
3765         if (nested_svm_check_permissions(svm))
3766                 return 1;
3767
3768         /*
3769          * If VGIF is enabled, the STGI intercept is only added to
3770          * detect the opening of the SMI/NMI window; remove it now.
3771          */
3772         if (vgif_enabled(svm))
3773                 clr_intercept(svm, INTERCEPT_STGI);
3774
3775         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3776         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3777
3778         enable_gif(svm);
3779
3780         return ret;
3781 }
3782
3783 static int clgi_interception(struct vcpu_svm *svm)
3784 {
3785         int ret;
3786
3787         if (nested_svm_check_permissions(svm))
3788                 return 1;
3789
3790         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3791
3792         disable_gif(svm);
3793
3794         /* After a CLGI no interrupts should come */
3795         if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3796                 svm_clear_vintr(svm);
3797                 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3798                 mark_dirty(svm->vmcb, VMCB_INTR);
3799         }
3800
3801         return ret;
3802 }
3803
3804 static int invlpga_interception(struct vcpu_svm *svm)
3805 {
3806         struct kvm_vcpu *vcpu = &svm->vcpu;
3807
3808         trace_kvm_invlpga(svm->vmcb->save.rip, kvm_rcx_read(&svm->vcpu),
3809                           kvm_rax_read(&svm->vcpu));
3810
3811         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3812         kvm_mmu_invlpg(vcpu, kvm_rax_read(&svm->vcpu));
3813
3814         return kvm_skip_emulated_instruction(&svm->vcpu);
3815 }
3816
3817 static int skinit_interception(struct vcpu_svm *svm)
3818 {
3819         trace_kvm_skinit(svm->vmcb->save.rip, kvm_rax_read(&svm->vcpu));
3820
3821         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3822         return 1;
3823 }
3824
3825 static int wbinvd_interception(struct vcpu_svm *svm)
3826 {
3827         return kvm_emulate_wbinvd(&svm->vcpu);
3828 }
3829
3830 static int xsetbv_interception(struct vcpu_svm *svm)
3831 {
3832         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3833         u32 index = kvm_rcx_read(&svm->vcpu);
3834
3835         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3836                 return kvm_skip_emulated_instruction(&svm->vcpu);
3837         }
3838
3839         return 1;
3840 }
3841
3842 static int rdpru_interception(struct vcpu_svm *svm)
3843 {
3844         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3845         return 1;
3846 }
3847
3848 static int task_switch_interception(struct vcpu_svm *svm)
3849 {
3850         u16 tss_selector;
3851         int reason;
3852         int int_type = svm->vmcb->control.exit_int_info &
3853                 SVM_EXITINTINFO_TYPE_MASK;
3854         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3855         uint32_t type =
3856                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3857         uint32_t idt_v =
3858                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3859         bool has_error_code = false;
3860         u32 error_code = 0;
3861
3862         tss_selector = (u16)svm->vmcb->control.exit_info_1;
3863
3864         if (svm->vmcb->control.exit_info_2 &
3865             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3866                 reason = TASK_SWITCH_IRET;
3867         else if (svm->vmcb->control.exit_info_2 &
3868                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3869                 reason = TASK_SWITCH_JMP;
3870         else if (idt_v)
3871                 reason = TASK_SWITCH_GATE;
3872         else
3873                 reason = TASK_SWITCH_CALL;
3874
3875         if (reason == TASK_SWITCH_GATE) {
3876                 switch (type) {
3877                 case SVM_EXITINTINFO_TYPE_NMI:
3878                         svm->vcpu.arch.nmi_injected = false;
3879                         break;
3880                 case SVM_EXITINTINFO_TYPE_EXEPT:
3881                         if (svm->vmcb->control.exit_info_2 &
3882                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3883                                 has_error_code = true;
3884                                 error_code =
3885                                         (u32)svm->vmcb->control.exit_info_2;
3886                         }
3887                         kvm_clear_exception_queue(&svm->vcpu);
3888                         break;
3889                 case SVM_EXITINTINFO_TYPE_INTR:
3890                         kvm_clear_interrupt_queue(&svm->vcpu);
3891                         break;
3892                 default:
3893                         break;
3894                 }
3895         }
3896
3897         if (reason != TASK_SWITCH_GATE ||
3898             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3899             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3900              (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
3901                 if (!skip_emulated_instruction(&svm->vcpu))
3902                         return 0;
3903         }
3904
3905         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3906                 int_vec = -1;
3907
3908         return kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3909                                has_error_code, error_code);
3910 }
3911
3912 static int cpuid_interception(struct vcpu_svm *svm)
3913 {
3914         return kvm_emulate_cpuid(&svm->vcpu);
3915 }
3916
3917 static int iret_interception(struct vcpu_svm *svm)
3918 {
3919         ++svm->vcpu.stat.nmi_window_exits;
3920         clr_intercept(svm, INTERCEPT_IRET);
3921         svm->vcpu.arch.hflags |= HF_IRET_MASK;
3922         svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3923         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3924         return 1;
3925 }
3926
3927 static int invlpg_interception(struct vcpu_svm *svm)
3928 {
3929         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3930                 return kvm_emulate_instruction(&svm->vcpu, 0);
3931
3932         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3933         return kvm_skip_emulated_instruction(&svm->vcpu);
3934 }
3935
3936 static int emulate_on_interception(struct vcpu_svm *svm)
3937 {
3938         return kvm_emulate_instruction(&svm->vcpu, 0);
3939 }
3940
3941 static int rsm_interception(struct vcpu_svm *svm)
3942 {
3943         return kvm_emulate_instruction_from_buffer(&svm->vcpu, rsm_ins_bytes, 2);
3944 }
3945
3946 static int rdpmc_interception(struct vcpu_svm *svm)
3947 {
3948         int err;
3949
3950         if (!nrips)
3951                 return emulate_on_interception(svm);
3952
3953         err = kvm_rdpmc(&svm->vcpu);
3954         return kvm_complete_insn_gp(&svm->vcpu, err);
3955 }
3956
3957 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3958                                             unsigned long val)
3959 {
3960         unsigned long cr0 = svm->vcpu.arch.cr0;
3961         bool ret = false;
3962         u64 intercept;
3963
3964         intercept = svm->nested.intercept;
3965
3966         if (!is_guest_mode(&svm->vcpu) ||
3967             (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3968                 return false;
3969
3970         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3971         val &= ~SVM_CR0_SELECTIVE_MASK;
3972
3973         if (cr0 ^ val) {
3974                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3975                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3976         }
3977
3978         return ret;
3979 }
3980
3981 #define CR_VALID (1ULL << 63)
3982
3983 static int cr_interception(struct vcpu_svm *svm)
3984 {
3985         int reg, cr;
3986         unsigned long val;
3987         int err;
3988
3989         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3990                 return emulate_on_interception(svm);
3991
3992         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3993                 return emulate_on_interception(svm);
3994
3995         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3996         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3997                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3998         else
3999                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
4000
4001         err = 0;
4002         if (cr >= 16) { /* mov to cr */
4003                 cr -= 16;
4004                 val = kvm_register_read(&svm->vcpu, reg);
4005                 switch (cr) {
4006                 case 0:
4007                         if (!check_selective_cr0_intercepted(svm, val))
4008                                 err = kvm_set_cr0(&svm->vcpu, val);
4009                         else
4010                                 return 1;
4011
4012                         break;
4013                 case 3:
4014                         err = kvm_set_cr3(&svm->vcpu, val);
4015                         break;
4016                 case 4:
4017                         err = kvm_set_cr4(&svm->vcpu, val);
4018                         break;
4019                 case 8:
4020                         err = kvm_set_cr8(&svm->vcpu, val);
4021                         break;
4022                 default:
4023                         WARN(1, "unhandled write to CR%d", cr);
4024                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
4025                         return 1;
4026                 }
4027         } else { /* mov from cr */
4028                 switch (cr) {
4029                 case 0:
4030                         val = kvm_read_cr0(&svm->vcpu);
4031                         break;
4032                 case 2:
4033                         val = svm->vcpu.arch.cr2;
4034                         break;
4035                 case 3:
4036                         val = kvm_read_cr3(&svm->vcpu);
4037                         break;
4038                 case 4:
4039                         val = kvm_read_cr4(&svm->vcpu);
4040                         break;
4041                 case 8:
4042                         val = kvm_get_cr8(&svm->vcpu);
4043                         break;
4044                 default:
4045                         WARN(1, "unhandled read from CR%d", cr);
4046                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
4047                         return 1;
4048                 }
4049                 kvm_register_write(&svm->vcpu, reg, val);
4050         }
4051         return kvm_complete_insn_gp(&svm->vcpu, err);
4052 }
4053
4054 static int dr_interception(struct vcpu_svm *svm)
4055 {
4056         int reg, dr;
4057         unsigned long val;
4058
4059         if (svm->vcpu.guest_debug == 0) {
4060                 /*
4061                  * No more DR vmexits; force a reload of the debug registers
4062                  * and reenter on this instruction.  The next vmexit will
4063                  * retrieve the full state of the debug registers.
4064                  */
4065                 clr_dr_intercepts(svm);
4066                 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4067                 return 1;
4068         }
4069
4070         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
4071                 return emulate_on_interception(svm);
4072
4073         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
4074         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
4075
4076         if (dr >= 16) { /* mov to DRn */
4077                 if (!kvm_require_dr(&svm->vcpu, dr - 16))
4078                         return 1;
4079                 val = kvm_register_read(&svm->vcpu, reg);
4080                 kvm_set_dr(&svm->vcpu, dr - 16, val);
4081         } else {
4082                 if (!kvm_require_dr(&svm->vcpu, dr))
4083                         return 1;
4084                 kvm_get_dr(&svm->vcpu, dr, &val);
4085                 kvm_register_write(&svm->vcpu, reg, val);
4086         }
4087
4088         return kvm_skip_emulated_instruction(&svm->vcpu);
4089 }
4090
4091 static int cr8_write_interception(struct vcpu_svm *svm)
4092 {
4093         struct kvm_run *kvm_run = svm->vcpu.run;
4094         int r;
4095
4096         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
4097         /* instruction emulation calls kvm_set_cr8() */
4098         r = cr_interception(svm);
4099         if (lapic_in_kernel(&svm->vcpu))
4100                 return r;
4101         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
4102                 return r;
4103         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
4104         return 0;
4105 }
4106
4107 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
4108 {
4109         msr->data = 0;
4110
4111         switch (msr->index) {
4112         case MSR_F10H_DECFG:
4113                 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
4114                         msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
4115                 break;
4116         default:
4117                 return 1;
4118         }
4119
4120         return 0;
4121 }
4122
4123 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4124 {
4125         struct vcpu_svm *svm = to_svm(vcpu);
4126
4127         switch (msr_info->index) {
4128         case MSR_STAR:
4129                 msr_info->data = svm->vmcb->save.star;
4130                 break;
4131 #ifdef CONFIG_X86_64
4132         case MSR_LSTAR:
4133                 msr_info->data = svm->vmcb->save.lstar;
4134                 break;
4135         case MSR_CSTAR:
4136                 msr_info->data = svm->vmcb->save.cstar;
4137                 break;
4138         case MSR_KERNEL_GS_BASE:
4139                 msr_info->data = svm->vmcb->save.kernel_gs_base;
4140                 break;
4141         case MSR_SYSCALL_MASK:
4142                 msr_info->data = svm->vmcb->save.sfmask;
4143                 break;
4144 #endif
4145         case MSR_IA32_SYSENTER_CS:
4146                 msr_info->data = svm->vmcb->save.sysenter_cs;
4147                 break;
4148         case MSR_IA32_SYSENTER_EIP:
4149                 msr_info->data = svm->sysenter_eip;
4150                 break;
4151         case MSR_IA32_SYSENTER_ESP:
4152                 msr_info->data = svm->sysenter_esp;
4153                 break;
4154         case MSR_TSC_AUX:
4155                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4156                         return 1;
4157                 msr_info->data = svm->tsc_aux;
4158                 break;
4159         /*
4160          * Nobody will change the following 5 values in the VMCB so we can
4161          * safely return them on rdmsr. They will always be 0 until LBRV is
4162          * implemented.
4163          */
4164         case MSR_IA32_DEBUGCTLMSR:
4165                 msr_info->data = svm->vmcb->save.dbgctl;
4166                 break;
4167         case MSR_IA32_LASTBRANCHFROMIP:
4168                 msr_info->data = svm->vmcb->save.br_from;
4169                 break;
4170         case MSR_IA32_LASTBRANCHTOIP:
4171                 msr_info->data = svm->vmcb->save.br_to;
4172                 break;
4173         case MSR_IA32_LASTINTFROMIP:
4174                 msr_info->data = svm->vmcb->save.last_excp_from;
4175                 break;
4176         case MSR_IA32_LASTINTTOIP:
4177                 msr_info->data = svm->vmcb->save.last_excp_to;
4178                 break;
4179         case MSR_VM_HSAVE_PA:
4180                 msr_info->data = svm->nested.hsave_msr;
4181                 break;
4182         case MSR_VM_CR:
4183                 msr_info->data = svm->nested.vm_cr_msr;
4184                 break;
4185         case MSR_IA32_SPEC_CTRL:
4186                 if (!msr_info->host_initiated &&
4187                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
4188                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
4189                         return 1;
4190
4191                 msr_info->data = svm->spec_ctrl;
4192                 break;
4193         case MSR_AMD64_VIRT_SPEC_CTRL:
4194                 if (!msr_info->host_initiated &&
4195                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4196                         return 1;
4197
4198                 msr_info->data = svm->virt_spec_ctrl;
4199                 break;
4200         case MSR_F15H_IC_CFG: {
4201
4202                 int family, model;
4203
4204                 family = guest_cpuid_family(vcpu);
4205                 model  = guest_cpuid_model(vcpu);
4206
4207                 if (family < 0 || model < 0)
4208                         return kvm_get_msr_common(vcpu, msr_info);
4209
4210                 msr_info->data = 0;
4211
4212                 if (family == 0x15 &&
4213                     (model >= 0x2 && model < 0x20))
4214                         msr_info->data = 0x1E;
4215                 }
4216                 break;
4217         case MSR_F10H_DECFG:
4218                 msr_info->data = svm->msr_decfg;
4219                 break;
4220         default:
4221                 return kvm_get_msr_common(vcpu, msr_info);
4222         }
4223         return 0;
4224 }
4225
4226 static int rdmsr_interception(struct vcpu_svm *svm)
4227 {
4228         return kvm_emulate_rdmsr(&svm->vcpu);
4229 }
4230
4231 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
4232 {
4233         struct vcpu_svm *svm = to_svm(vcpu);
4234         int svm_dis, chg_mask;
4235
4236         if (data & ~SVM_VM_CR_VALID_MASK)
4237                 return 1;
4238
4239         chg_mask = SVM_VM_CR_VALID_MASK;
4240
4241         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
4242                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
4243
4244         svm->nested.vm_cr_msr &= ~chg_mask;
4245         svm->nested.vm_cr_msr |= (data & chg_mask);
4246
4247         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
4248
4249         /* check for svm_disable while efer.svme is set */
4250         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
4251                 return 1;
4252
4253         return 0;
4254 }
4255
4256 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
4257 {
4258         struct vcpu_svm *svm = to_svm(vcpu);
4259
4260         u32 ecx = msr->index;
4261         u64 data = msr->data;
4262         switch (ecx) {
4263         case MSR_IA32_CR_PAT:
4264                 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
4265                         return 1;
4266                 vcpu->arch.pat = data;
4267                 svm->vmcb->save.g_pat = data;
4268                 mark_dirty(svm->vmcb, VMCB_NPT);
4269                 break;
4270         case MSR_IA32_SPEC_CTRL:
4271                 if (!msr->host_initiated &&
4272                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
4273                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
4274                         return 1;
4275
4276                 /* The STIBP bit doesn't fault even if it's not advertised */
4277                 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
4278                         return 1;
4279
4280                 svm->spec_ctrl = data;
4281
4282                 if (!data)
4283                         break;
4284
4285                 /*
4286                  * For non-nested:
4287                  * When it's written (to non-zero) for the first time, pass
4288                  * it through.
4289                  *
4290                  * For nested:
4291                  * The handling of the MSR bitmap for L2 guests is done in
4292                  * nested_svm_vmrun_msrpm.
4293                  * We update the L1 MSR bit as well since it will end up
4294                  * touching the MSR anyway now.
4295                  */
4296                 set_msr_interception(svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
4297                 break;
4298         case MSR_IA32_PRED_CMD:
4299                 if (!msr->host_initiated &&
4300                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB))
4301                         return 1;
4302
4303                 if (data & ~PRED_CMD_IBPB)
4304                         return 1;
4305
4306                 if (!data)
4307                         break;
4308
4309                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
4310                 if (is_guest_mode(vcpu))
4311                         break;
4312                 set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
4313                 break;
4314         case MSR_AMD64_VIRT_SPEC_CTRL:
4315                 if (!msr->host_initiated &&
4316                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4317                         return 1;
4318
4319                 if (data & ~SPEC_CTRL_SSBD)
4320                         return 1;
4321
4322                 svm->virt_spec_ctrl = data;
4323                 break;
4324         case MSR_STAR:
4325                 svm->vmcb->save.star = data;
4326                 break;
4327 #ifdef CONFIG_X86_64
4328         case MSR_LSTAR:
4329                 svm->vmcb->save.lstar = data;
4330                 break;
4331         case MSR_CSTAR:
4332                 svm->vmcb->save.cstar = data;
4333                 break;
4334         case MSR_KERNEL_GS_BASE:
4335                 svm->vmcb->save.kernel_gs_base = data;
4336                 break;
4337         case MSR_SYSCALL_MASK:
4338                 svm->vmcb->save.sfmask = data;
4339                 break;
4340 #endif
4341         case MSR_IA32_SYSENTER_CS:
4342                 svm->vmcb->save.sysenter_cs = data;
4343                 break;
4344         case MSR_IA32_SYSENTER_EIP:
4345                 svm->sysenter_eip = data;
4346                 svm->vmcb->save.sysenter_eip = data;
4347                 break;
4348         case MSR_IA32_SYSENTER_ESP:
4349                 svm->sysenter_esp = data;
4350                 svm->vmcb->save.sysenter_esp = data;
4351                 break;
4352         case MSR_TSC_AUX:
4353                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4354                         return 1;
4355
4356                 /*
4357                  * This is rare, so we update the MSR here instead of using
4358                  * direct_access_msrs.  Doing that would require a rdmsr in
4359                  * svm_vcpu_put.
4360                  */
4361                 svm->tsc_aux = data;
4362                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
4363                 break;
4364         case MSR_IA32_DEBUGCTLMSR:
4365                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
4366                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
4367                                     __func__, data);
4368                         break;
4369                 }
4370                 if (data & DEBUGCTL_RESERVED_BITS)
4371                         return 1;
4372
4373                 svm->vmcb->save.dbgctl = data;
4374                 mark_dirty(svm->vmcb, VMCB_LBR);
4375                 if (data & (1ULL<<0))
4376                         svm_enable_lbrv(svm);
4377                 else
4378                         svm_disable_lbrv(svm);
4379                 break;
4380         case MSR_VM_HSAVE_PA:
4381                 svm->nested.hsave_msr = data;
4382                 break;
4383         case MSR_VM_CR:
4384                 return svm_set_vm_cr(vcpu, data);
4385         case MSR_VM_IGNNE:
4386                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
4387                 break;
4388         case MSR_F10H_DECFG: {
4389                 struct kvm_msr_entry msr_entry;
4390
4391                 msr_entry.index = msr->index;
4392                 if (svm_get_msr_feature(&msr_entry))
4393                         return 1;
4394
4395                 /* Check the supported bits */
4396                 if (data & ~msr_entry.data)
4397                         return 1;
4398
4399                 /* Don't allow the guest to change a bit, #GP */
4400                 if (!msr->host_initiated && (data ^ msr_entry.data))
4401                         return 1;
4402
4403                 svm->msr_decfg = data;
4404                 break;
4405         }
4406         case MSR_IA32_APICBASE:
4407                 if (kvm_vcpu_apicv_active(vcpu))
4408                         avic_update_vapic_bar(to_svm(vcpu), data);
4409                 /* Fall through */
4410         default:
4411                 return kvm_set_msr_common(vcpu, msr);
4412         }
4413         return 0;
4414 }
4415
4416 static int wrmsr_interception(struct vcpu_svm *svm)
4417 {
4418         return kvm_emulate_wrmsr(&svm->vcpu);
4419 }
4420
4421 static int msr_interception(struct vcpu_svm *svm)
4422 {
4423         if (svm->vmcb->control.exit_info_1)
4424                 return wrmsr_interception(svm);
4425         else
4426                 return rdmsr_interception(svm);
4427 }
4428
4429 static int interrupt_window_interception(struct vcpu_svm *svm)
4430 {
4431         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4432         svm_clear_vintr(svm);
4433         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
4434         mark_dirty(svm->vmcb, VMCB_INTR);
4435         ++svm->vcpu.stat.irq_window_exits;
4436         return 1;
4437 }
4438
4439 static int pause_interception(struct vcpu_svm *svm)
4440 {
4441         struct kvm_vcpu *vcpu = &svm->vcpu;
4442         bool in_kernel = (svm_get_cpl(vcpu) == 0);
4443
4444         if (pause_filter_thresh)
4445                 grow_ple_window(vcpu);
4446
4447         kvm_vcpu_on_spin(vcpu, in_kernel);
4448         return 1;
4449 }
4450
4451 static int nop_interception(struct vcpu_svm *svm)
4452 {
4453         return kvm_skip_emulated_instruction(&(svm->vcpu));
4454 }
4455
4456 static int monitor_interception(struct vcpu_svm *svm)
4457 {
4458         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
4459         return nop_interception(svm);
4460 }
4461
4462 static int mwait_interception(struct vcpu_svm *svm)
4463 {
4464         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
4465         return nop_interception(svm);
4466 }
4467
4468 enum avic_ipi_failure_cause {
4469         AVIC_IPI_FAILURE_INVALID_INT_TYPE,
4470         AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
4471         AVIC_IPI_FAILURE_INVALID_TARGET,
4472         AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
4473 };
4474
4475 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
4476 {
4477         u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
4478         u32 icrl = svm->vmcb->control.exit_info_1;
4479         u32 id = svm->vmcb->control.exit_info_2 >> 32;
4480         u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
4481         struct kvm_lapic *apic = svm->vcpu.arch.apic;
4482
4483         trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
4484
4485         switch (id) {
4486         case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
4487                 /*
4488                  * AVIC hardware handles the generation of
4489                  * IPIs when the specified Message Type is Fixed
4490                  * (also known as fixed delivery mode) and
4491                  * the Trigger Mode is edge-triggered. The hardware
4492                  * also supports self and broadcast delivery modes
4493                  * specified via the Destination Shorthand(DSH)
4494                  * field of the ICRL. Logical and physical APIC ID
4495                  * formats are supported. All other IPI types cause
4496                  * a #VMEXIT, which needs to emulated.
4497                  */
4498                 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
4499                 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
4500                 break;
4501         case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
4502                 int i;
4503                 struct kvm_vcpu *vcpu;
4504                 struct kvm *kvm = svm->vcpu.kvm;
4505                 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4506
4507                 /*
4508                  * At this point, we expect that the AVIC HW has already
4509                  * set the appropriate IRR bits on the valid target
4510                  * vcpus. So, we just need to kick the appropriate vcpu.
4511                  */
4512                 kvm_for_each_vcpu(i, vcpu, kvm) {
4513                         bool m = kvm_apic_match_dest(vcpu, apic,
4514                                                      icrl & KVM_APIC_SHORT_MASK,
4515                                                      GET_APIC_DEST_FIELD(icrh),
4516                                                      icrl & KVM_APIC_DEST_MASK);
4517
4518                         if (m && !avic_vcpu_is_running(vcpu))
4519                                 kvm_vcpu_wake_up(vcpu);
4520                 }
4521                 break;
4522         }
4523         case AVIC_IPI_FAILURE_INVALID_TARGET:
4524                 WARN_ONCE(1, "Invalid IPI target: index=%u, vcpu=%d, icr=%#0x:%#0x\n",
4525                           index, svm->vcpu.vcpu_id, icrh, icrl);
4526                 break;
4527         case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
4528                 WARN_ONCE(1, "Invalid backing page\n");
4529                 break;
4530         default:
4531                 pr_err("Unknown IPI interception\n");
4532         }
4533
4534         return 1;
4535 }
4536
4537 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
4538 {
4539         struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
4540         int index;
4541         u32 *logical_apic_id_table;
4542         int dlid = GET_APIC_LOGICAL_ID(ldr);
4543
4544         if (!dlid)
4545                 return NULL;
4546
4547         if (flat) { /* flat */
4548                 index = ffs(dlid) - 1;
4549                 if (index > 7)
4550                         return NULL;
4551         } else { /* cluster */
4552                 int cluster = (dlid & 0xf0) >> 4;
4553                 int apic = ffs(dlid & 0x0f) - 1;
4554
4555                 if ((apic < 0) || (apic > 7) ||
4556                     (cluster >= 0xf))
4557                         return NULL;
4558                 index = (cluster << 2) + apic;
4559         }
4560
4561         logical_apic_id_table = (u32 *) page_address(kvm_svm->avic_logical_id_table_page);
4562
4563         return &logical_apic_id_table[index];
4564 }
4565
4566 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr)
4567 {
4568         bool flat;
4569         u32 *entry, new_entry;
4570
4571         flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
4572         entry = avic_get_logical_id_entry(vcpu, ldr, flat);
4573         if (!entry)
4574                 return -EINVAL;
4575
4576         new_entry = READ_ONCE(*entry);
4577         new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
4578         new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
4579         new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
4580         WRITE_ONCE(*entry, new_entry);
4581
4582         return 0;
4583 }
4584
4585 static void avic_invalidate_logical_id_entry(struct kvm_vcpu *vcpu)
4586 {
4587         struct vcpu_svm *svm = to_svm(vcpu);
4588         bool flat = svm->dfr_reg == APIC_DFR_FLAT;
4589         u32 *entry = avic_get_logical_id_entry(vcpu, svm->ldr_reg, flat);
4590
4591         if (entry)
4592                 clear_bit(AVIC_LOGICAL_ID_ENTRY_VALID_BIT, (unsigned long *)entry);
4593 }
4594
4595 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
4596 {
4597         int ret = 0;
4598         struct vcpu_svm *svm = to_svm(vcpu);
4599         u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
4600         u32 id = kvm_xapic_id(vcpu->arch.apic);
4601
4602         if (ldr == svm->ldr_reg)
4603                 return 0;
4604
4605         avic_invalidate_logical_id_entry(vcpu);
4606
4607         if (ldr)
4608                 ret = avic_ldr_write(vcpu, id, ldr);
4609
4610         if (!ret)
4611                 svm->ldr_reg = ldr;
4612
4613         return ret;
4614 }
4615
4616 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
4617 {
4618         u64 *old, *new;
4619         struct vcpu_svm *svm = to_svm(vcpu);
4620         u32 id = kvm_xapic_id(vcpu->arch.apic);
4621
4622         if (vcpu->vcpu_id == id)
4623                 return 0;
4624
4625         old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
4626         new = avic_get_physical_id_entry(vcpu, id);
4627         if (!new || !old)
4628                 return 1;
4629
4630         /* We need to move physical_id_entry to new offset */
4631         *new = *old;
4632         *old = 0ULL;
4633         to_svm(vcpu)->avic_physical_id_cache = new;
4634
4635         /*
4636          * Also update the guest physical APIC ID in the logical
4637          * APIC ID table entry if already setup the LDR.
4638          */
4639         if (svm->ldr_reg)
4640                 avic_handle_ldr_update(vcpu);
4641
4642         return 0;
4643 }
4644
4645 static void avic_handle_dfr_update(struct kvm_vcpu *vcpu)
4646 {
4647         struct vcpu_svm *svm = to_svm(vcpu);
4648         u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
4649
4650         if (svm->dfr_reg == dfr)
4651                 return;
4652
4653         avic_invalidate_logical_id_entry(vcpu);
4654         svm->dfr_reg = dfr;
4655 }
4656
4657 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
4658 {
4659         struct kvm_lapic *apic = svm->vcpu.arch.apic;
4660         u32 offset = svm->vmcb->control.exit_info_1 &
4661                                 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4662
4663         switch (offset) {
4664         case APIC_ID:
4665                 if (avic_handle_apic_id_update(&svm->vcpu))
4666                         return 0;
4667                 break;
4668         case APIC_LDR:
4669                 if (avic_handle_ldr_update(&svm->vcpu))
4670                         return 0;
4671                 break;
4672         case APIC_DFR:
4673                 avic_handle_dfr_update(&svm->vcpu);
4674                 break;
4675         default:
4676                 break;
4677         }
4678
4679         kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
4680
4681         return 1;
4682 }
4683
4684 static bool is_avic_unaccelerated_access_trap(u32 offset)
4685 {
4686         bool ret = false;
4687
4688         switch (offset) {
4689         case APIC_ID:
4690         case APIC_EOI:
4691         case APIC_RRR:
4692         case APIC_LDR:
4693         case APIC_DFR:
4694         case APIC_SPIV:
4695         case APIC_ESR:
4696         case APIC_ICR:
4697         case APIC_LVTT:
4698         case APIC_LVTTHMR:
4699         case APIC_LVTPC:
4700         case APIC_LVT0:
4701         case APIC_LVT1:
4702         case APIC_LVTERR:
4703         case APIC_TMICT:
4704         case APIC_TDCR:
4705                 ret = true;
4706                 break;
4707         default:
4708                 break;
4709         }
4710         return ret;
4711 }
4712
4713 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
4714 {
4715         int ret = 0;
4716         u32 offset = svm->vmcb->control.exit_info_1 &
4717                      AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4718         u32 vector = svm->vmcb->control.exit_info_2 &
4719                      AVIC_UNACCEL_ACCESS_VECTOR_MASK;
4720         bool write = (svm->vmcb->control.exit_info_1 >> 32) &
4721                      AVIC_UNACCEL_ACCESS_WRITE_MASK;
4722         bool trap = is_avic_unaccelerated_access_trap(offset);
4723
4724         trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
4725                                             trap, write, vector);
4726         if (trap) {
4727                 /* Handling Trap */
4728                 WARN_ONCE(!write, "svm: Handling trap read.\n");
4729                 ret = avic_unaccel_trap_write(svm);
4730         } else {
4731                 /* Handling Fault */
4732                 ret = kvm_emulate_instruction(&svm->vcpu, 0);
4733         }
4734
4735         return ret;
4736 }
4737
4738 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
4739         [SVM_EXIT_READ_CR0]                     = cr_interception,
4740         [SVM_EXIT_READ_CR3]                     = cr_interception,
4741         [SVM_EXIT_READ_CR4]                     = cr_interception,
4742         [SVM_EXIT_READ_CR8]                     = cr_interception,
4743         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
4744         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
4745         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
4746         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
4747         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
4748         [SVM_EXIT_READ_DR0]                     = dr_interception,
4749         [SVM_EXIT_READ_DR1]                     = dr_interception,
4750         [SVM_EXIT_READ_DR2]                     = dr_interception,
4751         [SVM_EXIT_READ_DR3]                     = dr_interception,
4752         [SVM_EXIT_READ_DR4]                     = dr_interception,
4753         [SVM_EXIT_READ_DR5]                     = dr_interception,
4754         [SVM_EXIT_READ_DR6]                     = dr_interception,
4755         [SVM_EXIT_READ_DR7]                     = dr_interception,
4756         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
4757         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
4758         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
4759         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
4760         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
4761         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
4762         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
4763         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
4764         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
4765         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
4766         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
4767         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
4768         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
4769         [SVM_EXIT_EXCP_BASE + AC_VECTOR]        = ac_interception,
4770         [SVM_EXIT_EXCP_BASE + GP_VECTOR]        = gp_interception,
4771         [SVM_EXIT_INTR]                         = intr_interception,
4772         [SVM_EXIT_NMI]                          = nmi_interception,
4773         [SVM_EXIT_SMI]                          = nop_on_interception,
4774         [SVM_EXIT_INIT]                         = nop_on_interception,
4775         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
4776         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
4777         [SVM_EXIT_CPUID]                        = cpuid_interception,
4778         [SVM_EXIT_IRET]                         = iret_interception,
4779         [SVM_EXIT_INVD]                         = emulate_on_interception,
4780         [SVM_EXIT_PAUSE]                        = pause_interception,
4781         [SVM_EXIT_HLT]                          = halt_interception,
4782         [SVM_EXIT_INVLPG]                       = invlpg_interception,
4783         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
4784         [SVM_EXIT_IOIO]                         = io_interception,
4785         [SVM_EXIT_MSR]                          = msr_interception,
4786         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
4787         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
4788         [SVM_EXIT_VMRUN]                        = vmrun_interception,
4789         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
4790         [SVM_EXIT_VMLOAD]                       = vmload_interception,
4791         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
4792         [SVM_EXIT_STGI]                         = stgi_interception,
4793         [SVM_EXIT_CLGI]                         = clgi_interception,
4794         [SVM_EXIT_SKINIT]                       = skinit_interception,
4795         [SVM_EXIT_WBINVD]                       = wbinvd_interception,
4796         [SVM_EXIT_MONITOR]                      = monitor_interception,
4797         [SVM_EXIT_MWAIT]                        = mwait_interception,
4798         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
4799         [SVM_EXIT_RDPRU]                        = rdpru_interception,
4800         [SVM_EXIT_NPF]                          = npf_interception,
4801         [SVM_EXIT_RSM]                          = rsm_interception,
4802         [SVM_EXIT_AVIC_INCOMPLETE_IPI]          = avic_incomplete_ipi_interception,
4803         [SVM_EXIT_AVIC_UNACCELERATED_ACCESS]    = avic_unaccelerated_access_interception,
4804 };
4805
4806 static void dump_vmcb(struct kvm_vcpu *vcpu)
4807 {
4808         struct vcpu_svm *svm = to_svm(vcpu);
4809         struct vmcb_control_area *control = &svm->vmcb->control;
4810         struct vmcb_save_area *save = &svm->vmcb->save;
4811
4812         if (!dump_invalid_vmcb) {
4813                 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
4814                 return;
4815         }
4816
4817         pr_err("VMCB Control Area:\n");
4818         pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4819         pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4820         pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4821         pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4822         pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4823         pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4824         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4825         pr_err("%-20s%d\n", "pause filter threshold:",
4826                control->pause_filter_thresh);
4827         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4828         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4829         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4830         pr_err("%-20s%d\n", "asid:", control->asid);
4831         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4832         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4833         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4834         pr_err("%-20s%08x\n", "int_state:", control->int_state);
4835         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4836         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4837         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4838         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4839         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4840         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4841         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4842         pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4843         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4844         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4845         pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
4846         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4847         pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4848         pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4849         pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4850         pr_err("VMCB State Save Area:\n");
4851         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4852                "es:",
4853                save->es.selector, save->es.attrib,
4854                save->es.limit, save->es.base);
4855         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4856                "cs:",
4857                save->cs.selector, save->cs.attrib,
4858                save->cs.limit, save->cs.base);
4859         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4860                "ss:",
4861                save->ss.selector, save->ss.attrib,
4862                save->ss.limit, save->ss.base);
4863         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4864                "ds:",
4865                save->ds.selector, save->ds.attrib,
4866                save->ds.limit, save->ds.base);
4867         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4868                "fs:",
4869                save->fs.selector, save->fs.attrib,
4870                save->fs.limit, save->fs.base);
4871         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4872                "gs:",
4873                save->gs.selector, save->gs.attrib,
4874                save->gs.limit, save->gs.base);
4875         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4876                "gdtr:",
4877                save->gdtr.selector, save->gdtr.attrib,
4878                save->gdtr.limit, save->gdtr.base);
4879         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4880                "ldtr:",
4881                save->ldtr.selector, save->ldtr.attrib,
4882                save->ldtr.limit, save->ldtr.base);
4883         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4884                "idtr:",
4885                save->idtr.selector, save->idtr.attrib,
4886                save->idtr.limit, save->idtr.base);
4887         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4888                "tr:",
4889                save->tr.selector, save->tr.attrib,
4890                save->tr.limit, save->tr.base);
4891         pr_err("cpl:            %d                efer:         %016llx\n",
4892                 save->cpl, save->efer);
4893         pr_err("%-15s %016llx %-13s %016llx\n",
4894                "cr0:", save->cr0, "cr2:", save->cr2);
4895         pr_err("%-15s %016llx %-13s %016llx\n",
4896                "cr3:", save->cr3, "cr4:", save->cr4);
4897         pr_err("%-15s %016llx %-13s %016llx\n",
4898                "dr6:", save->dr6, "dr7:", save->dr7);
4899         pr_err("%-15s %016llx %-13s %016llx\n",
4900                "rip:", save->rip, "rflags:", save->rflags);
4901         pr_err("%-15s %016llx %-13s %016llx\n",
4902                "rsp:", save->rsp, "rax:", save->rax);
4903         pr_err("%-15s %016llx %-13s %016llx\n",
4904                "star:", save->star, "lstar:", save->lstar);
4905         pr_err("%-15s %016llx %-13s %016llx\n",
4906                "cstar:", save->cstar, "sfmask:", save->sfmask);
4907         pr_err("%-15s %016llx %-13s %016llx\n",
4908                "kernel_gs_base:", save->kernel_gs_base,
4909                "sysenter_cs:", save->sysenter_cs);
4910         pr_err("%-15s %016llx %-13s %016llx\n",
4911                "sysenter_esp:", save->sysenter_esp,
4912                "sysenter_eip:", save->sysenter_eip);
4913         pr_err("%-15s %016llx %-13s %016llx\n",
4914                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4915         pr_err("%-15s %016llx %-13s %016llx\n",
4916                "br_from:", save->br_from, "br_to:", save->br_to);
4917         pr_err("%-15s %016llx %-13s %016llx\n",
4918                "excp_from:", save->last_excp_from,
4919                "excp_to:", save->last_excp_to);
4920 }
4921
4922 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4923 {
4924         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4925
4926         *info1 = control->exit_info_1;
4927         *info2 = control->exit_info_2;
4928 }
4929
4930 static int handle_exit(struct kvm_vcpu *vcpu)
4931 {
4932         struct vcpu_svm *svm = to_svm(vcpu);
4933         struct kvm_run *kvm_run = vcpu->run;
4934         u32 exit_code = svm->vmcb->control.exit_code;
4935
4936         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4937
4938         if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4939                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4940         if (npt_enabled)
4941                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4942
4943         if (unlikely(svm->nested.exit_required)) {
4944                 nested_svm_vmexit(svm);
4945                 svm->nested.exit_required = false;
4946
4947                 return 1;
4948         }
4949
4950         if (is_guest_mode(vcpu)) {
4951                 int vmexit;
4952
4953                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
4954                                         svm->vmcb->control.exit_info_1,
4955                                         svm->vmcb->control.exit_info_2,
4956                                         svm->vmcb->control.exit_int_info,
4957                                         svm->vmcb->control.exit_int_info_err,
4958                                         KVM_ISA_SVM);
4959
4960                 vmexit = nested_svm_exit_special(svm);
4961
4962                 if (vmexit == NESTED_EXIT_CONTINUE)
4963                         vmexit = nested_svm_exit_handled(svm);
4964
4965                 if (vmexit == NESTED_EXIT_DONE)
4966                         return 1;
4967         }
4968
4969         svm_complete_interrupts(svm);
4970
4971         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
4972                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4973                 kvm_run->fail_entry.hardware_entry_failure_reason
4974                         = svm->vmcb->control.exit_code;
4975                 dump_vmcb(vcpu);
4976                 return 0;
4977         }
4978
4979         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
4980             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
4981             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
4982             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
4983                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
4984                        "exit_code 0x%x\n",
4985                        __func__, svm->vmcb->control.exit_int_info,
4986                        exit_code);
4987
4988         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
4989             || !svm_exit_handlers[exit_code]) {
4990                 vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%x\n", exit_code);
4991                 dump_vmcb(vcpu);
4992                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4993                 vcpu->run->internal.suberror =
4994                         KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
4995                 vcpu->run->internal.ndata = 1;
4996                 vcpu->run->internal.data[0] = exit_code;
4997                 return 0;
4998         }
4999
5000         return svm_exit_handlers[exit_code](svm);
5001 }
5002
5003 static void reload_tss(struct kvm_vcpu *vcpu)
5004 {
5005         int cpu = raw_smp_processor_id();
5006
5007         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5008         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
5009         load_TR_desc();
5010 }
5011
5012 static void pre_sev_run(struct vcpu_svm *svm, int cpu)
5013 {
5014         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5015         int asid = sev_get_asid(svm->vcpu.kvm);
5016
5017         /* Assign the asid allocated with this SEV guest */
5018         svm->vmcb->control.asid = asid;
5019
5020         /*
5021          * Flush guest TLB:
5022          *
5023          * 1) when different VMCB for the same ASID is to be run on the same host CPU.
5024          * 2) or this VMCB was executed on different host CPU in previous VMRUNs.
5025          */
5026         if (sd->sev_vmcbs[asid] == svm->vmcb &&
5027             svm->last_cpu == cpu)
5028                 return;
5029
5030         svm->last_cpu = cpu;
5031         sd->sev_vmcbs[asid] = svm->vmcb;
5032         svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5033         mark_dirty(svm->vmcb, VMCB_ASID);
5034 }
5035
5036 static void pre_svm_run(struct vcpu_svm *svm)
5037 {
5038         int cpu = raw_smp_processor_id();
5039
5040         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5041
5042         if (sev_guest(svm->vcpu.kvm))
5043                 return pre_sev_run(svm, cpu);
5044
5045         /* FIXME: handle wraparound of asid_generation */
5046         if (svm->asid_generation != sd->asid_generation)
5047                 new_asid(svm, sd);
5048 }
5049
5050 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
5051 {
5052         struct vcpu_svm *svm = to_svm(vcpu);
5053
5054         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
5055         vcpu->arch.hflags |= HF_NMI_MASK;
5056         set_intercept(svm, INTERCEPT_IRET);
5057         ++vcpu->stat.nmi_injections;
5058 }
5059
5060 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
5061 {
5062         struct vmcb_control_area *control;
5063
5064         /* The following fields are ignored when AVIC is enabled */
5065         control = &svm->vmcb->control;
5066         control->int_vector = irq;
5067         control->int_ctl &= ~V_INTR_PRIO_MASK;
5068         control->int_ctl |= V_IRQ_MASK |
5069                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
5070         mark_dirty(svm->vmcb, VMCB_INTR);
5071 }
5072
5073 static void svm_set_irq(struct kvm_vcpu *vcpu)
5074 {
5075         struct vcpu_svm *svm = to_svm(vcpu);
5076
5077         BUG_ON(!(gif_set(svm)));
5078
5079         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
5080         ++vcpu->stat.irq_injections;
5081
5082         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
5083                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
5084 }
5085
5086 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
5087 {
5088         return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
5089 }
5090
5091 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5092 {
5093         struct vcpu_svm *svm = to_svm(vcpu);
5094
5095         if (svm_nested_virtualize_tpr(vcpu) ||
5096             kvm_vcpu_apicv_active(vcpu))
5097                 return;
5098
5099         clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5100
5101         if (irr == -1)
5102                 return;
5103
5104         if (tpr >= irr)
5105                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5106 }
5107
5108 static void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
5109 {
5110         return;
5111 }
5112
5113 static bool svm_get_enable_apicv(struct kvm_vcpu *vcpu)
5114 {
5115         return avic && irqchip_split(vcpu->kvm);
5116 }
5117
5118 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
5119 {
5120 }
5121
5122 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
5123 {
5124 }
5125
5126 /* Note: Currently only used by Hyper-V. */
5127 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5128 {
5129         struct vcpu_svm *svm = to_svm(vcpu);
5130         struct vmcb *vmcb = svm->vmcb;
5131
5132         if (kvm_vcpu_apicv_active(vcpu))
5133                 vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
5134         else
5135                 vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
5136         mark_dirty(vmcb, VMCB_AVIC);
5137 }
5138
5139 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
5140 {
5141         return;
5142 }
5143
5144 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
5145 {
5146         kvm_lapic_set_irr(vec, vcpu->arch.apic);
5147         smp_mb__after_atomic();
5148
5149         if (avic_vcpu_is_running(vcpu)) {
5150                 int cpuid = vcpu->cpu;
5151
5152                 if (cpuid != get_cpu())
5153                         wrmsrl(SVM_AVIC_DOORBELL, kvm_cpu_get_apicid(cpuid));
5154                 put_cpu();
5155         } else
5156                 kvm_vcpu_wake_up(vcpu);
5157 }
5158
5159 static bool svm_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
5160 {
5161         return false;
5162 }
5163
5164 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5165 {
5166         unsigned long flags;
5167         struct amd_svm_iommu_ir *cur;
5168
5169         spin_lock_irqsave(&svm->ir_list_lock, flags);
5170         list_for_each_entry(cur, &svm->ir_list, node) {
5171                 if (cur->data != pi->ir_data)
5172                         continue;
5173                 list_del(&cur->node);
5174                 kfree(cur);
5175                 break;
5176         }
5177         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5178 }
5179
5180 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5181 {
5182         int ret = 0;
5183         unsigned long flags;
5184         struct amd_svm_iommu_ir *ir;
5185
5186         /**
5187          * In some cases, the existing irte is updaed and re-set,
5188          * so we need to check here if it's already been * added
5189          * to the ir_list.
5190          */
5191         if (pi->ir_data && (pi->prev_ga_tag != 0)) {
5192                 struct kvm *kvm = svm->vcpu.kvm;
5193                 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
5194                 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
5195                 struct vcpu_svm *prev_svm;
5196
5197                 if (!prev_vcpu) {
5198                         ret = -EINVAL;
5199                         goto out;
5200                 }
5201
5202                 prev_svm = to_svm(prev_vcpu);
5203                 svm_ir_list_del(prev_svm, pi);
5204         }
5205
5206         /**
5207          * Allocating new amd_iommu_pi_data, which will get
5208          * add to the per-vcpu ir_list.
5209          */
5210         ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL_ACCOUNT);
5211         if (!ir) {
5212                 ret = -ENOMEM;
5213                 goto out;
5214         }
5215         ir->data = pi->ir_data;
5216
5217         spin_lock_irqsave(&svm->ir_list_lock, flags);
5218         list_add(&ir->node, &svm->ir_list);
5219         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5220 out:
5221         return ret;
5222 }
5223
5224 /**
5225  * Note:
5226  * The HW cannot support posting multicast/broadcast
5227  * interrupts to a vCPU. So, we still use legacy interrupt
5228  * remapping for these kind of interrupts.
5229  *
5230  * For lowest-priority interrupts, we only support
5231  * those with single CPU as the destination, e.g. user
5232  * configures the interrupts via /proc/irq or uses
5233  * irqbalance to make the interrupts single-CPU.
5234  */
5235 static int
5236 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
5237                  struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
5238 {
5239         struct kvm_lapic_irq irq;
5240         struct kvm_vcpu *vcpu = NULL;
5241
5242         kvm_set_msi_irq(kvm, e, &irq);
5243
5244         if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) ||
5245             !kvm_irq_is_postable(&irq)) {
5246                 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
5247                          __func__, irq.vector);
5248                 return -1;
5249         }
5250
5251         pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
5252                  irq.vector);
5253         *svm = to_svm(vcpu);
5254         vcpu_info->pi_desc_addr = __sme_set(page_to_phys((*svm)->avic_backing_page));
5255         vcpu_info->vector = irq.vector;
5256
5257         return 0;
5258 }
5259
5260 /*
5261  * svm_update_pi_irte - set IRTE for Posted-Interrupts
5262  *
5263  * @kvm: kvm
5264  * @host_irq: host irq of the interrupt
5265  * @guest_irq: gsi of the interrupt
5266  * @set: set or unset PI
5267  * returns 0 on success, < 0 on failure
5268  */
5269 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
5270                               uint32_t guest_irq, bool set)
5271 {
5272         struct kvm_kernel_irq_routing_entry *e;
5273         struct kvm_irq_routing_table *irq_rt;
5274         int idx, ret = -EINVAL;
5275
5276         if (!kvm_arch_has_assigned_device(kvm) ||
5277             !irq_remapping_cap(IRQ_POSTING_CAP))
5278                 return 0;
5279
5280         pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
5281                  __func__, host_irq, guest_irq, set);
5282
5283         idx = srcu_read_lock(&kvm->irq_srcu);
5284         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
5285         WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
5286
5287         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
5288                 struct vcpu_data vcpu_info;
5289                 struct vcpu_svm *svm = NULL;
5290
5291                 if (e->type != KVM_IRQ_ROUTING_MSI)
5292                         continue;
5293
5294                 /**
5295                  * Here, we setup with legacy mode in the following cases:
5296                  * 1. When cannot target interrupt to a specific vcpu.
5297                  * 2. Unsetting posted interrupt.
5298                  * 3. APIC virtialization is disabled for the vcpu.
5299                  * 4. IRQ has incompatible delivery mode (SMI, INIT, etc)
5300                  */
5301                 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
5302                     kvm_vcpu_apicv_active(&svm->vcpu)) {
5303                         struct amd_iommu_pi_data pi;
5304
5305                         /* Try to enable guest_mode in IRTE */
5306                         pi.base = __sme_set(page_to_phys(svm->avic_backing_page) &
5307                                             AVIC_HPA_MASK);
5308                         pi.ga_tag = AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id,
5309                                                      svm->vcpu.vcpu_id);
5310                         pi.is_guest_mode = true;
5311                         pi.vcpu_data = &vcpu_info;
5312                         ret = irq_set_vcpu_affinity(host_irq, &pi);
5313
5314                         /**
5315                          * Here, we successfully setting up vcpu affinity in
5316                          * IOMMU guest mode. Now, we need to store the posted
5317                          * interrupt information in a per-vcpu ir_list so that
5318                          * we can reference to them directly when we update vcpu
5319                          * scheduling information in IOMMU irte.
5320                          */
5321                         if (!ret && pi.is_guest_mode)
5322                                 svm_ir_list_add(svm, &pi);
5323                 } else {
5324                         /* Use legacy mode in IRTE */
5325                         struct amd_iommu_pi_data pi;
5326
5327                         /**
5328                          * Here, pi is used to:
5329                          * - Tell IOMMU to use legacy mode for this interrupt.
5330                          * - Retrieve ga_tag of prior interrupt remapping data.
5331                          */
5332                         pi.is_guest_mode = false;
5333                         ret = irq_set_vcpu_affinity(host_irq, &pi);
5334
5335                         /**
5336                          * Check if the posted interrupt was previously
5337                          * setup with the guest_mode by checking if the ga_tag
5338                          * was cached. If so, we need to clean up the per-vcpu
5339                          * ir_list.
5340                          */
5341                         if (!ret && pi.prev_ga_tag) {
5342                                 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
5343                                 struct kvm_vcpu *vcpu;
5344
5345                                 vcpu = kvm_get_vcpu_by_id(kvm, id);
5346                                 if (vcpu)
5347                                         svm_ir_list_del(to_svm(vcpu), &pi);
5348                         }
5349                 }
5350
5351                 if (!ret && svm) {
5352                         trace_kvm_pi_irte_update(host_irq, svm->vcpu.vcpu_id,
5353                                                  e->gsi, vcpu_info.vector,
5354                                                  vcpu_info.pi_desc_addr, set);
5355                 }
5356
5357                 if (ret < 0) {
5358                         pr_err("%s: failed to update PI IRTE\n", __func__);
5359                         goto out;
5360                 }
5361         }
5362
5363         ret = 0;
5364 out:
5365         srcu_read_unlock(&kvm->irq_srcu, idx);
5366         return ret;
5367 }
5368
5369 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
5370 {
5371         struct vcpu_svm *svm = to_svm(vcpu);
5372         struct vmcb *vmcb = svm->vmcb;
5373         int ret;
5374         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
5375               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
5376         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
5377
5378         return ret;
5379 }
5380
5381 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
5382 {
5383         struct vcpu_svm *svm = to_svm(vcpu);
5384
5385         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
5386 }
5387
5388 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5389 {
5390         struct vcpu_svm *svm = to_svm(vcpu);
5391
5392         if (masked) {
5393                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
5394                 set_intercept(svm, INTERCEPT_IRET);
5395         } else {
5396                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
5397                 clr_intercept(svm, INTERCEPT_IRET);
5398         }
5399 }
5400
5401 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
5402 {
5403         struct vcpu_svm *svm = to_svm(vcpu);
5404         struct vmcb *vmcb = svm->vmcb;
5405         int ret;
5406
5407         if (!gif_set(svm) ||
5408              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
5409                 return 0;
5410
5411         ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
5412
5413         if (is_guest_mode(vcpu))
5414                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
5415
5416         return ret;
5417 }
5418
5419 static void enable_irq_window(struct kvm_vcpu *vcpu)
5420 {
5421         struct vcpu_svm *svm = to_svm(vcpu);
5422
5423         if (kvm_vcpu_apicv_active(vcpu))
5424                 return;
5425
5426         /*
5427          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
5428          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
5429          * get that intercept, this function will be called again though and
5430          * we'll get the vintr intercept. However, if the vGIF feature is
5431          * enabled, the STGI interception will not occur. Enable the irq
5432          * window under the assumption that the hardware will set the GIF.
5433          */
5434         if ((vgif_enabled(svm) || gif_set(svm)) && nested_svm_intr(svm)) {
5435                 svm_set_vintr(svm);
5436                 svm_inject_irq(svm, 0x0);
5437         }
5438 }
5439
5440 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5441 {
5442         struct vcpu_svm *svm = to_svm(vcpu);
5443
5444         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
5445             == HF_NMI_MASK)
5446                 return; /* IRET will cause a vm exit */
5447
5448         if (!gif_set(svm)) {
5449                 if (vgif_enabled(svm))
5450                         set_intercept(svm, INTERCEPT_STGI);
5451                 return; /* STGI will cause a vm exit */
5452         }
5453
5454         if (svm->nested.exit_required)
5455                 return; /* we're not going to run the guest yet */
5456
5457         /*
5458          * Something prevents NMI from been injected. Single step over possible
5459          * problem (IRET or exception injection or interrupt shadow)
5460          */
5461         svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
5462         svm->nmi_singlestep = true;
5463         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
5464 }
5465
5466 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
5467 {
5468         return 0;
5469 }
5470
5471 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
5472 {
5473         return 0;
5474 }
5475
5476 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
5477 {
5478         struct vcpu_svm *svm = to_svm(vcpu);
5479
5480         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
5481                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5482         else
5483                 svm->asid_generation--;
5484 }
5485
5486 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
5487 {
5488         struct vcpu_svm *svm = to_svm(vcpu);
5489
5490         invlpga(gva, svm->vmcb->control.asid);
5491 }
5492
5493 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
5494 {
5495 }
5496
5497 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
5498 {
5499         struct vcpu_svm *svm = to_svm(vcpu);
5500
5501         if (svm_nested_virtualize_tpr(vcpu))
5502                 return;
5503
5504         if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
5505                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
5506                 kvm_set_cr8(vcpu, cr8);
5507         }
5508 }
5509
5510 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
5511 {
5512         struct vcpu_svm *svm = to_svm(vcpu);
5513         u64 cr8;
5514
5515         if (svm_nested_virtualize_tpr(vcpu) ||
5516             kvm_vcpu_apicv_active(vcpu))
5517                 return;
5518
5519         cr8 = kvm_get_cr8(vcpu);
5520         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
5521         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
5522 }
5523
5524 static void svm_complete_interrupts(struct vcpu_svm *svm)
5525 {
5526         u8 vector;
5527         int type;
5528         u32 exitintinfo = svm->vmcb->control.exit_int_info;
5529         unsigned int3_injected = svm->int3_injected;
5530
5531         svm->int3_injected = 0;
5532
5533         /*
5534          * If we've made progress since setting HF_IRET_MASK, we've
5535          * executed an IRET and can allow NMI injection.
5536          */
5537         if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
5538             && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
5539                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
5540                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5541         }
5542
5543         svm->vcpu.arch.nmi_injected = false;
5544         kvm_clear_exception_queue(&svm->vcpu);
5545         kvm_clear_interrupt_queue(&svm->vcpu);
5546
5547         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
5548                 return;
5549
5550         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5551
5552         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
5553         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
5554
5555         switch (type) {
5556         case SVM_EXITINTINFO_TYPE_NMI:
5557                 svm->vcpu.arch.nmi_injected = true;
5558                 break;
5559         case SVM_EXITINTINFO_TYPE_EXEPT:
5560                 /*
5561                  * In case of software exceptions, do not reinject the vector,
5562                  * but re-execute the instruction instead. Rewind RIP first
5563                  * if we emulated INT3 before.
5564                  */
5565                 if (kvm_exception_is_soft(vector)) {
5566                         if (vector == BP_VECTOR && int3_injected &&
5567                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
5568                                 kvm_rip_write(&svm->vcpu,
5569                                               kvm_rip_read(&svm->vcpu) -
5570                                               int3_injected);
5571                         break;
5572                 }
5573                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
5574                         u32 err = svm->vmcb->control.exit_int_info_err;
5575                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
5576
5577                 } else
5578                         kvm_requeue_exception(&svm->vcpu, vector);
5579                 break;
5580         case SVM_EXITINTINFO_TYPE_INTR:
5581                 kvm_queue_interrupt(&svm->vcpu, vector, false);
5582                 break;
5583         default:
5584                 break;
5585         }
5586 }
5587
5588 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
5589 {
5590         struct vcpu_svm *svm = to_svm(vcpu);
5591         struct vmcb_control_area *control = &svm->vmcb->control;
5592
5593         control->exit_int_info = control->event_inj;
5594         control->exit_int_info_err = control->event_inj_err;
5595         control->event_inj = 0;
5596         svm_complete_interrupts(svm);
5597 }
5598
5599 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
5600 {
5601         struct vcpu_svm *svm = to_svm(vcpu);
5602
5603         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
5604         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
5605         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
5606
5607         /*
5608          * A vmexit emulation is required before the vcpu can be executed
5609          * again.
5610          */
5611         if (unlikely(svm->nested.exit_required))
5612                 return;
5613
5614         /*
5615          * Disable singlestep if we're injecting an interrupt/exception.
5616          * We don't want our modified rflags to be pushed on the stack where
5617          * we might not be able to easily reset them if we disabled NMI
5618          * singlestep later.
5619          */
5620         if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
5621                 /*
5622                  * Event injection happens before external interrupts cause a
5623                  * vmexit and interrupts are disabled here, so smp_send_reschedule
5624                  * is enough to force an immediate vmexit.
5625                  */
5626                 disable_nmi_singlestep(svm);
5627                 smp_send_reschedule(vcpu->cpu);
5628         }
5629
5630         pre_svm_run(svm);
5631
5632         sync_lapic_to_cr8(vcpu);
5633
5634         svm->vmcb->save.cr2 = vcpu->arch.cr2;
5635
5636         clgi();
5637         kvm_load_guest_xcr0(vcpu);
5638
5639         if (lapic_in_kernel(vcpu) &&
5640                 vcpu->arch.apic->lapic_timer.timer_advance_ns)
5641                 kvm_wait_lapic_expire(vcpu);
5642
5643         /*
5644          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
5645          * it's non-zero. Since vmentry is serialising on affected CPUs, there
5646          * is no need to worry about the conditional branch over the wrmsr
5647          * being speculatively taken.
5648          */
5649         x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
5650
5651         local_irq_enable();
5652
5653         asm volatile (
5654                 "push %%" _ASM_BP "; \n\t"
5655                 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
5656                 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
5657                 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
5658                 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
5659                 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
5660                 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
5661 #ifdef CONFIG_X86_64
5662                 "mov %c[r8](%[svm]),  %%r8  \n\t"
5663                 "mov %c[r9](%[svm]),  %%r9  \n\t"
5664                 "mov %c[r10](%[svm]), %%r10 \n\t"
5665                 "mov %c[r11](%[svm]), %%r11 \n\t"
5666                 "mov %c[r12](%[svm]), %%r12 \n\t"
5667                 "mov %c[r13](%[svm]), %%r13 \n\t"
5668                 "mov %c[r14](%[svm]), %%r14 \n\t"
5669                 "mov %c[r15](%[svm]), %%r15 \n\t"
5670 #endif
5671
5672                 /* Enter guest mode */
5673                 "push %%" _ASM_AX " \n\t"
5674                 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
5675                 __ex("vmload %%" _ASM_AX) "\n\t"
5676                 __ex("vmrun %%" _ASM_AX) "\n\t"
5677                 __ex("vmsave %%" _ASM_AX) "\n\t"
5678                 "pop %%" _ASM_AX " \n\t"
5679
5680                 /* Save guest registers, load host registers */
5681                 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
5682                 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
5683                 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
5684                 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
5685                 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
5686                 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
5687 #ifdef CONFIG_X86_64
5688                 "mov %%r8,  %c[r8](%[svm]) \n\t"
5689                 "mov %%r9,  %c[r9](%[svm]) \n\t"
5690                 "mov %%r10, %c[r10](%[svm]) \n\t"
5691                 "mov %%r11, %c[r11](%[svm]) \n\t"
5692                 "mov %%r12, %c[r12](%[svm]) \n\t"
5693                 "mov %%r13, %c[r13](%[svm]) \n\t"
5694                 "mov %%r14, %c[r14](%[svm]) \n\t"
5695                 "mov %%r15, %c[r15](%[svm]) \n\t"
5696                 /*
5697                 * Clear host registers marked as clobbered to prevent
5698                 * speculative use.
5699                 */
5700                 "xor %%r8d, %%r8d \n\t"
5701                 "xor %%r9d, %%r9d \n\t"
5702                 "xor %%r10d, %%r10d \n\t"
5703                 "xor %%r11d, %%r11d \n\t"
5704                 "xor %%r12d, %%r12d \n\t"
5705                 "xor %%r13d, %%r13d \n\t"
5706                 "xor %%r14d, %%r14d \n\t"
5707                 "xor %%r15d, %%r15d \n\t"
5708 #endif
5709                 "xor %%ebx, %%ebx \n\t"
5710                 "xor %%ecx, %%ecx \n\t"
5711                 "xor %%edx, %%edx \n\t"
5712                 "xor %%esi, %%esi \n\t"
5713                 "xor %%edi, %%edi \n\t"
5714                 "pop %%" _ASM_BP
5715                 :
5716                 : [svm]"a"(svm),
5717                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
5718                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
5719                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
5720                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
5721                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
5722                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
5723                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
5724 #ifdef CONFIG_X86_64
5725                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
5726                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
5727                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
5728                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
5729                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
5730                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
5731                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
5732                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
5733 #endif
5734                 : "cc", "memory"
5735 #ifdef CONFIG_X86_64
5736                 , "rbx", "rcx", "rdx", "rsi", "rdi"
5737                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
5738 #else
5739                 , "ebx", "ecx", "edx", "esi", "edi"
5740 #endif
5741                 );
5742
5743         /* Eliminate branch target predictions from guest mode */
5744         vmexit_fill_RSB();
5745
5746 #ifdef CONFIG_X86_64
5747         wrmsrl(MSR_GS_BASE, svm->host.gs_base);
5748 #else
5749         loadsegment(fs, svm->host.fs);
5750 #ifndef CONFIG_X86_32_LAZY_GS
5751         loadsegment(gs, svm->host.gs);
5752 #endif
5753 #endif
5754
5755         /*
5756          * We do not use IBRS in the kernel. If this vCPU has used the
5757          * SPEC_CTRL MSR it may have left it on; save the value and
5758          * turn it off. This is much more efficient than blindly adding
5759          * it to the atomic save/restore list. Especially as the former
5760          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
5761          *
5762          * For non-nested case:
5763          * If the L01 MSR bitmap does not intercept the MSR, then we need to
5764          * save it.
5765          *
5766          * For nested case:
5767          * If the L02 MSR bitmap does not intercept the MSR, then we need to
5768          * save it.
5769          */
5770         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
5771                 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
5772
5773         reload_tss(vcpu);
5774
5775         local_irq_disable();
5776
5777         x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
5778
5779         vcpu->arch.cr2 = svm->vmcb->save.cr2;
5780         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
5781         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
5782         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
5783
5784         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5785                 kvm_before_interrupt(&svm->vcpu);
5786
5787         kvm_put_guest_xcr0(vcpu);
5788         stgi();
5789
5790         /* Any pending NMI will happen here */
5791
5792         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5793                 kvm_after_interrupt(&svm->vcpu);
5794
5795         sync_cr8_to_lapic(vcpu);
5796
5797         svm->next_rip = 0;
5798
5799         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
5800
5801         /* if exit due to PF check for async PF */
5802         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
5803                 svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
5804
5805         if (npt_enabled) {
5806                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
5807                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
5808         }
5809
5810         /*
5811          * We need to handle MC intercepts here before the vcpu has a chance to
5812          * change the physical cpu
5813          */
5814         if (unlikely(svm->vmcb->control.exit_code ==
5815                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
5816                 svm_handle_mce(svm);
5817
5818         mark_all_clean(svm->vmcb);
5819 }
5820 STACK_FRAME_NON_STANDARD(svm_vcpu_run);
5821
5822 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5823 {
5824         struct vcpu_svm *svm = to_svm(vcpu);
5825
5826         svm->vmcb->save.cr3 = __sme_set(root);
5827         mark_dirty(svm->vmcb, VMCB_CR);
5828 }
5829
5830 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5831 {
5832         struct vcpu_svm *svm = to_svm(vcpu);
5833
5834         svm->vmcb->control.nested_cr3 = __sme_set(root);
5835         mark_dirty(svm->vmcb, VMCB_NPT);
5836
5837         /* Also sync guest cr3 here in case we live migrate */
5838         svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
5839         mark_dirty(svm->vmcb, VMCB_CR);
5840 }
5841
5842 static int is_disabled(void)
5843 {
5844         u64 vm_cr;
5845
5846         rdmsrl(MSR_VM_CR, vm_cr);
5847         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
5848                 return 1;
5849
5850         return 0;
5851 }
5852
5853 static void
5854 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5855 {
5856         /*
5857          * Patch in the VMMCALL instruction:
5858          */
5859         hypercall[0] = 0x0f;
5860         hypercall[1] = 0x01;
5861         hypercall[2] = 0xd9;
5862 }
5863
5864 static int __init svm_check_processor_compat(void)
5865 {
5866         return 0;
5867 }
5868
5869 static bool svm_cpu_has_accelerated_tpr(void)
5870 {
5871         return false;
5872 }
5873
5874 static bool svm_has_emulated_msr(int index)
5875 {
5876         switch (index) {
5877         case MSR_IA32_MCG_EXT_CTL:
5878         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
5879                 return false;
5880         default:
5881                 break;
5882         }
5883
5884         return true;
5885 }
5886
5887 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
5888 {
5889         return 0;
5890 }
5891
5892 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
5893 {
5894         struct vcpu_svm *svm = to_svm(vcpu);
5895
5896         /* Update nrips enabled cache */
5897         svm->nrips_enabled = !!guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
5898
5899         if (!kvm_vcpu_apicv_active(vcpu))
5900                 return;
5901
5902         guest_cpuid_clear(vcpu, X86_FEATURE_X2APIC);
5903 }
5904
5905 #define F(x) bit(X86_FEATURE_##x)
5906
5907 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
5908 {
5909         switch (func) {
5910         case 0x1:
5911                 if (avic)
5912                         entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5913                 break;
5914         case 0x80000001:
5915                 if (nested)
5916                         entry->ecx |= (1 << 2); /* Set SVM bit */
5917                 break;
5918         case 0x80000008:
5919                 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
5920                      boot_cpu_has(X86_FEATURE_AMD_SSBD))
5921                         entry->ebx |= F(VIRT_SSBD);
5922                 break;
5923         case 0x8000000A:
5924                 entry->eax = 1; /* SVM revision 1 */
5925                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5926                                    ASID emulation to nested SVM */
5927                 entry->ecx = 0; /* Reserved */
5928                 entry->edx = 0; /* Per default do not support any
5929                                    additional features */
5930
5931                 /* Support next_rip if host supports it */
5932                 if (boot_cpu_has(X86_FEATURE_NRIPS))
5933                         entry->edx |= F(NRIPS);
5934
5935                 /* Support NPT for the guest if enabled */
5936                 if (npt_enabled)
5937                         entry->edx |= F(NPT);
5938
5939                 break;
5940         case 0x8000001F:
5941                 /* Support memory encryption cpuid if host supports it */
5942                 if (boot_cpu_has(X86_FEATURE_SEV))
5943                         cpuid(0x8000001f, &entry->eax, &entry->ebx,
5944                                 &entry->ecx, &entry->edx);
5945
5946         }
5947 }
5948
5949 static int svm_get_lpage_level(void)
5950 {
5951         return PT_PDPE_LEVEL;
5952 }
5953
5954 static bool svm_rdtscp_supported(void)
5955 {
5956         return boot_cpu_has(X86_FEATURE_RDTSCP);
5957 }
5958
5959 static bool svm_invpcid_supported(void)
5960 {
5961         return false;
5962 }
5963
5964 static bool svm_mpx_supported(void)
5965 {
5966         return false;
5967 }
5968
5969 static bool svm_xsaves_supported(void)
5970 {
5971         return false;
5972 }
5973
5974 static bool svm_umip_emulated(void)
5975 {
5976         return false;
5977 }
5978
5979 static bool svm_pt_supported(void)
5980 {
5981         return false;
5982 }
5983
5984 static bool svm_has_wbinvd_exit(void)
5985 {
5986         return true;
5987 }
5988
5989 #define PRE_EX(exit)  { .exit_code = (exit), \
5990                         .stage = X86_ICPT_PRE_EXCEPT, }
5991 #define POST_EX(exit) { .exit_code = (exit), \
5992                         .stage = X86_ICPT_POST_EXCEPT, }
5993 #define POST_MEM(exit) { .exit_code = (exit), \
5994                         .stage = X86_ICPT_POST_MEMACCESS, }
5995
5996 static const struct __x86_intercept {
5997         u32 exit_code;
5998         enum x86_intercept_stage stage;
5999 } x86_intercept_map[] = {
6000         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
6001         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
6002         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
6003         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
6004         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
6005         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
6006         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
6007         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
6008         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
6009         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
6010         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
6011         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
6012         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
6013         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
6014         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
6015         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
6016         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
6017         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
6018         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
6019         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
6020         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
6021         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
6022         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
6023         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
6024         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
6025         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
6026         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
6027         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
6028         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
6029         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
6030         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
6031         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
6032         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
6033         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
6034         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
6035         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
6036         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
6037         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
6038         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
6039         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
6040         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
6041         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
6042         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
6043         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
6044         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
6045         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
6046         [x86_intercept_xsetbv]          = PRE_EX(SVM_EXIT_XSETBV),
6047 };
6048
6049 #undef PRE_EX
6050 #undef POST_EX
6051 #undef POST_MEM
6052
6053 static int svm_check_intercept(struct kvm_vcpu *vcpu,
6054                                struct x86_instruction_info *info,
6055                                enum x86_intercept_stage stage)
6056 {
6057         struct vcpu_svm *svm = to_svm(vcpu);
6058         int vmexit, ret = X86EMUL_CONTINUE;
6059         struct __x86_intercept icpt_info;
6060         struct vmcb *vmcb = svm->vmcb;
6061
6062         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
6063                 goto out;
6064
6065         icpt_info = x86_intercept_map[info->intercept];
6066
6067         if (stage != icpt_info.stage)
6068                 goto out;
6069
6070         switch (icpt_info.exit_code) {
6071         case SVM_EXIT_READ_CR0:
6072                 if (info->intercept == x86_intercept_cr_read)
6073                         icpt_info.exit_code += info->modrm_reg;
6074                 break;
6075         case SVM_EXIT_WRITE_CR0: {
6076                 unsigned long cr0, val;
6077                 u64 intercept;
6078
6079                 if (info->intercept == x86_intercept_cr_write)
6080                         icpt_info.exit_code += info->modrm_reg;
6081
6082                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
6083                     info->intercept == x86_intercept_clts)
6084                         break;
6085
6086                 intercept = svm->nested.intercept;
6087
6088                 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
6089                         break;
6090
6091                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
6092                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
6093
6094                 if (info->intercept == x86_intercept_lmsw) {
6095                         cr0 &= 0xfUL;
6096                         val &= 0xfUL;
6097                         /* lmsw can't clear PE - catch this here */
6098                         if (cr0 & X86_CR0_PE)
6099                                 val |= X86_CR0_PE;
6100                 }
6101
6102                 if (cr0 ^ val)
6103                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
6104
6105                 break;
6106         }
6107         case SVM_EXIT_READ_DR0:
6108         case SVM_EXIT_WRITE_DR0:
6109                 icpt_info.exit_code += info->modrm_reg;
6110                 break;
6111         case SVM_EXIT_MSR:
6112                 if (info->intercept == x86_intercept_wrmsr)
6113                         vmcb->control.exit_info_1 = 1;
6114                 else
6115                         vmcb->control.exit_info_1 = 0;
6116                 break;
6117         case SVM_EXIT_PAUSE:
6118                 /*
6119                  * We get this for NOP only, but pause
6120                  * is rep not, check this here
6121                  */
6122                 if (info->rep_prefix != REPE_PREFIX)
6123                         goto out;
6124                 break;
6125         case SVM_EXIT_IOIO: {
6126                 u64 exit_info;
6127                 u32 bytes;
6128
6129                 if (info->intercept == x86_intercept_in ||
6130                     info->intercept == x86_intercept_ins) {
6131                         exit_info = ((info->src_val & 0xffff) << 16) |
6132                                 SVM_IOIO_TYPE_MASK;
6133                         bytes = info->dst_bytes;
6134                 } else {
6135                         exit_info = (info->dst_val & 0xffff) << 16;
6136                         bytes = info->src_bytes;
6137                 }
6138
6139                 if (info->intercept == x86_intercept_outs ||
6140                     info->intercept == x86_intercept_ins)
6141                         exit_info |= SVM_IOIO_STR_MASK;
6142
6143                 if (info->rep_prefix)
6144                         exit_info |= SVM_IOIO_REP_MASK;
6145
6146                 bytes = min(bytes, 4u);
6147
6148                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
6149
6150                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
6151
6152                 vmcb->control.exit_info_1 = exit_info;
6153                 vmcb->control.exit_info_2 = info->next_rip;
6154
6155                 break;
6156         }
6157         default:
6158                 break;
6159         }
6160
6161         /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
6162         if (static_cpu_has(X86_FEATURE_NRIPS))
6163                 vmcb->control.next_rip  = info->next_rip;
6164         vmcb->control.exit_code = icpt_info.exit_code;
6165         vmexit = nested_svm_exit_handled(svm);
6166
6167         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
6168                                            : X86EMUL_CONTINUE;
6169
6170 out:
6171         return ret;
6172 }
6173
6174 static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu)
6175 {
6176
6177 }
6178
6179 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
6180 {
6181         if (pause_filter_thresh)
6182                 shrink_ple_window(vcpu);
6183 }
6184
6185 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
6186 {
6187         if (avic_handle_apic_id_update(vcpu) != 0)
6188                 return;
6189         avic_handle_dfr_update(vcpu);
6190         avic_handle_ldr_update(vcpu);
6191 }
6192
6193 static void svm_setup_mce(struct kvm_vcpu *vcpu)
6194 {
6195         /* [63:9] are reserved. */
6196         vcpu->arch.mcg_cap &= 0x1ff;
6197 }
6198
6199 static int svm_smi_allowed(struct kvm_vcpu *vcpu)
6200 {
6201         struct vcpu_svm *svm = to_svm(vcpu);
6202
6203         /* Per APM Vol.2 15.22.2 "Response to SMI" */
6204         if (!gif_set(svm))
6205                 return 0;
6206
6207         if (is_guest_mode(&svm->vcpu) &&
6208             svm->nested.intercept & (1ULL << INTERCEPT_SMI)) {
6209                 /* TODO: Might need to set exit_info_1 and exit_info_2 here */
6210                 svm->vmcb->control.exit_code = SVM_EXIT_SMI;
6211                 svm->nested.exit_required = true;
6212                 return 0;
6213         }
6214
6215         return 1;
6216 }
6217
6218 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
6219 {
6220         struct vcpu_svm *svm = to_svm(vcpu);
6221         int ret;
6222
6223         if (is_guest_mode(vcpu)) {
6224                 /* FED8h - SVM Guest */
6225                 put_smstate(u64, smstate, 0x7ed8, 1);
6226                 /* FEE0h - SVM Guest VMCB Physical Address */
6227                 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb);
6228
6229                 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
6230                 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
6231                 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
6232
6233                 ret = nested_svm_vmexit(svm);
6234                 if (ret)
6235                         return ret;
6236         }
6237         return 0;
6238 }
6239
6240 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
6241 {
6242         struct vcpu_svm *svm = to_svm(vcpu);
6243         struct vmcb *nested_vmcb;
6244         struct kvm_host_map map;
6245         u64 guest;
6246         u64 vmcb;
6247
6248         guest = GET_SMSTATE(u64, smstate, 0x7ed8);
6249         vmcb = GET_SMSTATE(u64, smstate, 0x7ee0);
6250
6251         if (guest) {
6252                 if (kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(vmcb), &map) == -EINVAL)
6253                         return 1;
6254                 nested_vmcb = map.hva;
6255                 enter_svm_guest_mode(svm, vmcb, nested_vmcb, &map);
6256         }
6257         return 0;
6258 }
6259
6260 static int enable_smi_window(struct kvm_vcpu *vcpu)
6261 {
6262         struct vcpu_svm *svm = to_svm(vcpu);
6263
6264         if (!gif_set(svm)) {
6265                 if (vgif_enabled(svm))
6266                         set_intercept(svm, INTERCEPT_STGI);
6267                 /* STGI will cause a vm exit */
6268                 return 1;
6269         }
6270         return 0;
6271 }
6272
6273 static int sev_asid_new(void)
6274 {
6275         int pos;
6276
6277         /*
6278          * SEV-enabled guest must use asid from min_sev_asid to max_sev_asid.
6279          */
6280         pos = find_next_zero_bit(sev_asid_bitmap, max_sev_asid, min_sev_asid - 1);
6281         if (pos >= max_sev_asid)
6282                 return -EBUSY;
6283
6284         set_bit(pos, sev_asid_bitmap);
6285         return pos + 1;
6286 }
6287
6288 static int sev_guest_init(struct kvm *kvm, struct kvm_sev_cmd *argp)
6289 {
6290         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6291         int asid, ret;
6292
6293         ret = -EBUSY;
6294         if (unlikely(sev->active))
6295                 return ret;
6296
6297         asid = sev_asid_new();
6298         if (asid < 0)
6299                 return ret;
6300
6301         ret = sev_platform_init(&argp->error);
6302         if (ret)
6303                 goto e_free;
6304
6305         sev->active = true;
6306         sev->asid = asid;
6307         INIT_LIST_HEAD(&sev->regions_list);
6308
6309         return 0;
6310
6311 e_free:
6312         __sev_asid_free(asid);
6313         return ret;
6314 }
6315
6316 static int sev_bind_asid(struct kvm *kvm, unsigned int handle, int *error)
6317 {
6318         struct sev_data_activate *data;
6319         int asid = sev_get_asid(kvm);
6320         int ret;
6321
6322         wbinvd_on_all_cpus();
6323
6324         ret = sev_guest_df_flush(error);
6325         if (ret)
6326                 return ret;
6327
6328         data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6329         if (!data)
6330                 return -ENOMEM;
6331
6332         /* activate ASID on the given handle */
6333         data->handle = handle;
6334         data->asid   = asid;
6335         ret = sev_guest_activate(data, error);
6336         kfree(data);
6337
6338         return ret;
6339 }
6340
6341 static int __sev_issue_cmd(int fd, int id, void *data, int *error)
6342 {
6343         struct fd f;
6344         int ret;
6345
6346         f = fdget(fd);
6347         if (!f.file)
6348                 return -EBADF;
6349
6350         ret = sev_issue_cmd_external_user(f.file, id, data, error);
6351
6352         fdput(f);
6353         return ret;
6354 }
6355
6356 static int sev_issue_cmd(struct kvm *kvm, int id, void *data, int *error)
6357 {
6358         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6359
6360         return __sev_issue_cmd(sev->fd, id, data, error);
6361 }
6362
6363 static int sev_launch_start(struct kvm *kvm, struct kvm_sev_cmd *argp)
6364 {
6365         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6366         struct sev_data_launch_start *start;
6367         struct kvm_sev_launch_start params;
6368         void *dh_blob, *session_blob;
6369         int *error = &argp->error;
6370         int ret;
6371
6372         if (!sev_guest(kvm))
6373                 return -ENOTTY;
6374
6375         if (copy_from_user(&params, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6376                 return -EFAULT;
6377
6378         start = kzalloc(sizeof(*start), GFP_KERNEL_ACCOUNT);
6379         if (!start)
6380                 return -ENOMEM;
6381
6382         dh_blob = NULL;
6383         if (params.dh_uaddr) {
6384                 dh_blob = psp_copy_user_blob(params.dh_uaddr, params.dh_len);
6385                 if (IS_ERR(dh_blob)) {
6386                         ret = PTR_ERR(dh_blob);
6387                         goto e_free;
6388                 }
6389
6390                 start->dh_cert_address = __sme_set(__pa(dh_blob));
6391                 start->dh_cert_len = params.dh_len;
6392         }
6393
6394         session_blob = NULL;
6395         if (params.session_uaddr) {
6396                 session_blob = psp_copy_user_blob(params.session_uaddr, params.session_len);
6397                 if (IS_ERR(session_blob)) {
6398                         ret = PTR_ERR(session_blob);
6399                         goto e_free_dh;
6400                 }
6401
6402                 start->session_address = __sme_set(__pa(session_blob));
6403                 start->session_len = params.session_len;
6404         }
6405
6406         start->handle = params.handle;
6407         start->policy = params.policy;
6408
6409         /* create memory encryption context */
6410         ret = __sev_issue_cmd(argp->sev_fd, SEV_CMD_LAUNCH_START, start, error);
6411         if (ret)
6412                 goto e_free_session;
6413
6414         /* Bind ASID to this guest */
6415         ret = sev_bind_asid(kvm, start->handle, error);
6416         if (ret)
6417                 goto e_free_session;
6418
6419         /* return handle to userspace */
6420         params.handle = start->handle;
6421         if (copy_to_user((void __user *)(uintptr_t)argp->data, &params, sizeof(params))) {
6422                 sev_unbind_asid(kvm, start->handle);
6423                 ret = -EFAULT;
6424                 goto e_free_session;
6425         }
6426
6427         sev->handle = start->handle;
6428         sev->fd = argp->sev_fd;
6429
6430 e_free_session:
6431         kfree(session_blob);
6432 e_free_dh:
6433         kfree(dh_blob);
6434 e_free:
6435         kfree(start);
6436         return ret;
6437 }
6438
6439 static unsigned long get_num_contig_pages(unsigned long idx,
6440                                 struct page **inpages, unsigned long npages)
6441 {
6442         unsigned long paddr, next_paddr;
6443         unsigned long i = idx + 1, pages = 1;
6444
6445         /* find the number of contiguous pages starting from idx */
6446         paddr = __sme_page_pa(inpages[idx]);
6447         while (i < npages) {
6448                 next_paddr = __sme_page_pa(inpages[i++]);
6449                 if ((paddr + PAGE_SIZE) == next_paddr) {
6450                         pages++;
6451                         paddr = next_paddr;
6452                         continue;
6453                 }
6454                 break;
6455         }
6456
6457         return pages;
6458 }
6459
6460 static int sev_launch_update_data(struct kvm *kvm, struct kvm_sev_cmd *argp)
6461 {
6462         unsigned long vaddr, vaddr_end, next_vaddr, npages, pages, size, i;
6463         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6464         struct kvm_sev_launch_update_data params;
6465         struct sev_data_launch_update_data *data;
6466         struct page **inpages;
6467         int ret;
6468
6469         if (!sev_guest(kvm))
6470                 return -ENOTTY;
6471
6472         if (copy_from_user(&params, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6473                 return -EFAULT;
6474
6475         data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6476         if (!data)
6477                 return -ENOMEM;
6478
6479         vaddr = params.uaddr;
6480         size = params.len;
6481         vaddr_end = vaddr + size;
6482
6483         /* Lock the user memory. */
6484         inpages = sev_pin_memory(kvm, vaddr, size, &npages, 1);
6485         if (!inpages) {
6486                 ret = -ENOMEM;
6487                 goto e_free;
6488         }
6489
6490         /*
6491          * The LAUNCH_UPDATE command will perform in-place encryption of the
6492          * memory content (i.e it will write the same memory region with C=1).
6493          * It's possible that the cache may contain the data with C=0, i.e.,
6494          * unencrypted so invalidate it first.
6495          */
6496         sev_clflush_pages(inpages, npages);
6497
6498         for (i = 0; vaddr < vaddr_end; vaddr = next_vaddr, i += pages) {
6499                 int offset, len;
6500
6501                 /*
6502                  * If the user buffer is not page-aligned, calculate the offset
6503                  * within the page.
6504                  */
6505                 offset = vaddr & (PAGE_SIZE - 1);
6506
6507                 /* Calculate the number of pages that can be encrypted in one go. */
6508                 pages = get_num_contig_pages(i, inpages, npages);
6509
6510                 len = min_t(size_t, ((pages * PAGE_SIZE) - offset), size);
6511
6512                 data->handle = sev->handle;
6513                 data->len = len;
6514                 data->address = __sme_page_pa(inpages[i]) + offset;
6515                 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_DATA, data, &argp->error);
6516                 if (ret)
6517                         goto e_unpin;
6518
6519                 size -= len;
6520                 next_vaddr = vaddr + len;
6521         }
6522
6523 e_unpin:
6524         /* content of memory is updated, mark pages dirty */
6525         for (i = 0; i < npages; i++) {
6526                 set_page_dirty_lock(inpages[i]);
6527                 mark_page_accessed(inpages[i]);
6528         }
6529         /* unlock the user pages */
6530         sev_unpin_memory(kvm, inpages, npages);
6531 e_free:
6532         kfree(data);
6533         return ret;
6534 }
6535
6536 static int sev_launch_measure(struct kvm *kvm, struct kvm_sev_cmd *argp)
6537 {
6538         void __user *measure = (void __user *)(uintptr_t)argp->data;
6539         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6540         struct sev_data_launch_measure *data;
6541         struct kvm_sev_launch_measure params;
6542         void __user *p = NULL;
6543         void *blob = NULL;
6544         int ret;
6545
6546         if (!sev_guest(kvm))
6547                 return -ENOTTY;
6548
6549         if (copy_from_user(&params, measure, sizeof(params)))
6550                 return -EFAULT;
6551
6552         data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6553         if (!data)
6554                 return -ENOMEM;
6555
6556         /* User wants to query the blob length */
6557         if (!params.len)
6558                 goto cmd;
6559
6560         p = (void __user *)(uintptr_t)params.uaddr;
6561         if (p) {
6562                 if (params.len > SEV_FW_BLOB_MAX_SIZE) {
6563                         ret = -EINVAL;
6564                         goto e_free;
6565                 }
6566
6567                 ret = -ENOMEM;
6568                 blob = kmalloc(params.len, GFP_KERNEL);
6569                 if (!blob)
6570                         goto e_free;
6571
6572                 data->address = __psp_pa(blob);
6573                 data->len = params.len;
6574         }
6575
6576 cmd:
6577         data->handle = sev->handle;
6578         ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_MEASURE, data, &argp->error);
6579
6580         /*
6581          * If we query the session length, FW responded with expected data.
6582          */
6583         if (!params.len)
6584                 goto done;
6585
6586         if (ret)
6587                 goto e_free_blob;
6588
6589         if (blob) {
6590                 if (copy_to_user(p, blob, params.len))
6591                         ret = -EFAULT;
6592         }
6593
6594 done:
6595         params.len = data->len;
6596         if (copy_to_user(measure, &params, sizeof(params)))
6597                 ret = -EFAULT;
6598 e_free_blob:
6599         kfree(blob);
6600 e_free:
6601         kfree(data);
6602         return ret;
6603 }
6604
6605 static int sev_launch_finish(struct kvm *kvm, struct kvm_sev_cmd *argp)
6606 {
6607         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6608         struct sev_data_launch_finish *data;
6609         int ret;
6610
6611         if (!sev_guest(kvm))
6612                 return -ENOTTY;
6613
6614         data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6615         if (!data)
6616                 return -ENOMEM;
6617
6618         data->handle = sev->handle;
6619         ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_FINISH, data, &argp->error);
6620
6621         kfree(data);
6622         return ret;
6623 }
6624
6625 static int sev_guest_status(struct kvm *kvm, struct kvm_sev_cmd *argp)
6626 {
6627         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6628         struct kvm_sev_guest_status params;
6629         struct sev_data_guest_status *data;
6630         int ret;
6631
6632         if (!sev_guest(kvm))
6633                 return -ENOTTY;
6634
6635         data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6636         if (!data)
6637                 return -ENOMEM;
6638
6639         data->handle = sev->handle;
6640         ret = sev_issue_cmd(kvm, SEV_CMD_GUEST_STATUS, data, &argp->error);
6641         if (ret)
6642                 goto e_free;
6643
6644         params.policy = data->policy;
6645         params.state = data->state;
6646         params.handle = data->handle;
6647
6648         if (copy_to_user((void __user *)(uintptr_t)argp->data, &params, sizeof(params)))
6649                 ret = -EFAULT;
6650 e_free:
6651         kfree(data);
6652         return ret;
6653 }
6654
6655 static int __sev_issue_dbg_cmd(struct kvm *kvm, unsigned long src,
6656                                unsigned long dst, int size,
6657                                int *error, bool enc)
6658 {
6659         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6660         struct sev_data_dbg *data;
6661         int ret;
6662
6663         data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6664         if (!data)
6665                 return -ENOMEM;
6666
6667         data->handle = sev->handle;
6668         data->dst_addr = dst;
6669         data->src_addr = src;
6670         data->len = size;
6671
6672         ret = sev_issue_cmd(kvm,
6673                             enc ? SEV_CMD_DBG_ENCRYPT : SEV_CMD_DBG_DECRYPT,
6674                             data, error);
6675         kfree(data);
6676         return ret;
6677 }
6678
6679 static int __sev_dbg_decrypt(struct kvm *kvm, unsigned long src_paddr,
6680                              unsigned long dst_paddr, int sz, int *err)
6681 {
6682         int offset;
6683
6684         /*
6685          * Its safe to read more than we are asked, caller should ensure that
6686          * destination has enough space.
6687          */
6688         src_paddr = round_down(src_paddr, 16);
6689         offset = src_paddr & 15;
6690         sz = round_up(sz + offset, 16);
6691
6692         return __sev_issue_dbg_cmd(kvm, src_paddr, dst_paddr, sz, err, false);
6693 }
6694
6695 static int __sev_dbg_decrypt_user(struct kvm *kvm, unsigned long paddr,
6696                                   unsigned long __user dst_uaddr,
6697                                   unsigned long dst_paddr,
6698                                   int size, int *err)
6699 {
6700         struct page *tpage = NULL;
6701         int ret, offset;
6702
6703         /* if inputs are not 16-byte then use intermediate buffer */
6704         if (!IS_ALIGNED(dst_paddr, 16) ||
6705             !IS_ALIGNED(paddr,     16) ||
6706             !IS_ALIGNED(size,      16)) {
6707                 tpage = (void *)alloc_page(GFP_KERNEL);
6708                 if (!tpage)
6709                         return -ENOMEM;
6710
6711                 dst_paddr = __sme_page_pa(tpage);
6712         }
6713
6714         ret = __sev_dbg_decrypt(kvm, paddr, dst_paddr, size, err);
6715         if (ret)
6716                 goto e_free;
6717
6718         if (tpage) {
6719                 offset = paddr & 15;
6720                 if (copy_to_user((void __user *)(uintptr_t)dst_uaddr,
6721                                  page_address(tpage) + offset, size))
6722                         ret = -EFAULT;
6723         }
6724
6725 e_free:
6726         if (tpage)
6727                 __free_page(tpage);
6728
6729         return ret;
6730 }
6731
6732 static int __sev_dbg_encrypt_user(struct kvm *kvm, unsigned long paddr,
6733                                   unsigned long __user vaddr,
6734                                   unsigned long dst_paddr,
6735                                   unsigned long __user dst_vaddr,
6736                                   int size, int *error)
6737 {
6738         struct page *src_tpage = NULL;
6739         struct page *dst_tpage = NULL;
6740         int ret, len = size;
6741
6742         /* If source buffer is not aligned then use an intermediate buffer */
6743         if (!IS_ALIGNED(vaddr, 16)) {
6744                 src_tpage = alloc_page(GFP_KERNEL);
6745                 if (!src_tpage)
6746                         return -ENOMEM;
6747
6748                 if (copy_from_user(page_address(src_tpage),
6749                                 (void __user *)(uintptr_t)vaddr, size)) {
6750                         __free_page(src_tpage);
6751                         return -EFAULT;
6752                 }
6753
6754                 paddr = __sme_page_pa(src_tpage);
6755         }
6756
6757         /*
6758          *  If destination buffer or length is not aligned then do read-modify-write:
6759          *   - decrypt destination in an intermediate buffer
6760          *   - copy the source buffer in an intermediate buffer
6761          *   - use the intermediate buffer as source buffer
6762          */
6763         if (!IS_ALIGNED(dst_vaddr, 16) || !IS_ALIGNED(size, 16)) {
6764                 int dst_offset;
6765
6766                 dst_tpage = alloc_page(GFP_KERNEL);
6767                 if (!dst_tpage) {
6768                         ret = -ENOMEM;
6769                         goto e_free;
6770                 }
6771
6772                 ret = __sev_dbg_decrypt(kvm, dst_paddr,
6773                                         __sme_page_pa(dst_tpage), size, error);
6774                 if (ret)
6775                         goto e_free;
6776
6777                 /*
6778                  *  If source is kernel buffer then use memcpy() otherwise
6779                  *  copy_from_user().
6780                  */
6781                 dst_offset = dst_paddr & 15;
6782
6783                 if (src_tpage)
6784                         memcpy(page_address(dst_tpage) + dst_offset,
6785                                page_address(src_tpage), size);
6786                 else {
6787                         if (copy_from_user(page_address(dst_tpage) + dst_offset,
6788                                            (void __user *)(uintptr_t)vaddr, size)) {
6789                                 ret = -EFAULT;
6790                                 goto e_free;
6791                         }
6792                 }
6793
6794                 paddr = __sme_page_pa(dst_tpage);
6795                 dst_paddr = round_down(dst_paddr, 16);
6796                 len = round_up(size, 16);
6797         }
6798
6799         ret = __sev_issue_dbg_cmd(kvm, paddr, dst_paddr, len, error, true);
6800
6801 e_free:
6802         if (src_tpage)
6803                 __free_page(src_tpage);
6804         if (dst_tpage)
6805                 __free_page(dst_tpage);
6806         return ret;
6807 }
6808
6809 static int sev_dbg_crypt(struct kvm *kvm, struct kvm_sev_cmd *argp, bool dec)
6810 {
6811         unsigned long vaddr, vaddr_end, next_vaddr;
6812         unsigned long dst_vaddr;
6813         struct page **src_p, **dst_p;
6814         struct kvm_sev_dbg debug;
6815         unsigned long n;
6816         unsigned int size;
6817         int ret;
6818
6819         if (!sev_guest(kvm))
6820                 return -ENOTTY;
6821
6822         if (copy_from_user(&debug, (void __user *)(uintptr_t)argp->data, sizeof(debug)))
6823                 return -EFAULT;
6824
6825         if (!debug.len || debug.src_uaddr + debug.len < debug.src_uaddr)
6826                 return -EINVAL;
6827         if (!debug.dst_uaddr)
6828                 return -EINVAL;
6829
6830         vaddr = debug.src_uaddr;
6831         size = debug.len;
6832         vaddr_end = vaddr + size;
6833         dst_vaddr = debug.dst_uaddr;
6834
6835         for (; vaddr < vaddr_end; vaddr = next_vaddr) {
6836                 int len, s_off, d_off;
6837
6838                 /* lock userspace source and destination page */
6839                 src_p = sev_pin_memory(kvm, vaddr & PAGE_MASK, PAGE_SIZE, &n, 0);
6840                 if (!src_p)
6841                         return -EFAULT;
6842
6843                 dst_p = sev_pin_memory(kvm, dst_vaddr & PAGE_MASK, PAGE_SIZE, &n, 1);
6844                 if (!dst_p) {
6845                         sev_unpin_memory(kvm, src_p, n);
6846                         return -EFAULT;
6847                 }
6848
6849                 /*
6850                  * The DBG_{DE,EN}CRYPT commands will perform {dec,en}cryption of the
6851                  * memory content (i.e it will write the same memory region with C=1).
6852                  * It's possible that the cache may contain the data with C=0, i.e.,
6853                  * unencrypted so invalidate it first.
6854                  */
6855                 sev_clflush_pages(src_p, 1);
6856                 sev_clflush_pages(dst_p, 1);
6857
6858                 /*
6859                  * Since user buffer may not be page aligned, calculate the
6860                  * offset within the page.
6861                  */
6862                 s_off = vaddr & ~PAGE_MASK;
6863                 d_off = dst_vaddr & ~PAGE_MASK;
6864                 len = min_t(size_t, (PAGE_SIZE - s_off), size);
6865
6866                 if (dec)
6867                         ret = __sev_dbg_decrypt_user(kvm,
6868                                                      __sme_page_pa(src_p[0]) + s_off,
6869                                                      dst_vaddr,
6870                                                      __sme_page_pa(dst_p[0]) + d_off,
6871                                                      len, &argp->error);
6872                 else
6873                         ret = __sev_dbg_encrypt_user(kvm,
6874                                                      __sme_page_pa(src_p[0]) + s_off,
6875                                                      vaddr,
6876                                                      __sme_page_pa(dst_p[0]) + d_off,
6877                                                      dst_vaddr,
6878                                                      len, &argp->error);
6879
6880                 sev_unpin_memory(kvm, src_p, n);
6881                 sev_unpin_memory(kvm, dst_p, n);
6882
6883                 if (ret)
6884                         goto err;
6885
6886                 next_vaddr = vaddr + len;
6887                 dst_vaddr = dst_vaddr + len;
6888                 size -= len;
6889         }
6890 err:
6891         return ret;
6892 }
6893
6894 static int sev_launch_secret(struct kvm *kvm, struct kvm_sev_cmd *argp)
6895 {
6896         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6897         struct sev_data_launch_secret *data;
6898         struct kvm_sev_launch_secret params;
6899         struct page **pages;
6900         void *blob, *hdr;
6901         unsigned long n;
6902         int ret, offset;
6903
6904         if (!sev_guest(kvm))
6905                 return -ENOTTY;
6906
6907         if (copy_from_user(&params, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6908                 return -EFAULT;
6909
6910         pages = sev_pin_memory(kvm, params.guest_uaddr, params.guest_len, &n, 1);
6911         if (!pages)
6912                 return -ENOMEM;
6913
6914         /*
6915          * The secret must be copied into contiguous memory region, lets verify
6916          * that userspace memory pages are contiguous before we issue command.
6917          */
6918         if (get_num_contig_pages(0, pages, n) != n) {
6919                 ret = -EINVAL;
6920                 goto e_unpin_memory;
6921         }
6922
6923         ret = -ENOMEM;
6924         data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6925         if (!data)
6926                 goto e_unpin_memory;
6927
6928         offset = params.guest_uaddr & (PAGE_SIZE - 1);
6929         data->guest_address = __sme_page_pa(pages[0]) + offset;
6930         data->guest_len = params.guest_len;
6931
6932         blob = psp_copy_user_blob(params.trans_uaddr, params.trans_len);
6933         if (IS_ERR(blob)) {
6934                 ret = PTR_ERR(blob);
6935                 goto e_free;
6936         }
6937
6938         data->trans_address = __psp_pa(blob);
6939         data->trans_len = params.trans_len;
6940
6941         hdr = psp_copy_user_blob(params.hdr_uaddr, params.hdr_len);
6942         if (IS_ERR(hdr)) {
6943                 ret = PTR_ERR(hdr);
6944                 goto e_free_blob;
6945         }
6946         data->hdr_address = __psp_pa(hdr);
6947         data->hdr_len = params.hdr_len;
6948
6949         data->handle = sev->handle;
6950         ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_SECRET, data, &argp->error);
6951
6952         kfree(hdr);
6953
6954 e_free_blob:
6955         kfree(blob);
6956 e_free:
6957         kfree(data);
6958 e_unpin_memory:
6959         sev_unpin_memory(kvm, pages, n);
6960         return ret;
6961 }
6962
6963 static int svm_mem_enc_op(struct kvm *kvm, void __user *argp)
6964 {
6965         struct kvm_sev_cmd sev_cmd;
6966         int r;
6967
6968         if (!svm_sev_enabled())
6969                 return -ENOTTY;
6970
6971         if (copy_from_user(&sev_cmd, argp, sizeof(struct kvm_sev_cmd)))
6972                 return -EFAULT;
6973
6974         mutex_lock(&kvm->lock);
6975
6976         switch (sev_cmd.id) {
6977         case KVM_SEV_INIT:
6978                 r = sev_guest_init(kvm, &sev_cmd);
6979                 break;
6980         case KVM_SEV_LAUNCH_START:
6981                 r = sev_launch_start(kvm, &sev_cmd);
6982                 break;
6983         case KVM_SEV_LAUNCH_UPDATE_DATA:
6984                 r = sev_launch_update_data(kvm, &sev_cmd);
6985                 break;
6986         case KVM_SEV_LAUNCH_MEASURE:
6987                 r = sev_launch_measure(kvm, &sev_cmd);
6988                 break;
6989         case KVM_SEV_LAUNCH_FINISH:
6990                 r = sev_launch_finish(kvm, &sev_cmd);
6991                 break;
6992         case KVM_SEV_GUEST_STATUS:
6993                 r = sev_guest_status(kvm, &sev_cmd);
6994                 break;
6995         case KVM_SEV_DBG_DECRYPT:
6996                 r = sev_dbg_crypt(kvm, &sev_cmd, true);
6997                 break;
6998         case KVM_SEV_DBG_ENCRYPT:
6999                 r = sev_dbg_crypt(kvm, &sev_cmd, false);
7000                 break;
7001         case KVM_SEV_LAUNCH_SECRET:
7002                 r = sev_launch_secret(kvm, &sev_cmd);
7003                 break;
7004         default:
7005                 r = -EINVAL;
7006                 goto out;
7007         }
7008
7009         if (copy_to_user(argp, &sev_cmd, sizeof(struct kvm_sev_cmd)))
7010                 r = -EFAULT;
7011
7012 out:
7013         mutex_unlock(&kvm->lock);
7014         return r;
7015 }
7016
7017 static int svm_register_enc_region(struct kvm *kvm,
7018                                    struct kvm_enc_region *range)
7019 {
7020         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
7021         struct enc_region *region;
7022         int ret = 0;
7023
7024         if (!sev_guest(kvm))
7025                 return -ENOTTY;
7026
7027         if (range->addr > ULONG_MAX || range->size > ULONG_MAX)
7028                 return -EINVAL;
7029
7030         region = kzalloc(sizeof(*region), GFP_KERNEL_ACCOUNT);
7031         if (!region)
7032                 return -ENOMEM;
7033
7034         region->pages = sev_pin_memory(kvm, range->addr, range->size, &region->npages, 1);
7035         if (!region->pages) {
7036                 ret = -ENOMEM;
7037                 goto e_free;
7038         }
7039
7040         /*
7041          * The guest may change the memory encryption attribute from C=0 -> C=1
7042          * or vice versa for this memory range. Lets make sure caches are
7043          * flushed to ensure that guest data gets written into memory with
7044          * correct C-bit.
7045          */
7046         sev_clflush_pages(region->pages, region->npages);
7047
7048         region->uaddr = range->addr;
7049         region->size = range->size;
7050
7051         mutex_lock(&kvm->lock);
7052         list_add_tail(&region->list, &sev->regions_list);
7053         mutex_unlock(&kvm->lock);
7054
7055         return ret;
7056
7057 e_free:
7058         kfree(region);
7059         return ret;
7060 }
7061
7062 static struct enc_region *
7063 find_enc_region(struct kvm *kvm, struct kvm_enc_region *range)
7064 {
7065         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
7066         struct list_head *head = &sev->regions_list;
7067         struct enc_region *i;
7068
7069         list_for_each_entry(i, head, list) {
7070                 if (i->uaddr == range->addr &&
7071                     i->size == range->size)
7072                         return i;
7073         }
7074
7075         return NULL;
7076 }
7077
7078
7079 static int svm_unregister_enc_region(struct kvm *kvm,
7080                                      struct kvm_enc_region *range)
7081 {
7082         struct enc_region *region;
7083         int ret;
7084
7085         mutex_lock(&kvm->lock);
7086
7087         if (!sev_guest(kvm)) {
7088                 ret = -ENOTTY;
7089                 goto failed;
7090         }
7091
7092         region = find_enc_region(kvm, range);
7093         if (!region) {
7094                 ret = -EINVAL;
7095                 goto failed;
7096         }
7097
7098         __unregister_enc_region_locked(kvm, region);
7099
7100         mutex_unlock(&kvm->lock);
7101         return 0;
7102
7103 failed:
7104         mutex_unlock(&kvm->lock);
7105         return ret;
7106 }
7107
7108 static bool svm_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7109 {
7110         unsigned long cr4 = kvm_read_cr4(vcpu);
7111         bool smep = cr4 & X86_CR4_SMEP;
7112         bool smap = cr4 & X86_CR4_SMAP;
7113         bool is_user = svm_get_cpl(vcpu) == 3;
7114
7115         /*
7116          * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
7117          *
7118          * Errata:
7119          * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is
7120          * possible that CPU microcode implementing DecodeAssist will fail
7121          * to read bytes of instruction which caused #NPF. In this case,
7122          * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly
7123          * return 0 instead of the correct guest instruction bytes.
7124          *
7125          * This happens because CPU microcode reading instruction bytes
7126          * uses a special opcode which attempts to read data using CPL=0
7127          * priviledges. The microcode reads CS:RIP and if it hits a SMAP
7128          * fault, it gives up and returns no instruction bytes.
7129          *
7130          * Detection:
7131          * We reach here in case CPU supports DecodeAssist, raised #NPF and
7132          * returned 0 in GuestIntrBytes field of the VMCB.
7133          * First, errata can only be triggered in case vCPU CR4.SMAP=1.
7134          * Second, if vCPU CR4.SMEP=1, errata could only be triggered
7135          * in case vCPU CPL==3 (Because otherwise guest would have triggered
7136          * a SMEP fault instead of #NPF).
7137          * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL.
7138          * As most guests enable SMAP if they have also enabled SMEP, use above
7139          * logic in order to attempt minimize false-positive of detecting errata
7140          * while still preserving all cases semantic correctness.
7141          *
7142          * Workaround:
7143          * To determine what instruction the guest was executing, the hypervisor
7144          * will have to decode the instruction at the instruction pointer.
7145          *
7146          * In non SEV guest, hypervisor will be able to read the guest
7147          * memory to decode the instruction pointer when insn_len is zero
7148          * so we return true to indicate that decoding is possible.
7149          *
7150          * But in the SEV guest, the guest memory is encrypted with the
7151          * guest specific key and hypervisor will not be able to decode the
7152          * instruction pointer so we will not able to workaround it. Lets
7153          * print the error and request to kill the guest.
7154          */
7155         if (smap && (!smep || is_user)) {
7156                 if (!sev_guest(vcpu->kvm))
7157                         return true;
7158
7159                 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
7160                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7161         }
7162
7163         return false;
7164 }
7165
7166 static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7167 {
7168         struct vcpu_svm *svm = to_svm(vcpu);
7169
7170         /*
7171          * TODO: Last condition latch INIT signals on vCPU when
7172          * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
7173          * To properly emulate the INIT intercept, SVM should implement
7174          * kvm_x86_ops->check_nested_events() and call nested_svm_vmexit()
7175          * there if an INIT signal is pending.
7176          */
7177         return !gif_set(svm) ||
7178                    (svm->vmcb->control.intercept & (1ULL << INTERCEPT_INIT));
7179 }
7180
7181 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
7182         .cpu_has_kvm_support = has_svm,
7183         .disabled_by_bios = is_disabled,
7184         .hardware_setup = svm_hardware_setup,
7185         .hardware_unsetup = svm_hardware_unsetup,
7186         .check_processor_compatibility = svm_check_processor_compat,
7187         .hardware_enable = svm_hardware_enable,
7188         .hardware_disable = svm_hardware_disable,
7189         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
7190         .has_emulated_msr = svm_has_emulated_msr,
7191
7192         .vcpu_create = svm_create_vcpu,
7193         .vcpu_free = svm_free_vcpu,
7194         .vcpu_reset = svm_vcpu_reset,
7195
7196         .vm_alloc = svm_vm_alloc,
7197         .vm_free = svm_vm_free,
7198         .vm_init = avic_vm_init,
7199         .vm_destroy = svm_vm_destroy,
7200
7201         .prepare_guest_switch = svm_prepare_guest_switch,
7202         .vcpu_load = svm_vcpu_load,
7203         .vcpu_put = svm_vcpu_put,
7204         .vcpu_blocking = svm_vcpu_blocking,
7205         .vcpu_unblocking = svm_vcpu_unblocking,
7206
7207         .update_bp_intercept = update_bp_intercept,
7208         .get_msr_feature = svm_get_msr_feature,
7209         .get_msr = svm_get_msr,
7210         .set_msr = svm_set_msr,
7211         .get_segment_base = svm_get_segment_base,
7212         .get_segment = svm_get_segment,
7213         .set_segment = svm_set_segment,
7214         .get_cpl = svm_get_cpl,
7215         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
7216         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
7217         .decache_cr3 = svm_decache_cr3,
7218         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
7219         .set_cr0 = svm_set_cr0,
7220         .set_cr3 = svm_set_cr3,
7221         .set_cr4 = svm_set_cr4,
7222         .set_efer = svm_set_efer,
7223         .get_idt = svm_get_idt,
7224         .set_idt = svm_set_idt,
7225         .get_gdt = svm_get_gdt,
7226         .set_gdt = svm_set_gdt,
7227         .get_dr6 = svm_get_dr6,
7228         .set_dr6 = svm_set_dr6,
7229         .set_dr7 = svm_set_dr7,
7230         .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
7231         .cache_reg = svm_cache_reg,
7232         .get_rflags = svm_get_rflags,
7233         .set_rflags = svm_set_rflags,
7234
7235         .tlb_flush = svm_flush_tlb,
7236         .tlb_flush_gva = svm_flush_tlb_gva,
7237
7238         .run = svm_vcpu_run,
7239         .handle_exit = handle_exit,
7240         .skip_emulated_instruction = skip_emulated_instruction,
7241         .set_interrupt_shadow = svm_set_interrupt_shadow,
7242         .get_interrupt_shadow = svm_get_interrupt_shadow,
7243         .patch_hypercall = svm_patch_hypercall,
7244         .set_irq = svm_set_irq,
7245         .set_nmi = svm_inject_nmi,
7246         .queue_exception = svm_queue_exception,
7247         .cancel_injection = svm_cancel_injection,
7248         .interrupt_allowed = svm_interrupt_allowed,
7249         .nmi_allowed = svm_nmi_allowed,
7250         .get_nmi_mask = svm_get_nmi_mask,
7251         .set_nmi_mask = svm_set_nmi_mask,
7252         .enable_nmi_window = enable_nmi_window,
7253         .enable_irq_window = enable_irq_window,
7254         .update_cr8_intercept = update_cr8_intercept,
7255         .set_virtual_apic_mode = svm_set_virtual_apic_mode,
7256         .get_enable_apicv = svm_get_enable_apicv,
7257         .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
7258         .load_eoi_exitmap = svm_load_eoi_exitmap,
7259         .hwapic_irr_update = svm_hwapic_irr_update,
7260         .hwapic_isr_update = svm_hwapic_isr_update,
7261         .sync_pir_to_irr = kvm_lapic_find_highest_irr,
7262         .apicv_post_state_restore = avic_post_state_restore,
7263
7264         .set_tss_addr = svm_set_tss_addr,
7265         .set_identity_map_addr = svm_set_identity_map_addr,
7266         .get_tdp_level = get_npt_level,
7267         .get_mt_mask = svm_get_mt_mask,
7268
7269         .get_exit_info = svm_get_exit_info,
7270
7271         .get_lpage_level = svm_get_lpage_level,
7272
7273         .cpuid_update = svm_cpuid_update,
7274
7275         .rdtscp_supported = svm_rdtscp_supported,
7276         .invpcid_supported = svm_invpcid_supported,
7277         .mpx_supported = svm_mpx_supported,
7278         .xsaves_supported = svm_xsaves_supported,
7279         .umip_emulated = svm_umip_emulated,
7280         .pt_supported = svm_pt_supported,
7281
7282         .set_supported_cpuid = svm_set_supported_cpuid,
7283
7284         .has_wbinvd_exit = svm_has_wbinvd_exit,
7285
7286         .read_l1_tsc_offset = svm_read_l1_tsc_offset,
7287         .write_l1_tsc_offset = svm_write_l1_tsc_offset,
7288
7289         .set_tdp_cr3 = set_tdp_cr3,
7290
7291         .check_intercept = svm_check_intercept,
7292         .handle_exit_irqoff = svm_handle_exit_irqoff,
7293
7294         .request_immediate_exit = __kvm_request_immediate_exit,
7295
7296         .sched_in = svm_sched_in,
7297
7298         .pmu_ops = &amd_pmu_ops,
7299         .deliver_posted_interrupt = svm_deliver_avic_intr,
7300         .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt,
7301         .update_pi_irte = svm_update_pi_irte,
7302         .setup_mce = svm_setup_mce,
7303
7304         .smi_allowed = svm_smi_allowed,
7305         .pre_enter_smm = svm_pre_enter_smm,
7306         .pre_leave_smm = svm_pre_leave_smm,
7307         .enable_smi_window = enable_smi_window,
7308
7309         .mem_enc_op = svm_mem_enc_op,
7310         .mem_enc_reg_region = svm_register_enc_region,
7311         .mem_enc_unreg_region = svm_unregister_enc_region,
7312
7313         .nested_enable_evmcs = NULL,
7314         .nested_get_evmcs_version = NULL,
7315
7316         .need_emulation_on_page_fault = svm_need_emulation_on_page_fault,
7317
7318         .apic_init_signal_blocked = svm_apic_init_signal_blocked,
7319 };
7320
7321 static int __init svm_init(void)
7322 {
7323         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
7324                         __alignof__(struct vcpu_svm), THIS_MODULE);
7325 }
7326
7327 static void __exit svm_exit(void)
7328 {
7329         kvm_exit();
7330 }
7331
7332 module_init(svm_init)
7333 module_exit(svm_exit)