arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   8  *
   9  * Authors:
  10  *   Yaniv Kamay  <yaniv@qumranet.com>
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17 #include <linux/kvm_host.h>
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "kvm_cache_regs.h"
  22 #include "x86.h"
  23
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/vmalloc.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/ftrace_event.h>
  30 #include <linux/slab.h>
  31
  32 #include <asm/tlbflush.h>
  33 #include <asm/desc.h>
  34 #include <asm/kvm_para.h>
  35
  36 #include <asm/virtext.h>
  37 #include "trace.h"
  38
  39 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  40
  41 MODULE_AUTHOR("Qumranet");
  42 MODULE_LICENSE("GPL");
  43
  44 #define IOPM_ALLOC_ORDER 2
  45 #define MSRPM_ALLOC_ORDER 1
  46
  47 #define SEG_TYPE_LDT 2
  48 #define SEG_TYPE_BUSY_TSS16 3
  49
  50 #define SVM_FEATURE_NPT            (1 <<  0)
  51 #define SVM_FEATURE_LBRV           (1 <<  1)
  52 #define SVM_FEATURE_SVML           (1 <<  2)
  53 #define SVM_FEATURE_NRIP           (1 <<  3)
  54 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  55 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  56 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  57 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  58 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  59
  60 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  61 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  62 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  63
  64 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  65
  66 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  67 #define TSC_RATIO_MIN           0x0000000000000001ULL
  68 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  69
  70 static bool erratum_383_found __read_mostly;
  71
  72 static const u32 host_save_user_msrs[] = {
  73 #ifdef CONFIG_X86_64
  74         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  75         MSR_FS_BASE,
  76 #endif
  77         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  78 };
  79
  80 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  81
  82 struct kvm_vcpu;
  83
  84 struct nested_state {
  85         struct vmcb *hsave;
  86         u64 hsave_msr;
  87         u64 vm_cr_msr;
  88         u64 vmcb;
  89
  90         /* These are the merged vectors */
  91         u32 *msrpm;
  92
  93         /* gpa pointers to the real vectors */
  94         u64 vmcb_msrpm;
  95         u64 vmcb_iopm;
  96
  97         /* A VMEXIT is required but not yet emulated */
  98         bool exit_required;
  99
 100         /* cache for intercepts of the guest */
 101         u32 intercept_cr;
 102         u32 intercept_dr;
 103         u32 intercept_exceptions;
 104         u64 intercept;
 105
 106         /* Nested Paging related state */
 107         u64 nested_cr3;
 108 };
 109
 110 #define MSRPM_OFFSETS   16
 111 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 112
 113 struct vcpu_svm {
 114         struct kvm_vcpu vcpu;
 115         struct vmcb *vmcb;
 116         unsigned long vmcb_pa;
 117         struct svm_cpu_data *svm_data;
 118         uint64_t asid_generation;
 119         uint64_t sysenter_esp;
 120         uint64_t sysenter_eip;
 121
 122         u64 next_rip;
 123
 124         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 125         struct {
 126                 u16 fs;
 127                 u16 gs;
 128                 u16 ldt;
 129                 u64 gs_base;
 130         } host;
 131
 132         u32 *msrpm;
 133
 134         ulong nmi_iret_rip;
 135
 136         struct nested_state nested;
 137
 138         bool nmi_singlestep;
 139
 140         unsigned int3_injected;
 141         unsigned long int3_rip;
 142         u32 apf_reason;
 143
 144         u64  tsc_ratio;
 145 };
 146
 147 static DEFINE_PER_CPU(u64, current_tsc_ratio);
 148 #define TSC_RATIO_DEFAULT       0x0100000000ULL
 149
 150 #define MSR_INVALID                     0xffffffffU
 151
 152 static struct svm_direct_access_msrs {
 153         u32 index;   /* Index of the MSR */
 154         bool always; /* True if intercept is always on */
 155 } direct_access_msrs[] = {
 156         { .index = MSR_STAR,                            .always = true  },
 157         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 158 #ifdef CONFIG_X86_64
 159         { .index = MSR_GS_BASE,                         .always = true  },
 160         { .index = MSR_FS_BASE,                         .always = true  },
 161         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 162         { .index = MSR_LSTAR,                           .always = true  },
 163         { .index = MSR_CSTAR,                           .always = true  },
 164         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 165 #endif
 166         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 167         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 168         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 169         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 170         { .index = MSR_INVALID,                         .always = false },
 171 };
 172
 173 /* enable NPT for AMD64 and X86 with PAE */
 174 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 175 static bool npt_enabled = true;
 176 #else
 177 static bool npt_enabled;
 178 #endif
 179 static int npt = 1;
 180
 181 module_param(npt, int, S_IRUGO);
 182
 183 static int nested = 1;
 184 module_param(nested, int, S_IRUGO);
 185
 186 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 187 static void svm_complete_interrupts(struct vcpu_svm *svm);
 188
 189 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 190 static int nested_svm_intercept(struct vcpu_svm *svm);
 191 static int nested_svm_vmexit(struct vcpu_svm *svm);
 192 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 193                                       bool has_error_code, u32 error_code);
 194 static u64 __scale_tsc(u64 ratio, u64 tsc);
 195
 196 enum {
 197         VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
 198                             pause filter count */
 199         VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
 200         VMCB_ASID,       /* ASID */
 201         VMCB_INTR,       /* int_ctl, int_vector */
 202         VMCB_NPT,        /* npt_en, nCR3, gPAT */
 203         VMCB_CR,         /* CR0, CR3, CR4, EFER */
 204         VMCB_DR,         /* DR6, DR7 */
 205         VMCB_DT,         /* GDT, IDT */
 206         VMCB_SEG,        /* CS, DS, SS, ES, CPL */
 207         VMCB_CR2,        /* CR2 only */
 208         VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
 209         VMCB_DIRTY_MAX,
 210 };
 211
 212 /* TPR and CR2 are always written before VMRUN */
 213 #define VMCB_ALWAYS_DIRTY_MASK  ((1U << VMCB_INTR) | (1U << VMCB_CR2))
 214
 215 static inline void mark_all_dirty(struct vmcb *vmcb)
 216 {
 217         vmcb->control.clean = 0;
 218 }
 219
 220 static inline void mark_all_clean(struct vmcb *vmcb)
 221 {
 222         vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
 223                                & ~VMCB_ALWAYS_DIRTY_MASK;
 224 }
 225
 226 static inline void mark_dirty(struct vmcb *vmcb, int bit)
 227 {
 228         vmcb->control.clean &= ~(1 << bit);
 229 }
 230
 231 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 232 {
 233         return container_of(vcpu, struct vcpu_svm, vcpu);
 234 }
 235
 236 static void recalc_intercepts(struct vcpu_svm *svm)
 237 {
 238         struct vmcb_control_area *c, *h;
 239         struct nested_state *g;
 240
 241         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 242
 243         if (!is_guest_mode(&svm->vcpu))
 244                 return;
 245
 246         c = &svm->vmcb->control;
 247         h = &svm->nested.hsave->control;
 248         g = &svm->nested;
 249
 250         c->intercept_cr = h->intercept_cr | g->intercept_cr;
 251         c->intercept_dr = h->intercept_dr | g->intercept_dr;
 252         c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
 253         c->intercept = h->intercept | g->intercept;
 254 }
 255
 256 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
 257 {
 258         if (is_guest_mode(&svm->vcpu))
 259                 return svm->nested.hsave;
 260         else
 261                 return svm->vmcb;
 262 }
 263
 264 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
 265 {
 266         struct vmcb *vmcb = get_host_vmcb(svm);
 267
 268         vmcb->control.intercept_cr |= (1U << bit);
 269
 270         recalc_intercepts(svm);
 271 }
 272
 273 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
 274 {
 275         struct vmcb *vmcb = get_host_vmcb(svm);
 276
 277         vmcb->control.intercept_cr &= ~(1U << bit);
 278
 279         recalc_intercepts(svm);
 280 }
 281
 282 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
 283 {
 284         struct vmcb *vmcb = get_host_vmcb(svm);
 285
 286         return vmcb->control.intercept_cr & (1U << bit);
 287 }
 288
 289 static inline void set_dr_intercept(struct vcpu_svm *svm, int bit)
 290 {
 291         struct vmcb *vmcb = get_host_vmcb(svm);
 292
 293         vmcb->control.intercept_dr |= (1U << bit);
 294
 295         recalc_intercepts(svm);
 296 }
 297
 298 static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit)
 299 {
 300         struct vmcb *vmcb = get_host_vmcb(svm);
 301
 302         vmcb->control.intercept_dr &= ~(1U << bit);
 303
 304         recalc_intercepts(svm);
 305 }
 306
 307 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
 308 {
 309         struct vmcb *vmcb = get_host_vmcb(svm);
 310
 311         vmcb->control.intercept_exceptions |= (1U << bit);
 312
 313         recalc_intercepts(svm);
 314 }
 315
 316 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
 317 {
 318         struct vmcb *vmcb = get_host_vmcb(svm);
 319
 320         vmcb->control.intercept_exceptions &= ~(1U << bit);
 321
 322         recalc_intercepts(svm);
 323 }
 324
 325 static inline void set_intercept(struct vcpu_svm *svm, int bit)
 326 {
 327         struct vmcb *vmcb = get_host_vmcb(svm);
 328
 329         vmcb->control.intercept |= (1ULL << bit);
 330
 331         recalc_intercepts(svm);
 332 }
 333
 334 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
 335 {
 336         struct vmcb *vmcb = get_host_vmcb(svm);
 337
 338         vmcb->control.intercept &= ~(1ULL << bit);
 339
 340         recalc_intercepts(svm);
 341 }
 342
 343 static inline void enable_gif(struct vcpu_svm *svm)
 344 {
 345         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 346 }
 347
 348 static inline void disable_gif(struct vcpu_svm *svm)
 349 {
 350         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 351 }
 352
 353 static inline bool gif_set(struct vcpu_svm *svm)
 354 {
 355         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 356 }
 357
 358 static unsigned long iopm_base;
 359
 360 struct kvm_ldttss_desc {
 361         u16 limit0;
 362         u16 base0;
 363         unsigned base1:8, type:5, dpl:2, p:1;
 364         unsigned limit1:4, zero0:3, g:1, base2:8;
 365         u32 base3;
 366         u32 zero1;
 367 } __attribute__((packed));
 368
 369 struct svm_cpu_data {
 370         int cpu;
 371
 372         u64 asid_generation;
 373         u32 max_asid;
 374         u32 next_asid;
 375         struct kvm_ldttss_desc *tss_desc;
 376
 377         struct page *save_area;
 378 };
 379
 380 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 381
 382 struct svm_init_data {
 383         int cpu;
 384         int r;
 385 };
 386
 387 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 388
 389 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 390 #define MSRS_RANGE_SIZE 2048
 391 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 392
 393 static u32 svm_msrpm_offset(u32 msr)
 394 {
 395         u32 offset;
 396         int i;
 397
 398         for (i = 0; i < NUM_MSR_MAPS; i++) {
 399                 if (msr < msrpm_ranges[i] ||
 400                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 401                         continue;
 402
 403                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 404                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 405
 406                 /* Now we have the u8 offset - but need the u32 offset */
 407                 return offset / 4;
 408         }
 409
 410         /* MSR not in any range */
 411         return MSR_INVALID;
 412 }
 413
 414 #define MAX_INST_SIZE 15
 415
 416 static inline void clgi(void)
 417 {
 418         asm volatile (__ex(SVM_CLGI));
 419 }
 420
 421 static inline void stgi(void)
 422 {
 423         asm volatile (__ex(SVM_STGI));
 424 }
 425
 426 static inline void invlpga(unsigned long addr, u32 asid)
 427 {
 428         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
 429 }
 430
 431 static int get_npt_level(void)
 432 {
 433 #ifdef CONFIG_X86_64
 434         return PT64_ROOT_LEVEL;
 435 #else
 436         return PT32E_ROOT_LEVEL;
 437 #endif
 438 }
 439
 440 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 441 {
 442         vcpu->arch.efer = efer;
 443         if (!npt_enabled && !(efer & EFER_LMA))
 444                 efer &= ~EFER_LME;
 445
 446         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 447         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
 448 }
 449
 450 static int is_external_interrupt(u32 info)
 451 {
 452         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 453         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 454 }
 455
 456 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 457 {
 458         struct vcpu_svm *svm = to_svm(vcpu);
 459         u32 ret = 0;
 460
 461         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 462                 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 463         return ret & mask;
 464 }
 465
 466 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 467 {
 468         struct vcpu_svm *svm = to_svm(vcpu);
 469
 470         if (mask == 0)
 471                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 472         else
 473                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 474
 475 }
 476
 477 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 478 {
 479         struct vcpu_svm *svm = to_svm(vcpu);
 480
 481         if (svm->vmcb->control.next_rip != 0)
 482                 svm->next_rip = svm->vmcb->control.next_rip;
 483
 484         if (!svm->next_rip) {
 485                 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
 486                                 EMULATE_DONE)
 487                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 488                 return;
 489         }
 490         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 491                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 492                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 493
 494         kvm_rip_write(vcpu, svm->next_rip);
 495         svm_set_interrupt_shadow(vcpu, 0);
 496 }
 497
 498 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 499                                 bool has_error_code, u32 error_code,
 500                                 bool reinject)
 501 {
 502         struct vcpu_svm *svm = to_svm(vcpu);
 503
 504         /*
 505          * If we are within a nested VM we'd better #VMEXIT and let the guest
 506          * handle the exception
 507          */
 508         if (!reinject &&
 509             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 510                 return;
 511
 512         if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
 513                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 514
 515                 /*
 516                  * For guest debugging where we have to reinject #BP if some
 517                  * INT3 is guest-owned:
 518                  * Emulate nRIP by moving RIP forward. Will fail if injection
 519                  * raises a fault that is not intercepted. Still better than
 520                  * failing in all cases.
 521                  */
 522                 skip_emulated_instruction(&svm->vcpu);
 523                 rip = kvm_rip_read(&svm->vcpu);
 524                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 525                 svm->int3_injected = rip - old_rip;
 526         }
 527
 528         svm->vmcb->control.event_inj = nr
 529                 | SVM_EVTINJ_VALID
 530                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 531                 | SVM_EVTINJ_TYPE_EXEPT;
 532         svm->vmcb->control.event_inj_err = error_code;
 533 }
 534
 535 static void svm_init_erratum_383(void)
 536 {
 537         u32 low, high;
 538         int err;
 539         u64 val;
 540
 541         if (!cpu_has_amd_erratum(amd_erratum_383))
 542                 return;
 543
 544         /* Use _safe variants to not break nested virtualization */
 545         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 546         if (err)
 547                 return;
 548
 549         val |= (1ULL << 47);
 550
 551         low  = lower_32_bits(val);
 552         high = upper_32_bits(val);
 553
 554         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 555
 556         erratum_383_found = true;
 557 }
 558
 559 static int has_svm(void)
 560 {
 561         const char *msg;
 562
 563         if (!cpu_has_svm(&msg)) {
 564                 printk(KERN_INFO "has_svm: %s\n", msg);
 565                 return 0;
 566         }
 567
 568         return 1;
 569 }
 570
 571 static void svm_hardware_disable(void *garbage)
 572 {
 573         /* Make sure we clean up behind us */
 574         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 575                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 576
 577         cpu_svm_disable();
 578 }
 579
 580 static int svm_hardware_enable(void *garbage)
 581 {
 582
 583         struct svm_cpu_data *sd;
 584         uint64_t efer;
 585         struct desc_ptr gdt_descr;
 586         struct desc_struct *gdt;
 587         int me = raw_smp_processor_id();
 588
 589         rdmsrl(MSR_EFER, efer);
 590         if (efer & EFER_SVME)
 591                 return -EBUSY;
 592
 593         if (!has_svm()) {
 594                 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
 595                        me);
 596                 return -EINVAL;
 597         }
 598         sd = per_cpu(svm_data, me);
 599
 600         if (!sd) {
 601                 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
 602                        me);
 603                 return -EINVAL;
 604         }
 605
 606         sd->asid_generation = 1;
 607         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 608         sd->next_asid = sd->max_asid + 1;
 609
 610         native_store_gdt(&gdt_descr);
 611         gdt = (struct desc_struct *)gdt_descr.address;
 612         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 613
 614         wrmsrl(MSR_EFER, efer | EFER_SVME);
 615
 616         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 617
 618         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 619                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 620                 __get_cpu_var(current_tsc_ratio) = TSC_RATIO_DEFAULT;
 621         }
 622
 623         svm_init_erratum_383();
 624
 625         return 0;
 626 }
 627
 628 static void svm_cpu_uninit(int cpu)
 629 {
 630         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 631
 632         if (!sd)
 633                 return;
 634
 635         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 636         __free_page(sd->save_area);
 637         kfree(sd);
 638 }
 639
 640 static int svm_cpu_init(int cpu)
 641 {
 642         struct svm_cpu_data *sd;
 643         int r;
 644
 645         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 646         if (!sd)
 647                 return -ENOMEM;
 648         sd->cpu = cpu;
 649         sd->save_area = alloc_page(GFP_KERNEL);
 650         r = -ENOMEM;
 651         if (!sd->save_area)
 652                 goto err_1;
 653
 654         per_cpu(svm_data, cpu) = sd;
 655
 656         return 0;
 657
 658 err_1:
 659         kfree(sd);
 660         return r;
 661
 662 }
 663
 664 static bool valid_msr_intercept(u32 index)
 665 {
 666         int i;
 667
 668         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 669                 if (direct_access_msrs[i].index == index)
 670                         return true;
 671
 672         return false;
 673 }
 674
 675 static void set_msr_interception(u32 *msrpm, unsigned msr,
 676                                  int read, int write)
 677 {
 678         u8 bit_read, bit_write;
 679         unsigned long tmp;
 680         u32 offset;
 681
 682         /*
 683          * If this warning triggers extend the direct_access_msrs list at the
 684          * beginning of the file
 685          */
 686         WARN_ON(!valid_msr_intercept(msr));
 687
 688         offset    = svm_msrpm_offset(msr);
 689         bit_read  = 2 * (msr & 0x0f);
 690         bit_write = 2 * (msr & 0x0f) + 1;
 691         tmp       = msrpm[offset];
 692
 693         BUG_ON(offset == MSR_INVALID);
 694
 695         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 696         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 697
 698         msrpm[offset] = tmp;
 699 }
 700
 701 static void svm_vcpu_init_msrpm(u32 *msrpm)
 702 {
 703         int i;
 704
 705         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 706
 707         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 708                 if (!direct_access_msrs[i].always)
 709                         continue;
 710
 711                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
 712         }
 713 }
 714
 715 static void add_msr_offset(u32 offset)
 716 {
 717         int i;
 718
 719         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 720
 721                 /* Offset already in list? */
 722                 if (msrpm_offsets[i] == offset)
 723                         return;
 724
 725                 /* Slot used by another offset? */
 726                 if (msrpm_offsets[i] != MSR_INVALID)
 727                         continue;
 728
 729                 /* Add offset to list */
 730                 msrpm_offsets[i] = offset;
 731
 732                 return;
 733         }
 734
 735         /*
 736          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 737          * increase MSRPM_OFFSETS in this case.
 738          */
 739         BUG();
 740 }
 741
 742 static void init_msrpm_offsets(void)
 743 {
 744         int i;
 745
 746         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 747
 748         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 749                 u32 offset;
 750
 751                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 752                 BUG_ON(offset == MSR_INVALID);
 753
 754                 add_msr_offset(offset);
 755         }
 756 }
 757
 758 static void svm_enable_lbrv(struct vcpu_svm *svm)
 759 {
 760         u32 *msrpm = svm->msrpm;
 761
 762         svm->vmcb->control.lbr_ctl = 1;
 763         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 764         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 765         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 766         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 767 }
 768
 769 static void svm_disable_lbrv(struct vcpu_svm *svm)
 770 {
 771         u32 *msrpm = svm->msrpm;
 772
 773         svm->vmcb->control.lbr_ctl = 0;
 774         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 775         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 776         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 777         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 778 }
 779
 780 static __init int svm_hardware_setup(void)
 781 {
 782         int cpu;
 783         struct page *iopm_pages;
 784         void *iopm_va;
 785         int r;
 786
 787         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 788
 789         if (!iopm_pages)
 790                 return -ENOMEM;
 791
 792         iopm_va = page_address(iopm_pages);
 793         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 794         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 795
 796         init_msrpm_offsets();
 797
 798         if (boot_cpu_has(X86_FEATURE_NX))
 799                 kvm_enable_efer_bits(EFER_NX);
 800
 801         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 802                 kvm_enable_efer_bits(EFER_FFXSR);
 803
 804         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 805                 u64 max;
 806
 807                 kvm_has_tsc_control = true;
 808
 809                 /*
 810                  * Make sure the user can only configure tsc_khz values that
 811                  * fit into a signed integer.
 812                  * A min value is not calculated needed because it will always
 813                  * be 1 on all machines and a value of 0 is used to disable
 814                  * tsc-scaling for the vcpu.
 815                  */
 816                 max = min(0x7fffffffULL, __scale_tsc(tsc_khz, TSC_RATIO_MAX));
 817
 818                 kvm_max_guest_tsc_khz = max;
 819         }
 820
 821         if (nested) {
 822                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 823                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
 824         }
 825
 826         for_each_possible_cpu(cpu) {
 827                 r = svm_cpu_init(cpu);
 828                 if (r)
 829                         goto err;
 830         }
 831
 832         if (!boot_cpu_has(X86_FEATURE_NPT))
 833                 npt_enabled = false;
 834
 835         if (npt_enabled && !npt) {
 836                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 837                 npt_enabled = false;
 838         }
 839
 840         if (npt_enabled) {
 841                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 842                 kvm_enable_tdp();
 843         } else
 844                 kvm_disable_tdp();
 845
 846         return 0;
 847
 848 err:
 849         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 850         iopm_base = 0;
 851         return r;
 852 }
 853
 854 static __exit void svm_hardware_unsetup(void)
 855 {
 856         int cpu;
 857
 858         for_each_possible_cpu(cpu)
 859                 svm_cpu_uninit(cpu);
 860
 861         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 862         iopm_base = 0;
 863 }
 864
 865 static void init_seg(struct vmcb_seg *seg)
 866 {
 867         seg->selector = 0;
 868         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 869                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 870         seg->limit = 0xffff;
 871         seg->base = 0;
 872 }
 873
 874 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 875 {
 876         seg->selector = 0;
 877         seg->attrib = SVM_SELECTOR_P_MASK | type;
 878         seg->limit = 0xffff;
 879         seg->base = 0;
 880 }
 881
 882 static u64 __scale_tsc(u64 ratio, u64 tsc)
 883 {
 884         u64 mult, frac, _tsc;
 885
 886         mult  = ratio >> 32;
 887         frac  = ratio & ((1ULL << 32) - 1);
 888
 889         _tsc  = tsc;
 890         _tsc *= mult;
 891         _tsc += (tsc >> 32) * frac;
 892         _tsc += ((tsc & ((1ULL << 32) - 1)) * frac) >> 32;
 893
 894         return _tsc;
 895 }
 896
 897 static u64 svm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
 898 {
 899         struct vcpu_svm *svm = to_svm(vcpu);
 900         u64 _tsc = tsc;
 901
 902         if (svm->tsc_ratio != TSC_RATIO_DEFAULT)
 903                 _tsc = __scale_tsc(svm->tsc_ratio, tsc);
 904
 905         return _tsc;
 906 }
 907
 908 static void svm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
 909 {
 910         struct vcpu_svm *svm = to_svm(vcpu);
 911         u64 ratio;
 912         u64 khz;
 913
 914         /* TSC scaling supported? */
 915         if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR))
 916                 return;
 917
 918         /* TSC-Scaling disabled or guest TSC same frequency as host TSC? */
 919         if (user_tsc_khz == 0) {
 920                 vcpu->arch.virtual_tsc_khz = 0;
 921                 svm->tsc_ratio = TSC_RATIO_DEFAULT;
 922                 return;
 923         }
 924
 925         khz = user_tsc_khz;
 926
 927         /* TSC scaling required  - calculate ratio */
 928         ratio = khz << 32;
 929         do_div(ratio, tsc_khz);
 930
 931         if (ratio == 0 || ratio & TSC_RATIO_RSVD) {
 932                 WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n",
 933                                 user_tsc_khz);
 934                 return;
 935         }
 936         vcpu->arch.virtual_tsc_khz = user_tsc_khz;
 937         svm->tsc_ratio             = ratio;
 938 }
 939
 940 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
 941 {
 942         struct vcpu_svm *svm = to_svm(vcpu);
 943         u64 g_tsc_offset = 0;
 944
 945         if (is_guest_mode(vcpu)) {
 946                 g_tsc_offset = svm->vmcb->control.tsc_offset -
 947                                svm->nested.hsave->control.tsc_offset;
 948                 svm->nested.hsave->control.tsc_offset = offset;
 949         }
 950
 951         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
 952
 953         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 954 }
 955
 956 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
 957 {
 958         struct vcpu_svm *svm = to_svm(vcpu);
 959
 960         svm->vmcb->control.tsc_offset += adjustment;
 961         if (is_guest_mode(vcpu))
 962                 svm->nested.hsave->control.tsc_offset += adjustment;
 963         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 964 }
 965
 966 static u64 svm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
 967 {
 968         u64 tsc;
 969
 970         tsc = svm_scale_tsc(vcpu, native_read_tsc());
 971
 972         return target_tsc - tsc;
 973 }
 974
 975 static void init_vmcb(struct vcpu_svm *svm)
 976 {
 977         struct vmcb_control_area *control = &svm->vmcb->control;
 978         struct vmcb_save_area *save = &svm->vmcb->save;
 979
 980         svm->vcpu.fpu_active = 1;
 981         svm->vcpu.arch.hflags = 0;
 982
 983         set_cr_intercept(svm, INTERCEPT_CR0_READ);
 984         set_cr_intercept(svm, INTERCEPT_CR3_READ);
 985         set_cr_intercept(svm, INTERCEPT_CR4_READ);
 986         set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
 987         set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
 988         set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
 989         set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
 990
 991         set_dr_intercept(svm, INTERCEPT_DR0_READ);
 992         set_dr_intercept(svm, INTERCEPT_DR1_READ);
 993         set_dr_intercept(svm, INTERCEPT_DR2_READ);
 994         set_dr_intercept(svm, INTERCEPT_DR3_READ);
 995         set_dr_intercept(svm, INTERCEPT_DR4_READ);
 996         set_dr_intercept(svm, INTERCEPT_DR5_READ);
 997         set_dr_intercept(svm, INTERCEPT_DR6_READ);
 998         set_dr_intercept(svm, INTERCEPT_DR7_READ);
 999
1000         set_dr_intercept(svm, INTERCEPT_DR0_WRITE);
1001         set_dr_intercept(svm, INTERCEPT_DR1_WRITE);
1002         set_dr_intercept(svm, INTERCEPT_DR2_WRITE);
1003         set_dr_intercept(svm, INTERCEPT_DR3_WRITE);
1004         set_dr_intercept(svm, INTERCEPT_DR4_WRITE);
1005         set_dr_intercept(svm, INTERCEPT_DR5_WRITE);
1006         set_dr_intercept(svm, INTERCEPT_DR6_WRITE);
1007         set_dr_intercept(svm, INTERCEPT_DR7_WRITE);
1008
1009         set_exception_intercept(svm, PF_VECTOR);
1010         set_exception_intercept(svm, UD_VECTOR);
1011         set_exception_intercept(svm, MC_VECTOR);
1012
1013         set_intercept(svm, INTERCEPT_INTR);
1014         set_intercept(svm, INTERCEPT_NMI);
1015         set_intercept(svm, INTERCEPT_SMI);
1016         set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1017         set_intercept(svm, INTERCEPT_RDPMC);
1018         set_intercept(svm, INTERCEPT_CPUID);
1019         set_intercept(svm, INTERCEPT_INVD);
1020         set_intercept(svm, INTERCEPT_HLT);
1021         set_intercept(svm, INTERCEPT_INVLPG);
1022         set_intercept(svm, INTERCEPT_INVLPGA);
1023         set_intercept(svm, INTERCEPT_IOIO_PROT);
1024         set_intercept(svm, INTERCEPT_MSR_PROT);
1025         set_intercept(svm, INTERCEPT_TASK_SWITCH);
1026         set_intercept(svm, INTERCEPT_SHUTDOWN);
1027         set_intercept(svm, INTERCEPT_VMRUN);
1028         set_intercept(svm, INTERCEPT_VMMCALL);
1029         set_intercept(svm, INTERCEPT_VMLOAD);
1030         set_intercept(svm, INTERCEPT_VMSAVE);
1031         set_intercept(svm, INTERCEPT_STGI);
1032         set_intercept(svm, INTERCEPT_CLGI);
1033         set_intercept(svm, INTERCEPT_SKINIT);
1034         set_intercept(svm, INTERCEPT_WBINVD);
1035         set_intercept(svm, INTERCEPT_MONITOR);
1036         set_intercept(svm, INTERCEPT_MWAIT);
1037         set_intercept(svm, INTERCEPT_XSETBV);
1038
1039         control->iopm_base_pa = iopm_base;
1040         control->msrpm_base_pa = __pa(svm->msrpm);
1041         control->int_ctl = V_INTR_MASKING_MASK;
1042
1043         init_seg(&save->es);
1044         init_seg(&save->ss);
1045         init_seg(&save->ds);
1046         init_seg(&save->fs);
1047         init_seg(&save->gs);
1048
1049         save->cs.selector = 0xf000;
1050         /* Executable/Readable Code Segment */
1051         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1052                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1053         save->cs.limit = 0xffff;
1054         /*
1055          * cs.base should really be 0xffff0000, but vmx can't handle that, so
1056          * be consistent with it.
1057          *
1058          * Replace when we have real mode working for vmx.
1059          */
1060         save->cs.base = 0xf0000;
1061
1062         save->gdtr.limit = 0xffff;
1063         save->idtr.limit = 0xffff;
1064
1065         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1066         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1067
1068         svm_set_efer(&svm->vcpu, 0);
1069         save->dr6 = 0xffff0ff0;
1070         save->dr7 = 0x400;
1071         kvm_set_rflags(&svm->vcpu, 2);
1072         save->rip = 0x0000fff0;
1073         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1074
1075         /*
1076          * This is the guest-visible cr0 value.
1077          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1078          */
1079         svm->vcpu.arch.cr0 = 0;
1080         (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1081
1082         save->cr4 = X86_CR4_PAE;
1083         /* rdx = ?? */
1084
1085         if (npt_enabled) {
1086                 /* Setup VMCB for Nested Paging */
1087                 control->nested_ctl = 1;
1088                 clr_intercept(svm, INTERCEPT_INVLPG);
1089                 clr_exception_intercept(svm, PF_VECTOR);
1090                 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1091                 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1092                 save->g_pat = 0x0007040600070406ULL;
1093                 save->cr3 = 0;
1094                 save->cr4 = 0;
1095         }
1096         svm->asid_generation = 0;
1097
1098         svm->nested.vmcb = 0;
1099         svm->vcpu.arch.hflags = 0;
1100
1101         if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1102                 control->pause_filter_count = 3000;
1103                 set_intercept(svm, INTERCEPT_PAUSE);
1104         }
1105
1106         mark_all_dirty(svm->vmcb);
1107
1108         enable_gif(svm);
1109 }
1110
1111 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
1112 {
1113         struct vcpu_svm *svm = to_svm(vcpu);
1114
1115         init_vmcb(svm);
1116
1117         if (!kvm_vcpu_is_bsp(vcpu)) {
1118                 kvm_rip_write(vcpu, 0);
1119                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
1120                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
1121         }
1122         vcpu->arch.regs_avail = ~0;
1123         vcpu->arch.regs_dirty = ~0;
1124
1125         return 0;
1126 }
1127
1128 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1129 {
1130         struct vcpu_svm *svm;
1131         struct page *page;
1132         struct page *msrpm_pages;
1133         struct page *hsave_page;
1134         struct page *nested_msrpm_pages;
1135         int err;
1136
1137         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1138         if (!svm) {
1139                 err = -ENOMEM;
1140                 goto out;
1141         }
1142
1143         svm->tsc_ratio = TSC_RATIO_DEFAULT;
1144
1145         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1146         if (err)
1147                 goto free_svm;
1148
1149         err = -ENOMEM;
1150         page = alloc_page(GFP_KERNEL);
1151         if (!page)
1152                 goto uninit;
1153
1154         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1155         if (!msrpm_pages)
1156                 goto free_page1;
1157
1158         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1159         if (!nested_msrpm_pages)
1160                 goto free_page2;
1161
1162         hsave_page = alloc_page(GFP_KERNEL);
1163         if (!hsave_page)
1164                 goto free_page3;
1165
1166         svm->nested.hsave = page_address(hsave_page);
1167
1168         svm->msrpm = page_address(msrpm_pages);
1169         svm_vcpu_init_msrpm(svm->msrpm);
1170
1171         svm->nested.msrpm = page_address(nested_msrpm_pages);
1172         svm_vcpu_init_msrpm(svm->nested.msrpm);
1173
1174         svm->vmcb = page_address(page);
1175         clear_page(svm->vmcb);
1176         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1177         svm->asid_generation = 0;
1178         init_vmcb(svm);
1179         kvm_write_tsc(&svm->vcpu, 0);
1180
1181         err = fx_init(&svm->vcpu);
1182         if (err)
1183                 goto free_page4;
1184
1185         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1186         if (kvm_vcpu_is_bsp(&svm->vcpu))
1187                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1188
1189         return &svm->vcpu;
1190
1191 free_page4:
1192         __free_page(hsave_page);
1193 free_page3:
1194         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1195 free_page2:
1196         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1197 free_page1:
1198         __free_page(page);
1199 uninit:
1200         kvm_vcpu_uninit(&svm->vcpu);
1201 free_svm:
1202         kmem_cache_free(kvm_vcpu_cache, svm);
1203 out:
1204         return ERR_PTR(err);
1205 }
1206
1207 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1208 {
1209         struct vcpu_svm *svm = to_svm(vcpu);
1210
1211         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1212         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1213         __free_page(virt_to_page(svm->nested.hsave));
1214         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1215         kvm_vcpu_uninit(vcpu);
1216         kmem_cache_free(kvm_vcpu_cache, svm);
1217 }
1218
1219 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1220 {
1221         struct vcpu_svm *svm = to_svm(vcpu);
1222         int i;
1223
1224         if (unlikely(cpu != vcpu->cpu)) {
1225                 svm->asid_generation = 0;
1226                 mark_all_dirty(svm->vmcb);
1227         }
1228
1229 #ifdef CONFIG_X86_64
1230         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1231 #endif
1232         savesegment(fs, svm->host.fs);
1233         savesegment(gs, svm->host.gs);
1234         svm->host.ldt = kvm_read_ldt();
1235
1236         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1237                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1238
1239         if (static_cpu_has(X86_FEATURE_TSCRATEMSR) &&
1240             svm->tsc_ratio != __get_cpu_var(current_tsc_ratio)) {
1241                 __get_cpu_var(current_tsc_ratio) = svm->tsc_ratio;
1242                 wrmsrl(MSR_AMD64_TSC_RATIO, svm->tsc_ratio);
1243         }
1244 }
1245
1246 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1247 {
1248         struct vcpu_svm *svm = to_svm(vcpu);
1249         int i;
1250
1251         ++vcpu->stat.host_state_reload;
1252         kvm_load_ldt(svm->host.ldt);
1253 #ifdef CONFIG_X86_64
1254         loadsegment(fs, svm->host.fs);
1255         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1256         load_gs_index(svm->host.gs);
1257 #else
1258 #ifdef CONFIG_X86_32_LAZY_GS
1259         loadsegment(gs, svm->host.gs);
1260 #endif
1261 #endif
1262         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1263                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1264 }
1265
1266 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1267 {
1268         return to_svm(vcpu)->vmcb->save.rflags;
1269 }
1270
1271 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1272 {
1273         to_svm(vcpu)->vmcb->save.rflags = rflags;
1274 }
1275
1276 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1277 {
1278         switch (reg) {
1279         case VCPU_EXREG_PDPTR:
1280                 BUG_ON(!npt_enabled);
1281                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1282                 break;
1283         default:
1284                 BUG();
1285         }
1286 }
1287
1288 static void svm_set_vintr(struct vcpu_svm *svm)
1289 {
1290         set_intercept(svm, INTERCEPT_VINTR);
1291 }
1292
1293 static void svm_clear_vintr(struct vcpu_svm *svm)
1294 {
1295         clr_intercept(svm, INTERCEPT_VINTR);
1296 }
1297
1298 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1299 {
1300         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1301
1302         switch (seg) {
1303         case VCPU_SREG_CS: return &save->cs;
1304         case VCPU_SREG_DS: return &save->ds;
1305         case VCPU_SREG_ES: return &save->es;
1306         case VCPU_SREG_FS: return &save->fs;
1307         case VCPU_SREG_GS: return &save->gs;
1308         case VCPU_SREG_SS: return &save->ss;
1309         case VCPU_SREG_TR: return &save->tr;
1310         case VCPU_SREG_LDTR: return &save->ldtr;
1311         }
1312         BUG();
1313         return NULL;
1314 }
1315
1316 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1317 {
1318         struct vmcb_seg *s = svm_seg(vcpu, seg);
1319
1320         return s->base;
1321 }
1322
1323 static void svm_get_segment(struct kvm_vcpu *vcpu,
1324                             struct kvm_segment *var, int seg)
1325 {
1326         struct vmcb_seg *s = svm_seg(vcpu, seg);
1327
1328         var->base = s->base;
1329         var->limit = s->limit;
1330         var->selector = s->selector;
1331         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1332         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1333         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1334         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1335         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1336         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1337         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1338         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1339
1340         /*
1341          * AMD's VMCB does not have an explicit unusable field, so emulate it
1342          * for cross vendor migration purposes by "not present"
1343          */
1344         var->unusable = !var->present || (var->type == 0);
1345
1346         switch (seg) {
1347         case VCPU_SREG_CS:
1348                 /*
1349                  * SVM always stores 0 for the 'G' bit in the CS selector in
1350                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1351                  * Intel's VMENTRY has a check on the 'G' bit.
1352                  */
1353                 var->g = s->limit > 0xfffff;
1354                 break;
1355         case VCPU_SREG_TR:
1356                 /*
1357                  * Work around a bug where the busy flag in the tr selector
1358                  * isn't exposed
1359                  */
1360                 var->type |= 0x2;
1361                 break;
1362         case VCPU_SREG_DS:
1363         case VCPU_SREG_ES:
1364         case VCPU_SREG_FS:
1365         case VCPU_SREG_GS:
1366                 /*
1367                  * The accessed bit must always be set in the segment
1368                  * descriptor cache, although it can be cleared in the
1369                  * descriptor, the cached bit always remains at 1. Since
1370                  * Intel has a check on this, set it here to support
1371                  * cross-vendor migration.
1372                  */
1373                 if (!var->unusable)
1374                         var->type |= 0x1;
1375                 break;
1376         case VCPU_SREG_SS:
1377                 /*
1378                  * On AMD CPUs sometimes the DB bit in the segment
1379                  * descriptor is left as 1, although the whole segment has
1380                  * been made unusable. Clear it here to pass an Intel VMX
1381                  * entry check when cross vendor migrating.
1382                  */
1383                 if (var->unusable)
1384                         var->db = 0;
1385                 break;
1386         }
1387 }
1388
1389 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1390 {
1391         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1392
1393         return save->cpl;
1394 }
1395
1396 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1397 {
1398         struct vcpu_svm *svm = to_svm(vcpu);
1399
1400         dt->size = svm->vmcb->save.idtr.limit;
1401         dt->address = svm->vmcb->save.idtr.base;
1402 }
1403
1404 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1405 {
1406         struct vcpu_svm *svm = to_svm(vcpu);
1407
1408         svm->vmcb->save.idtr.limit = dt->size;
1409         svm->vmcb->save.idtr.base = dt->address ;
1410         mark_dirty(svm->vmcb, VMCB_DT);
1411 }
1412
1413 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1414 {
1415         struct vcpu_svm *svm = to_svm(vcpu);
1416
1417         dt->size = svm->vmcb->save.gdtr.limit;
1418         dt->address = svm->vmcb->save.gdtr.base;
1419 }
1420
1421 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1422 {
1423         struct vcpu_svm *svm = to_svm(vcpu);
1424
1425         svm->vmcb->save.gdtr.limit = dt->size;
1426         svm->vmcb->save.gdtr.base = dt->address ;
1427         mark_dirty(svm->vmcb, VMCB_DT);
1428 }
1429
1430 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1431 {
1432 }
1433
1434 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1435 {
1436 }
1437
1438 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1439 {
1440 }
1441
1442 static void update_cr0_intercept(struct vcpu_svm *svm)
1443 {
1444         ulong gcr0 = svm->vcpu.arch.cr0;
1445         u64 *hcr0 = &svm->vmcb->save.cr0;
1446
1447         if (!svm->vcpu.fpu_active)
1448                 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1449         else
1450                 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1451                         | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1452
1453         mark_dirty(svm->vmcb, VMCB_CR);
1454
1455         if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1456                 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1457                 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1458         } else {
1459                 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1460                 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1461         }
1462 }
1463
1464 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1465 {
1466         struct vcpu_svm *svm = to_svm(vcpu);
1467
1468 #ifdef CONFIG_X86_64
1469         if (vcpu->arch.efer & EFER_LME) {
1470                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1471                         vcpu->arch.efer |= EFER_LMA;
1472                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1473                 }
1474
1475                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1476                         vcpu->arch.efer &= ~EFER_LMA;
1477                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1478                 }
1479         }
1480 #endif
1481         vcpu->arch.cr0 = cr0;
1482
1483         if (!npt_enabled)
1484                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1485
1486         if (!vcpu->fpu_active)
1487                 cr0 |= X86_CR0_TS;
1488         /*
1489          * re-enable caching here because the QEMU bios
1490          * does not do it - this results in some delay at
1491          * reboot
1492          */
1493         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1494         svm->vmcb->save.cr0 = cr0;
1495         mark_dirty(svm->vmcb, VMCB_CR);
1496         update_cr0_intercept(svm);
1497 }
1498
1499 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1500 {
1501         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1502         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1503
1504         if (cr4 & X86_CR4_VMXE)
1505                 return 1;
1506
1507         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1508                 svm_flush_tlb(vcpu);
1509
1510         vcpu->arch.cr4 = cr4;
1511         if (!npt_enabled)
1512                 cr4 |= X86_CR4_PAE;
1513         cr4 |= host_cr4_mce;
1514         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1515         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1516         return 0;
1517 }
1518
1519 static void svm_set_segment(struct kvm_vcpu *vcpu,
1520                             struct kvm_segment *var, int seg)
1521 {
1522         struct vcpu_svm *svm = to_svm(vcpu);
1523         struct vmcb_seg *s = svm_seg(vcpu, seg);
1524
1525         s->base = var->base;
1526         s->limit = var->limit;
1527         s->selector = var->selector;
1528         if (var->unusable)
1529                 s->attrib = 0;
1530         else {
1531                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1532                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1533                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1534                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1535                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1536                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1537                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1538                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1539         }
1540         if (seg == VCPU_SREG_CS)
1541                 svm->vmcb->save.cpl
1542                         = (svm->vmcb->save.cs.attrib
1543                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
1544
1545         mark_dirty(svm->vmcb, VMCB_SEG);
1546 }
1547
1548 static void update_db_intercept(struct kvm_vcpu *vcpu)
1549 {
1550         struct vcpu_svm *svm = to_svm(vcpu);
1551
1552         clr_exception_intercept(svm, DB_VECTOR);
1553         clr_exception_intercept(svm, BP_VECTOR);
1554
1555         if (svm->nmi_singlestep)
1556                 set_exception_intercept(svm, DB_VECTOR);
1557
1558         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1559                 if (vcpu->guest_debug &
1560                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1561                         set_exception_intercept(svm, DB_VECTOR);
1562                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1563                         set_exception_intercept(svm, BP_VECTOR);
1564         } else
1565                 vcpu->guest_debug = 0;
1566 }
1567
1568 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1569 {
1570         struct vcpu_svm *svm = to_svm(vcpu);
1571
1572         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1573                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1574         else
1575                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1576
1577         mark_dirty(svm->vmcb, VMCB_DR);
1578
1579         update_db_intercept(vcpu);
1580 }
1581
1582 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1583 {
1584         if (sd->next_asid > sd->max_asid) {
1585                 ++sd->asid_generation;
1586                 sd->next_asid = 1;
1587                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1588         }
1589
1590         svm->asid_generation = sd->asid_generation;
1591         svm->vmcb->control.asid = sd->next_asid++;
1592
1593         mark_dirty(svm->vmcb, VMCB_ASID);
1594 }
1595
1596 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1597 {
1598         struct vcpu_svm *svm = to_svm(vcpu);
1599
1600         svm->vmcb->save.dr7 = value;
1601         mark_dirty(svm->vmcb, VMCB_DR);
1602 }
1603
1604 static int pf_interception(struct vcpu_svm *svm)
1605 {
1606         u64 fault_address = svm->vmcb->control.exit_info_2;
1607         u32 error_code;
1608         int r = 1;
1609
1610         switch (svm->apf_reason) {
1611         default:
1612                 error_code = svm->vmcb->control.exit_info_1;
1613
1614                 trace_kvm_page_fault(fault_address, error_code);
1615                 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1616                         kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1617                 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1618                         svm->vmcb->control.insn_bytes,
1619                         svm->vmcb->control.insn_len);
1620                 break;
1621         case KVM_PV_REASON_PAGE_NOT_PRESENT:
1622                 svm->apf_reason = 0;
1623                 local_irq_disable();
1624                 kvm_async_pf_task_wait(fault_address);
1625                 local_irq_enable();
1626                 break;
1627         case KVM_PV_REASON_PAGE_READY:
1628                 svm->apf_reason = 0;
1629                 local_irq_disable();
1630                 kvm_async_pf_task_wake(fault_address);
1631                 local_irq_enable();
1632                 break;
1633         }
1634         return r;
1635 }
1636
1637 static int db_interception(struct vcpu_svm *svm)
1638 {
1639         struct kvm_run *kvm_run = svm->vcpu.run;
1640
1641         if (!(svm->vcpu.guest_debug &
1642               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1643                 !svm->nmi_singlestep) {
1644                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1645                 return 1;
1646         }
1647
1648         if (svm->nmi_singlestep) {
1649                 svm->nmi_singlestep = false;
1650                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1651                         svm->vmcb->save.rflags &=
1652                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1653                 update_db_intercept(&svm->vcpu);
1654         }
1655
1656         if (svm->vcpu.guest_debug &
1657             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1658                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1659                 kvm_run->debug.arch.pc =
1660                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1661                 kvm_run->debug.arch.exception = DB_VECTOR;
1662                 return 0;
1663         }
1664
1665         return 1;
1666 }
1667
1668 static int bp_interception(struct vcpu_svm *svm)
1669 {
1670         struct kvm_run *kvm_run = svm->vcpu.run;
1671
1672         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1673         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1674         kvm_run->debug.arch.exception = BP_VECTOR;
1675         return 0;
1676 }
1677
1678 static int ud_interception(struct vcpu_svm *svm)
1679 {
1680         int er;
1681
1682         er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
1683         if (er != EMULATE_DONE)
1684                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1685         return 1;
1686 }
1687
1688 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1689 {
1690         struct vcpu_svm *svm = to_svm(vcpu);
1691
1692         clr_exception_intercept(svm, NM_VECTOR);
1693
1694         svm->vcpu.fpu_active = 1;
1695         update_cr0_intercept(svm);
1696 }
1697
1698 static int nm_interception(struct vcpu_svm *svm)
1699 {
1700         svm_fpu_activate(&svm->vcpu);
1701         return 1;
1702 }
1703
1704 static bool is_erratum_383(void)
1705 {
1706         int err, i;
1707         u64 value;
1708
1709         if (!erratum_383_found)
1710                 return false;
1711
1712         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1713         if (err)
1714                 return false;
1715
1716         /* Bit 62 may or may not be set for this mce */
1717         value &= ~(1ULL << 62);
1718
1719         if (value != 0xb600000000010015ULL)
1720                 return false;
1721
1722         /* Clear MCi_STATUS registers */
1723         for (i = 0; i < 6; ++i)
1724                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1725
1726         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1727         if (!err) {
1728                 u32 low, high;
1729
1730                 value &= ~(1ULL << 2);
1731                 low    = lower_32_bits(value);
1732                 high   = upper_32_bits(value);
1733
1734                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1735         }
1736
1737         /* Flush tlb to evict multi-match entries */
1738         __flush_tlb_all();
1739
1740         return true;
1741 }
1742
1743 static void svm_handle_mce(struct vcpu_svm *svm)
1744 {
1745         if (is_erratum_383()) {
1746                 /*
1747                  * Erratum 383 triggered. Guest state is corrupt so kill the
1748                  * guest.
1749                  */
1750                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1751
1752                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1753
1754                 return;
1755         }
1756
1757         /*
1758          * On an #MC intercept the MCE handler is not called automatically in
1759          * the host. So do it by hand here.
1760          */
1761         asm volatile (
1762                 "int $0x12\n");
1763         /* not sure if we ever come back to this point */
1764
1765         return;
1766 }
1767
1768 static int mc_interception(struct vcpu_svm *svm)
1769 {
1770         return 1;
1771 }
1772
1773 static int shutdown_interception(struct vcpu_svm *svm)
1774 {
1775         struct kvm_run *kvm_run = svm->vcpu.run;
1776
1777         /*
1778          * VMCB is undefined after a SHUTDOWN intercept
1779          * so reinitialize it.
1780          */
1781         clear_page(svm->vmcb);
1782         init_vmcb(svm);
1783
1784         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1785         return 0;
1786 }
1787
1788 static int io_interception(struct vcpu_svm *svm)
1789 {
1790         struct kvm_vcpu *vcpu = &svm->vcpu;
1791         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1792         int size, in, string;
1793         unsigned port;
1794
1795         ++svm->vcpu.stat.io_exits;
1796         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1797         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1798         if (string || in)
1799                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
1800
1801         port = io_info >> 16;
1802         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1803         svm->next_rip = svm->vmcb->control.exit_info_2;
1804         skip_emulated_instruction(&svm->vcpu);
1805
1806         return kvm_fast_pio_out(vcpu, size, port);
1807 }
1808
1809 static int nmi_interception(struct vcpu_svm *svm)
1810 {
1811         return 1;
1812 }
1813
1814 static int intr_interception(struct vcpu_svm *svm)
1815 {
1816         ++svm->vcpu.stat.irq_exits;
1817         return 1;
1818 }
1819
1820 static int nop_on_interception(struct vcpu_svm *svm)
1821 {
1822         return 1;
1823 }
1824
1825 static int halt_interception(struct vcpu_svm *svm)
1826 {
1827         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1828         skip_emulated_instruction(&svm->vcpu);
1829         return kvm_emulate_halt(&svm->vcpu);
1830 }
1831
1832 static int vmmcall_interception(struct vcpu_svm *svm)
1833 {
1834         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1835         skip_emulated_instruction(&svm->vcpu);
1836         kvm_emulate_hypercall(&svm->vcpu);
1837         return 1;
1838 }
1839
1840 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1841 {
1842         struct vcpu_svm *svm = to_svm(vcpu);
1843
1844         return svm->nested.nested_cr3;
1845 }
1846
1847 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
1848 {
1849         struct vcpu_svm *svm = to_svm(vcpu);
1850         u64 cr3 = svm->nested.nested_cr3;
1851         u64 pdpte;
1852         int ret;
1853
1854         ret = kvm_read_guest_page(vcpu->kvm, gpa_to_gfn(cr3), &pdpte,
1855                                   offset_in_page(cr3) + index * 8, 8);
1856         if (ret)
1857                 return 0;
1858         return pdpte;
1859 }
1860
1861 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1862                                    unsigned long root)
1863 {
1864         struct vcpu_svm *svm = to_svm(vcpu);
1865
1866         svm->vmcb->control.nested_cr3 = root;
1867         mark_dirty(svm->vmcb, VMCB_NPT);
1868         svm_flush_tlb(vcpu);
1869 }
1870
1871 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1872                                        struct x86_exception *fault)
1873 {
1874         struct vcpu_svm *svm = to_svm(vcpu);
1875
1876         svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1877         svm->vmcb->control.exit_code_hi = 0;
1878         svm->vmcb->control.exit_info_1 = fault->error_code;
1879         svm->vmcb->control.exit_info_2 = fault->address;
1880
1881         nested_svm_vmexit(svm);
1882 }
1883
1884 static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1885 {
1886         int r;
1887
1888         r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1889
1890         vcpu->arch.mmu.set_cr3           = nested_svm_set_tdp_cr3;
1891         vcpu->arch.mmu.get_cr3           = nested_svm_get_tdp_cr3;
1892         vcpu->arch.mmu.get_pdptr         = nested_svm_get_tdp_pdptr;
1893         vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1894         vcpu->arch.mmu.shadow_root_level = get_npt_level();
1895         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
1896
1897         return r;
1898 }
1899
1900 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1901 {
1902         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1903 }
1904
1905 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1906 {
1907         if (!(svm->vcpu.arch.efer & EFER_SVME)
1908             || !is_paging(&svm->vcpu)) {
1909                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1910                 return 1;
1911         }
1912
1913         if (svm->vmcb->save.cpl) {
1914                 kvm_inject_gp(&svm->vcpu, 0);
1915                 return 1;
1916         }
1917
1918        return 0;
1919 }
1920
1921 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1922                                       bool has_error_code, u32 error_code)
1923 {
1924         int vmexit;
1925
1926         if (!is_guest_mode(&svm->vcpu))
1927                 return 0;
1928
1929         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1930         svm->vmcb->control.exit_code_hi = 0;
1931         svm->vmcb->control.exit_info_1 = error_code;
1932         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1933
1934         vmexit = nested_svm_intercept(svm);
1935         if (vmexit == NESTED_EXIT_DONE)
1936                 svm->nested.exit_required = true;
1937
1938         return vmexit;
1939 }
1940
1941 /* This function returns true if it is save to enable the irq window */
1942 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1943 {
1944         if (!is_guest_mode(&svm->vcpu))
1945                 return true;
1946
1947         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1948                 return true;
1949
1950         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1951                 return false;
1952
1953         /*
1954          * if vmexit was already requested (by intercepted exception
1955          * for instance) do not overwrite it with "external interrupt"
1956          * vmexit.
1957          */
1958         if (svm->nested.exit_required)
1959                 return false;
1960
1961         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
1962         svm->vmcb->control.exit_info_1 = 0;
1963         svm->vmcb->control.exit_info_2 = 0;
1964
1965         if (svm->nested.intercept & 1ULL) {
1966                 /*
1967                  * The #vmexit can't be emulated here directly because this
1968                  * code path runs with irqs and preemtion disabled. A
1969                  * #vmexit emulation might sleep. Only signal request for
1970                  * the #vmexit here.
1971                  */
1972                 svm->nested.exit_required = true;
1973                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1974                 return false;
1975         }
1976
1977         return true;
1978 }
1979
1980 /* This function returns true if it is save to enable the nmi window */
1981 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1982 {
1983         if (!is_guest_mode(&svm->vcpu))
1984                 return true;
1985
1986         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1987                 return true;
1988
1989         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1990         svm->nested.exit_required = true;
1991
1992         return false;
1993 }
1994
1995 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1996 {
1997         struct page *page;
1998
1999         might_sleep();
2000
2001         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
2002         if (is_error_page(page))
2003                 goto error;
2004
2005         *_page = page;
2006
2007         return kmap(page);
2008
2009 error:
2010         kvm_release_page_clean(page);
2011         kvm_inject_gp(&svm->vcpu, 0);
2012
2013         return NULL;
2014 }
2015
2016 static void nested_svm_unmap(struct page *page)
2017 {
2018         kunmap(page);
2019         kvm_release_page_dirty(page);
2020 }
2021
2022 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2023 {
2024         unsigned port;
2025         u8 val, bit;
2026         u64 gpa;
2027
2028         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2029                 return NESTED_EXIT_HOST;
2030
2031         port = svm->vmcb->control.exit_info_1 >> 16;
2032         gpa  = svm->nested.vmcb_iopm + (port / 8);
2033         bit  = port % 8;
2034         val  = 0;
2035
2036         if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
2037                 val &= (1 << bit);
2038
2039         return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2040 }
2041
2042 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2043 {
2044         u32 offset, msr, value;
2045         int write, mask;
2046
2047         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2048                 return NESTED_EXIT_HOST;
2049
2050         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2051         offset = svm_msrpm_offset(msr);
2052         write  = svm->vmcb->control.exit_info_1 & 1;
2053         mask   = 1 << ((2 * (msr & 0xf)) + write);
2054
2055         if (offset == MSR_INVALID)
2056                 return NESTED_EXIT_DONE;
2057
2058         /* Offset is in 32 bit units but need in 8 bit units */
2059         offset *= 4;
2060
2061         if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
2062                 return NESTED_EXIT_DONE;
2063
2064         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2065 }
2066
2067 static int nested_svm_exit_special(struct vcpu_svm *svm)
2068 {
2069         u32 exit_code = svm->vmcb->control.exit_code;
2070
2071         switch (exit_code) {
2072         case SVM_EXIT_INTR:
2073         case SVM_EXIT_NMI:
2074         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2075                 return NESTED_EXIT_HOST;
2076         case SVM_EXIT_NPF:
2077                 /* For now we are always handling NPFs when using them */
2078                 if (npt_enabled)
2079                         return NESTED_EXIT_HOST;
2080                 break;
2081         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2082                 /* When we're shadowing, trap PFs, but not async PF */
2083                 if (!npt_enabled && svm->apf_reason == 0)
2084                         return NESTED_EXIT_HOST;
2085                 break;
2086         case SVM_EXIT_EXCP_BASE + NM_VECTOR:
2087                 nm_interception(svm);
2088                 break;
2089         default:
2090                 break;
2091         }
2092
2093         return NESTED_EXIT_CONTINUE;
2094 }
2095
2096 /*
2097  * If this function returns true, this #vmexit was already handled
2098  */
2099 static int nested_svm_intercept(struct vcpu_svm *svm)
2100 {
2101         u32 exit_code = svm->vmcb->control.exit_code;
2102         int vmexit = NESTED_EXIT_HOST;
2103
2104         switch (exit_code) {
2105         case SVM_EXIT_MSR:
2106                 vmexit = nested_svm_exit_handled_msr(svm);
2107                 break;
2108         case SVM_EXIT_IOIO:
2109                 vmexit = nested_svm_intercept_ioio(svm);
2110                 break;
2111         case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2112                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2113                 if (svm->nested.intercept_cr & bit)
2114                         vmexit = NESTED_EXIT_DONE;
2115                 break;
2116         }
2117         case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2118                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2119                 if (svm->nested.intercept_dr & bit)
2120                         vmexit = NESTED_EXIT_DONE;
2121                 break;
2122         }
2123         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2124                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2125                 if (svm->nested.intercept_exceptions & excp_bits)
2126                         vmexit = NESTED_EXIT_DONE;
2127                 /* async page fault always cause vmexit */
2128                 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2129                          svm->apf_reason != 0)
2130                         vmexit = NESTED_EXIT_DONE;
2131                 break;
2132         }
2133         case SVM_EXIT_ERR: {
2134                 vmexit = NESTED_EXIT_DONE;
2135                 break;
2136         }
2137         default: {
2138                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2139                 if (svm->nested.intercept & exit_bits)
2140                         vmexit = NESTED_EXIT_DONE;
2141         }
2142         }
2143
2144         return vmexit;
2145 }
2146
2147 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2148 {
2149         int vmexit;
2150
2151         vmexit = nested_svm_intercept(svm);
2152
2153         if (vmexit == NESTED_EXIT_DONE)
2154                 nested_svm_vmexit(svm);
2155
2156         return vmexit;
2157 }
2158
2159 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2160 {
2161         struct vmcb_control_area *dst  = &dst_vmcb->control;
2162         struct vmcb_control_area *from = &from_vmcb->control;
2163
2164         dst->intercept_cr         = from->intercept_cr;
2165         dst->intercept_dr         = from->intercept_dr;
2166         dst->intercept_exceptions = from->intercept_exceptions;
2167         dst->intercept            = from->intercept;
2168         dst->iopm_base_pa         = from->iopm_base_pa;
2169         dst->msrpm_base_pa        = from->msrpm_base_pa;
2170         dst->tsc_offset           = from->tsc_offset;
2171         dst->asid                 = from->asid;
2172         dst->tlb_ctl              = from->tlb_ctl;
2173         dst->int_ctl              = from->int_ctl;
2174         dst->int_vector           = from->int_vector;
2175         dst->int_state            = from->int_state;
2176         dst->exit_code            = from->exit_code;
2177         dst->exit_code_hi         = from->exit_code_hi;
2178         dst->exit_info_1          = from->exit_info_1;
2179         dst->exit_info_2          = from->exit_info_2;
2180         dst->exit_int_info        = from->exit_int_info;
2181         dst->exit_int_info_err    = from->exit_int_info_err;
2182         dst->nested_ctl           = from->nested_ctl;
2183         dst->event_inj            = from->event_inj;
2184         dst->event_inj_err        = from->event_inj_err;
2185         dst->nested_cr3           = from->nested_cr3;
2186         dst->lbr_ctl              = from->lbr_ctl;
2187 }
2188
2189 static int nested_svm_vmexit(struct vcpu_svm *svm)
2190 {
2191         struct vmcb *nested_vmcb;
2192         struct vmcb *hsave = svm->nested.hsave;
2193         struct vmcb *vmcb = svm->vmcb;
2194         struct page *page;
2195
2196         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2197                                        vmcb->control.exit_info_1,
2198                                        vmcb->control.exit_info_2,
2199                                        vmcb->control.exit_int_info,
2200                                        vmcb->control.exit_int_info_err,
2201                                        KVM_ISA_SVM);
2202
2203         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2204         if (!nested_vmcb)
2205                 return 1;
2206
2207         /* Exit Guest-Mode */
2208         leave_guest_mode(&svm->vcpu);
2209         svm->nested.vmcb = 0;
2210
2211         /* Give the current vmcb to the guest */
2212         disable_gif(svm);
2213
2214         nested_vmcb->save.es     = vmcb->save.es;
2215         nested_vmcb->save.cs     = vmcb->save.cs;
2216         nested_vmcb->save.ss     = vmcb->save.ss;
2217         nested_vmcb->save.ds     = vmcb->save.ds;
2218         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
2219         nested_vmcb->save.idtr   = vmcb->save.idtr;
2220         nested_vmcb->save.efer   = svm->vcpu.arch.efer;
2221         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
2222         nested_vmcb->save.cr3    = kvm_read_cr3(&svm->vcpu);
2223         nested_vmcb->save.cr2    = vmcb->save.cr2;
2224         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
2225         nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2226         nested_vmcb->save.rip    = vmcb->save.rip;
2227         nested_vmcb->save.rsp    = vmcb->save.rsp;
2228         nested_vmcb->save.rax    = vmcb->save.rax;
2229         nested_vmcb->save.dr7    = vmcb->save.dr7;
2230         nested_vmcb->save.dr6    = vmcb->save.dr6;
2231         nested_vmcb->save.cpl    = vmcb->save.cpl;
2232
2233         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
2234         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
2235         nested_vmcb->control.int_state         = vmcb->control.int_state;
2236         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
2237         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
2238         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
2239         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
2240         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
2241         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2242         nested_vmcb->control.next_rip          = vmcb->control.next_rip;
2243
2244         /*
2245          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2246          * to make sure that we do not lose injected events. So check event_inj
2247          * here and copy it to exit_int_info if it is valid.
2248          * Exit_int_info and event_inj can't be both valid because the case
2249          * below only happens on a VMRUN instruction intercept which has
2250          * no valid exit_int_info set.
2251          */
2252         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2253                 struct vmcb_control_area *nc = &nested_vmcb->control;
2254
2255                 nc->exit_int_info     = vmcb->control.event_inj;
2256                 nc->exit_int_info_err = vmcb->control.event_inj_err;
2257         }
2258
2259         nested_vmcb->control.tlb_ctl           = 0;
2260         nested_vmcb->control.event_inj         = 0;
2261         nested_vmcb->control.event_inj_err     = 0;
2262
2263         /* We always set V_INTR_MASKING and remember the old value in hflags */
2264         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2265                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2266
2267         /* Restore the original control entries */
2268         copy_vmcb_control_area(vmcb, hsave);
2269
2270         kvm_clear_exception_queue(&svm->vcpu);
2271         kvm_clear_interrupt_queue(&svm->vcpu);
2272
2273         svm->nested.nested_cr3 = 0;
2274
2275         /* Restore selected save entries */
2276         svm->vmcb->save.es = hsave->save.es;
2277         svm->vmcb->save.cs = hsave->save.cs;
2278         svm->vmcb->save.ss = hsave->save.ss;
2279         svm->vmcb->save.ds = hsave->save.ds;
2280         svm->vmcb->save.gdtr = hsave->save.gdtr;
2281         svm->vmcb->save.idtr = hsave->save.idtr;
2282         kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2283         svm_set_efer(&svm->vcpu, hsave->save.efer);
2284         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2285         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2286         if (npt_enabled) {
2287                 svm->vmcb->save.cr3 = hsave->save.cr3;
2288                 svm->vcpu.arch.cr3 = hsave->save.cr3;
2289         } else {
2290                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2291         }
2292         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2293         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2294         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2295         svm->vmcb->save.dr7 = 0;
2296         svm->vmcb->save.cpl = 0;
2297         svm->vmcb->control.exit_int_info = 0;
2298
2299         mark_all_dirty(svm->vmcb);
2300
2301         nested_svm_unmap(page);
2302
2303         nested_svm_uninit_mmu_context(&svm->vcpu);
2304         kvm_mmu_reset_context(&svm->vcpu);
2305         kvm_mmu_load(&svm->vcpu);
2306
2307         return 0;
2308 }
2309
2310 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2311 {
2312         /*
2313          * This function merges the msr permission bitmaps of kvm and the
2314          * nested vmcb. It is omptimized in that it only merges the parts where
2315          * the kvm msr permission bitmap may contain zero bits
2316          */
2317         int i;
2318
2319         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2320                 return true;
2321
2322         for (i = 0; i < MSRPM_OFFSETS; i++) {
2323                 u32 value, p;
2324                 u64 offset;
2325
2326                 if (msrpm_offsets[i] == 0xffffffff)
2327                         break;
2328
2329                 p      = msrpm_offsets[i];
2330                 offset = svm->nested.vmcb_msrpm + (p * 4);
2331
2332                 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2333                         return false;
2334
2335                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2336         }
2337
2338         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2339
2340         return true;
2341 }
2342
2343 static bool nested_vmcb_checks(struct vmcb *vmcb)
2344 {
2345         if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2346                 return false;
2347
2348         if (vmcb->control.asid == 0)
2349                 return false;
2350
2351         if (vmcb->control.nested_ctl && !npt_enabled)
2352                 return false;
2353
2354         return true;
2355 }
2356
2357 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2358 {
2359         struct vmcb *nested_vmcb;
2360         struct vmcb *hsave = svm->nested.hsave;
2361         struct vmcb *vmcb = svm->vmcb;
2362         struct page *page;
2363         u64 vmcb_gpa;
2364
2365         vmcb_gpa = svm->vmcb->save.rax;
2366
2367         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2368         if (!nested_vmcb)
2369                 return false;
2370
2371         if (!nested_vmcb_checks(nested_vmcb)) {
2372                 nested_vmcb->control.exit_code    = SVM_EXIT_ERR;
2373                 nested_vmcb->control.exit_code_hi = 0;
2374                 nested_vmcb->control.exit_info_1  = 0;
2375                 nested_vmcb->control.exit_info_2  = 0;
2376
2377                 nested_svm_unmap(page);
2378
2379                 return false;
2380         }
2381
2382         trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2383                                nested_vmcb->save.rip,
2384                                nested_vmcb->control.int_ctl,
2385                                nested_vmcb->control.event_inj,
2386                                nested_vmcb->control.nested_ctl);
2387
2388         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2389                                     nested_vmcb->control.intercept_cr >> 16,
2390                                     nested_vmcb->control.intercept_exceptions,
2391                                     nested_vmcb->control.intercept);
2392
2393         /* Clear internal status */
2394         kvm_clear_exception_queue(&svm->vcpu);
2395         kvm_clear_interrupt_queue(&svm->vcpu);
2396
2397         /*
2398          * Save the old vmcb, so we don't need to pick what we save, but can
2399          * restore everything when a VMEXIT occurs
2400          */
2401         hsave->save.es     = vmcb->save.es;
2402         hsave->save.cs     = vmcb->save.cs;
2403         hsave->save.ss     = vmcb->save.ss;
2404         hsave->save.ds     = vmcb->save.ds;
2405         hsave->save.gdtr   = vmcb->save.gdtr;
2406         hsave->save.idtr   = vmcb->save.idtr;
2407         hsave->save.efer   = svm->vcpu.arch.efer;
2408         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
2409         hsave->save.cr4    = svm->vcpu.arch.cr4;
2410         hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2411         hsave->save.rip    = kvm_rip_read(&svm->vcpu);
2412         hsave->save.rsp    = vmcb->save.rsp;
2413         hsave->save.rax    = vmcb->save.rax;
2414         if (npt_enabled)
2415                 hsave->save.cr3    = vmcb->save.cr3;
2416         else
2417                 hsave->save.cr3    = kvm_read_cr3(&svm->vcpu);
2418
2419         copy_vmcb_control_area(hsave, vmcb);
2420
2421         if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2422                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2423         else
2424                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2425
2426         if (nested_vmcb->control.nested_ctl) {
2427                 kvm_mmu_unload(&svm->vcpu);
2428                 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2429                 nested_svm_init_mmu_context(&svm->vcpu);
2430         }
2431
2432         /* Load the nested guest state */
2433         svm->vmcb->save.es = nested_vmcb->save.es;
2434         svm->vmcb->save.cs = nested_vmcb->save.cs;
2435         svm->vmcb->save.ss = nested_vmcb->save.ss;
2436         svm->vmcb->save.ds = nested_vmcb->save.ds;
2437         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2438         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2439         kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2440         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2441         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2442         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2443         if (npt_enabled) {
2444                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2445                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2446         } else
2447                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2448
2449         /* Guest paging mode is active - reset mmu */
2450         kvm_mmu_reset_context(&svm->vcpu);
2451
2452         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2453         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2454         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2455         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2456
2457         /* In case we don't even reach vcpu_run, the fields are not updated */
2458         svm->vmcb->save.rax = nested_vmcb->save.rax;
2459         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2460         svm->vmcb->save.rip = nested_vmcb->save.rip;
2461         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2462         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2463         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2464
2465         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2466         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
2467
2468         /* cache intercepts */
2469         svm->nested.intercept_cr         = nested_vmcb->control.intercept_cr;
2470         svm->nested.intercept_dr         = nested_vmcb->control.intercept_dr;
2471         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2472         svm->nested.intercept            = nested_vmcb->control.intercept;
2473
2474         svm_flush_tlb(&svm->vcpu);
2475         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2476         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2477                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2478         else
2479                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2480
2481         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2482                 /* We only want the cr8 intercept bits of the guest */
2483                 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2484                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2485         }
2486
2487         /* We don't want to see VMMCALLs from a nested guest */
2488         clr_intercept(svm, INTERCEPT_VMMCALL);
2489
2490         svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2491         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2492         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2493         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2494         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2495         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2496
2497         nested_svm_unmap(page);
2498
2499         /* Enter Guest-Mode */
2500         enter_guest_mode(&svm->vcpu);
2501
2502         /*
2503          * Merge guest and host intercepts - must be called  with vcpu in
2504          * guest-mode to take affect here
2505          */
2506         recalc_intercepts(svm);
2507
2508         svm->nested.vmcb = vmcb_gpa;
2509
2510         enable_gif(svm);
2511
2512         mark_all_dirty(svm->vmcb);
2513
2514         return true;
2515 }
2516
2517 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2518 {
2519         to_vmcb->save.fs = from_vmcb->save.fs;
2520         to_vmcb->save.gs = from_vmcb->save.gs;
2521         to_vmcb->save.tr = from_vmcb->save.tr;
2522         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2523         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2524         to_vmcb->save.star = from_vmcb->save.star;
2525         to_vmcb->save.lstar = from_vmcb->save.lstar;
2526         to_vmcb->save.cstar = from_vmcb->save.cstar;
2527         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2528         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2529         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2530         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2531 }
2532
2533 static int vmload_interception(struct vcpu_svm *svm)
2534 {
2535         struct vmcb *nested_vmcb;
2536         struct page *page;
2537
2538         if (nested_svm_check_permissions(svm))
2539                 return 1;
2540
2541         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2542         if (!nested_vmcb)
2543                 return 1;
2544
2545         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2546         skip_emulated_instruction(&svm->vcpu);
2547
2548         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2549         nested_svm_unmap(page);
2550
2551         return 1;
2552 }
2553
2554 static int vmsave_interception(struct vcpu_svm *svm)
2555 {
2556         struct vmcb *nested_vmcb;
2557         struct page *page;
2558
2559         if (nested_svm_check_permissions(svm))
2560                 return 1;
2561
2562         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2563         if (!nested_vmcb)
2564                 return 1;
2565
2566         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2567         skip_emulated_instruction(&svm->vcpu);
2568
2569         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2570         nested_svm_unmap(page);
2571
2572         return 1;
2573 }
2574
2575 static int vmrun_interception(struct vcpu_svm *svm)
2576 {
2577         if (nested_svm_check_permissions(svm))
2578                 return 1;
2579
2580         /* Save rip after vmrun instruction */
2581         kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2582
2583         if (!nested_svm_vmrun(svm))
2584                 return 1;
2585
2586         if (!nested_svm_vmrun_msrpm(svm))
2587                 goto failed;
2588
2589         return 1;
2590
2591 failed:
2592
2593         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
2594         svm->vmcb->control.exit_code_hi = 0;
2595         svm->vmcb->control.exit_info_1  = 0;
2596         svm->vmcb->control.exit_info_2  = 0;
2597
2598         nested_svm_vmexit(svm);
2599
2600         return 1;
2601 }
2602
2603 static int stgi_interception(struct vcpu_svm *svm)
2604 {
2605         if (nested_svm_check_permissions(svm))
2606                 return 1;
2607
2608         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2609         skip_emulated_instruction(&svm->vcpu);
2610         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2611
2612         enable_gif(svm);
2613
2614         return 1;
2615 }
2616
2617 static int clgi_interception(struct vcpu_svm *svm)
2618 {
2619         if (nested_svm_check_permissions(svm))
2620                 return 1;
2621
2622         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2623         skip_emulated_instruction(&svm->vcpu);
2624
2625         disable_gif(svm);
2626
2627         /* After a CLGI no interrupts should come */
2628         svm_clear_vintr(svm);
2629         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2630
2631         mark_dirty(svm->vmcb, VMCB_INTR);
2632
2633         return 1;
2634 }
2635
2636 static int invlpga_interception(struct vcpu_svm *svm)
2637 {
2638         struct kvm_vcpu *vcpu = &svm->vcpu;
2639
2640         trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2641                           vcpu->arch.regs[VCPU_REGS_RAX]);
2642
2643         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2644         kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2645
2646         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2647         skip_emulated_instruction(&svm->vcpu);
2648         return 1;
2649 }
2650
2651 static int skinit_interception(struct vcpu_svm *svm)
2652 {
2653         trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2654
2655         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2656         return 1;
2657 }
2658
2659 static int xsetbv_interception(struct vcpu_svm *svm)
2660 {
2661         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2662         u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
2663
2664         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2665                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2666                 skip_emulated_instruction(&svm->vcpu);
2667         }
2668
2669         return 1;
2670 }
2671
2672 static int invalid_op_interception(struct vcpu_svm *svm)
2673 {
2674         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2675         return 1;
2676 }
2677
2678 static int task_switch_interception(struct vcpu_svm *svm)
2679 {
2680         u16 tss_selector;
2681         int reason;
2682         int int_type = svm->vmcb->control.exit_int_info &
2683                 SVM_EXITINTINFO_TYPE_MASK;
2684         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2685         uint32_t type =
2686                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2687         uint32_t idt_v =
2688                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2689         bool has_error_code = false;
2690         u32 error_code = 0;
2691
2692         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2693
2694         if (svm->vmcb->control.exit_info_2 &
2695             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2696                 reason = TASK_SWITCH_IRET;
2697         else if (svm->vmcb->control.exit_info_2 &
2698                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2699                 reason = TASK_SWITCH_JMP;
2700         else if (idt_v)
2701                 reason = TASK_SWITCH_GATE;
2702         else
2703                 reason = TASK_SWITCH_CALL;
2704
2705         if (reason == TASK_SWITCH_GATE) {
2706                 switch (type) {
2707                 case SVM_EXITINTINFO_TYPE_NMI:
2708                         svm->vcpu.arch.nmi_injected = false;
2709                         break;
2710                 case SVM_EXITINTINFO_TYPE_EXEPT:
2711                         if (svm->vmcb->control.exit_info_2 &
2712                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2713                                 has_error_code = true;
2714                                 error_code =
2715                                         (u32)svm->vmcb->control.exit_info_2;
2716                         }
2717                         kvm_clear_exception_queue(&svm->vcpu);
2718                         break;
2719                 case SVM_EXITINTINFO_TYPE_INTR:
2720                         kvm_clear_interrupt_queue(&svm->vcpu);
2721                         break;
2722                 default:
2723                         break;
2724                 }
2725         }
2726
2727         if (reason != TASK_SWITCH_GATE ||
2728             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2729             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2730              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2731                 skip_emulated_instruction(&svm->vcpu);
2732
2733         if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2734                                 has_error_code, error_code) == EMULATE_FAIL) {
2735                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2736                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2737                 svm->vcpu.run->internal.ndata = 0;
2738                 return 0;
2739         }
2740         return 1;
2741 }
2742
2743 static int cpuid_interception(struct vcpu_svm *svm)
2744 {
2745         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2746         kvm_emulate_cpuid(&svm->vcpu);
2747         return 1;
2748 }
2749
2750 static int iret_interception(struct vcpu_svm *svm)
2751 {
2752         ++svm->vcpu.stat.nmi_window_exits;
2753         clr_intercept(svm, INTERCEPT_IRET);
2754         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2755         svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2756         return 1;
2757 }
2758
2759 static int invlpg_interception(struct vcpu_svm *svm)
2760 {
2761         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2762                 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2763
2764         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2765         skip_emulated_instruction(&svm->vcpu);
2766         return 1;
2767 }
2768
2769 static int emulate_on_interception(struct vcpu_svm *svm)
2770 {
2771         return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2772 }
2773
2774 static int rdpmc_interception(struct vcpu_svm *svm)
2775 {
2776         int err;
2777
2778         if (!static_cpu_has(X86_FEATURE_NRIPS))
2779                 return emulate_on_interception(svm);
2780
2781         err = kvm_rdpmc(&svm->vcpu);
2782         kvm_complete_insn_gp(&svm->vcpu, err);
2783
2784         return 1;
2785 }
2786
2787 bool check_selective_cr0_intercepted(struct vcpu_svm *svm, unsigned long val)
2788 {
2789         unsigned long cr0 = svm->vcpu.arch.cr0;
2790         bool ret = false;
2791         u64 intercept;
2792
2793         intercept = svm->nested.intercept;
2794
2795         if (!is_guest_mode(&svm->vcpu) ||
2796             (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
2797                 return false;
2798
2799         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2800         val &= ~SVM_CR0_SELECTIVE_MASK;
2801
2802         if (cr0 ^ val) {
2803                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2804                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2805         }
2806
2807         return ret;
2808 }
2809
2810 #define CR_VALID (1ULL << 63)
2811
2812 static int cr_interception(struct vcpu_svm *svm)
2813 {
2814         int reg, cr;
2815         unsigned long val;
2816         int err;
2817
2818         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2819                 return emulate_on_interception(svm);
2820
2821         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2822                 return emulate_on_interception(svm);
2823
2824         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2825         cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2826
2827         err = 0;
2828         if (cr >= 16) { /* mov to cr */
2829                 cr -= 16;
2830                 val = kvm_register_read(&svm->vcpu, reg);
2831                 switch (cr) {
2832                 case 0:
2833                         if (!check_selective_cr0_intercepted(svm, val))
2834                                 err = kvm_set_cr0(&svm->vcpu, val);
2835                         else
2836                                 return 1;
2837
2838                         break;
2839                 case 3:
2840                         err = kvm_set_cr3(&svm->vcpu, val);
2841                         break;
2842                 case 4:
2843                         err = kvm_set_cr4(&svm->vcpu, val);
2844                         break;
2845                 case 8:
2846                         err = kvm_set_cr8(&svm->vcpu, val);
2847                         break;
2848                 default:
2849                         WARN(1, "unhandled write to CR%d", cr);
2850                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2851                         return 1;
2852                 }
2853         } else { /* mov from cr */
2854                 switch (cr) {
2855                 case 0:
2856                         val = kvm_read_cr0(&svm->vcpu);
2857                         break;
2858                 case 2:
2859                         val = svm->vcpu.arch.cr2;
2860                         break;
2861                 case 3:
2862                         val = kvm_read_cr3(&svm->vcpu);
2863                         break;
2864                 case 4:
2865                         val = kvm_read_cr4(&svm->vcpu);
2866                         break;
2867                 case 8:
2868                         val = kvm_get_cr8(&svm->vcpu);
2869                         break;
2870                 default:
2871                         WARN(1, "unhandled read from CR%d", cr);
2872                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2873                         return 1;
2874                 }
2875                 kvm_register_write(&svm->vcpu, reg, val);
2876         }
2877         kvm_complete_insn_gp(&svm->vcpu, err);
2878
2879         return 1;
2880 }
2881
2882 static int dr_interception(struct vcpu_svm *svm)
2883 {
2884         int reg, dr;
2885         unsigned long val;
2886         int err;
2887
2888         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2889                 return emulate_on_interception(svm);
2890
2891         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2892         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2893
2894         if (dr >= 16) { /* mov to DRn */
2895                 val = kvm_register_read(&svm->vcpu, reg);
2896                 kvm_set_dr(&svm->vcpu, dr - 16, val);
2897         } else {
2898                 err = kvm_get_dr(&svm->vcpu, dr, &val);
2899                 if (!err)
2900                         kvm_register_write(&svm->vcpu, reg, val);
2901         }
2902
2903         skip_emulated_instruction(&svm->vcpu);
2904
2905         return 1;
2906 }
2907
2908 static int cr8_write_interception(struct vcpu_svm *svm)
2909 {
2910         struct kvm_run *kvm_run = svm->vcpu.run;
2911         int r;
2912
2913         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2914         /* instruction emulation calls kvm_set_cr8() */
2915         r = cr_interception(svm);
2916         if (irqchip_in_kernel(svm->vcpu.kvm)) {
2917                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2918                 return r;
2919         }
2920         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2921                 return r;
2922         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2923         return 0;
2924 }
2925
2926 u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu)
2927 {
2928         struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu));
2929         return vmcb->control.tsc_offset +
2930                 svm_scale_tsc(vcpu, native_read_tsc());
2931 }
2932
2933 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2934 {
2935         struct vcpu_svm *svm = to_svm(vcpu);
2936
2937         switch (ecx) {
2938         case MSR_IA32_TSC: {
2939                 *data = svm->vmcb->control.tsc_offset +
2940                         svm_scale_tsc(vcpu, native_read_tsc());
2941
2942                 break;
2943         }
2944         case MSR_STAR:
2945                 *data = svm->vmcb->save.star;
2946                 break;
2947 #ifdef CONFIG_X86_64
2948         case MSR_LSTAR:
2949                 *data = svm->vmcb->save.lstar;
2950                 break;
2951         case MSR_CSTAR:
2952                 *data = svm->vmcb->save.cstar;
2953                 break;
2954         case MSR_KERNEL_GS_BASE:
2955                 *data = svm->vmcb->save.kernel_gs_base;
2956                 break;
2957         case MSR_SYSCALL_MASK:
2958                 *data = svm->vmcb->save.sfmask;
2959                 break;
2960 #endif
2961         case MSR_IA32_SYSENTER_CS:
2962                 *data = svm->vmcb->save.sysenter_cs;
2963                 break;
2964         case MSR_IA32_SYSENTER_EIP:
2965                 *data = svm->sysenter_eip;
2966                 break;
2967         case MSR_IA32_SYSENTER_ESP:
2968                 *data = svm->sysenter_esp;
2969                 break;
2970         /*
2971          * Nobody will change the following 5 values in the VMCB so we can
2972          * safely return them on rdmsr. They will always be 0 until LBRV is
2973          * implemented.
2974          */
2975         case MSR_IA32_DEBUGCTLMSR:
2976                 *data = svm->vmcb->save.dbgctl;
2977                 break;
2978         case MSR_IA32_LASTBRANCHFROMIP:
2979                 *data = svm->vmcb->save.br_from;
2980                 break;
2981         case MSR_IA32_LASTBRANCHTOIP:
2982                 *data = svm->vmcb->save.br_to;
2983                 break;
2984         case MSR_IA32_LASTINTFROMIP:
2985                 *data = svm->vmcb->save.last_excp_from;
2986                 break;
2987         case MSR_IA32_LASTINTTOIP:
2988                 *data = svm->vmcb->save.last_excp_to;
2989                 break;
2990         case MSR_VM_HSAVE_PA:
2991                 *data = svm->nested.hsave_msr;
2992                 break;
2993         case MSR_VM_CR:
2994                 *data = svm->nested.vm_cr_msr;
2995                 break;
2996         case MSR_IA32_UCODE_REV:
2997                 *data = 0x01000065;
2998                 break;
2999         default:
3000                 return kvm_get_msr_common(vcpu, ecx, data);
3001         }
3002         return 0;
3003 }
3004
3005 static int rdmsr_interception(struct vcpu_svm *svm)
3006 {
3007         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3008         u64 data;
3009
3010         if (svm_get_msr(&svm->vcpu, ecx, &data)) {
3011                 trace_kvm_msr_read_ex(ecx);
3012                 kvm_inject_gp(&svm->vcpu, 0);
3013         } else {
3014                 trace_kvm_msr_read(ecx, data);
3015
3016                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
3017                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
3018                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3019                 skip_emulated_instruction(&svm->vcpu);
3020         }
3021         return 1;
3022 }
3023
3024 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3025 {
3026         struct vcpu_svm *svm = to_svm(vcpu);
3027         int svm_dis, chg_mask;
3028
3029         if (data & ~SVM_VM_CR_VALID_MASK)
3030                 return 1;
3031
3032         chg_mask = SVM_VM_CR_VALID_MASK;
3033
3034         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3035                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3036
3037         svm->nested.vm_cr_msr &= ~chg_mask;
3038         svm->nested.vm_cr_msr |= (data & chg_mask);
3039
3040         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3041
3042         /* check for svm_disable while efer.svme is set */
3043         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3044                 return 1;
3045
3046         return 0;
3047 }
3048
3049 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
3050 {
3051         struct vcpu_svm *svm = to_svm(vcpu);
3052
3053         switch (ecx) {
3054         case MSR_IA32_TSC:
3055                 kvm_write_tsc(vcpu, data);
3056                 break;
3057         case MSR_STAR:
3058                 svm->vmcb->save.star = data;
3059                 break;
3060 #ifdef CONFIG_X86_64
3061         case MSR_LSTAR:
3062                 svm->vmcb->save.lstar = data;
3063                 break;
3064         case MSR_CSTAR:
3065                 svm->vmcb->save.cstar = data;
3066                 break;
3067         case MSR_KERNEL_GS_BASE:
3068                 svm->vmcb->save.kernel_gs_base = data;
3069                 break;
3070         case MSR_SYSCALL_MASK:
3071                 svm->vmcb->save.sfmask = data;
3072                 break;
3073 #endif
3074         case MSR_IA32_SYSENTER_CS:
3075                 svm->vmcb->save.sysenter_cs = data;
3076                 break;
3077         case MSR_IA32_SYSENTER_EIP:
3078                 svm->sysenter_eip = data;
3079                 svm->vmcb->save.sysenter_eip = data;
3080                 break;
3081         case MSR_IA32_SYSENTER_ESP:
3082                 svm->sysenter_esp = data;
3083                 svm->vmcb->save.sysenter_esp = data;
3084                 break;
3085         case MSR_IA32_DEBUGCTLMSR:
3086                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3087                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3088                                         __func__, data);
3089                         break;
3090                 }
3091                 if (data & DEBUGCTL_RESERVED_BITS)
3092                         return 1;
3093
3094                 svm->vmcb->save.dbgctl = data;
3095                 mark_dirty(svm->vmcb, VMCB_LBR);
3096                 if (data & (1ULL<<0))
3097                         svm_enable_lbrv(svm);
3098                 else
3099                         svm_disable_lbrv(svm);
3100                 break;
3101         case MSR_VM_HSAVE_PA:
3102                 svm->nested.hsave_msr = data;
3103                 break;
3104         case MSR_VM_CR:
3105                 return svm_set_vm_cr(vcpu, data);
3106         case MSR_VM_IGNNE:
3107                 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3108                 break;
3109         default:
3110                 return kvm_set_msr_common(vcpu, ecx, data);
3111         }
3112         return 0;
3113 }
3114
3115 static int wrmsr_interception(struct vcpu_svm *svm)
3116 {
3117         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3118         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
3119                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3120
3121
3122         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3123         if (svm_set_msr(&svm->vcpu, ecx, data)) {
3124                 trace_kvm_msr_write_ex(ecx, data);
3125                 kvm_inject_gp(&svm->vcpu, 0);
3126         } else {
3127                 trace_kvm_msr_write(ecx, data);
3128                 skip_emulated_instruction(&svm->vcpu);
3129         }
3130         return 1;
3131 }
3132
3133 static int msr_interception(struct vcpu_svm *svm)
3134 {
3135         if (svm->vmcb->control.exit_info_1)
3136                 return wrmsr_interception(svm);
3137         else
3138                 return rdmsr_interception(svm);
3139 }
3140
3141 static int interrupt_window_interception(struct vcpu_svm *svm)
3142 {
3143         struct kvm_run *kvm_run = svm->vcpu.run;
3144
3145         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3146         svm_clear_vintr(svm);
3147         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3148         mark_dirty(svm->vmcb, VMCB_INTR);
3149         /*
3150          * If the user space waits to inject interrupts, exit as soon as
3151          * possible
3152          */
3153         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
3154             kvm_run->request_interrupt_window &&
3155             !kvm_cpu_has_interrupt(&svm->vcpu)) {
3156                 ++svm->vcpu.stat.irq_window_exits;
3157                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3158                 return 0;
3159         }
3160
3161         return 1;
3162 }
3163
3164 static int pause_interception(struct vcpu_svm *svm)
3165 {
3166         kvm_vcpu_on_spin(&(svm->vcpu));
3167         return 1;
3168 }
3169
3170 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
3171         [SVM_EXIT_READ_CR0]                     = cr_interception,
3172         [SVM_EXIT_READ_CR3]                     = cr_interception,
3173         [SVM_EXIT_READ_CR4]                     = cr_interception,
3174         [SVM_EXIT_READ_CR8]                     = cr_interception,
3175         [SVM_EXIT_CR0_SEL_WRITE]                = emulate_on_interception,
3176         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
3177         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
3178         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
3179         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
3180         [SVM_EXIT_READ_DR0]                     = dr_interception,
3181         [SVM_EXIT_READ_DR1]                     = dr_interception,
3182         [SVM_EXIT_READ_DR2]                     = dr_interception,
3183         [SVM_EXIT_READ_DR3]                     = dr_interception,
3184         [SVM_EXIT_READ_DR4]                     = dr_interception,
3185         [SVM_EXIT_READ_DR5]                     = dr_interception,
3186         [SVM_EXIT_READ_DR6]                     = dr_interception,
3187         [SVM_EXIT_READ_DR7]                     = dr_interception,
3188         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
3189         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
3190         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
3191         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
3192         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
3193         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
3194         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
3195         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
3196         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
3197         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
3198         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
3199         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
3200         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
3201         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
3202         [SVM_EXIT_INTR]                         = intr_interception,
3203         [SVM_EXIT_NMI]                          = nmi_interception,
3204         [SVM_EXIT_SMI]                          = nop_on_interception,
3205         [SVM_EXIT_INIT]                         = nop_on_interception,
3206         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
3207         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
3208         [SVM_EXIT_CPUID]                        = cpuid_interception,
3209         [SVM_EXIT_IRET]                         = iret_interception,
3210         [SVM_EXIT_INVD]                         = emulate_on_interception,
3211         [SVM_EXIT_PAUSE]                        = pause_interception,
3212         [SVM_EXIT_HLT]                          = halt_interception,
3213         [SVM_EXIT_INVLPG]                       = invlpg_interception,
3214         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
3215         [SVM_EXIT_IOIO]                         = io_interception,
3216         [SVM_EXIT_MSR]                          = msr_interception,
3217         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
3218         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
3219         [SVM_EXIT_VMRUN]                        = vmrun_interception,
3220         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
3221         [SVM_EXIT_VMLOAD]                       = vmload_interception,
3222         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
3223         [SVM_EXIT_STGI]                         = stgi_interception,
3224         [SVM_EXIT_CLGI]                         = clgi_interception,
3225         [SVM_EXIT_SKINIT]                       = skinit_interception,
3226         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
3227         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
3228         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
3229         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
3230         [SVM_EXIT_NPF]                          = pf_interception,
3231 };
3232
3233 static void dump_vmcb(struct kvm_vcpu *vcpu)
3234 {
3235         struct vcpu_svm *svm = to_svm(vcpu);
3236         struct vmcb_control_area *control = &svm->vmcb->control;
3237         struct vmcb_save_area *save = &svm->vmcb->save;
3238
3239         pr_err("VMCB Control Area:\n");
3240         pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
3241         pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
3242         pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
3243         pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
3244         pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
3245         pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
3246         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3247         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3248         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3249         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3250         pr_err("%-20s%d\n", "asid:", control->asid);
3251         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3252         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3253         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3254         pr_err("%-20s%08x\n", "int_state:", control->int_state);
3255         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3256         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3257         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3258         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3259         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3260         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3261         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3262         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3263         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3264         pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
3265         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3266         pr_err("VMCB State Save Area:\n");
3267         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3268                "es:",
3269                save->es.selector, save->es.attrib,
3270                save->es.limit, save->es.base);
3271         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3272                "cs:",
3273                save->cs.selector, save->cs.attrib,
3274                save->cs.limit, save->cs.base);
3275         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3276                "ss:",
3277                save->ss.selector, save->ss.attrib,
3278                save->ss.limit, save->ss.base);
3279         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3280                "ds:",
3281                save->ds.selector, save->ds.attrib,
3282                save->ds.limit, save->ds.base);
3283         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3284                "fs:",
3285                save->fs.selector, save->fs.attrib,
3286                save->fs.limit, save->fs.base);
3287         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3288                "gs:",
3289                save->gs.selector, save->gs.attrib,
3290                save->gs.limit, save->gs.base);
3291         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3292                "gdtr:",
3293                save->gdtr.selector, save->gdtr.attrib,
3294                save->gdtr.limit, save->gdtr.base);
3295         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3296                "ldtr:",
3297                save->ldtr.selector, save->ldtr.attrib,
3298                save->ldtr.limit, save->ldtr.base);
3299         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3300                "idtr:",
3301                save->idtr.selector, save->idtr.attrib,
3302                save->idtr.limit, save->idtr.base);
3303         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3304                "tr:",
3305                save->tr.selector, save->tr.attrib,
3306                save->tr.limit, save->tr.base);
3307         pr_err("cpl:            %d                efer:         %016llx\n",
3308                 save->cpl, save->efer);
3309         pr_err("%-15s %016llx %-13s %016llx\n",
3310                "cr0:", save->cr0, "cr2:", save->cr2);
3311         pr_err("%-15s %016llx %-13s %016llx\n",
3312                "cr3:", save->cr3, "cr4:", save->cr4);
3313         pr_err("%-15s %016llx %-13s %016llx\n",
3314                "dr6:", save->dr6, "dr7:", save->dr7);
3315         pr_err("%-15s %016llx %-13s %016llx\n",
3316                "rip:", save->rip, "rflags:", save->rflags);
3317         pr_err("%-15s %016llx %-13s %016llx\n",
3318                "rsp:", save->rsp, "rax:", save->rax);
3319         pr_err("%-15s %016llx %-13s %016llx\n",
3320                "star:", save->star, "lstar:", save->lstar);
3321         pr_err("%-15s %016llx %-13s %016llx\n",
3322                "cstar:", save->cstar, "sfmask:", save->sfmask);
3323         pr_err("%-15s %016llx %-13s %016llx\n",
3324                "kernel_gs_base:", save->kernel_gs_base,
3325                "sysenter_cs:", save->sysenter_cs);
3326         pr_err("%-15s %016llx %-13s %016llx\n",
3327                "sysenter_esp:", save->sysenter_esp,
3328                "sysenter_eip:", save->sysenter_eip);
3329         pr_err("%-15s %016llx %-13s %016llx\n",
3330                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3331         pr_err("%-15s %016llx %-13s %016llx\n",
3332                "br_from:", save->br_from, "br_to:", save->br_to);
3333         pr_err("%-15s %016llx %-13s %016llx\n",
3334                "excp_from:", save->last_excp_from,
3335                "excp_to:", save->last_excp_to);
3336 }
3337
3338 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3339 {
3340         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3341
3342         *info1 = control->exit_info_1;
3343         *info2 = control->exit_info_2;
3344 }
3345
3346 static int handle_exit(struct kvm_vcpu *vcpu)
3347 {
3348         struct vcpu_svm *svm = to_svm(vcpu);
3349         struct kvm_run *kvm_run = vcpu->run;
3350         u32 exit_code = svm->vmcb->control.exit_code;
3351
3352         if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3353                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3354         if (npt_enabled)
3355                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3356
3357         if (unlikely(svm->nested.exit_required)) {
3358                 nested_svm_vmexit(svm);
3359                 svm->nested.exit_required = false;
3360
3361                 return 1;
3362         }
3363
3364         if (is_guest_mode(vcpu)) {
3365                 int vmexit;
3366
3367                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3368                                         svm->vmcb->control.exit_info_1,
3369                                         svm->vmcb->control.exit_info_2,
3370                                         svm->vmcb->control.exit_int_info,
3371                                         svm->vmcb->control.exit_int_info_err,
3372                                         KVM_ISA_SVM);
3373
3374                 vmexit = nested_svm_exit_special(svm);
3375
3376                 if (vmexit == NESTED_EXIT_CONTINUE)
3377                         vmexit = nested_svm_exit_handled(svm);
3378
3379                 if (vmexit == NESTED_EXIT_DONE)
3380                         return 1;
3381         }
3382
3383         svm_complete_interrupts(svm);
3384
3385         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3386                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3387                 kvm_run->fail_entry.hardware_entry_failure_reason
3388                         = svm->vmcb->control.exit_code;
3389                 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3390                 dump_vmcb(vcpu);
3391                 return 0;
3392         }
3393
3394         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3395             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3396             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3397             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3398                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3399                        "exit_code 0x%x\n",
3400                        __func__, svm->vmcb->control.exit_int_info,
3401                        exit_code);
3402
3403         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3404             || !svm_exit_handlers[exit_code]) {
3405                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3406                 kvm_run->hw.hardware_exit_reason = exit_code;
3407                 return 0;
3408         }
3409
3410         return svm_exit_handlers[exit_code](svm);
3411 }
3412
3413 static void reload_tss(struct kvm_vcpu *vcpu)
3414 {
3415         int cpu = raw_smp_processor_id();
3416
3417         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3418         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3419         load_TR_desc();
3420 }
3421
3422 static void pre_svm_run(struct vcpu_svm *svm)
3423 {
3424         int cpu = raw_smp_processor_id();
3425
3426         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3427
3428         /* FIXME: handle wraparound of asid_generation */
3429         if (svm->asid_generation != sd->asid_generation)
3430                 new_asid(svm, sd);
3431 }
3432
3433 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3434 {
3435         struct vcpu_svm *svm = to_svm(vcpu);
3436
3437         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3438         vcpu->arch.hflags |= HF_NMI_MASK;
3439         set_intercept(svm, INTERCEPT_IRET);
3440         ++vcpu->stat.nmi_injections;
3441 }
3442
3443 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3444 {
3445         struct vmcb_control_area *control;
3446
3447         control = &svm->vmcb->control;
3448         control->int_vector = irq;
3449         control->int_ctl &= ~V_INTR_PRIO_MASK;
3450         control->int_ctl |= V_IRQ_MASK |
3451                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3452         mark_dirty(svm->vmcb, VMCB_INTR);
3453 }
3454
3455 static void svm_set_irq(struct kvm_vcpu *vcpu)
3456 {
3457         struct vcpu_svm *svm = to_svm(vcpu);
3458
3459         BUG_ON(!(gif_set(svm)));
3460
3461         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3462         ++vcpu->stat.irq_injections;
3463
3464         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3465                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3466 }
3467
3468 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3469 {
3470         struct vcpu_svm *svm = to_svm(vcpu);
3471
3472         if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3473                 return;
3474
3475         if (irr == -1)
3476                 return;
3477
3478         if (tpr >= irr)
3479                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3480 }
3481
3482 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3483 {
3484         struct vcpu_svm *svm = to_svm(vcpu);
3485         struct vmcb *vmcb = svm->vmcb;
3486         int ret;
3487         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3488               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3489         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3490
3491         return ret;
3492 }
3493
3494 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3495 {
3496         struct vcpu_svm *svm = to_svm(vcpu);
3497
3498         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3499 }
3500
3501 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3502 {
3503         struct vcpu_svm *svm = to_svm(vcpu);
3504
3505         if (masked) {
3506                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3507                 set_intercept(svm, INTERCEPT_IRET);
3508         } else {
3509                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3510                 clr_intercept(svm, INTERCEPT_IRET);
3511         }
3512 }
3513
3514 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3515 {
3516         struct vcpu_svm *svm = to_svm(vcpu);
3517         struct vmcb *vmcb = svm->vmcb;
3518         int ret;
3519
3520         if (!gif_set(svm) ||
3521              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3522                 return 0;
3523
3524         ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
3525
3526         if (is_guest_mode(vcpu))
3527                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3528
3529         return ret;
3530 }
3531
3532 static void enable_irq_window(struct kvm_vcpu *vcpu)
3533 {
3534         struct vcpu_svm *svm = to_svm(vcpu);
3535
3536         /*
3537          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3538          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
3539          * get that intercept, this function will be called again though and
3540          * we'll get the vintr intercept.
3541          */
3542         if (gif_set(svm) && nested_svm_intr(svm)) {
3543                 svm_set_vintr(svm);
3544                 svm_inject_irq(svm, 0x0);
3545         }
3546 }
3547
3548 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3549 {
3550         struct vcpu_svm *svm = to_svm(vcpu);
3551
3552         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3553             == HF_NMI_MASK)
3554                 return; /* IRET will cause a vm exit */
3555
3556         /*
3557          * Something prevents NMI from been injected. Single step over possible
3558          * problem (IRET or exception injection or interrupt shadow)
3559          */
3560         svm->nmi_singlestep = true;
3561         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3562         update_db_intercept(vcpu);
3563 }
3564
3565 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3566 {
3567         return 0;
3568 }
3569
3570 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3571 {
3572         struct vcpu_svm *svm = to_svm(vcpu);
3573
3574         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3575                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3576         else
3577                 svm->asid_generation--;
3578 }
3579
3580 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3581 {
3582 }
3583
3584 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3585 {
3586         struct vcpu_svm *svm = to_svm(vcpu);
3587
3588         if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3589                 return;
3590
3591         if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3592                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3593                 kvm_set_cr8(vcpu, cr8);
3594         }
3595 }
3596
3597 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3598 {
3599         struct vcpu_svm *svm = to_svm(vcpu);
3600         u64 cr8;
3601
3602         if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3603                 return;
3604
3605         cr8 = kvm_get_cr8(vcpu);
3606         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3607         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3608 }
3609
3610 static void svm_complete_interrupts(struct vcpu_svm *svm)
3611 {
3612         u8 vector;
3613         int type;
3614         u32 exitintinfo = svm->vmcb->control.exit_int_info;
3615         unsigned int3_injected = svm->int3_injected;
3616
3617         svm->int3_injected = 0;
3618
3619         /*
3620          * If we've made progress since setting HF_IRET_MASK, we've
3621          * executed an IRET and can allow NMI injection.
3622          */
3623         if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3624             && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3625                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3626                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3627         }
3628
3629         svm->vcpu.arch.nmi_injected = false;
3630         kvm_clear_exception_queue(&svm->vcpu);
3631         kvm_clear_interrupt_queue(&svm->vcpu);
3632
3633         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3634                 return;
3635
3636         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3637
3638         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3639         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3640
3641         switch (type) {
3642         case SVM_EXITINTINFO_TYPE_NMI:
3643                 svm->vcpu.arch.nmi_injected = true;
3644                 break;
3645         case SVM_EXITINTINFO_TYPE_EXEPT:
3646                 /*
3647                  * In case of software exceptions, do not reinject the vector,
3648                  * but re-execute the instruction instead. Rewind RIP first
3649                  * if we emulated INT3 before.
3650                  */
3651                 if (kvm_exception_is_soft(vector)) {
3652                         if (vector == BP_VECTOR && int3_injected &&
3653                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3654                                 kvm_rip_write(&svm->vcpu,
3655                                               kvm_rip_read(&svm->vcpu) -
3656                                               int3_injected);
3657                         break;
3658                 }
3659                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3660                         u32 err = svm->vmcb->control.exit_int_info_err;
3661                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
3662
3663                 } else
3664                         kvm_requeue_exception(&svm->vcpu, vector);
3665                 break;
3666         case SVM_EXITINTINFO_TYPE_INTR:
3667                 kvm_queue_interrupt(&svm->vcpu, vector, false);
3668                 break;
3669         default:
3670                 break;
3671         }
3672 }
3673
3674 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3675 {
3676         struct vcpu_svm *svm = to_svm(vcpu);
3677         struct vmcb_control_area *control = &svm->vmcb->control;
3678
3679         control->exit_int_info = control->event_inj;
3680         control->exit_int_info_err = control->event_inj_err;
3681         control->event_inj = 0;
3682         svm_complete_interrupts(svm);
3683 }
3684
3685 #ifdef CONFIG_X86_64
3686 #define R "r"
3687 #else
3688 #define R "e"
3689 #endif
3690
3691 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3692 {
3693         struct vcpu_svm *svm = to_svm(vcpu);
3694
3695         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3696         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3697         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3698
3699         /*
3700          * A vmexit emulation is required before the vcpu can be executed
3701          * again.
3702          */
3703         if (unlikely(svm->nested.exit_required))
3704                 return;
3705
3706         pre_svm_run(svm);
3707
3708         sync_lapic_to_cr8(vcpu);
3709
3710         svm->vmcb->save.cr2 = vcpu->arch.cr2;
3711
3712         clgi();
3713
3714         local_irq_enable();
3715
3716         asm volatile (
3717                 "push %%"R"bp; \n\t"
3718                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3719                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3720                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3721                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3722                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3723                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3724 #ifdef CONFIG_X86_64
3725                 "mov %c[r8](%[svm]),  %%r8  \n\t"
3726                 "mov %c[r9](%[svm]),  %%r9  \n\t"
3727                 "mov %c[r10](%[svm]), %%r10 \n\t"
3728                 "mov %c[r11](%[svm]), %%r11 \n\t"
3729                 "mov %c[r12](%[svm]), %%r12 \n\t"
3730                 "mov %c[r13](%[svm]), %%r13 \n\t"
3731                 "mov %c[r14](%[svm]), %%r14 \n\t"
3732                 "mov %c[r15](%[svm]), %%r15 \n\t"
3733 #endif
3734
3735                 /* Enter guest mode */
3736                 "push %%"R"ax \n\t"
3737                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3738                 __ex(SVM_VMLOAD) "\n\t"
3739                 __ex(SVM_VMRUN) "\n\t"
3740                 __ex(SVM_VMSAVE) "\n\t"
3741                 "pop %%"R"ax \n\t"
3742
3743                 /* Save guest registers, load host registers */
3744                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3745                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3746                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3747                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3748                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3749                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3750 #ifdef CONFIG_X86_64
3751                 "mov %%r8,  %c[r8](%[svm]) \n\t"
3752                 "mov %%r9,  %c[r9](%[svm]) \n\t"
3753                 "mov %%r10, %c[r10](%[svm]) \n\t"
3754                 "mov %%r11, %c[r11](%[svm]) \n\t"
3755                 "mov %%r12, %c[r12](%[svm]) \n\t"
3756                 "mov %%r13, %c[r13](%[svm]) \n\t"
3757                 "mov %%r14, %c[r14](%[svm]) \n\t"
3758                 "mov %%r15, %c[r15](%[svm]) \n\t"
3759 #endif
3760                 "pop %%"R"bp"
3761                 :
3762                 : [svm]"a"(svm),
3763                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3764                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3765                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3766                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3767                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3768                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3769                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3770 #ifdef CONFIG_X86_64
3771                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3772                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3773                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3774                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3775                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3776                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3777                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3778                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3779 #endif
3780                 : "cc", "memory"
3781                 , R"bx", R"cx", R"dx", R"si", R"di"
3782 #ifdef CONFIG_X86_64
3783                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3784 #endif
3785                 );
3786
3787 #ifdef CONFIG_X86_64
3788         wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3789 #else
3790         loadsegment(fs, svm->host.fs);
3791 #ifndef CONFIG_X86_32_LAZY_GS
3792         loadsegment(gs, svm->host.gs);
3793 #endif
3794 #endif
3795
3796         reload_tss(vcpu);
3797
3798         local_irq_disable();
3799
3800         vcpu->arch.cr2 = svm->vmcb->save.cr2;
3801         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3802         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3803         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3804
3805         trace_kvm_exit(svm->vmcb->control.exit_code, vcpu, KVM_ISA_SVM);
3806
3807         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3808                 kvm_before_handle_nmi(&svm->vcpu);
3809
3810         stgi();
3811
3812         /* Any pending NMI will happen here */
3813
3814         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3815                 kvm_after_handle_nmi(&svm->vcpu);
3816
3817         sync_cr8_to_lapic(vcpu);
3818
3819         svm->next_rip = 0;
3820
3821         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3822
3823         /* if exit due to PF check for async PF */
3824         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3825                 svm->apf_reason = kvm_read_and_reset_pf_reason();
3826
3827         if (npt_enabled) {
3828                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3829                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3830         }
3831
3832         /*
3833          * We need to handle MC intercepts here before the vcpu has a chance to
3834          * change the physical cpu
3835          */
3836         if (unlikely(svm->vmcb->control.exit_code ==
3837                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
3838                 svm_handle_mce(svm);
3839
3840         mark_all_clean(svm->vmcb);
3841 }
3842
3843 #undef R
3844
3845 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3846 {
3847         struct vcpu_svm *svm = to_svm(vcpu);
3848
3849         svm->vmcb->save.cr3 = root;
3850         mark_dirty(svm->vmcb, VMCB_CR);
3851         svm_flush_tlb(vcpu);
3852 }
3853
3854 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3855 {
3856         struct vcpu_svm *svm = to_svm(vcpu);
3857
3858         svm->vmcb->control.nested_cr3 = root;
3859         mark_dirty(svm->vmcb, VMCB_NPT);
3860
3861         /* Also sync guest cr3 here in case we live migrate */
3862         svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
3863         mark_dirty(svm->vmcb, VMCB_CR);
3864
3865         svm_flush_tlb(vcpu);
3866 }
3867
3868 static int is_disabled(void)
3869 {
3870         u64 vm_cr;
3871
3872         rdmsrl(MSR_VM_CR, vm_cr);
3873         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3874                 return 1;
3875
3876         return 0;
3877 }
3878
3879 static void
3880 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3881 {
3882         /*
3883          * Patch in the VMMCALL instruction:
3884          */
3885         hypercall[0] = 0x0f;
3886         hypercall[1] = 0x01;
3887         hypercall[2] = 0xd9;
3888 }
3889
3890 static void svm_check_processor_compat(void *rtn)
3891 {
3892         *(int *)rtn = 0;
3893 }
3894
3895 static bool svm_cpu_has_accelerated_tpr(void)
3896 {
3897         return false;
3898 }
3899
3900 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3901 {
3902         return 0;
3903 }
3904
3905 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3906 {
3907 }
3908
3909 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3910 {
3911         switch (func) {
3912         case 0x80000001:
3913                 if (nested)
3914                         entry->ecx |= (1 << 2); /* Set SVM bit */
3915                 break;
3916         case 0x8000000A:
3917                 entry->eax = 1; /* SVM revision 1 */
3918                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3919                                    ASID emulation to nested SVM */
3920                 entry->ecx = 0; /* Reserved */
3921                 entry->edx = 0; /* Per default do not support any
3922                                    additional features */
3923
3924                 /* Support next_rip if host supports it */
3925                 if (boot_cpu_has(X86_FEATURE_NRIPS))
3926                         entry->edx |= SVM_FEATURE_NRIP;
3927
3928                 /* Support NPT for the guest if enabled */
3929                 if (npt_enabled)
3930                         entry->edx |= SVM_FEATURE_NPT;
3931
3932                 break;
3933         }
3934 }
3935
3936 static int svm_get_lpage_level(void)
3937 {
3938         return PT_PDPE_LEVEL;
3939 }
3940
3941 static bool svm_rdtscp_supported(void)
3942 {
3943         return false;
3944 }
3945
3946 static bool svm_has_wbinvd_exit(void)
3947 {
3948         return true;
3949 }
3950
3951 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3952 {
3953         struct vcpu_svm *svm = to_svm(vcpu);
3954
3955         set_exception_intercept(svm, NM_VECTOR);
3956         update_cr0_intercept(svm);
3957 }
3958
3959 #define PRE_EX(exit)  { .exit_code = (exit), \
3960                         .stage = X86_ICPT_PRE_EXCEPT, }
3961 #define POST_EX(exit) { .exit_code = (exit), \
3962                         .stage = X86_ICPT_POST_EXCEPT, }
3963 #define POST_MEM(exit) { .exit_code = (exit), \
3964                         .stage = X86_ICPT_POST_MEMACCESS, }
3965
3966 static struct __x86_intercept {
3967         u32 exit_code;
3968         enum x86_intercept_stage stage;
3969 } x86_intercept_map[] = {
3970         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
3971         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
3972         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
3973         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
3974         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
3975         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
3976         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
3977         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
3978         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
3979         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
3980         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
3981         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
3982         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
3983         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
3984         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
3985         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
3986         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
3987         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
3988         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
3989         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
3990         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
3991         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
3992         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
3993         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
3994         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
3995         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
3996         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
3997         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
3998         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
3999         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
4000         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
4001         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
4002         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
4003         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
4004         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
4005         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
4006         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
4007         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
4008         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
4009         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
4010         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
4011         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
4012         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
4013         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
4014         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
4015         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
4016 };
4017
4018 #undef PRE_EX
4019 #undef POST_EX
4020 #undef POST_MEM
4021
4022 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4023                                struct x86_instruction_info *info,
4024                                enum x86_intercept_stage stage)
4025 {
4026         struct vcpu_svm *svm = to_svm(vcpu);
4027         int vmexit, ret = X86EMUL_CONTINUE;
4028         struct __x86_intercept icpt_info;
4029         struct vmcb *vmcb = svm->vmcb;
4030
4031         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4032                 goto out;
4033
4034         icpt_info = x86_intercept_map[info->intercept];
4035
4036         if (stage != icpt_info.stage)
4037                 goto out;
4038
4039         switch (icpt_info.exit_code) {
4040         case SVM_EXIT_READ_CR0:
4041                 if (info->intercept == x86_intercept_cr_read)
4042                         icpt_info.exit_code += info->modrm_reg;
4043                 break;
4044         case SVM_EXIT_WRITE_CR0: {
4045                 unsigned long cr0, val;
4046                 u64 intercept;
4047
4048                 if (info->intercept == x86_intercept_cr_write)
4049                         icpt_info.exit_code += info->modrm_reg;
4050
4051                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0)
4052                         break;
4053
4054                 intercept = svm->nested.intercept;
4055
4056                 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
4057                         break;
4058
4059                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4060                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
4061
4062                 if (info->intercept == x86_intercept_lmsw) {
4063                         cr0 &= 0xfUL;
4064                         val &= 0xfUL;
4065                         /* lmsw can't clear PE - catch this here */
4066                         if (cr0 & X86_CR0_PE)
4067                                 val |= X86_CR0_PE;
4068                 }
4069
4070                 if (cr0 ^ val)
4071                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4072
4073                 break;
4074         }
4075         case SVM_EXIT_READ_DR0:
4076         case SVM_EXIT_WRITE_DR0:
4077                 icpt_info.exit_code += info->modrm_reg;
4078                 break;
4079         case SVM_EXIT_MSR:
4080                 if (info->intercept == x86_intercept_wrmsr)
4081                         vmcb->control.exit_info_1 = 1;
4082                 else
4083                         vmcb->control.exit_info_1 = 0;
4084                 break;
4085         case SVM_EXIT_PAUSE:
4086                 /*
4087                  * We get this for NOP only, but pause
4088                  * is rep not, check this here
4089                  */
4090                 if (info->rep_prefix != REPE_PREFIX)
4091                         goto out;
4092         case SVM_EXIT_IOIO: {
4093                 u64 exit_info;
4094                 u32 bytes;
4095
4096                 exit_info = (vcpu->arch.regs[VCPU_REGS_RDX] & 0xffff) << 16;
4097
4098                 if (info->intercept == x86_intercept_in ||
4099                     info->intercept == x86_intercept_ins) {
4100                         exit_info |= SVM_IOIO_TYPE_MASK;
4101                         bytes = info->src_bytes;
4102                 } else {
4103                         bytes = info->dst_bytes;
4104                 }
4105
4106                 if (info->intercept == x86_intercept_outs ||
4107                     info->intercept == x86_intercept_ins)
4108                         exit_info |= SVM_IOIO_STR_MASK;
4109
4110                 if (info->rep_prefix)
4111                         exit_info |= SVM_IOIO_REP_MASK;
4112
4113                 bytes = min(bytes, 4u);
4114
4115                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4116
4117                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4118
4119                 vmcb->control.exit_info_1 = exit_info;
4120                 vmcb->control.exit_info_2 = info->next_rip;
4121
4122                 break;
4123         }
4124         default:
4125                 break;
4126         }
4127
4128         vmcb->control.next_rip  = info->next_rip;
4129         vmcb->control.exit_code = icpt_info.exit_code;
4130         vmexit = nested_svm_exit_handled(svm);
4131
4132         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4133                                            : X86EMUL_CONTINUE;
4134
4135 out:
4136         return ret;
4137 }
4138
4139 static struct kvm_x86_ops svm_x86_ops = {
4140         .cpu_has_kvm_support = has_svm,
4141         .disabled_by_bios = is_disabled,
4142         .hardware_setup = svm_hardware_setup,
4143         .hardware_unsetup = svm_hardware_unsetup,
4144         .check_processor_compatibility = svm_check_processor_compat,
4145         .hardware_enable = svm_hardware_enable,
4146         .hardware_disable = svm_hardware_disable,
4147         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4148
4149         .vcpu_create = svm_create_vcpu,
4150         .vcpu_free = svm_free_vcpu,
4151         .vcpu_reset = svm_vcpu_reset,
4152
4153         .prepare_guest_switch = svm_prepare_guest_switch,
4154         .vcpu_load = svm_vcpu_load,
4155         .vcpu_put = svm_vcpu_put,
4156
4157         .set_guest_debug = svm_guest_debug,
4158         .get_msr = svm_get_msr,
4159         .set_msr = svm_set_msr,
4160         .get_segment_base = svm_get_segment_base,
4161         .get_segment = svm_get_segment,
4162         .set_segment = svm_set_segment,
4163         .get_cpl = svm_get_cpl,
4164         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4165         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
4166         .decache_cr3 = svm_decache_cr3,
4167         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
4168         .set_cr0 = svm_set_cr0,
4169         .set_cr3 = svm_set_cr3,
4170         .set_cr4 = svm_set_cr4,
4171         .set_efer = svm_set_efer,
4172         .get_idt = svm_get_idt,
4173         .set_idt = svm_set_idt,
4174         .get_gdt = svm_get_gdt,
4175         .set_gdt = svm_set_gdt,
4176         .set_dr7 = svm_set_dr7,
4177         .cache_reg = svm_cache_reg,
4178         .get_rflags = svm_get_rflags,
4179         .set_rflags = svm_set_rflags,
4180         .fpu_activate = svm_fpu_activate,
4181         .fpu_deactivate = svm_fpu_deactivate,
4182
4183         .tlb_flush = svm_flush_tlb,
4184
4185         .run = svm_vcpu_run,
4186         .handle_exit = handle_exit,
4187         .skip_emulated_instruction = skip_emulated_instruction,
4188         .set_interrupt_shadow = svm_set_interrupt_shadow,
4189         .get_interrupt_shadow = svm_get_interrupt_shadow,
4190         .patch_hypercall = svm_patch_hypercall,
4191         .set_irq = svm_set_irq,
4192         .set_nmi = svm_inject_nmi,
4193         .queue_exception = svm_queue_exception,
4194         .cancel_injection = svm_cancel_injection,
4195         .interrupt_allowed = svm_interrupt_allowed,
4196         .nmi_allowed = svm_nmi_allowed,
4197         .get_nmi_mask = svm_get_nmi_mask,
4198         .set_nmi_mask = svm_set_nmi_mask,
4199         .enable_nmi_window = enable_nmi_window,
4200         .enable_irq_window = enable_irq_window,
4201         .update_cr8_intercept = update_cr8_intercept,
4202
4203         .set_tss_addr = svm_set_tss_addr,
4204         .get_tdp_level = get_npt_level,
4205         .get_mt_mask = svm_get_mt_mask,
4206
4207         .get_exit_info = svm_get_exit_info,
4208
4209         .get_lpage_level = svm_get_lpage_level,
4210
4211         .cpuid_update = svm_cpuid_update,
4212
4213         .rdtscp_supported = svm_rdtscp_supported,
4214
4215         .set_supported_cpuid = svm_set_supported_cpuid,
4216
4217         .has_wbinvd_exit = svm_has_wbinvd_exit,
4218
4219         .set_tsc_khz = svm_set_tsc_khz,
4220         .write_tsc_offset = svm_write_tsc_offset,
4221         .adjust_tsc_offset = svm_adjust_tsc_offset,
4222         .compute_tsc_offset = svm_compute_tsc_offset,
4223         .read_l1_tsc = svm_read_l1_tsc,
4224
4225         .set_tdp_cr3 = set_tdp_cr3,
4226
4227         .check_intercept = svm_check_intercept,
4228 };
4229
4230 static int __init svm_init(void)
4231 {
4232         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
4233                         __alignof__(struct vcpu_svm), THIS_MODULE);
4234 }
4235
4236 static void __exit svm_exit(void)
4237 {
4238         kvm_exit();
4239 }
4240
4241 module_init(svm_init)
4242 module_exit(svm_exit)