arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright 2010 Red Hat, Inc. and/or its affilates.
   8  *
   9  * Authors:
  10  *   Yaniv Kamay  <yaniv@qumranet.com>
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17 #include <linux/kvm_host.h>
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "kvm_cache_regs.h"
  22 #include "x86.h"
  23
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/vmalloc.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/ftrace_event.h>
  30 #include <linux/slab.h>
  31
  32 #include <asm/tlbflush.h>
  33 #include <asm/desc.h>
  34
  35 #include <asm/virtext.h>
  36 #include "trace.h"
  37
  38 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  39
  40 MODULE_AUTHOR("Qumranet");
  41 MODULE_LICENSE("GPL");
  42
  43 #define IOPM_ALLOC_ORDER 2
  44 #define MSRPM_ALLOC_ORDER 1
  45
  46 #define SEG_TYPE_LDT 2
  47 #define SEG_TYPE_BUSY_TSS16 3
  48
  49 #define SVM_FEATURE_NPT            (1 <<  0)
  50 #define SVM_FEATURE_LBRV           (1 <<  1)
  51 #define SVM_FEATURE_SVML           (1 <<  2)
  52 #define SVM_FEATURE_NRIP           (1 <<  3)
  53 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  54
  55 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  56 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  57 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  58
  59 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  60
  61 static bool erratum_383_found __read_mostly;
  62
  63 static const u32 host_save_user_msrs[] = {
  64 #ifdef CONFIG_X86_64
  65         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  66         MSR_FS_BASE,
  67 #endif
  68         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  69 };
  70
  71 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  72
  73 struct kvm_vcpu;
  74
  75 struct nested_state {
  76         struct vmcb *hsave;
  77         u64 hsave_msr;
  78         u64 vm_cr_msr;
  79         u64 vmcb;
  80
  81         /* These are the merged vectors */
  82         u32 *msrpm;
  83
  84         /* gpa pointers to the real vectors */
  85         u64 vmcb_msrpm;
  86         u64 vmcb_iopm;
  87
  88         /* A VMEXIT is required but not yet emulated */
  89         bool exit_required;
  90
  91         /*
  92          * If we vmexit during an instruction emulation we need this to restore
  93          * the l1 guest rip after the emulation
  94          */
  95         unsigned long vmexit_rip;
  96         unsigned long vmexit_rsp;
  97         unsigned long vmexit_rax;
  98
  99         /* cache for intercepts of the guest */
 100         u16 intercept_cr_read;
 101         u16 intercept_cr_write;
 102         u16 intercept_dr_read;
 103         u16 intercept_dr_write;
 104         u32 intercept_exceptions;
 105         u64 intercept;
 106
 107         /* Nested Paging related state */
 108         u64 nested_cr3;
 109 };
 110
 111 #define MSRPM_OFFSETS   16
 112 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 113
 114 struct vcpu_svm {
 115         struct kvm_vcpu vcpu;
 116         struct vmcb *vmcb;
 117         unsigned long vmcb_pa;
 118         struct svm_cpu_data *svm_data;
 119         uint64_t asid_generation;
 120         uint64_t sysenter_esp;
 121         uint64_t sysenter_eip;
 122
 123         u64 next_rip;
 124
 125         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 126         u64 host_gs_base;
 127
 128         u32 *msrpm;
 129
 130         struct nested_state nested;
 131
 132         bool nmi_singlestep;
 133
 134         unsigned int3_injected;
 135         unsigned long int3_rip;
 136 };
 137
 138 #define MSR_INVALID                     0xffffffffU
 139
 140 static struct svm_direct_access_msrs {
 141         u32 index;   /* Index of the MSR */
 142         bool always; /* True if intercept is always on */
 143 } direct_access_msrs[] = {
 144         { .index = MSR_STAR,                            .always = true  },
 145         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 146 #ifdef CONFIG_X86_64
 147         { .index = MSR_GS_BASE,                         .always = true  },
 148         { .index = MSR_FS_BASE,                         .always = true  },
 149         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 150         { .index = MSR_LSTAR,                           .always = true  },
 151         { .index = MSR_CSTAR,                           .always = true  },
 152         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 153 #endif
 154         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 155         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 156         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 157         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 158         { .index = MSR_INVALID,                         .always = false },
 159 };
 160
 161 /* enable NPT for AMD64 and X86 with PAE */
 162 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 163 static bool npt_enabled = true;
 164 #else
 165 static bool npt_enabled;
 166 #endif
 167 static int npt = 1;
 168
 169 module_param(npt, int, S_IRUGO);
 170
 171 static int nested = 1;
 172 module_param(nested, int, S_IRUGO);
 173
 174 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 175 static void svm_complete_interrupts(struct vcpu_svm *svm);
 176
 177 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 178 static int nested_svm_intercept(struct vcpu_svm *svm);
 179 static int nested_svm_vmexit(struct vcpu_svm *svm);
 180 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 181                                       bool has_error_code, u32 error_code);
 182
 183 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 184 {
 185         return container_of(vcpu, struct vcpu_svm, vcpu);
 186 }
 187
 188 static inline bool is_nested(struct vcpu_svm *svm)
 189 {
 190         return svm->nested.vmcb;
 191 }
 192
 193 static inline void enable_gif(struct vcpu_svm *svm)
 194 {
 195         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 196 }
 197
 198 static inline void disable_gif(struct vcpu_svm *svm)
 199 {
 200         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 201 }
 202
 203 static inline bool gif_set(struct vcpu_svm *svm)
 204 {
 205         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 206 }
 207
 208 static unsigned long iopm_base;
 209
 210 struct kvm_ldttss_desc {
 211         u16 limit0;
 212         u16 base0;
 213         unsigned base1:8, type:5, dpl:2, p:1;
 214         unsigned limit1:4, zero0:3, g:1, base2:8;
 215         u32 base3;
 216         u32 zero1;
 217 } __attribute__((packed));
 218
 219 struct svm_cpu_data {
 220         int cpu;
 221
 222         u64 asid_generation;
 223         u32 max_asid;
 224         u32 next_asid;
 225         struct kvm_ldttss_desc *tss_desc;
 226
 227         struct page *save_area;
 228 };
 229
 230 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 231 static uint32_t svm_features;
 232
 233 struct svm_init_data {
 234         int cpu;
 235         int r;
 236 };
 237
 238 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 239
 240 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 241 #define MSRS_RANGE_SIZE 2048
 242 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 243
 244 static u32 svm_msrpm_offset(u32 msr)
 245 {
 246         u32 offset;
 247         int i;
 248
 249         for (i = 0; i < NUM_MSR_MAPS; i++) {
 250                 if (msr < msrpm_ranges[i] ||
 251                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 252                         continue;
 253
 254                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 255                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 256
 257                 /* Now we have the u8 offset - but need the u32 offset */
 258                 return offset / 4;
 259         }
 260
 261         /* MSR not in any range */
 262         return MSR_INVALID;
 263 }
 264
 265 #define MAX_INST_SIZE 15
 266
 267 static inline u32 svm_has(u32 feat)
 268 {
 269         return svm_features & feat;
 270 }
 271
 272 static inline void clgi(void)
 273 {
 274         asm volatile (__ex(SVM_CLGI));
 275 }
 276
 277 static inline void stgi(void)
 278 {
 279         asm volatile (__ex(SVM_STGI));
 280 }
 281
 282 static inline void invlpga(unsigned long addr, u32 asid)
 283 {
 284         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
 285 }
 286
 287 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 288 {
 289         to_svm(vcpu)->asid_generation--;
 290 }
 291
 292 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 293 {
 294         force_new_asid(vcpu);
 295 }
 296
 297 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 298 {
 299         vcpu->arch.efer = efer;
 300         if (!npt_enabled && !(efer & EFER_LMA))
 301                 efer &= ~EFER_LME;
 302
 303         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 304 }
 305
 306 static int is_external_interrupt(u32 info)
 307 {
 308         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 309         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 310 }
 311
 312 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 313 {
 314         struct vcpu_svm *svm = to_svm(vcpu);
 315         u32 ret = 0;
 316
 317         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 318                 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 319         return ret & mask;
 320 }
 321
 322 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 323 {
 324         struct vcpu_svm *svm = to_svm(vcpu);
 325
 326         if (mask == 0)
 327                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 328         else
 329                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 330
 331 }
 332
 333 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 334 {
 335         struct vcpu_svm *svm = to_svm(vcpu);
 336
 337         if (svm->vmcb->control.next_rip != 0)
 338                 svm->next_rip = svm->vmcb->control.next_rip;
 339
 340         if (!svm->next_rip) {
 341                 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
 342                                 EMULATE_DONE)
 343                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 344                 return;
 345         }
 346         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 347                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 348                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 349
 350         kvm_rip_write(vcpu, svm->next_rip);
 351         svm_set_interrupt_shadow(vcpu, 0);
 352 }
 353
 354 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 355                                 bool has_error_code, u32 error_code,
 356                                 bool reinject)
 357 {
 358         struct vcpu_svm *svm = to_svm(vcpu);
 359
 360         /*
 361          * If we are within a nested VM we'd better #VMEXIT and let the guest
 362          * handle the exception
 363          */
 364         if (!reinject &&
 365             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 366                 return;
 367
 368         if (nr == BP_VECTOR && !svm_has(SVM_FEATURE_NRIP)) {
 369                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 370
 371                 /*
 372                  * For guest debugging where we have to reinject #BP if some
 373                  * INT3 is guest-owned:
 374                  * Emulate nRIP by moving RIP forward. Will fail if injection
 375                  * raises a fault that is not intercepted. Still better than
 376                  * failing in all cases.
 377                  */
 378                 skip_emulated_instruction(&svm->vcpu);
 379                 rip = kvm_rip_read(&svm->vcpu);
 380                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 381                 svm->int3_injected = rip - old_rip;
 382         }
 383
 384         svm->vmcb->control.event_inj = nr
 385                 | SVM_EVTINJ_VALID
 386                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 387                 | SVM_EVTINJ_TYPE_EXEPT;
 388         svm->vmcb->control.event_inj_err = error_code;
 389 }
 390
 391 static void svm_init_erratum_383(void)
 392 {
 393         u32 low, high;
 394         int err;
 395         u64 val;
 396
 397         if (!cpu_has_amd_erratum(amd_erratum_383))
 398                 return;
 399
 400         /* Use _safe variants to not break nested virtualization */
 401         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 402         if (err)
 403                 return;
 404
 405         val |= (1ULL << 47);
 406
 407         low  = lower_32_bits(val);
 408         high = upper_32_bits(val);
 409
 410         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 411
 412         erratum_383_found = true;
 413 }
 414
 415 static int has_svm(void)
 416 {
 417         const char *msg;
 418
 419         if (!cpu_has_svm(&msg)) {
 420                 printk(KERN_INFO "has_svm: %s\n", msg);
 421                 return 0;
 422         }
 423
 424         return 1;
 425 }
 426
 427 static void svm_hardware_disable(void *garbage)
 428 {
 429         cpu_svm_disable();
 430 }
 431
 432 static int svm_hardware_enable(void *garbage)
 433 {
 434
 435         struct svm_cpu_data *sd;
 436         uint64_t efer;
 437         struct desc_ptr gdt_descr;
 438         struct desc_struct *gdt;
 439         int me = raw_smp_processor_id();
 440
 441         rdmsrl(MSR_EFER, efer);
 442         if (efer & EFER_SVME)
 443                 return -EBUSY;
 444
 445         if (!has_svm()) {
 446                 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
 447                        me);
 448                 return -EINVAL;
 449         }
 450         sd = per_cpu(svm_data, me);
 451
 452         if (!sd) {
 453                 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
 454                        me);
 455                 return -EINVAL;
 456         }
 457
 458         sd->asid_generation = 1;
 459         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 460         sd->next_asid = sd->max_asid + 1;
 461
 462         native_store_gdt(&gdt_descr);
 463         gdt = (struct desc_struct *)gdt_descr.address;
 464         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 465
 466         wrmsrl(MSR_EFER, efer | EFER_SVME);
 467
 468         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 469
 470         svm_init_erratum_383();
 471
 472         return 0;
 473 }
 474
 475 static void svm_cpu_uninit(int cpu)
 476 {
 477         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 478
 479         if (!sd)
 480                 return;
 481
 482         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 483         __free_page(sd->save_area);
 484         kfree(sd);
 485 }
 486
 487 static int svm_cpu_init(int cpu)
 488 {
 489         struct svm_cpu_data *sd;
 490         int r;
 491
 492         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 493         if (!sd)
 494                 return -ENOMEM;
 495         sd->cpu = cpu;
 496         sd->save_area = alloc_page(GFP_KERNEL);
 497         r = -ENOMEM;
 498         if (!sd->save_area)
 499                 goto err_1;
 500
 501         per_cpu(svm_data, cpu) = sd;
 502
 503         return 0;
 504
 505 err_1:
 506         kfree(sd);
 507         return r;
 508
 509 }
 510
 511 static bool valid_msr_intercept(u32 index)
 512 {
 513         int i;
 514
 515         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 516                 if (direct_access_msrs[i].index == index)
 517                         return true;
 518
 519         return false;
 520 }
 521
 522 static void set_msr_interception(u32 *msrpm, unsigned msr,
 523                                  int read, int write)
 524 {
 525         u8 bit_read, bit_write;
 526         unsigned long tmp;
 527         u32 offset;
 528
 529         /*
 530          * If this warning triggers extend the direct_access_msrs list at the
 531          * beginning of the file
 532          */
 533         WARN_ON(!valid_msr_intercept(msr));
 534
 535         offset    = svm_msrpm_offset(msr);
 536         bit_read  = 2 * (msr & 0x0f);
 537         bit_write = 2 * (msr & 0x0f) + 1;
 538         tmp       = msrpm[offset];
 539
 540         BUG_ON(offset == MSR_INVALID);
 541
 542         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 543         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 544
 545         msrpm[offset] = tmp;
 546 }
 547
 548 static void svm_vcpu_init_msrpm(u32 *msrpm)
 549 {
 550         int i;
 551
 552         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 553
 554         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 555                 if (!direct_access_msrs[i].always)
 556                         continue;
 557
 558                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
 559         }
 560 }
 561
 562 static void add_msr_offset(u32 offset)
 563 {
 564         int i;
 565
 566         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 567
 568                 /* Offset already in list? */
 569                 if (msrpm_offsets[i] == offset)
 570                         return;
 571
 572                 /* Slot used by another offset? */
 573                 if (msrpm_offsets[i] != MSR_INVALID)
 574                         continue;
 575
 576                 /* Add offset to list */
 577                 msrpm_offsets[i] = offset;
 578
 579                 return;
 580         }
 581
 582         /*
 583          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 584          * increase MSRPM_OFFSETS in this case.
 585          */
 586         BUG();
 587 }
 588
 589 static void init_msrpm_offsets(void)
 590 {
 591         int i;
 592
 593         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 594
 595         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 596                 u32 offset;
 597
 598                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 599                 BUG_ON(offset == MSR_INVALID);
 600
 601                 add_msr_offset(offset);
 602         }
 603 }
 604
 605 static void svm_enable_lbrv(struct vcpu_svm *svm)
 606 {
 607         u32 *msrpm = svm->msrpm;
 608
 609         svm->vmcb->control.lbr_ctl = 1;
 610         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 611         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 612         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 613         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 614 }
 615
 616 static void svm_disable_lbrv(struct vcpu_svm *svm)
 617 {
 618         u32 *msrpm = svm->msrpm;
 619
 620         svm->vmcb->control.lbr_ctl = 0;
 621         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 622         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 623         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 624         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 625 }
 626
 627 static __init int svm_hardware_setup(void)
 628 {
 629         int cpu;
 630         struct page *iopm_pages;
 631         void *iopm_va;
 632         int r;
 633
 634         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 635
 636         if (!iopm_pages)
 637                 return -ENOMEM;
 638
 639         iopm_va = page_address(iopm_pages);
 640         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 641         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 642
 643         init_msrpm_offsets();
 644
 645         if (boot_cpu_has(X86_FEATURE_NX))
 646                 kvm_enable_efer_bits(EFER_NX);
 647
 648         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 649                 kvm_enable_efer_bits(EFER_FFXSR);
 650
 651         if (nested) {
 652                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 653                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
 654         }
 655
 656         for_each_possible_cpu(cpu) {
 657                 r = svm_cpu_init(cpu);
 658                 if (r)
 659                         goto err;
 660         }
 661
 662         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 663
 664         if (!svm_has(SVM_FEATURE_NPT))
 665                 npt_enabled = false;
 666
 667         if (npt_enabled && !npt) {
 668                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 669                 npt_enabled = false;
 670         }
 671
 672         if (npt_enabled) {
 673                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 674                 kvm_enable_tdp();
 675         } else
 676                 kvm_disable_tdp();
 677
 678         return 0;
 679
 680 err:
 681         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 682         iopm_base = 0;
 683         return r;
 684 }
 685
 686 static __exit void svm_hardware_unsetup(void)
 687 {
 688         int cpu;
 689
 690         for_each_possible_cpu(cpu)
 691                 svm_cpu_uninit(cpu);
 692
 693         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 694         iopm_base = 0;
 695 }
 696
 697 static void init_seg(struct vmcb_seg *seg)
 698 {
 699         seg->selector = 0;
 700         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 701                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 702         seg->limit = 0xffff;
 703         seg->base = 0;
 704 }
 705
 706 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 707 {
 708         seg->selector = 0;
 709         seg->attrib = SVM_SELECTOR_P_MASK | type;
 710         seg->limit = 0xffff;
 711         seg->base = 0;
 712 }
 713
 714 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
 715 {
 716         struct vcpu_svm *svm = to_svm(vcpu);
 717         u64 g_tsc_offset = 0;
 718
 719         if (is_nested(svm)) {
 720                 g_tsc_offset = svm->vmcb->control.tsc_offset -
 721                                svm->nested.hsave->control.tsc_offset;
 722                 svm->nested.hsave->control.tsc_offset = offset;
 723         }
 724
 725         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
 726 }
 727
 728 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
 729 {
 730         struct vcpu_svm *svm = to_svm(vcpu);
 731
 732         svm->vmcb->control.tsc_offset += adjustment;
 733         if (is_nested(svm))
 734                 svm->nested.hsave->control.tsc_offset += adjustment;
 735 }
 736
 737 static void init_vmcb(struct vcpu_svm *svm)
 738 {
 739         struct vmcb_control_area *control = &svm->vmcb->control;
 740         struct vmcb_save_area *save = &svm->vmcb->save;
 741
 742         svm->vcpu.fpu_active = 1;
 743
 744         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 745                                         INTERCEPT_CR3_MASK |
 746                                         INTERCEPT_CR4_MASK;
 747
 748         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 749                                         INTERCEPT_CR3_MASK |
 750                                         INTERCEPT_CR4_MASK |
 751                                         INTERCEPT_CR8_MASK;
 752
 753         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 754                                         INTERCEPT_DR1_MASK |
 755                                         INTERCEPT_DR2_MASK |
 756                                         INTERCEPT_DR3_MASK |
 757                                         INTERCEPT_DR4_MASK |
 758                                         INTERCEPT_DR5_MASK |
 759                                         INTERCEPT_DR6_MASK |
 760                                         INTERCEPT_DR7_MASK;
 761
 762         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 763                                         INTERCEPT_DR1_MASK |
 764                                         INTERCEPT_DR2_MASK |
 765                                         INTERCEPT_DR3_MASK |
 766                                         INTERCEPT_DR4_MASK |
 767                                         INTERCEPT_DR5_MASK |
 768                                         INTERCEPT_DR6_MASK |
 769                                         INTERCEPT_DR7_MASK;
 770
 771         control->intercept_exceptions = (1 << PF_VECTOR) |
 772                                         (1 << UD_VECTOR) |
 773                                         (1 << MC_VECTOR);
 774
 775
 776         control->intercept =    (1ULL << INTERCEPT_INTR) |
 777                                 (1ULL << INTERCEPT_NMI) |
 778                                 (1ULL << INTERCEPT_SMI) |
 779                                 (1ULL << INTERCEPT_SELECTIVE_CR0) |
 780                                 (1ULL << INTERCEPT_CPUID) |
 781                                 (1ULL << INTERCEPT_INVD) |
 782                                 (1ULL << INTERCEPT_HLT) |
 783                                 (1ULL << INTERCEPT_INVLPG) |
 784                                 (1ULL << INTERCEPT_INVLPGA) |
 785                                 (1ULL << INTERCEPT_IOIO_PROT) |
 786                                 (1ULL << INTERCEPT_MSR_PROT) |
 787                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 788                                 (1ULL << INTERCEPT_SHUTDOWN) |
 789                                 (1ULL << INTERCEPT_VMRUN) |
 790                                 (1ULL << INTERCEPT_VMMCALL) |
 791                                 (1ULL << INTERCEPT_VMLOAD) |
 792                                 (1ULL << INTERCEPT_VMSAVE) |
 793                                 (1ULL << INTERCEPT_STGI) |
 794                                 (1ULL << INTERCEPT_CLGI) |
 795                                 (1ULL << INTERCEPT_SKINIT) |
 796                                 (1ULL << INTERCEPT_WBINVD) |
 797                                 (1ULL << INTERCEPT_MONITOR) |
 798                                 (1ULL << INTERCEPT_MWAIT);
 799
 800         control->iopm_base_pa = iopm_base;
 801         control->msrpm_base_pa = __pa(svm->msrpm);
 802         control->int_ctl = V_INTR_MASKING_MASK;
 803
 804         init_seg(&save->es);
 805         init_seg(&save->ss);
 806         init_seg(&save->ds);
 807         init_seg(&save->fs);
 808         init_seg(&save->gs);
 809
 810         save->cs.selector = 0xf000;
 811         /* Executable/Readable Code Segment */
 812         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 813                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 814         save->cs.limit = 0xffff;
 815         /*
 816          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 817          * be consistent with it.
 818          *
 819          * Replace when we have real mode working for vmx.
 820          */
 821         save->cs.base = 0xf0000;
 822
 823         save->gdtr.limit = 0xffff;
 824         save->idtr.limit = 0xffff;
 825
 826         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 827         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 828
 829         svm_set_efer(&svm->vcpu, 0);
 830         save->dr6 = 0xffff0ff0;
 831         save->dr7 = 0x400;
 832         save->rflags = 2;
 833         save->rip = 0x0000fff0;
 834         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 835
 836         /*
 837          * This is the guest-visible cr0 value.
 838          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
 839          */
 840         svm->vcpu.arch.cr0 = 0;
 841         (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
 842
 843         save->cr4 = X86_CR4_PAE;
 844         /* rdx = ?? */
 845
 846         if (npt_enabled) {
 847                 /* Setup VMCB for Nested Paging */
 848                 control->nested_ctl = 1;
 849                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 850                                         (1ULL << INTERCEPT_INVLPG));
 851                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 852                 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
 853                 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
 854                 save->g_pat = 0x0007040600070406ULL;
 855                 save->cr3 = 0;
 856                 save->cr4 = 0;
 857         }
 858         force_new_asid(&svm->vcpu);
 859
 860         svm->nested.vmcb = 0;
 861         svm->vcpu.arch.hflags = 0;
 862
 863         if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
 864                 control->pause_filter_count = 3000;
 865                 control->intercept |= (1ULL << INTERCEPT_PAUSE);
 866         }
 867
 868         enable_gif(svm);
 869 }
 870
 871 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 872 {
 873         struct vcpu_svm *svm = to_svm(vcpu);
 874
 875         init_vmcb(svm);
 876
 877         if (!kvm_vcpu_is_bsp(vcpu)) {
 878                 kvm_rip_write(vcpu, 0);
 879                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 880                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 881         }
 882         vcpu->arch.regs_avail = ~0;
 883         vcpu->arch.regs_dirty = ~0;
 884
 885         return 0;
 886 }
 887
 888 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 889 {
 890         struct vcpu_svm *svm;
 891         struct page *page;
 892         struct page *msrpm_pages;
 893         struct page *hsave_page;
 894         struct page *nested_msrpm_pages;
 895         int err;
 896
 897         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 898         if (!svm) {
 899                 err = -ENOMEM;
 900                 goto out;
 901         }
 902
 903         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 904         if (err)
 905                 goto free_svm;
 906
 907         err = -ENOMEM;
 908         page = alloc_page(GFP_KERNEL);
 909         if (!page)
 910                 goto uninit;
 911
 912         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 913         if (!msrpm_pages)
 914                 goto free_page1;
 915
 916         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 917         if (!nested_msrpm_pages)
 918                 goto free_page2;
 919
 920         hsave_page = alloc_page(GFP_KERNEL);
 921         if (!hsave_page)
 922                 goto free_page3;
 923
 924         svm->nested.hsave = page_address(hsave_page);
 925
 926         svm->msrpm = page_address(msrpm_pages);
 927         svm_vcpu_init_msrpm(svm->msrpm);
 928
 929         svm->nested.msrpm = page_address(nested_msrpm_pages);
 930         svm_vcpu_init_msrpm(svm->nested.msrpm);
 931
 932         svm->vmcb = page_address(page);
 933         clear_page(svm->vmcb);
 934         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 935         svm->asid_generation = 0;
 936         init_vmcb(svm);
 937         kvm_write_tsc(&svm->vcpu, 0);
 938
 939         err = fx_init(&svm->vcpu);
 940         if (err)
 941                 goto free_page4;
 942
 943         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 944         if (kvm_vcpu_is_bsp(&svm->vcpu))
 945                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 946
 947         return &svm->vcpu;
 948
 949 free_page4:
 950         __free_page(hsave_page);
 951 free_page3:
 952         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
 953 free_page2:
 954         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
 955 free_page1:
 956         __free_page(page);
 957 uninit:
 958         kvm_vcpu_uninit(&svm->vcpu);
 959 free_svm:
 960         kmem_cache_free(kvm_vcpu_cache, svm);
 961 out:
 962         return ERR_PTR(err);
 963 }
 964
 965 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 966 {
 967         struct vcpu_svm *svm = to_svm(vcpu);
 968
 969         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 970         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 971         __free_page(virt_to_page(svm->nested.hsave));
 972         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
 973         kvm_vcpu_uninit(vcpu);
 974         kmem_cache_free(kvm_vcpu_cache, svm);
 975 }
 976
 977 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 978 {
 979         struct vcpu_svm *svm = to_svm(vcpu);
 980         int i;
 981
 982         if (unlikely(cpu != vcpu->cpu)) {
 983                 svm->asid_generation = 0;
 984         }
 985
 986         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 987                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 988 }
 989
 990 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 991 {
 992         struct vcpu_svm *svm = to_svm(vcpu);
 993         int i;
 994
 995         ++vcpu->stat.host_state_reload;
 996         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 997                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 998 }
 999
1000 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1001 {
1002         return to_svm(vcpu)->vmcb->save.rflags;
1003 }
1004
1005 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1006 {
1007         to_svm(vcpu)->vmcb->save.rflags = rflags;
1008 }
1009
1010 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1011 {
1012         switch (reg) {
1013         case VCPU_EXREG_PDPTR:
1014                 BUG_ON(!npt_enabled);
1015                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
1016                 break;
1017         default:
1018                 BUG();
1019         }
1020 }
1021
1022 static void svm_set_vintr(struct vcpu_svm *svm)
1023 {
1024         svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
1025 }
1026
1027 static void svm_clear_vintr(struct vcpu_svm *svm)
1028 {
1029         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1030 }
1031
1032 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1033 {
1034         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1035
1036         switch (seg) {
1037         case VCPU_SREG_CS: return &save->cs;
1038         case VCPU_SREG_DS: return &save->ds;
1039         case VCPU_SREG_ES: return &save->es;
1040         case VCPU_SREG_FS: return &save->fs;
1041         case VCPU_SREG_GS: return &save->gs;
1042         case VCPU_SREG_SS: return &save->ss;
1043         case VCPU_SREG_TR: return &save->tr;
1044         case VCPU_SREG_LDTR: return &save->ldtr;
1045         }
1046         BUG();
1047         return NULL;
1048 }
1049
1050 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1051 {
1052         struct vmcb_seg *s = svm_seg(vcpu, seg);
1053
1054         return s->base;
1055 }
1056
1057 static void svm_get_segment(struct kvm_vcpu *vcpu,
1058                             struct kvm_segment *var, int seg)
1059 {
1060         struct vmcb_seg *s = svm_seg(vcpu, seg);
1061
1062         var->base = s->base;
1063         var->limit = s->limit;
1064         var->selector = s->selector;
1065         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1066         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1067         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1068         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1069         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1070         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1071         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1072         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1073
1074         /*
1075          * AMD's VMCB does not have an explicit unusable field, so emulate it
1076          * for cross vendor migration purposes by "not present"
1077          */
1078         var->unusable = !var->present || (var->type == 0);
1079
1080         switch (seg) {
1081         case VCPU_SREG_CS:
1082                 /*
1083                  * SVM always stores 0 for the 'G' bit in the CS selector in
1084                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1085                  * Intel's VMENTRY has a check on the 'G' bit.
1086                  */
1087                 var->g = s->limit > 0xfffff;
1088                 break;
1089         case VCPU_SREG_TR:
1090                 /*
1091                  * Work around a bug where the busy flag in the tr selector
1092                  * isn't exposed
1093                  */
1094                 var->type |= 0x2;
1095                 break;
1096         case VCPU_SREG_DS:
1097         case VCPU_SREG_ES:
1098         case VCPU_SREG_FS:
1099         case VCPU_SREG_GS:
1100                 /*
1101                  * The accessed bit must always be set in the segment
1102                  * descriptor cache, although it can be cleared in the
1103                  * descriptor, the cached bit always remains at 1. Since
1104                  * Intel has a check on this, set it here to support
1105                  * cross-vendor migration.
1106                  */
1107                 if (!var->unusable)
1108                         var->type |= 0x1;
1109                 break;
1110         case VCPU_SREG_SS:
1111                 /*
1112                  * On AMD CPUs sometimes the DB bit in the segment
1113                  * descriptor is left as 1, although the whole segment has
1114                  * been made unusable. Clear it here to pass an Intel VMX
1115                  * entry check when cross vendor migrating.
1116                  */
1117                 if (var->unusable)
1118                         var->db = 0;
1119                 break;
1120         }
1121 }
1122
1123 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1124 {
1125         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1126
1127         return save->cpl;
1128 }
1129
1130 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1131 {
1132         struct vcpu_svm *svm = to_svm(vcpu);
1133
1134         dt->size = svm->vmcb->save.idtr.limit;
1135         dt->address = svm->vmcb->save.idtr.base;
1136 }
1137
1138 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1139 {
1140         struct vcpu_svm *svm = to_svm(vcpu);
1141
1142         svm->vmcb->save.idtr.limit = dt->size;
1143         svm->vmcb->save.idtr.base = dt->address ;
1144 }
1145
1146 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1147 {
1148         struct vcpu_svm *svm = to_svm(vcpu);
1149
1150         dt->size = svm->vmcb->save.gdtr.limit;
1151         dt->address = svm->vmcb->save.gdtr.base;
1152 }
1153
1154 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1155 {
1156         struct vcpu_svm *svm = to_svm(vcpu);
1157
1158         svm->vmcb->save.gdtr.limit = dt->size;
1159         svm->vmcb->save.gdtr.base = dt->address ;
1160 }
1161
1162 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1163 {
1164 }
1165
1166 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1167 {
1168 }
1169
1170 static void update_cr0_intercept(struct vcpu_svm *svm)
1171 {
1172         struct vmcb *vmcb = svm->vmcb;
1173         ulong gcr0 = svm->vcpu.arch.cr0;
1174         u64 *hcr0 = &svm->vmcb->save.cr0;
1175
1176         if (!svm->vcpu.fpu_active)
1177                 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1178         else
1179                 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1180                         | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1181
1182
1183         if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1184                 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1185                 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1186                 if (is_nested(svm)) {
1187                         struct vmcb *hsave = svm->nested.hsave;
1188
1189                         hsave->control.intercept_cr_read  &= ~INTERCEPT_CR0_MASK;
1190                         hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1191                         vmcb->control.intercept_cr_read  |= svm->nested.intercept_cr_read;
1192                         vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1193                 }
1194         } else {
1195                 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1196                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1197                 if (is_nested(svm)) {
1198                         struct vmcb *hsave = svm->nested.hsave;
1199
1200                         hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1201                         hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1202                 }
1203         }
1204 }
1205
1206 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1207 {
1208         struct vcpu_svm *svm = to_svm(vcpu);
1209
1210         if (is_nested(svm)) {
1211                 /*
1212                  * We are here because we run in nested mode, the host kvm
1213                  * intercepts cr0 writes but the l1 hypervisor does not.
1214                  * But the L1 hypervisor may intercept selective cr0 writes.
1215                  * This needs to be checked here.
1216                  */
1217                 unsigned long old, new;
1218
1219                 /* Remove bits that would trigger a real cr0 write intercept */
1220                 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1221                 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1222
1223                 if (old == new) {
1224                         /* cr0 write with ts and mp unchanged */
1225                         svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1226                         if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) {
1227                                 svm->nested.vmexit_rip = kvm_rip_read(vcpu);
1228                                 svm->nested.vmexit_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
1229                                 svm->nested.vmexit_rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
1230                                 return;
1231                         }
1232                 }
1233         }
1234
1235 #ifdef CONFIG_X86_64
1236         if (vcpu->arch.efer & EFER_LME) {
1237                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1238                         vcpu->arch.efer |= EFER_LMA;
1239                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1240                 }
1241
1242                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1243                         vcpu->arch.efer &= ~EFER_LMA;
1244                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1245                 }
1246         }
1247 #endif
1248         vcpu->arch.cr0 = cr0;
1249
1250         if (!npt_enabled)
1251                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1252
1253         if (!vcpu->fpu_active)
1254                 cr0 |= X86_CR0_TS;
1255         /*
1256          * re-enable caching here because the QEMU bios
1257          * does not do it - this results in some delay at
1258          * reboot
1259          */
1260         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1261         svm->vmcb->save.cr0 = cr0;
1262         update_cr0_intercept(svm);
1263 }
1264
1265 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1266 {
1267         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1268         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1269
1270         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1271                 force_new_asid(vcpu);
1272
1273         vcpu->arch.cr4 = cr4;
1274         if (!npt_enabled)
1275                 cr4 |= X86_CR4_PAE;
1276         cr4 |= host_cr4_mce;
1277         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1278 }
1279
1280 static void svm_set_segment(struct kvm_vcpu *vcpu,
1281                             struct kvm_segment *var, int seg)
1282 {
1283         struct vcpu_svm *svm = to_svm(vcpu);
1284         struct vmcb_seg *s = svm_seg(vcpu, seg);
1285
1286         s->base = var->base;
1287         s->limit = var->limit;
1288         s->selector = var->selector;
1289         if (var->unusable)
1290                 s->attrib = 0;
1291         else {
1292                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1293                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1294                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1295                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1296                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1297                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1298                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1299                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1300         }
1301         if (seg == VCPU_SREG_CS)
1302                 svm->vmcb->save.cpl
1303                         = (svm->vmcb->save.cs.attrib
1304                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
1305
1306 }
1307
1308 static void update_db_intercept(struct kvm_vcpu *vcpu)
1309 {
1310         struct vcpu_svm *svm = to_svm(vcpu);
1311
1312         svm->vmcb->control.intercept_exceptions &=
1313                 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1314
1315         if (svm->nmi_singlestep)
1316                 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1317
1318         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1319                 if (vcpu->guest_debug &
1320                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1321                         svm->vmcb->control.intercept_exceptions |=
1322                                 1 << DB_VECTOR;
1323                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1324                         svm->vmcb->control.intercept_exceptions |=
1325                                 1 << BP_VECTOR;
1326         } else
1327                 vcpu->guest_debug = 0;
1328 }
1329
1330 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1331 {
1332         struct vcpu_svm *svm = to_svm(vcpu);
1333
1334         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1335                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1336         else
1337                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1338
1339         update_db_intercept(vcpu);
1340 }
1341
1342 static void load_host_msrs(struct kvm_vcpu *vcpu)
1343 {
1344 #ifdef CONFIG_X86_64
1345         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1346 #endif
1347 }
1348
1349 static void save_host_msrs(struct kvm_vcpu *vcpu)
1350 {
1351 #ifdef CONFIG_X86_64
1352         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1353 #endif
1354 }
1355
1356 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1357 {
1358         if (sd->next_asid > sd->max_asid) {
1359                 ++sd->asid_generation;
1360                 sd->next_asid = 1;
1361                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1362         }
1363
1364         svm->asid_generation = sd->asid_generation;
1365         svm->vmcb->control.asid = sd->next_asid++;
1366 }
1367
1368 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1369 {
1370         struct vcpu_svm *svm = to_svm(vcpu);
1371
1372         svm->vmcb->save.dr7 = value;
1373 }
1374
1375 static int pf_interception(struct vcpu_svm *svm)
1376 {
1377         u64 fault_address;
1378         u32 error_code;
1379
1380         fault_address  = svm->vmcb->control.exit_info_2;
1381         error_code = svm->vmcb->control.exit_info_1;
1382
1383         trace_kvm_page_fault(fault_address, error_code);
1384         if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1385                 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1386         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1387 }
1388
1389 static int db_interception(struct vcpu_svm *svm)
1390 {
1391         struct kvm_run *kvm_run = svm->vcpu.run;
1392
1393         if (!(svm->vcpu.guest_debug &
1394               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1395                 !svm->nmi_singlestep) {
1396                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1397                 return 1;
1398         }
1399
1400         if (svm->nmi_singlestep) {
1401                 svm->nmi_singlestep = false;
1402                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1403                         svm->vmcb->save.rflags &=
1404                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1405                 update_db_intercept(&svm->vcpu);
1406         }
1407
1408         if (svm->vcpu.guest_debug &
1409             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1410                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1411                 kvm_run->debug.arch.pc =
1412                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1413                 kvm_run->debug.arch.exception = DB_VECTOR;
1414                 return 0;
1415         }
1416
1417         return 1;
1418 }
1419
1420 static int bp_interception(struct vcpu_svm *svm)
1421 {
1422         struct kvm_run *kvm_run = svm->vcpu.run;
1423
1424         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1425         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1426         kvm_run->debug.arch.exception = BP_VECTOR;
1427         return 0;
1428 }
1429
1430 static int ud_interception(struct vcpu_svm *svm)
1431 {
1432         int er;
1433
1434         er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1435         if (er != EMULATE_DONE)
1436                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1437         return 1;
1438 }
1439
1440 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1441 {
1442         struct vcpu_svm *svm = to_svm(vcpu);
1443         u32 excp;
1444
1445         if (is_nested(svm)) {
1446                 u32 h_excp, n_excp;
1447
1448                 h_excp  = svm->nested.hsave->control.intercept_exceptions;
1449                 n_excp  = svm->nested.intercept_exceptions;
1450                 h_excp &= ~(1 << NM_VECTOR);
1451                 excp    = h_excp | n_excp;
1452         } else {
1453                 excp  = svm->vmcb->control.intercept_exceptions;
1454                 excp &= ~(1 << NM_VECTOR);
1455         }
1456
1457         svm->vmcb->control.intercept_exceptions = excp;
1458
1459         svm->vcpu.fpu_active = 1;
1460         update_cr0_intercept(svm);
1461 }
1462
1463 static int nm_interception(struct vcpu_svm *svm)
1464 {
1465         svm_fpu_activate(&svm->vcpu);
1466         return 1;
1467 }
1468
1469 static bool is_erratum_383(void)
1470 {
1471         int err, i;
1472         u64 value;
1473
1474         if (!erratum_383_found)
1475                 return false;
1476
1477         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1478         if (err)
1479                 return false;
1480
1481         /* Bit 62 may or may not be set for this mce */
1482         value &= ~(1ULL << 62);
1483
1484         if (value != 0xb600000000010015ULL)
1485                 return false;
1486
1487         /* Clear MCi_STATUS registers */
1488         for (i = 0; i < 6; ++i)
1489                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1490
1491         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1492         if (!err) {
1493                 u32 low, high;
1494
1495                 value &= ~(1ULL << 2);
1496                 low    = lower_32_bits(value);
1497                 high   = upper_32_bits(value);
1498
1499                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1500         }
1501
1502         /* Flush tlb to evict multi-match entries */
1503         __flush_tlb_all();
1504
1505         return true;
1506 }
1507
1508 static void svm_handle_mce(struct vcpu_svm *svm)
1509 {
1510         if (is_erratum_383()) {
1511                 /*
1512                  * Erratum 383 triggered. Guest state is corrupt so kill the
1513                  * guest.
1514                  */
1515                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1516
1517                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1518
1519                 return;
1520         }
1521
1522         /*
1523          * On an #MC intercept the MCE handler is not called automatically in
1524          * the host. So do it by hand here.
1525          */
1526         asm volatile (
1527                 "int $0x12\n");
1528         /* not sure if we ever come back to this point */
1529
1530         return;
1531 }
1532
1533 static int mc_interception(struct vcpu_svm *svm)
1534 {
1535         return 1;
1536 }
1537
1538 static int shutdown_interception(struct vcpu_svm *svm)
1539 {
1540         struct kvm_run *kvm_run = svm->vcpu.run;
1541
1542         /*
1543          * VMCB is undefined after a SHUTDOWN intercept
1544          * so reinitialize it.
1545          */
1546         clear_page(svm->vmcb);
1547         init_vmcb(svm);
1548
1549         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1550         return 0;
1551 }
1552
1553 static int io_interception(struct vcpu_svm *svm)
1554 {
1555         struct kvm_vcpu *vcpu = &svm->vcpu;
1556         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1557         int size, in, string;
1558         unsigned port;
1559
1560         ++svm->vcpu.stat.io_exits;
1561         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1562         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1563         if (string || in)
1564                 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
1565
1566         port = io_info >> 16;
1567         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1568         svm->next_rip = svm->vmcb->control.exit_info_2;
1569         skip_emulated_instruction(&svm->vcpu);
1570
1571         return kvm_fast_pio_out(vcpu, size, port);
1572 }
1573
1574 static int nmi_interception(struct vcpu_svm *svm)
1575 {
1576         return 1;
1577 }
1578
1579 static int intr_interception(struct vcpu_svm *svm)
1580 {
1581         ++svm->vcpu.stat.irq_exits;
1582         return 1;
1583 }
1584
1585 static int nop_on_interception(struct vcpu_svm *svm)
1586 {
1587         return 1;
1588 }
1589
1590 static int halt_interception(struct vcpu_svm *svm)
1591 {
1592         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1593         skip_emulated_instruction(&svm->vcpu);
1594         return kvm_emulate_halt(&svm->vcpu);
1595 }
1596
1597 static int vmmcall_interception(struct vcpu_svm *svm)
1598 {
1599         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1600         skip_emulated_instruction(&svm->vcpu);
1601         kvm_emulate_hypercall(&svm->vcpu);
1602         return 1;
1603 }
1604
1605 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1606 {
1607         struct vcpu_svm *svm = to_svm(vcpu);
1608
1609         return svm->nested.nested_cr3;
1610 }
1611
1612 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1613                                    unsigned long root)
1614 {
1615         struct vcpu_svm *svm = to_svm(vcpu);
1616
1617         svm->vmcb->control.nested_cr3 = root;
1618         force_new_asid(vcpu);
1619 }
1620
1621 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu)
1622 {
1623         struct vcpu_svm *svm = to_svm(vcpu);
1624
1625         svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1626         svm->vmcb->control.exit_code_hi = 0;
1627         svm->vmcb->control.exit_info_1 = vcpu->arch.fault.error_code;
1628         svm->vmcb->control.exit_info_2 = vcpu->arch.fault.address;
1629
1630         nested_svm_vmexit(svm);
1631 }
1632
1633 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1634 {
1635         if (!(svm->vcpu.arch.efer & EFER_SVME)
1636             || !is_paging(&svm->vcpu)) {
1637                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1638                 return 1;
1639         }
1640
1641         if (svm->vmcb->save.cpl) {
1642                 kvm_inject_gp(&svm->vcpu, 0);
1643                 return 1;
1644         }
1645
1646        return 0;
1647 }
1648
1649 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1650                                       bool has_error_code, u32 error_code)
1651 {
1652         int vmexit;
1653
1654         if (!is_nested(svm))
1655                 return 0;
1656
1657         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1658         svm->vmcb->control.exit_code_hi = 0;
1659         svm->vmcb->control.exit_info_1 = error_code;
1660         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1661
1662         vmexit = nested_svm_intercept(svm);
1663         if (vmexit == NESTED_EXIT_DONE)
1664                 svm->nested.exit_required = true;
1665
1666         return vmexit;
1667 }
1668
1669 /* This function returns true if it is save to enable the irq window */
1670 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1671 {
1672         if (!is_nested(svm))
1673                 return true;
1674
1675         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1676                 return true;
1677
1678         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1679                 return false;
1680
1681         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
1682         svm->vmcb->control.exit_info_1 = 0;
1683         svm->vmcb->control.exit_info_2 = 0;
1684
1685         if (svm->nested.intercept & 1ULL) {
1686                 /*
1687                  * The #vmexit can't be emulated here directly because this
1688                  * code path runs with irqs and preemtion disabled. A
1689                  * #vmexit emulation might sleep. Only signal request for
1690                  * the #vmexit here.
1691                  */
1692                 svm->nested.exit_required = true;
1693                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1694                 return false;
1695         }
1696
1697         return true;
1698 }
1699
1700 /* This function returns true if it is save to enable the nmi window */
1701 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1702 {
1703         if (!is_nested(svm))
1704                 return true;
1705
1706         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1707                 return true;
1708
1709         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1710         svm->nested.exit_required = true;
1711
1712         return false;
1713 }
1714
1715 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1716 {
1717         struct page *page;
1718
1719         might_sleep();
1720
1721         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1722         if (is_error_page(page))
1723                 goto error;
1724
1725         *_page = page;
1726
1727         return kmap(page);
1728
1729 error:
1730         kvm_release_page_clean(page);
1731         kvm_inject_gp(&svm->vcpu, 0);
1732
1733         return NULL;
1734 }
1735
1736 static void nested_svm_unmap(struct page *page)
1737 {
1738         kunmap(page);
1739         kvm_release_page_dirty(page);
1740 }
1741
1742 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1743 {
1744         unsigned port;
1745         u8 val, bit;
1746         u64 gpa;
1747
1748         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1749                 return NESTED_EXIT_HOST;
1750
1751         port = svm->vmcb->control.exit_info_1 >> 16;
1752         gpa  = svm->nested.vmcb_iopm + (port / 8);
1753         bit  = port % 8;
1754         val  = 0;
1755
1756         if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1757                 val &= (1 << bit);
1758
1759         return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1760 }
1761
1762 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1763 {
1764         u32 offset, msr, value;
1765         int write, mask;
1766
1767         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1768                 return NESTED_EXIT_HOST;
1769
1770         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1771         offset = svm_msrpm_offset(msr);
1772         write  = svm->vmcb->control.exit_info_1 & 1;
1773         mask   = 1 << ((2 * (msr & 0xf)) + write);
1774
1775         if (offset == MSR_INVALID)
1776                 return NESTED_EXIT_DONE;
1777
1778         /* Offset is in 32 bit units but need in 8 bit units */
1779         offset *= 4;
1780
1781         if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1782                 return NESTED_EXIT_DONE;
1783
1784         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1785 }
1786
1787 static int nested_svm_exit_special(struct vcpu_svm *svm)
1788 {
1789         u32 exit_code = svm->vmcb->control.exit_code;
1790
1791         switch (exit_code) {
1792         case SVM_EXIT_INTR:
1793         case SVM_EXIT_NMI:
1794         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
1795                 return NESTED_EXIT_HOST;
1796         case SVM_EXIT_NPF:
1797                 /* For now we are always handling NPFs when using them */
1798                 if (npt_enabled)
1799                         return NESTED_EXIT_HOST;
1800                 break;
1801         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1802                 /* When we're shadowing, trap PFs */
1803                 if (!npt_enabled)
1804                         return NESTED_EXIT_HOST;
1805                 break;
1806         case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1807                 nm_interception(svm);
1808                 break;
1809         default:
1810                 break;
1811         }
1812
1813         return NESTED_EXIT_CONTINUE;
1814 }
1815
1816 /*
1817  * If this function returns true, this #vmexit was already handled
1818  */
1819 static int nested_svm_intercept(struct vcpu_svm *svm)
1820 {
1821         u32 exit_code = svm->vmcb->control.exit_code;
1822         int vmexit = NESTED_EXIT_HOST;
1823
1824         switch (exit_code) {
1825         case SVM_EXIT_MSR:
1826                 vmexit = nested_svm_exit_handled_msr(svm);
1827                 break;
1828         case SVM_EXIT_IOIO:
1829                 vmexit = nested_svm_intercept_ioio(svm);
1830                 break;
1831         case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1832                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1833                 if (svm->nested.intercept_cr_read & cr_bits)
1834                         vmexit = NESTED_EXIT_DONE;
1835                 break;
1836         }
1837         case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1838                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1839                 if (svm->nested.intercept_cr_write & cr_bits)
1840                         vmexit = NESTED_EXIT_DONE;
1841                 break;
1842         }
1843         case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1844                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1845                 if (svm->nested.intercept_dr_read & dr_bits)
1846                         vmexit = NESTED_EXIT_DONE;
1847                 break;
1848         }
1849         case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1850                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1851                 if (svm->nested.intercept_dr_write & dr_bits)
1852                         vmexit = NESTED_EXIT_DONE;
1853                 break;
1854         }
1855         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1856                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1857                 if (svm->nested.intercept_exceptions & excp_bits)
1858                         vmexit = NESTED_EXIT_DONE;
1859                 break;
1860         }
1861         case SVM_EXIT_ERR: {
1862                 vmexit = NESTED_EXIT_DONE;
1863                 break;
1864         }
1865         default: {
1866                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1867                 if (svm->nested.intercept & exit_bits)
1868                         vmexit = NESTED_EXIT_DONE;
1869         }
1870         }
1871
1872         return vmexit;
1873 }
1874
1875 static int nested_svm_exit_handled(struct vcpu_svm *svm)
1876 {
1877         int vmexit;
1878
1879         vmexit = nested_svm_intercept(svm);
1880
1881         if (vmexit == NESTED_EXIT_DONE)
1882                 nested_svm_vmexit(svm);
1883
1884         return vmexit;
1885 }
1886
1887 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1888 {
1889         struct vmcb_control_area *dst  = &dst_vmcb->control;
1890         struct vmcb_control_area *from = &from_vmcb->control;
1891
1892         dst->intercept_cr_read    = from->intercept_cr_read;
1893         dst->intercept_cr_write   = from->intercept_cr_write;
1894         dst->intercept_dr_read    = from->intercept_dr_read;
1895         dst->intercept_dr_write   = from->intercept_dr_write;
1896         dst->intercept_exceptions = from->intercept_exceptions;
1897         dst->intercept            = from->intercept;
1898         dst->iopm_base_pa         = from->iopm_base_pa;
1899         dst->msrpm_base_pa        = from->msrpm_base_pa;
1900         dst->tsc_offset           = from->tsc_offset;
1901         dst->asid                 = from->asid;
1902         dst->tlb_ctl              = from->tlb_ctl;
1903         dst->int_ctl              = from->int_ctl;
1904         dst->int_vector           = from->int_vector;
1905         dst->int_state            = from->int_state;
1906         dst->exit_code            = from->exit_code;
1907         dst->exit_code_hi         = from->exit_code_hi;
1908         dst->exit_info_1          = from->exit_info_1;
1909         dst->exit_info_2          = from->exit_info_2;
1910         dst->exit_int_info        = from->exit_int_info;
1911         dst->exit_int_info_err    = from->exit_int_info_err;
1912         dst->nested_ctl           = from->nested_ctl;
1913         dst->event_inj            = from->event_inj;
1914         dst->event_inj_err        = from->event_inj_err;
1915         dst->nested_cr3           = from->nested_cr3;
1916         dst->lbr_ctl              = from->lbr_ctl;
1917 }
1918
1919 static int nested_svm_vmexit(struct vcpu_svm *svm)
1920 {
1921         struct vmcb *nested_vmcb;
1922         struct vmcb *hsave = svm->nested.hsave;
1923         struct vmcb *vmcb = svm->vmcb;
1924         struct page *page;
1925
1926         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1927                                        vmcb->control.exit_info_1,
1928                                        vmcb->control.exit_info_2,
1929                                        vmcb->control.exit_int_info,
1930                                        vmcb->control.exit_int_info_err);
1931
1932         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
1933         if (!nested_vmcb)
1934                 return 1;
1935
1936         /* Exit nested SVM mode */
1937         svm->nested.vmcb = 0;
1938
1939         /* Give the current vmcb to the guest */
1940         disable_gif(svm);
1941
1942         nested_vmcb->save.es     = vmcb->save.es;
1943         nested_vmcb->save.cs     = vmcb->save.cs;
1944         nested_vmcb->save.ss     = vmcb->save.ss;
1945         nested_vmcb->save.ds     = vmcb->save.ds;
1946         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
1947         nested_vmcb->save.idtr   = vmcb->save.idtr;
1948         nested_vmcb->save.efer   = svm->vcpu.arch.efer;
1949         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
1950         nested_vmcb->save.cr3    = svm->vcpu.arch.cr3;
1951         nested_vmcb->save.cr2    = vmcb->save.cr2;
1952         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
1953         nested_vmcb->save.rflags = vmcb->save.rflags;
1954         nested_vmcb->save.rip    = vmcb->save.rip;
1955         nested_vmcb->save.rsp    = vmcb->save.rsp;
1956         nested_vmcb->save.rax    = vmcb->save.rax;
1957         nested_vmcb->save.dr7    = vmcb->save.dr7;
1958         nested_vmcb->save.dr6    = vmcb->save.dr6;
1959         nested_vmcb->save.cpl    = vmcb->save.cpl;
1960
1961         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
1962         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
1963         nested_vmcb->control.int_state         = vmcb->control.int_state;
1964         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
1965         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
1966         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
1967         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
1968         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
1969         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1970         nested_vmcb->control.next_rip          = vmcb->control.next_rip;
1971
1972         /*
1973          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1974          * to make sure that we do not lose injected events. So check event_inj
1975          * here and copy it to exit_int_info if it is valid.
1976          * Exit_int_info and event_inj can't be both valid because the case
1977          * below only happens on a VMRUN instruction intercept which has
1978          * no valid exit_int_info set.
1979          */
1980         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1981                 struct vmcb_control_area *nc = &nested_vmcb->control;
1982
1983                 nc->exit_int_info     = vmcb->control.event_inj;
1984                 nc->exit_int_info_err = vmcb->control.event_inj_err;
1985         }
1986
1987         nested_vmcb->control.tlb_ctl           = 0;
1988         nested_vmcb->control.event_inj         = 0;
1989         nested_vmcb->control.event_inj_err     = 0;
1990
1991         /* We always set V_INTR_MASKING and remember the old value in hflags */
1992         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1993                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1994
1995         /* Restore the original control entries */
1996         copy_vmcb_control_area(vmcb, hsave);
1997
1998         kvm_clear_exception_queue(&svm->vcpu);
1999         kvm_clear_interrupt_queue(&svm->vcpu);
2000
2001         /* Restore selected save entries */
2002         svm->vmcb->save.es = hsave->save.es;
2003         svm->vmcb->save.cs = hsave->save.cs;
2004         svm->vmcb->save.ss = hsave->save.ss;
2005         svm->vmcb->save.ds = hsave->save.ds;
2006         svm->vmcb->save.gdtr = hsave->save.gdtr;
2007         svm->vmcb->save.idtr = hsave->save.idtr;
2008         svm->vmcb->save.rflags = hsave->save.rflags;
2009         svm_set_efer(&svm->vcpu, hsave->save.efer);
2010         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2011         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2012         if (npt_enabled) {
2013                 svm->vmcb->save.cr3 = hsave->save.cr3;
2014                 svm->vcpu.arch.cr3 = hsave->save.cr3;
2015         } else {
2016                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2017         }
2018         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2019         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2020         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2021         svm->vmcb->save.dr7 = 0;
2022         svm->vmcb->save.cpl = 0;
2023         svm->vmcb->control.exit_int_info = 0;
2024
2025         nested_svm_unmap(page);
2026
2027         kvm_mmu_reset_context(&svm->vcpu);
2028         kvm_mmu_load(&svm->vcpu);
2029
2030         return 0;
2031 }
2032
2033 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2034 {
2035         /*
2036          * This function merges the msr permission bitmaps of kvm and the
2037          * nested vmcb. It is omptimized in that it only merges the parts where
2038          * the kvm msr permission bitmap may contain zero bits
2039          */
2040         int i;
2041
2042         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2043                 return true;
2044
2045         for (i = 0; i < MSRPM_OFFSETS; i++) {
2046                 u32 value, p;
2047                 u64 offset;
2048
2049                 if (msrpm_offsets[i] == 0xffffffff)
2050                         break;
2051
2052                 p      = msrpm_offsets[i];
2053                 offset = svm->nested.vmcb_msrpm + (p * 4);
2054
2055                 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2056                         return false;
2057
2058                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2059         }
2060
2061         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2062
2063         return true;
2064 }
2065
2066 static bool nested_vmcb_checks(struct vmcb *vmcb)
2067 {
2068         if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2069                 return false;
2070
2071         if (vmcb->control.asid == 0)
2072                 return false;
2073
2074         return true;
2075 }
2076
2077 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2078 {
2079         struct vmcb *nested_vmcb;
2080         struct vmcb *hsave = svm->nested.hsave;
2081         struct vmcb *vmcb = svm->vmcb;
2082         struct page *page;
2083         u64 vmcb_gpa;
2084
2085         vmcb_gpa = svm->vmcb->save.rax;
2086
2087         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2088         if (!nested_vmcb)
2089                 return false;
2090
2091         if (!nested_vmcb_checks(nested_vmcb)) {
2092                 nested_vmcb->control.exit_code    = SVM_EXIT_ERR;
2093                 nested_vmcb->control.exit_code_hi = 0;
2094                 nested_vmcb->control.exit_info_1  = 0;
2095                 nested_vmcb->control.exit_info_2  = 0;
2096
2097                 nested_svm_unmap(page);
2098
2099                 return false;
2100         }
2101
2102         trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2103                                nested_vmcb->save.rip,
2104                                nested_vmcb->control.int_ctl,
2105                                nested_vmcb->control.event_inj,
2106                                nested_vmcb->control.nested_ctl);
2107
2108         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr_read,
2109                                     nested_vmcb->control.intercept_cr_write,
2110                                     nested_vmcb->control.intercept_exceptions,
2111                                     nested_vmcb->control.intercept);
2112
2113         /* Clear internal status */
2114         kvm_clear_exception_queue(&svm->vcpu);
2115         kvm_clear_interrupt_queue(&svm->vcpu);
2116
2117         /*
2118          * Save the old vmcb, so we don't need to pick what we save, but can
2119          * restore everything when a VMEXIT occurs
2120          */
2121         hsave->save.es     = vmcb->save.es;
2122         hsave->save.cs     = vmcb->save.cs;
2123         hsave->save.ss     = vmcb->save.ss;
2124         hsave->save.ds     = vmcb->save.ds;
2125         hsave->save.gdtr   = vmcb->save.gdtr;
2126         hsave->save.idtr   = vmcb->save.idtr;
2127         hsave->save.efer   = svm->vcpu.arch.efer;
2128         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
2129         hsave->save.cr4    = svm->vcpu.arch.cr4;
2130         hsave->save.rflags = vmcb->save.rflags;
2131         hsave->save.rip    = kvm_rip_read(&svm->vcpu);
2132         hsave->save.rsp    = vmcb->save.rsp;
2133         hsave->save.rax    = vmcb->save.rax;
2134         if (npt_enabled)
2135                 hsave->save.cr3    = vmcb->save.cr3;
2136         else
2137                 hsave->save.cr3    = svm->vcpu.arch.cr3;
2138
2139         copy_vmcb_control_area(hsave, vmcb);
2140
2141         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2142                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2143         else
2144                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2145
2146         /* Load the nested guest state */
2147         svm->vmcb->save.es = nested_vmcb->save.es;
2148         svm->vmcb->save.cs = nested_vmcb->save.cs;
2149         svm->vmcb->save.ss = nested_vmcb->save.ss;
2150         svm->vmcb->save.ds = nested_vmcb->save.ds;
2151         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2152         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2153         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2154         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2155         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2156         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2157         if (npt_enabled) {
2158                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2159                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2160         } else
2161                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2162
2163         /* Guest paging mode is active - reset mmu */
2164         kvm_mmu_reset_context(&svm->vcpu);
2165
2166         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2167         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2168         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2169         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2170
2171         /* In case we don't even reach vcpu_run, the fields are not updated */
2172         svm->vmcb->save.rax = nested_vmcb->save.rax;
2173         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2174         svm->vmcb->save.rip = nested_vmcb->save.rip;
2175         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2176         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2177         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2178
2179         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2180         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
2181
2182         /* cache intercepts */
2183         svm->nested.intercept_cr_read    = nested_vmcb->control.intercept_cr_read;
2184         svm->nested.intercept_cr_write   = nested_vmcb->control.intercept_cr_write;
2185         svm->nested.intercept_dr_read    = nested_vmcb->control.intercept_dr_read;
2186         svm->nested.intercept_dr_write   = nested_vmcb->control.intercept_dr_write;
2187         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2188         svm->nested.intercept            = nested_vmcb->control.intercept;
2189
2190         force_new_asid(&svm->vcpu);
2191         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2192         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2193                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2194         else
2195                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2196
2197         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2198                 /* We only want the cr8 intercept bits of the guest */
2199                 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
2200                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2201         }
2202
2203         /* We don't want to see VMMCALLs from a nested guest */
2204         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMMCALL);
2205
2206         /*
2207          * We don't want a nested guest to be more powerful than the guest, so
2208          * all intercepts are ORed
2209          */
2210         svm->vmcb->control.intercept_cr_read |=
2211                 nested_vmcb->control.intercept_cr_read;
2212         svm->vmcb->control.intercept_cr_write |=
2213                 nested_vmcb->control.intercept_cr_write;
2214         svm->vmcb->control.intercept_dr_read |=
2215                 nested_vmcb->control.intercept_dr_read;
2216         svm->vmcb->control.intercept_dr_write |=
2217                 nested_vmcb->control.intercept_dr_write;
2218         svm->vmcb->control.intercept_exceptions |=
2219                 nested_vmcb->control.intercept_exceptions;
2220
2221         svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
2222
2223         svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2224         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2225         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2226         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2227         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2228         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2229
2230         nested_svm_unmap(page);
2231
2232         /* nested_vmcb is our indicator if nested SVM is activated */
2233         svm->nested.vmcb = vmcb_gpa;
2234
2235         enable_gif(svm);
2236
2237         return true;
2238 }
2239
2240 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2241 {
2242         to_vmcb->save.fs = from_vmcb->save.fs;
2243         to_vmcb->save.gs = from_vmcb->save.gs;
2244         to_vmcb->save.tr = from_vmcb->save.tr;
2245         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2246         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2247         to_vmcb->save.star = from_vmcb->save.star;
2248         to_vmcb->save.lstar = from_vmcb->save.lstar;
2249         to_vmcb->save.cstar = from_vmcb->save.cstar;
2250         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2251         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2252         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2253         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2254 }
2255
2256 static int vmload_interception(struct vcpu_svm *svm)
2257 {
2258         struct vmcb *nested_vmcb;
2259         struct page *page;
2260
2261         if (nested_svm_check_permissions(svm))
2262                 return 1;
2263
2264         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2265         skip_emulated_instruction(&svm->vcpu);
2266
2267         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2268         if (!nested_vmcb)
2269                 return 1;
2270
2271         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2272         nested_svm_unmap(page);
2273
2274         return 1;
2275 }
2276
2277 static int vmsave_interception(struct vcpu_svm *svm)
2278 {
2279         struct vmcb *nested_vmcb;
2280         struct page *page;
2281
2282         if (nested_svm_check_permissions(svm))
2283                 return 1;
2284
2285         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2286         skip_emulated_instruction(&svm->vcpu);
2287
2288         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2289         if (!nested_vmcb)
2290                 return 1;
2291
2292         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2293         nested_svm_unmap(page);
2294
2295         return 1;
2296 }
2297
2298 static int vmrun_interception(struct vcpu_svm *svm)
2299 {
2300         if (nested_svm_check_permissions(svm))
2301                 return 1;
2302
2303         /* Save rip after vmrun instruction */
2304         kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2305
2306         if (!nested_svm_vmrun(svm))
2307                 return 1;
2308
2309         if (!nested_svm_vmrun_msrpm(svm))
2310                 goto failed;
2311
2312         return 1;
2313
2314 failed:
2315
2316         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
2317         svm->vmcb->control.exit_code_hi = 0;
2318         svm->vmcb->control.exit_info_1  = 0;
2319         svm->vmcb->control.exit_info_2  = 0;
2320
2321         nested_svm_vmexit(svm);
2322
2323         return 1;
2324 }
2325
2326 static int stgi_interception(struct vcpu_svm *svm)
2327 {
2328         if (nested_svm_check_permissions(svm))
2329                 return 1;
2330
2331         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2332         skip_emulated_instruction(&svm->vcpu);
2333
2334         enable_gif(svm);
2335
2336         return 1;
2337 }
2338
2339 static int clgi_interception(struct vcpu_svm *svm)
2340 {
2341         if (nested_svm_check_permissions(svm))
2342                 return 1;
2343
2344         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2345         skip_emulated_instruction(&svm->vcpu);
2346
2347         disable_gif(svm);
2348
2349         /* After a CLGI no interrupts should come */
2350         svm_clear_vintr(svm);
2351         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2352
2353         return 1;
2354 }
2355
2356 static int invlpga_interception(struct vcpu_svm *svm)
2357 {
2358         struct kvm_vcpu *vcpu = &svm->vcpu;
2359
2360         trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2361                           vcpu->arch.regs[VCPU_REGS_RAX]);
2362
2363         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2364         kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2365
2366         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2367         skip_emulated_instruction(&svm->vcpu);
2368         return 1;
2369 }
2370
2371 static int skinit_interception(struct vcpu_svm *svm)
2372 {
2373         trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2374
2375         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2376         return 1;
2377 }
2378
2379 static int invalid_op_interception(struct vcpu_svm *svm)
2380 {
2381         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2382         return 1;
2383 }
2384
2385 static int task_switch_interception(struct vcpu_svm *svm)
2386 {
2387         u16 tss_selector;
2388         int reason;
2389         int int_type = svm->vmcb->control.exit_int_info &
2390                 SVM_EXITINTINFO_TYPE_MASK;
2391         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2392         uint32_t type =
2393                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2394         uint32_t idt_v =
2395                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2396         bool has_error_code = false;
2397         u32 error_code = 0;
2398
2399         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2400
2401         if (svm->vmcb->control.exit_info_2 &
2402             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2403                 reason = TASK_SWITCH_IRET;
2404         else if (svm->vmcb->control.exit_info_2 &
2405                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2406                 reason = TASK_SWITCH_JMP;
2407         else if (idt_v)
2408                 reason = TASK_SWITCH_GATE;
2409         else
2410                 reason = TASK_SWITCH_CALL;
2411
2412         if (reason == TASK_SWITCH_GATE) {
2413                 switch (type) {
2414                 case SVM_EXITINTINFO_TYPE_NMI:
2415                         svm->vcpu.arch.nmi_injected = false;
2416                         break;
2417                 case SVM_EXITINTINFO_TYPE_EXEPT:
2418                         if (svm->vmcb->control.exit_info_2 &
2419                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2420                                 has_error_code = true;
2421                                 error_code =
2422                                         (u32)svm->vmcb->control.exit_info_2;
2423                         }
2424                         kvm_clear_exception_queue(&svm->vcpu);
2425                         break;
2426                 case SVM_EXITINTINFO_TYPE_INTR:
2427                         kvm_clear_interrupt_queue(&svm->vcpu);
2428                         break;
2429                 default:
2430                         break;
2431                 }
2432         }
2433
2434         if (reason != TASK_SWITCH_GATE ||
2435             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2436             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2437              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2438                 skip_emulated_instruction(&svm->vcpu);
2439
2440         if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2441                                 has_error_code, error_code) == EMULATE_FAIL) {
2442                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2443                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2444                 svm->vcpu.run->internal.ndata = 0;
2445                 return 0;
2446         }
2447         return 1;
2448 }
2449
2450 static int cpuid_interception(struct vcpu_svm *svm)
2451 {
2452         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2453         kvm_emulate_cpuid(&svm->vcpu);
2454         return 1;
2455 }
2456
2457 static int iret_interception(struct vcpu_svm *svm)
2458 {
2459         ++svm->vcpu.stat.nmi_window_exits;
2460         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
2461         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2462         return 1;
2463 }
2464
2465 static int invlpg_interception(struct vcpu_svm *svm)
2466 {
2467         return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2468 }
2469
2470 static int emulate_on_interception(struct vcpu_svm *svm)
2471 {
2472         return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2473 }
2474
2475 static int cr0_write_interception(struct vcpu_svm *svm)
2476 {
2477         struct kvm_vcpu *vcpu = &svm->vcpu;
2478         int r;
2479
2480         r = emulate_instruction(&svm->vcpu, 0, 0, 0);
2481
2482         if (svm->nested.vmexit_rip) {
2483                 kvm_register_write(vcpu, VCPU_REGS_RIP, svm->nested.vmexit_rip);
2484                 kvm_register_write(vcpu, VCPU_REGS_RSP, svm->nested.vmexit_rsp);
2485                 kvm_register_write(vcpu, VCPU_REGS_RAX, svm->nested.vmexit_rax);
2486                 svm->nested.vmexit_rip = 0;
2487         }
2488
2489         return r == EMULATE_DONE;
2490 }
2491
2492 static int cr8_write_interception(struct vcpu_svm *svm)
2493 {
2494         struct kvm_run *kvm_run = svm->vcpu.run;
2495
2496         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2497         /* instruction emulation calls kvm_set_cr8() */
2498         emulate_instruction(&svm->vcpu, 0, 0, 0);
2499         if (irqchip_in_kernel(svm->vcpu.kvm)) {
2500                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2501                 return 1;
2502         }
2503         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2504                 return 1;
2505         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2506         return 0;
2507 }
2508
2509 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2510 {
2511         struct vcpu_svm *svm = to_svm(vcpu);
2512
2513         switch (ecx) {
2514         case MSR_IA32_TSC: {
2515                 u64 tsc_offset;
2516
2517                 if (is_nested(svm))
2518                         tsc_offset = svm->nested.hsave->control.tsc_offset;
2519                 else
2520                         tsc_offset = svm->vmcb->control.tsc_offset;
2521
2522                 *data = tsc_offset + native_read_tsc();
2523                 break;
2524         }
2525         case MSR_STAR:
2526                 *data = svm->vmcb->save.star;
2527                 break;
2528 #ifdef CONFIG_X86_64
2529         case MSR_LSTAR:
2530                 *data = svm->vmcb->save.lstar;
2531                 break;
2532         case MSR_CSTAR:
2533                 *data = svm->vmcb->save.cstar;
2534                 break;
2535         case MSR_KERNEL_GS_BASE:
2536                 *data = svm->vmcb->save.kernel_gs_base;
2537                 break;
2538         case MSR_SYSCALL_MASK:
2539                 *data = svm->vmcb->save.sfmask;
2540                 break;
2541 #endif
2542         case MSR_IA32_SYSENTER_CS:
2543                 *data = svm->vmcb->save.sysenter_cs;
2544                 break;
2545         case MSR_IA32_SYSENTER_EIP:
2546                 *data = svm->sysenter_eip;
2547                 break;
2548         case MSR_IA32_SYSENTER_ESP:
2549                 *data = svm->sysenter_esp;
2550                 break;
2551         /*
2552          * Nobody will change the following 5 values in the VMCB so we can
2553          * safely return them on rdmsr. They will always be 0 until LBRV is
2554          * implemented.
2555          */
2556         case MSR_IA32_DEBUGCTLMSR:
2557                 *data = svm->vmcb->save.dbgctl;
2558                 break;
2559         case MSR_IA32_LASTBRANCHFROMIP:
2560                 *data = svm->vmcb->save.br_from;
2561                 break;
2562         case MSR_IA32_LASTBRANCHTOIP:
2563                 *data = svm->vmcb->save.br_to;
2564                 break;
2565         case MSR_IA32_LASTINTFROMIP:
2566                 *data = svm->vmcb->save.last_excp_from;
2567                 break;
2568         case MSR_IA32_LASTINTTOIP:
2569                 *data = svm->vmcb->save.last_excp_to;
2570                 break;
2571         case MSR_VM_HSAVE_PA:
2572                 *data = svm->nested.hsave_msr;
2573                 break;
2574         case MSR_VM_CR:
2575                 *data = svm->nested.vm_cr_msr;
2576                 break;
2577         case MSR_IA32_UCODE_REV:
2578                 *data = 0x01000065;
2579                 break;
2580         default:
2581                 return kvm_get_msr_common(vcpu, ecx, data);
2582         }
2583         return 0;
2584 }
2585
2586 static int rdmsr_interception(struct vcpu_svm *svm)
2587 {
2588         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2589         u64 data;
2590
2591         if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2592                 trace_kvm_msr_read_ex(ecx);
2593                 kvm_inject_gp(&svm->vcpu, 0);
2594         } else {
2595                 trace_kvm_msr_read(ecx, data);
2596
2597                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2598                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2599                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2600                 skip_emulated_instruction(&svm->vcpu);
2601         }
2602         return 1;
2603 }
2604
2605 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2606 {
2607         struct vcpu_svm *svm = to_svm(vcpu);
2608         int svm_dis, chg_mask;
2609
2610         if (data & ~SVM_VM_CR_VALID_MASK)
2611                 return 1;
2612
2613         chg_mask = SVM_VM_CR_VALID_MASK;
2614
2615         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2616                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2617
2618         svm->nested.vm_cr_msr &= ~chg_mask;
2619         svm->nested.vm_cr_msr |= (data & chg_mask);
2620
2621         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2622
2623         /* check for svm_disable while efer.svme is set */
2624         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2625                 return 1;
2626
2627         return 0;
2628 }
2629
2630 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2631 {
2632         struct vcpu_svm *svm = to_svm(vcpu);
2633
2634         switch (ecx) {
2635         case MSR_IA32_TSC:
2636                 kvm_write_tsc(vcpu, data);
2637                 break;
2638         case MSR_STAR:
2639                 svm->vmcb->save.star = data;
2640                 break;
2641 #ifdef CONFIG_X86_64
2642         case MSR_LSTAR:
2643                 svm->vmcb->save.lstar = data;
2644                 break;
2645         case MSR_CSTAR:
2646                 svm->vmcb->save.cstar = data;
2647                 break;
2648         case MSR_KERNEL_GS_BASE:
2649                 svm->vmcb->save.kernel_gs_base = data;
2650                 break;
2651         case MSR_SYSCALL_MASK:
2652                 svm->vmcb->save.sfmask = data;
2653                 break;
2654 #endif
2655         case MSR_IA32_SYSENTER_CS:
2656                 svm->vmcb->save.sysenter_cs = data;
2657                 break;
2658         case MSR_IA32_SYSENTER_EIP:
2659                 svm->sysenter_eip = data;
2660                 svm->vmcb->save.sysenter_eip = data;
2661                 break;
2662         case MSR_IA32_SYSENTER_ESP:
2663                 svm->sysenter_esp = data;
2664                 svm->vmcb->save.sysenter_esp = data;
2665                 break;
2666         case MSR_IA32_DEBUGCTLMSR:
2667                 if (!svm_has(SVM_FEATURE_LBRV)) {
2668                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2669                                         __func__, data);
2670                         break;
2671                 }
2672                 if (data & DEBUGCTL_RESERVED_BITS)
2673                         return 1;
2674
2675                 svm->vmcb->save.dbgctl = data;
2676                 if (data & (1ULL<<0))
2677                         svm_enable_lbrv(svm);
2678                 else
2679                         svm_disable_lbrv(svm);
2680                 break;
2681         case MSR_VM_HSAVE_PA:
2682                 svm->nested.hsave_msr = data;
2683                 break;
2684         case MSR_VM_CR:
2685                 return svm_set_vm_cr(vcpu, data);
2686         case MSR_VM_IGNNE:
2687                 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2688                 break;
2689         default:
2690                 return kvm_set_msr_common(vcpu, ecx, data);
2691         }
2692         return 0;
2693 }
2694
2695 static int wrmsr_interception(struct vcpu_svm *svm)
2696 {
2697         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2698         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2699                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2700
2701
2702         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2703         if (svm_set_msr(&svm->vcpu, ecx, data)) {
2704                 trace_kvm_msr_write_ex(ecx, data);
2705                 kvm_inject_gp(&svm->vcpu, 0);
2706         } else {
2707                 trace_kvm_msr_write(ecx, data);
2708                 skip_emulated_instruction(&svm->vcpu);
2709         }
2710         return 1;
2711 }
2712
2713 static int msr_interception(struct vcpu_svm *svm)
2714 {
2715         if (svm->vmcb->control.exit_info_1)
2716                 return wrmsr_interception(svm);
2717         else
2718                 return rdmsr_interception(svm);
2719 }
2720
2721 static int interrupt_window_interception(struct vcpu_svm *svm)
2722 {
2723         struct kvm_run *kvm_run = svm->vcpu.run;
2724
2725         svm_clear_vintr(svm);
2726         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2727         /*
2728          * If the user space waits to inject interrupts, exit as soon as
2729          * possible
2730          */
2731         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2732             kvm_run->request_interrupt_window &&
2733             !kvm_cpu_has_interrupt(&svm->vcpu)) {
2734                 ++svm->vcpu.stat.irq_window_exits;
2735                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2736                 return 0;
2737         }
2738
2739         return 1;
2740 }
2741
2742 static int pause_interception(struct vcpu_svm *svm)
2743 {
2744         kvm_vcpu_on_spin(&(svm->vcpu));
2745         return 1;
2746 }
2747
2748 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2749         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
2750         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
2751         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
2752         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
2753         [SVM_EXIT_CR0_SEL_WRITE]                = emulate_on_interception,
2754         [SVM_EXIT_WRITE_CR0]                    = cr0_write_interception,
2755         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
2756         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
2757         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2758         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
2759         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
2760         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
2761         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
2762         [SVM_EXIT_READ_DR4]                     = emulate_on_interception,
2763         [SVM_EXIT_READ_DR5]                     = emulate_on_interception,
2764         [SVM_EXIT_READ_DR6]                     = emulate_on_interception,
2765         [SVM_EXIT_READ_DR7]                     = emulate_on_interception,
2766         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
2767         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
2768         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
2769         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
2770         [SVM_EXIT_WRITE_DR4]                    = emulate_on_interception,
2771         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
2772         [SVM_EXIT_WRITE_DR6]                    = emulate_on_interception,
2773         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
2774         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2775         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2776         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2777         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2778         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
2779         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2780         [SVM_EXIT_INTR]                         = intr_interception,
2781         [SVM_EXIT_NMI]                          = nmi_interception,
2782         [SVM_EXIT_SMI]                          = nop_on_interception,
2783         [SVM_EXIT_INIT]                         = nop_on_interception,
2784         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2785         [SVM_EXIT_CPUID]                        = cpuid_interception,
2786         [SVM_EXIT_IRET]                         = iret_interception,
2787         [SVM_EXIT_INVD]                         = emulate_on_interception,
2788         [SVM_EXIT_PAUSE]                        = pause_interception,
2789         [SVM_EXIT_HLT]                          = halt_interception,
2790         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2791         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
2792         [SVM_EXIT_IOIO]                         = io_interception,
2793         [SVM_EXIT_MSR]                          = msr_interception,
2794         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2795         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2796         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2797         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2798         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2799         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2800         [SVM_EXIT_STGI]                         = stgi_interception,
2801         [SVM_EXIT_CLGI]                         = clgi_interception,
2802         [SVM_EXIT_SKINIT]                       = skinit_interception,
2803         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
2804         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
2805         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
2806         [SVM_EXIT_NPF]                          = pf_interception,
2807 };
2808
2809 void dump_vmcb(struct kvm_vcpu *vcpu)
2810 {
2811         struct vcpu_svm *svm = to_svm(vcpu);
2812         struct vmcb_control_area *control = &svm->vmcb->control;
2813         struct vmcb_save_area *save = &svm->vmcb->save;
2814
2815         pr_err("VMCB Control Area:\n");
2816         pr_err("cr_read:            %04x\n", control->intercept_cr_read);
2817         pr_err("cr_write:           %04x\n", control->intercept_cr_write);
2818         pr_err("dr_read:            %04x\n", control->intercept_dr_read);
2819         pr_err("dr_write:           %04x\n", control->intercept_dr_write);
2820         pr_err("exceptions:         %08x\n", control->intercept_exceptions);
2821         pr_err("intercepts:         %016llx\n", control->intercept);
2822         pr_err("pause filter count: %d\n", control->pause_filter_count);
2823         pr_err("iopm_base_pa:       %016llx\n", control->iopm_base_pa);
2824         pr_err("msrpm_base_pa:      %016llx\n", control->msrpm_base_pa);
2825         pr_err("tsc_offset:         %016llx\n", control->tsc_offset);
2826         pr_err("asid:               %d\n", control->asid);
2827         pr_err("tlb_ctl:            %d\n", control->tlb_ctl);
2828         pr_err("int_ctl:            %08x\n", control->int_ctl);
2829         pr_err("int_vector:         %08x\n", control->int_vector);
2830         pr_err("int_state:          %08x\n", control->int_state);
2831         pr_err("exit_code:          %08x\n", control->exit_code);
2832         pr_err("exit_info1:         %016llx\n", control->exit_info_1);
2833         pr_err("exit_info2:         %016llx\n", control->exit_info_2);
2834         pr_err("exit_int_info:      %08x\n", control->exit_int_info);
2835         pr_err("exit_int_info_err:  %08x\n", control->exit_int_info_err);
2836         pr_err("nested_ctl:         %lld\n", control->nested_ctl);
2837         pr_err("nested_cr3:         %016llx\n", control->nested_cr3);
2838         pr_err("event_inj:          %08x\n", control->event_inj);
2839         pr_err("event_inj_err:      %08x\n", control->event_inj_err);
2840         pr_err("lbr_ctl:            %lld\n", control->lbr_ctl);
2841         pr_err("next_rip:           %016llx\n", control->next_rip);
2842         pr_err("VMCB State Save Area:\n");
2843         pr_err("es:   s: %04x a: %04x l: %08x b: %016llx\n",
2844                 save->es.selector, save->es.attrib,
2845                 save->es.limit, save->es.base);
2846         pr_err("cs:   s: %04x a: %04x l: %08x b: %016llx\n",
2847                 save->cs.selector, save->cs.attrib,
2848                 save->cs.limit, save->cs.base);
2849         pr_err("ss:   s: %04x a: %04x l: %08x b: %016llx\n",
2850                 save->ss.selector, save->ss.attrib,
2851                 save->ss.limit, save->ss.base);
2852         pr_err("ds:   s: %04x a: %04x l: %08x b: %016llx\n",
2853                 save->ds.selector, save->ds.attrib,
2854                 save->ds.limit, save->ds.base);
2855         pr_err("fs:   s: %04x a: %04x l: %08x b: %016llx\n",
2856                 save->fs.selector, save->fs.attrib,
2857                 save->fs.limit, save->fs.base);
2858         pr_err("gs:   s: %04x a: %04x l: %08x b: %016llx\n",
2859                 save->gs.selector, save->gs.attrib,
2860                 save->gs.limit, save->gs.base);
2861         pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
2862                 save->gdtr.selector, save->gdtr.attrib,
2863                 save->gdtr.limit, save->gdtr.base);
2864         pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
2865                 save->ldtr.selector, save->ldtr.attrib,
2866                 save->ldtr.limit, save->ldtr.base);
2867         pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
2868                 save->idtr.selector, save->idtr.attrib,
2869                 save->idtr.limit, save->idtr.base);
2870         pr_err("tr:   s: %04x a: %04x l: %08x b: %016llx\n",
2871                 save->tr.selector, save->tr.attrib,
2872                 save->tr.limit, save->tr.base);
2873         pr_err("cpl:            %d                efer:         %016llx\n",
2874                 save->cpl, save->efer);
2875         pr_err("cr0:            %016llx cr2:          %016llx\n",
2876                 save->cr0, save->cr2);
2877         pr_err("cr3:            %016llx cr4:          %016llx\n",
2878                 save->cr3, save->cr4);
2879         pr_err("dr6:            %016llx dr7:          %016llx\n",
2880                 save->dr6, save->dr7);
2881         pr_err("rip:            %016llx rflags:       %016llx\n",
2882                 save->rip, save->rflags);
2883         pr_err("rsp:            %016llx rax:          %016llx\n",
2884                 save->rsp, save->rax);
2885         pr_err("star:           %016llx lstar:        %016llx\n",
2886                 save->star, save->lstar);
2887         pr_err("cstar:          %016llx sfmask:       %016llx\n",
2888                 save->cstar, save->sfmask);
2889         pr_err("kernel_gs_base: %016llx sysenter_cs:  %016llx\n",
2890                 save->kernel_gs_base, save->sysenter_cs);
2891         pr_err("sysenter_esp:   %016llx sysenter_eip: %016llx\n",
2892                 save->sysenter_esp, save->sysenter_eip);
2893         pr_err("gpat:           %016llx dbgctl:       %016llx\n",
2894                 save->g_pat, save->dbgctl);
2895         pr_err("br_from:        %016llx br_to:        %016llx\n",
2896                 save->br_from, save->br_to);
2897         pr_err("excp_from:      %016llx excp_to:      %016llx\n",
2898                 save->last_excp_from, save->last_excp_to);
2899
2900 }
2901
2902 static int handle_exit(struct kvm_vcpu *vcpu)
2903 {
2904         struct vcpu_svm *svm = to_svm(vcpu);
2905         struct kvm_run *kvm_run = vcpu->run;
2906         u32 exit_code = svm->vmcb->control.exit_code;
2907
2908         trace_kvm_exit(exit_code, vcpu);
2909
2910         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
2911                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2912         if (npt_enabled)
2913                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2914
2915         if (unlikely(svm->nested.exit_required)) {
2916                 nested_svm_vmexit(svm);
2917                 svm->nested.exit_required = false;
2918
2919                 return 1;
2920         }
2921
2922         if (is_nested(svm)) {
2923                 int vmexit;
2924
2925                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2926                                         svm->vmcb->control.exit_info_1,
2927                                         svm->vmcb->control.exit_info_2,
2928                                         svm->vmcb->control.exit_int_info,
2929                                         svm->vmcb->control.exit_int_info_err);
2930
2931                 vmexit = nested_svm_exit_special(svm);
2932
2933                 if (vmexit == NESTED_EXIT_CONTINUE)
2934                         vmexit = nested_svm_exit_handled(svm);
2935
2936                 if (vmexit == NESTED_EXIT_DONE)
2937                         return 1;
2938         }
2939
2940         svm_complete_interrupts(svm);
2941
2942         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2943                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2944                 kvm_run->fail_entry.hardware_entry_failure_reason
2945                         = svm->vmcb->control.exit_code;
2946                 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
2947                 dump_vmcb(vcpu);
2948                 return 0;
2949         }
2950
2951         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2952             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2953             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2954                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2955                        "exit_code 0x%x\n",
2956                        __func__, svm->vmcb->control.exit_int_info,
2957                        exit_code);
2958
2959         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2960             || !svm_exit_handlers[exit_code]) {
2961                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2962                 kvm_run->hw.hardware_exit_reason = exit_code;
2963                 return 0;
2964         }
2965
2966         return svm_exit_handlers[exit_code](svm);
2967 }
2968
2969 static void reload_tss(struct kvm_vcpu *vcpu)
2970 {
2971         int cpu = raw_smp_processor_id();
2972
2973         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2974         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
2975         load_TR_desc();
2976 }
2977
2978 static void pre_svm_run(struct vcpu_svm *svm)
2979 {
2980         int cpu = raw_smp_processor_id();
2981
2982         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2983
2984         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2985         /* FIXME: handle wraparound of asid_generation */
2986         if (svm->asid_generation != sd->asid_generation)
2987                 new_asid(svm, sd);
2988 }
2989
2990 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2991 {
2992         struct vcpu_svm *svm = to_svm(vcpu);
2993
2994         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2995         vcpu->arch.hflags |= HF_NMI_MASK;
2996         svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
2997         ++vcpu->stat.nmi_injections;
2998 }
2999
3000 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3001 {
3002         struct vmcb_control_area *control;
3003
3004         control = &svm->vmcb->control;
3005         control->int_vector = irq;
3006         control->int_ctl &= ~V_INTR_PRIO_MASK;
3007         control->int_ctl |= V_IRQ_MASK |
3008                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3009 }
3010
3011 static void svm_set_irq(struct kvm_vcpu *vcpu)
3012 {
3013         struct vcpu_svm *svm = to_svm(vcpu);
3014
3015         BUG_ON(!(gif_set(svm)));
3016
3017         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3018         ++vcpu->stat.irq_injections;
3019
3020         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3021                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3022 }
3023
3024 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3025 {
3026         struct vcpu_svm *svm = to_svm(vcpu);
3027
3028         if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3029                 return;
3030
3031         if (irr == -1)
3032                 return;
3033
3034         if (tpr >= irr)
3035                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
3036 }
3037
3038 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3039 {
3040         struct vcpu_svm *svm = to_svm(vcpu);
3041         struct vmcb *vmcb = svm->vmcb;
3042         int ret;
3043         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3044               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3045         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3046
3047         return ret;
3048 }
3049
3050 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3051 {
3052         struct vcpu_svm *svm = to_svm(vcpu);
3053
3054         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3055 }
3056
3057 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3058 {
3059         struct vcpu_svm *svm = to_svm(vcpu);
3060
3061         if (masked) {
3062                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3063                 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
3064         } else {
3065                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3066                 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
3067         }
3068 }
3069
3070 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3071 {
3072         struct vcpu_svm *svm = to_svm(vcpu);
3073         struct vmcb *vmcb = svm->vmcb;
3074         int ret;
3075
3076         if (!gif_set(svm) ||
3077              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3078                 return 0;
3079
3080         ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3081
3082         if (is_nested(svm))
3083                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3084
3085         return ret;
3086 }
3087
3088 static void enable_irq_window(struct kvm_vcpu *vcpu)
3089 {
3090         struct vcpu_svm *svm = to_svm(vcpu);
3091
3092         /*
3093          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3094          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
3095          * get that intercept, this function will be called again though and
3096          * we'll get the vintr intercept.
3097          */
3098         if (gif_set(svm) && nested_svm_intr(svm)) {
3099                 svm_set_vintr(svm);
3100                 svm_inject_irq(svm, 0x0);
3101         }
3102 }
3103
3104 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3105 {
3106         struct vcpu_svm *svm = to_svm(vcpu);
3107
3108         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3109             == HF_NMI_MASK)
3110                 return; /* IRET will cause a vm exit */
3111
3112         /*
3113          * Something prevents NMI from been injected. Single step over possible
3114          * problem (IRET or exception injection or interrupt shadow)
3115          */
3116         svm->nmi_singlestep = true;
3117         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3118         update_db_intercept(vcpu);
3119 }
3120
3121 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3122 {
3123         return 0;
3124 }
3125
3126 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3127 {
3128         force_new_asid(vcpu);
3129 }
3130
3131 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3132 {
3133 }
3134
3135 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3136 {
3137         struct vcpu_svm *svm = to_svm(vcpu);
3138
3139         if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3140                 return;
3141
3142         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
3143                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3144                 kvm_set_cr8(vcpu, cr8);
3145         }
3146 }
3147
3148 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3149 {
3150         struct vcpu_svm *svm = to_svm(vcpu);
3151         u64 cr8;
3152
3153         if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3154                 return;
3155
3156         cr8 = kvm_get_cr8(vcpu);
3157         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3158         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3159 }
3160
3161 static void svm_complete_interrupts(struct vcpu_svm *svm)
3162 {
3163         u8 vector;
3164         int type;
3165         u32 exitintinfo = svm->vmcb->control.exit_int_info;
3166         unsigned int3_injected = svm->int3_injected;
3167
3168         svm->int3_injected = 0;
3169
3170         if (svm->vcpu.arch.hflags & HF_IRET_MASK)
3171                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3172
3173         svm->vcpu.arch.nmi_injected = false;
3174         kvm_clear_exception_queue(&svm->vcpu);
3175         kvm_clear_interrupt_queue(&svm->vcpu);
3176
3177         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3178                 return;
3179
3180         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3181         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3182
3183         switch (type) {
3184         case SVM_EXITINTINFO_TYPE_NMI:
3185                 svm->vcpu.arch.nmi_injected = true;
3186                 break;
3187         case SVM_EXITINTINFO_TYPE_EXEPT:
3188                 /*
3189                  * In case of software exceptions, do not reinject the vector,
3190                  * but re-execute the instruction instead. Rewind RIP first
3191                  * if we emulated INT3 before.
3192                  */
3193                 if (kvm_exception_is_soft(vector)) {
3194                         if (vector == BP_VECTOR && int3_injected &&
3195                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3196                                 kvm_rip_write(&svm->vcpu,
3197                                               kvm_rip_read(&svm->vcpu) -
3198                                               int3_injected);
3199                         break;
3200                 }
3201                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3202                         u32 err = svm->vmcb->control.exit_int_info_err;
3203                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
3204
3205                 } else
3206                         kvm_requeue_exception(&svm->vcpu, vector);
3207                 break;
3208         case SVM_EXITINTINFO_TYPE_INTR:
3209                 kvm_queue_interrupt(&svm->vcpu, vector, false);
3210                 break;
3211         default:
3212                 break;
3213         }
3214 }
3215
3216 #ifdef CONFIG_X86_64
3217 #define R "r"
3218 #else
3219 #define R "e"
3220 #endif
3221
3222 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3223 {
3224         struct vcpu_svm *svm = to_svm(vcpu);
3225         u16 fs_selector;
3226         u16 gs_selector;
3227         u16 ldt_selector;
3228
3229         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3230         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3231         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3232
3233         /*
3234          * A vmexit emulation is required before the vcpu can be executed
3235          * again.
3236          */
3237         if (unlikely(svm->nested.exit_required))
3238                 return;
3239
3240         pre_svm_run(svm);
3241
3242         sync_lapic_to_cr8(vcpu);
3243
3244         save_host_msrs(vcpu);
3245         savesegment(fs, fs_selector);
3246         savesegment(gs, gs_selector);
3247         ldt_selector = kvm_read_ldt();
3248         svm->vmcb->save.cr2 = vcpu->arch.cr2;
3249
3250         clgi();
3251
3252         local_irq_enable();
3253
3254         asm volatile (
3255                 "push %%"R"bp; \n\t"
3256                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3257                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3258                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3259                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3260                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3261                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3262 #ifdef CONFIG_X86_64
3263                 "mov %c[r8](%[svm]),  %%r8  \n\t"
3264                 "mov %c[r9](%[svm]),  %%r9  \n\t"
3265                 "mov %c[r10](%[svm]), %%r10 \n\t"
3266                 "mov %c[r11](%[svm]), %%r11 \n\t"
3267                 "mov %c[r12](%[svm]), %%r12 \n\t"
3268                 "mov %c[r13](%[svm]), %%r13 \n\t"
3269                 "mov %c[r14](%[svm]), %%r14 \n\t"
3270                 "mov %c[r15](%[svm]), %%r15 \n\t"
3271 #endif
3272
3273                 /* Enter guest mode */
3274                 "push %%"R"ax \n\t"
3275                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3276                 __ex(SVM_VMLOAD) "\n\t"
3277                 __ex(SVM_VMRUN) "\n\t"
3278                 __ex(SVM_VMSAVE) "\n\t"
3279                 "pop %%"R"ax \n\t"
3280
3281                 /* Save guest registers, load host registers */
3282                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3283                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3284                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3285                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3286                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3287                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3288 #ifdef CONFIG_X86_64
3289                 "mov %%r8,  %c[r8](%[svm]) \n\t"
3290                 "mov %%r9,  %c[r9](%[svm]) \n\t"
3291                 "mov %%r10, %c[r10](%[svm]) \n\t"
3292                 "mov %%r11, %c[r11](%[svm]) \n\t"
3293                 "mov %%r12, %c[r12](%[svm]) \n\t"
3294                 "mov %%r13, %c[r13](%[svm]) \n\t"
3295                 "mov %%r14, %c[r14](%[svm]) \n\t"
3296                 "mov %%r15, %c[r15](%[svm]) \n\t"
3297 #endif
3298                 "pop %%"R"bp"
3299                 :
3300                 : [svm]"a"(svm),
3301                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3302                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3303                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3304                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3305                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3306                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3307                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3308 #ifdef CONFIG_X86_64
3309                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3310                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3311                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3312                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3313                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3314                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3315                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3316                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3317 #endif
3318                 : "cc", "memory"
3319                 , R"bx", R"cx", R"dx", R"si", R"di"
3320 #ifdef CONFIG_X86_64
3321                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3322 #endif
3323                 );
3324
3325         vcpu->arch.cr2 = svm->vmcb->save.cr2;
3326         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3327         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3328         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3329
3330         load_host_msrs(vcpu);
3331         loadsegment(fs, fs_selector);
3332 #ifdef CONFIG_X86_64
3333         load_gs_index(gs_selector);
3334         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
3335 #else
3336         loadsegment(gs, gs_selector);
3337 #endif
3338         kvm_load_ldt(ldt_selector);
3339
3340         reload_tss(vcpu);
3341
3342         local_irq_disable();
3343
3344         stgi();
3345
3346         sync_cr8_to_lapic(vcpu);
3347
3348         svm->next_rip = 0;
3349
3350         if (npt_enabled) {
3351                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3352                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3353         }
3354
3355         /*
3356          * We need to handle MC intercepts here before the vcpu has a chance to
3357          * change the physical cpu
3358          */
3359         if (unlikely(svm->vmcb->control.exit_code ==
3360                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
3361                 svm_handle_mce(svm);
3362 }
3363
3364 #undef R
3365
3366 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3367 {
3368         struct vcpu_svm *svm = to_svm(vcpu);
3369
3370         svm->vmcb->save.cr3 = root;
3371         force_new_asid(vcpu);
3372 }
3373
3374 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3375 {
3376         struct vcpu_svm *svm = to_svm(vcpu);
3377
3378         svm->vmcb->control.nested_cr3 = root;
3379
3380         /* Also sync guest cr3 here in case we live migrate */
3381         svm->vmcb->save.cr3 = vcpu->arch.cr3;
3382
3383         force_new_asid(vcpu);
3384 }
3385
3386 static int is_disabled(void)
3387 {
3388         u64 vm_cr;
3389
3390         rdmsrl(MSR_VM_CR, vm_cr);
3391         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3392                 return 1;
3393
3394         return 0;
3395 }
3396
3397 static void
3398 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3399 {
3400         /*
3401          * Patch in the VMMCALL instruction:
3402          */
3403         hypercall[0] = 0x0f;
3404         hypercall[1] = 0x01;
3405         hypercall[2] = 0xd9;
3406 }
3407
3408 static void svm_check_processor_compat(void *rtn)
3409 {
3410         *(int *)rtn = 0;
3411 }
3412
3413 static bool svm_cpu_has_accelerated_tpr(void)
3414 {
3415         return false;
3416 }
3417
3418 static int get_npt_level(void)
3419 {
3420 #ifdef CONFIG_X86_64
3421         return PT64_ROOT_LEVEL;
3422 #else
3423         return PT32E_ROOT_LEVEL;
3424 #endif
3425 }
3426
3427 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3428 {
3429         return 0;
3430 }
3431
3432 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3433 {
3434 }
3435
3436 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3437 {
3438         switch (func) {
3439         case 0x8000000A:
3440                 entry->eax = 1; /* SVM revision 1 */
3441                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3442                                    ASID emulation to nested SVM */
3443                 entry->ecx = 0; /* Reserved */
3444                 entry->edx = 0; /* Per default do not support any
3445                                    additional features */
3446
3447                 /* Support next_rip if host supports it */
3448                 if (svm_has(SVM_FEATURE_NRIP))
3449                         entry->edx |= SVM_FEATURE_NRIP;
3450
3451                 break;
3452         }
3453 }
3454
3455 static const struct trace_print_flags svm_exit_reasons_str[] = {
3456         { SVM_EXIT_READ_CR0,                    "read_cr0" },
3457         { SVM_EXIT_READ_CR3,                    "read_cr3" },
3458         { SVM_EXIT_READ_CR4,                    "read_cr4" },
3459         { SVM_EXIT_READ_CR8,                    "read_cr8" },
3460         { SVM_EXIT_WRITE_CR0,                   "write_cr0" },
3461         { SVM_EXIT_WRITE_CR3,                   "write_cr3" },
3462         { SVM_EXIT_WRITE_CR4,                   "write_cr4" },
3463         { SVM_EXIT_WRITE_CR8,                   "write_cr8" },
3464         { SVM_EXIT_READ_DR0,                    "read_dr0" },
3465         { SVM_EXIT_READ_DR1,                    "read_dr1" },
3466         { SVM_EXIT_READ_DR2,                    "read_dr2" },
3467         { SVM_EXIT_READ_DR3,                    "read_dr3" },
3468         { SVM_EXIT_WRITE_DR0,                   "write_dr0" },
3469         { SVM_EXIT_WRITE_DR1,                   "write_dr1" },
3470         { SVM_EXIT_WRITE_DR2,                   "write_dr2" },
3471         { SVM_EXIT_WRITE_DR3,                   "write_dr3" },
3472         { SVM_EXIT_WRITE_DR5,                   "write_dr5" },
3473         { SVM_EXIT_WRITE_DR7,                   "write_dr7" },
3474         { SVM_EXIT_EXCP_BASE + DB_VECTOR,       "DB excp" },
3475         { SVM_EXIT_EXCP_BASE + BP_VECTOR,       "BP excp" },
3476         { SVM_EXIT_EXCP_BASE + UD_VECTOR,       "UD excp" },
3477         { SVM_EXIT_EXCP_BASE + PF_VECTOR,       "PF excp" },
3478         { SVM_EXIT_EXCP_BASE + NM_VECTOR,       "NM excp" },
3479         { SVM_EXIT_EXCP_BASE + MC_VECTOR,       "MC excp" },
3480         { SVM_EXIT_INTR,                        "interrupt" },
3481         { SVM_EXIT_NMI,                         "nmi" },
3482         { SVM_EXIT_SMI,                         "smi" },
3483         { SVM_EXIT_INIT,                        "init" },
3484         { SVM_EXIT_VINTR,                       "vintr" },
3485         { SVM_EXIT_CPUID,                       "cpuid" },
3486         { SVM_EXIT_INVD,                        "invd" },
3487         { SVM_EXIT_HLT,                         "hlt" },
3488         { SVM_EXIT_INVLPG,                      "invlpg" },
3489         { SVM_EXIT_INVLPGA,                     "invlpga" },
3490         { SVM_EXIT_IOIO,                        "io" },
3491         { SVM_EXIT_MSR,                         "msr" },
3492         { SVM_EXIT_TASK_SWITCH,                 "task_switch" },
3493         { SVM_EXIT_SHUTDOWN,                    "shutdown" },
3494         { SVM_EXIT_VMRUN,                       "vmrun" },
3495         { SVM_EXIT_VMMCALL,                     "hypercall" },
3496         { SVM_EXIT_VMLOAD,                      "vmload" },
3497         { SVM_EXIT_VMSAVE,                      "vmsave" },
3498         { SVM_EXIT_STGI,                        "stgi" },
3499         { SVM_EXIT_CLGI,                        "clgi" },
3500         { SVM_EXIT_SKINIT,                      "skinit" },
3501         { SVM_EXIT_WBINVD,                      "wbinvd" },
3502         { SVM_EXIT_MONITOR,                     "monitor" },
3503         { SVM_EXIT_MWAIT,                       "mwait" },
3504         { SVM_EXIT_NPF,                         "npf" },
3505         { -1, NULL }
3506 };
3507
3508 static int svm_get_lpage_level(void)
3509 {
3510         return PT_PDPE_LEVEL;
3511 }
3512
3513 static bool svm_rdtscp_supported(void)
3514 {
3515         return false;
3516 }
3517
3518 static bool svm_has_wbinvd_exit(void)
3519 {
3520         return true;
3521 }
3522
3523 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3524 {
3525         struct vcpu_svm *svm = to_svm(vcpu);
3526
3527         svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
3528         if (is_nested(svm))
3529                 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3530         update_cr0_intercept(svm);
3531 }
3532
3533 static struct kvm_x86_ops svm_x86_ops = {
3534         .cpu_has_kvm_support = has_svm,
3535         .disabled_by_bios = is_disabled,
3536         .hardware_setup = svm_hardware_setup,
3537         .hardware_unsetup = svm_hardware_unsetup,
3538         .check_processor_compatibility = svm_check_processor_compat,
3539         .hardware_enable = svm_hardware_enable,
3540         .hardware_disable = svm_hardware_disable,
3541         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3542
3543         .vcpu_create = svm_create_vcpu,
3544         .vcpu_free = svm_free_vcpu,
3545         .vcpu_reset = svm_vcpu_reset,
3546
3547         .prepare_guest_switch = svm_prepare_guest_switch,
3548         .vcpu_load = svm_vcpu_load,
3549         .vcpu_put = svm_vcpu_put,
3550
3551         .set_guest_debug = svm_guest_debug,
3552         .get_msr = svm_get_msr,
3553         .set_msr = svm_set_msr,
3554         .get_segment_base = svm_get_segment_base,
3555         .get_segment = svm_get_segment,
3556         .set_segment = svm_set_segment,
3557         .get_cpl = svm_get_cpl,
3558         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3559         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3560         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3561         .set_cr0 = svm_set_cr0,
3562         .set_cr3 = svm_set_cr3,
3563         .set_cr4 = svm_set_cr4,
3564         .set_efer = svm_set_efer,
3565         .get_idt = svm_get_idt,
3566         .set_idt = svm_set_idt,
3567         .get_gdt = svm_get_gdt,
3568         .set_gdt = svm_set_gdt,
3569         .set_dr7 = svm_set_dr7,
3570         .cache_reg = svm_cache_reg,
3571         .get_rflags = svm_get_rflags,
3572         .set_rflags = svm_set_rflags,
3573         .fpu_activate = svm_fpu_activate,
3574         .fpu_deactivate = svm_fpu_deactivate,
3575
3576         .tlb_flush = svm_flush_tlb,
3577
3578         .run = svm_vcpu_run,
3579         .handle_exit = handle_exit,
3580         .skip_emulated_instruction = skip_emulated_instruction,
3581         .set_interrupt_shadow = svm_set_interrupt_shadow,
3582         .get_interrupt_shadow = svm_get_interrupt_shadow,
3583         .patch_hypercall = svm_patch_hypercall,
3584         .set_irq = svm_set_irq,
3585         .set_nmi = svm_inject_nmi,
3586         .queue_exception = svm_queue_exception,
3587         .interrupt_allowed = svm_interrupt_allowed,
3588         .nmi_allowed = svm_nmi_allowed,
3589         .get_nmi_mask = svm_get_nmi_mask,
3590         .set_nmi_mask = svm_set_nmi_mask,
3591         .enable_nmi_window = enable_nmi_window,
3592         .enable_irq_window = enable_irq_window,
3593         .update_cr8_intercept = update_cr8_intercept,
3594
3595         .set_tss_addr = svm_set_tss_addr,
3596         .get_tdp_level = get_npt_level,
3597         .get_mt_mask = svm_get_mt_mask,
3598
3599         .exit_reasons_str = svm_exit_reasons_str,
3600         .get_lpage_level = svm_get_lpage_level,
3601
3602         .cpuid_update = svm_cpuid_update,
3603
3604         .rdtscp_supported = svm_rdtscp_supported,
3605
3606         .set_supported_cpuid = svm_set_supported_cpuid,
3607
3608         .has_wbinvd_exit = svm_has_wbinvd_exit,
3609
3610         .write_tsc_offset = svm_write_tsc_offset,
3611         .adjust_tsc_offset = svm_adjust_tsc_offset,
3612
3613         .set_tdp_cr3 = set_tdp_cr3,
3614 };
3615
3616 static int __init svm_init(void)
3617 {
3618         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3619                         __alignof__(struct vcpu_svm), THIS_MODULE);
3620 }
3621
3622 static void __exit svm_exit(void)
3623 {
3624         kvm_exit();
3625 }
3626
3627 module_init(svm_init)
3628 module_exit(svm_exit)