arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   8  *
   9  * Authors:
  10  *   Yaniv Kamay  <yaniv@qumranet.com>
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17 #include <linux/kvm_host.h>
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "kvm_cache_regs.h"
  22 #include "x86.h"
  23 #include "cpuid.h"
  24
  25 #include <linux/module.h>
  26 #include <linux/mod_devicetable.h>
  27 #include <linux/kernel.h>
  28 #include <linux/vmalloc.h>
  29 #include <linux/highmem.h>
  30 #include <linux/sched.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33
  34 #include <asm/perf_event.h>
  35 #include <asm/tlbflush.h>
  36 #include <asm/desc.h>
  37 #include <asm/kvm_para.h>
  38
  39 #include <asm/virtext.h>
  40 #include "trace.h"
  41
  42 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  43
  44 MODULE_AUTHOR("Qumranet");
  45 MODULE_LICENSE("GPL");
  46
  47 static const struct x86_cpu_id svm_cpu_id[] = {
  48         X86_FEATURE_MATCH(X86_FEATURE_SVM),
  49         {}
  50 };
  51 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  52
  53 #define IOPM_ALLOC_ORDER 2
  54 #define MSRPM_ALLOC_ORDER 1
  55
  56 #define SEG_TYPE_LDT 2
  57 #define SEG_TYPE_BUSY_TSS16 3
  58
  59 #define SVM_FEATURE_NPT            (1 <<  0)
  60 #define SVM_FEATURE_LBRV           (1 <<  1)
  61 #define SVM_FEATURE_SVML           (1 <<  2)
  62 #define SVM_FEATURE_NRIP           (1 <<  3)
  63 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  64 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  65 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  66 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  67 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  68
  69 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  70 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  71 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  72
  73 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  74
  75 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  76 #define TSC_RATIO_MIN           0x0000000000000001ULL
  77 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  78
  79 static bool erratum_383_found __read_mostly;
  80
  81 static const u32 host_save_user_msrs[] = {
  82 #ifdef CONFIG_X86_64
  83         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  84         MSR_FS_BASE,
  85 #endif
  86         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  87 };
  88
  89 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  90
  91 struct kvm_vcpu;
  92
  93 struct nested_state {
  94         struct vmcb *hsave;
  95         u64 hsave_msr;
  96         u64 vm_cr_msr;
  97         u64 vmcb;
  98
  99         /* These are the merged vectors */
 100         u32 *msrpm;
 101
 102         /* gpa pointers to the real vectors */
 103         u64 vmcb_msrpm;
 104         u64 vmcb_iopm;
 105
 106         /* A VMEXIT is required but not yet emulated */
 107         bool exit_required;
 108
 109         /* cache for intercepts of the guest */
 110         u32 intercept_cr;
 111         u32 intercept_dr;
 112         u32 intercept_exceptions;
 113         u64 intercept;
 114
 115         /* Nested Paging related state */
 116         u64 nested_cr3;
 117 };
 118
 119 #define MSRPM_OFFSETS   16
 120 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 121
 122 /*
 123  * Set osvw_len to higher value when updated Revision Guides
 124  * are published and we know what the new status bits are
 125  */
 126 static uint64_t osvw_len = 4, osvw_status;
 127
 128 struct vcpu_svm {
 129         struct kvm_vcpu vcpu;
 130         struct vmcb *vmcb;
 131         unsigned long vmcb_pa;
 132         struct svm_cpu_data *svm_data;
 133         uint64_t asid_generation;
 134         uint64_t sysenter_esp;
 135         uint64_t sysenter_eip;
 136
 137         u64 next_rip;
 138
 139         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 140         struct {
 141                 u16 fs;
 142                 u16 gs;
 143                 u16 ldt;
 144                 u64 gs_base;
 145         } host;
 146
 147         u32 *msrpm;
 148
 149         ulong nmi_iret_rip;
 150
 151         struct nested_state nested;
 152
 153         bool nmi_singlestep;
 154
 155         unsigned int3_injected;
 156         unsigned long int3_rip;
 157         u32 apf_reason;
 158
 159         u64  tsc_ratio;
 160 };
 161
 162 static DEFINE_PER_CPU(u64, current_tsc_ratio);
 163 #define TSC_RATIO_DEFAULT       0x0100000000ULL
 164
 165 #define MSR_INVALID                     0xffffffffU
 166
 167 static const struct svm_direct_access_msrs {
 168         u32 index;   /* Index of the MSR */
 169         bool always; /* True if intercept is always on */
 170 } direct_access_msrs[] = {
 171         { .index = MSR_STAR,                            .always = true  },
 172         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 173 #ifdef CONFIG_X86_64
 174         { .index = MSR_GS_BASE,                         .always = true  },
 175         { .index = MSR_FS_BASE,                         .always = true  },
 176         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 177         { .index = MSR_LSTAR,                           .always = true  },
 178         { .index = MSR_CSTAR,                           .always = true  },
 179         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 180 #endif
 181         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 182         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 183         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 184         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 185         { .index = MSR_INVALID,                         .always = false },
 186 };
 187
 188 /* enable NPT for AMD64 and X86 with PAE */
 189 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 190 static bool npt_enabled = true;
 191 #else
 192 static bool npt_enabled;
 193 #endif
 194
 195 /* allow nested paging (virtualized MMU) for all guests */
 196 static int npt = true;
 197 module_param(npt, int, S_IRUGO);
 198
 199 /* allow nested virtualization in KVM/SVM */
 200 static int nested = true;
 201 module_param(nested, int, S_IRUGO);
 202
 203 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 204 static void svm_complete_interrupts(struct vcpu_svm *svm);
 205
 206 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 207 static int nested_svm_intercept(struct vcpu_svm *svm);
 208 static int nested_svm_vmexit(struct vcpu_svm *svm);
 209 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 210                                       bool has_error_code, u32 error_code);
 211 static u64 __scale_tsc(u64 ratio, u64 tsc);
 212
 213 enum {
 214         VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
 215                             pause filter count */
 216         VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
 217         VMCB_ASID,       /* ASID */
 218         VMCB_INTR,       /* int_ctl, int_vector */
 219         VMCB_NPT,        /* npt_en, nCR3, gPAT */
 220         VMCB_CR,         /* CR0, CR3, CR4, EFER */
 221         VMCB_DR,         /* DR6, DR7 */
 222         VMCB_DT,         /* GDT, IDT */
 223         VMCB_SEG,        /* CS, DS, SS, ES, CPL */
 224         VMCB_CR2,        /* CR2 only */
 225         VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
 226         VMCB_DIRTY_MAX,
 227 };
 228
 229 /* TPR and CR2 are always written before VMRUN */
 230 #define VMCB_ALWAYS_DIRTY_MASK  ((1U << VMCB_INTR) | (1U << VMCB_CR2))
 231
 232 static inline void mark_all_dirty(struct vmcb *vmcb)
 233 {
 234         vmcb->control.clean = 0;
 235 }
 236
 237 static inline void mark_all_clean(struct vmcb *vmcb)
 238 {
 239         vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
 240                                & ~VMCB_ALWAYS_DIRTY_MASK;
 241 }
 242
 243 static inline void mark_dirty(struct vmcb *vmcb, int bit)
 244 {
 245         vmcb->control.clean &= ~(1 << bit);
 246 }
 247
 248 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 249 {
 250         return container_of(vcpu, struct vcpu_svm, vcpu);
 251 }
 252
 253 static void recalc_intercepts(struct vcpu_svm *svm)
 254 {
 255         struct vmcb_control_area *c, *h;
 256         struct nested_state *g;
 257
 258         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 259
 260         if (!is_guest_mode(&svm->vcpu))
 261                 return;
 262
 263         c = &svm->vmcb->control;
 264         h = &svm->nested.hsave->control;
 265         g = &svm->nested;
 266
 267         c->intercept_cr = h->intercept_cr | g->intercept_cr;
 268         c->intercept_dr = h->intercept_dr | g->intercept_dr;
 269         c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
 270         c->intercept = h->intercept | g->intercept;
 271 }
 272
 273 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
 274 {
 275         if (is_guest_mode(&svm->vcpu))
 276                 return svm->nested.hsave;
 277         else
 278                 return svm->vmcb;
 279 }
 280
 281 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
 282 {
 283         struct vmcb *vmcb = get_host_vmcb(svm);
 284
 285         vmcb->control.intercept_cr |= (1U << bit);
 286
 287         recalc_intercepts(svm);
 288 }
 289
 290 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
 291 {
 292         struct vmcb *vmcb = get_host_vmcb(svm);
 293
 294         vmcb->control.intercept_cr &= ~(1U << bit);
 295
 296         recalc_intercepts(svm);
 297 }
 298
 299 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
 300 {
 301         struct vmcb *vmcb = get_host_vmcb(svm);
 302
 303         return vmcb->control.intercept_cr & (1U << bit);
 304 }
 305
 306 static inline void set_dr_intercept(struct vcpu_svm *svm, int bit)
 307 {
 308         struct vmcb *vmcb = get_host_vmcb(svm);
 309
 310         vmcb->control.intercept_dr |= (1U << bit);
 311
 312         recalc_intercepts(svm);
 313 }
 314
 315 static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit)
 316 {
 317         struct vmcb *vmcb = get_host_vmcb(svm);
 318
 319         vmcb->control.intercept_dr &= ~(1U << bit);
 320
 321         recalc_intercepts(svm);
 322 }
 323
 324 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
 325 {
 326         struct vmcb *vmcb = get_host_vmcb(svm);
 327
 328         vmcb->control.intercept_exceptions |= (1U << bit);
 329
 330         recalc_intercepts(svm);
 331 }
 332
 333 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
 334 {
 335         struct vmcb *vmcb = get_host_vmcb(svm);
 336
 337         vmcb->control.intercept_exceptions &= ~(1U << bit);
 338
 339         recalc_intercepts(svm);
 340 }
 341
 342 static inline void set_intercept(struct vcpu_svm *svm, int bit)
 343 {
 344         struct vmcb *vmcb = get_host_vmcb(svm);
 345
 346         vmcb->control.intercept |= (1ULL << bit);
 347
 348         recalc_intercepts(svm);
 349 }
 350
 351 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
 352 {
 353         struct vmcb *vmcb = get_host_vmcb(svm);
 354
 355         vmcb->control.intercept &= ~(1ULL << bit);
 356
 357         recalc_intercepts(svm);
 358 }
 359
 360 static inline void enable_gif(struct vcpu_svm *svm)
 361 {
 362         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 363 }
 364
 365 static inline void disable_gif(struct vcpu_svm *svm)
 366 {
 367         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 368 }
 369
 370 static inline bool gif_set(struct vcpu_svm *svm)
 371 {
 372         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 373 }
 374
 375 static unsigned long iopm_base;
 376
 377 struct kvm_ldttss_desc {
 378         u16 limit0;
 379         u16 base0;
 380         unsigned base1:8, type:5, dpl:2, p:1;
 381         unsigned limit1:4, zero0:3, g:1, base2:8;
 382         u32 base3;
 383         u32 zero1;
 384 } __attribute__((packed));
 385
 386 struct svm_cpu_data {
 387         int cpu;
 388
 389         u64 asid_generation;
 390         u32 max_asid;
 391         u32 next_asid;
 392         struct kvm_ldttss_desc *tss_desc;
 393
 394         struct page *save_area;
 395 };
 396
 397 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 398
 399 struct svm_init_data {
 400         int cpu;
 401         int r;
 402 };
 403
 404 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 405
 406 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 407 #define MSRS_RANGE_SIZE 2048
 408 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 409
 410 static u32 svm_msrpm_offset(u32 msr)
 411 {
 412         u32 offset;
 413         int i;
 414
 415         for (i = 0; i < NUM_MSR_MAPS; i++) {
 416                 if (msr < msrpm_ranges[i] ||
 417                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 418                         continue;
 419
 420                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 421                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 422
 423                 /* Now we have the u8 offset - but need the u32 offset */
 424                 return offset / 4;
 425         }
 426
 427         /* MSR not in any range */
 428         return MSR_INVALID;
 429 }
 430
 431 #define MAX_INST_SIZE 15
 432
 433 static inline void clgi(void)
 434 {
 435         asm volatile (__ex(SVM_CLGI));
 436 }
 437
 438 static inline void stgi(void)
 439 {
 440         asm volatile (__ex(SVM_STGI));
 441 }
 442
 443 static inline void invlpga(unsigned long addr, u32 asid)
 444 {
 445         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
 446 }
 447
 448 static int get_npt_level(void)
 449 {
 450 #ifdef CONFIG_X86_64
 451         return PT64_ROOT_LEVEL;
 452 #else
 453         return PT32E_ROOT_LEVEL;
 454 #endif
 455 }
 456
 457 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 458 {
 459         vcpu->arch.efer = efer;
 460         if (!npt_enabled && !(efer & EFER_LMA))
 461                 efer &= ~EFER_LME;
 462
 463         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 464         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
 465 }
 466
 467 static int is_external_interrupt(u32 info)
 468 {
 469         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 470         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 471 }
 472
 473 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 474 {
 475         struct vcpu_svm *svm = to_svm(vcpu);
 476         u32 ret = 0;
 477
 478         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 479                 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 480         return ret & mask;
 481 }
 482
 483 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 484 {
 485         struct vcpu_svm *svm = to_svm(vcpu);
 486
 487         if (mask == 0)
 488                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 489         else
 490                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 491
 492 }
 493
 494 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 495 {
 496         struct vcpu_svm *svm = to_svm(vcpu);
 497
 498         if (svm->vmcb->control.next_rip != 0)
 499                 svm->next_rip = svm->vmcb->control.next_rip;
 500
 501         if (!svm->next_rip) {
 502                 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
 503                                 EMULATE_DONE)
 504                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 505                 return;
 506         }
 507         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 508                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 509                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 510
 511         kvm_rip_write(vcpu, svm->next_rip);
 512         svm_set_interrupt_shadow(vcpu, 0);
 513 }
 514
 515 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 516                                 bool has_error_code, u32 error_code,
 517                                 bool reinject)
 518 {
 519         struct vcpu_svm *svm = to_svm(vcpu);
 520
 521         /*
 522          * If we are within a nested VM we'd better #VMEXIT and let the guest
 523          * handle the exception
 524          */
 525         if (!reinject &&
 526             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 527                 return;
 528
 529         if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
 530                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 531
 532                 /*
 533                  * For guest debugging where we have to reinject #BP if some
 534                  * INT3 is guest-owned:
 535                  * Emulate nRIP by moving RIP forward. Will fail if injection
 536                  * raises a fault that is not intercepted. Still better than
 537                  * failing in all cases.
 538                  */
 539                 skip_emulated_instruction(&svm->vcpu);
 540                 rip = kvm_rip_read(&svm->vcpu);
 541                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 542                 svm->int3_injected = rip - old_rip;
 543         }
 544
 545         svm->vmcb->control.event_inj = nr
 546                 | SVM_EVTINJ_VALID
 547                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 548                 | SVM_EVTINJ_TYPE_EXEPT;
 549         svm->vmcb->control.event_inj_err = error_code;
 550 }
 551
 552 static void svm_init_erratum_383(void)
 553 {
 554         u32 low, high;
 555         int err;
 556         u64 val;
 557
 558         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 559                 return;
 560
 561         /* Use _safe variants to not break nested virtualization */
 562         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 563         if (err)
 564                 return;
 565
 566         val |= (1ULL << 47);
 567
 568         low  = lower_32_bits(val);
 569         high = upper_32_bits(val);
 570
 571         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 572
 573         erratum_383_found = true;
 574 }
 575
 576 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 577 {
 578         /*
 579          * Guests should see errata 400 and 415 as fixed (assuming that
 580          * HLT and IO instructions are intercepted).
 581          */
 582         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 583         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 584
 585         /*
 586          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 587          * all osvw.status bits inside that length, including bit 0 (which is
 588          * reserved for erratum 298), are valid. However, if host processor's
 589          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 590          * be conservative here and therefore we tell the guest that erratum 298
 591          * is present (because we really don't know).
 592          */
 593         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 594                 vcpu->arch.osvw.status |= 1;
 595 }
 596
 597 static int has_svm(void)
 598 {
 599         const char *msg;
 600
 601         if (!cpu_has_svm(&msg)) {
 602                 printk(KERN_INFO "has_svm: %s\n", msg);
 603                 return 0;
 604         }
 605
 606         return 1;
 607 }
 608
 609 static void svm_hardware_disable(void *garbage)
 610 {
 611         /* Make sure we clean up behind us */
 612         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 613                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 614
 615         cpu_svm_disable();
 616
 617         amd_pmu_disable_virt();
 618 }
 619
 620 static int svm_hardware_enable(void *garbage)
 621 {
 622
 623         struct svm_cpu_data *sd;
 624         uint64_t efer;
 625         struct desc_ptr gdt_descr;
 626         struct desc_struct *gdt;
 627         int me = raw_smp_processor_id();
 628
 629         rdmsrl(MSR_EFER, efer);
 630         if (efer & EFER_SVME)
 631                 return -EBUSY;
 632
 633         if (!has_svm()) {
 634                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 635                 return -EINVAL;
 636         }
 637         sd = per_cpu(svm_data, me);
 638         if (!sd) {
 639                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 640                 return -EINVAL;
 641         }
 642
 643         sd->asid_generation = 1;
 644         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 645         sd->next_asid = sd->max_asid + 1;
 646
 647         native_store_gdt(&gdt_descr);
 648         gdt = (struct desc_struct *)gdt_descr.address;
 649         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 650
 651         wrmsrl(MSR_EFER, efer | EFER_SVME);
 652
 653         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 654
 655         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 656                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 657                 __get_cpu_var(current_tsc_ratio) = TSC_RATIO_DEFAULT;
 658         }
 659
 660
 661         /*
 662          * Get OSVW bits.
 663          *
 664          * Note that it is possible to have a system with mixed processor
 665          * revisions and therefore different OSVW bits. If bits are not the same
 666          * on different processors then choose the worst case (i.e. if erratum
 667          * is present on one processor and not on another then assume that the
 668          * erratum is present everywhere).
 669          */
 670         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 671                 uint64_t len, status = 0;
 672                 int err;
 673
 674                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 675                 if (!err)
 676                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 677                                                       &err);
 678
 679                 if (err)
 680                         osvw_status = osvw_len = 0;
 681                 else {
 682                         if (len < osvw_len)
 683                                 osvw_len = len;
 684                         osvw_status |= status;
 685                         osvw_status &= (1ULL << osvw_len) - 1;
 686                 }
 687         } else
 688                 osvw_status = osvw_len = 0;
 689
 690         svm_init_erratum_383();
 691
 692         amd_pmu_enable_virt();
 693
 694         return 0;
 695 }
 696
 697 static void svm_cpu_uninit(int cpu)
 698 {
 699         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 700
 701         if (!sd)
 702                 return;
 703
 704         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 705         __free_page(sd->save_area);
 706         kfree(sd);
 707 }
 708
 709 static int svm_cpu_init(int cpu)
 710 {
 711         struct svm_cpu_data *sd;
 712         int r;
 713
 714         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 715         if (!sd)
 716                 return -ENOMEM;
 717         sd->cpu = cpu;
 718         sd->save_area = alloc_page(GFP_KERNEL);
 719         r = -ENOMEM;
 720         if (!sd->save_area)
 721                 goto err_1;
 722
 723         per_cpu(svm_data, cpu) = sd;
 724
 725         return 0;
 726
 727 err_1:
 728         kfree(sd);
 729         return r;
 730
 731 }
 732
 733 static bool valid_msr_intercept(u32 index)
 734 {
 735         int i;
 736
 737         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 738                 if (direct_access_msrs[i].index == index)
 739                         return true;
 740
 741         return false;
 742 }
 743
 744 static void set_msr_interception(u32 *msrpm, unsigned msr,
 745                                  int read, int write)
 746 {
 747         u8 bit_read, bit_write;
 748         unsigned long tmp;
 749         u32 offset;
 750
 751         /*
 752          * If this warning triggers extend the direct_access_msrs list at the
 753          * beginning of the file
 754          */
 755         WARN_ON(!valid_msr_intercept(msr));
 756
 757         offset    = svm_msrpm_offset(msr);
 758         bit_read  = 2 * (msr & 0x0f);
 759         bit_write = 2 * (msr & 0x0f) + 1;
 760         tmp       = msrpm[offset];
 761
 762         BUG_ON(offset == MSR_INVALID);
 763
 764         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 765         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 766
 767         msrpm[offset] = tmp;
 768 }
 769
 770 static void svm_vcpu_init_msrpm(u32 *msrpm)
 771 {
 772         int i;
 773
 774         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 775
 776         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 777                 if (!direct_access_msrs[i].always)
 778                         continue;
 779
 780                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
 781         }
 782 }
 783
 784 static void add_msr_offset(u32 offset)
 785 {
 786         int i;
 787
 788         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 789
 790                 /* Offset already in list? */
 791                 if (msrpm_offsets[i] == offset)
 792                         return;
 793
 794                 /* Slot used by another offset? */
 795                 if (msrpm_offsets[i] != MSR_INVALID)
 796                         continue;
 797
 798                 /* Add offset to list */
 799                 msrpm_offsets[i] = offset;
 800
 801                 return;
 802         }
 803
 804         /*
 805          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 806          * increase MSRPM_OFFSETS in this case.
 807          */
 808         BUG();
 809 }
 810
 811 static void init_msrpm_offsets(void)
 812 {
 813         int i;
 814
 815         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 816
 817         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 818                 u32 offset;
 819
 820                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 821                 BUG_ON(offset == MSR_INVALID);
 822
 823                 add_msr_offset(offset);
 824         }
 825 }
 826
 827 static void svm_enable_lbrv(struct vcpu_svm *svm)
 828 {
 829         u32 *msrpm = svm->msrpm;
 830
 831         svm->vmcb->control.lbr_ctl = 1;
 832         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 833         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 834         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 835         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 836 }
 837
 838 static void svm_disable_lbrv(struct vcpu_svm *svm)
 839 {
 840         u32 *msrpm = svm->msrpm;
 841
 842         svm->vmcb->control.lbr_ctl = 0;
 843         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 844         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 845         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 846         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 847 }
 848
 849 static __init int svm_hardware_setup(void)
 850 {
 851         int cpu;
 852         struct page *iopm_pages;
 853         void *iopm_va;
 854         int r;
 855
 856         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 857
 858         if (!iopm_pages)
 859                 return -ENOMEM;
 860
 861         iopm_va = page_address(iopm_pages);
 862         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 863         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 864
 865         init_msrpm_offsets();
 866
 867         if (boot_cpu_has(X86_FEATURE_NX))
 868                 kvm_enable_efer_bits(EFER_NX);
 869
 870         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 871                 kvm_enable_efer_bits(EFER_FFXSR);
 872
 873         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 874                 u64 max;
 875
 876                 kvm_has_tsc_control = true;
 877
 878                 /*
 879                  * Make sure the user can only configure tsc_khz values that
 880                  * fit into a signed integer.
 881                  * A min value is not calculated needed because it will always
 882                  * be 1 on all machines and a value of 0 is used to disable
 883                  * tsc-scaling for the vcpu.
 884                  */
 885                 max = min(0x7fffffffULL, __scale_tsc(tsc_khz, TSC_RATIO_MAX));
 886
 887                 kvm_max_guest_tsc_khz = max;
 888         }
 889
 890         if (nested) {
 891                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 892                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
 893         }
 894
 895         for_each_possible_cpu(cpu) {
 896                 r = svm_cpu_init(cpu);
 897                 if (r)
 898                         goto err;
 899         }
 900
 901         if (!boot_cpu_has(X86_FEATURE_NPT))
 902                 npt_enabled = false;
 903
 904         if (npt_enabled && !npt) {
 905                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 906                 npt_enabled = false;
 907         }
 908
 909         if (npt_enabled) {
 910                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 911                 kvm_enable_tdp();
 912         } else
 913                 kvm_disable_tdp();
 914
 915         return 0;
 916
 917 err:
 918         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 919         iopm_base = 0;
 920         return r;
 921 }
 922
 923 static __exit void svm_hardware_unsetup(void)
 924 {
 925         int cpu;
 926
 927         for_each_possible_cpu(cpu)
 928                 svm_cpu_uninit(cpu);
 929
 930         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 931         iopm_base = 0;
 932 }
 933
 934 static void init_seg(struct vmcb_seg *seg)
 935 {
 936         seg->selector = 0;
 937         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 938                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 939         seg->limit = 0xffff;
 940         seg->base = 0;
 941 }
 942
 943 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 944 {
 945         seg->selector = 0;
 946         seg->attrib = SVM_SELECTOR_P_MASK | type;
 947         seg->limit = 0xffff;
 948         seg->base = 0;
 949 }
 950
 951 static u64 __scale_tsc(u64 ratio, u64 tsc)
 952 {
 953         u64 mult, frac, _tsc;
 954
 955         mult  = ratio >> 32;
 956         frac  = ratio & ((1ULL << 32) - 1);
 957
 958         _tsc  = tsc;
 959         _tsc *= mult;
 960         _tsc += (tsc >> 32) * frac;
 961         _tsc += ((tsc & ((1ULL << 32) - 1)) * frac) >> 32;
 962
 963         return _tsc;
 964 }
 965
 966 static u64 svm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
 967 {
 968         struct vcpu_svm *svm = to_svm(vcpu);
 969         u64 _tsc = tsc;
 970
 971         if (svm->tsc_ratio != TSC_RATIO_DEFAULT)
 972                 _tsc = __scale_tsc(svm->tsc_ratio, tsc);
 973
 974         return _tsc;
 975 }
 976
 977 static void svm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
 978 {
 979         struct vcpu_svm *svm = to_svm(vcpu);
 980         u64 ratio;
 981         u64 khz;
 982
 983         /* Guest TSC same frequency as host TSC? */
 984         if (!scale) {
 985                 svm->tsc_ratio = TSC_RATIO_DEFAULT;
 986                 return;
 987         }
 988
 989         /* TSC scaling supported? */
 990         if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 991                 if (user_tsc_khz > tsc_khz) {
 992                         vcpu->arch.tsc_catchup = 1;
 993                         vcpu->arch.tsc_always_catchup = 1;
 994                 } else
 995                         WARN(1, "user requested TSC rate below hardware speed\n");
 996                 return;
 997         }
 998
 999         khz = user_tsc_khz;
1000
1001         /* TSC scaling required  - calculate ratio */
1002         ratio = khz << 32;
1003         do_div(ratio, tsc_khz);
1004
1005         if (ratio == 0 || ratio & TSC_RATIO_RSVD) {
1006                 WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n",
1007                                 user_tsc_khz);
1008                 return;
1009         }
1010         svm->tsc_ratio             = ratio;
1011 }
1012
1013 static u64 svm_read_tsc_offset(struct kvm_vcpu *vcpu)
1014 {
1015         struct vcpu_svm *svm = to_svm(vcpu);
1016
1017         return svm->vmcb->control.tsc_offset;
1018 }
1019
1020 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1021 {
1022         struct vcpu_svm *svm = to_svm(vcpu);
1023         u64 g_tsc_offset = 0;
1024
1025         if (is_guest_mode(vcpu)) {
1026                 g_tsc_offset = svm->vmcb->control.tsc_offset -
1027                                svm->nested.hsave->control.tsc_offset;
1028                 svm->nested.hsave->control.tsc_offset = offset;
1029         }
1030
1031         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1032
1033         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1034 }
1035
1036 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1037 {
1038         struct vcpu_svm *svm = to_svm(vcpu);
1039
1040         WARN_ON(adjustment < 0);
1041         if (host)
1042                 adjustment = svm_scale_tsc(vcpu, adjustment);
1043
1044         svm->vmcb->control.tsc_offset += adjustment;
1045         if (is_guest_mode(vcpu))
1046                 svm->nested.hsave->control.tsc_offset += adjustment;
1047         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1048 }
1049
1050 static u64 svm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1051 {
1052         u64 tsc;
1053
1054         tsc = svm_scale_tsc(vcpu, native_read_tsc());
1055
1056         return target_tsc - tsc;
1057 }
1058
1059 static void init_vmcb(struct vcpu_svm *svm)
1060 {
1061         struct vmcb_control_area *control = &svm->vmcb->control;
1062         struct vmcb_save_area *save = &svm->vmcb->save;
1063
1064         svm->vcpu.fpu_active = 1;
1065         svm->vcpu.arch.hflags = 0;
1066
1067         set_cr_intercept(svm, INTERCEPT_CR0_READ);
1068         set_cr_intercept(svm, INTERCEPT_CR3_READ);
1069         set_cr_intercept(svm, INTERCEPT_CR4_READ);
1070         set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1071         set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1072         set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1073         set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1074
1075         set_dr_intercept(svm, INTERCEPT_DR0_READ);
1076         set_dr_intercept(svm, INTERCEPT_DR1_READ);
1077         set_dr_intercept(svm, INTERCEPT_DR2_READ);
1078         set_dr_intercept(svm, INTERCEPT_DR3_READ);
1079         set_dr_intercept(svm, INTERCEPT_DR4_READ);
1080         set_dr_intercept(svm, INTERCEPT_DR5_READ);
1081         set_dr_intercept(svm, INTERCEPT_DR6_READ);
1082         set_dr_intercept(svm, INTERCEPT_DR7_READ);
1083
1084         set_dr_intercept(svm, INTERCEPT_DR0_WRITE);
1085         set_dr_intercept(svm, INTERCEPT_DR1_WRITE);
1086         set_dr_intercept(svm, INTERCEPT_DR2_WRITE);
1087         set_dr_intercept(svm, INTERCEPT_DR3_WRITE);
1088         set_dr_intercept(svm, INTERCEPT_DR4_WRITE);
1089         set_dr_intercept(svm, INTERCEPT_DR5_WRITE);
1090         set_dr_intercept(svm, INTERCEPT_DR6_WRITE);
1091         set_dr_intercept(svm, INTERCEPT_DR7_WRITE);
1092
1093         set_exception_intercept(svm, PF_VECTOR);
1094         set_exception_intercept(svm, UD_VECTOR);
1095         set_exception_intercept(svm, MC_VECTOR);
1096
1097         set_intercept(svm, INTERCEPT_INTR);
1098         set_intercept(svm, INTERCEPT_NMI);
1099         set_intercept(svm, INTERCEPT_SMI);
1100         set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1101         set_intercept(svm, INTERCEPT_RDPMC);
1102         set_intercept(svm, INTERCEPT_CPUID);
1103         set_intercept(svm, INTERCEPT_INVD);
1104         set_intercept(svm, INTERCEPT_HLT);
1105         set_intercept(svm, INTERCEPT_INVLPG);
1106         set_intercept(svm, INTERCEPT_INVLPGA);
1107         set_intercept(svm, INTERCEPT_IOIO_PROT);
1108         set_intercept(svm, INTERCEPT_MSR_PROT);
1109         set_intercept(svm, INTERCEPT_TASK_SWITCH);
1110         set_intercept(svm, INTERCEPT_SHUTDOWN);
1111         set_intercept(svm, INTERCEPT_VMRUN);
1112         set_intercept(svm, INTERCEPT_VMMCALL);
1113         set_intercept(svm, INTERCEPT_VMLOAD);
1114         set_intercept(svm, INTERCEPT_VMSAVE);
1115         set_intercept(svm, INTERCEPT_STGI);
1116         set_intercept(svm, INTERCEPT_CLGI);
1117         set_intercept(svm, INTERCEPT_SKINIT);
1118         set_intercept(svm, INTERCEPT_WBINVD);
1119         set_intercept(svm, INTERCEPT_MONITOR);
1120         set_intercept(svm, INTERCEPT_MWAIT);
1121         set_intercept(svm, INTERCEPT_XSETBV);
1122
1123         control->iopm_base_pa = iopm_base;
1124         control->msrpm_base_pa = __pa(svm->msrpm);
1125         control->int_ctl = V_INTR_MASKING_MASK;
1126
1127         init_seg(&save->es);
1128         init_seg(&save->ss);
1129         init_seg(&save->ds);
1130         init_seg(&save->fs);
1131         init_seg(&save->gs);
1132
1133         save->cs.selector = 0xf000;
1134         /* Executable/Readable Code Segment */
1135         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1136                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1137         save->cs.limit = 0xffff;
1138         /*
1139          * cs.base should really be 0xffff0000, but vmx can't handle that, so
1140          * be consistent with it.
1141          *
1142          * Replace when we have real mode working for vmx.
1143          */
1144         save->cs.base = 0xf0000;
1145
1146         save->gdtr.limit = 0xffff;
1147         save->idtr.limit = 0xffff;
1148
1149         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1150         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1151
1152         svm_set_efer(&svm->vcpu, 0);
1153         save->dr6 = 0xffff0ff0;
1154         kvm_set_rflags(&svm->vcpu, 2);
1155         save->rip = 0x0000fff0;
1156         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1157
1158         /*
1159          * This is the guest-visible cr0 value.
1160          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1161          */
1162         svm->vcpu.arch.cr0 = 0;
1163         (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1164
1165         save->cr4 = X86_CR4_PAE;
1166         /* rdx = ?? */
1167
1168         if (npt_enabled) {
1169                 /* Setup VMCB for Nested Paging */
1170                 control->nested_ctl = 1;
1171                 clr_intercept(svm, INTERCEPT_INVLPG);
1172                 clr_exception_intercept(svm, PF_VECTOR);
1173                 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1174                 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1175                 save->g_pat = 0x0007040600070406ULL;
1176                 save->cr3 = 0;
1177                 save->cr4 = 0;
1178         }
1179         svm->asid_generation = 0;
1180
1181         svm->nested.vmcb = 0;
1182         svm->vcpu.arch.hflags = 0;
1183
1184         if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1185                 control->pause_filter_count = 3000;
1186                 set_intercept(svm, INTERCEPT_PAUSE);
1187         }
1188
1189         mark_all_dirty(svm->vmcb);
1190
1191         enable_gif(svm);
1192 }
1193
1194 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
1195 {
1196         struct vcpu_svm *svm = to_svm(vcpu);
1197         u32 dummy;
1198         u32 eax = 1;
1199
1200         init_vmcb(svm);
1201
1202         if (!kvm_vcpu_is_bsp(vcpu)) {
1203                 kvm_rip_write(vcpu, 0);
1204                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
1205                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
1206         }
1207
1208         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy);
1209         kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1210
1211         return 0;
1212 }
1213
1214 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1215 {
1216         struct vcpu_svm *svm;
1217         struct page *page;
1218         struct page *msrpm_pages;
1219         struct page *hsave_page;
1220         struct page *nested_msrpm_pages;
1221         int err;
1222
1223         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1224         if (!svm) {
1225                 err = -ENOMEM;
1226                 goto out;
1227         }
1228
1229         svm->tsc_ratio = TSC_RATIO_DEFAULT;
1230
1231         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1232         if (err)
1233                 goto free_svm;
1234
1235         err = -ENOMEM;
1236         page = alloc_page(GFP_KERNEL);
1237         if (!page)
1238                 goto uninit;
1239
1240         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1241         if (!msrpm_pages)
1242                 goto free_page1;
1243
1244         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1245         if (!nested_msrpm_pages)
1246                 goto free_page2;
1247
1248         hsave_page = alloc_page(GFP_KERNEL);
1249         if (!hsave_page)
1250                 goto free_page3;
1251
1252         svm->nested.hsave = page_address(hsave_page);
1253
1254         svm->msrpm = page_address(msrpm_pages);
1255         svm_vcpu_init_msrpm(svm->msrpm);
1256
1257         svm->nested.msrpm = page_address(nested_msrpm_pages);
1258         svm_vcpu_init_msrpm(svm->nested.msrpm);
1259
1260         svm->vmcb = page_address(page);
1261         clear_page(svm->vmcb);
1262         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1263         svm->asid_generation = 0;
1264         init_vmcb(svm);
1265
1266         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1267         if (kvm_vcpu_is_bsp(&svm->vcpu))
1268                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1269
1270         svm_init_osvw(&svm->vcpu);
1271
1272         return &svm->vcpu;
1273
1274 free_page3:
1275         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1276 free_page2:
1277         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1278 free_page1:
1279         __free_page(page);
1280 uninit:
1281         kvm_vcpu_uninit(&svm->vcpu);
1282 free_svm:
1283         kmem_cache_free(kvm_vcpu_cache, svm);
1284 out:
1285         return ERR_PTR(err);
1286 }
1287
1288 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1289 {
1290         struct vcpu_svm *svm = to_svm(vcpu);
1291
1292         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1293         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1294         __free_page(virt_to_page(svm->nested.hsave));
1295         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1296         kvm_vcpu_uninit(vcpu);
1297         kmem_cache_free(kvm_vcpu_cache, svm);
1298 }
1299
1300 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1301 {
1302         struct vcpu_svm *svm = to_svm(vcpu);
1303         int i;
1304
1305         if (unlikely(cpu != vcpu->cpu)) {
1306                 svm->asid_generation = 0;
1307                 mark_all_dirty(svm->vmcb);
1308         }
1309
1310 #ifdef CONFIG_X86_64
1311         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1312 #endif
1313         savesegment(fs, svm->host.fs);
1314         savesegment(gs, svm->host.gs);
1315         svm->host.ldt = kvm_read_ldt();
1316
1317         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1318                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1319
1320         if (static_cpu_has(X86_FEATURE_TSCRATEMSR) &&
1321             svm->tsc_ratio != __get_cpu_var(current_tsc_ratio)) {
1322                 __get_cpu_var(current_tsc_ratio) = svm->tsc_ratio;
1323                 wrmsrl(MSR_AMD64_TSC_RATIO, svm->tsc_ratio);
1324         }
1325 }
1326
1327 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1328 {
1329         struct vcpu_svm *svm = to_svm(vcpu);
1330         int i;
1331
1332         ++vcpu->stat.host_state_reload;
1333         kvm_load_ldt(svm->host.ldt);
1334 #ifdef CONFIG_X86_64
1335         loadsegment(fs, svm->host.fs);
1336         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1337         load_gs_index(svm->host.gs);
1338 #else
1339 #ifdef CONFIG_X86_32_LAZY_GS
1340         loadsegment(gs, svm->host.gs);
1341 #endif
1342 #endif
1343         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1344                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1345 }
1346
1347 static void svm_update_cpl(struct kvm_vcpu *vcpu)
1348 {
1349         struct vcpu_svm *svm = to_svm(vcpu);
1350         int cpl;
1351
1352         if (!is_protmode(vcpu))
1353                 cpl = 0;
1354         else if (svm->vmcb->save.rflags & X86_EFLAGS_VM)
1355                 cpl = 3;
1356         else
1357                 cpl = svm->vmcb->save.cs.selector & 0x3;
1358
1359         svm->vmcb->save.cpl = cpl;
1360 }
1361
1362 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1363 {
1364         return to_svm(vcpu)->vmcb->save.rflags;
1365 }
1366
1367 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1368 {
1369         unsigned long old_rflags = to_svm(vcpu)->vmcb->save.rflags;
1370
1371         to_svm(vcpu)->vmcb->save.rflags = rflags;
1372         if ((old_rflags ^ rflags) & X86_EFLAGS_VM)
1373                 svm_update_cpl(vcpu);
1374 }
1375
1376 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1377 {
1378         switch (reg) {
1379         case VCPU_EXREG_PDPTR:
1380                 BUG_ON(!npt_enabled);
1381                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1382                 break;
1383         default:
1384                 BUG();
1385         }
1386 }
1387
1388 static void svm_set_vintr(struct vcpu_svm *svm)
1389 {
1390         set_intercept(svm, INTERCEPT_VINTR);
1391 }
1392
1393 static void svm_clear_vintr(struct vcpu_svm *svm)
1394 {
1395         clr_intercept(svm, INTERCEPT_VINTR);
1396 }
1397
1398 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1399 {
1400         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1401
1402         switch (seg) {
1403         case VCPU_SREG_CS: return &save->cs;
1404         case VCPU_SREG_DS: return &save->ds;
1405         case VCPU_SREG_ES: return &save->es;
1406         case VCPU_SREG_FS: return &save->fs;
1407         case VCPU_SREG_GS: return &save->gs;
1408         case VCPU_SREG_SS: return &save->ss;
1409         case VCPU_SREG_TR: return &save->tr;
1410         case VCPU_SREG_LDTR: return &save->ldtr;
1411         }
1412         BUG();
1413         return NULL;
1414 }
1415
1416 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1417 {
1418         struct vmcb_seg *s = svm_seg(vcpu, seg);
1419
1420         return s->base;
1421 }
1422
1423 static void svm_get_segment(struct kvm_vcpu *vcpu,
1424                             struct kvm_segment *var, int seg)
1425 {
1426         struct vmcb_seg *s = svm_seg(vcpu, seg);
1427
1428         var->base = s->base;
1429         var->limit = s->limit;
1430         var->selector = s->selector;
1431         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1432         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1433         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1434         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1435         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1436         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1437         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1438         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1439
1440         /*
1441          * AMD's VMCB does not have an explicit unusable field, so emulate it
1442          * for cross vendor migration purposes by "not present"
1443          */
1444         var->unusable = !var->present || (var->type == 0);
1445
1446         switch (seg) {
1447         case VCPU_SREG_CS:
1448                 /*
1449                  * SVM always stores 0 for the 'G' bit in the CS selector in
1450                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1451                  * Intel's VMENTRY has a check on the 'G' bit.
1452                  */
1453                 var->g = s->limit > 0xfffff;
1454                 break;
1455         case VCPU_SREG_TR:
1456                 /*
1457                  * Work around a bug where the busy flag in the tr selector
1458                  * isn't exposed
1459                  */
1460                 var->type |= 0x2;
1461                 break;
1462         case VCPU_SREG_DS:
1463         case VCPU_SREG_ES:
1464         case VCPU_SREG_FS:
1465         case VCPU_SREG_GS:
1466                 /*
1467                  * The accessed bit must always be set in the segment
1468                  * descriptor cache, although it can be cleared in the
1469                  * descriptor, the cached bit always remains at 1. Since
1470                  * Intel has a check on this, set it here to support
1471                  * cross-vendor migration.
1472                  */
1473                 if (!var->unusable)
1474                         var->type |= 0x1;
1475                 break;
1476         case VCPU_SREG_SS:
1477                 /*
1478                  * On AMD CPUs sometimes the DB bit in the segment
1479                  * descriptor is left as 1, although the whole segment has
1480                  * been made unusable. Clear it here to pass an Intel VMX
1481                  * entry check when cross vendor migrating.
1482                  */
1483                 if (var->unusable)
1484                         var->db = 0;
1485                 break;
1486         }
1487 }
1488
1489 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1490 {
1491         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1492
1493         return save->cpl;
1494 }
1495
1496 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1497 {
1498         struct vcpu_svm *svm = to_svm(vcpu);
1499
1500         dt->size = svm->vmcb->save.idtr.limit;
1501         dt->address = svm->vmcb->save.idtr.base;
1502 }
1503
1504 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1505 {
1506         struct vcpu_svm *svm = to_svm(vcpu);
1507
1508         svm->vmcb->save.idtr.limit = dt->size;
1509         svm->vmcb->save.idtr.base = dt->address ;
1510         mark_dirty(svm->vmcb, VMCB_DT);
1511 }
1512
1513 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1514 {
1515         struct vcpu_svm *svm = to_svm(vcpu);
1516
1517         dt->size = svm->vmcb->save.gdtr.limit;
1518         dt->address = svm->vmcb->save.gdtr.base;
1519 }
1520
1521 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1522 {
1523         struct vcpu_svm *svm = to_svm(vcpu);
1524
1525         svm->vmcb->save.gdtr.limit = dt->size;
1526         svm->vmcb->save.gdtr.base = dt->address ;
1527         mark_dirty(svm->vmcb, VMCB_DT);
1528 }
1529
1530 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1531 {
1532 }
1533
1534 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1535 {
1536 }
1537
1538 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1539 {
1540 }
1541
1542 static void update_cr0_intercept(struct vcpu_svm *svm)
1543 {
1544         ulong gcr0 = svm->vcpu.arch.cr0;
1545         u64 *hcr0 = &svm->vmcb->save.cr0;
1546
1547         if (!svm->vcpu.fpu_active)
1548                 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1549         else
1550                 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1551                         | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1552
1553         mark_dirty(svm->vmcb, VMCB_CR);
1554
1555         if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1556                 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1557                 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1558         } else {
1559                 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1560                 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1561         }
1562 }
1563
1564 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1565 {
1566         struct vcpu_svm *svm = to_svm(vcpu);
1567
1568 #ifdef CONFIG_X86_64
1569         if (vcpu->arch.efer & EFER_LME) {
1570                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1571                         vcpu->arch.efer |= EFER_LMA;
1572                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1573                 }
1574
1575                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1576                         vcpu->arch.efer &= ~EFER_LMA;
1577                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1578                 }
1579         }
1580 #endif
1581         vcpu->arch.cr0 = cr0;
1582
1583         if (!npt_enabled)
1584                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1585
1586         if (!vcpu->fpu_active)
1587                 cr0 |= X86_CR0_TS;
1588         /*
1589          * re-enable caching here because the QEMU bios
1590          * does not do it - this results in some delay at
1591          * reboot
1592          */
1593         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1594         svm->vmcb->save.cr0 = cr0;
1595         mark_dirty(svm->vmcb, VMCB_CR);
1596         update_cr0_intercept(svm);
1597 }
1598
1599 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1600 {
1601         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1602         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1603
1604         if (cr4 & X86_CR4_VMXE)
1605                 return 1;
1606
1607         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1608                 svm_flush_tlb(vcpu);
1609
1610         vcpu->arch.cr4 = cr4;
1611         if (!npt_enabled)
1612                 cr4 |= X86_CR4_PAE;
1613         cr4 |= host_cr4_mce;
1614         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1615         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1616         return 0;
1617 }
1618
1619 static void svm_set_segment(struct kvm_vcpu *vcpu,
1620                             struct kvm_segment *var, int seg)
1621 {
1622         struct vcpu_svm *svm = to_svm(vcpu);
1623         struct vmcb_seg *s = svm_seg(vcpu, seg);
1624
1625         s->base = var->base;
1626         s->limit = var->limit;
1627         s->selector = var->selector;
1628         if (var->unusable)
1629                 s->attrib = 0;
1630         else {
1631                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1632                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1633                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1634                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1635                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1636                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1637                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1638                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1639         }
1640         if (seg == VCPU_SREG_CS)
1641                 svm_update_cpl(vcpu);
1642
1643         mark_dirty(svm->vmcb, VMCB_SEG);
1644 }
1645
1646 static void update_db_bp_intercept(struct kvm_vcpu *vcpu)
1647 {
1648         struct vcpu_svm *svm = to_svm(vcpu);
1649
1650         clr_exception_intercept(svm, DB_VECTOR);
1651         clr_exception_intercept(svm, BP_VECTOR);
1652
1653         if (svm->nmi_singlestep)
1654                 set_exception_intercept(svm, DB_VECTOR);
1655
1656         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1657                 if (vcpu->guest_debug &
1658                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1659                         set_exception_intercept(svm, DB_VECTOR);
1660                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1661                         set_exception_intercept(svm, BP_VECTOR);
1662         } else
1663                 vcpu->guest_debug = 0;
1664 }
1665
1666 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1667 {
1668         if (sd->next_asid > sd->max_asid) {
1669                 ++sd->asid_generation;
1670                 sd->next_asid = 1;
1671                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1672         }
1673
1674         svm->asid_generation = sd->asid_generation;
1675         svm->vmcb->control.asid = sd->next_asid++;
1676
1677         mark_dirty(svm->vmcb, VMCB_ASID);
1678 }
1679
1680 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1681 {
1682         struct vcpu_svm *svm = to_svm(vcpu);
1683
1684         svm->vmcb->save.dr7 = value;
1685         mark_dirty(svm->vmcb, VMCB_DR);
1686 }
1687
1688 static int pf_interception(struct vcpu_svm *svm)
1689 {
1690         u64 fault_address = svm->vmcb->control.exit_info_2;
1691         u32 error_code;
1692         int r = 1;
1693
1694         switch (svm->apf_reason) {
1695         default:
1696                 error_code = svm->vmcb->control.exit_info_1;
1697
1698                 trace_kvm_page_fault(fault_address, error_code);
1699                 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1700                         kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1701                 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1702                         svm->vmcb->control.insn_bytes,
1703                         svm->vmcb->control.insn_len);
1704                 break;
1705         case KVM_PV_REASON_PAGE_NOT_PRESENT:
1706                 svm->apf_reason = 0;
1707                 local_irq_disable();
1708                 kvm_async_pf_task_wait(fault_address);
1709                 local_irq_enable();
1710                 break;
1711         case KVM_PV_REASON_PAGE_READY:
1712                 svm->apf_reason = 0;
1713                 local_irq_disable();
1714                 kvm_async_pf_task_wake(fault_address);
1715                 local_irq_enable();
1716                 break;
1717         }
1718         return r;
1719 }
1720
1721 static int db_interception(struct vcpu_svm *svm)
1722 {
1723         struct kvm_run *kvm_run = svm->vcpu.run;
1724
1725         if (!(svm->vcpu.guest_debug &
1726               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1727                 !svm->nmi_singlestep) {
1728                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1729                 return 1;
1730         }
1731
1732         if (svm->nmi_singlestep) {
1733                 svm->nmi_singlestep = false;
1734                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1735                         svm->vmcb->save.rflags &=
1736                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1737                 update_db_bp_intercept(&svm->vcpu);
1738         }
1739
1740         if (svm->vcpu.guest_debug &
1741             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1742                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1743                 kvm_run->debug.arch.pc =
1744                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1745                 kvm_run->debug.arch.exception = DB_VECTOR;
1746                 return 0;
1747         }
1748
1749         return 1;
1750 }
1751
1752 static int bp_interception(struct vcpu_svm *svm)
1753 {
1754         struct kvm_run *kvm_run = svm->vcpu.run;
1755
1756         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1757         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1758         kvm_run->debug.arch.exception = BP_VECTOR;
1759         return 0;
1760 }
1761
1762 static int ud_interception(struct vcpu_svm *svm)
1763 {
1764         int er;
1765
1766         er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
1767         if (er != EMULATE_DONE)
1768                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1769         return 1;
1770 }
1771
1772 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1773 {
1774         struct vcpu_svm *svm = to_svm(vcpu);
1775
1776         clr_exception_intercept(svm, NM_VECTOR);
1777
1778         svm->vcpu.fpu_active = 1;
1779         update_cr0_intercept(svm);
1780 }
1781
1782 static int nm_interception(struct vcpu_svm *svm)
1783 {
1784         svm_fpu_activate(&svm->vcpu);
1785         return 1;
1786 }
1787
1788 static bool is_erratum_383(void)
1789 {
1790         int err, i;
1791         u64 value;
1792
1793         if (!erratum_383_found)
1794                 return false;
1795
1796         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1797         if (err)
1798                 return false;
1799
1800         /* Bit 62 may or may not be set for this mce */
1801         value &= ~(1ULL << 62);
1802
1803         if (value != 0xb600000000010015ULL)
1804                 return false;
1805
1806         /* Clear MCi_STATUS registers */
1807         for (i = 0; i < 6; ++i)
1808                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1809
1810         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1811         if (!err) {
1812                 u32 low, high;
1813
1814                 value &= ~(1ULL << 2);
1815                 low    = lower_32_bits(value);
1816                 high   = upper_32_bits(value);
1817
1818                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1819         }
1820
1821         /* Flush tlb to evict multi-match entries */
1822         __flush_tlb_all();
1823
1824         return true;
1825 }
1826
1827 static void svm_handle_mce(struct vcpu_svm *svm)
1828 {
1829         if (is_erratum_383()) {
1830                 /*
1831                  * Erratum 383 triggered. Guest state is corrupt so kill the
1832                  * guest.
1833                  */
1834                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1835
1836                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1837
1838                 return;
1839         }
1840
1841         /*
1842          * On an #MC intercept the MCE handler is not called automatically in
1843          * the host. So do it by hand here.
1844          */
1845         asm volatile (
1846                 "int $0x12\n");
1847         /* not sure if we ever come back to this point */
1848
1849         return;
1850 }
1851
1852 static int mc_interception(struct vcpu_svm *svm)
1853 {
1854         return 1;
1855 }
1856
1857 static int shutdown_interception(struct vcpu_svm *svm)
1858 {
1859         struct kvm_run *kvm_run = svm->vcpu.run;
1860
1861         /*
1862          * VMCB is undefined after a SHUTDOWN intercept
1863          * so reinitialize it.
1864          */
1865         clear_page(svm->vmcb);
1866         init_vmcb(svm);
1867
1868         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1869         return 0;
1870 }
1871
1872 static int io_interception(struct vcpu_svm *svm)
1873 {
1874         struct kvm_vcpu *vcpu = &svm->vcpu;
1875         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1876         int size, in, string;
1877         unsigned port;
1878
1879         ++svm->vcpu.stat.io_exits;
1880         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1881         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1882         if (string || in)
1883                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
1884
1885         port = io_info >> 16;
1886         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1887         svm->next_rip = svm->vmcb->control.exit_info_2;
1888         skip_emulated_instruction(&svm->vcpu);
1889
1890         return kvm_fast_pio_out(vcpu, size, port);
1891 }
1892
1893 static int nmi_interception(struct vcpu_svm *svm)
1894 {
1895         return 1;
1896 }
1897
1898 static int intr_interception(struct vcpu_svm *svm)
1899 {
1900         ++svm->vcpu.stat.irq_exits;
1901         return 1;
1902 }
1903
1904 static int nop_on_interception(struct vcpu_svm *svm)
1905 {
1906         return 1;
1907 }
1908
1909 static int halt_interception(struct vcpu_svm *svm)
1910 {
1911         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1912         skip_emulated_instruction(&svm->vcpu);
1913         return kvm_emulate_halt(&svm->vcpu);
1914 }
1915
1916 static int vmmcall_interception(struct vcpu_svm *svm)
1917 {
1918         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1919         skip_emulated_instruction(&svm->vcpu);
1920         kvm_emulate_hypercall(&svm->vcpu);
1921         return 1;
1922 }
1923
1924 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1925 {
1926         struct vcpu_svm *svm = to_svm(vcpu);
1927
1928         return svm->nested.nested_cr3;
1929 }
1930
1931 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
1932 {
1933         struct vcpu_svm *svm = to_svm(vcpu);
1934         u64 cr3 = svm->nested.nested_cr3;
1935         u64 pdpte;
1936         int ret;
1937
1938         ret = kvm_read_guest_page(vcpu->kvm, gpa_to_gfn(cr3), &pdpte,
1939                                   offset_in_page(cr3) + index * 8, 8);
1940         if (ret)
1941                 return 0;
1942         return pdpte;
1943 }
1944
1945 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1946                                    unsigned long root)
1947 {
1948         struct vcpu_svm *svm = to_svm(vcpu);
1949
1950         svm->vmcb->control.nested_cr3 = root;
1951         mark_dirty(svm->vmcb, VMCB_NPT);
1952         svm_flush_tlb(vcpu);
1953 }
1954
1955 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1956                                        struct x86_exception *fault)
1957 {
1958         struct vcpu_svm *svm = to_svm(vcpu);
1959
1960         svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1961         svm->vmcb->control.exit_code_hi = 0;
1962         svm->vmcb->control.exit_info_1 = fault->error_code;
1963         svm->vmcb->control.exit_info_2 = fault->address;
1964
1965         nested_svm_vmexit(svm);
1966 }
1967
1968 static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1969 {
1970         int r;
1971
1972         r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1973
1974         vcpu->arch.mmu.set_cr3           = nested_svm_set_tdp_cr3;
1975         vcpu->arch.mmu.get_cr3           = nested_svm_get_tdp_cr3;
1976         vcpu->arch.mmu.get_pdptr         = nested_svm_get_tdp_pdptr;
1977         vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1978         vcpu->arch.mmu.shadow_root_level = get_npt_level();
1979         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
1980
1981         return r;
1982 }
1983
1984 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1985 {
1986         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1987 }
1988
1989 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1990 {
1991         if (!(svm->vcpu.arch.efer & EFER_SVME)
1992             || !is_paging(&svm->vcpu)) {
1993                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1994                 return 1;
1995         }
1996
1997         if (svm->vmcb->save.cpl) {
1998                 kvm_inject_gp(&svm->vcpu, 0);
1999                 return 1;
2000         }
2001
2002        return 0;
2003 }
2004
2005 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2006                                       bool has_error_code, u32 error_code)
2007 {
2008         int vmexit;
2009
2010         if (!is_guest_mode(&svm->vcpu))
2011                 return 0;
2012
2013         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2014         svm->vmcb->control.exit_code_hi = 0;
2015         svm->vmcb->control.exit_info_1 = error_code;
2016         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2017
2018         vmexit = nested_svm_intercept(svm);
2019         if (vmexit == NESTED_EXIT_DONE)
2020                 svm->nested.exit_required = true;
2021
2022         return vmexit;
2023 }
2024
2025 /* This function returns true if it is save to enable the irq window */
2026 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2027 {
2028         if (!is_guest_mode(&svm->vcpu))
2029                 return true;
2030
2031         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2032                 return true;
2033
2034         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2035                 return false;
2036
2037         /*
2038          * if vmexit was already requested (by intercepted exception
2039          * for instance) do not overwrite it with "external interrupt"
2040          * vmexit.
2041          */
2042         if (svm->nested.exit_required)
2043                 return false;
2044
2045         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
2046         svm->vmcb->control.exit_info_1 = 0;
2047         svm->vmcb->control.exit_info_2 = 0;
2048
2049         if (svm->nested.intercept & 1ULL) {
2050                 /*
2051                  * The #vmexit can't be emulated here directly because this
2052                  * code path runs with irqs and preemption disabled. A
2053                  * #vmexit emulation might sleep. Only signal request for
2054                  * the #vmexit here.
2055                  */
2056                 svm->nested.exit_required = true;
2057                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2058                 return false;
2059         }
2060
2061         return true;
2062 }
2063
2064 /* This function returns true if it is save to enable the nmi window */
2065 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2066 {
2067         if (!is_guest_mode(&svm->vcpu))
2068                 return true;
2069
2070         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2071                 return true;
2072
2073         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2074         svm->nested.exit_required = true;
2075
2076         return false;
2077 }
2078
2079 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2080 {
2081         struct page *page;
2082
2083         might_sleep();
2084
2085         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
2086         if (is_error_page(page))
2087                 goto error;
2088
2089         *_page = page;
2090
2091         return kmap(page);
2092
2093 error:
2094         kvm_inject_gp(&svm->vcpu, 0);
2095
2096         return NULL;
2097 }
2098
2099 static void nested_svm_unmap(struct page *page)
2100 {
2101         kunmap(page);
2102         kvm_release_page_dirty(page);
2103 }
2104
2105 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2106 {
2107         unsigned port;
2108         u8 val, bit;
2109         u64 gpa;
2110
2111         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2112                 return NESTED_EXIT_HOST;
2113
2114         port = svm->vmcb->control.exit_info_1 >> 16;
2115         gpa  = svm->nested.vmcb_iopm + (port / 8);
2116         bit  = port % 8;
2117         val  = 0;
2118
2119         if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
2120                 val &= (1 << bit);
2121
2122         return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2123 }
2124
2125 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2126 {
2127         u32 offset, msr, value;
2128         int write, mask;
2129
2130         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2131                 return NESTED_EXIT_HOST;
2132
2133         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2134         offset = svm_msrpm_offset(msr);
2135         write  = svm->vmcb->control.exit_info_1 & 1;
2136         mask   = 1 << ((2 * (msr & 0xf)) + write);
2137
2138         if (offset == MSR_INVALID)
2139                 return NESTED_EXIT_DONE;
2140
2141         /* Offset is in 32 bit units but need in 8 bit units */
2142         offset *= 4;
2143
2144         if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
2145                 return NESTED_EXIT_DONE;
2146
2147         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2148 }
2149
2150 static int nested_svm_exit_special(struct vcpu_svm *svm)
2151 {
2152         u32 exit_code = svm->vmcb->control.exit_code;
2153
2154         switch (exit_code) {
2155         case SVM_EXIT_INTR:
2156         case SVM_EXIT_NMI:
2157         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2158                 return NESTED_EXIT_HOST;
2159         case SVM_EXIT_NPF:
2160                 /* For now we are always handling NPFs when using them */
2161                 if (npt_enabled)
2162                         return NESTED_EXIT_HOST;
2163                 break;
2164         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2165                 /* When we're shadowing, trap PFs, but not async PF */
2166                 if (!npt_enabled && svm->apf_reason == 0)
2167                         return NESTED_EXIT_HOST;
2168                 break;
2169         case SVM_EXIT_EXCP_BASE + NM_VECTOR:
2170                 nm_interception(svm);
2171                 break;
2172         default:
2173                 break;
2174         }
2175
2176         return NESTED_EXIT_CONTINUE;
2177 }
2178
2179 /*
2180  * If this function returns true, this #vmexit was already handled
2181  */
2182 static int nested_svm_intercept(struct vcpu_svm *svm)
2183 {
2184         u32 exit_code = svm->vmcb->control.exit_code;
2185         int vmexit = NESTED_EXIT_HOST;
2186
2187         switch (exit_code) {
2188         case SVM_EXIT_MSR:
2189                 vmexit = nested_svm_exit_handled_msr(svm);
2190                 break;
2191         case SVM_EXIT_IOIO:
2192                 vmexit = nested_svm_intercept_ioio(svm);
2193                 break;
2194         case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2195                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2196                 if (svm->nested.intercept_cr & bit)
2197                         vmexit = NESTED_EXIT_DONE;
2198                 break;
2199         }
2200         case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2201                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2202                 if (svm->nested.intercept_dr & bit)
2203                         vmexit = NESTED_EXIT_DONE;
2204                 break;
2205         }
2206         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2207                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2208                 if (svm->nested.intercept_exceptions & excp_bits)
2209                         vmexit = NESTED_EXIT_DONE;
2210                 /* async page fault always cause vmexit */
2211                 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2212                          svm->apf_reason != 0)
2213                         vmexit = NESTED_EXIT_DONE;
2214                 break;
2215         }
2216         case SVM_EXIT_ERR: {
2217                 vmexit = NESTED_EXIT_DONE;
2218                 break;
2219         }
2220         default: {
2221                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2222                 if (svm->nested.intercept & exit_bits)
2223                         vmexit = NESTED_EXIT_DONE;
2224         }
2225         }
2226
2227         return vmexit;
2228 }
2229
2230 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2231 {
2232         int vmexit;
2233
2234         vmexit = nested_svm_intercept(svm);
2235
2236         if (vmexit == NESTED_EXIT_DONE)
2237                 nested_svm_vmexit(svm);
2238
2239         return vmexit;
2240 }
2241
2242 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2243 {
2244         struct vmcb_control_area *dst  = &dst_vmcb->control;
2245         struct vmcb_control_area *from = &from_vmcb->control;
2246
2247         dst->intercept_cr         = from->intercept_cr;
2248         dst->intercept_dr         = from->intercept_dr;
2249         dst->intercept_exceptions = from->intercept_exceptions;
2250         dst->intercept            = from->intercept;
2251         dst->iopm_base_pa         = from->iopm_base_pa;
2252         dst->msrpm_base_pa        = from->msrpm_base_pa;
2253         dst->tsc_offset           = from->tsc_offset;
2254         dst->asid                 = from->asid;
2255         dst->tlb_ctl              = from->tlb_ctl;
2256         dst->int_ctl              = from->int_ctl;
2257         dst->int_vector           = from->int_vector;
2258         dst->int_state            = from->int_state;
2259         dst->exit_code            = from->exit_code;
2260         dst->exit_code_hi         = from->exit_code_hi;
2261         dst->exit_info_1          = from->exit_info_1;
2262         dst->exit_info_2          = from->exit_info_2;
2263         dst->exit_int_info        = from->exit_int_info;
2264         dst->exit_int_info_err    = from->exit_int_info_err;
2265         dst->nested_ctl           = from->nested_ctl;
2266         dst->event_inj            = from->event_inj;
2267         dst->event_inj_err        = from->event_inj_err;
2268         dst->nested_cr3           = from->nested_cr3;
2269         dst->lbr_ctl              = from->lbr_ctl;
2270 }
2271
2272 static int nested_svm_vmexit(struct vcpu_svm *svm)
2273 {
2274         struct vmcb *nested_vmcb;
2275         struct vmcb *hsave = svm->nested.hsave;
2276         struct vmcb *vmcb = svm->vmcb;
2277         struct page *page;
2278
2279         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2280                                        vmcb->control.exit_info_1,
2281                                        vmcb->control.exit_info_2,
2282                                        vmcb->control.exit_int_info,
2283                                        vmcb->control.exit_int_info_err,
2284                                        KVM_ISA_SVM);
2285
2286         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2287         if (!nested_vmcb)
2288                 return 1;
2289
2290         /* Exit Guest-Mode */
2291         leave_guest_mode(&svm->vcpu);
2292         svm->nested.vmcb = 0;
2293
2294         /* Give the current vmcb to the guest */
2295         disable_gif(svm);
2296
2297         nested_vmcb->save.es     = vmcb->save.es;
2298         nested_vmcb->save.cs     = vmcb->save.cs;
2299         nested_vmcb->save.ss     = vmcb->save.ss;
2300         nested_vmcb->save.ds     = vmcb->save.ds;
2301         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
2302         nested_vmcb->save.idtr   = vmcb->save.idtr;
2303         nested_vmcb->save.efer   = svm->vcpu.arch.efer;
2304         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
2305         nested_vmcb->save.cr3    = kvm_read_cr3(&svm->vcpu);
2306         nested_vmcb->save.cr2    = vmcb->save.cr2;
2307         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
2308         nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2309         nested_vmcb->save.rip    = vmcb->save.rip;
2310         nested_vmcb->save.rsp    = vmcb->save.rsp;
2311         nested_vmcb->save.rax    = vmcb->save.rax;
2312         nested_vmcb->save.dr7    = vmcb->save.dr7;
2313         nested_vmcb->save.dr6    = vmcb->save.dr6;
2314         nested_vmcb->save.cpl    = vmcb->save.cpl;
2315
2316         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
2317         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
2318         nested_vmcb->control.int_state         = vmcb->control.int_state;
2319         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
2320         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
2321         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
2322         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
2323         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
2324         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2325         nested_vmcb->control.next_rip          = vmcb->control.next_rip;
2326
2327         /*
2328          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2329          * to make sure that we do not lose injected events. So check event_inj
2330          * here and copy it to exit_int_info if it is valid.
2331          * Exit_int_info and event_inj can't be both valid because the case
2332          * below only happens on a VMRUN instruction intercept which has
2333          * no valid exit_int_info set.
2334          */
2335         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2336                 struct vmcb_control_area *nc = &nested_vmcb->control;
2337
2338                 nc->exit_int_info     = vmcb->control.event_inj;
2339                 nc->exit_int_info_err = vmcb->control.event_inj_err;
2340         }
2341
2342         nested_vmcb->control.tlb_ctl           = 0;
2343         nested_vmcb->control.event_inj         = 0;
2344         nested_vmcb->control.event_inj_err     = 0;
2345
2346         /* We always set V_INTR_MASKING and remember the old value in hflags */
2347         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2348                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2349
2350         /* Restore the original control entries */
2351         copy_vmcb_control_area(vmcb, hsave);
2352
2353         kvm_clear_exception_queue(&svm->vcpu);
2354         kvm_clear_interrupt_queue(&svm->vcpu);
2355
2356         svm->nested.nested_cr3 = 0;
2357
2358         /* Restore selected save entries */
2359         svm->vmcb->save.es = hsave->save.es;
2360         svm->vmcb->save.cs = hsave->save.cs;
2361         svm->vmcb->save.ss = hsave->save.ss;
2362         svm->vmcb->save.ds = hsave->save.ds;
2363         svm->vmcb->save.gdtr = hsave->save.gdtr;
2364         svm->vmcb->save.idtr = hsave->save.idtr;
2365         kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2366         svm_set_efer(&svm->vcpu, hsave->save.efer);
2367         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2368         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2369         if (npt_enabled) {
2370                 svm->vmcb->save.cr3 = hsave->save.cr3;
2371                 svm->vcpu.arch.cr3 = hsave->save.cr3;
2372         } else {
2373                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2374         }
2375         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2376         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2377         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2378         svm->vmcb->save.dr7 = 0;
2379         svm->vmcb->save.cpl = 0;
2380         svm->vmcb->control.exit_int_info = 0;
2381
2382         mark_all_dirty(svm->vmcb);
2383
2384         nested_svm_unmap(page);
2385
2386         nested_svm_uninit_mmu_context(&svm->vcpu);
2387         kvm_mmu_reset_context(&svm->vcpu);
2388         kvm_mmu_load(&svm->vcpu);
2389
2390         return 0;
2391 }
2392
2393 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2394 {
2395         /*
2396          * This function merges the msr permission bitmaps of kvm and the
2397          * nested vmcb. It is optimized in that it only merges the parts where
2398          * the kvm msr permission bitmap may contain zero bits
2399          */
2400         int i;
2401
2402         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2403                 return true;
2404
2405         for (i = 0; i < MSRPM_OFFSETS; i++) {
2406                 u32 value, p;
2407                 u64 offset;
2408
2409                 if (msrpm_offsets[i] == 0xffffffff)
2410                         break;
2411
2412                 p      = msrpm_offsets[i];
2413                 offset = svm->nested.vmcb_msrpm + (p * 4);
2414
2415                 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2416                         return false;
2417
2418                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2419         }
2420
2421         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2422
2423         return true;
2424 }
2425
2426 static bool nested_vmcb_checks(struct vmcb *vmcb)
2427 {
2428         if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2429                 return false;
2430
2431         if (vmcb->control.asid == 0)
2432                 return false;
2433
2434         if (vmcb->control.nested_ctl && !npt_enabled)
2435                 return false;
2436
2437         return true;
2438 }
2439
2440 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2441 {
2442         struct vmcb *nested_vmcb;
2443         struct vmcb *hsave = svm->nested.hsave;
2444         struct vmcb *vmcb = svm->vmcb;
2445         struct page *page;
2446         u64 vmcb_gpa;
2447
2448         vmcb_gpa = svm->vmcb->save.rax;
2449
2450         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2451         if (!nested_vmcb)
2452                 return false;
2453
2454         if (!nested_vmcb_checks(nested_vmcb)) {
2455                 nested_vmcb->control.exit_code    = SVM_EXIT_ERR;
2456                 nested_vmcb->control.exit_code_hi = 0;
2457                 nested_vmcb->control.exit_info_1  = 0;
2458                 nested_vmcb->control.exit_info_2  = 0;
2459
2460                 nested_svm_unmap(page);
2461
2462                 return false;
2463         }
2464
2465         trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2466                                nested_vmcb->save.rip,
2467                                nested_vmcb->control.int_ctl,
2468                                nested_vmcb->control.event_inj,
2469                                nested_vmcb->control.nested_ctl);
2470
2471         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2472                                     nested_vmcb->control.intercept_cr >> 16,
2473                                     nested_vmcb->control.intercept_exceptions,
2474                                     nested_vmcb->control.intercept);
2475
2476         /* Clear internal status */
2477         kvm_clear_exception_queue(&svm->vcpu);
2478         kvm_clear_interrupt_queue(&svm->vcpu);
2479
2480         /*
2481          * Save the old vmcb, so we don't need to pick what we save, but can
2482          * restore everything when a VMEXIT occurs
2483          */
2484         hsave->save.es     = vmcb->save.es;
2485         hsave->save.cs     = vmcb->save.cs;
2486         hsave->save.ss     = vmcb->save.ss;
2487         hsave->save.ds     = vmcb->save.ds;
2488         hsave->save.gdtr   = vmcb->save.gdtr;
2489         hsave->save.idtr   = vmcb->save.idtr;
2490         hsave->save.efer   = svm->vcpu.arch.efer;
2491         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
2492         hsave->save.cr4    = svm->vcpu.arch.cr4;
2493         hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2494         hsave->save.rip    = kvm_rip_read(&svm->vcpu);
2495         hsave->save.rsp    = vmcb->save.rsp;
2496         hsave->save.rax    = vmcb->save.rax;
2497         if (npt_enabled)
2498                 hsave->save.cr3    = vmcb->save.cr3;
2499         else
2500                 hsave->save.cr3    = kvm_read_cr3(&svm->vcpu);
2501
2502         copy_vmcb_control_area(hsave, vmcb);
2503
2504         if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2505                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2506         else
2507                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2508
2509         if (nested_vmcb->control.nested_ctl) {
2510                 kvm_mmu_unload(&svm->vcpu);
2511                 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2512                 nested_svm_init_mmu_context(&svm->vcpu);
2513         }
2514
2515         /* Load the nested guest state */
2516         svm->vmcb->save.es = nested_vmcb->save.es;
2517         svm->vmcb->save.cs = nested_vmcb->save.cs;
2518         svm->vmcb->save.ss = nested_vmcb->save.ss;
2519         svm->vmcb->save.ds = nested_vmcb->save.ds;
2520         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2521         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2522         kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2523         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2524         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2525         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2526         if (npt_enabled) {
2527                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2528                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2529         } else
2530                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2531
2532         /* Guest paging mode is active - reset mmu */
2533         kvm_mmu_reset_context(&svm->vcpu);
2534
2535         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2536         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2537         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2538         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2539
2540         /* In case we don't even reach vcpu_run, the fields are not updated */
2541         svm->vmcb->save.rax = nested_vmcb->save.rax;
2542         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2543         svm->vmcb->save.rip = nested_vmcb->save.rip;
2544         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2545         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2546         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2547
2548         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2549         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
2550
2551         /* cache intercepts */
2552         svm->nested.intercept_cr         = nested_vmcb->control.intercept_cr;
2553         svm->nested.intercept_dr         = nested_vmcb->control.intercept_dr;
2554         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2555         svm->nested.intercept            = nested_vmcb->control.intercept;
2556
2557         svm_flush_tlb(&svm->vcpu);
2558         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2559         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2560                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2561         else
2562                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2563
2564         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2565                 /* We only want the cr8 intercept bits of the guest */
2566                 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2567                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2568         }
2569
2570         /* We don't want to see VMMCALLs from a nested guest */
2571         clr_intercept(svm, INTERCEPT_VMMCALL);
2572
2573         svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2574         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2575         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2576         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2577         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2578         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2579
2580         nested_svm_unmap(page);
2581
2582         /* Enter Guest-Mode */
2583         enter_guest_mode(&svm->vcpu);
2584
2585         /*
2586          * Merge guest and host intercepts - must be called  with vcpu in
2587          * guest-mode to take affect here
2588          */
2589         recalc_intercepts(svm);
2590
2591         svm->nested.vmcb = vmcb_gpa;
2592
2593         enable_gif(svm);
2594
2595         mark_all_dirty(svm->vmcb);
2596
2597         return true;
2598 }
2599
2600 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2601 {
2602         to_vmcb->save.fs = from_vmcb->save.fs;
2603         to_vmcb->save.gs = from_vmcb->save.gs;
2604         to_vmcb->save.tr = from_vmcb->save.tr;
2605         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2606         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2607         to_vmcb->save.star = from_vmcb->save.star;
2608         to_vmcb->save.lstar = from_vmcb->save.lstar;
2609         to_vmcb->save.cstar = from_vmcb->save.cstar;
2610         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2611         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2612         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2613         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2614 }
2615
2616 static int vmload_interception(struct vcpu_svm *svm)
2617 {
2618         struct vmcb *nested_vmcb;
2619         struct page *page;
2620
2621         if (nested_svm_check_permissions(svm))
2622                 return 1;
2623
2624         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2625         if (!nested_vmcb)
2626                 return 1;
2627
2628         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2629         skip_emulated_instruction(&svm->vcpu);
2630
2631         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2632         nested_svm_unmap(page);
2633
2634         return 1;
2635 }
2636
2637 static int vmsave_interception(struct vcpu_svm *svm)
2638 {
2639         struct vmcb *nested_vmcb;
2640         struct page *page;
2641
2642         if (nested_svm_check_permissions(svm))
2643                 return 1;
2644
2645         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2646         if (!nested_vmcb)
2647                 return 1;
2648
2649         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2650         skip_emulated_instruction(&svm->vcpu);
2651
2652         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2653         nested_svm_unmap(page);
2654
2655         return 1;
2656 }
2657
2658 static int vmrun_interception(struct vcpu_svm *svm)
2659 {
2660         if (nested_svm_check_permissions(svm))
2661                 return 1;
2662
2663         /* Save rip after vmrun instruction */
2664         kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2665
2666         if (!nested_svm_vmrun(svm))
2667                 return 1;
2668
2669         if (!nested_svm_vmrun_msrpm(svm))
2670                 goto failed;
2671
2672         return 1;
2673
2674 failed:
2675
2676         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
2677         svm->vmcb->control.exit_code_hi = 0;
2678         svm->vmcb->control.exit_info_1  = 0;
2679         svm->vmcb->control.exit_info_2  = 0;
2680
2681         nested_svm_vmexit(svm);
2682
2683         return 1;
2684 }
2685
2686 static int stgi_interception(struct vcpu_svm *svm)
2687 {
2688         if (nested_svm_check_permissions(svm))
2689                 return 1;
2690
2691         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2692         skip_emulated_instruction(&svm->vcpu);
2693         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2694
2695         enable_gif(svm);
2696
2697         return 1;
2698 }
2699
2700 static int clgi_interception(struct vcpu_svm *svm)
2701 {
2702         if (nested_svm_check_permissions(svm))
2703                 return 1;
2704
2705         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2706         skip_emulated_instruction(&svm->vcpu);
2707
2708         disable_gif(svm);
2709
2710         /* After a CLGI no interrupts should come */
2711         svm_clear_vintr(svm);
2712         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2713
2714         mark_dirty(svm->vmcb, VMCB_INTR);
2715
2716         return 1;
2717 }
2718
2719 static int invlpga_interception(struct vcpu_svm *svm)
2720 {
2721         struct kvm_vcpu *vcpu = &svm->vcpu;
2722
2723         trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2724                           vcpu->arch.regs[VCPU_REGS_RAX]);
2725
2726         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2727         kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2728
2729         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2730         skip_emulated_instruction(&svm->vcpu);
2731         return 1;
2732 }
2733
2734 static int skinit_interception(struct vcpu_svm *svm)
2735 {
2736         trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2737
2738         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2739         return 1;
2740 }
2741
2742 static int xsetbv_interception(struct vcpu_svm *svm)
2743 {
2744         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2745         u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
2746
2747         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2748                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2749                 skip_emulated_instruction(&svm->vcpu);
2750         }
2751
2752         return 1;
2753 }
2754
2755 static int invalid_op_interception(struct vcpu_svm *svm)
2756 {
2757         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2758         return 1;
2759 }
2760
2761 static int task_switch_interception(struct vcpu_svm *svm)
2762 {
2763         u16 tss_selector;
2764         int reason;
2765         int int_type = svm->vmcb->control.exit_int_info &
2766                 SVM_EXITINTINFO_TYPE_MASK;
2767         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2768         uint32_t type =
2769                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2770         uint32_t idt_v =
2771                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2772         bool has_error_code = false;
2773         u32 error_code = 0;
2774
2775         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2776
2777         if (svm->vmcb->control.exit_info_2 &
2778             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2779                 reason = TASK_SWITCH_IRET;
2780         else if (svm->vmcb->control.exit_info_2 &
2781                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2782                 reason = TASK_SWITCH_JMP;
2783         else if (idt_v)
2784                 reason = TASK_SWITCH_GATE;
2785         else
2786                 reason = TASK_SWITCH_CALL;
2787
2788         if (reason == TASK_SWITCH_GATE) {
2789                 switch (type) {
2790                 case SVM_EXITINTINFO_TYPE_NMI:
2791                         svm->vcpu.arch.nmi_injected = false;
2792                         break;
2793                 case SVM_EXITINTINFO_TYPE_EXEPT:
2794                         if (svm->vmcb->control.exit_info_2 &
2795                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2796                                 has_error_code = true;
2797                                 error_code =
2798                                         (u32)svm->vmcb->control.exit_info_2;
2799                         }
2800                         kvm_clear_exception_queue(&svm->vcpu);
2801                         break;
2802                 case SVM_EXITINTINFO_TYPE_INTR:
2803                         kvm_clear_interrupt_queue(&svm->vcpu);
2804                         break;
2805                 default:
2806                         break;
2807                 }
2808         }
2809
2810         if (reason != TASK_SWITCH_GATE ||
2811             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2812             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2813              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2814                 skip_emulated_instruction(&svm->vcpu);
2815
2816         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2817                 int_vec = -1;
2818
2819         if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2820                                 has_error_code, error_code) == EMULATE_FAIL) {
2821                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2822                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2823                 svm->vcpu.run->internal.ndata = 0;
2824                 return 0;
2825         }
2826         return 1;
2827 }
2828
2829 static int cpuid_interception(struct vcpu_svm *svm)
2830 {
2831         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2832         kvm_emulate_cpuid(&svm->vcpu);
2833         return 1;
2834 }
2835
2836 static int iret_interception(struct vcpu_svm *svm)
2837 {
2838         ++svm->vcpu.stat.nmi_window_exits;
2839         clr_intercept(svm, INTERCEPT_IRET);
2840         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2841         svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2842         return 1;
2843 }
2844
2845 static int invlpg_interception(struct vcpu_svm *svm)
2846 {
2847         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2848                 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2849
2850         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2851         skip_emulated_instruction(&svm->vcpu);
2852         return 1;
2853 }
2854
2855 static int emulate_on_interception(struct vcpu_svm *svm)
2856 {
2857         return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2858 }
2859
2860 static int rdpmc_interception(struct vcpu_svm *svm)
2861 {
2862         int err;
2863
2864         if (!static_cpu_has(X86_FEATURE_NRIPS))
2865                 return emulate_on_interception(svm);
2866
2867         err = kvm_rdpmc(&svm->vcpu);
2868         kvm_complete_insn_gp(&svm->vcpu, err);
2869
2870         return 1;
2871 }
2872
2873 bool check_selective_cr0_intercepted(struct vcpu_svm *svm, unsigned long val)
2874 {
2875         unsigned long cr0 = svm->vcpu.arch.cr0;
2876         bool ret = false;
2877         u64 intercept;
2878
2879         intercept = svm->nested.intercept;
2880
2881         if (!is_guest_mode(&svm->vcpu) ||
2882             (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
2883                 return false;
2884
2885         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2886         val &= ~SVM_CR0_SELECTIVE_MASK;
2887
2888         if (cr0 ^ val) {
2889                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2890                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2891         }
2892
2893         return ret;
2894 }
2895
2896 #define CR_VALID (1ULL << 63)
2897
2898 static int cr_interception(struct vcpu_svm *svm)
2899 {
2900         int reg, cr;
2901         unsigned long val;
2902         int err;
2903
2904         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2905                 return emulate_on_interception(svm);
2906
2907         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2908                 return emulate_on_interception(svm);
2909
2910         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2911         cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2912
2913         err = 0;
2914         if (cr >= 16) { /* mov to cr */
2915                 cr -= 16;
2916                 val = kvm_register_read(&svm->vcpu, reg);
2917                 switch (cr) {
2918                 case 0:
2919                         if (!check_selective_cr0_intercepted(svm, val))
2920                                 err = kvm_set_cr0(&svm->vcpu, val);
2921                         else
2922                                 return 1;
2923
2924                         break;
2925                 case 3:
2926                         err = kvm_set_cr3(&svm->vcpu, val);
2927                         break;
2928                 case 4:
2929                         err = kvm_set_cr4(&svm->vcpu, val);
2930                         break;
2931                 case 8:
2932                         err = kvm_set_cr8(&svm->vcpu, val);
2933                         break;
2934                 default:
2935                         WARN(1, "unhandled write to CR%d", cr);
2936                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2937                         return 1;
2938                 }
2939         } else { /* mov from cr */
2940                 switch (cr) {
2941                 case 0:
2942                         val = kvm_read_cr0(&svm->vcpu);
2943                         break;
2944                 case 2:
2945                         val = svm->vcpu.arch.cr2;
2946                         break;
2947                 case 3:
2948                         val = kvm_read_cr3(&svm->vcpu);
2949                         break;
2950                 case 4:
2951                         val = kvm_read_cr4(&svm->vcpu);
2952                         break;
2953                 case 8:
2954                         val = kvm_get_cr8(&svm->vcpu);
2955                         break;
2956                 default:
2957                         WARN(1, "unhandled read from CR%d", cr);
2958                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2959                         return 1;
2960                 }
2961                 kvm_register_write(&svm->vcpu, reg, val);
2962         }
2963         kvm_complete_insn_gp(&svm->vcpu, err);
2964
2965         return 1;
2966 }
2967
2968 static int dr_interception(struct vcpu_svm *svm)
2969 {
2970         int reg, dr;
2971         unsigned long val;
2972         int err;
2973
2974         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2975                 return emulate_on_interception(svm);
2976
2977         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2978         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2979
2980         if (dr >= 16) { /* mov to DRn */
2981                 val = kvm_register_read(&svm->vcpu, reg);
2982                 kvm_set_dr(&svm->vcpu, dr - 16, val);
2983         } else {
2984                 err = kvm_get_dr(&svm->vcpu, dr, &val);
2985                 if (!err)
2986                         kvm_register_write(&svm->vcpu, reg, val);
2987         }
2988
2989         skip_emulated_instruction(&svm->vcpu);
2990
2991         return 1;
2992 }
2993
2994 static int cr8_write_interception(struct vcpu_svm *svm)
2995 {
2996         struct kvm_run *kvm_run = svm->vcpu.run;
2997         int r;
2998
2999         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
3000         /* instruction emulation calls kvm_set_cr8() */
3001         r = cr_interception(svm);
3002         if (irqchip_in_kernel(svm->vcpu.kvm)) {
3003                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3004                 return r;
3005         }
3006         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
3007                 return r;
3008         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
3009         return 0;
3010 }
3011
3012 u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
3013 {
3014         struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu));
3015         return vmcb->control.tsc_offset +
3016                 svm_scale_tsc(vcpu, host_tsc);
3017 }
3018
3019 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
3020 {
3021         struct vcpu_svm *svm = to_svm(vcpu);
3022
3023         switch (ecx) {
3024         case MSR_IA32_TSC: {
3025                 *data = svm->vmcb->control.tsc_offset +
3026                         svm_scale_tsc(vcpu, native_read_tsc());
3027
3028                 break;
3029         }
3030         case MSR_STAR:
3031                 *data = svm->vmcb->save.star;
3032                 break;
3033 #ifdef CONFIG_X86_64
3034         case MSR_LSTAR:
3035                 *data = svm->vmcb->save.lstar;
3036                 break;
3037         case MSR_CSTAR:
3038                 *data = svm->vmcb->save.cstar;
3039                 break;
3040         case MSR_KERNEL_GS_BASE:
3041                 *data = svm->vmcb->save.kernel_gs_base;
3042                 break;
3043         case MSR_SYSCALL_MASK:
3044                 *data = svm->vmcb->save.sfmask;
3045                 break;
3046 #endif
3047         case MSR_IA32_SYSENTER_CS:
3048                 *data = svm->vmcb->save.sysenter_cs;
3049                 break;
3050         case MSR_IA32_SYSENTER_EIP:
3051                 *data = svm->sysenter_eip;
3052                 break;
3053         case MSR_IA32_SYSENTER_ESP:
3054                 *data = svm->sysenter_esp;
3055                 break;
3056         /*
3057          * Nobody will change the following 5 values in the VMCB so we can
3058          * safely return them on rdmsr. They will always be 0 until LBRV is
3059          * implemented.
3060          */
3061         case MSR_IA32_DEBUGCTLMSR:
3062                 *data = svm->vmcb->save.dbgctl;
3063                 break;
3064         case MSR_IA32_LASTBRANCHFROMIP:
3065                 *data = svm->vmcb->save.br_from;
3066                 break;
3067         case MSR_IA32_LASTBRANCHTOIP:
3068                 *data = svm->vmcb->save.br_to;
3069                 break;
3070         case MSR_IA32_LASTINTFROMIP:
3071                 *data = svm->vmcb->save.last_excp_from;
3072                 break;
3073         case MSR_IA32_LASTINTTOIP:
3074                 *data = svm->vmcb->save.last_excp_to;
3075                 break;
3076         case MSR_VM_HSAVE_PA:
3077                 *data = svm->nested.hsave_msr;
3078                 break;
3079         case MSR_VM_CR:
3080                 *data = svm->nested.vm_cr_msr;
3081                 break;
3082         case MSR_IA32_UCODE_REV:
3083                 *data = 0x01000065;
3084                 break;
3085         default:
3086                 return kvm_get_msr_common(vcpu, ecx, data);
3087         }
3088         return 0;
3089 }
3090
3091 static int rdmsr_interception(struct vcpu_svm *svm)
3092 {
3093         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3094         u64 data;
3095
3096         if (svm_get_msr(&svm->vcpu, ecx, &data)) {
3097                 trace_kvm_msr_read_ex(ecx);
3098                 kvm_inject_gp(&svm->vcpu, 0);
3099         } else {
3100                 trace_kvm_msr_read(ecx, data);
3101
3102                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
3103                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
3104                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3105                 skip_emulated_instruction(&svm->vcpu);
3106         }
3107         return 1;
3108 }
3109
3110 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3111 {
3112         struct vcpu_svm *svm = to_svm(vcpu);
3113         int svm_dis, chg_mask;
3114
3115         if (data & ~SVM_VM_CR_VALID_MASK)
3116                 return 1;
3117
3118         chg_mask = SVM_VM_CR_VALID_MASK;
3119
3120         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3121                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3122
3123         svm->nested.vm_cr_msr &= ~chg_mask;
3124         svm->nested.vm_cr_msr |= (data & chg_mask);
3125
3126         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3127
3128         /* check for svm_disable while efer.svme is set */
3129         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3130                 return 1;
3131
3132         return 0;
3133 }
3134
3135 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3136 {
3137         struct vcpu_svm *svm = to_svm(vcpu);
3138
3139         u32 ecx = msr->index;
3140         u64 data = msr->data;
3141         switch (ecx) {
3142         case MSR_IA32_TSC:
3143                 kvm_write_tsc(vcpu, msr);
3144                 break;
3145         case MSR_STAR:
3146                 svm->vmcb->save.star = data;
3147                 break;
3148 #ifdef CONFIG_X86_64
3149         case MSR_LSTAR:
3150                 svm->vmcb->save.lstar = data;
3151                 break;
3152         case MSR_CSTAR:
3153                 svm->vmcb->save.cstar = data;
3154                 break;
3155         case MSR_KERNEL_GS_BASE:
3156                 svm->vmcb->save.kernel_gs_base = data;
3157                 break;
3158         case MSR_SYSCALL_MASK:
3159                 svm->vmcb->save.sfmask = data;
3160                 break;
3161 #endif
3162         case MSR_IA32_SYSENTER_CS:
3163                 svm->vmcb->save.sysenter_cs = data;
3164                 break;
3165         case MSR_IA32_SYSENTER_EIP:
3166                 svm->sysenter_eip = data;
3167                 svm->vmcb->save.sysenter_eip = data;
3168                 break;
3169         case MSR_IA32_SYSENTER_ESP:
3170                 svm->sysenter_esp = data;
3171                 svm->vmcb->save.sysenter_esp = data;
3172                 break;
3173         case MSR_IA32_DEBUGCTLMSR:
3174                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3175                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3176                                     __func__, data);
3177                         break;
3178                 }
3179                 if (data & DEBUGCTL_RESERVED_BITS)
3180                         return 1;
3181
3182                 svm->vmcb->save.dbgctl = data;
3183                 mark_dirty(svm->vmcb, VMCB_LBR);
3184                 if (data & (1ULL<<0))
3185                         svm_enable_lbrv(svm);
3186                 else
3187                         svm_disable_lbrv(svm);
3188                 break;
3189         case MSR_VM_HSAVE_PA:
3190                 svm->nested.hsave_msr = data;
3191                 break;
3192         case MSR_VM_CR:
3193                 return svm_set_vm_cr(vcpu, data);
3194         case MSR_VM_IGNNE:
3195                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3196                 break;
3197         default:
3198                 return kvm_set_msr_common(vcpu, msr);
3199         }
3200         return 0;
3201 }
3202
3203 static int wrmsr_interception(struct vcpu_svm *svm)
3204 {
3205         struct msr_data msr;
3206         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3207         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
3208                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3209
3210         msr.data = data;
3211         msr.index = ecx;
3212         msr.host_initiated = false;
3213
3214         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3215         if (svm_set_msr(&svm->vcpu, &msr)) {
3216                 trace_kvm_msr_write_ex(ecx, data);
3217                 kvm_inject_gp(&svm->vcpu, 0);
3218         } else {
3219                 trace_kvm_msr_write(ecx, data);
3220                 skip_emulated_instruction(&svm->vcpu);
3221         }
3222         return 1;
3223 }
3224
3225 static int msr_interception(struct vcpu_svm *svm)
3226 {
3227         if (svm->vmcb->control.exit_info_1)
3228                 return wrmsr_interception(svm);
3229         else
3230                 return rdmsr_interception(svm);
3231 }
3232
3233 static int interrupt_window_interception(struct vcpu_svm *svm)
3234 {
3235         struct kvm_run *kvm_run = svm->vcpu.run;
3236
3237         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3238         svm_clear_vintr(svm);
3239         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3240         mark_dirty(svm->vmcb, VMCB_INTR);
3241         ++svm->vcpu.stat.irq_window_exits;
3242         /*
3243          * If the user space waits to inject interrupts, exit as soon as
3244          * possible
3245          */
3246         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
3247             kvm_run->request_interrupt_window &&
3248             !kvm_cpu_has_interrupt(&svm->vcpu)) {
3249                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3250                 return 0;
3251         }
3252
3253         return 1;
3254 }
3255
3256 static int pause_interception(struct vcpu_svm *svm)
3257 {
3258         kvm_vcpu_on_spin(&(svm->vcpu));
3259         return 1;
3260 }
3261
3262 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
3263         [SVM_EXIT_READ_CR0]                     = cr_interception,
3264         [SVM_EXIT_READ_CR3]                     = cr_interception,
3265         [SVM_EXIT_READ_CR4]                     = cr_interception,
3266         [SVM_EXIT_READ_CR8]                     = cr_interception,
3267         [SVM_EXIT_CR0_SEL_WRITE]                = emulate_on_interception,
3268         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
3269         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
3270         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
3271         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
3272         [SVM_EXIT_READ_DR0]                     = dr_interception,
3273         [SVM_EXIT_READ_DR1]                     = dr_interception,
3274         [SVM_EXIT_READ_DR2]                     = dr_interception,
3275         [SVM_EXIT_READ_DR3]                     = dr_interception,
3276         [SVM_EXIT_READ_DR4]                     = dr_interception,
3277         [SVM_EXIT_READ_DR5]                     = dr_interception,
3278         [SVM_EXIT_READ_DR6]                     = dr_interception,
3279         [SVM_EXIT_READ_DR7]                     = dr_interception,
3280         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
3281         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
3282         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
3283         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
3284         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
3285         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
3286         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
3287         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
3288         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
3289         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
3290         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
3291         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
3292         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
3293         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
3294         [SVM_EXIT_INTR]                         = intr_interception,
3295         [SVM_EXIT_NMI]                          = nmi_interception,
3296         [SVM_EXIT_SMI]                          = nop_on_interception,
3297         [SVM_EXIT_INIT]                         = nop_on_interception,
3298         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
3299         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
3300         [SVM_EXIT_CPUID]                        = cpuid_interception,
3301         [SVM_EXIT_IRET]                         = iret_interception,
3302         [SVM_EXIT_INVD]                         = emulate_on_interception,
3303         [SVM_EXIT_PAUSE]                        = pause_interception,
3304         [SVM_EXIT_HLT]                          = halt_interception,
3305         [SVM_EXIT_INVLPG]                       = invlpg_interception,
3306         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
3307         [SVM_EXIT_IOIO]                         = io_interception,
3308         [SVM_EXIT_MSR]                          = msr_interception,
3309         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
3310         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
3311         [SVM_EXIT_VMRUN]                        = vmrun_interception,
3312         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
3313         [SVM_EXIT_VMLOAD]                       = vmload_interception,
3314         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
3315         [SVM_EXIT_STGI]                         = stgi_interception,
3316         [SVM_EXIT_CLGI]                         = clgi_interception,
3317         [SVM_EXIT_SKINIT]                       = skinit_interception,
3318         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
3319         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
3320         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
3321         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
3322         [SVM_EXIT_NPF]                          = pf_interception,
3323 };
3324
3325 static void dump_vmcb(struct kvm_vcpu *vcpu)
3326 {
3327         struct vcpu_svm *svm = to_svm(vcpu);
3328         struct vmcb_control_area *control = &svm->vmcb->control;
3329         struct vmcb_save_area *save = &svm->vmcb->save;
3330
3331         pr_err("VMCB Control Area:\n");
3332         pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
3333         pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
3334         pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
3335         pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
3336         pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
3337         pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
3338         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3339         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3340         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3341         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3342         pr_err("%-20s%d\n", "asid:", control->asid);
3343         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3344         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3345         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3346         pr_err("%-20s%08x\n", "int_state:", control->int_state);
3347         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3348         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3349         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3350         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3351         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3352         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3353         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3354         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3355         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3356         pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
3357         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3358         pr_err("VMCB State Save Area:\n");
3359         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3360                "es:",
3361                save->es.selector, save->es.attrib,
3362                save->es.limit, save->es.base);
3363         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3364                "cs:",
3365                save->cs.selector, save->cs.attrib,
3366                save->cs.limit, save->cs.base);
3367         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3368                "ss:",
3369                save->ss.selector, save->ss.attrib,
3370                save->ss.limit, save->ss.base);
3371         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3372                "ds:",
3373                save->ds.selector, save->ds.attrib,
3374                save->ds.limit, save->ds.base);
3375         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3376                "fs:",
3377                save->fs.selector, save->fs.attrib,
3378                save->fs.limit, save->fs.base);
3379         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3380                "gs:",
3381                save->gs.selector, save->gs.attrib,
3382                save->gs.limit, save->gs.base);
3383         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3384                "gdtr:",
3385                save->gdtr.selector, save->gdtr.attrib,
3386                save->gdtr.limit, save->gdtr.base);
3387         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3388                "ldtr:",
3389                save->ldtr.selector, save->ldtr.attrib,
3390                save->ldtr.limit, save->ldtr.base);
3391         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3392                "idtr:",
3393                save->idtr.selector, save->idtr.attrib,
3394                save->idtr.limit, save->idtr.base);
3395         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3396                "tr:",
3397                save->tr.selector, save->tr.attrib,
3398                save->tr.limit, save->tr.base);
3399         pr_err("cpl:            %d                efer:         %016llx\n",
3400                 save->cpl, save->efer);
3401         pr_err("%-15s %016llx %-13s %016llx\n",
3402                "cr0:", save->cr0, "cr2:", save->cr2);
3403         pr_err("%-15s %016llx %-13s %016llx\n",
3404                "cr3:", save->cr3, "cr4:", save->cr4);
3405         pr_err("%-15s %016llx %-13s %016llx\n",
3406                "dr6:", save->dr6, "dr7:", save->dr7);
3407         pr_err("%-15s %016llx %-13s %016llx\n",
3408                "rip:", save->rip, "rflags:", save->rflags);
3409         pr_err("%-15s %016llx %-13s %016llx\n",
3410                "rsp:", save->rsp, "rax:", save->rax);
3411         pr_err("%-15s %016llx %-13s %016llx\n",
3412                "star:", save->star, "lstar:", save->lstar);
3413         pr_err("%-15s %016llx %-13s %016llx\n",
3414                "cstar:", save->cstar, "sfmask:", save->sfmask);
3415         pr_err("%-15s %016llx %-13s %016llx\n",
3416                "kernel_gs_base:", save->kernel_gs_base,
3417                "sysenter_cs:", save->sysenter_cs);
3418         pr_err("%-15s %016llx %-13s %016llx\n",
3419                "sysenter_esp:", save->sysenter_esp,
3420                "sysenter_eip:", save->sysenter_eip);
3421         pr_err("%-15s %016llx %-13s %016llx\n",
3422                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3423         pr_err("%-15s %016llx %-13s %016llx\n",
3424                "br_from:", save->br_from, "br_to:", save->br_to);
3425         pr_err("%-15s %016llx %-13s %016llx\n",
3426                "excp_from:", save->last_excp_from,
3427                "excp_to:", save->last_excp_to);
3428 }
3429
3430 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3431 {
3432         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3433
3434         *info1 = control->exit_info_1;
3435         *info2 = control->exit_info_2;
3436 }
3437
3438 static int handle_exit(struct kvm_vcpu *vcpu)
3439 {
3440         struct vcpu_svm *svm = to_svm(vcpu);
3441         struct kvm_run *kvm_run = vcpu->run;
3442         u32 exit_code = svm->vmcb->control.exit_code;
3443
3444         if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3445                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3446         if (npt_enabled)
3447                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3448
3449         if (unlikely(svm->nested.exit_required)) {
3450                 nested_svm_vmexit(svm);
3451                 svm->nested.exit_required = false;
3452
3453                 return 1;
3454         }
3455
3456         if (is_guest_mode(vcpu)) {
3457                 int vmexit;
3458
3459                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3460                                         svm->vmcb->control.exit_info_1,
3461                                         svm->vmcb->control.exit_info_2,
3462                                         svm->vmcb->control.exit_int_info,
3463                                         svm->vmcb->control.exit_int_info_err,
3464                                         KVM_ISA_SVM);
3465
3466                 vmexit = nested_svm_exit_special(svm);
3467
3468                 if (vmexit == NESTED_EXIT_CONTINUE)
3469                         vmexit = nested_svm_exit_handled(svm);
3470
3471                 if (vmexit == NESTED_EXIT_DONE)
3472                         return 1;
3473         }
3474
3475         svm_complete_interrupts(svm);
3476
3477         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3478                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3479                 kvm_run->fail_entry.hardware_entry_failure_reason
3480                         = svm->vmcb->control.exit_code;
3481                 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3482                 dump_vmcb(vcpu);
3483                 return 0;
3484         }
3485
3486         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3487             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3488             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3489             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3490                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3491                        "exit_code 0x%x\n",
3492                        __func__, svm->vmcb->control.exit_int_info,
3493                        exit_code);
3494
3495         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3496             || !svm_exit_handlers[exit_code]) {
3497                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3498                 kvm_run->hw.hardware_exit_reason = exit_code;
3499                 return 0;
3500         }
3501
3502         return svm_exit_handlers[exit_code](svm);
3503 }
3504
3505 static void reload_tss(struct kvm_vcpu *vcpu)
3506 {
3507         int cpu = raw_smp_processor_id();
3508
3509         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3510         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3511         load_TR_desc();
3512 }
3513
3514 static void pre_svm_run(struct vcpu_svm *svm)
3515 {
3516         int cpu = raw_smp_processor_id();
3517
3518         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3519
3520         /* FIXME: handle wraparound of asid_generation */
3521         if (svm->asid_generation != sd->asid_generation)
3522                 new_asid(svm, sd);
3523 }
3524
3525 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3526 {
3527         struct vcpu_svm *svm = to_svm(vcpu);
3528
3529         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3530         vcpu->arch.hflags |= HF_NMI_MASK;
3531         set_intercept(svm, INTERCEPT_IRET);
3532         ++vcpu->stat.nmi_injections;
3533 }
3534
3535 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3536 {
3537         struct vmcb_control_area *control;
3538
3539         control = &svm->vmcb->control;
3540         control->int_vector = irq;
3541         control->int_ctl &= ~V_INTR_PRIO_MASK;
3542         control->int_ctl |= V_IRQ_MASK |
3543                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3544         mark_dirty(svm->vmcb, VMCB_INTR);
3545 }
3546
3547 static void svm_set_irq(struct kvm_vcpu *vcpu)
3548 {
3549         struct vcpu_svm *svm = to_svm(vcpu);
3550
3551         BUG_ON(!(gif_set(svm)));
3552
3553         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3554         ++vcpu->stat.irq_injections;
3555
3556         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3557                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3558 }
3559
3560 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3561 {
3562         struct vcpu_svm *svm = to_svm(vcpu);
3563
3564         if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3565                 return;
3566
3567         if (irr == -1)
3568                 return;
3569
3570         if (tpr >= irr)
3571                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3572 }
3573
3574 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
3575 {
3576         return;
3577 }
3578
3579 static int svm_vm_has_apicv(struct kvm *kvm)
3580 {
3581         return 0;
3582 }
3583
3584 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
3585 {
3586         return;
3587 }
3588
3589 static void svm_hwapic_isr_update(struct kvm *kvm, int isr)
3590 {
3591         return;
3592 }
3593
3594 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3595 {
3596         struct vcpu_svm *svm = to_svm(vcpu);
3597         struct vmcb *vmcb = svm->vmcb;
3598         int ret;
3599         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3600               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3601         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3602
3603         return ret;
3604 }
3605
3606 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3607 {
3608         struct vcpu_svm *svm = to_svm(vcpu);
3609
3610         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3611 }
3612
3613 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3614 {
3615         struct vcpu_svm *svm = to_svm(vcpu);
3616
3617         if (masked) {
3618                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3619                 set_intercept(svm, INTERCEPT_IRET);
3620         } else {
3621                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3622                 clr_intercept(svm, INTERCEPT_IRET);
3623         }
3624 }
3625
3626 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3627 {
3628         struct vcpu_svm *svm = to_svm(vcpu);
3629         struct vmcb *vmcb = svm->vmcb;
3630         int ret;
3631
3632         if (!gif_set(svm) ||
3633              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3634                 return 0;
3635
3636         ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
3637
3638         if (is_guest_mode(vcpu))
3639                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3640
3641         return ret;
3642 }
3643
3644 static void enable_irq_window(struct kvm_vcpu *vcpu)
3645 {
3646         struct vcpu_svm *svm = to_svm(vcpu);
3647
3648         /*
3649          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3650          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
3651          * get that intercept, this function will be called again though and
3652          * we'll get the vintr intercept.
3653          */
3654         if (gif_set(svm) && nested_svm_intr(svm)) {
3655                 svm_set_vintr(svm);
3656                 svm_inject_irq(svm, 0x0);
3657         }
3658 }
3659
3660 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3661 {
3662         struct vcpu_svm *svm = to_svm(vcpu);
3663
3664         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3665             == HF_NMI_MASK)
3666                 return; /* IRET will cause a vm exit */
3667
3668         /*
3669          * Something prevents NMI from been injected. Single step over possible
3670          * problem (IRET or exception injection or interrupt shadow)
3671          */
3672         svm->nmi_singlestep = true;
3673         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3674         update_db_bp_intercept(vcpu);
3675 }
3676
3677 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3678 {
3679         return 0;
3680 }
3681
3682 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3683 {
3684         struct vcpu_svm *svm = to_svm(vcpu);
3685
3686         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3687                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3688         else
3689                 svm->asid_generation--;
3690 }
3691
3692 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3693 {
3694 }
3695
3696 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3697 {
3698         struct vcpu_svm *svm = to_svm(vcpu);
3699
3700         if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3701                 return;
3702
3703         if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3704                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3705                 kvm_set_cr8(vcpu, cr8);
3706         }
3707 }
3708
3709 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3710 {
3711         struct vcpu_svm *svm = to_svm(vcpu);
3712         u64 cr8;
3713
3714         if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3715                 return;
3716
3717         cr8 = kvm_get_cr8(vcpu);
3718         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3719         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3720 }
3721
3722 static void svm_complete_interrupts(struct vcpu_svm *svm)
3723 {
3724         u8 vector;
3725         int type;
3726         u32 exitintinfo = svm->vmcb->control.exit_int_info;
3727         unsigned int3_injected = svm->int3_injected;
3728
3729         svm->int3_injected = 0;
3730
3731         /*
3732          * If we've made progress since setting HF_IRET_MASK, we've
3733          * executed an IRET and can allow NMI injection.
3734          */
3735         if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3736             && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3737                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3738                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3739         }
3740
3741         svm->vcpu.arch.nmi_injected = false;
3742         kvm_clear_exception_queue(&svm->vcpu);
3743         kvm_clear_interrupt_queue(&svm->vcpu);
3744
3745         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3746                 return;
3747
3748         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3749
3750         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3751         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3752
3753         switch (type) {
3754         case SVM_EXITINTINFO_TYPE_NMI:
3755                 svm->vcpu.arch.nmi_injected = true;
3756                 break;
3757         case SVM_EXITINTINFO_TYPE_EXEPT:
3758                 /*
3759                  * In case of software exceptions, do not reinject the vector,
3760                  * but re-execute the instruction instead. Rewind RIP first
3761                  * if we emulated INT3 before.
3762                  */
3763                 if (kvm_exception_is_soft(vector)) {
3764                         if (vector == BP_VECTOR && int3_injected &&
3765                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3766                                 kvm_rip_write(&svm->vcpu,
3767                                               kvm_rip_read(&svm->vcpu) -
3768                                               int3_injected);
3769                         break;
3770                 }
3771                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3772                         u32 err = svm->vmcb->control.exit_int_info_err;
3773                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
3774
3775                 } else
3776                         kvm_requeue_exception(&svm->vcpu, vector);
3777                 break;
3778         case SVM_EXITINTINFO_TYPE_INTR:
3779                 kvm_queue_interrupt(&svm->vcpu, vector, false);
3780                 break;
3781         default:
3782                 break;
3783         }
3784 }
3785
3786 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3787 {
3788         struct vcpu_svm *svm = to_svm(vcpu);
3789         struct vmcb_control_area *control = &svm->vmcb->control;
3790
3791         control->exit_int_info = control->event_inj;
3792         control->exit_int_info_err = control->event_inj_err;
3793         control->event_inj = 0;
3794         svm_complete_interrupts(svm);
3795 }
3796
3797 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3798 {
3799         struct vcpu_svm *svm = to_svm(vcpu);
3800
3801         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3802         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3803         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3804
3805         /*
3806          * A vmexit emulation is required before the vcpu can be executed
3807          * again.
3808          */
3809         if (unlikely(svm->nested.exit_required))
3810                 return;
3811
3812         pre_svm_run(svm);
3813
3814         sync_lapic_to_cr8(vcpu);
3815
3816         svm->vmcb->save.cr2 = vcpu->arch.cr2;
3817
3818         clgi();
3819
3820         local_irq_enable();
3821
3822         asm volatile (
3823                 "push %%" _ASM_BP "; \n\t"
3824                 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
3825                 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
3826                 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
3827                 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
3828                 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
3829                 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
3830 #ifdef CONFIG_X86_64
3831                 "mov %c[r8](%[svm]),  %%r8  \n\t"
3832                 "mov %c[r9](%[svm]),  %%r9  \n\t"
3833                 "mov %c[r10](%[svm]), %%r10 \n\t"
3834                 "mov %c[r11](%[svm]), %%r11 \n\t"
3835                 "mov %c[r12](%[svm]), %%r12 \n\t"
3836                 "mov %c[r13](%[svm]), %%r13 \n\t"
3837                 "mov %c[r14](%[svm]), %%r14 \n\t"
3838                 "mov %c[r15](%[svm]), %%r15 \n\t"
3839 #endif
3840
3841                 /* Enter guest mode */
3842                 "push %%" _ASM_AX " \n\t"
3843                 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
3844                 __ex(SVM_VMLOAD) "\n\t"
3845                 __ex(SVM_VMRUN) "\n\t"
3846                 __ex(SVM_VMSAVE) "\n\t"
3847                 "pop %%" _ASM_AX " \n\t"
3848
3849                 /* Save guest registers, load host registers */
3850                 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
3851                 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
3852                 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
3853                 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
3854                 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
3855                 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
3856 #ifdef CONFIG_X86_64
3857                 "mov %%r8,  %c[r8](%[svm]) \n\t"
3858                 "mov %%r9,  %c[r9](%[svm]) \n\t"
3859                 "mov %%r10, %c[r10](%[svm]) \n\t"
3860                 "mov %%r11, %c[r11](%[svm]) \n\t"
3861                 "mov %%r12, %c[r12](%[svm]) \n\t"
3862                 "mov %%r13, %c[r13](%[svm]) \n\t"
3863                 "mov %%r14, %c[r14](%[svm]) \n\t"
3864                 "mov %%r15, %c[r15](%[svm]) \n\t"
3865 #endif
3866                 "pop %%" _ASM_BP
3867                 :
3868                 : [svm]"a"(svm),
3869                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3870                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3871                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3872                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3873                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3874                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3875                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3876 #ifdef CONFIG_X86_64
3877                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3878                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3879                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3880                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3881                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3882                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3883                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3884                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3885 #endif
3886                 : "cc", "memory"
3887 #ifdef CONFIG_X86_64
3888                 , "rbx", "rcx", "rdx", "rsi", "rdi"
3889                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3890 #else
3891                 , "ebx", "ecx", "edx", "esi", "edi"
3892 #endif
3893                 );
3894
3895 #ifdef CONFIG_X86_64
3896         wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3897 #else
3898         loadsegment(fs, svm->host.fs);
3899 #ifndef CONFIG_X86_32_LAZY_GS
3900         loadsegment(gs, svm->host.gs);
3901 #endif
3902 #endif
3903
3904         reload_tss(vcpu);
3905
3906         local_irq_disable();
3907
3908         vcpu->arch.cr2 = svm->vmcb->save.cr2;
3909         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3910         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3911         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3912
3913         trace_kvm_exit(svm->vmcb->control.exit_code, vcpu, KVM_ISA_SVM);
3914
3915         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3916                 kvm_before_handle_nmi(&svm->vcpu);
3917
3918         stgi();
3919
3920         /* Any pending NMI will happen here */
3921
3922         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3923                 kvm_after_handle_nmi(&svm->vcpu);
3924
3925         sync_cr8_to_lapic(vcpu);
3926
3927         svm->next_rip = 0;
3928
3929         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3930
3931         /* if exit due to PF check for async PF */
3932         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3933                 svm->apf_reason = kvm_read_and_reset_pf_reason();
3934
3935         if (npt_enabled) {
3936                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3937                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3938         }
3939
3940         /*
3941          * We need to handle MC intercepts here before the vcpu has a chance to
3942          * change the physical cpu
3943          */
3944         if (unlikely(svm->vmcb->control.exit_code ==
3945                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
3946                 svm_handle_mce(svm);
3947
3948         mark_all_clean(svm->vmcb);
3949 }
3950
3951 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3952 {
3953         struct vcpu_svm *svm = to_svm(vcpu);
3954
3955         svm->vmcb->save.cr3 = root;
3956         mark_dirty(svm->vmcb, VMCB_CR);
3957         svm_flush_tlb(vcpu);
3958 }
3959
3960 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3961 {
3962         struct vcpu_svm *svm = to_svm(vcpu);
3963
3964         svm->vmcb->control.nested_cr3 = root;
3965         mark_dirty(svm->vmcb, VMCB_NPT);
3966
3967         /* Also sync guest cr3 here in case we live migrate */
3968         svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
3969         mark_dirty(svm->vmcb, VMCB_CR);
3970
3971         svm_flush_tlb(vcpu);
3972 }
3973
3974 static int is_disabled(void)
3975 {
3976         u64 vm_cr;
3977
3978         rdmsrl(MSR_VM_CR, vm_cr);
3979         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3980                 return 1;
3981
3982         return 0;
3983 }
3984
3985 static void
3986 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3987 {
3988         /*
3989          * Patch in the VMMCALL instruction:
3990          */
3991         hypercall[0] = 0x0f;
3992         hypercall[1] = 0x01;
3993         hypercall[2] = 0xd9;
3994 }
3995
3996 static void svm_check_processor_compat(void *rtn)
3997 {
3998         *(int *)rtn = 0;
3999 }
4000
4001 static bool svm_cpu_has_accelerated_tpr(void)
4002 {
4003         return false;
4004 }
4005
4006 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4007 {
4008         return 0;
4009 }
4010
4011 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
4012 {
4013 }
4014
4015 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4016 {
4017         switch (func) {
4018         case 0x80000001:
4019                 if (nested)
4020                         entry->ecx |= (1 << 2); /* Set SVM bit */
4021                 break;
4022         case 0x8000000A:
4023                 entry->eax = 1; /* SVM revision 1 */
4024                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
4025                                    ASID emulation to nested SVM */
4026                 entry->ecx = 0; /* Reserved */
4027                 entry->edx = 0; /* Per default do not support any
4028                                    additional features */
4029
4030                 /* Support next_rip if host supports it */
4031                 if (boot_cpu_has(X86_FEATURE_NRIPS))
4032                         entry->edx |= SVM_FEATURE_NRIP;
4033
4034                 /* Support NPT for the guest if enabled */
4035                 if (npt_enabled)
4036                         entry->edx |= SVM_FEATURE_NPT;
4037
4038                 break;
4039         }
4040 }
4041
4042 static int svm_get_lpage_level(void)
4043 {
4044         return PT_PDPE_LEVEL;
4045 }
4046
4047 static bool svm_rdtscp_supported(void)
4048 {
4049         return false;
4050 }
4051
4052 static bool svm_invpcid_supported(void)
4053 {
4054         return false;
4055 }
4056
4057 static bool svm_has_wbinvd_exit(void)
4058 {
4059         return true;
4060 }
4061
4062 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
4063 {
4064         struct vcpu_svm *svm = to_svm(vcpu);
4065
4066         set_exception_intercept(svm, NM_VECTOR);
4067         update_cr0_intercept(svm);
4068 }
4069
4070 #define PRE_EX(exit)  { .exit_code = (exit), \
4071                         .stage = X86_ICPT_PRE_EXCEPT, }
4072 #define POST_EX(exit) { .exit_code = (exit), \
4073                         .stage = X86_ICPT_POST_EXCEPT, }
4074 #define POST_MEM(exit) { .exit_code = (exit), \
4075                         .stage = X86_ICPT_POST_MEMACCESS, }
4076
4077 static const struct __x86_intercept {
4078         u32 exit_code;
4079         enum x86_intercept_stage stage;
4080 } x86_intercept_map[] = {
4081         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
4082         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
4083         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
4084         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
4085         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
4086         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
4087         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
4088         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
4089         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
4090         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
4091         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
4092         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
4093         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
4094         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
4095         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
4096         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
4097         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
4098         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
4099         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
4100         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
4101         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
4102         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
4103         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
4104         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
4105         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
4106         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
4107         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
4108         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
4109         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
4110         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
4111         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
4112         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
4113         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
4114         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
4115         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
4116         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
4117         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
4118         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
4119         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
4120         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
4121         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
4122         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
4123         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
4124         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
4125         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
4126         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
4127 };
4128
4129 #undef PRE_EX
4130 #undef POST_EX
4131 #undef POST_MEM
4132
4133 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4134                                struct x86_instruction_info *info,
4135                                enum x86_intercept_stage stage)
4136 {
4137         struct vcpu_svm *svm = to_svm(vcpu);
4138         int vmexit, ret = X86EMUL_CONTINUE;
4139         struct __x86_intercept icpt_info;
4140         struct vmcb *vmcb = svm->vmcb;
4141
4142         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4143                 goto out;
4144
4145         icpt_info = x86_intercept_map[info->intercept];
4146
4147         if (stage != icpt_info.stage)
4148                 goto out;
4149
4150         switch (icpt_info.exit_code) {
4151         case SVM_EXIT_READ_CR0:
4152                 if (info->intercept == x86_intercept_cr_read)
4153                         icpt_info.exit_code += info->modrm_reg;
4154                 break;
4155         case SVM_EXIT_WRITE_CR0: {
4156                 unsigned long cr0, val;
4157                 u64 intercept;
4158
4159                 if (info->intercept == x86_intercept_cr_write)
4160                         icpt_info.exit_code += info->modrm_reg;
4161
4162                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0)
4163                         break;
4164
4165                 intercept = svm->nested.intercept;
4166
4167                 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
4168                         break;
4169
4170                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4171                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
4172
4173                 if (info->intercept == x86_intercept_lmsw) {
4174                         cr0 &= 0xfUL;
4175                         val &= 0xfUL;
4176                         /* lmsw can't clear PE - catch this here */
4177                         if (cr0 & X86_CR0_PE)
4178                                 val |= X86_CR0_PE;
4179                 }
4180
4181                 if (cr0 ^ val)
4182                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4183
4184                 break;
4185         }
4186         case SVM_EXIT_READ_DR0:
4187         case SVM_EXIT_WRITE_DR0:
4188                 icpt_info.exit_code += info->modrm_reg;
4189                 break;
4190         case SVM_EXIT_MSR:
4191                 if (info->intercept == x86_intercept_wrmsr)
4192                         vmcb->control.exit_info_1 = 1;
4193                 else
4194                         vmcb->control.exit_info_1 = 0;
4195                 break;
4196         case SVM_EXIT_PAUSE:
4197                 /*
4198                  * We get this for NOP only, but pause
4199                  * is rep not, check this here
4200                  */
4201                 if (info->rep_prefix != REPE_PREFIX)
4202                         goto out;
4203         case SVM_EXIT_IOIO: {
4204                 u64 exit_info;
4205                 u32 bytes;
4206
4207                 exit_info = (vcpu->arch.regs[VCPU_REGS_RDX] & 0xffff) << 16;
4208
4209                 if (info->intercept == x86_intercept_in ||
4210                     info->intercept == x86_intercept_ins) {
4211                         exit_info |= SVM_IOIO_TYPE_MASK;
4212                         bytes = info->src_bytes;
4213                 } else {
4214                         bytes = info->dst_bytes;
4215                 }
4216
4217                 if (info->intercept == x86_intercept_outs ||
4218                     info->intercept == x86_intercept_ins)
4219                         exit_info |= SVM_IOIO_STR_MASK;
4220
4221                 if (info->rep_prefix)
4222                         exit_info |= SVM_IOIO_REP_MASK;
4223
4224                 bytes = min(bytes, 4u);
4225
4226                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4227
4228                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4229
4230                 vmcb->control.exit_info_1 = exit_info;
4231                 vmcb->control.exit_info_2 = info->next_rip;
4232
4233                 break;
4234         }
4235         default:
4236                 break;
4237         }
4238
4239         vmcb->control.next_rip  = info->next_rip;
4240         vmcb->control.exit_code = icpt_info.exit_code;
4241         vmexit = nested_svm_exit_handled(svm);
4242
4243         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4244                                            : X86EMUL_CONTINUE;
4245
4246 out:
4247         return ret;
4248 }
4249
4250 static struct kvm_x86_ops svm_x86_ops = {
4251         .cpu_has_kvm_support = has_svm,
4252         .disabled_by_bios = is_disabled,
4253         .hardware_setup = svm_hardware_setup,
4254         .hardware_unsetup = svm_hardware_unsetup,
4255         .check_processor_compatibility = svm_check_processor_compat,
4256         .hardware_enable = svm_hardware_enable,
4257         .hardware_disable = svm_hardware_disable,
4258         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4259
4260         .vcpu_create = svm_create_vcpu,
4261         .vcpu_free = svm_free_vcpu,
4262         .vcpu_reset = svm_vcpu_reset,
4263
4264         .prepare_guest_switch = svm_prepare_guest_switch,
4265         .vcpu_load = svm_vcpu_load,
4266         .vcpu_put = svm_vcpu_put,
4267
4268         .update_db_bp_intercept = update_db_bp_intercept,
4269         .get_msr = svm_get_msr,
4270         .set_msr = svm_set_msr,
4271         .get_segment_base = svm_get_segment_base,
4272         .get_segment = svm_get_segment,
4273         .set_segment = svm_set_segment,
4274         .get_cpl = svm_get_cpl,
4275         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4276         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
4277         .decache_cr3 = svm_decache_cr3,
4278         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
4279         .set_cr0 = svm_set_cr0,
4280         .set_cr3 = svm_set_cr3,
4281         .set_cr4 = svm_set_cr4,
4282         .set_efer = svm_set_efer,
4283         .get_idt = svm_get_idt,
4284         .set_idt = svm_set_idt,
4285         .get_gdt = svm_get_gdt,
4286         .set_gdt = svm_set_gdt,
4287         .set_dr7 = svm_set_dr7,
4288         .cache_reg = svm_cache_reg,
4289         .get_rflags = svm_get_rflags,
4290         .set_rflags = svm_set_rflags,
4291         .fpu_activate = svm_fpu_activate,
4292         .fpu_deactivate = svm_fpu_deactivate,
4293
4294         .tlb_flush = svm_flush_tlb,
4295
4296         .run = svm_vcpu_run,
4297         .handle_exit = handle_exit,
4298         .skip_emulated_instruction = skip_emulated_instruction,
4299         .set_interrupt_shadow = svm_set_interrupt_shadow,
4300         .get_interrupt_shadow = svm_get_interrupt_shadow,
4301         .patch_hypercall = svm_patch_hypercall,
4302         .set_irq = svm_set_irq,
4303         .set_nmi = svm_inject_nmi,
4304         .queue_exception = svm_queue_exception,
4305         .cancel_injection = svm_cancel_injection,
4306         .interrupt_allowed = svm_interrupt_allowed,
4307         .nmi_allowed = svm_nmi_allowed,
4308         .get_nmi_mask = svm_get_nmi_mask,
4309         .set_nmi_mask = svm_set_nmi_mask,
4310         .enable_nmi_window = enable_nmi_window,
4311         .enable_irq_window = enable_irq_window,
4312         .update_cr8_intercept = update_cr8_intercept,
4313         .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
4314         .vm_has_apicv = svm_vm_has_apicv,
4315         .load_eoi_exitmap = svm_load_eoi_exitmap,
4316         .hwapic_isr_update = svm_hwapic_isr_update,
4317
4318         .set_tss_addr = svm_set_tss_addr,
4319         .get_tdp_level = get_npt_level,
4320         .get_mt_mask = svm_get_mt_mask,
4321
4322         .get_exit_info = svm_get_exit_info,
4323
4324         .get_lpage_level = svm_get_lpage_level,
4325
4326         .cpuid_update = svm_cpuid_update,
4327
4328         .rdtscp_supported = svm_rdtscp_supported,
4329         .invpcid_supported = svm_invpcid_supported,
4330
4331         .set_supported_cpuid = svm_set_supported_cpuid,
4332
4333         .has_wbinvd_exit = svm_has_wbinvd_exit,
4334
4335         .set_tsc_khz = svm_set_tsc_khz,
4336         .read_tsc_offset = svm_read_tsc_offset,
4337         .write_tsc_offset = svm_write_tsc_offset,
4338         .adjust_tsc_offset = svm_adjust_tsc_offset,
4339         .compute_tsc_offset = svm_compute_tsc_offset,
4340         .read_l1_tsc = svm_read_l1_tsc,
4341
4342         .set_tdp_cr3 = set_tdp_cr3,
4343
4344         .check_intercept = svm_check_intercept,
4345 };
4346
4347 static int __init svm_init(void)
4348 {
4349         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
4350                         __alignof__(struct vcpu_svm), THIS_MODULE);
4351 }
4352
4353 static void __exit svm_exit(void)
4354 {
4355         kvm_exit();
4356 }
4357
4358 module_init(svm_init)
4359 module_exit(svm_exit)