arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   8  *
   9  * Authors:
  10  *   Yaniv Kamay  <yaniv@qumranet.com>
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17 #include <linux/kvm_host.h>
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "kvm_cache_regs.h"
  22 #include "x86.h"
  23
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/vmalloc.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/ftrace_event.h>
  30 #include <linux/slab.h>
  31
  32 #include <asm/tlbflush.h>
  33 #include <asm/desc.h>
  34 #include <asm/kvm_para.h>
  35
  36 #include <asm/virtext.h>
  37 #include "trace.h"
  38
  39 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  40
  41 MODULE_AUTHOR("Qumranet");
  42 MODULE_LICENSE("GPL");
  43
  44 #define IOPM_ALLOC_ORDER 2
  45 #define MSRPM_ALLOC_ORDER 1
  46
  47 #define SEG_TYPE_LDT 2
  48 #define SEG_TYPE_BUSY_TSS16 3
  49
  50 #define SVM_FEATURE_NPT            (1 <<  0)
  51 #define SVM_FEATURE_LBRV           (1 <<  1)
  52 #define SVM_FEATURE_SVML           (1 <<  2)
  53 #define SVM_FEATURE_NRIP           (1 <<  3)
  54 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  55 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  56 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  57 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  58 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  59
  60 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  61 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  62 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  63
  64 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  65
  66 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  67 #define TSC_RATIO_MIN           0x0000000000000001ULL
  68 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  69
  70 static bool erratum_383_found __read_mostly;
  71
  72 static const u32 host_save_user_msrs[] = {
  73 #ifdef CONFIG_X86_64
  74         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  75         MSR_FS_BASE,
  76 #endif
  77         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  78 };
  79
  80 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  81
  82 struct kvm_vcpu;
  83
  84 struct nested_state {
  85         struct vmcb *hsave;
  86         u64 hsave_msr;
  87         u64 vm_cr_msr;
  88         u64 vmcb;
  89
  90         /* These are the merged vectors */
  91         u32 *msrpm;
  92
  93         /* gpa pointers to the real vectors */
  94         u64 vmcb_msrpm;
  95         u64 vmcb_iopm;
  96
  97         /* A VMEXIT is required but not yet emulated */
  98         bool exit_required;
  99
 100         /* cache for intercepts of the guest */
 101         u32 intercept_cr;
 102         u32 intercept_dr;
 103         u32 intercept_exceptions;
 104         u64 intercept;
 105
 106         /* Nested Paging related state */
 107         u64 nested_cr3;
 108 };
 109
 110 #define MSRPM_OFFSETS   16
 111 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 112
 113 /*
 114  * Set osvw_len to higher value when updated Revision Guides
 115  * are published and we know what the new status bits are
 116  */
 117 static uint64_t osvw_len = 4, osvw_status;
 118
 119 struct vcpu_svm {
 120         struct kvm_vcpu vcpu;
 121         struct vmcb *vmcb;
 122         unsigned long vmcb_pa;
 123         struct svm_cpu_data *svm_data;
 124         uint64_t asid_generation;
 125         uint64_t sysenter_esp;
 126         uint64_t sysenter_eip;
 127
 128         u64 next_rip;
 129
 130         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 131         struct {
 132                 u16 fs;
 133                 u16 gs;
 134                 u16 ldt;
 135                 u64 gs_base;
 136         } host;
 137
 138         u32 *msrpm;
 139
 140         ulong nmi_iret_rip;
 141
 142         struct nested_state nested;
 143
 144         bool nmi_singlestep;
 145
 146         unsigned int3_injected;
 147         unsigned long int3_rip;
 148         u32 apf_reason;
 149
 150         u64  tsc_ratio;
 151 };
 152
 153 static DEFINE_PER_CPU(u64, current_tsc_ratio);
 154 #define TSC_RATIO_DEFAULT       0x0100000000ULL
 155
 156 #define MSR_INVALID                     0xffffffffU
 157
 158 static struct svm_direct_access_msrs {
 159         u32 index;   /* Index of the MSR */
 160         bool always; /* True if intercept is always on */
 161 } direct_access_msrs[] = {
 162         { .index = MSR_STAR,                            .always = true  },
 163         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 164 #ifdef CONFIG_X86_64
 165         { .index = MSR_GS_BASE,                         .always = true  },
 166         { .index = MSR_FS_BASE,                         .always = true  },
 167         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 168         { .index = MSR_LSTAR,                           .always = true  },
 169         { .index = MSR_CSTAR,                           .always = true  },
 170         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 171 #endif
 172         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 173         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 174         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 175         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 176         { .index = MSR_INVALID,                         .always = false },
 177 };
 178
 179 /* enable NPT for AMD64 and X86 with PAE */
 180 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 181 static bool npt_enabled = true;
 182 #else
 183 static bool npt_enabled;
 184 #endif
 185
 186 /* allow nested paging (virtualized MMU) for all guests */
 187 static int npt = true;
 188 module_param(npt, int, S_IRUGO);
 189
 190 /* allow nested virtualization in KVM/SVM */
 191 static int nested = true;
 192 module_param(nested, int, S_IRUGO);
 193
 194 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 195 static void svm_complete_interrupts(struct vcpu_svm *svm);
 196
 197 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 198 static int nested_svm_intercept(struct vcpu_svm *svm);
 199 static int nested_svm_vmexit(struct vcpu_svm *svm);
 200 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 201                                       bool has_error_code, u32 error_code);
 202 static u64 __scale_tsc(u64 ratio, u64 tsc);
 203
 204 enum {
 205         VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
 206                             pause filter count */
 207         VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
 208         VMCB_ASID,       /* ASID */
 209         VMCB_INTR,       /* int_ctl, int_vector */
 210         VMCB_NPT,        /* npt_en, nCR3, gPAT */
 211         VMCB_CR,         /* CR0, CR3, CR4, EFER */
 212         VMCB_DR,         /* DR6, DR7 */
 213         VMCB_DT,         /* GDT, IDT */
 214         VMCB_SEG,        /* CS, DS, SS, ES, CPL */
 215         VMCB_CR2,        /* CR2 only */
 216         VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
 217         VMCB_DIRTY_MAX,
 218 };
 219
 220 /* TPR and CR2 are always written before VMRUN */
 221 #define VMCB_ALWAYS_DIRTY_MASK  ((1U << VMCB_INTR) | (1U << VMCB_CR2))
 222
 223 static inline void mark_all_dirty(struct vmcb *vmcb)
 224 {
 225         vmcb->control.clean = 0;
 226 }
 227
 228 static inline void mark_all_clean(struct vmcb *vmcb)
 229 {
 230         vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
 231                                & ~VMCB_ALWAYS_DIRTY_MASK;
 232 }
 233
 234 static inline void mark_dirty(struct vmcb *vmcb, int bit)
 235 {
 236         vmcb->control.clean &= ~(1 << bit);
 237 }
 238
 239 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 240 {
 241         return container_of(vcpu, struct vcpu_svm, vcpu);
 242 }
 243
 244 static void recalc_intercepts(struct vcpu_svm *svm)
 245 {
 246         struct vmcb_control_area *c, *h;
 247         struct nested_state *g;
 248
 249         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 250
 251         if (!is_guest_mode(&svm->vcpu))
 252                 return;
 253
 254         c = &svm->vmcb->control;
 255         h = &svm->nested.hsave->control;
 256         g = &svm->nested;
 257
 258         c->intercept_cr = h->intercept_cr | g->intercept_cr;
 259         c->intercept_dr = h->intercept_dr | g->intercept_dr;
 260         c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
 261         c->intercept = h->intercept | g->intercept;
 262 }
 263
 264 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
 265 {
 266         if (is_guest_mode(&svm->vcpu))
 267                 return svm->nested.hsave;
 268         else
 269                 return svm->vmcb;
 270 }
 271
 272 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
 273 {
 274         struct vmcb *vmcb = get_host_vmcb(svm);
 275
 276         vmcb->control.intercept_cr |= (1U << bit);
 277
 278         recalc_intercepts(svm);
 279 }
 280
 281 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
 282 {
 283         struct vmcb *vmcb = get_host_vmcb(svm);
 284
 285         vmcb->control.intercept_cr &= ~(1U << bit);
 286
 287         recalc_intercepts(svm);
 288 }
 289
 290 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
 291 {
 292         struct vmcb *vmcb = get_host_vmcb(svm);
 293
 294         return vmcb->control.intercept_cr & (1U << bit);
 295 }
 296
 297 static inline void set_dr_intercept(struct vcpu_svm *svm, int bit)
 298 {
 299         struct vmcb *vmcb = get_host_vmcb(svm);
 300
 301         vmcb->control.intercept_dr |= (1U << bit);
 302
 303         recalc_intercepts(svm);
 304 }
 305
 306 static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit)
 307 {
 308         struct vmcb *vmcb = get_host_vmcb(svm);
 309
 310         vmcb->control.intercept_dr &= ~(1U << bit);
 311
 312         recalc_intercepts(svm);
 313 }
 314
 315 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
 316 {
 317         struct vmcb *vmcb = get_host_vmcb(svm);
 318
 319         vmcb->control.intercept_exceptions |= (1U << bit);
 320
 321         recalc_intercepts(svm);
 322 }
 323
 324 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
 325 {
 326         struct vmcb *vmcb = get_host_vmcb(svm);
 327
 328         vmcb->control.intercept_exceptions &= ~(1U << bit);
 329
 330         recalc_intercepts(svm);
 331 }
 332
 333 static inline void set_intercept(struct vcpu_svm *svm, int bit)
 334 {
 335         struct vmcb *vmcb = get_host_vmcb(svm);
 336
 337         vmcb->control.intercept |= (1ULL << bit);
 338
 339         recalc_intercepts(svm);
 340 }
 341
 342 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
 343 {
 344         struct vmcb *vmcb = get_host_vmcb(svm);
 345
 346         vmcb->control.intercept &= ~(1ULL << bit);
 347
 348         recalc_intercepts(svm);
 349 }
 350
 351 static inline void enable_gif(struct vcpu_svm *svm)
 352 {
 353         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 354 }
 355
 356 static inline void disable_gif(struct vcpu_svm *svm)
 357 {
 358         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 359 }
 360
 361 static inline bool gif_set(struct vcpu_svm *svm)
 362 {
 363         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 364 }
 365
 366 static unsigned long iopm_base;
 367
 368 struct kvm_ldttss_desc {
 369         u16 limit0;
 370         u16 base0;
 371         unsigned base1:8, type:5, dpl:2, p:1;
 372         unsigned limit1:4, zero0:3, g:1, base2:8;
 373         u32 base3;
 374         u32 zero1;
 375 } __attribute__((packed));
 376
 377 struct svm_cpu_data {
 378         int cpu;
 379
 380         u64 asid_generation;
 381         u32 max_asid;
 382         u32 next_asid;
 383         struct kvm_ldttss_desc *tss_desc;
 384
 385         struct page *save_area;
 386 };
 387
 388 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 389
 390 struct svm_init_data {
 391         int cpu;
 392         int r;
 393 };
 394
 395 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 396
 397 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 398 #define MSRS_RANGE_SIZE 2048
 399 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 400
 401 static u32 svm_msrpm_offset(u32 msr)
 402 {
 403         u32 offset;
 404         int i;
 405
 406         for (i = 0; i < NUM_MSR_MAPS; i++) {
 407                 if (msr < msrpm_ranges[i] ||
 408                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 409                         continue;
 410
 411                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 412                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 413
 414                 /* Now we have the u8 offset - but need the u32 offset */
 415                 return offset / 4;
 416         }
 417
 418         /* MSR not in any range */
 419         return MSR_INVALID;
 420 }
 421
 422 #define MAX_INST_SIZE 15
 423
 424 static inline void clgi(void)
 425 {
 426         asm volatile (__ex(SVM_CLGI));
 427 }
 428
 429 static inline void stgi(void)
 430 {
 431         asm volatile (__ex(SVM_STGI));
 432 }
 433
 434 static inline void invlpga(unsigned long addr, u32 asid)
 435 {
 436         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
 437 }
 438
 439 static int get_npt_level(void)
 440 {
 441 #ifdef CONFIG_X86_64
 442         return PT64_ROOT_LEVEL;
 443 #else
 444         return PT32E_ROOT_LEVEL;
 445 #endif
 446 }
 447
 448 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 449 {
 450         vcpu->arch.efer = efer;
 451         if (!npt_enabled && !(efer & EFER_LMA))
 452                 efer &= ~EFER_LME;
 453
 454         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 455         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
 456 }
 457
 458 static int is_external_interrupt(u32 info)
 459 {
 460         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 461         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 462 }
 463
 464 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 465 {
 466         struct vcpu_svm *svm = to_svm(vcpu);
 467         u32 ret = 0;
 468
 469         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 470                 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 471         return ret & mask;
 472 }
 473
 474 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 475 {
 476         struct vcpu_svm *svm = to_svm(vcpu);
 477
 478         if (mask == 0)
 479                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 480         else
 481                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 482
 483 }
 484
 485 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 486 {
 487         struct vcpu_svm *svm = to_svm(vcpu);
 488
 489         if (svm->vmcb->control.next_rip != 0)
 490                 svm->next_rip = svm->vmcb->control.next_rip;
 491
 492         if (!svm->next_rip) {
 493                 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
 494                                 EMULATE_DONE)
 495                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 496                 return;
 497         }
 498         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 499                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 500                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 501
 502         kvm_rip_write(vcpu, svm->next_rip);
 503         svm_set_interrupt_shadow(vcpu, 0);
 504 }
 505
 506 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 507                                 bool has_error_code, u32 error_code,
 508                                 bool reinject)
 509 {
 510         struct vcpu_svm *svm = to_svm(vcpu);
 511
 512         /*
 513          * If we are within a nested VM we'd better #VMEXIT and let the guest
 514          * handle the exception
 515          */
 516         if (!reinject &&
 517             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 518                 return;
 519
 520         if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
 521                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 522
 523                 /*
 524                  * For guest debugging where we have to reinject #BP if some
 525                  * INT3 is guest-owned:
 526                  * Emulate nRIP by moving RIP forward. Will fail if injection
 527                  * raises a fault that is not intercepted. Still better than
 528                  * failing in all cases.
 529                  */
 530                 skip_emulated_instruction(&svm->vcpu);
 531                 rip = kvm_rip_read(&svm->vcpu);
 532                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 533                 svm->int3_injected = rip - old_rip;
 534         }
 535
 536         svm->vmcb->control.event_inj = nr
 537                 | SVM_EVTINJ_VALID
 538                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 539                 | SVM_EVTINJ_TYPE_EXEPT;
 540         svm->vmcb->control.event_inj_err = error_code;
 541 }
 542
 543 static void svm_init_erratum_383(void)
 544 {
 545         u32 low, high;
 546         int err;
 547         u64 val;
 548
 549         if (!cpu_has_amd_erratum(amd_erratum_383))
 550                 return;
 551
 552         /* Use _safe variants to not break nested virtualization */
 553         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 554         if (err)
 555                 return;
 556
 557         val |= (1ULL << 47);
 558
 559         low  = lower_32_bits(val);
 560         high = upper_32_bits(val);
 561
 562         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 563
 564         erratum_383_found = true;
 565 }
 566
 567 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 568 {
 569         /*
 570          * Guests should see errata 400 and 415 as fixed (assuming that
 571          * HLT and IO instructions are intercepted).
 572          */
 573         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 574         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 575
 576         /*
 577          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 578          * all osvw.status bits inside that length, including bit 0 (which is
 579          * reserved for erratum 298), are valid. However, if host processor's
 580          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 581          * be conservative here and therefore we tell the guest that erratum 298
 582          * is present (because we really don't know).
 583          */
 584         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 585                 vcpu->arch.osvw.status |= 1;
 586 }
 587
 588 static int has_svm(void)
 589 {
 590         const char *msg;
 591
 592         if (!cpu_has_svm(&msg)) {
 593                 printk(KERN_INFO "has_svm: %s\n", msg);
 594                 return 0;
 595         }
 596
 597         return 1;
 598 }
 599
 600 static void svm_hardware_disable(void *garbage)
 601 {
 602         /* Make sure we clean up behind us */
 603         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 604                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 605
 606         cpu_svm_disable();
 607 }
 608
 609 static int svm_hardware_enable(void *garbage)
 610 {
 611
 612         struct svm_cpu_data *sd;
 613         uint64_t efer;
 614         struct desc_ptr gdt_descr;
 615         struct desc_struct *gdt;
 616         int me = raw_smp_processor_id();
 617
 618         rdmsrl(MSR_EFER, efer);
 619         if (efer & EFER_SVME)
 620                 return -EBUSY;
 621
 622         if (!has_svm()) {
 623                 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
 624                        me);
 625                 return -EINVAL;
 626         }
 627         sd = per_cpu(svm_data, me);
 628
 629         if (!sd) {
 630                 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
 631                        me);
 632                 return -EINVAL;
 633         }
 634
 635         sd->asid_generation = 1;
 636         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 637         sd->next_asid = sd->max_asid + 1;
 638
 639         native_store_gdt(&gdt_descr);
 640         gdt = (struct desc_struct *)gdt_descr.address;
 641         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 642
 643         wrmsrl(MSR_EFER, efer | EFER_SVME);
 644
 645         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 646
 647         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 648                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 649                 __get_cpu_var(current_tsc_ratio) = TSC_RATIO_DEFAULT;
 650         }
 651
 652
 653         /*
 654          * Get OSVW bits.
 655          *
 656          * Note that it is possible to have a system with mixed processor
 657          * revisions and therefore different OSVW bits. If bits are not the same
 658          * on different processors then choose the worst case (i.e. if erratum
 659          * is present on one processor and not on another then assume that the
 660          * erratum is present everywhere).
 661          */
 662         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 663                 uint64_t len, status = 0;
 664                 int err;
 665
 666                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 667                 if (!err)
 668                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 669                                                       &err);
 670
 671                 if (err)
 672                         osvw_status = osvw_len = 0;
 673                 else {
 674                         if (len < osvw_len)
 675                                 osvw_len = len;
 676                         osvw_status |= status;
 677                         osvw_status &= (1ULL << osvw_len) - 1;
 678                 }
 679         } else
 680                 osvw_status = osvw_len = 0;
 681
 682         svm_init_erratum_383();
 683
 684         return 0;
 685 }
 686
 687 static void svm_cpu_uninit(int cpu)
 688 {
 689         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 690
 691         if (!sd)
 692                 return;
 693
 694         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 695         __free_page(sd->save_area);
 696         kfree(sd);
 697 }
 698
 699 static int svm_cpu_init(int cpu)
 700 {
 701         struct svm_cpu_data *sd;
 702         int r;
 703
 704         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 705         if (!sd)
 706                 return -ENOMEM;
 707         sd->cpu = cpu;
 708         sd->save_area = alloc_page(GFP_KERNEL);
 709         r = -ENOMEM;
 710         if (!sd->save_area)
 711                 goto err_1;
 712
 713         per_cpu(svm_data, cpu) = sd;
 714
 715         return 0;
 716
 717 err_1:
 718         kfree(sd);
 719         return r;
 720
 721 }
 722
 723 static bool valid_msr_intercept(u32 index)
 724 {
 725         int i;
 726
 727         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 728                 if (direct_access_msrs[i].index == index)
 729                         return true;
 730
 731         return false;
 732 }
 733
 734 static void set_msr_interception(u32 *msrpm, unsigned msr,
 735                                  int read, int write)
 736 {
 737         u8 bit_read, bit_write;
 738         unsigned long tmp;
 739         u32 offset;
 740
 741         /*
 742          * If this warning triggers extend the direct_access_msrs list at the
 743          * beginning of the file
 744          */
 745         WARN_ON(!valid_msr_intercept(msr));
 746
 747         offset    = svm_msrpm_offset(msr);
 748         bit_read  = 2 * (msr & 0x0f);
 749         bit_write = 2 * (msr & 0x0f) + 1;
 750         tmp       = msrpm[offset];
 751
 752         BUG_ON(offset == MSR_INVALID);
 753
 754         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 755         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 756
 757         msrpm[offset] = tmp;
 758 }
 759
 760 static void svm_vcpu_init_msrpm(u32 *msrpm)
 761 {
 762         int i;
 763
 764         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 765
 766         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 767                 if (!direct_access_msrs[i].always)
 768                         continue;
 769
 770                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
 771         }
 772 }
 773
 774 static void add_msr_offset(u32 offset)
 775 {
 776         int i;
 777
 778         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 779
 780                 /* Offset already in list? */
 781                 if (msrpm_offsets[i] == offset)
 782                         return;
 783
 784                 /* Slot used by another offset? */
 785                 if (msrpm_offsets[i] != MSR_INVALID)
 786                         continue;
 787
 788                 /* Add offset to list */
 789                 msrpm_offsets[i] = offset;
 790
 791                 return;
 792         }
 793
 794         /*
 795          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 796          * increase MSRPM_OFFSETS in this case.
 797          */
 798         BUG();
 799 }
 800
 801 static void init_msrpm_offsets(void)
 802 {
 803         int i;
 804
 805         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 806
 807         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 808                 u32 offset;
 809
 810                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 811                 BUG_ON(offset == MSR_INVALID);
 812
 813                 add_msr_offset(offset);
 814         }
 815 }
 816
 817 static void svm_enable_lbrv(struct vcpu_svm *svm)
 818 {
 819         u32 *msrpm = svm->msrpm;
 820
 821         svm->vmcb->control.lbr_ctl = 1;
 822         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 823         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 824         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 825         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 826 }
 827
 828 static void svm_disable_lbrv(struct vcpu_svm *svm)
 829 {
 830         u32 *msrpm = svm->msrpm;
 831
 832         svm->vmcb->control.lbr_ctl = 0;
 833         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 834         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 835         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 836         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 837 }
 838
 839 static __init int svm_hardware_setup(void)
 840 {
 841         int cpu;
 842         struct page *iopm_pages;
 843         void *iopm_va;
 844         int r;
 845
 846         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 847
 848         if (!iopm_pages)
 849                 return -ENOMEM;
 850
 851         iopm_va = page_address(iopm_pages);
 852         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 853         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 854
 855         init_msrpm_offsets();
 856
 857         if (boot_cpu_has(X86_FEATURE_NX))
 858                 kvm_enable_efer_bits(EFER_NX);
 859
 860         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 861                 kvm_enable_efer_bits(EFER_FFXSR);
 862
 863         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 864                 u64 max;
 865
 866                 kvm_has_tsc_control = true;
 867
 868                 /*
 869                  * Make sure the user can only configure tsc_khz values that
 870                  * fit into a signed integer.
 871                  * A min value is not calculated needed because it will always
 872                  * be 1 on all machines and a value of 0 is used to disable
 873                  * tsc-scaling for the vcpu.
 874                  */
 875                 max = min(0x7fffffffULL, __scale_tsc(tsc_khz, TSC_RATIO_MAX));
 876
 877                 kvm_max_guest_tsc_khz = max;
 878         }
 879
 880         if (nested) {
 881                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 882                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
 883         }
 884
 885         for_each_possible_cpu(cpu) {
 886                 r = svm_cpu_init(cpu);
 887                 if (r)
 888                         goto err;
 889         }
 890
 891         if (!boot_cpu_has(X86_FEATURE_NPT))
 892                 npt_enabled = false;
 893
 894         if (npt_enabled && !npt) {
 895                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 896                 npt_enabled = false;
 897         }
 898
 899         if (npt_enabled) {
 900                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 901                 kvm_enable_tdp();
 902         } else
 903                 kvm_disable_tdp();
 904
 905         return 0;
 906
 907 err:
 908         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 909         iopm_base = 0;
 910         return r;
 911 }
 912
 913 static __exit void svm_hardware_unsetup(void)
 914 {
 915         int cpu;
 916
 917         for_each_possible_cpu(cpu)
 918                 svm_cpu_uninit(cpu);
 919
 920         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 921         iopm_base = 0;
 922 }
 923
 924 static void init_seg(struct vmcb_seg *seg)
 925 {
 926         seg->selector = 0;
 927         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 928                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 929         seg->limit = 0xffff;
 930         seg->base = 0;
 931 }
 932
 933 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 934 {
 935         seg->selector = 0;
 936         seg->attrib = SVM_SELECTOR_P_MASK | type;
 937         seg->limit = 0xffff;
 938         seg->base = 0;
 939 }
 940
 941 static u64 __scale_tsc(u64 ratio, u64 tsc)
 942 {
 943         u64 mult, frac, _tsc;
 944
 945         mult  = ratio >> 32;
 946         frac  = ratio & ((1ULL << 32) - 1);
 947
 948         _tsc  = tsc;
 949         _tsc *= mult;
 950         _tsc += (tsc >> 32) * frac;
 951         _tsc += ((tsc & ((1ULL << 32) - 1)) * frac) >> 32;
 952
 953         return _tsc;
 954 }
 955
 956 static u64 svm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
 957 {
 958         struct vcpu_svm *svm = to_svm(vcpu);
 959         u64 _tsc = tsc;
 960
 961         if (svm->tsc_ratio != TSC_RATIO_DEFAULT)
 962                 _tsc = __scale_tsc(svm->tsc_ratio, tsc);
 963
 964         return _tsc;
 965 }
 966
 967 static void svm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
 968 {
 969         struct vcpu_svm *svm = to_svm(vcpu);
 970         u64 ratio;
 971         u64 khz;
 972
 973         /* TSC scaling supported? */
 974         if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR))
 975                 return;
 976
 977         /* TSC-Scaling disabled or guest TSC same frequency as host TSC? */
 978         if (user_tsc_khz == 0) {
 979                 vcpu->arch.virtual_tsc_khz = 0;
 980                 svm->tsc_ratio = TSC_RATIO_DEFAULT;
 981                 return;
 982         }
 983
 984         khz = user_tsc_khz;
 985
 986         /* TSC scaling required  - calculate ratio */
 987         ratio = khz << 32;
 988         do_div(ratio, tsc_khz);
 989
 990         if (ratio == 0 || ratio & TSC_RATIO_RSVD) {
 991                 WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n",
 992                                 user_tsc_khz);
 993                 return;
 994         }
 995         vcpu->arch.virtual_tsc_khz = user_tsc_khz;
 996         svm->tsc_ratio             = ratio;
 997 }
 998
 999 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1000 {
1001         struct vcpu_svm *svm = to_svm(vcpu);
1002         u64 g_tsc_offset = 0;
1003
1004         if (is_guest_mode(vcpu)) {
1005                 g_tsc_offset = svm->vmcb->control.tsc_offset -
1006                                svm->nested.hsave->control.tsc_offset;
1007                 svm->nested.hsave->control.tsc_offset = offset;
1008         }
1009
1010         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1011
1012         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1013 }
1014
1015 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1016 {
1017         struct vcpu_svm *svm = to_svm(vcpu);
1018
1019         svm->vmcb->control.tsc_offset += adjustment;
1020         if (is_guest_mode(vcpu))
1021                 svm->nested.hsave->control.tsc_offset += adjustment;
1022         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1023 }
1024
1025 static u64 svm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1026 {
1027         u64 tsc;
1028
1029         tsc = svm_scale_tsc(vcpu, native_read_tsc());
1030
1031         return target_tsc - tsc;
1032 }
1033
1034 static void init_vmcb(struct vcpu_svm *svm)
1035 {
1036         struct vmcb_control_area *control = &svm->vmcb->control;
1037         struct vmcb_save_area *save = &svm->vmcb->save;
1038
1039         svm->vcpu.fpu_active = 1;
1040         svm->vcpu.arch.hflags = 0;
1041
1042         set_cr_intercept(svm, INTERCEPT_CR0_READ);
1043         set_cr_intercept(svm, INTERCEPT_CR3_READ);
1044         set_cr_intercept(svm, INTERCEPT_CR4_READ);
1045         set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1046         set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1047         set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1048         set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1049
1050         set_dr_intercept(svm, INTERCEPT_DR0_READ);
1051         set_dr_intercept(svm, INTERCEPT_DR1_READ);
1052         set_dr_intercept(svm, INTERCEPT_DR2_READ);
1053         set_dr_intercept(svm, INTERCEPT_DR3_READ);
1054         set_dr_intercept(svm, INTERCEPT_DR4_READ);
1055         set_dr_intercept(svm, INTERCEPT_DR5_READ);
1056         set_dr_intercept(svm, INTERCEPT_DR6_READ);
1057         set_dr_intercept(svm, INTERCEPT_DR7_READ);
1058
1059         set_dr_intercept(svm, INTERCEPT_DR0_WRITE);
1060         set_dr_intercept(svm, INTERCEPT_DR1_WRITE);
1061         set_dr_intercept(svm, INTERCEPT_DR2_WRITE);
1062         set_dr_intercept(svm, INTERCEPT_DR3_WRITE);
1063         set_dr_intercept(svm, INTERCEPT_DR4_WRITE);
1064         set_dr_intercept(svm, INTERCEPT_DR5_WRITE);
1065         set_dr_intercept(svm, INTERCEPT_DR6_WRITE);
1066         set_dr_intercept(svm, INTERCEPT_DR7_WRITE);
1067
1068         set_exception_intercept(svm, PF_VECTOR);
1069         set_exception_intercept(svm, UD_VECTOR);
1070         set_exception_intercept(svm, MC_VECTOR);
1071
1072         set_intercept(svm, INTERCEPT_INTR);
1073         set_intercept(svm, INTERCEPT_NMI);
1074         set_intercept(svm, INTERCEPT_SMI);
1075         set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1076         set_intercept(svm, INTERCEPT_RDPMC);
1077         set_intercept(svm, INTERCEPT_CPUID);
1078         set_intercept(svm, INTERCEPT_INVD);
1079         set_intercept(svm, INTERCEPT_HLT);
1080         set_intercept(svm, INTERCEPT_INVLPG);
1081         set_intercept(svm, INTERCEPT_INVLPGA);
1082         set_intercept(svm, INTERCEPT_IOIO_PROT);
1083         set_intercept(svm, INTERCEPT_MSR_PROT);
1084         set_intercept(svm, INTERCEPT_TASK_SWITCH);
1085         set_intercept(svm, INTERCEPT_SHUTDOWN);
1086         set_intercept(svm, INTERCEPT_VMRUN);
1087         set_intercept(svm, INTERCEPT_VMMCALL);
1088         set_intercept(svm, INTERCEPT_VMLOAD);
1089         set_intercept(svm, INTERCEPT_VMSAVE);
1090         set_intercept(svm, INTERCEPT_STGI);
1091         set_intercept(svm, INTERCEPT_CLGI);
1092         set_intercept(svm, INTERCEPT_SKINIT);
1093         set_intercept(svm, INTERCEPT_WBINVD);
1094         set_intercept(svm, INTERCEPT_MONITOR);
1095         set_intercept(svm, INTERCEPT_MWAIT);
1096         set_intercept(svm, INTERCEPT_XSETBV);
1097
1098         control->iopm_base_pa = iopm_base;
1099         control->msrpm_base_pa = __pa(svm->msrpm);
1100         control->int_ctl = V_INTR_MASKING_MASK;
1101
1102         init_seg(&save->es);
1103         init_seg(&save->ss);
1104         init_seg(&save->ds);
1105         init_seg(&save->fs);
1106         init_seg(&save->gs);
1107
1108         save->cs.selector = 0xf000;
1109         /* Executable/Readable Code Segment */
1110         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1111                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1112         save->cs.limit = 0xffff;
1113         /*
1114          * cs.base should really be 0xffff0000, but vmx can't handle that, so
1115          * be consistent with it.
1116          *
1117          * Replace when we have real mode working for vmx.
1118          */
1119         save->cs.base = 0xf0000;
1120
1121         save->gdtr.limit = 0xffff;
1122         save->idtr.limit = 0xffff;
1123
1124         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1125         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1126
1127         svm_set_efer(&svm->vcpu, 0);
1128         save->dr6 = 0xffff0ff0;
1129         save->dr7 = 0x400;
1130         kvm_set_rflags(&svm->vcpu, 2);
1131         save->rip = 0x0000fff0;
1132         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1133
1134         /*
1135          * This is the guest-visible cr0 value.
1136          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1137          */
1138         svm->vcpu.arch.cr0 = 0;
1139         (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1140
1141         save->cr4 = X86_CR4_PAE;
1142         /* rdx = ?? */
1143
1144         if (npt_enabled) {
1145                 /* Setup VMCB for Nested Paging */
1146                 control->nested_ctl = 1;
1147                 clr_intercept(svm, INTERCEPT_INVLPG);
1148                 clr_exception_intercept(svm, PF_VECTOR);
1149                 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1150                 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1151                 save->g_pat = 0x0007040600070406ULL;
1152                 save->cr3 = 0;
1153                 save->cr4 = 0;
1154         }
1155         svm->asid_generation = 0;
1156
1157         svm->nested.vmcb = 0;
1158         svm->vcpu.arch.hflags = 0;
1159
1160         if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1161                 control->pause_filter_count = 3000;
1162                 set_intercept(svm, INTERCEPT_PAUSE);
1163         }
1164
1165         mark_all_dirty(svm->vmcb);
1166
1167         enable_gif(svm);
1168 }
1169
1170 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
1171 {
1172         struct vcpu_svm *svm = to_svm(vcpu);
1173
1174         init_vmcb(svm);
1175
1176         if (!kvm_vcpu_is_bsp(vcpu)) {
1177                 kvm_rip_write(vcpu, 0);
1178                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
1179                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
1180         }
1181         vcpu->arch.regs_avail = ~0;
1182         vcpu->arch.regs_dirty = ~0;
1183
1184         return 0;
1185 }
1186
1187 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1188 {
1189         struct vcpu_svm *svm;
1190         struct page *page;
1191         struct page *msrpm_pages;
1192         struct page *hsave_page;
1193         struct page *nested_msrpm_pages;
1194         int err;
1195
1196         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1197         if (!svm) {
1198                 err = -ENOMEM;
1199                 goto out;
1200         }
1201
1202         svm->tsc_ratio = TSC_RATIO_DEFAULT;
1203
1204         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1205         if (err)
1206                 goto free_svm;
1207
1208         err = -ENOMEM;
1209         page = alloc_page(GFP_KERNEL);
1210         if (!page)
1211                 goto uninit;
1212
1213         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1214         if (!msrpm_pages)
1215                 goto free_page1;
1216
1217         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1218         if (!nested_msrpm_pages)
1219                 goto free_page2;
1220
1221         hsave_page = alloc_page(GFP_KERNEL);
1222         if (!hsave_page)
1223                 goto free_page3;
1224
1225         svm->nested.hsave = page_address(hsave_page);
1226
1227         svm->msrpm = page_address(msrpm_pages);
1228         svm_vcpu_init_msrpm(svm->msrpm);
1229
1230         svm->nested.msrpm = page_address(nested_msrpm_pages);
1231         svm_vcpu_init_msrpm(svm->nested.msrpm);
1232
1233         svm->vmcb = page_address(page);
1234         clear_page(svm->vmcb);
1235         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1236         svm->asid_generation = 0;
1237         init_vmcb(svm);
1238         kvm_write_tsc(&svm->vcpu, 0);
1239
1240         err = fx_init(&svm->vcpu);
1241         if (err)
1242                 goto free_page4;
1243
1244         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1245         if (kvm_vcpu_is_bsp(&svm->vcpu))
1246                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1247
1248         svm_init_osvw(&svm->vcpu);
1249
1250         return &svm->vcpu;
1251
1252 free_page4:
1253         __free_page(hsave_page);
1254 free_page3:
1255         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1256 free_page2:
1257         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1258 free_page1:
1259         __free_page(page);
1260 uninit:
1261         kvm_vcpu_uninit(&svm->vcpu);
1262 free_svm:
1263         kmem_cache_free(kvm_vcpu_cache, svm);
1264 out:
1265         return ERR_PTR(err);
1266 }
1267
1268 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1269 {
1270         struct vcpu_svm *svm = to_svm(vcpu);
1271
1272         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1273         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1274         __free_page(virt_to_page(svm->nested.hsave));
1275         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1276         kvm_vcpu_uninit(vcpu);
1277         kmem_cache_free(kvm_vcpu_cache, svm);
1278 }
1279
1280 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1281 {
1282         struct vcpu_svm *svm = to_svm(vcpu);
1283         int i;
1284
1285         if (unlikely(cpu != vcpu->cpu)) {
1286                 svm->asid_generation = 0;
1287                 mark_all_dirty(svm->vmcb);
1288         }
1289
1290 #ifdef CONFIG_X86_64
1291         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1292 #endif
1293         savesegment(fs, svm->host.fs);
1294         savesegment(gs, svm->host.gs);
1295         svm->host.ldt = kvm_read_ldt();
1296
1297         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1298                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1299
1300         if (static_cpu_has(X86_FEATURE_TSCRATEMSR) &&
1301             svm->tsc_ratio != __get_cpu_var(current_tsc_ratio)) {
1302                 __get_cpu_var(current_tsc_ratio) = svm->tsc_ratio;
1303                 wrmsrl(MSR_AMD64_TSC_RATIO, svm->tsc_ratio);
1304         }
1305 }
1306
1307 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1308 {
1309         struct vcpu_svm *svm = to_svm(vcpu);
1310         int i;
1311
1312         ++vcpu->stat.host_state_reload;
1313         kvm_load_ldt(svm->host.ldt);
1314 #ifdef CONFIG_X86_64
1315         loadsegment(fs, svm->host.fs);
1316         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1317         load_gs_index(svm->host.gs);
1318 #else
1319 #ifdef CONFIG_X86_32_LAZY_GS
1320         loadsegment(gs, svm->host.gs);
1321 #endif
1322 #endif
1323         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1324                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1325 }
1326
1327 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1328 {
1329         return to_svm(vcpu)->vmcb->save.rflags;
1330 }
1331
1332 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1333 {
1334         to_svm(vcpu)->vmcb->save.rflags = rflags;
1335 }
1336
1337 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1338 {
1339         switch (reg) {
1340         case VCPU_EXREG_PDPTR:
1341                 BUG_ON(!npt_enabled);
1342                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1343                 break;
1344         default:
1345                 BUG();
1346         }
1347 }
1348
1349 static void svm_set_vintr(struct vcpu_svm *svm)
1350 {
1351         set_intercept(svm, INTERCEPT_VINTR);
1352 }
1353
1354 static void svm_clear_vintr(struct vcpu_svm *svm)
1355 {
1356         clr_intercept(svm, INTERCEPT_VINTR);
1357 }
1358
1359 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1360 {
1361         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1362
1363         switch (seg) {
1364         case VCPU_SREG_CS: return &save->cs;
1365         case VCPU_SREG_DS: return &save->ds;
1366         case VCPU_SREG_ES: return &save->es;
1367         case VCPU_SREG_FS: return &save->fs;
1368         case VCPU_SREG_GS: return &save->gs;
1369         case VCPU_SREG_SS: return &save->ss;
1370         case VCPU_SREG_TR: return &save->tr;
1371         case VCPU_SREG_LDTR: return &save->ldtr;
1372         }
1373         BUG();
1374         return NULL;
1375 }
1376
1377 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1378 {
1379         struct vmcb_seg *s = svm_seg(vcpu, seg);
1380
1381         return s->base;
1382 }
1383
1384 static void svm_get_segment(struct kvm_vcpu *vcpu,
1385                             struct kvm_segment *var, int seg)
1386 {
1387         struct vmcb_seg *s = svm_seg(vcpu, seg);
1388
1389         var->base = s->base;
1390         var->limit = s->limit;
1391         var->selector = s->selector;
1392         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1393         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1394         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1395         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1396         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1397         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1398         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1399         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1400
1401         /*
1402          * AMD's VMCB does not have an explicit unusable field, so emulate it
1403          * for cross vendor migration purposes by "not present"
1404          */
1405         var->unusable = !var->present || (var->type == 0);
1406
1407         switch (seg) {
1408         case VCPU_SREG_CS:
1409                 /*
1410                  * SVM always stores 0 for the 'G' bit in the CS selector in
1411                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1412                  * Intel's VMENTRY has a check on the 'G' bit.
1413                  */
1414                 var->g = s->limit > 0xfffff;
1415                 break;
1416         case VCPU_SREG_TR:
1417                 /*
1418                  * Work around a bug where the busy flag in the tr selector
1419                  * isn't exposed
1420                  */
1421                 var->type |= 0x2;
1422                 break;
1423         case VCPU_SREG_DS:
1424         case VCPU_SREG_ES:
1425         case VCPU_SREG_FS:
1426         case VCPU_SREG_GS:
1427                 /*
1428                  * The accessed bit must always be set in the segment
1429                  * descriptor cache, although it can be cleared in the
1430                  * descriptor, the cached bit always remains at 1. Since
1431                  * Intel has a check on this, set it here to support
1432                  * cross-vendor migration.
1433                  */
1434                 if (!var->unusable)
1435                         var->type |= 0x1;
1436                 break;
1437         case VCPU_SREG_SS:
1438                 /*
1439                  * On AMD CPUs sometimes the DB bit in the segment
1440                  * descriptor is left as 1, although the whole segment has
1441                  * been made unusable. Clear it here to pass an Intel VMX
1442                  * entry check when cross vendor migrating.
1443                  */
1444                 if (var->unusable)
1445                         var->db = 0;
1446                 break;
1447         }
1448 }
1449
1450 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1451 {
1452         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1453
1454         return save->cpl;
1455 }
1456
1457 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1458 {
1459         struct vcpu_svm *svm = to_svm(vcpu);
1460
1461         dt->size = svm->vmcb->save.idtr.limit;
1462         dt->address = svm->vmcb->save.idtr.base;
1463 }
1464
1465 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1466 {
1467         struct vcpu_svm *svm = to_svm(vcpu);
1468
1469         svm->vmcb->save.idtr.limit = dt->size;
1470         svm->vmcb->save.idtr.base = dt->address ;
1471         mark_dirty(svm->vmcb, VMCB_DT);
1472 }
1473
1474 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1475 {
1476         struct vcpu_svm *svm = to_svm(vcpu);
1477
1478         dt->size = svm->vmcb->save.gdtr.limit;
1479         dt->address = svm->vmcb->save.gdtr.base;
1480 }
1481
1482 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1483 {
1484         struct vcpu_svm *svm = to_svm(vcpu);
1485
1486         svm->vmcb->save.gdtr.limit = dt->size;
1487         svm->vmcb->save.gdtr.base = dt->address ;
1488         mark_dirty(svm->vmcb, VMCB_DT);
1489 }
1490
1491 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1492 {
1493 }
1494
1495 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1496 {
1497 }
1498
1499 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1500 {
1501 }
1502
1503 static void update_cr0_intercept(struct vcpu_svm *svm)
1504 {
1505         ulong gcr0 = svm->vcpu.arch.cr0;
1506         u64 *hcr0 = &svm->vmcb->save.cr0;
1507
1508         if (!svm->vcpu.fpu_active)
1509                 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1510         else
1511                 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1512                         | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1513
1514         mark_dirty(svm->vmcb, VMCB_CR);
1515
1516         if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1517                 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1518                 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1519         } else {
1520                 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1521                 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1522         }
1523 }
1524
1525 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1526 {
1527         struct vcpu_svm *svm = to_svm(vcpu);
1528
1529 #ifdef CONFIG_X86_64
1530         if (vcpu->arch.efer & EFER_LME) {
1531                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1532                         vcpu->arch.efer |= EFER_LMA;
1533                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1534                 }
1535
1536                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1537                         vcpu->arch.efer &= ~EFER_LMA;
1538                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1539                 }
1540         }
1541 #endif
1542         vcpu->arch.cr0 = cr0;
1543
1544         if (!npt_enabled)
1545                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1546
1547         if (!vcpu->fpu_active)
1548                 cr0 |= X86_CR0_TS;
1549         /*
1550          * re-enable caching here because the QEMU bios
1551          * does not do it - this results in some delay at
1552          * reboot
1553          */
1554         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1555         svm->vmcb->save.cr0 = cr0;
1556         mark_dirty(svm->vmcb, VMCB_CR);
1557         update_cr0_intercept(svm);
1558 }
1559
1560 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1561 {
1562         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1563         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1564
1565         if (cr4 & X86_CR4_VMXE)
1566                 return 1;
1567
1568         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1569                 svm_flush_tlb(vcpu);
1570
1571         vcpu->arch.cr4 = cr4;
1572         if (!npt_enabled)
1573                 cr4 |= X86_CR4_PAE;
1574         cr4 |= host_cr4_mce;
1575         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1576         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1577         return 0;
1578 }
1579
1580 static void svm_set_segment(struct kvm_vcpu *vcpu,
1581                             struct kvm_segment *var, int seg)
1582 {
1583         struct vcpu_svm *svm = to_svm(vcpu);
1584         struct vmcb_seg *s = svm_seg(vcpu, seg);
1585
1586         s->base = var->base;
1587         s->limit = var->limit;
1588         s->selector = var->selector;
1589         if (var->unusable)
1590                 s->attrib = 0;
1591         else {
1592                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1593                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1594                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1595                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1596                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1597                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1598                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1599                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1600         }
1601         if (seg == VCPU_SREG_CS)
1602                 svm->vmcb->save.cpl
1603                         = (svm->vmcb->save.cs.attrib
1604                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
1605
1606         mark_dirty(svm->vmcb, VMCB_SEG);
1607 }
1608
1609 static void update_db_intercept(struct kvm_vcpu *vcpu)
1610 {
1611         struct vcpu_svm *svm = to_svm(vcpu);
1612
1613         clr_exception_intercept(svm, DB_VECTOR);
1614         clr_exception_intercept(svm, BP_VECTOR);
1615
1616         if (svm->nmi_singlestep)
1617                 set_exception_intercept(svm, DB_VECTOR);
1618
1619         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1620                 if (vcpu->guest_debug &
1621                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1622                         set_exception_intercept(svm, DB_VECTOR);
1623                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1624                         set_exception_intercept(svm, BP_VECTOR);
1625         } else
1626                 vcpu->guest_debug = 0;
1627 }
1628
1629 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1630 {
1631         struct vcpu_svm *svm = to_svm(vcpu);
1632
1633         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1634                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1635         else
1636                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1637
1638         mark_dirty(svm->vmcb, VMCB_DR);
1639
1640         update_db_intercept(vcpu);
1641 }
1642
1643 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1644 {
1645         if (sd->next_asid > sd->max_asid) {
1646                 ++sd->asid_generation;
1647                 sd->next_asid = 1;
1648                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1649         }
1650
1651         svm->asid_generation = sd->asid_generation;
1652         svm->vmcb->control.asid = sd->next_asid++;
1653
1654         mark_dirty(svm->vmcb, VMCB_ASID);
1655 }
1656
1657 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1658 {
1659         struct vcpu_svm *svm = to_svm(vcpu);
1660
1661         svm->vmcb->save.dr7 = value;
1662         mark_dirty(svm->vmcb, VMCB_DR);
1663 }
1664
1665 static int pf_interception(struct vcpu_svm *svm)
1666 {
1667         u64 fault_address = svm->vmcb->control.exit_info_2;
1668         u32 error_code;
1669         int r = 1;
1670
1671         switch (svm->apf_reason) {
1672         default:
1673                 error_code = svm->vmcb->control.exit_info_1;
1674
1675                 trace_kvm_page_fault(fault_address, error_code);
1676                 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1677                         kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1678                 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1679                         svm->vmcb->control.insn_bytes,
1680                         svm->vmcb->control.insn_len);
1681                 break;
1682         case KVM_PV_REASON_PAGE_NOT_PRESENT:
1683                 svm->apf_reason = 0;
1684                 local_irq_disable();
1685                 kvm_async_pf_task_wait(fault_address);
1686                 local_irq_enable();
1687                 break;
1688         case KVM_PV_REASON_PAGE_READY:
1689                 svm->apf_reason = 0;
1690                 local_irq_disable();
1691                 kvm_async_pf_task_wake(fault_address);
1692                 local_irq_enable();
1693                 break;
1694         }
1695         return r;
1696 }
1697
1698 static int db_interception(struct vcpu_svm *svm)
1699 {
1700         struct kvm_run *kvm_run = svm->vcpu.run;
1701
1702         if (!(svm->vcpu.guest_debug &
1703               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1704                 !svm->nmi_singlestep) {
1705                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1706                 return 1;
1707         }
1708
1709         if (svm->nmi_singlestep) {
1710                 svm->nmi_singlestep = false;
1711                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1712                         svm->vmcb->save.rflags &=
1713                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1714                 update_db_intercept(&svm->vcpu);
1715         }
1716
1717         if (svm->vcpu.guest_debug &
1718             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1719                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1720                 kvm_run->debug.arch.pc =
1721                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1722                 kvm_run->debug.arch.exception = DB_VECTOR;
1723                 return 0;
1724         }
1725
1726         return 1;
1727 }
1728
1729 static int bp_interception(struct vcpu_svm *svm)
1730 {
1731         struct kvm_run *kvm_run = svm->vcpu.run;
1732
1733         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1734         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1735         kvm_run->debug.arch.exception = BP_VECTOR;
1736         return 0;
1737 }
1738
1739 static int ud_interception(struct vcpu_svm *svm)
1740 {
1741         int er;
1742
1743         er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
1744         if (er != EMULATE_DONE)
1745                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1746         return 1;
1747 }
1748
1749 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1750 {
1751         struct vcpu_svm *svm = to_svm(vcpu);
1752
1753         clr_exception_intercept(svm, NM_VECTOR);
1754
1755         svm->vcpu.fpu_active = 1;
1756         update_cr0_intercept(svm);
1757 }
1758
1759 static int nm_interception(struct vcpu_svm *svm)
1760 {
1761         svm_fpu_activate(&svm->vcpu);
1762         return 1;
1763 }
1764
1765 static bool is_erratum_383(void)
1766 {
1767         int err, i;
1768         u64 value;
1769
1770         if (!erratum_383_found)
1771                 return false;
1772
1773         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1774         if (err)
1775                 return false;
1776
1777         /* Bit 62 may or may not be set for this mce */
1778         value &= ~(1ULL << 62);
1779
1780         if (value != 0xb600000000010015ULL)
1781                 return false;
1782
1783         /* Clear MCi_STATUS registers */
1784         for (i = 0; i < 6; ++i)
1785                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1786
1787         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1788         if (!err) {
1789                 u32 low, high;
1790
1791                 value &= ~(1ULL << 2);
1792                 low    = lower_32_bits(value);
1793                 high   = upper_32_bits(value);
1794
1795                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1796         }
1797
1798         /* Flush tlb to evict multi-match entries */
1799         __flush_tlb_all();
1800
1801         return true;
1802 }
1803
1804 static void svm_handle_mce(struct vcpu_svm *svm)
1805 {
1806         if (is_erratum_383()) {
1807                 /*
1808                  * Erratum 383 triggered. Guest state is corrupt so kill the
1809                  * guest.
1810                  */
1811                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1812
1813                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1814
1815                 return;
1816         }
1817
1818         /*
1819          * On an #MC intercept the MCE handler is not called automatically in
1820          * the host. So do it by hand here.
1821          */
1822         asm volatile (
1823                 "int $0x12\n");
1824         /* not sure if we ever come back to this point */
1825
1826         return;
1827 }
1828
1829 static int mc_interception(struct vcpu_svm *svm)
1830 {
1831         return 1;
1832 }
1833
1834 static int shutdown_interception(struct vcpu_svm *svm)
1835 {
1836         struct kvm_run *kvm_run = svm->vcpu.run;
1837
1838         /*
1839          * VMCB is undefined after a SHUTDOWN intercept
1840          * so reinitialize it.
1841          */
1842         clear_page(svm->vmcb);
1843         init_vmcb(svm);
1844
1845         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1846         return 0;
1847 }
1848
1849 static int io_interception(struct vcpu_svm *svm)
1850 {
1851         struct kvm_vcpu *vcpu = &svm->vcpu;
1852         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1853         int size, in, string;
1854         unsigned port;
1855
1856         ++svm->vcpu.stat.io_exits;
1857         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1858         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1859         if (string || in)
1860                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
1861
1862         port = io_info >> 16;
1863         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1864         svm->next_rip = svm->vmcb->control.exit_info_2;
1865         skip_emulated_instruction(&svm->vcpu);
1866
1867         return kvm_fast_pio_out(vcpu, size, port);
1868 }
1869
1870 static int nmi_interception(struct vcpu_svm *svm)
1871 {
1872         return 1;
1873 }
1874
1875 static int intr_interception(struct vcpu_svm *svm)
1876 {
1877         ++svm->vcpu.stat.irq_exits;
1878         return 1;
1879 }
1880
1881 static int nop_on_interception(struct vcpu_svm *svm)
1882 {
1883         return 1;
1884 }
1885
1886 static int halt_interception(struct vcpu_svm *svm)
1887 {
1888         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1889         skip_emulated_instruction(&svm->vcpu);
1890         return kvm_emulate_halt(&svm->vcpu);
1891 }
1892
1893 static int vmmcall_interception(struct vcpu_svm *svm)
1894 {
1895         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1896         skip_emulated_instruction(&svm->vcpu);
1897         kvm_emulate_hypercall(&svm->vcpu);
1898         return 1;
1899 }
1900
1901 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1902 {
1903         struct vcpu_svm *svm = to_svm(vcpu);
1904
1905         return svm->nested.nested_cr3;
1906 }
1907
1908 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
1909 {
1910         struct vcpu_svm *svm = to_svm(vcpu);
1911         u64 cr3 = svm->nested.nested_cr3;
1912         u64 pdpte;
1913         int ret;
1914
1915         ret = kvm_read_guest_page(vcpu->kvm, gpa_to_gfn(cr3), &pdpte,
1916                                   offset_in_page(cr3) + index * 8, 8);
1917         if (ret)
1918                 return 0;
1919         return pdpte;
1920 }
1921
1922 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1923                                    unsigned long root)
1924 {
1925         struct vcpu_svm *svm = to_svm(vcpu);
1926
1927         svm->vmcb->control.nested_cr3 = root;
1928         mark_dirty(svm->vmcb, VMCB_NPT);
1929         svm_flush_tlb(vcpu);
1930 }
1931
1932 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1933                                        struct x86_exception *fault)
1934 {
1935         struct vcpu_svm *svm = to_svm(vcpu);
1936
1937         svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1938         svm->vmcb->control.exit_code_hi = 0;
1939         svm->vmcb->control.exit_info_1 = fault->error_code;
1940         svm->vmcb->control.exit_info_2 = fault->address;
1941
1942         nested_svm_vmexit(svm);
1943 }
1944
1945 static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1946 {
1947         int r;
1948
1949         r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1950
1951         vcpu->arch.mmu.set_cr3           = nested_svm_set_tdp_cr3;
1952         vcpu->arch.mmu.get_cr3           = nested_svm_get_tdp_cr3;
1953         vcpu->arch.mmu.get_pdptr         = nested_svm_get_tdp_pdptr;
1954         vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1955         vcpu->arch.mmu.shadow_root_level = get_npt_level();
1956         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
1957
1958         return r;
1959 }
1960
1961 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1962 {
1963         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1964 }
1965
1966 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1967 {
1968         if (!(svm->vcpu.arch.efer & EFER_SVME)
1969             || !is_paging(&svm->vcpu)) {
1970                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1971                 return 1;
1972         }
1973
1974         if (svm->vmcb->save.cpl) {
1975                 kvm_inject_gp(&svm->vcpu, 0);
1976                 return 1;
1977         }
1978
1979        return 0;
1980 }
1981
1982 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1983                                       bool has_error_code, u32 error_code)
1984 {
1985         int vmexit;
1986
1987         if (!is_guest_mode(&svm->vcpu))
1988                 return 0;
1989
1990         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1991         svm->vmcb->control.exit_code_hi = 0;
1992         svm->vmcb->control.exit_info_1 = error_code;
1993         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1994
1995         vmexit = nested_svm_intercept(svm);
1996         if (vmexit == NESTED_EXIT_DONE)
1997                 svm->nested.exit_required = true;
1998
1999         return vmexit;
2000 }
2001
2002 /* This function returns true if it is save to enable the irq window */
2003 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2004 {
2005         if (!is_guest_mode(&svm->vcpu))
2006                 return true;
2007
2008         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2009                 return true;
2010
2011         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2012                 return false;
2013
2014         /*
2015          * if vmexit was already requested (by intercepted exception
2016          * for instance) do not overwrite it with "external interrupt"
2017          * vmexit.
2018          */
2019         if (svm->nested.exit_required)
2020                 return false;
2021
2022         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
2023         svm->vmcb->control.exit_info_1 = 0;
2024         svm->vmcb->control.exit_info_2 = 0;
2025
2026         if (svm->nested.intercept & 1ULL) {
2027                 /*
2028                  * The #vmexit can't be emulated here directly because this
2029                  * code path runs with irqs and preemtion disabled. A
2030                  * #vmexit emulation might sleep. Only signal request for
2031                  * the #vmexit here.
2032                  */
2033                 svm->nested.exit_required = true;
2034                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2035                 return false;
2036         }
2037
2038         return true;
2039 }
2040
2041 /* This function returns true if it is save to enable the nmi window */
2042 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2043 {
2044         if (!is_guest_mode(&svm->vcpu))
2045                 return true;
2046
2047         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2048                 return true;
2049
2050         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2051         svm->nested.exit_required = true;
2052
2053         return false;
2054 }
2055
2056 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2057 {
2058         struct page *page;
2059
2060         might_sleep();
2061
2062         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
2063         if (is_error_page(page))
2064                 goto error;
2065
2066         *_page = page;
2067
2068         return kmap(page);
2069
2070 error:
2071         kvm_release_page_clean(page);
2072         kvm_inject_gp(&svm->vcpu, 0);
2073
2074         return NULL;
2075 }
2076
2077 static void nested_svm_unmap(struct page *page)
2078 {
2079         kunmap(page);
2080         kvm_release_page_dirty(page);
2081 }
2082
2083 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2084 {
2085         unsigned port;
2086         u8 val, bit;
2087         u64 gpa;
2088
2089         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2090                 return NESTED_EXIT_HOST;
2091
2092         port = svm->vmcb->control.exit_info_1 >> 16;
2093         gpa  = svm->nested.vmcb_iopm + (port / 8);
2094         bit  = port % 8;
2095         val  = 0;
2096
2097         if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
2098                 val &= (1 << bit);
2099
2100         return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2101 }
2102
2103 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2104 {
2105         u32 offset, msr, value;
2106         int write, mask;
2107
2108         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2109                 return NESTED_EXIT_HOST;
2110
2111         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2112         offset = svm_msrpm_offset(msr);
2113         write  = svm->vmcb->control.exit_info_1 & 1;
2114         mask   = 1 << ((2 * (msr & 0xf)) + write);
2115
2116         if (offset == MSR_INVALID)
2117                 return NESTED_EXIT_DONE;
2118
2119         /* Offset is in 32 bit units but need in 8 bit units */
2120         offset *= 4;
2121
2122         if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
2123                 return NESTED_EXIT_DONE;
2124
2125         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2126 }
2127
2128 static int nested_svm_exit_special(struct vcpu_svm *svm)
2129 {
2130         u32 exit_code = svm->vmcb->control.exit_code;
2131
2132         switch (exit_code) {
2133         case SVM_EXIT_INTR:
2134         case SVM_EXIT_NMI:
2135         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2136                 return NESTED_EXIT_HOST;
2137         case SVM_EXIT_NPF:
2138                 /* For now we are always handling NPFs when using them */
2139                 if (npt_enabled)
2140                         return NESTED_EXIT_HOST;
2141                 break;
2142         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2143                 /* When we're shadowing, trap PFs, but not async PF */
2144                 if (!npt_enabled && svm->apf_reason == 0)
2145                         return NESTED_EXIT_HOST;
2146                 break;
2147         case SVM_EXIT_EXCP_BASE + NM_VECTOR:
2148                 nm_interception(svm);
2149                 break;
2150         default:
2151                 break;
2152         }
2153
2154         return NESTED_EXIT_CONTINUE;
2155 }
2156
2157 /*
2158  * If this function returns true, this #vmexit was already handled
2159  */
2160 static int nested_svm_intercept(struct vcpu_svm *svm)
2161 {
2162         u32 exit_code = svm->vmcb->control.exit_code;
2163         int vmexit = NESTED_EXIT_HOST;
2164
2165         switch (exit_code) {
2166         case SVM_EXIT_MSR:
2167                 vmexit = nested_svm_exit_handled_msr(svm);
2168                 break;
2169         case SVM_EXIT_IOIO:
2170                 vmexit = nested_svm_intercept_ioio(svm);
2171                 break;
2172         case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2173                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2174                 if (svm->nested.intercept_cr & bit)
2175                         vmexit = NESTED_EXIT_DONE;
2176                 break;
2177         }
2178         case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2179                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2180                 if (svm->nested.intercept_dr & bit)
2181                         vmexit = NESTED_EXIT_DONE;
2182                 break;
2183         }
2184         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2185                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2186                 if (svm->nested.intercept_exceptions & excp_bits)
2187                         vmexit = NESTED_EXIT_DONE;
2188                 /* async page fault always cause vmexit */
2189                 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2190                          svm->apf_reason != 0)
2191                         vmexit = NESTED_EXIT_DONE;
2192                 break;
2193         }
2194         case SVM_EXIT_ERR: {
2195                 vmexit = NESTED_EXIT_DONE;
2196                 break;
2197         }
2198         default: {
2199                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2200                 if (svm->nested.intercept & exit_bits)
2201                         vmexit = NESTED_EXIT_DONE;
2202         }
2203         }
2204
2205         return vmexit;
2206 }
2207
2208 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2209 {
2210         int vmexit;
2211
2212         vmexit = nested_svm_intercept(svm);
2213
2214         if (vmexit == NESTED_EXIT_DONE)
2215                 nested_svm_vmexit(svm);
2216
2217         return vmexit;
2218 }
2219
2220 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2221 {
2222         struct vmcb_control_area *dst  = &dst_vmcb->control;
2223         struct vmcb_control_area *from = &from_vmcb->control;
2224
2225         dst->intercept_cr         = from->intercept_cr;
2226         dst->intercept_dr         = from->intercept_dr;
2227         dst->intercept_exceptions = from->intercept_exceptions;
2228         dst->intercept            = from->intercept;
2229         dst->iopm_base_pa         = from->iopm_base_pa;
2230         dst->msrpm_base_pa        = from->msrpm_base_pa;
2231         dst->tsc_offset           = from->tsc_offset;
2232         dst->asid                 = from->asid;
2233         dst->tlb_ctl              = from->tlb_ctl;
2234         dst->int_ctl              = from->int_ctl;
2235         dst->int_vector           = from->int_vector;
2236         dst->int_state            = from->int_state;
2237         dst->exit_code            = from->exit_code;
2238         dst->exit_code_hi         = from->exit_code_hi;
2239         dst->exit_info_1          = from->exit_info_1;
2240         dst->exit_info_2          = from->exit_info_2;
2241         dst->exit_int_info        = from->exit_int_info;
2242         dst->exit_int_info_err    = from->exit_int_info_err;
2243         dst->nested_ctl           = from->nested_ctl;
2244         dst->event_inj            = from->event_inj;
2245         dst->event_inj_err        = from->event_inj_err;
2246         dst->nested_cr3           = from->nested_cr3;
2247         dst->lbr_ctl              = from->lbr_ctl;
2248 }
2249
2250 static int nested_svm_vmexit(struct vcpu_svm *svm)
2251 {
2252         struct vmcb *nested_vmcb;
2253         struct vmcb *hsave = svm->nested.hsave;
2254         struct vmcb *vmcb = svm->vmcb;
2255         struct page *page;
2256
2257         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2258                                        vmcb->control.exit_info_1,
2259                                        vmcb->control.exit_info_2,
2260                                        vmcb->control.exit_int_info,
2261                                        vmcb->control.exit_int_info_err,
2262                                        KVM_ISA_SVM);
2263
2264         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2265         if (!nested_vmcb)
2266                 return 1;
2267
2268         /* Exit Guest-Mode */
2269         leave_guest_mode(&svm->vcpu);
2270         svm->nested.vmcb = 0;
2271
2272         /* Give the current vmcb to the guest */
2273         disable_gif(svm);
2274
2275         nested_vmcb->save.es     = vmcb->save.es;
2276         nested_vmcb->save.cs     = vmcb->save.cs;
2277         nested_vmcb->save.ss     = vmcb->save.ss;
2278         nested_vmcb->save.ds     = vmcb->save.ds;
2279         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
2280         nested_vmcb->save.idtr   = vmcb->save.idtr;
2281         nested_vmcb->save.efer   = svm->vcpu.arch.efer;
2282         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
2283         nested_vmcb->save.cr3    = kvm_read_cr3(&svm->vcpu);
2284         nested_vmcb->save.cr2    = vmcb->save.cr2;
2285         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
2286         nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2287         nested_vmcb->save.rip    = vmcb->save.rip;
2288         nested_vmcb->save.rsp    = vmcb->save.rsp;
2289         nested_vmcb->save.rax    = vmcb->save.rax;
2290         nested_vmcb->save.dr7    = vmcb->save.dr7;
2291         nested_vmcb->save.dr6    = vmcb->save.dr6;
2292         nested_vmcb->save.cpl    = vmcb->save.cpl;
2293
2294         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
2295         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
2296         nested_vmcb->control.int_state         = vmcb->control.int_state;
2297         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
2298         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
2299         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
2300         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
2301         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
2302         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2303         nested_vmcb->control.next_rip          = vmcb->control.next_rip;
2304
2305         /*
2306          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2307          * to make sure that we do not lose injected events. So check event_inj
2308          * here and copy it to exit_int_info if it is valid.
2309          * Exit_int_info and event_inj can't be both valid because the case
2310          * below only happens on a VMRUN instruction intercept which has
2311          * no valid exit_int_info set.
2312          */
2313         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2314                 struct vmcb_control_area *nc = &nested_vmcb->control;
2315
2316                 nc->exit_int_info     = vmcb->control.event_inj;
2317                 nc->exit_int_info_err = vmcb->control.event_inj_err;
2318         }
2319
2320         nested_vmcb->control.tlb_ctl           = 0;
2321         nested_vmcb->control.event_inj         = 0;
2322         nested_vmcb->control.event_inj_err     = 0;
2323
2324         /* We always set V_INTR_MASKING and remember the old value in hflags */
2325         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2326                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2327
2328         /* Restore the original control entries */
2329         copy_vmcb_control_area(vmcb, hsave);
2330
2331         kvm_clear_exception_queue(&svm->vcpu);
2332         kvm_clear_interrupt_queue(&svm->vcpu);
2333
2334         svm->nested.nested_cr3 = 0;
2335
2336         /* Restore selected save entries */
2337         svm->vmcb->save.es = hsave->save.es;
2338         svm->vmcb->save.cs = hsave->save.cs;
2339         svm->vmcb->save.ss = hsave->save.ss;
2340         svm->vmcb->save.ds = hsave->save.ds;
2341         svm->vmcb->save.gdtr = hsave->save.gdtr;
2342         svm->vmcb->save.idtr = hsave->save.idtr;
2343         kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2344         svm_set_efer(&svm->vcpu, hsave->save.efer);
2345         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2346         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2347         if (npt_enabled) {
2348                 svm->vmcb->save.cr3 = hsave->save.cr3;
2349                 svm->vcpu.arch.cr3 = hsave->save.cr3;
2350         } else {
2351                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2352         }
2353         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2354         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2355         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2356         svm->vmcb->save.dr7 = 0;
2357         svm->vmcb->save.cpl = 0;
2358         svm->vmcb->control.exit_int_info = 0;
2359
2360         mark_all_dirty(svm->vmcb);
2361
2362         nested_svm_unmap(page);
2363
2364         nested_svm_uninit_mmu_context(&svm->vcpu);
2365         kvm_mmu_reset_context(&svm->vcpu);
2366         kvm_mmu_load(&svm->vcpu);
2367
2368         return 0;
2369 }
2370
2371 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2372 {
2373         /*
2374          * This function merges the msr permission bitmaps of kvm and the
2375          * nested vmcb. It is omptimized in that it only merges the parts where
2376          * the kvm msr permission bitmap may contain zero bits
2377          */
2378         int i;
2379
2380         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2381                 return true;
2382
2383         for (i = 0; i < MSRPM_OFFSETS; i++) {
2384                 u32 value, p;
2385                 u64 offset;
2386
2387                 if (msrpm_offsets[i] == 0xffffffff)
2388                         break;
2389
2390                 p      = msrpm_offsets[i];
2391                 offset = svm->nested.vmcb_msrpm + (p * 4);
2392
2393                 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2394                         return false;
2395
2396                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2397         }
2398
2399         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2400
2401         return true;
2402 }
2403
2404 static bool nested_vmcb_checks(struct vmcb *vmcb)
2405 {
2406         if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2407                 return false;
2408
2409         if (vmcb->control.asid == 0)
2410                 return false;
2411
2412         if (vmcb->control.nested_ctl && !npt_enabled)
2413                 return false;
2414
2415         return true;
2416 }
2417
2418 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2419 {
2420         struct vmcb *nested_vmcb;
2421         struct vmcb *hsave = svm->nested.hsave;
2422         struct vmcb *vmcb = svm->vmcb;
2423         struct page *page;
2424         u64 vmcb_gpa;
2425
2426         vmcb_gpa = svm->vmcb->save.rax;
2427
2428         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2429         if (!nested_vmcb)
2430                 return false;
2431
2432         if (!nested_vmcb_checks(nested_vmcb)) {
2433                 nested_vmcb->control.exit_code    = SVM_EXIT_ERR;
2434                 nested_vmcb->control.exit_code_hi = 0;
2435                 nested_vmcb->control.exit_info_1  = 0;
2436                 nested_vmcb->control.exit_info_2  = 0;
2437
2438                 nested_svm_unmap(page);
2439
2440                 return false;
2441         }
2442
2443         trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2444                                nested_vmcb->save.rip,
2445                                nested_vmcb->control.int_ctl,
2446                                nested_vmcb->control.event_inj,
2447                                nested_vmcb->control.nested_ctl);
2448
2449         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2450                                     nested_vmcb->control.intercept_cr >> 16,
2451                                     nested_vmcb->control.intercept_exceptions,
2452                                     nested_vmcb->control.intercept);
2453
2454         /* Clear internal status */
2455         kvm_clear_exception_queue(&svm->vcpu);
2456         kvm_clear_interrupt_queue(&svm->vcpu);
2457
2458         /*
2459          * Save the old vmcb, so we don't need to pick what we save, but can
2460          * restore everything when a VMEXIT occurs
2461          */
2462         hsave->save.es     = vmcb->save.es;
2463         hsave->save.cs     = vmcb->save.cs;
2464         hsave->save.ss     = vmcb->save.ss;
2465         hsave->save.ds     = vmcb->save.ds;
2466         hsave->save.gdtr   = vmcb->save.gdtr;
2467         hsave->save.idtr   = vmcb->save.idtr;
2468         hsave->save.efer   = svm->vcpu.arch.efer;
2469         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
2470         hsave->save.cr4    = svm->vcpu.arch.cr4;
2471         hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2472         hsave->save.rip    = kvm_rip_read(&svm->vcpu);
2473         hsave->save.rsp    = vmcb->save.rsp;
2474         hsave->save.rax    = vmcb->save.rax;
2475         if (npt_enabled)
2476                 hsave->save.cr3    = vmcb->save.cr3;
2477         else
2478                 hsave->save.cr3    = kvm_read_cr3(&svm->vcpu);
2479
2480         copy_vmcb_control_area(hsave, vmcb);
2481
2482         if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2483                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2484         else
2485                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2486
2487         if (nested_vmcb->control.nested_ctl) {
2488                 kvm_mmu_unload(&svm->vcpu);
2489                 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2490                 nested_svm_init_mmu_context(&svm->vcpu);
2491         }
2492
2493         /* Load the nested guest state */
2494         svm->vmcb->save.es = nested_vmcb->save.es;
2495         svm->vmcb->save.cs = nested_vmcb->save.cs;
2496         svm->vmcb->save.ss = nested_vmcb->save.ss;
2497         svm->vmcb->save.ds = nested_vmcb->save.ds;
2498         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2499         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2500         kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2501         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2502         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2503         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2504         if (npt_enabled) {
2505                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2506                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2507         } else
2508                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2509
2510         /* Guest paging mode is active - reset mmu */
2511         kvm_mmu_reset_context(&svm->vcpu);
2512
2513         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2514         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2515         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2516         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2517
2518         /* In case we don't even reach vcpu_run, the fields are not updated */
2519         svm->vmcb->save.rax = nested_vmcb->save.rax;
2520         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2521         svm->vmcb->save.rip = nested_vmcb->save.rip;
2522         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2523         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2524         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2525
2526         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2527         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
2528
2529         /* cache intercepts */
2530         svm->nested.intercept_cr         = nested_vmcb->control.intercept_cr;
2531         svm->nested.intercept_dr         = nested_vmcb->control.intercept_dr;
2532         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2533         svm->nested.intercept            = nested_vmcb->control.intercept;
2534
2535         svm_flush_tlb(&svm->vcpu);
2536         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2537         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2538                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2539         else
2540                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2541
2542         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2543                 /* We only want the cr8 intercept bits of the guest */
2544                 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2545                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2546         }
2547
2548         /* We don't want to see VMMCALLs from a nested guest */
2549         clr_intercept(svm, INTERCEPT_VMMCALL);
2550
2551         svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2552         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2553         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2554         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2555         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2556         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2557
2558         nested_svm_unmap(page);
2559
2560         /* Enter Guest-Mode */
2561         enter_guest_mode(&svm->vcpu);
2562
2563         /*
2564          * Merge guest and host intercepts - must be called  with vcpu in
2565          * guest-mode to take affect here
2566          */
2567         recalc_intercepts(svm);
2568
2569         svm->nested.vmcb = vmcb_gpa;
2570
2571         enable_gif(svm);
2572
2573         mark_all_dirty(svm->vmcb);
2574
2575         return true;
2576 }
2577
2578 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2579 {
2580         to_vmcb->save.fs = from_vmcb->save.fs;
2581         to_vmcb->save.gs = from_vmcb->save.gs;
2582         to_vmcb->save.tr = from_vmcb->save.tr;
2583         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2584         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2585         to_vmcb->save.star = from_vmcb->save.star;
2586         to_vmcb->save.lstar = from_vmcb->save.lstar;
2587         to_vmcb->save.cstar = from_vmcb->save.cstar;
2588         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2589         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2590         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2591         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2592 }
2593
2594 static int vmload_interception(struct vcpu_svm *svm)
2595 {
2596         struct vmcb *nested_vmcb;
2597         struct page *page;
2598
2599         if (nested_svm_check_permissions(svm))
2600                 return 1;
2601
2602         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2603         if (!nested_vmcb)
2604                 return 1;
2605
2606         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2607         skip_emulated_instruction(&svm->vcpu);
2608
2609         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2610         nested_svm_unmap(page);
2611
2612         return 1;
2613 }
2614
2615 static int vmsave_interception(struct vcpu_svm *svm)
2616 {
2617         struct vmcb *nested_vmcb;
2618         struct page *page;
2619
2620         if (nested_svm_check_permissions(svm))
2621                 return 1;
2622
2623         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2624         if (!nested_vmcb)
2625                 return 1;
2626
2627         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2628         skip_emulated_instruction(&svm->vcpu);
2629
2630         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2631         nested_svm_unmap(page);
2632
2633         return 1;
2634 }
2635
2636 static int vmrun_interception(struct vcpu_svm *svm)
2637 {
2638         if (nested_svm_check_permissions(svm))
2639                 return 1;
2640
2641         /* Save rip after vmrun instruction */
2642         kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2643
2644         if (!nested_svm_vmrun(svm))
2645                 return 1;
2646
2647         if (!nested_svm_vmrun_msrpm(svm))
2648                 goto failed;
2649
2650         return 1;
2651
2652 failed:
2653
2654         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
2655         svm->vmcb->control.exit_code_hi = 0;
2656         svm->vmcb->control.exit_info_1  = 0;
2657         svm->vmcb->control.exit_info_2  = 0;
2658
2659         nested_svm_vmexit(svm);
2660
2661         return 1;
2662 }
2663
2664 static int stgi_interception(struct vcpu_svm *svm)
2665 {
2666         if (nested_svm_check_permissions(svm))
2667                 return 1;
2668
2669         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2670         skip_emulated_instruction(&svm->vcpu);
2671         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2672
2673         enable_gif(svm);
2674
2675         return 1;
2676 }
2677
2678 static int clgi_interception(struct vcpu_svm *svm)
2679 {
2680         if (nested_svm_check_permissions(svm))
2681                 return 1;
2682
2683         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2684         skip_emulated_instruction(&svm->vcpu);
2685
2686         disable_gif(svm);
2687
2688         /* After a CLGI no interrupts should come */
2689         svm_clear_vintr(svm);
2690         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2691
2692         mark_dirty(svm->vmcb, VMCB_INTR);
2693
2694         return 1;
2695 }
2696
2697 static int invlpga_interception(struct vcpu_svm *svm)
2698 {
2699         struct kvm_vcpu *vcpu = &svm->vcpu;
2700
2701         trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2702                           vcpu->arch.regs[VCPU_REGS_RAX]);
2703
2704         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2705         kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2706
2707         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2708         skip_emulated_instruction(&svm->vcpu);
2709         return 1;
2710 }
2711
2712 static int skinit_interception(struct vcpu_svm *svm)
2713 {
2714         trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2715
2716         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2717         return 1;
2718 }
2719
2720 static int xsetbv_interception(struct vcpu_svm *svm)
2721 {
2722         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2723         u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
2724
2725         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2726                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2727                 skip_emulated_instruction(&svm->vcpu);
2728         }
2729
2730         return 1;
2731 }
2732
2733 static int invalid_op_interception(struct vcpu_svm *svm)
2734 {
2735         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2736         return 1;
2737 }
2738
2739 static int task_switch_interception(struct vcpu_svm *svm)
2740 {
2741         u16 tss_selector;
2742         int reason;
2743         int int_type = svm->vmcb->control.exit_int_info &
2744                 SVM_EXITINTINFO_TYPE_MASK;
2745         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2746         uint32_t type =
2747                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2748         uint32_t idt_v =
2749                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2750         bool has_error_code = false;
2751         u32 error_code = 0;
2752
2753         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2754
2755         if (svm->vmcb->control.exit_info_2 &
2756             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2757                 reason = TASK_SWITCH_IRET;
2758         else if (svm->vmcb->control.exit_info_2 &
2759                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2760                 reason = TASK_SWITCH_JMP;
2761         else if (idt_v)
2762                 reason = TASK_SWITCH_GATE;
2763         else
2764                 reason = TASK_SWITCH_CALL;
2765
2766         if (reason == TASK_SWITCH_GATE) {
2767                 switch (type) {
2768                 case SVM_EXITINTINFO_TYPE_NMI:
2769                         svm->vcpu.arch.nmi_injected = false;
2770                         break;
2771                 case SVM_EXITINTINFO_TYPE_EXEPT:
2772                         if (svm->vmcb->control.exit_info_2 &
2773                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2774                                 has_error_code = true;
2775                                 error_code =
2776                                         (u32)svm->vmcb->control.exit_info_2;
2777                         }
2778                         kvm_clear_exception_queue(&svm->vcpu);
2779                         break;
2780                 case SVM_EXITINTINFO_TYPE_INTR:
2781                         kvm_clear_interrupt_queue(&svm->vcpu);
2782                         break;
2783                 default:
2784                         break;
2785                 }
2786         }
2787
2788         if (reason != TASK_SWITCH_GATE ||
2789             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2790             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2791              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2792                 skip_emulated_instruction(&svm->vcpu);
2793
2794         if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2795                                 has_error_code, error_code) == EMULATE_FAIL) {
2796                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2797                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2798                 svm->vcpu.run->internal.ndata = 0;
2799                 return 0;
2800         }
2801         return 1;
2802 }
2803
2804 static int cpuid_interception(struct vcpu_svm *svm)
2805 {
2806         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2807         kvm_emulate_cpuid(&svm->vcpu);
2808         return 1;
2809 }
2810
2811 static int iret_interception(struct vcpu_svm *svm)
2812 {
2813         ++svm->vcpu.stat.nmi_window_exits;
2814         clr_intercept(svm, INTERCEPT_IRET);
2815         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2816         svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2817         return 1;
2818 }
2819
2820 static int invlpg_interception(struct vcpu_svm *svm)
2821 {
2822         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2823                 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2824
2825         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2826         skip_emulated_instruction(&svm->vcpu);
2827         return 1;
2828 }
2829
2830 static int emulate_on_interception(struct vcpu_svm *svm)
2831 {
2832         return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2833 }
2834
2835 static int rdpmc_interception(struct vcpu_svm *svm)
2836 {
2837         int err;
2838
2839         if (!static_cpu_has(X86_FEATURE_NRIPS))
2840                 return emulate_on_interception(svm);
2841
2842         err = kvm_rdpmc(&svm->vcpu);
2843         kvm_complete_insn_gp(&svm->vcpu, err);
2844
2845         return 1;
2846 }
2847
2848 bool check_selective_cr0_intercepted(struct vcpu_svm *svm, unsigned long val)
2849 {
2850         unsigned long cr0 = svm->vcpu.arch.cr0;
2851         bool ret = false;
2852         u64 intercept;
2853
2854         intercept = svm->nested.intercept;
2855
2856         if (!is_guest_mode(&svm->vcpu) ||
2857             (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
2858                 return false;
2859
2860         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2861         val &= ~SVM_CR0_SELECTIVE_MASK;
2862
2863         if (cr0 ^ val) {
2864                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2865                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2866         }
2867
2868         return ret;
2869 }
2870
2871 #define CR_VALID (1ULL << 63)
2872
2873 static int cr_interception(struct vcpu_svm *svm)
2874 {
2875         int reg, cr;
2876         unsigned long val;
2877         int err;
2878
2879         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2880                 return emulate_on_interception(svm);
2881
2882         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2883                 return emulate_on_interception(svm);
2884
2885         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2886         cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2887
2888         err = 0;
2889         if (cr >= 16) { /* mov to cr */
2890                 cr -= 16;
2891                 val = kvm_register_read(&svm->vcpu, reg);
2892                 switch (cr) {
2893                 case 0:
2894                         if (!check_selective_cr0_intercepted(svm, val))
2895                                 err = kvm_set_cr0(&svm->vcpu, val);
2896                         else
2897                                 return 1;
2898
2899                         break;
2900                 case 3:
2901                         err = kvm_set_cr3(&svm->vcpu, val);
2902                         break;
2903                 case 4:
2904                         err = kvm_set_cr4(&svm->vcpu, val);
2905                         break;
2906                 case 8:
2907                         err = kvm_set_cr8(&svm->vcpu, val);
2908                         break;
2909                 default:
2910                         WARN(1, "unhandled write to CR%d", cr);
2911                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2912                         return 1;
2913                 }
2914         } else { /* mov from cr */
2915                 switch (cr) {
2916                 case 0:
2917                         val = kvm_read_cr0(&svm->vcpu);
2918                         break;
2919                 case 2:
2920                         val = svm->vcpu.arch.cr2;
2921                         break;
2922                 case 3:
2923                         val = kvm_read_cr3(&svm->vcpu);
2924                         break;
2925                 case 4:
2926                         val = kvm_read_cr4(&svm->vcpu);
2927                         break;
2928                 case 8:
2929                         val = kvm_get_cr8(&svm->vcpu);
2930                         break;
2931                 default:
2932                         WARN(1, "unhandled read from CR%d", cr);
2933                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2934                         return 1;
2935                 }
2936                 kvm_register_write(&svm->vcpu, reg, val);
2937         }
2938         kvm_complete_insn_gp(&svm->vcpu, err);
2939
2940         return 1;
2941 }
2942
2943 static int dr_interception(struct vcpu_svm *svm)
2944 {
2945         int reg, dr;
2946         unsigned long val;
2947         int err;
2948
2949         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2950                 return emulate_on_interception(svm);
2951
2952         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2953         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2954
2955         if (dr >= 16) { /* mov to DRn */
2956                 val = kvm_register_read(&svm->vcpu, reg);
2957                 kvm_set_dr(&svm->vcpu, dr - 16, val);
2958         } else {
2959                 err = kvm_get_dr(&svm->vcpu, dr, &val);
2960                 if (!err)
2961                         kvm_register_write(&svm->vcpu, reg, val);
2962         }
2963
2964         skip_emulated_instruction(&svm->vcpu);
2965
2966         return 1;
2967 }
2968
2969 static int cr8_write_interception(struct vcpu_svm *svm)
2970 {
2971         struct kvm_run *kvm_run = svm->vcpu.run;
2972         int r;
2973
2974         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2975         /* instruction emulation calls kvm_set_cr8() */
2976         r = cr_interception(svm);
2977         if (irqchip_in_kernel(svm->vcpu.kvm)) {
2978                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2979                 return r;
2980         }
2981         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2982                 return r;
2983         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2984         return 0;
2985 }
2986
2987 u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu)
2988 {
2989         struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu));
2990         return vmcb->control.tsc_offset +
2991                 svm_scale_tsc(vcpu, native_read_tsc());
2992 }
2993
2994 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2995 {
2996         struct vcpu_svm *svm = to_svm(vcpu);
2997
2998         switch (ecx) {
2999         case MSR_IA32_TSC: {
3000                 *data = svm->vmcb->control.tsc_offset +
3001                         svm_scale_tsc(vcpu, native_read_tsc());
3002
3003                 break;
3004         }
3005         case MSR_STAR:
3006                 *data = svm->vmcb->save.star;
3007                 break;
3008 #ifdef CONFIG_X86_64
3009         case MSR_LSTAR:
3010                 *data = svm->vmcb->save.lstar;
3011                 break;
3012         case MSR_CSTAR:
3013                 *data = svm->vmcb->save.cstar;
3014                 break;
3015         case MSR_KERNEL_GS_BASE:
3016                 *data = svm->vmcb->save.kernel_gs_base;
3017                 break;
3018         case MSR_SYSCALL_MASK:
3019                 *data = svm->vmcb->save.sfmask;
3020                 break;
3021 #endif
3022         case MSR_IA32_SYSENTER_CS:
3023                 *data = svm->vmcb->save.sysenter_cs;
3024                 break;
3025         case MSR_IA32_SYSENTER_EIP:
3026                 *data = svm->sysenter_eip;
3027                 break;
3028         case MSR_IA32_SYSENTER_ESP:
3029                 *data = svm->sysenter_esp;
3030                 break;
3031         /*
3032          * Nobody will change the following 5 values in the VMCB so we can
3033          * safely return them on rdmsr. They will always be 0 until LBRV is
3034          * implemented.
3035          */
3036         case MSR_IA32_DEBUGCTLMSR:
3037                 *data = svm->vmcb->save.dbgctl;
3038                 break;
3039         case MSR_IA32_LASTBRANCHFROMIP:
3040                 *data = svm->vmcb->save.br_from;
3041                 break;
3042         case MSR_IA32_LASTBRANCHTOIP:
3043                 *data = svm->vmcb->save.br_to;
3044                 break;
3045         case MSR_IA32_LASTINTFROMIP:
3046                 *data = svm->vmcb->save.last_excp_from;
3047                 break;
3048         case MSR_IA32_LASTINTTOIP:
3049                 *data = svm->vmcb->save.last_excp_to;
3050                 break;
3051         case MSR_VM_HSAVE_PA:
3052                 *data = svm->nested.hsave_msr;
3053                 break;
3054         case MSR_VM_CR:
3055                 *data = svm->nested.vm_cr_msr;
3056                 break;
3057         case MSR_IA32_UCODE_REV:
3058                 *data = 0x01000065;
3059                 break;
3060         default:
3061                 return kvm_get_msr_common(vcpu, ecx, data);
3062         }
3063         return 0;
3064 }
3065
3066 static int rdmsr_interception(struct vcpu_svm *svm)
3067 {
3068         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3069         u64 data;
3070
3071         if (svm_get_msr(&svm->vcpu, ecx, &data)) {
3072                 trace_kvm_msr_read_ex(ecx);
3073                 kvm_inject_gp(&svm->vcpu, 0);
3074         } else {
3075                 trace_kvm_msr_read(ecx, data);
3076
3077                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
3078                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
3079                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3080                 skip_emulated_instruction(&svm->vcpu);
3081         }
3082         return 1;
3083 }
3084
3085 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3086 {
3087         struct vcpu_svm *svm = to_svm(vcpu);
3088         int svm_dis, chg_mask;
3089
3090         if (data & ~SVM_VM_CR_VALID_MASK)
3091                 return 1;
3092
3093         chg_mask = SVM_VM_CR_VALID_MASK;
3094
3095         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3096                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3097
3098         svm->nested.vm_cr_msr &= ~chg_mask;
3099         svm->nested.vm_cr_msr |= (data & chg_mask);
3100
3101         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3102
3103         /* check for svm_disable while efer.svme is set */
3104         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3105                 return 1;
3106
3107         return 0;
3108 }
3109
3110 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
3111 {
3112         struct vcpu_svm *svm = to_svm(vcpu);
3113
3114         switch (ecx) {
3115         case MSR_IA32_TSC:
3116                 kvm_write_tsc(vcpu, data);
3117                 break;
3118         case MSR_STAR:
3119                 svm->vmcb->save.star = data;
3120                 break;
3121 #ifdef CONFIG_X86_64
3122         case MSR_LSTAR:
3123                 svm->vmcb->save.lstar = data;
3124                 break;
3125         case MSR_CSTAR:
3126                 svm->vmcb->save.cstar = data;
3127                 break;
3128         case MSR_KERNEL_GS_BASE:
3129                 svm->vmcb->save.kernel_gs_base = data;
3130                 break;
3131         case MSR_SYSCALL_MASK:
3132                 svm->vmcb->save.sfmask = data;
3133                 break;
3134 #endif
3135         case MSR_IA32_SYSENTER_CS:
3136                 svm->vmcb->save.sysenter_cs = data;
3137                 break;
3138         case MSR_IA32_SYSENTER_EIP:
3139                 svm->sysenter_eip = data;
3140                 svm->vmcb->save.sysenter_eip = data;
3141                 break;
3142         case MSR_IA32_SYSENTER_ESP:
3143                 svm->sysenter_esp = data;
3144                 svm->vmcb->save.sysenter_esp = data;
3145                 break;
3146         case MSR_IA32_DEBUGCTLMSR:
3147                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3148                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3149                                         __func__, data);
3150                         break;
3151                 }
3152                 if (data & DEBUGCTL_RESERVED_BITS)
3153                         return 1;
3154
3155                 svm->vmcb->save.dbgctl = data;
3156                 mark_dirty(svm->vmcb, VMCB_LBR);
3157                 if (data & (1ULL<<0))
3158                         svm_enable_lbrv(svm);
3159                 else
3160                         svm_disable_lbrv(svm);
3161                 break;
3162         case MSR_VM_HSAVE_PA:
3163                 svm->nested.hsave_msr = data;
3164                 break;
3165         case MSR_VM_CR:
3166                 return svm_set_vm_cr(vcpu, data);
3167         case MSR_VM_IGNNE:
3168                 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3169                 break;
3170         default:
3171                 return kvm_set_msr_common(vcpu, ecx, data);
3172         }
3173         return 0;
3174 }
3175
3176 static int wrmsr_interception(struct vcpu_svm *svm)
3177 {
3178         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3179         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
3180                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3181
3182
3183         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3184         if (svm_set_msr(&svm->vcpu, ecx, data)) {
3185                 trace_kvm_msr_write_ex(ecx, data);
3186                 kvm_inject_gp(&svm->vcpu, 0);
3187         } else {
3188                 trace_kvm_msr_write(ecx, data);
3189                 skip_emulated_instruction(&svm->vcpu);
3190         }
3191         return 1;
3192 }
3193
3194 static int msr_interception(struct vcpu_svm *svm)
3195 {
3196         if (svm->vmcb->control.exit_info_1)
3197                 return wrmsr_interception(svm);
3198         else
3199                 return rdmsr_interception(svm);
3200 }
3201
3202 static int interrupt_window_interception(struct vcpu_svm *svm)
3203 {
3204         struct kvm_run *kvm_run = svm->vcpu.run;
3205
3206         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3207         svm_clear_vintr(svm);
3208         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3209         mark_dirty(svm->vmcb, VMCB_INTR);
3210         /*
3211          * If the user space waits to inject interrupts, exit as soon as
3212          * possible
3213          */
3214         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
3215             kvm_run->request_interrupt_window &&
3216             !kvm_cpu_has_interrupt(&svm->vcpu)) {
3217                 ++svm->vcpu.stat.irq_window_exits;
3218                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3219                 return 0;
3220         }
3221
3222         return 1;
3223 }
3224
3225 static int pause_interception(struct vcpu_svm *svm)
3226 {
3227         kvm_vcpu_on_spin(&(svm->vcpu));
3228         return 1;
3229 }
3230
3231 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
3232         [SVM_EXIT_READ_CR0]                     = cr_interception,
3233         [SVM_EXIT_READ_CR3]                     = cr_interception,
3234         [SVM_EXIT_READ_CR4]                     = cr_interception,
3235         [SVM_EXIT_READ_CR8]                     = cr_interception,
3236         [SVM_EXIT_CR0_SEL_WRITE]                = emulate_on_interception,
3237         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
3238         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
3239         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
3240         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
3241         [SVM_EXIT_READ_DR0]                     = dr_interception,
3242         [SVM_EXIT_READ_DR1]                     = dr_interception,
3243         [SVM_EXIT_READ_DR2]                     = dr_interception,
3244         [SVM_EXIT_READ_DR3]                     = dr_interception,
3245         [SVM_EXIT_READ_DR4]                     = dr_interception,
3246         [SVM_EXIT_READ_DR5]                     = dr_interception,
3247         [SVM_EXIT_READ_DR6]                     = dr_interception,
3248         [SVM_EXIT_READ_DR7]                     = dr_interception,
3249         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
3250         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
3251         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
3252         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
3253         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
3254         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
3255         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
3256         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
3257         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
3258         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
3259         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
3260         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
3261         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
3262         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
3263         [SVM_EXIT_INTR]                         = intr_interception,
3264         [SVM_EXIT_NMI]                          = nmi_interception,
3265         [SVM_EXIT_SMI]                          = nop_on_interception,
3266         [SVM_EXIT_INIT]                         = nop_on_interception,
3267         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
3268         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
3269         [SVM_EXIT_CPUID]                        = cpuid_interception,
3270         [SVM_EXIT_IRET]                         = iret_interception,
3271         [SVM_EXIT_INVD]                         = emulate_on_interception,
3272         [SVM_EXIT_PAUSE]                        = pause_interception,
3273         [SVM_EXIT_HLT]                          = halt_interception,
3274         [SVM_EXIT_INVLPG]                       = invlpg_interception,
3275         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
3276         [SVM_EXIT_IOIO]                         = io_interception,
3277         [SVM_EXIT_MSR]                          = msr_interception,
3278         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
3279         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
3280         [SVM_EXIT_VMRUN]                        = vmrun_interception,
3281         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
3282         [SVM_EXIT_VMLOAD]                       = vmload_interception,
3283         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
3284         [SVM_EXIT_STGI]                         = stgi_interception,
3285         [SVM_EXIT_CLGI]                         = clgi_interception,
3286         [SVM_EXIT_SKINIT]                       = skinit_interception,
3287         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
3288         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
3289         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
3290         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
3291         [SVM_EXIT_NPF]                          = pf_interception,
3292 };
3293
3294 static void dump_vmcb(struct kvm_vcpu *vcpu)
3295 {
3296         struct vcpu_svm *svm = to_svm(vcpu);
3297         struct vmcb_control_area *control = &svm->vmcb->control;
3298         struct vmcb_save_area *save = &svm->vmcb->save;
3299
3300         pr_err("VMCB Control Area:\n");
3301         pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
3302         pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
3303         pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
3304         pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
3305         pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
3306         pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
3307         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3308         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3309         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3310         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3311         pr_err("%-20s%d\n", "asid:", control->asid);
3312         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3313         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3314         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3315         pr_err("%-20s%08x\n", "int_state:", control->int_state);
3316         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3317         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3318         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3319         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3320         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3321         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3322         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3323         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3324         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3325         pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
3326         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3327         pr_err("VMCB State Save Area:\n");
3328         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3329                "es:",
3330                save->es.selector, save->es.attrib,
3331                save->es.limit, save->es.base);
3332         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3333                "cs:",
3334                save->cs.selector, save->cs.attrib,
3335                save->cs.limit, save->cs.base);
3336         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3337                "ss:",
3338                save->ss.selector, save->ss.attrib,
3339                save->ss.limit, save->ss.base);
3340         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3341                "ds:",
3342                save->ds.selector, save->ds.attrib,
3343                save->ds.limit, save->ds.base);
3344         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3345                "fs:",
3346                save->fs.selector, save->fs.attrib,
3347                save->fs.limit, save->fs.base);
3348         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3349                "gs:",
3350                save->gs.selector, save->gs.attrib,
3351                save->gs.limit, save->gs.base);
3352         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3353                "gdtr:",
3354                save->gdtr.selector, save->gdtr.attrib,
3355                save->gdtr.limit, save->gdtr.base);
3356         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3357                "ldtr:",
3358                save->ldtr.selector, save->ldtr.attrib,
3359                save->ldtr.limit, save->ldtr.base);
3360         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3361                "idtr:",
3362                save->idtr.selector, save->idtr.attrib,
3363                save->idtr.limit, save->idtr.base);
3364         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3365                "tr:",
3366                save->tr.selector, save->tr.attrib,
3367                save->tr.limit, save->tr.base);
3368         pr_err("cpl:            %d                efer:         %016llx\n",
3369                 save->cpl, save->efer);
3370         pr_err("%-15s %016llx %-13s %016llx\n",
3371                "cr0:", save->cr0, "cr2:", save->cr2);
3372         pr_err("%-15s %016llx %-13s %016llx\n",
3373                "cr3:", save->cr3, "cr4:", save->cr4);
3374         pr_err("%-15s %016llx %-13s %016llx\n",
3375                "dr6:", save->dr6, "dr7:", save->dr7);
3376         pr_err("%-15s %016llx %-13s %016llx\n",
3377                "rip:", save->rip, "rflags:", save->rflags);
3378         pr_err("%-15s %016llx %-13s %016llx\n",
3379                "rsp:", save->rsp, "rax:", save->rax);
3380         pr_err("%-15s %016llx %-13s %016llx\n",
3381                "star:", save->star, "lstar:", save->lstar);
3382         pr_err("%-15s %016llx %-13s %016llx\n",
3383                "cstar:", save->cstar, "sfmask:", save->sfmask);
3384         pr_err("%-15s %016llx %-13s %016llx\n",
3385                "kernel_gs_base:", save->kernel_gs_base,
3386                "sysenter_cs:", save->sysenter_cs);
3387         pr_err("%-15s %016llx %-13s %016llx\n",
3388                "sysenter_esp:", save->sysenter_esp,
3389                "sysenter_eip:", save->sysenter_eip);
3390         pr_err("%-15s %016llx %-13s %016llx\n",
3391                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3392         pr_err("%-15s %016llx %-13s %016llx\n",
3393                "br_from:", save->br_from, "br_to:", save->br_to);
3394         pr_err("%-15s %016llx %-13s %016llx\n",
3395                "excp_from:", save->last_excp_from,
3396                "excp_to:", save->last_excp_to);
3397 }
3398
3399 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3400 {
3401         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3402
3403         *info1 = control->exit_info_1;
3404         *info2 = control->exit_info_2;
3405 }
3406
3407 static int handle_exit(struct kvm_vcpu *vcpu)
3408 {
3409         struct vcpu_svm *svm = to_svm(vcpu);
3410         struct kvm_run *kvm_run = vcpu->run;
3411         u32 exit_code = svm->vmcb->control.exit_code;
3412
3413         if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3414                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3415         if (npt_enabled)
3416                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3417
3418         if (unlikely(svm->nested.exit_required)) {
3419                 nested_svm_vmexit(svm);
3420                 svm->nested.exit_required = false;
3421
3422                 return 1;
3423         }
3424
3425         if (is_guest_mode(vcpu)) {
3426                 int vmexit;
3427
3428                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3429                                         svm->vmcb->control.exit_info_1,
3430                                         svm->vmcb->control.exit_info_2,
3431                                         svm->vmcb->control.exit_int_info,
3432                                         svm->vmcb->control.exit_int_info_err,
3433                                         KVM_ISA_SVM);
3434
3435                 vmexit = nested_svm_exit_special(svm);
3436
3437                 if (vmexit == NESTED_EXIT_CONTINUE)
3438                         vmexit = nested_svm_exit_handled(svm);
3439
3440                 if (vmexit == NESTED_EXIT_DONE)
3441                         return 1;
3442         }
3443
3444         svm_complete_interrupts(svm);
3445
3446         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3447                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3448                 kvm_run->fail_entry.hardware_entry_failure_reason
3449                         = svm->vmcb->control.exit_code;
3450                 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3451                 dump_vmcb(vcpu);
3452                 return 0;
3453         }
3454
3455         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3456             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3457             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3458             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3459                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3460                        "exit_code 0x%x\n",
3461                        __func__, svm->vmcb->control.exit_int_info,
3462                        exit_code);
3463
3464         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3465             || !svm_exit_handlers[exit_code]) {
3466                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3467                 kvm_run->hw.hardware_exit_reason = exit_code;
3468                 return 0;
3469         }
3470
3471         return svm_exit_handlers[exit_code](svm);
3472 }
3473
3474 static void reload_tss(struct kvm_vcpu *vcpu)
3475 {
3476         int cpu = raw_smp_processor_id();
3477
3478         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3479         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3480         load_TR_desc();
3481 }
3482
3483 static void pre_svm_run(struct vcpu_svm *svm)
3484 {
3485         int cpu = raw_smp_processor_id();
3486
3487         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3488
3489         /* FIXME: handle wraparound of asid_generation */
3490         if (svm->asid_generation != sd->asid_generation)
3491                 new_asid(svm, sd);
3492 }
3493
3494 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3495 {
3496         struct vcpu_svm *svm = to_svm(vcpu);
3497
3498         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3499         vcpu->arch.hflags |= HF_NMI_MASK;
3500         set_intercept(svm, INTERCEPT_IRET);
3501         ++vcpu->stat.nmi_injections;
3502 }
3503
3504 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3505 {
3506         struct vmcb_control_area *control;
3507
3508         control = &svm->vmcb->control;
3509         control->int_vector = irq;
3510         control->int_ctl &= ~V_INTR_PRIO_MASK;
3511         control->int_ctl |= V_IRQ_MASK |
3512                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3513         mark_dirty(svm->vmcb, VMCB_INTR);
3514 }
3515
3516 static void svm_set_irq(struct kvm_vcpu *vcpu)
3517 {
3518         struct vcpu_svm *svm = to_svm(vcpu);
3519
3520         BUG_ON(!(gif_set(svm)));
3521
3522         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3523         ++vcpu->stat.irq_injections;
3524
3525         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3526                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3527 }
3528
3529 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3530 {
3531         struct vcpu_svm *svm = to_svm(vcpu);
3532
3533         if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3534                 return;
3535
3536         if (irr == -1)
3537                 return;
3538
3539         if (tpr >= irr)
3540                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3541 }
3542
3543 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3544 {
3545         struct vcpu_svm *svm = to_svm(vcpu);
3546         struct vmcb *vmcb = svm->vmcb;
3547         int ret;
3548         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3549               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3550         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3551
3552         return ret;
3553 }
3554
3555 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3556 {
3557         struct vcpu_svm *svm = to_svm(vcpu);
3558
3559         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3560 }
3561
3562 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3563 {
3564         struct vcpu_svm *svm = to_svm(vcpu);
3565
3566         if (masked) {
3567                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3568                 set_intercept(svm, INTERCEPT_IRET);
3569         } else {
3570                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3571                 clr_intercept(svm, INTERCEPT_IRET);
3572         }
3573 }
3574
3575 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3576 {
3577         struct vcpu_svm *svm = to_svm(vcpu);
3578         struct vmcb *vmcb = svm->vmcb;
3579         int ret;
3580
3581         if (!gif_set(svm) ||
3582              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3583                 return 0;
3584
3585         ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
3586
3587         if (is_guest_mode(vcpu))
3588                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3589
3590         return ret;
3591 }
3592
3593 static void enable_irq_window(struct kvm_vcpu *vcpu)
3594 {
3595         struct vcpu_svm *svm = to_svm(vcpu);
3596
3597         /*
3598          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3599          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
3600          * get that intercept, this function will be called again though and
3601          * we'll get the vintr intercept.
3602          */
3603         if (gif_set(svm) && nested_svm_intr(svm)) {
3604                 svm_set_vintr(svm);
3605                 svm_inject_irq(svm, 0x0);
3606         }
3607 }
3608
3609 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3610 {
3611         struct vcpu_svm *svm = to_svm(vcpu);
3612
3613         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3614             == HF_NMI_MASK)
3615                 return; /* IRET will cause a vm exit */
3616
3617         /*
3618          * Something prevents NMI from been injected. Single step over possible
3619          * problem (IRET or exception injection or interrupt shadow)
3620          */
3621         svm->nmi_singlestep = true;
3622         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3623         update_db_intercept(vcpu);
3624 }
3625
3626 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3627 {
3628         return 0;
3629 }
3630
3631 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3632 {
3633         struct vcpu_svm *svm = to_svm(vcpu);
3634
3635         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3636                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3637         else
3638                 svm->asid_generation--;
3639 }
3640
3641 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3642 {
3643 }
3644
3645 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3646 {
3647         struct vcpu_svm *svm = to_svm(vcpu);
3648
3649         if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3650                 return;
3651
3652         if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3653                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3654                 kvm_set_cr8(vcpu, cr8);
3655         }
3656 }
3657
3658 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3659 {
3660         struct vcpu_svm *svm = to_svm(vcpu);
3661         u64 cr8;
3662
3663         if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3664                 return;
3665
3666         cr8 = kvm_get_cr8(vcpu);
3667         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3668         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3669 }
3670
3671 static void svm_complete_interrupts(struct vcpu_svm *svm)
3672 {
3673         u8 vector;
3674         int type;
3675         u32 exitintinfo = svm->vmcb->control.exit_int_info;
3676         unsigned int3_injected = svm->int3_injected;
3677
3678         svm->int3_injected = 0;
3679
3680         /*
3681          * If we've made progress since setting HF_IRET_MASK, we've
3682          * executed an IRET and can allow NMI injection.
3683          */
3684         if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3685             && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3686                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3687                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3688         }
3689
3690         svm->vcpu.arch.nmi_injected = false;
3691         kvm_clear_exception_queue(&svm->vcpu);
3692         kvm_clear_interrupt_queue(&svm->vcpu);
3693
3694         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3695                 return;
3696
3697         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3698
3699         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3700         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3701
3702         switch (type) {
3703         case SVM_EXITINTINFO_TYPE_NMI:
3704                 svm->vcpu.arch.nmi_injected = true;
3705                 break;
3706         case SVM_EXITINTINFO_TYPE_EXEPT:
3707                 /*
3708                  * In case of software exceptions, do not reinject the vector,
3709                  * but re-execute the instruction instead. Rewind RIP first
3710                  * if we emulated INT3 before.
3711                  */
3712                 if (kvm_exception_is_soft(vector)) {
3713                         if (vector == BP_VECTOR && int3_injected &&
3714                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3715                                 kvm_rip_write(&svm->vcpu,
3716                                               kvm_rip_read(&svm->vcpu) -
3717                                               int3_injected);
3718                         break;
3719                 }
3720                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3721                         u32 err = svm->vmcb->control.exit_int_info_err;
3722                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
3723
3724                 } else
3725                         kvm_requeue_exception(&svm->vcpu, vector);
3726                 break;
3727         case SVM_EXITINTINFO_TYPE_INTR:
3728                 kvm_queue_interrupt(&svm->vcpu, vector, false);
3729                 break;
3730         default:
3731                 break;
3732         }
3733 }
3734
3735 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3736 {
3737         struct vcpu_svm *svm = to_svm(vcpu);
3738         struct vmcb_control_area *control = &svm->vmcb->control;
3739
3740         control->exit_int_info = control->event_inj;
3741         control->exit_int_info_err = control->event_inj_err;
3742         control->event_inj = 0;
3743         svm_complete_interrupts(svm);
3744 }
3745
3746 #ifdef CONFIG_X86_64
3747 #define R "r"
3748 #else
3749 #define R "e"
3750 #endif
3751
3752 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3753 {
3754         struct vcpu_svm *svm = to_svm(vcpu);
3755
3756         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3757         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3758         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3759
3760         /*
3761          * A vmexit emulation is required before the vcpu can be executed
3762          * again.
3763          */
3764         if (unlikely(svm->nested.exit_required))
3765                 return;
3766
3767         pre_svm_run(svm);
3768
3769         sync_lapic_to_cr8(vcpu);
3770
3771         svm->vmcb->save.cr2 = vcpu->arch.cr2;
3772
3773         clgi();
3774
3775         local_irq_enable();
3776
3777         asm volatile (
3778                 "push %%"R"bp; \n\t"
3779                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3780                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3781                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3782                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3783                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3784                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3785 #ifdef CONFIG_X86_64
3786                 "mov %c[r8](%[svm]),  %%r8  \n\t"
3787                 "mov %c[r9](%[svm]),  %%r9  \n\t"
3788                 "mov %c[r10](%[svm]), %%r10 \n\t"
3789                 "mov %c[r11](%[svm]), %%r11 \n\t"
3790                 "mov %c[r12](%[svm]), %%r12 \n\t"
3791                 "mov %c[r13](%[svm]), %%r13 \n\t"
3792                 "mov %c[r14](%[svm]), %%r14 \n\t"
3793                 "mov %c[r15](%[svm]), %%r15 \n\t"
3794 #endif
3795
3796                 /* Enter guest mode */
3797                 "push %%"R"ax \n\t"
3798                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3799                 __ex(SVM_VMLOAD) "\n\t"
3800                 __ex(SVM_VMRUN) "\n\t"
3801                 __ex(SVM_VMSAVE) "\n\t"
3802                 "pop %%"R"ax \n\t"
3803
3804                 /* Save guest registers, load host registers */
3805                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3806                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3807                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3808                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3809                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3810                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3811 #ifdef CONFIG_X86_64
3812                 "mov %%r8,  %c[r8](%[svm]) \n\t"
3813                 "mov %%r9,  %c[r9](%[svm]) \n\t"
3814                 "mov %%r10, %c[r10](%[svm]) \n\t"
3815                 "mov %%r11, %c[r11](%[svm]) \n\t"
3816                 "mov %%r12, %c[r12](%[svm]) \n\t"
3817                 "mov %%r13, %c[r13](%[svm]) \n\t"
3818                 "mov %%r14, %c[r14](%[svm]) \n\t"
3819                 "mov %%r15, %c[r15](%[svm]) \n\t"
3820 #endif
3821                 "pop %%"R"bp"
3822                 :
3823                 : [svm]"a"(svm),
3824                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3825                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3826                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3827                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3828                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3829                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3830                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3831 #ifdef CONFIG_X86_64
3832                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3833                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3834                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3835                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3836                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3837                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3838                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3839                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3840 #endif
3841                 : "cc", "memory"
3842                 , R"bx", R"cx", R"dx", R"si", R"di"
3843 #ifdef CONFIG_X86_64
3844                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3845 #endif
3846                 );
3847
3848 #ifdef CONFIG_X86_64
3849         wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3850 #else
3851         loadsegment(fs, svm->host.fs);
3852 #ifndef CONFIG_X86_32_LAZY_GS
3853         loadsegment(gs, svm->host.gs);
3854 #endif
3855 #endif
3856
3857         reload_tss(vcpu);
3858
3859         local_irq_disable();
3860
3861         vcpu->arch.cr2 = svm->vmcb->save.cr2;
3862         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3863         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3864         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3865
3866         trace_kvm_exit(svm->vmcb->control.exit_code, vcpu, KVM_ISA_SVM);
3867
3868         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3869                 kvm_before_handle_nmi(&svm->vcpu);
3870
3871         stgi();
3872
3873         /* Any pending NMI will happen here */
3874
3875         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3876                 kvm_after_handle_nmi(&svm->vcpu);
3877
3878         sync_cr8_to_lapic(vcpu);
3879
3880         svm->next_rip = 0;
3881
3882         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3883
3884         /* if exit due to PF check for async PF */
3885         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3886                 svm->apf_reason = kvm_read_and_reset_pf_reason();
3887
3888         if (npt_enabled) {
3889                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3890                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3891         }
3892
3893         /*
3894          * We need to handle MC intercepts here before the vcpu has a chance to
3895          * change the physical cpu
3896          */
3897         if (unlikely(svm->vmcb->control.exit_code ==
3898                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
3899                 svm_handle_mce(svm);
3900
3901         mark_all_clean(svm->vmcb);
3902 }
3903
3904 #undef R
3905
3906 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3907 {
3908         struct vcpu_svm *svm = to_svm(vcpu);
3909
3910         svm->vmcb->save.cr3 = root;
3911         mark_dirty(svm->vmcb, VMCB_CR);
3912         svm_flush_tlb(vcpu);
3913 }
3914
3915 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3916 {
3917         struct vcpu_svm *svm = to_svm(vcpu);
3918
3919         svm->vmcb->control.nested_cr3 = root;
3920         mark_dirty(svm->vmcb, VMCB_NPT);
3921
3922         /* Also sync guest cr3 here in case we live migrate */
3923         svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
3924         mark_dirty(svm->vmcb, VMCB_CR);
3925
3926         svm_flush_tlb(vcpu);
3927 }
3928
3929 static int is_disabled(void)
3930 {
3931         u64 vm_cr;
3932
3933         rdmsrl(MSR_VM_CR, vm_cr);
3934         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3935                 return 1;
3936
3937         return 0;
3938 }
3939
3940 static void
3941 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3942 {
3943         /*
3944          * Patch in the VMMCALL instruction:
3945          */
3946         hypercall[0] = 0x0f;
3947         hypercall[1] = 0x01;
3948         hypercall[2] = 0xd9;
3949 }
3950
3951 static void svm_check_processor_compat(void *rtn)
3952 {
3953         *(int *)rtn = 0;
3954 }
3955
3956 static bool svm_cpu_has_accelerated_tpr(void)
3957 {
3958         return false;
3959 }
3960
3961 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3962 {
3963         return 0;
3964 }
3965
3966 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3967 {
3968 }
3969
3970 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3971 {
3972         switch (func) {
3973         case 0x80000001:
3974                 if (nested)
3975                         entry->ecx |= (1 << 2); /* Set SVM bit */
3976                 break;
3977         case 0x8000000A:
3978                 entry->eax = 1; /* SVM revision 1 */
3979                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3980                                    ASID emulation to nested SVM */
3981                 entry->ecx = 0; /* Reserved */
3982                 entry->edx = 0; /* Per default do not support any
3983                                    additional features */
3984
3985                 /* Support next_rip if host supports it */
3986                 if (boot_cpu_has(X86_FEATURE_NRIPS))
3987                         entry->edx |= SVM_FEATURE_NRIP;
3988
3989                 /* Support NPT for the guest if enabled */
3990                 if (npt_enabled)
3991                         entry->edx |= SVM_FEATURE_NPT;
3992
3993                 break;
3994         }
3995 }
3996
3997 static int svm_get_lpage_level(void)
3998 {
3999         return PT_PDPE_LEVEL;
4000 }
4001
4002 static bool svm_rdtscp_supported(void)
4003 {
4004         return false;
4005 }
4006
4007 static bool svm_has_wbinvd_exit(void)
4008 {
4009         return true;
4010 }
4011
4012 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
4013 {
4014         struct vcpu_svm *svm = to_svm(vcpu);
4015
4016         set_exception_intercept(svm, NM_VECTOR);
4017         update_cr0_intercept(svm);
4018 }
4019
4020 #define PRE_EX(exit)  { .exit_code = (exit), \
4021                         .stage = X86_ICPT_PRE_EXCEPT, }
4022 #define POST_EX(exit) { .exit_code = (exit), \
4023                         .stage = X86_ICPT_POST_EXCEPT, }
4024 #define POST_MEM(exit) { .exit_code = (exit), \
4025                         .stage = X86_ICPT_POST_MEMACCESS, }
4026
4027 static struct __x86_intercept {
4028         u32 exit_code;
4029         enum x86_intercept_stage stage;
4030 } x86_intercept_map[] = {
4031         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
4032         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
4033         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
4034         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
4035         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
4036         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
4037         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
4038         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
4039         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
4040         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
4041         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
4042         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
4043         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
4044         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
4045         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
4046         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
4047         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
4048         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
4049         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
4050         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
4051         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
4052         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
4053         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
4054         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
4055         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
4056         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
4057         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
4058         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
4059         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
4060         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
4061         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
4062         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
4063         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
4064         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
4065         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
4066         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
4067         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
4068         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
4069         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
4070         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
4071         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
4072         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
4073         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
4074         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
4075         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
4076         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
4077 };
4078
4079 #undef PRE_EX
4080 #undef POST_EX
4081 #undef POST_MEM
4082
4083 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4084                                struct x86_instruction_info *info,
4085                                enum x86_intercept_stage stage)
4086 {
4087         struct vcpu_svm *svm = to_svm(vcpu);
4088         int vmexit, ret = X86EMUL_CONTINUE;
4089         struct __x86_intercept icpt_info;
4090         struct vmcb *vmcb = svm->vmcb;
4091
4092         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4093                 goto out;
4094
4095         icpt_info = x86_intercept_map[info->intercept];
4096
4097         if (stage != icpt_info.stage)
4098                 goto out;
4099
4100         switch (icpt_info.exit_code) {
4101         case SVM_EXIT_READ_CR0:
4102                 if (info->intercept == x86_intercept_cr_read)
4103                         icpt_info.exit_code += info->modrm_reg;
4104                 break;
4105         case SVM_EXIT_WRITE_CR0: {
4106                 unsigned long cr0, val;
4107                 u64 intercept;
4108
4109                 if (info->intercept == x86_intercept_cr_write)
4110                         icpt_info.exit_code += info->modrm_reg;
4111
4112                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0)
4113                         break;
4114
4115                 intercept = svm->nested.intercept;
4116
4117                 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
4118                         break;
4119
4120                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4121                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
4122
4123                 if (info->intercept == x86_intercept_lmsw) {
4124                         cr0 &= 0xfUL;
4125                         val &= 0xfUL;
4126                         /* lmsw can't clear PE - catch this here */
4127                         if (cr0 & X86_CR0_PE)
4128                                 val |= X86_CR0_PE;
4129                 }
4130
4131                 if (cr0 ^ val)
4132                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4133
4134                 break;
4135         }
4136         case SVM_EXIT_READ_DR0:
4137         case SVM_EXIT_WRITE_DR0:
4138                 icpt_info.exit_code += info->modrm_reg;
4139                 break;
4140         case SVM_EXIT_MSR:
4141                 if (info->intercept == x86_intercept_wrmsr)
4142                         vmcb->control.exit_info_1 = 1;
4143                 else
4144                         vmcb->control.exit_info_1 = 0;
4145                 break;
4146         case SVM_EXIT_PAUSE:
4147                 /*
4148                  * We get this for NOP only, but pause
4149                  * is rep not, check this here
4150                  */
4151                 if (info->rep_prefix != REPE_PREFIX)
4152                         goto out;
4153         case SVM_EXIT_IOIO: {
4154                 u64 exit_info;
4155                 u32 bytes;
4156
4157                 exit_info = (vcpu->arch.regs[VCPU_REGS_RDX] & 0xffff) << 16;
4158
4159                 if (info->intercept == x86_intercept_in ||
4160                     info->intercept == x86_intercept_ins) {
4161                         exit_info |= SVM_IOIO_TYPE_MASK;
4162                         bytes = info->src_bytes;
4163                 } else {
4164                         bytes = info->dst_bytes;
4165                 }
4166
4167                 if (info->intercept == x86_intercept_outs ||
4168                     info->intercept == x86_intercept_ins)
4169                         exit_info |= SVM_IOIO_STR_MASK;
4170
4171                 if (info->rep_prefix)
4172                         exit_info |= SVM_IOIO_REP_MASK;
4173
4174                 bytes = min(bytes, 4u);
4175
4176                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4177
4178                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4179
4180                 vmcb->control.exit_info_1 = exit_info;
4181                 vmcb->control.exit_info_2 = info->next_rip;
4182
4183                 break;
4184         }
4185         default:
4186                 break;
4187         }
4188
4189         vmcb->control.next_rip  = info->next_rip;
4190         vmcb->control.exit_code = icpt_info.exit_code;
4191         vmexit = nested_svm_exit_handled(svm);
4192
4193         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4194                                            : X86EMUL_CONTINUE;
4195
4196 out:
4197         return ret;
4198 }
4199
4200 static struct kvm_x86_ops svm_x86_ops = {
4201         .cpu_has_kvm_support = has_svm,
4202         .disabled_by_bios = is_disabled,
4203         .hardware_setup = svm_hardware_setup,
4204         .hardware_unsetup = svm_hardware_unsetup,
4205         .check_processor_compatibility = svm_check_processor_compat,
4206         .hardware_enable = svm_hardware_enable,
4207         .hardware_disable = svm_hardware_disable,
4208         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4209
4210         .vcpu_create = svm_create_vcpu,
4211         .vcpu_free = svm_free_vcpu,
4212         .vcpu_reset = svm_vcpu_reset,
4213
4214         .prepare_guest_switch = svm_prepare_guest_switch,
4215         .vcpu_load = svm_vcpu_load,
4216         .vcpu_put = svm_vcpu_put,
4217
4218         .set_guest_debug = svm_guest_debug,
4219         .get_msr = svm_get_msr,
4220         .set_msr = svm_set_msr,
4221         .get_segment_base = svm_get_segment_base,
4222         .get_segment = svm_get_segment,
4223         .set_segment = svm_set_segment,
4224         .get_cpl = svm_get_cpl,
4225         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4226         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
4227         .decache_cr3 = svm_decache_cr3,
4228         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
4229         .set_cr0 = svm_set_cr0,
4230         .set_cr3 = svm_set_cr3,
4231         .set_cr4 = svm_set_cr4,
4232         .set_efer = svm_set_efer,
4233         .get_idt = svm_get_idt,
4234         .set_idt = svm_set_idt,
4235         .get_gdt = svm_get_gdt,
4236         .set_gdt = svm_set_gdt,
4237         .set_dr7 = svm_set_dr7,
4238         .cache_reg = svm_cache_reg,
4239         .get_rflags = svm_get_rflags,
4240         .set_rflags = svm_set_rflags,
4241         .fpu_activate = svm_fpu_activate,
4242         .fpu_deactivate = svm_fpu_deactivate,
4243
4244         .tlb_flush = svm_flush_tlb,
4245
4246         .run = svm_vcpu_run,
4247         .handle_exit = handle_exit,
4248         .skip_emulated_instruction = skip_emulated_instruction,
4249         .set_interrupt_shadow = svm_set_interrupt_shadow,
4250         .get_interrupt_shadow = svm_get_interrupt_shadow,
4251         .patch_hypercall = svm_patch_hypercall,
4252         .set_irq = svm_set_irq,
4253         .set_nmi = svm_inject_nmi,
4254         .queue_exception = svm_queue_exception,
4255         .cancel_injection = svm_cancel_injection,
4256         .interrupt_allowed = svm_interrupt_allowed,
4257         .nmi_allowed = svm_nmi_allowed,
4258         .get_nmi_mask = svm_get_nmi_mask,
4259         .set_nmi_mask = svm_set_nmi_mask,
4260         .enable_nmi_window = enable_nmi_window,
4261         .enable_irq_window = enable_irq_window,
4262         .update_cr8_intercept = update_cr8_intercept,
4263
4264         .set_tss_addr = svm_set_tss_addr,
4265         .get_tdp_level = get_npt_level,
4266         .get_mt_mask = svm_get_mt_mask,
4267
4268         .get_exit_info = svm_get_exit_info,
4269
4270         .get_lpage_level = svm_get_lpage_level,
4271
4272         .cpuid_update = svm_cpuid_update,
4273
4274         .rdtscp_supported = svm_rdtscp_supported,
4275
4276         .set_supported_cpuid = svm_set_supported_cpuid,
4277
4278         .has_wbinvd_exit = svm_has_wbinvd_exit,
4279
4280         .set_tsc_khz = svm_set_tsc_khz,
4281         .write_tsc_offset = svm_write_tsc_offset,
4282         .adjust_tsc_offset = svm_adjust_tsc_offset,
4283         .compute_tsc_offset = svm_compute_tsc_offset,
4284         .read_l1_tsc = svm_read_l1_tsc,
4285
4286         .set_tdp_cr3 = set_tdp_cr3,
4287
4288         .check_intercept = svm_check_intercept,
4289 };
4290
4291 static int __init svm_init(void)
4292 {
4293         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
4294                         __alignof__(struct vcpu_svm), THIS_MODULE);
4295 }
4296
4297 static void __exit svm_exit(void)
4298 {
4299         kvm_exit();
4300 }
4301
4302 module_init(svm_init)
4303 module_exit(svm_exit)