2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
17 #include <linux/kvm_host.h>
21 #include "kvm_cache_regs.h"
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/vmalloc.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
32 #include <asm/tlbflush.h>
34 #include <asm/kvm_para.h>
36 #include <asm/virtext.h>
39 #define __ex(x) __kvm_handle_fault_on_reboot(x)
41 MODULE_AUTHOR("Qumranet");
42 MODULE_LICENSE("GPL");
44 #define IOPM_ALLOC_ORDER 2
45 #define MSRPM_ALLOC_ORDER 1
47 #define SEG_TYPE_LDT 2
48 #define SEG_TYPE_BUSY_TSS16 3
50 #define SVM_FEATURE_NPT (1 << 0)
51 #define SVM_FEATURE_LBRV (1 << 1)
52 #define SVM_FEATURE_SVML (1 << 2)
53 #define SVM_FEATURE_NRIP (1 << 3)
54 #define SVM_FEATURE_TSC_RATE (1 << 4)
55 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
56 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
57 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
58 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
60 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
61 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
62 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
64 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
66 static bool erratum_383_found __read_mostly;
68 static const u32 host_save_user_msrs[] = {
70 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
73 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
76 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
86 /* These are the merged vectors */
89 /* gpa pointers to the real vectors */
93 /* A VMEXIT is required but not yet emulated */
97 * If we vmexit during an instruction emulation we need this to restore
98 * the l1 guest rip after the emulation
100 unsigned long vmexit_rip;
101 unsigned long vmexit_rsp;
102 unsigned long vmexit_rax;
104 /* cache for intercepts of the guest */
107 u32 intercept_exceptions;
110 /* Nested Paging related state */
114 #define MSRPM_OFFSETS 16
115 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
118 struct kvm_vcpu vcpu;
120 unsigned long vmcb_pa;
121 struct svm_cpu_data *svm_data;
122 uint64_t asid_generation;
123 uint64_t sysenter_esp;
124 uint64_t sysenter_eip;
128 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
138 struct nested_state nested;
142 unsigned int3_injected;
143 unsigned long int3_rip;
147 #define MSR_INVALID 0xffffffffU
149 static struct svm_direct_access_msrs {
150 u32 index; /* Index of the MSR */
151 bool always; /* True if intercept is always on */
152 } direct_access_msrs[] = {
153 { .index = MSR_STAR, .always = true },
154 { .index = MSR_IA32_SYSENTER_CS, .always = true },
156 { .index = MSR_GS_BASE, .always = true },
157 { .index = MSR_FS_BASE, .always = true },
158 { .index = MSR_KERNEL_GS_BASE, .always = true },
159 { .index = MSR_LSTAR, .always = true },
160 { .index = MSR_CSTAR, .always = true },
161 { .index = MSR_SYSCALL_MASK, .always = true },
163 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
164 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
165 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
166 { .index = MSR_IA32_LASTINTTOIP, .always = false },
167 { .index = MSR_INVALID, .always = false },
170 /* enable NPT for AMD64 and X86 with PAE */
171 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
172 static bool npt_enabled = true;
174 static bool npt_enabled;
178 module_param(npt, int, S_IRUGO);
180 static int nested = 1;
181 module_param(nested, int, S_IRUGO);
183 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
184 static void svm_complete_interrupts(struct vcpu_svm *svm);
186 static int nested_svm_exit_handled(struct vcpu_svm *svm);
187 static int nested_svm_intercept(struct vcpu_svm *svm);
188 static int nested_svm_vmexit(struct vcpu_svm *svm);
189 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
190 bool has_error_code, u32 error_code);
193 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
194 pause filter count */
195 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
196 VMCB_ASID, /* ASID */
197 VMCB_INTR, /* int_ctl, int_vector */
198 VMCB_NPT, /* npt_en, nCR3, gPAT */
199 VMCB_CR, /* CR0, CR3, CR4, EFER */
200 VMCB_DR, /* DR6, DR7 */
201 VMCB_DT, /* GDT, IDT */
202 VMCB_SEG, /* CS, DS, SS, ES, CPL */
203 VMCB_CR2, /* CR2 only */
204 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
208 /* TPR and CR2 are always written before VMRUN */
209 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
211 static inline void mark_all_dirty(struct vmcb *vmcb)
213 vmcb->control.clean = 0;
216 static inline void mark_all_clean(struct vmcb *vmcb)
218 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
219 & ~VMCB_ALWAYS_DIRTY_MASK;
222 static inline void mark_dirty(struct vmcb *vmcb, int bit)
224 vmcb->control.clean &= ~(1 << bit);
227 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
229 return container_of(vcpu, struct vcpu_svm, vcpu);
232 static void recalc_intercepts(struct vcpu_svm *svm)
234 struct vmcb_control_area *c, *h;
235 struct nested_state *g;
237 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
239 if (!is_guest_mode(&svm->vcpu))
242 c = &svm->vmcb->control;
243 h = &svm->nested.hsave->control;
246 c->intercept_cr = h->intercept_cr | g->intercept_cr;
247 c->intercept_dr = h->intercept_dr | g->intercept_dr;
248 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
249 c->intercept = h->intercept | g->intercept;
252 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
254 if (is_guest_mode(&svm->vcpu))
255 return svm->nested.hsave;
260 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
262 struct vmcb *vmcb = get_host_vmcb(svm);
264 vmcb->control.intercept_cr |= (1U << bit);
266 recalc_intercepts(svm);
269 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
271 struct vmcb *vmcb = get_host_vmcb(svm);
273 vmcb->control.intercept_cr &= ~(1U << bit);
275 recalc_intercepts(svm);
278 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
280 struct vmcb *vmcb = get_host_vmcb(svm);
282 return vmcb->control.intercept_cr & (1U << bit);
285 static inline void set_dr_intercept(struct vcpu_svm *svm, int bit)
287 struct vmcb *vmcb = get_host_vmcb(svm);
289 vmcb->control.intercept_dr |= (1U << bit);
291 recalc_intercepts(svm);
294 static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit)
296 struct vmcb *vmcb = get_host_vmcb(svm);
298 vmcb->control.intercept_dr &= ~(1U << bit);
300 recalc_intercepts(svm);
303 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
305 struct vmcb *vmcb = get_host_vmcb(svm);
307 vmcb->control.intercept_exceptions |= (1U << bit);
309 recalc_intercepts(svm);
312 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
314 struct vmcb *vmcb = get_host_vmcb(svm);
316 vmcb->control.intercept_exceptions &= ~(1U << bit);
318 recalc_intercepts(svm);
321 static inline void set_intercept(struct vcpu_svm *svm, int bit)
323 struct vmcb *vmcb = get_host_vmcb(svm);
325 vmcb->control.intercept |= (1ULL << bit);
327 recalc_intercepts(svm);
330 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
332 struct vmcb *vmcb = get_host_vmcb(svm);
334 vmcb->control.intercept &= ~(1ULL << bit);
336 recalc_intercepts(svm);
339 static inline void enable_gif(struct vcpu_svm *svm)
341 svm->vcpu.arch.hflags |= HF_GIF_MASK;
344 static inline void disable_gif(struct vcpu_svm *svm)
346 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
349 static inline bool gif_set(struct vcpu_svm *svm)
351 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
354 static unsigned long iopm_base;
356 struct kvm_ldttss_desc {
359 unsigned base1:8, type:5, dpl:2, p:1;
360 unsigned limit1:4, zero0:3, g:1, base2:8;
363 } __attribute__((packed));
365 struct svm_cpu_data {
371 struct kvm_ldttss_desc *tss_desc;
373 struct page *save_area;
376 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
377 static uint32_t svm_features;
379 struct svm_init_data {
384 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
386 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
387 #define MSRS_RANGE_SIZE 2048
388 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
390 static u32 svm_msrpm_offset(u32 msr)
395 for (i = 0; i < NUM_MSR_MAPS; i++) {
396 if (msr < msrpm_ranges[i] ||
397 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
400 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
401 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
403 /* Now we have the u8 offset - but need the u32 offset */
407 /* MSR not in any range */
411 #define MAX_INST_SIZE 15
413 static inline void clgi(void)
415 asm volatile (__ex(SVM_CLGI));
418 static inline void stgi(void)
420 asm volatile (__ex(SVM_STGI));
423 static inline void invlpga(unsigned long addr, u32 asid)
425 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
428 static int get_npt_level(void)
431 return PT64_ROOT_LEVEL;
433 return PT32E_ROOT_LEVEL;
437 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
439 vcpu->arch.efer = efer;
440 if (!npt_enabled && !(efer & EFER_LMA))
443 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
444 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
447 static int is_external_interrupt(u32 info)
449 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
450 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
453 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
455 struct vcpu_svm *svm = to_svm(vcpu);
458 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
459 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
463 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
465 struct vcpu_svm *svm = to_svm(vcpu);
468 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
470 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
474 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
476 struct vcpu_svm *svm = to_svm(vcpu);
478 if (svm->vmcb->control.next_rip != 0)
479 svm->next_rip = svm->vmcb->control.next_rip;
481 if (!svm->next_rip) {
482 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
484 printk(KERN_DEBUG "%s: NOP\n", __func__);
487 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
488 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
489 __func__, kvm_rip_read(vcpu), svm->next_rip);
491 kvm_rip_write(vcpu, svm->next_rip);
492 svm_set_interrupt_shadow(vcpu, 0);
495 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
496 bool has_error_code, u32 error_code,
499 struct vcpu_svm *svm = to_svm(vcpu);
502 * If we are within a nested VM we'd better #VMEXIT and let the guest
503 * handle the exception
506 nested_svm_check_exception(svm, nr, has_error_code, error_code))
509 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
510 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
513 * For guest debugging where we have to reinject #BP if some
514 * INT3 is guest-owned:
515 * Emulate nRIP by moving RIP forward. Will fail if injection
516 * raises a fault that is not intercepted. Still better than
517 * failing in all cases.
519 skip_emulated_instruction(&svm->vcpu);
520 rip = kvm_rip_read(&svm->vcpu);
521 svm->int3_rip = rip + svm->vmcb->save.cs.base;
522 svm->int3_injected = rip - old_rip;
525 svm->vmcb->control.event_inj = nr
527 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
528 | SVM_EVTINJ_TYPE_EXEPT;
529 svm->vmcb->control.event_inj_err = error_code;
532 static void svm_init_erratum_383(void)
538 if (!cpu_has_amd_erratum(amd_erratum_383))
541 /* Use _safe variants to not break nested virtualization */
542 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
548 low = lower_32_bits(val);
549 high = upper_32_bits(val);
551 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
553 erratum_383_found = true;
556 static int has_svm(void)
560 if (!cpu_has_svm(&msg)) {
561 printk(KERN_INFO "has_svm: %s\n", msg);
568 static void svm_hardware_disable(void *garbage)
573 static int svm_hardware_enable(void *garbage)
576 struct svm_cpu_data *sd;
578 struct desc_ptr gdt_descr;
579 struct desc_struct *gdt;
580 int me = raw_smp_processor_id();
582 rdmsrl(MSR_EFER, efer);
583 if (efer & EFER_SVME)
587 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
591 sd = per_cpu(svm_data, me);
594 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
599 sd->asid_generation = 1;
600 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
601 sd->next_asid = sd->max_asid + 1;
603 native_store_gdt(&gdt_descr);
604 gdt = (struct desc_struct *)gdt_descr.address;
605 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
607 wrmsrl(MSR_EFER, efer | EFER_SVME);
609 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
611 svm_init_erratum_383();
616 static void svm_cpu_uninit(int cpu)
618 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
623 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
624 __free_page(sd->save_area);
628 static int svm_cpu_init(int cpu)
630 struct svm_cpu_data *sd;
633 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
637 sd->save_area = alloc_page(GFP_KERNEL);
642 per_cpu(svm_data, cpu) = sd;
652 static bool valid_msr_intercept(u32 index)
656 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
657 if (direct_access_msrs[i].index == index)
663 static void set_msr_interception(u32 *msrpm, unsigned msr,
666 u8 bit_read, bit_write;
671 * If this warning triggers extend the direct_access_msrs list at the
672 * beginning of the file
674 WARN_ON(!valid_msr_intercept(msr));
676 offset = svm_msrpm_offset(msr);
677 bit_read = 2 * (msr & 0x0f);
678 bit_write = 2 * (msr & 0x0f) + 1;
681 BUG_ON(offset == MSR_INVALID);
683 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
684 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
689 static void svm_vcpu_init_msrpm(u32 *msrpm)
693 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
695 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
696 if (!direct_access_msrs[i].always)
699 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
703 static void add_msr_offset(u32 offset)
707 for (i = 0; i < MSRPM_OFFSETS; ++i) {
709 /* Offset already in list? */
710 if (msrpm_offsets[i] == offset)
713 /* Slot used by another offset? */
714 if (msrpm_offsets[i] != MSR_INVALID)
717 /* Add offset to list */
718 msrpm_offsets[i] = offset;
724 * If this BUG triggers the msrpm_offsets table has an overflow. Just
725 * increase MSRPM_OFFSETS in this case.
730 static void init_msrpm_offsets(void)
734 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
736 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
739 offset = svm_msrpm_offset(direct_access_msrs[i].index);
740 BUG_ON(offset == MSR_INVALID);
742 add_msr_offset(offset);
746 static void svm_enable_lbrv(struct vcpu_svm *svm)
748 u32 *msrpm = svm->msrpm;
750 svm->vmcb->control.lbr_ctl = 1;
751 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
752 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
753 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
754 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
757 static void svm_disable_lbrv(struct vcpu_svm *svm)
759 u32 *msrpm = svm->msrpm;
761 svm->vmcb->control.lbr_ctl = 0;
762 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
763 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
764 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
765 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
768 static __init int svm_hardware_setup(void)
771 struct page *iopm_pages;
775 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
780 iopm_va = page_address(iopm_pages);
781 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
782 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
784 init_msrpm_offsets();
786 if (boot_cpu_has(X86_FEATURE_NX))
787 kvm_enable_efer_bits(EFER_NX);
789 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
790 kvm_enable_efer_bits(EFER_FFXSR);
793 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
794 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
797 for_each_possible_cpu(cpu) {
798 r = svm_cpu_init(cpu);
803 svm_features = cpuid_edx(SVM_CPUID_FUNC);
805 if (!boot_cpu_has(X86_FEATURE_NPT))
808 if (npt_enabled && !npt) {
809 printk(KERN_INFO "kvm: Nested Paging disabled\n");
814 printk(KERN_INFO "kvm: Nested Paging enabled\n");
822 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
827 static __exit void svm_hardware_unsetup(void)
831 for_each_possible_cpu(cpu)
834 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
838 static void init_seg(struct vmcb_seg *seg)
841 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
842 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
847 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
850 seg->attrib = SVM_SELECTOR_P_MASK | type;
855 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
857 struct vcpu_svm *svm = to_svm(vcpu);
858 u64 g_tsc_offset = 0;
860 if (is_guest_mode(vcpu)) {
861 g_tsc_offset = svm->vmcb->control.tsc_offset -
862 svm->nested.hsave->control.tsc_offset;
863 svm->nested.hsave->control.tsc_offset = offset;
866 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
868 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
871 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
873 struct vcpu_svm *svm = to_svm(vcpu);
875 svm->vmcb->control.tsc_offset += adjustment;
876 if (is_guest_mode(vcpu))
877 svm->nested.hsave->control.tsc_offset += adjustment;
878 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
881 static void init_vmcb(struct vcpu_svm *svm)
883 struct vmcb_control_area *control = &svm->vmcb->control;
884 struct vmcb_save_area *save = &svm->vmcb->save;
886 svm->vcpu.fpu_active = 1;
887 svm->vcpu.arch.hflags = 0;
889 set_cr_intercept(svm, INTERCEPT_CR0_READ);
890 set_cr_intercept(svm, INTERCEPT_CR3_READ);
891 set_cr_intercept(svm, INTERCEPT_CR4_READ);
892 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
893 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
894 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
895 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
897 set_dr_intercept(svm, INTERCEPT_DR0_READ);
898 set_dr_intercept(svm, INTERCEPT_DR1_READ);
899 set_dr_intercept(svm, INTERCEPT_DR2_READ);
900 set_dr_intercept(svm, INTERCEPT_DR3_READ);
901 set_dr_intercept(svm, INTERCEPT_DR4_READ);
902 set_dr_intercept(svm, INTERCEPT_DR5_READ);
903 set_dr_intercept(svm, INTERCEPT_DR6_READ);
904 set_dr_intercept(svm, INTERCEPT_DR7_READ);
906 set_dr_intercept(svm, INTERCEPT_DR0_WRITE);
907 set_dr_intercept(svm, INTERCEPT_DR1_WRITE);
908 set_dr_intercept(svm, INTERCEPT_DR2_WRITE);
909 set_dr_intercept(svm, INTERCEPT_DR3_WRITE);
910 set_dr_intercept(svm, INTERCEPT_DR4_WRITE);
911 set_dr_intercept(svm, INTERCEPT_DR5_WRITE);
912 set_dr_intercept(svm, INTERCEPT_DR6_WRITE);
913 set_dr_intercept(svm, INTERCEPT_DR7_WRITE);
915 set_exception_intercept(svm, PF_VECTOR);
916 set_exception_intercept(svm, UD_VECTOR);
917 set_exception_intercept(svm, MC_VECTOR);
919 set_intercept(svm, INTERCEPT_INTR);
920 set_intercept(svm, INTERCEPT_NMI);
921 set_intercept(svm, INTERCEPT_SMI);
922 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
923 set_intercept(svm, INTERCEPT_CPUID);
924 set_intercept(svm, INTERCEPT_INVD);
925 set_intercept(svm, INTERCEPT_HLT);
926 set_intercept(svm, INTERCEPT_INVLPG);
927 set_intercept(svm, INTERCEPT_INVLPGA);
928 set_intercept(svm, INTERCEPT_IOIO_PROT);
929 set_intercept(svm, INTERCEPT_MSR_PROT);
930 set_intercept(svm, INTERCEPT_TASK_SWITCH);
931 set_intercept(svm, INTERCEPT_SHUTDOWN);
932 set_intercept(svm, INTERCEPT_VMRUN);
933 set_intercept(svm, INTERCEPT_VMMCALL);
934 set_intercept(svm, INTERCEPT_VMLOAD);
935 set_intercept(svm, INTERCEPT_VMSAVE);
936 set_intercept(svm, INTERCEPT_STGI);
937 set_intercept(svm, INTERCEPT_CLGI);
938 set_intercept(svm, INTERCEPT_SKINIT);
939 set_intercept(svm, INTERCEPT_WBINVD);
940 set_intercept(svm, INTERCEPT_MONITOR);
941 set_intercept(svm, INTERCEPT_MWAIT);
942 set_intercept(svm, INTERCEPT_XSETBV);
944 control->iopm_base_pa = iopm_base;
945 control->msrpm_base_pa = __pa(svm->msrpm);
946 control->int_ctl = V_INTR_MASKING_MASK;
954 save->cs.selector = 0xf000;
955 /* Executable/Readable Code Segment */
956 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
957 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
958 save->cs.limit = 0xffff;
960 * cs.base should really be 0xffff0000, but vmx can't handle that, so
961 * be consistent with it.
963 * Replace when we have real mode working for vmx.
965 save->cs.base = 0xf0000;
967 save->gdtr.limit = 0xffff;
968 save->idtr.limit = 0xffff;
970 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
971 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
973 svm_set_efer(&svm->vcpu, 0);
974 save->dr6 = 0xffff0ff0;
977 save->rip = 0x0000fff0;
978 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
981 * This is the guest-visible cr0 value.
982 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
984 svm->vcpu.arch.cr0 = 0;
985 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
987 save->cr4 = X86_CR4_PAE;
991 /* Setup VMCB for Nested Paging */
992 control->nested_ctl = 1;
993 clr_intercept(svm, INTERCEPT_TASK_SWITCH);
994 clr_intercept(svm, INTERCEPT_INVLPG);
995 clr_exception_intercept(svm, PF_VECTOR);
996 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
997 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
998 save->g_pat = 0x0007040600070406ULL;
1002 svm->asid_generation = 0;
1004 svm->nested.vmcb = 0;
1005 svm->vcpu.arch.hflags = 0;
1007 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1008 control->pause_filter_count = 3000;
1009 set_intercept(svm, INTERCEPT_PAUSE);
1012 mark_all_dirty(svm->vmcb);
1017 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
1019 struct vcpu_svm *svm = to_svm(vcpu);
1023 if (!kvm_vcpu_is_bsp(vcpu)) {
1024 kvm_rip_write(vcpu, 0);
1025 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
1026 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
1028 vcpu->arch.regs_avail = ~0;
1029 vcpu->arch.regs_dirty = ~0;
1034 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1036 struct vcpu_svm *svm;
1038 struct page *msrpm_pages;
1039 struct page *hsave_page;
1040 struct page *nested_msrpm_pages;
1043 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1049 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1054 page = alloc_page(GFP_KERNEL);
1058 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1062 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1063 if (!nested_msrpm_pages)
1066 hsave_page = alloc_page(GFP_KERNEL);
1070 svm->nested.hsave = page_address(hsave_page);
1072 svm->msrpm = page_address(msrpm_pages);
1073 svm_vcpu_init_msrpm(svm->msrpm);
1075 svm->nested.msrpm = page_address(nested_msrpm_pages);
1076 svm_vcpu_init_msrpm(svm->nested.msrpm);
1078 svm->vmcb = page_address(page);
1079 clear_page(svm->vmcb);
1080 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1081 svm->asid_generation = 0;
1083 kvm_write_tsc(&svm->vcpu, 0);
1085 err = fx_init(&svm->vcpu);
1089 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1090 if (kvm_vcpu_is_bsp(&svm->vcpu))
1091 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1096 __free_page(hsave_page);
1098 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1100 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1104 kvm_vcpu_uninit(&svm->vcpu);
1106 kmem_cache_free(kvm_vcpu_cache, svm);
1108 return ERR_PTR(err);
1111 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1113 struct vcpu_svm *svm = to_svm(vcpu);
1115 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1116 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1117 __free_page(virt_to_page(svm->nested.hsave));
1118 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1119 kvm_vcpu_uninit(vcpu);
1120 kmem_cache_free(kvm_vcpu_cache, svm);
1123 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1125 struct vcpu_svm *svm = to_svm(vcpu);
1128 if (unlikely(cpu != vcpu->cpu)) {
1129 svm->asid_generation = 0;
1130 mark_all_dirty(svm->vmcb);
1133 #ifdef CONFIG_X86_64
1134 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1136 savesegment(fs, svm->host.fs);
1137 savesegment(gs, svm->host.gs);
1138 svm->host.ldt = kvm_read_ldt();
1140 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1141 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1144 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1146 struct vcpu_svm *svm = to_svm(vcpu);
1149 ++vcpu->stat.host_state_reload;
1150 kvm_load_ldt(svm->host.ldt);
1151 #ifdef CONFIG_X86_64
1152 loadsegment(fs, svm->host.fs);
1153 load_gs_index(svm->host.gs);
1154 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1156 loadsegment(gs, svm->host.gs);
1158 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1159 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1162 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1164 return to_svm(vcpu)->vmcb->save.rflags;
1167 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1169 to_svm(vcpu)->vmcb->save.rflags = rflags;
1172 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1175 case VCPU_EXREG_PDPTR:
1176 BUG_ON(!npt_enabled);
1177 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
1184 static void svm_set_vintr(struct vcpu_svm *svm)
1186 set_intercept(svm, INTERCEPT_VINTR);
1189 static void svm_clear_vintr(struct vcpu_svm *svm)
1191 clr_intercept(svm, INTERCEPT_VINTR);
1194 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1196 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1199 case VCPU_SREG_CS: return &save->cs;
1200 case VCPU_SREG_DS: return &save->ds;
1201 case VCPU_SREG_ES: return &save->es;
1202 case VCPU_SREG_FS: return &save->fs;
1203 case VCPU_SREG_GS: return &save->gs;
1204 case VCPU_SREG_SS: return &save->ss;
1205 case VCPU_SREG_TR: return &save->tr;
1206 case VCPU_SREG_LDTR: return &save->ldtr;
1212 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1214 struct vmcb_seg *s = svm_seg(vcpu, seg);
1219 static void svm_get_segment(struct kvm_vcpu *vcpu,
1220 struct kvm_segment *var, int seg)
1222 struct vmcb_seg *s = svm_seg(vcpu, seg);
1224 var->base = s->base;
1225 var->limit = s->limit;
1226 var->selector = s->selector;
1227 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1228 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1229 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1230 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1231 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1232 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1233 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1234 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1237 * AMD's VMCB does not have an explicit unusable field, so emulate it
1238 * for cross vendor migration purposes by "not present"
1240 var->unusable = !var->present || (var->type == 0);
1245 * SVM always stores 0 for the 'G' bit in the CS selector in
1246 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1247 * Intel's VMENTRY has a check on the 'G' bit.
1249 var->g = s->limit > 0xfffff;
1253 * Work around a bug where the busy flag in the tr selector
1263 * The accessed bit must always be set in the segment
1264 * descriptor cache, although it can be cleared in the
1265 * descriptor, the cached bit always remains at 1. Since
1266 * Intel has a check on this, set it here to support
1267 * cross-vendor migration.
1274 * On AMD CPUs sometimes the DB bit in the segment
1275 * descriptor is left as 1, although the whole segment has
1276 * been made unusable. Clear it here to pass an Intel VMX
1277 * entry check when cross vendor migrating.
1285 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1287 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1292 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1294 struct vcpu_svm *svm = to_svm(vcpu);
1296 dt->size = svm->vmcb->save.idtr.limit;
1297 dt->address = svm->vmcb->save.idtr.base;
1300 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1302 struct vcpu_svm *svm = to_svm(vcpu);
1304 svm->vmcb->save.idtr.limit = dt->size;
1305 svm->vmcb->save.idtr.base = dt->address ;
1306 mark_dirty(svm->vmcb, VMCB_DT);
1309 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1311 struct vcpu_svm *svm = to_svm(vcpu);
1313 dt->size = svm->vmcb->save.gdtr.limit;
1314 dt->address = svm->vmcb->save.gdtr.base;
1317 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1319 struct vcpu_svm *svm = to_svm(vcpu);
1321 svm->vmcb->save.gdtr.limit = dt->size;
1322 svm->vmcb->save.gdtr.base = dt->address ;
1323 mark_dirty(svm->vmcb, VMCB_DT);
1326 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1330 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1334 static void update_cr0_intercept(struct vcpu_svm *svm)
1336 ulong gcr0 = svm->vcpu.arch.cr0;
1337 u64 *hcr0 = &svm->vmcb->save.cr0;
1339 if (!svm->vcpu.fpu_active)
1340 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1342 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1343 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1345 mark_dirty(svm->vmcb, VMCB_CR);
1347 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1348 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1349 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1351 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1352 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1356 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1358 struct vcpu_svm *svm = to_svm(vcpu);
1360 if (is_guest_mode(vcpu)) {
1362 * We are here because we run in nested mode, the host kvm
1363 * intercepts cr0 writes but the l1 hypervisor does not.
1364 * But the L1 hypervisor may intercept selective cr0 writes.
1365 * This needs to be checked here.
1367 unsigned long old, new;
1369 /* Remove bits that would trigger a real cr0 write intercept */
1370 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1371 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1374 /* cr0 write with ts and mp unchanged */
1375 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1376 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) {
1377 svm->nested.vmexit_rip = kvm_rip_read(vcpu);
1378 svm->nested.vmexit_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
1379 svm->nested.vmexit_rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
1385 #ifdef CONFIG_X86_64
1386 if (vcpu->arch.efer & EFER_LME) {
1387 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1388 vcpu->arch.efer |= EFER_LMA;
1389 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1392 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1393 vcpu->arch.efer &= ~EFER_LMA;
1394 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1398 vcpu->arch.cr0 = cr0;
1401 cr0 |= X86_CR0_PG | X86_CR0_WP;
1403 if (!vcpu->fpu_active)
1406 * re-enable caching here because the QEMU bios
1407 * does not do it - this results in some delay at
1410 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1411 svm->vmcb->save.cr0 = cr0;
1412 mark_dirty(svm->vmcb, VMCB_CR);
1413 update_cr0_intercept(svm);
1416 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1418 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1419 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1421 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1422 svm_flush_tlb(vcpu);
1424 vcpu->arch.cr4 = cr4;
1427 cr4 |= host_cr4_mce;
1428 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1429 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1432 static void svm_set_segment(struct kvm_vcpu *vcpu,
1433 struct kvm_segment *var, int seg)
1435 struct vcpu_svm *svm = to_svm(vcpu);
1436 struct vmcb_seg *s = svm_seg(vcpu, seg);
1438 s->base = var->base;
1439 s->limit = var->limit;
1440 s->selector = var->selector;
1444 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1445 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1446 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1447 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1448 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1449 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1450 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1451 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1453 if (seg == VCPU_SREG_CS)
1455 = (svm->vmcb->save.cs.attrib
1456 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1458 mark_dirty(svm->vmcb, VMCB_SEG);
1461 static void update_db_intercept(struct kvm_vcpu *vcpu)
1463 struct vcpu_svm *svm = to_svm(vcpu);
1465 clr_exception_intercept(svm, DB_VECTOR);
1466 clr_exception_intercept(svm, BP_VECTOR);
1468 if (svm->nmi_singlestep)
1469 set_exception_intercept(svm, DB_VECTOR);
1471 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1472 if (vcpu->guest_debug &
1473 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1474 set_exception_intercept(svm, DB_VECTOR);
1475 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1476 set_exception_intercept(svm, BP_VECTOR);
1478 vcpu->guest_debug = 0;
1481 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1483 struct vcpu_svm *svm = to_svm(vcpu);
1485 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1486 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1488 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1490 mark_dirty(svm->vmcb, VMCB_DR);
1492 update_db_intercept(vcpu);
1495 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1497 if (sd->next_asid > sd->max_asid) {
1498 ++sd->asid_generation;
1500 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1503 svm->asid_generation = sd->asid_generation;
1504 svm->vmcb->control.asid = sd->next_asid++;
1506 mark_dirty(svm->vmcb, VMCB_ASID);
1509 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1511 struct vcpu_svm *svm = to_svm(vcpu);
1513 svm->vmcb->save.dr7 = value;
1514 mark_dirty(svm->vmcb, VMCB_DR);
1517 static int pf_interception(struct vcpu_svm *svm)
1519 u64 fault_address = svm->vmcb->control.exit_info_2;
1523 switch (svm->apf_reason) {
1525 error_code = svm->vmcb->control.exit_info_1;
1527 trace_kvm_page_fault(fault_address, error_code);
1528 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1529 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1530 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1532 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1533 svm->apf_reason = 0;
1534 local_irq_disable();
1535 kvm_async_pf_task_wait(fault_address);
1538 case KVM_PV_REASON_PAGE_READY:
1539 svm->apf_reason = 0;
1540 local_irq_disable();
1541 kvm_async_pf_task_wake(fault_address);
1548 static int db_interception(struct vcpu_svm *svm)
1550 struct kvm_run *kvm_run = svm->vcpu.run;
1552 if (!(svm->vcpu.guest_debug &
1553 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1554 !svm->nmi_singlestep) {
1555 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1559 if (svm->nmi_singlestep) {
1560 svm->nmi_singlestep = false;
1561 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1562 svm->vmcb->save.rflags &=
1563 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1564 update_db_intercept(&svm->vcpu);
1567 if (svm->vcpu.guest_debug &
1568 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1569 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1570 kvm_run->debug.arch.pc =
1571 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1572 kvm_run->debug.arch.exception = DB_VECTOR;
1579 static int bp_interception(struct vcpu_svm *svm)
1581 struct kvm_run *kvm_run = svm->vcpu.run;
1583 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1584 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1585 kvm_run->debug.arch.exception = BP_VECTOR;
1589 static int ud_interception(struct vcpu_svm *svm)
1593 er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
1594 if (er != EMULATE_DONE)
1595 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1599 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1601 struct vcpu_svm *svm = to_svm(vcpu);
1603 clr_exception_intercept(svm, NM_VECTOR);
1605 svm->vcpu.fpu_active = 1;
1606 update_cr0_intercept(svm);
1609 static int nm_interception(struct vcpu_svm *svm)
1611 svm_fpu_activate(&svm->vcpu);
1615 static bool is_erratum_383(void)
1620 if (!erratum_383_found)
1623 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1627 /* Bit 62 may or may not be set for this mce */
1628 value &= ~(1ULL << 62);
1630 if (value != 0xb600000000010015ULL)
1633 /* Clear MCi_STATUS registers */
1634 for (i = 0; i < 6; ++i)
1635 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1637 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1641 value &= ~(1ULL << 2);
1642 low = lower_32_bits(value);
1643 high = upper_32_bits(value);
1645 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1648 /* Flush tlb to evict multi-match entries */
1654 static void svm_handle_mce(struct vcpu_svm *svm)
1656 if (is_erratum_383()) {
1658 * Erratum 383 triggered. Guest state is corrupt so kill the
1661 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1663 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1669 * On an #MC intercept the MCE handler is not called automatically in
1670 * the host. So do it by hand here.
1674 /* not sure if we ever come back to this point */
1679 static int mc_interception(struct vcpu_svm *svm)
1684 static int shutdown_interception(struct vcpu_svm *svm)
1686 struct kvm_run *kvm_run = svm->vcpu.run;
1689 * VMCB is undefined after a SHUTDOWN intercept
1690 * so reinitialize it.
1692 clear_page(svm->vmcb);
1695 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1699 static int io_interception(struct vcpu_svm *svm)
1701 struct kvm_vcpu *vcpu = &svm->vcpu;
1702 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1703 int size, in, string;
1706 ++svm->vcpu.stat.io_exits;
1707 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1708 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1710 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
1712 port = io_info >> 16;
1713 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1714 svm->next_rip = svm->vmcb->control.exit_info_2;
1715 skip_emulated_instruction(&svm->vcpu);
1717 return kvm_fast_pio_out(vcpu, size, port);
1720 static int nmi_interception(struct vcpu_svm *svm)
1725 static int intr_interception(struct vcpu_svm *svm)
1727 ++svm->vcpu.stat.irq_exits;
1731 static int nop_on_interception(struct vcpu_svm *svm)
1736 static int halt_interception(struct vcpu_svm *svm)
1738 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1739 skip_emulated_instruction(&svm->vcpu);
1740 return kvm_emulate_halt(&svm->vcpu);
1743 static int vmmcall_interception(struct vcpu_svm *svm)
1745 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1746 skip_emulated_instruction(&svm->vcpu);
1747 kvm_emulate_hypercall(&svm->vcpu);
1751 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1753 struct vcpu_svm *svm = to_svm(vcpu);
1755 return svm->nested.nested_cr3;
1758 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1761 struct vcpu_svm *svm = to_svm(vcpu);
1763 svm->vmcb->control.nested_cr3 = root;
1764 mark_dirty(svm->vmcb, VMCB_NPT);
1765 svm_flush_tlb(vcpu);
1768 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1769 struct x86_exception *fault)
1771 struct vcpu_svm *svm = to_svm(vcpu);
1773 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1774 svm->vmcb->control.exit_code_hi = 0;
1775 svm->vmcb->control.exit_info_1 = fault->error_code;
1776 svm->vmcb->control.exit_info_2 = fault->address;
1778 nested_svm_vmexit(svm);
1781 static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1785 r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1787 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
1788 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
1789 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1790 vcpu->arch.mmu.shadow_root_level = get_npt_level();
1791 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
1796 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1798 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1801 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1803 if (!(svm->vcpu.arch.efer & EFER_SVME)
1804 || !is_paging(&svm->vcpu)) {
1805 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1809 if (svm->vmcb->save.cpl) {
1810 kvm_inject_gp(&svm->vcpu, 0);
1817 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1818 bool has_error_code, u32 error_code)
1822 if (!is_guest_mode(&svm->vcpu))
1825 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1826 svm->vmcb->control.exit_code_hi = 0;
1827 svm->vmcb->control.exit_info_1 = error_code;
1828 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1830 vmexit = nested_svm_intercept(svm);
1831 if (vmexit == NESTED_EXIT_DONE)
1832 svm->nested.exit_required = true;
1837 /* This function returns true if it is save to enable the irq window */
1838 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1840 if (!is_guest_mode(&svm->vcpu))
1843 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1846 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1850 * if vmexit was already requested (by intercepted exception
1851 * for instance) do not overwrite it with "external interrupt"
1854 if (svm->nested.exit_required)
1857 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1858 svm->vmcb->control.exit_info_1 = 0;
1859 svm->vmcb->control.exit_info_2 = 0;
1861 if (svm->nested.intercept & 1ULL) {
1863 * The #vmexit can't be emulated here directly because this
1864 * code path runs with irqs and preemtion disabled. A
1865 * #vmexit emulation might sleep. Only signal request for
1868 svm->nested.exit_required = true;
1869 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1876 /* This function returns true if it is save to enable the nmi window */
1877 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1879 if (!is_guest_mode(&svm->vcpu))
1882 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1885 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1886 svm->nested.exit_required = true;
1891 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1897 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1898 if (is_error_page(page))
1906 kvm_release_page_clean(page);
1907 kvm_inject_gp(&svm->vcpu, 0);
1912 static void nested_svm_unmap(struct page *page)
1915 kvm_release_page_dirty(page);
1918 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1924 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1925 return NESTED_EXIT_HOST;
1927 port = svm->vmcb->control.exit_info_1 >> 16;
1928 gpa = svm->nested.vmcb_iopm + (port / 8);
1932 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1935 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1938 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1940 u32 offset, msr, value;
1943 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1944 return NESTED_EXIT_HOST;
1946 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1947 offset = svm_msrpm_offset(msr);
1948 write = svm->vmcb->control.exit_info_1 & 1;
1949 mask = 1 << ((2 * (msr & 0xf)) + write);
1951 if (offset == MSR_INVALID)
1952 return NESTED_EXIT_DONE;
1954 /* Offset is in 32 bit units but need in 8 bit units */
1957 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1958 return NESTED_EXIT_DONE;
1960 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1963 static int nested_svm_exit_special(struct vcpu_svm *svm)
1965 u32 exit_code = svm->vmcb->control.exit_code;
1967 switch (exit_code) {
1970 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
1971 return NESTED_EXIT_HOST;
1973 /* For now we are always handling NPFs when using them */
1975 return NESTED_EXIT_HOST;
1977 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1978 /* When we're shadowing, trap PFs, but not async PF */
1979 if (!npt_enabled && svm->apf_reason == 0)
1980 return NESTED_EXIT_HOST;
1982 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1983 nm_interception(svm);
1989 return NESTED_EXIT_CONTINUE;
1993 * If this function returns true, this #vmexit was already handled
1995 static int nested_svm_intercept(struct vcpu_svm *svm)
1997 u32 exit_code = svm->vmcb->control.exit_code;
1998 int vmexit = NESTED_EXIT_HOST;
2000 switch (exit_code) {
2002 vmexit = nested_svm_exit_handled_msr(svm);
2005 vmexit = nested_svm_intercept_ioio(svm);
2007 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2008 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2009 if (svm->nested.intercept_cr & bit)
2010 vmexit = NESTED_EXIT_DONE;
2013 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2014 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2015 if (svm->nested.intercept_dr & bit)
2016 vmexit = NESTED_EXIT_DONE;
2019 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2020 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2021 if (svm->nested.intercept_exceptions & excp_bits)
2022 vmexit = NESTED_EXIT_DONE;
2023 /* async page fault always cause vmexit */
2024 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2025 svm->apf_reason != 0)
2026 vmexit = NESTED_EXIT_DONE;
2029 case SVM_EXIT_ERR: {
2030 vmexit = NESTED_EXIT_DONE;
2034 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2035 if (svm->nested.intercept & exit_bits)
2036 vmexit = NESTED_EXIT_DONE;
2043 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2047 vmexit = nested_svm_intercept(svm);
2049 if (vmexit == NESTED_EXIT_DONE)
2050 nested_svm_vmexit(svm);
2055 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2057 struct vmcb_control_area *dst = &dst_vmcb->control;
2058 struct vmcb_control_area *from = &from_vmcb->control;
2060 dst->intercept_cr = from->intercept_cr;
2061 dst->intercept_dr = from->intercept_dr;
2062 dst->intercept_exceptions = from->intercept_exceptions;
2063 dst->intercept = from->intercept;
2064 dst->iopm_base_pa = from->iopm_base_pa;
2065 dst->msrpm_base_pa = from->msrpm_base_pa;
2066 dst->tsc_offset = from->tsc_offset;
2067 dst->asid = from->asid;
2068 dst->tlb_ctl = from->tlb_ctl;
2069 dst->int_ctl = from->int_ctl;
2070 dst->int_vector = from->int_vector;
2071 dst->int_state = from->int_state;
2072 dst->exit_code = from->exit_code;
2073 dst->exit_code_hi = from->exit_code_hi;
2074 dst->exit_info_1 = from->exit_info_1;
2075 dst->exit_info_2 = from->exit_info_2;
2076 dst->exit_int_info = from->exit_int_info;
2077 dst->exit_int_info_err = from->exit_int_info_err;
2078 dst->nested_ctl = from->nested_ctl;
2079 dst->event_inj = from->event_inj;
2080 dst->event_inj_err = from->event_inj_err;
2081 dst->nested_cr3 = from->nested_cr3;
2082 dst->lbr_ctl = from->lbr_ctl;
2085 static int nested_svm_vmexit(struct vcpu_svm *svm)
2087 struct vmcb *nested_vmcb;
2088 struct vmcb *hsave = svm->nested.hsave;
2089 struct vmcb *vmcb = svm->vmcb;
2092 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2093 vmcb->control.exit_info_1,
2094 vmcb->control.exit_info_2,
2095 vmcb->control.exit_int_info,
2096 vmcb->control.exit_int_info_err);
2098 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2102 /* Exit Guest-Mode */
2103 leave_guest_mode(&svm->vcpu);
2104 svm->nested.vmcb = 0;
2106 /* Give the current vmcb to the guest */
2109 nested_vmcb->save.es = vmcb->save.es;
2110 nested_vmcb->save.cs = vmcb->save.cs;
2111 nested_vmcb->save.ss = vmcb->save.ss;
2112 nested_vmcb->save.ds = vmcb->save.ds;
2113 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2114 nested_vmcb->save.idtr = vmcb->save.idtr;
2115 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2116 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2117 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
2118 nested_vmcb->save.cr2 = vmcb->save.cr2;
2119 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2120 nested_vmcb->save.rflags = vmcb->save.rflags;
2121 nested_vmcb->save.rip = vmcb->save.rip;
2122 nested_vmcb->save.rsp = vmcb->save.rsp;
2123 nested_vmcb->save.rax = vmcb->save.rax;
2124 nested_vmcb->save.dr7 = vmcb->save.dr7;
2125 nested_vmcb->save.dr6 = vmcb->save.dr6;
2126 nested_vmcb->save.cpl = vmcb->save.cpl;
2128 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2129 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2130 nested_vmcb->control.int_state = vmcb->control.int_state;
2131 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2132 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2133 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2134 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2135 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2136 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2137 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2140 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2141 * to make sure that we do not lose injected events. So check event_inj
2142 * here and copy it to exit_int_info if it is valid.
2143 * Exit_int_info and event_inj can't be both valid because the case
2144 * below only happens on a VMRUN instruction intercept which has
2145 * no valid exit_int_info set.
2147 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2148 struct vmcb_control_area *nc = &nested_vmcb->control;
2150 nc->exit_int_info = vmcb->control.event_inj;
2151 nc->exit_int_info_err = vmcb->control.event_inj_err;
2154 nested_vmcb->control.tlb_ctl = 0;
2155 nested_vmcb->control.event_inj = 0;
2156 nested_vmcb->control.event_inj_err = 0;
2158 /* We always set V_INTR_MASKING and remember the old value in hflags */
2159 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2160 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2162 /* Restore the original control entries */
2163 copy_vmcb_control_area(vmcb, hsave);
2165 kvm_clear_exception_queue(&svm->vcpu);
2166 kvm_clear_interrupt_queue(&svm->vcpu);
2168 svm->nested.nested_cr3 = 0;
2170 /* Restore selected save entries */
2171 svm->vmcb->save.es = hsave->save.es;
2172 svm->vmcb->save.cs = hsave->save.cs;
2173 svm->vmcb->save.ss = hsave->save.ss;
2174 svm->vmcb->save.ds = hsave->save.ds;
2175 svm->vmcb->save.gdtr = hsave->save.gdtr;
2176 svm->vmcb->save.idtr = hsave->save.idtr;
2177 svm->vmcb->save.rflags = hsave->save.rflags;
2178 svm_set_efer(&svm->vcpu, hsave->save.efer);
2179 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2180 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2182 svm->vmcb->save.cr3 = hsave->save.cr3;
2183 svm->vcpu.arch.cr3 = hsave->save.cr3;
2185 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2187 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2188 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2189 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2190 svm->vmcb->save.dr7 = 0;
2191 svm->vmcb->save.cpl = 0;
2192 svm->vmcb->control.exit_int_info = 0;
2194 mark_all_dirty(svm->vmcb);
2196 nested_svm_unmap(page);
2198 nested_svm_uninit_mmu_context(&svm->vcpu);
2199 kvm_mmu_reset_context(&svm->vcpu);
2200 kvm_mmu_load(&svm->vcpu);
2205 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2208 * This function merges the msr permission bitmaps of kvm and the
2209 * nested vmcb. It is omptimized in that it only merges the parts where
2210 * the kvm msr permission bitmap may contain zero bits
2214 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2217 for (i = 0; i < MSRPM_OFFSETS; i++) {
2221 if (msrpm_offsets[i] == 0xffffffff)
2224 p = msrpm_offsets[i];
2225 offset = svm->nested.vmcb_msrpm + (p * 4);
2227 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2230 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2233 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2238 static bool nested_vmcb_checks(struct vmcb *vmcb)
2240 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2243 if (vmcb->control.asid == 0)
2246 if (vmcb->control.nested_ctl && !npt_enabled)
2252 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2254 struct vmcb *nested_vmcb;
2255 struct vmcb *hsave = svm->nested.hsave;
2256 struct vmcb *vmcb = svm->vmcb;
2260 vmcb_gpa = svm->vmcb->save.rax;
2262 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2266 if (!nested_vmcb_checks(nested_vmcb)) {
2267 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2268 nested_vmcb->control.exit_code_hi = 0;
2269 nested_vmcb->control.exit_info_1 = 0;
2270 nested_vmcb->control.exit_info_2 = 0;
2272 nested_svm_unmap(page);
2277 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2278 nested_vmcb->save.rip,
2279 nested_vmcb->control.int_ctl,
2280 nested_vmcb->control.event_inj,
2281 nested_vmcb->control.nested_ctl);
2283 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2284 nested_vmcb->control.intercept_cr >> 16,
2285 nested_vmcb->control.intercept_exceptions,
2286 nested_vmcb->control.intercept);
2288 /* Clear internal status */
2289 kvm_clear_exception_queue(&svm->vcpu);
2290 kvm_clear_interrupt_queue(&svm->vcpu);
2293 * Save the old vmcb, so we don't need to pick what we save, but can
2294 * restore everything when a VMEXIT occurs
2296 hsave->save.es = vmcb->save.es;
2297 hsave->save.cs = vmcb->save.cs;
2298 hsave->save.ss = vmcb->save.ss;
2299 hsave->save.ds = vmcb->save.ds;
2300 hsave->save.gdtr = vmcb->save.gdtr;
2301 hsave->save.idtr = vmcb->save.idtr;
2302 hsave->save.efer = svm->vcpu.arch.efer;
2303 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2304 hsave->save.cr4 = svm->vcpu.arch.cr4;
2305 hsave->save.rflags = vmcb->save.rflags;
2306 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2307 hsave->save.rsp = vmcb->save.rsp;
2308 hsave->save.rax = vmcb->save.rax;
2310 hsave->save.cr3 = vmcb->save.cr3;
2312 hsave->save.cr3 = svm->vcpu.arch.cr3;
2314 copy_vmcb_control_area(hsave, vmcb);
2316 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2317 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2319 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2321 if (nested_vmcb->control.nested_ctl) {
2322 kvm_mmu_unload(&svm->vcpu);
2323 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2324 nested_svm_init_mmu_context(&svm->vcpu);
2327 /* Load the nested guest state */
2328 svm->vmcb->save.es = nested_vmcb->save.es;
2329 svm->vmcb->save.cs = nested_vmcb->save.cs;
2330 svm->vmcb->save.ss = nested_vmcb->save.ss;
2331 svm->vmcb->save.ds = nested_vmcb->save.ds;
2332 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2333 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2334 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2335 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2336 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2337 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2339 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2340 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2342 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2344 /* Guest paging mode is active - reset mmu */
2345 kvm_mmu_reset_context(&svm->vcpu);
2347 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2348 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2349 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2350 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2352 /* In case we don't even reach vcpu_run, the fields are not updated */
2353 svm->vmcb->save.rax = nested_vmcb->save.rax;
2354 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2355 svm->vmcb->save.rip = nested_vmcb->save.rip;
2356 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2357 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2358 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2360 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2361 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2363 /* cache intercepts */
2364 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
2365 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
2366 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2367 svm->nested.intercept = nested_vmcb->control.intercept;
2369 svm_flush_tlb(&svm->vcpu);
2370 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2371 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2372 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2374 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2376 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2377 /* We only want the cr8 intercept bits of the guest */
2378 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2379 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2382 /* We don't want to see VMMCALLs from a nested guest */
2383 clr_intercept(svm, INTERCEPT_VMMCALL);
2385 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2386 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2387 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2388 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2389 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2390 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2392 nested_svm_unmap(page);
2394 /* Enter Guest-Mode */
2395 enter_guest_mode(&svm->vcpu);
2398 * Merge guest and host intercepts - must be called with vcpu in
2399 * guest-mode to take affect here
2401 recalc_intercepts(svm);
2403 svm->nested.vmcb = vmcb_gpa;
2407 mark_all_dirty(svm->vmcb);
2412 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2414 to_vmcb->save.fs = from_vmcb->save.fs;
2415 to_vmcb->save.gs = from_vmcb->save.gs;
2416 to_vmcb->save.tr = from_vmcb->save.tr;
2417 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2418 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2419 to_vmcb->save.star = from_vmcb->save.star;
2420 to_vmcb->save.lstar = from_vmcb->save.lstar;
2421 to_vmcb->save.cstar = from_vmcb->save.cstar;
2422 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2423 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2424 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2425 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2428 static int vmload_interception(struct vcpu_svm *svm)
2430 struct vmcb *nested_vmcb;
2433 if (nested_svm_check_permissions(svm))
2436 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2437 skip_emulated_instruction(&svm->vcpu);
2439 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2443 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2444 nested_svm_unmap(page);
2449 static int vmsave_interception(struct vcpu_svm *svm)
2451 struct vmcb *nested_vmcb;
2454 if (nested_svm_check_permissions(svm))
2457 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2458 skip_emulated_instruction(&svm->vcpu);
2460 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2464 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2465 nested_svm_unmap(page);
2470 static int vmrun_interception(struct vcpu_svm *svm)
2472 if (nested_svm_check_permissions(svm))
2475 /* Save rip after vmrun instruction */
2476 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2478 if (!nested_svm_vmrun(svm))
2481 if (!nested_svm_vmrun_msrpm(svm))
2488 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2489 svm->vmcb->control.exit_code_hi = 0;
2490 svm->vmcb->control.exit_info_1 = 0;
2491 svm->vmcb->control.exit_info_2 = 0;
2493 nested_svm_vmexit(svm);
2498 static int stgi_interception(struct vcpu_svm *svm)
2500 if (nested_svm_check_permissions(svm))
2503 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2504 skip_emulated_instruction(&svm->vcpu);
2505 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2512 static int clgi_interception(struct vcpu_svm *svm)
2514 if (nested_svm_check_permissions(svm))
2517 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2518 skip_emulated_instruction(&svm->vcpu);
2522 /* After a CLGI no interrupts should come */
2523 svm_clear_vintr(svm);
2524 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2526 mark_dirty(svm->vmcb, VMCB_INTR);
2531 static int invlpga_interception(struct vcpu_svm *svm)
2533 struct kvm_vcpu *vcpu = &svm->vcpu;
2535 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2536 vcpu->arch.regs[VCPU_REGS_RAX]);
2538 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2539 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2541 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2542 skip_emulated_instruction(&svm->vcpu);
2546 static int skinit_interception(struct vcpu_svm *svm)
2548 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2550 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2554 static int xsetbv_interception(struct vcpu_svm *svm)
2556 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2557 u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
2559 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2560 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2561 skip_emulated_instruction(&svm->vcpu);
2567 static int invalid_op_interception(struct vcpu_svm *svm)
2569 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2573 static int task_switch_interception(struct vcpu_svm *svm)
2577 int int_type = svm->vmcb->control.exit_int_info &
2578 SVM_EXITINTINFO_TYPE_MASK;
2579 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2581 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2583 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2584 bool has_error_code = false;
2587 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2589 if (svm->vmcb->control.exit_info_2 &
2590 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2591 reason = TASK_SWITCH_IRET;
2592 else if (svm->vmcb->control.exit_info_2 &
2593 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2594 reason = TASK_SWITCH_JMP;
2596 reason = TASK_SWITCH_GATE;
2598 reason = TASK_SWITCH_CALL;
2600 if (reason == TASK_SWITCH_GATE) {
2602 case SVM_EXITINTINFO_TYPE_NMI:
2603 svm->vcpu.arch.nmi_injected = false;
2605 case SVM_EXITINTINFO_TYPE_EXEPT:
2606 if (svm->vmcb->control.exit_info_2 &
2607 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2608 has_error_code = true;
2610 (u32)svm->vmcb->control.exit_info_2;
2612 kvm_clear_exception_queue(&svm->vcpu);
2614 case SVM_EXITINTINFO_TYPE_INTR:
2615 kvm_clear_interrupt_queue(&svm->vcpu);
2622 if (reason != TASK_SWITCH_GATE ||
2623 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2624 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2625 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2626 skip_emulated_instruction(&svm->vcpu);
2628 if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2629 has_error_code, error_code) == EMULATE_FAIL) {
2630 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2631 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2632 svm->vcpu.run->internal.ndata = 0;
2638 static int cpuid_interception(struct vcpu_svm *svm)
2640 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2641 kvm_emulate_cpuid(&svm->vcpu);
2645 static int iret_interception(struct vcpu_svm *svm)
2647 ++svm->vcpu.stat.nmi_window_exits;
2648 clr_intercept(svm, INTERCEPT_IRET);
2649 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2653 static int invlpg_interception(struct vcpu_svm *svm)
2655 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2658 static int emulate_on_interception(struct vcpu_svm *svm)
2660 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2663 #define CR_VALID (1ULL << 63)
2665 static int cr_interception(struct vcpu_svm *svm)
2671 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2672 return emulate_on_interception(svm);
2674 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2675 return emulate_on_interception(svm);
2677 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2678 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2681 if (cr >= 16) { /* mov to cr */
2683 val = kvm_register_read(&svm->vcpu, reg);
2686 err = kvm_set_cr0(&svm->vcpu, val);
2689 err = kvm_set_cr3(&svm->vcpu, val);
2692 err = kvm_set_cr4(&svm->vcpu, val);
2695 err = kvm_set_cr8(&svm->vcpu, val);
2698 WARN(1, "unhandled write to CR%d", cr);
2699 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2702 } else { /* mov from cr */
2705 val = kvm_read_cr0(&svm->vcpu);
2708 val = svm->vcpu.arch.cr2;
2711 val = svm->vcpu.arch.cr3;
2714 val = kvm_read_cr4(&svm->vcpu);
2717 val = kvm_get_cr8(&svm->vcpu);
2720 WARN(1, "unhandled read from CR%d", cr);
2721 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2724 kvm_register_write(&svm->vcpu, reg, val);
2726 kvm_complete_insn_gp(&svm->vcpu, err);
2731 static int cr0_write_interception(struct vcpu_svm *svm)
2733 struct kvm_vcpu *vcpu = &svm->vcpu;
2736 r = cr_interception(svm);
2738 if (svm->nested.vmexit_rip) {
2739 kvm_register_write(vcpu, VCPU_REGS_RIP, svm->nested.vmexit_rip);
2740 kvm_register_write(vcpu, VCPU_REGS_RSP, svm->nested.vmexit_rsp);
2741 kvm_register_write(vcpu, VCPU_REGS_RAX, svm->nested.vmexit_rax);
2742 svm->nested.vmexit_rip = 0;
2748 static int cr8_write_interception(struct vcpu_svm *svm)
2750 struct kvm_run *kvm_run = svm->vcpu.run;
2753 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2754 /* instruction emulation calls kvm_set_cr8() */
2755 r = cr_interception(svm);
2756 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2757 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2760 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2762 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2766 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2768 struct vcpu_svm *svm = to_svm(vcpu);
2771 case MSR_IA32_TSC: {
2772 struct vmcb *vmcb = get_host_vmcb(svm);
2774 *data = vmcb->control.tsc_offset + native_read_tsc();
2778 *data = svm->vmcb->save.star;
2780 #ifdef CONFIG_X86_64
2782 *data = svm->vmcb->save.lstar;
2785 *data = svm->vmcb->save.cstar;
2787 case MSR_KERNEL_GS_BASE:
2788 *data = svm->vmcb->save.kernel_gs_base;
2790 case MSR_SYSCALL_MASK:
2791 *data = svm->vmcb->save.sfmask;
2794 case MSR_IA32_SYSENTER_CS:
2795 *data = svm->vmcb->save.sysenter_cs;
2797 case MSR_IA32_SYSENTER_EIP:
2798 *data = svm->sysenter_eip;
2800 case MSR_IA32_SYSENTER_ESP:
2801 *data = svm->sysenter_esp;
2804 * Nobody will change the following 5 values in the VMCB so we can
2805 * safely return them on rdmsr. They will always be 0 until LBRV is
2808 case MSR_IA32_DEBUGCTLMSR:
2809 *data = svm->vmcb->save.dbgctl;
2811 case MSR_IA32_LASTBRANCHFROMIP:
2812 *data = svm->vmcb->save.br_from;
2814 case MSR_IA32_LASTBRANCHTOIP:
2815 *data = svm->vmcb->save.br_to;
2817 case MSR_IA32_LASTINTFROMIP:
2818 *data = svm->vmcb->save.last_excp_from;
2820 case MSR_IA32_LASTINTTOIP:
2821 *data = svm->vmcb->save.last_excp_to;
2823 case MSR_VM_HSAVE_PA:
2824 *data = svm->nested.hsave_msr;
2827 *data = svm->nested.vm_cr_msr;
2829 case MSR_IA32_UCODE_REV:
2833 return kvm_get_msr_common(vcpu, ecx, data);
2838 static int rdmsr_interception(struct vcpu_svm *svm)
2840 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2843 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2844 trace_kvm_msr_read_ex(ecx);
2845 kvm_inject_gp(&svm->vcpu, 0);
2847 trace_kvm_msr_read(ecx, data);
2849 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2850 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2851 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2852 skip_emulated_instruction(&svm->vcpu);
2857 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2859 struct vcpu_svm *svm = to_svm(vcpu);
2860 int svm_dis, chg_mask;
2862 if (data & ~SVM_VM_CR_VALID_MASK)
2865 chg_mask = SVM_VM_CR_VALID_MASK;
2867 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2868 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2870 svm->nested.vm_cr_msr &= ~chg_mask;
2871 svm->nested.vm_cr_msr |= (data & chg_mask);
2873 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2875 /* check for svm_disable while efer.svme is set */
2876 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2882 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2884 struct vcpu_svm *svm = to_svm(vcpu);
2888 kvm_write_tsc(vcpu, data);
2891 svm->vmcb->save.star = data;
2893 #ifdef CONFIG_X86_64
2895 svm->vmcb->save.lstar = data;
2898 svm->vmcb->save.cstar = data;
2900 case MSR_KERNEL_GS_BASE:
2901 svm->vmcb->save.kernel_gs_base = data;
2903 case MSR_SYSCALL_MASK:
2904 svm->vmcb->save.sfmask = data;
2907 case MSR_IA32_SYSENTER_CS:
2908 svm->vmcb->save.sysenter_cs = data;
2910 case MSR_IA32_SYSENTER_EIP:
2911 svm->sysenter_eip = data;
2912 svm->vmcb->save.sysenter_eip = data;
2914 case MSR_IA32_SYSENTER_ESP:
2915 svm->sysenter_esp = data;
2916 svm->vmcb->save.sysenter_esp = data;
2918 case MSR_IA32_DEBUGCTLMSR:
2919 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2920 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2924 if (data & DEBUGCTL_RESERVED_BITS)
2927 svm->vmcb->save.dbgctl = data;
2928 mark_dirty(svm->vmcb, VMCB_LBR);
2929 if (data & (1ULL<<0))
2930 svm_enable_lbrv(svm);
2932 svm_disable_lbrv(svm);
2934 case MSR_VM_HSAVE_PA:
2935 svm->nested.hsave_msr = data;
2938 return svm_set_vm_cr(vcpu, data);
2940 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2943 return kvm_set_msr_common(vcpu, ecx, data);
2948 static int wrmsr_interception(struct vcpu_svm *svm)
2950 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2951 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2952 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2955 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2956 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2957 trace_kvm_msr_write_ex(ecx, data);
2958 kvm_inject_gp(&svm->vcpu, 0);
2960 trace_kvm_msr_write(ecx, data);
2961 skip_emulated_instruction(&svm->vcpu);
2966 static int msr_interception(struct vcpu_svm *svm)
2968 if (svm->vmcb->control.exit_info_1)
2969 return wrmsr_interception(svm);
2971 return rdmsr_interception(svm);
2974 static int interrupt_window_interception(struct vcpu_svm *svm)
2976 struct kvm_run *kvm_run = svm->vcpu.run;
2978 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2979 svm_clear_vintr(svm);
2980 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2981 mark_dirty(svm->vmcb, VMCB_INTR);
2983 * If the user space waits to inject interrupts, exit as soon as
2986 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2987 kvm_run->request_interrupt_window &&
2988 !kvm_cpu_has_interrupt(&svm->vcpu)) {
2989 ++svm->vcpu.stat.irq_window_exits;
2990 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2997 static int pause_interception(struct vcpu_svm *svm)
2999 kvm_vcpu_on_spin(&(svm->vcpu));
3003 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
3004 [SVM_EXIT_READ_CR0] = cr_interception,
3005 [SVM_EXIT_READ_CR3] = cr_interception,
3006 [SVM_EXIT_READ_CR4] = cr_interception,
3007 [SVM_EXIT_READ_CR8] = cr_interception,
3008 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
3009 [SVM_EXIT_WRITE_CR0] = cr0_write_interception,
3010 [SVM_EXIT_WRITE_CR3] = cr_interception,
3011 [SVM_EXIT_WRITE_CR4] = cr_interception,
3012 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
3013 [SVM_EXIT_READ_DR0] = emulate_on_interception,
3014 [SVM_EXIT_READ_DR1] = emulate_on_interception,
3015 [SVM_EXIT_READ_DR2] = emulate_on_interception,
3016 [SVM_EXIT_READ_DR3] = emulate_on_interception,
3017 [SVM_EXIT_READ_DR4] = emulate_on_interception,
3018 [SVM_EXIT_READ_DR5] = emulate_on_interception,
3019 [SVM_EXIT_READ_DR6] = emulate_on_interception,
3020 [SVM_EXIT_READ_DR7] = emulate_on_interception,
3021 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
3022 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
3023 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
3024 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
3025 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
3026 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
3027 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
3028 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
3029 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
3030 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
3031 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
3032 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
3033 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
3034 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
3035 [SVM_EXIT_INTR] = intr_interception,
3036 [SVM_EXIT_NMI] = nmi_interception,
3037 [SVM_EXIT_SMI] = nop_on_interception,
3038 [SVM_EXIT_INIT] = nop_on_interception,
3039 [SVM_EXIT_VINTR] = interrupt_window_interception,
3040 [SVM_EXIT_CPUID] = cpuid_interception,
3041 [SVM_EXIT_IRET] = iret_interception,
3042 [SVM_EXIT_INVD] = emulate_on_interception,
3043 [SVM_EXIT_PAUSE] = pause_interception,
3044 [SVM_EXIT_HLT] = halt_interception,
3045 [SVM_EXIT_INVLPG] = invlpg_interception,
3046 [SVM_EXIT_INVLPGA] = invlpga_interception,
3047 [SVM_EXIT_IOIO] = io_interception,
3048 [SVM_EXIT_MSR] = msr_interception,
3049 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
3050 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3051 [SVM_EXIT_VMRUN] = vmrun_interception,
3052 [SVM_EXIT_VMMCALL] = vmmcall_interception,
3053 [SVM_EXIT_VMLOAD] = vmload_interception,
3054 [SVM_EXIT_VMSAVE] = vmsave_interception,
3055 [SVM_EXIT_STGI] = stgi_interception,
3056 [SVM_EXIT_CLGI] = clgi_interception,
3057 [SVM_EXIT_SKINIT] = skinit_interception,
3058 [SVM_EXIT_WBINVD] = emulate_on_interception,
3059 [SVM_EXIT_MONITOR] = invalid_op_interception,
3060 [SVM_EXIT_MWAIT] = invalid_op_interception,
3061 [SVM_EXIT_XSETBV] = xsetbv_interception,
3062 [SVM_EXIT_NPF] = pf_interception,
3065 void dump_vmcb(struct kvm_vcpu *vcpu)
3067 struct vcpu_svm *svm = to_svm(vcpu);
3068 struct vmcb_control_area *control = &svm->vmcb->control;
3069 struct vmcb_save_area *save = &svm->vmcb->save;
3071 pr_err("VMCB Control Area:\n");
3072 pr_err("cr_read: %04x\n", control->intercept_cr & 0xffff);
3073 pr_err("cr_write: %04x\n", control->intercept_cr >> 16);
3074 pr_err("dr_read: %04x\n", control->intercept_dr & 0xffff);
3075 pr_err("dr_write: %04x\n", control->intercept_dr >> 16);
3076 pr_err("exceptions: %08x\n", control->intercept_exceptions);
3077 pr_err("intercepts: %016llx\n", control->intercept);
3078 pr_err("pause filter count: %d\n", control->pause_filter_count);
3079 pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa);
3080 pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa);
3081 pr_err("tsc_offset: %016llx\n", control->tsc_offset);
3082 pr_err("asid: %d\n", control->asid);
3083 pr_err("tlb_ctl: %d\n", control->tlb_ctl);
3084 pr_err("int_ctl: %08x\n", control->int_ctl);
3085 pr_err("int_vector: %08x\n", control->int_vector);
3086 pr_err("int_state: %08x\n", control->int_state);
3087 pr_err("exit_code: %08x\n", control->exit_code);
3088 pr_err("exit_info1: %016llx\n", control->exit_info_1);
3089 pr_err("exit_info2: %016llx\n", control->exit_info_2);
3090 pr_err("exit_int_info: %08x\n", control->exit_int_info);
3091 pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err);
3092 pr_err("nested_ctl: %lld\n", control->nested_ctl);
3093 pr_err("nested_cr3: %016llx\n", control->nested_cr3);
3094 pr_err("event_inj: %08x\n", control->event_inj);
3095 pr_err("event_inj_err: %08x\n", control->event_inj_err);
3096 pr_err("lbr_ctl: %lld\n", control->lbr_ctl);
3097 pr_err("next_rip: %016llx\n", control->next_rip);
3098 pr_err("VMCB State Save Area:\n");
3099 pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n",
3100 save->es.selector, save->es.attrib,
3101 save->es.limit, save->es.base);
3102 pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n",
3103 save->cs.selector, save->cs.attrib,
3104 save->cs.limit, save->cs.base);
3105 pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n",
3106 save->ss.selector, save->ss.attrib,
3107 save->ss.limit, save->ss.base);
3108 pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n",
3109 save->ds.selector, save->ds.attrib,
3110 save->ds.limit, save->ds.base);
3111 pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n",
3112 save->fs.selector, save->fs.attrib,
3113 save->fs.limit, save->fs.base);
3114 pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n",
3115 save->gs.selector, save->gs.attrib,
3116 save->gs.limit, save->gs.base);
3117 pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
3118 save->gdtr.selector, save->gdtr.attrib,
3119 save->gdtr.limit, save->gdtr.base);
3120 pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
3121 save->ldtr.selector, save->ldtr.attrib,
3122 save->ldtr.limit, save->ldtr.base);
3123 pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
3124 save->idtr.selector, save->idtr.attrib,
3125 save->idtr.limit, save->idtr.base);
3126 pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n",
3127 save->tr.selector, save->tr.attrib,
3128 save->tr.limit, save->tr.base);
3129 pr_err("cpl: %d efer: %016llx\n",
3130 save->cpl, save->efer);
3131 pr_err("cr0: %016llx cr2: %016llx\n",
3132 save->cr0, save->cr2);
3133 pr_err("cr3: %016llx cr4: %016llx\n",
3134 save->cr3, save->cr4);
3135 pr_err("dr6: %016llx dr7: %016llx\n",
3136 save->dr6, save->dr7);
3137 pr_err("rip: %016llx rflags: %016llx\n",
3138 save->rip, save->rflags);
3139 pr_err("rsp: %016llx rax: %016llx\n",
3140 save->rsp, save->rax);
3141 pr_err("star: %016llx lstar: %016llx\n",
3142 save->star, save->lstar);
3143 pr_err("cstar: %016llx sfmask: %016llx\n",
3144 save->cstar, save->sfmask);
3145 pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n",
3146 save->kernel_gs_base, save->sysenter_cs);
3147 pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n",
3148 save->sysenter_esp, save->sysenter_eip);
3149 pr_err("gpat: %016llx dbgctl: %016llx\n",
3150 save->g_pat, save->dbgctl);
3151 pr_err("br_from: %016llx br_to: %016llx\n",
3152 save->br_from, save->br_to);
3153 pr_err("excp_from: %016llx excp_to: %016llx\n",
3154 save->last_excp_from, save->last_excp_to);
3158 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3160 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3162 *info1 = control->exit_info_1;
3163 *info2 = control->exit_info_2;
3166 static int handle_exit(struct kvm_vcpu *vcpu)
3168 struct vcpu_svm *svm = to_svm(vcpu);
3169 struct kvm_run *kvm_run = vcpu->run;
3170 u32 exit_code = svm->vmcb->control.exit_code;
3172 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
3174 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3175 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3177 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3179 if (unlikely(svm->nested.exit_required)) {
3180 nested_svm_vmexit(svm);
3181 svm->nested.exit_required = false;
3186 if (is_guest_mode(vcpu)) {
3189 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3190 svm->vmcb->control.exit_info_1,
3191 svm->vmcb->control.exit_info_2,
3192 svm->vmcb->control.exit_int_info,
3193 svm->vmcb->control.exit_int_info_err);
3195 vmexit = nested_svm_exit_special(svm);
3197 if (vmexit == NESTED_EXIT_CONTINUE)
3198 vmexit = nested_svm_exit_handled(svm);
3200 if (vmexit == NESTED_EXIT_DONE)
3204 svm_complete_interrupts(svm);
3206 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3207 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3208 kvm_run->fail_entry.hardware_entry_failure_reason
3209 = svm->vmcb->control.exit_code;
3210 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3215 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3216 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3217 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3218 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3219 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3221 __func__, svm->vmcb->control.exit_int_info,
3224 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3225 || !svm_exit_handlers[exit_code]) {
3226 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3227 kvm_run->hw.hardware_exit_reason = exit_code;
3231 return svm_exit_handlers[exit_code](svm);
3234 static void reload_tss(struct kvm_vcpu *vcpu)
3236 int cpu = raw_smp_processor_id();
3238 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3239 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3243 static void pre_svm_run(struct vcpu_svm *svm)
3245 int cpu = raw_smp_processor_id();
3247 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3249 /* FIXME: handle wraparound of asid_generation */
3250 if (svm->asid_generation != sd->asid_generation)
3254 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3256 struct vcpu_svm *svm = to_svm(vcpu);
3258 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3259 vcpu->arch.hflags |= HF_NMI_MASK;
3260 set_intercept(svm, INTERCEPT_IRET);
3261 ++vcpu->stat.nmi_injections;
3264 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3266 struct vmcb_control_area *control;
3268 control = &svm->vmcb->control;
3269 control->int_vector = irq;
3270 control->int_ctl &= ~V_INTR_PRIO_MASK;
3271 control->int_ctl |= V_IRQ_MASK |
3272 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3273 mark_dirty(svm->vmcb, VMCB_INTR);
3276 static void svm_set_irq(struct kvm_vcpu *vcpu)
3278 struct vcpu_svm *svm = to_svm(vcpu);
3280 BUG_ON(!(gif_set(svm)));
3282 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3283 ++vcpu->stat.irq_injections;
3285 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3286 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3289 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3291 struct vcpu_svm *svm = to_svm(vcpu);
3293 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3300 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3303 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3305 struct vcpu_svm *svm = to_svm(vcpu);
3306 struct vmcb *vmcb = svm->vmcb;
3308 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3309 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3310 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3315 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3317 struct vcpu_svm *svm = to_svm(vcpu);
3319 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3322 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3324 struct vcpu_svm *svm = to_svm(vcpu);
3327 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3328 set_intercept(svm, INTERCEPT_IRET);
3330 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3331 clr_intercept(svm, INTERCEPT_IRET);
3335 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3337 struct vcpu_svm *svm = to_svm(vcpu);
3338 struct vmcb *vmcb = svm->vmcb;
3341 if (!gif_set(svm) ||
3342 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3345 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3347 if (is_guest_mode(vcpu))
3348 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3353 static void enable_irq_window(struct kvm_vcpu *vcpu)
3355 struct vcpu_svm *svm = to_svm(vcpu);
3358 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3359 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3360 * get that intercept, this function will be called again though and
3361 * we'll get the vintr intercept.
3363 if (gif_set(svm) && nested_svm_intr(svm)) {
3365 svm_inject_irq(svm, 0x0);
3369 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3371 struct vcpu_svm *svm = to_svm(vcpu);
3373 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3375 return; /* IRET will cause a vm exit */
3378 * Something prevents NMI from been injected. Single step over possible
3379 * problem (IRET or exception injection or interrupt shadow)
3381 svm->nmi_singlestep = true;
3382 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3383 update_db_intercept(vcpu);
3386 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3391 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3393 struct vcpu_svm *svm = to_svm(vcpu);
3395 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3396 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3398 svm->asid_generation--;
3401 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3405 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3407 struct vcpu_svm *svm = to_svm(vcpu);
3409 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3412 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3413 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3414 kvm_set_cr8(vcpu, cr8);
3418 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3420 struct vcpu_svm *svm = to_svm(vcpu);
3423 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3426 cr8 = kvm_get_cr8(vcpu);
3427 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3428 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3431 static void svm_complete_interrupts(struct vcpu_svm *svm)
3435 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3436 unsigned int3_injected = svm->int3_injected;
3438 svm->int3_injected = 0;
3440 if (svm->vcpu.arch.hflags & HF_IRET_MASK) {
3441 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3442 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3445 svm->vcpu.arch.nmi_injected = false;
3446 kvm_clear_exception_queue(&svm->vcpu);
3447 kvm_clear_interrupt_queue(&svm->vcpu);
3449 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3452 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3454 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3455 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3458 case SVM_EXITINTINFO_TYPE_NMI:
3459 svm->vcpu.arch.nmi_injected = true;
3461 case SVM_EXITINTINFO_TYPE_EXEPT:
3463 * In case of software exceptions, do not reinject the vector,
3464 * but re-execute the instruction instead. Rewind RIP first
3465 * if we emulated INT3 before.
3467 if (kvm_exception_is_soft(vector)) {
3468 if (vector == BP_VECTOR && int3_injected &&
3469 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3470 kvm_rip_write(&svm->vcpu,
3471 kvm_rip_read(&svm->vcpu) -
3475 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3476 u32 err = svm->vmcb->control.exit_int_info_err;
3477 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3480 kvm_requeue_exception(&svm->vcpu, vector);
3482 case SVM_EXITINTINFO_TYPE_INTR:
3483 kvm_queue_interrupt(&svm->vcpu, vector, false);
3490 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3492 struct vcpu_svm *svm = to_svm(vcpu);
3493 struct vmcb_control_area *control = &svm->vmcb->control;
3495 control->exit_int_info = control->event_inj;
3496 control->exit_int_info_err = control->event_inj_err;
3497 control->event_inj = 0;
3498 svm_complete_interrupts(svm);
3501 #ifdef CONFIG_X86_64
3507 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3509 struct vcpu_svm *svm = to_svm(vcpu);
3511 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3512 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3513 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3516 * A vmexit emulation is required before the vcpu can be executed
3519 if (unlikely(svm->nested.exit_required))
3524 sync_lapic_to_cr8(vcpu);
3526 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3533 "push %%"R"bp; \n\t"
3534 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3535 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3536 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3537 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3538 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3539 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3540 #ifdef CONFIG_X86_64
3541 "mov %c[r8](%[svm]), %%r8 \n\t"
3542 "mov %c[r9](%[svm]), %%r9 \n\t"
3543 "mov %c[r10](%[svm]), %%r10 \n\t"
3544 "mov %c[r11](%[svm]), %%r11 \n\t"
3545 "mov %c[r12](%[svm]), %%r12 \n\t"
3546 "mov %c[r13](%[svm]), %%r13 \n\t"
3547 "mov %c[r14](%[svm]), %%r14 \n\t"
3548 "mov %c[r15](%[svm]), %%r15 \n\t"
3551 /* Enter guest mode */
3553 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3554 __ex(SVM_VMLOAD) "\n\t"
3555 __ex(SVM_VMRUN) "\n\t"
3556 __ex(SVM_VMSAVE) "\n\t"
3559 /* Save guest registers, load host registers */
3560 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3561 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3562 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3563 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3564 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3565 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3566 #ifdef CONFIG_X86_64
3567 "mov %%r8, %c[r8](%[svm]) \n\t"
3568 "mov %%r9, %c[r9](%[svm]) \n\t"
3569 "mov %%r10, %c[r10](%[svm]) \n\t"
3570 "mov %%r11, %c[r11](%[svm]) \n\t"
3571 "mov %%r12, %c[r12](%[svm]) \n\t"
3572 "mov %%r13, %c[r13](%[svm]) \n\t"
3573 "mov %%r14, %c[r14](%[svm]) \n\t"
3574 "mov %%r15, %c[r15](%[svm]) \n\t"
3579 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3580 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3581 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3582 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3583 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3584 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3585 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3586 #ifdef CONFIG_X86_64
3587 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3588 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3589 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3590 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3591 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3592 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3593 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3594 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3597 , R"bx", R"cx", R"dx", R"si", R"di"
3598 #ifdef CONFIG_X86_64
3599 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3603 #ifdef CONFIG_X86_64
3604 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3606 loadsegment(fs, svm->host.fs);
3611 local_irq_disable();
3615 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3616 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3617 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3618 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3620 sync_cr8_to_lapic(vcpu);
3624 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3626 /* if exit due to PF check for async PF */
3627 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3628 svm->apf_reason = kvm_read_and_reset_pf_reason();
3631 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3632 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3636 * We need to handle MC intercepts here before the vcpu has a chance to
3637 * change the physical cpu
3639 if (unlikely(svm->vmcb->control.exit_code ==
3640 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3641 svm_handle_mce(svm);
3643 mark_all_clean(svm->vmcb);
3648 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3650 struct vcpu_svm *svm = to_svm(vcpu);
3652 svm->vmcb->save.cr3 = root;
3653 mark_dirty(svm->vmcb, VMCB_CR);
3654 svm_flush_tlb(vcpu);
3657 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3659 struct vcpu_svm *svm = to_svm(vcpu);
3661 svm->vmcb->control.nested_cr3 = root;
3662 mark_dirty(svm->vmcb, VMCB_NPT);
3664 /* Also sync guest cr3 here in case we live migrate */
3665 svm->vmcb->save.cr3 = vcpu->arch.cr3;
3666 mark_dirty(svm->vmcb, VMCB_CR);
3668 svm_flush_tlb(vcpu);
3671 static int is_disabled(void)
3675 rdmsrl(MSR_VM_CR, vm_cr);
3676 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3683 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3686 * Patch in the VMMCALL instruction:
3688 hypercall[0] = 0x0f;
3689 hypercall[1] = 0x01;
3690 hypercall[2] = 0xd9;
3693 static void svm_check_processor_compat(void *rtn)
3698 static bool svm_cpu_has_accelerated_tpr(void)
3703 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3708 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3712 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3717 entry->ecx |= (1 << 2); /* Set SVM bit */
3720 entry->eax = 1; /* SVM revision 1 */
3721 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3722 ASID emulation to nested SVM */
3723 entry->ecx = 0; /* Reserved */
3724 entry->edx = 0; /* Per default do not support any
3725 additional features */
3727 /* Support next_rip if host supports it */
3728 if (boot_cpu_has(X86_FEATURE_NRIPS))
3729 entry->edx |= SVM_FEATURE_NRIP;
3731 /* Support NPT for the guest if enabled */
3733 entry->edx |= SVM_FEATURE_NPT;
3739 static const struct trace_print_flags svm_exit_reasons_str[] = {
3740 { SVM_EXIT_READ_CR0, "read_cr0" },
3741 { SVM_EXIT_READ_CR3, "read_cr3" },
3742 { SVM_EXIT_READ_CR4, "read_cr4" },
3743 { SVM_EXIT_READ_CR8, "read_cr8" },
3744 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3745 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3746 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3747 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3748 { SVM_EXIT_READ_DR0, "read_dr0" },
3749 { SVM_EXIT_READ_DR1, "read_dr1" },
3750 { SVM_EXIT_READ_DR2, "read_dr2" },
3751 { SVM_EXIT_READ_DR3, "read_dr3" },
3752 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3753 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3754 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3755 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3756 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3757 { SVM_EXIT_WRITE_DR7, "write_dr7" },
3758 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3759 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3760 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3761 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3762 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3763 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3764 { SVM_EXIT_INTR, "interrupt" },
3765 { SVM_EXIT_NMI, "nmi" },
3766 { SVM_EXIT_SMI, "smi" },
3767 { SVM_EXIT_INIT, "init" },
3768 { SVM_EXIT_VINTR, "vintr" },
3769 { SVM_EXIT_CPUID, "cpuid" },
3770 { SVM_EXIT_INVD, "invd" },
3771 { SVM_EXIT_HLT, "hlt" },
3772 { SVM_EXIT_INVLPG, "invlpg" },
3773 { SVM_EXIT_INVLPGA, "invlpga" },
3774 { SVM_EXIT_IOIO, "io" },
3775 { SVM_EXIT_MSR, "msr" },
3776 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3777 { SVM_EXIT_SHUTDOWN, "shutdown" },
3778 { SVM_EXIT_VMRUN, "vmrun" },
3779 { SVM_EXIT_VMMCALL, "hypercall" },
3780 { SVM_EXIT_VMLOAD, "vmload" },
3781 { SVM_EXIT_VMSAVE, "vmsave" },
3782 { SVM_EXIT_STGI, "stgi" },
3783 { SVM_EXIT_CLGI, "clgi" },
3784 { SVM_EXIT_SKINIT, "skinit" },
3785 { SVM_EXIT_WBINVD, "wbinvd" },
3786 { SVM_EXIT_MONITOR, "monitor" },
3787 { SVM_EXIT_MWAIT, "mwait" },
3788 { SVM_EXIT_XSETBV, "xsetbv" },
3789 { SVM_EXIT_NPF, "npf" },
3793 static int svm_get_lpage_level(void)
3795 return PT_PDPE_LEVEL;
3798 static bool svm_rdtscp_supported(void)
3803 static bool svm_has_wbinvd_exit(void)
3808 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3810 struct vcpu_svm *svm = to_svm(vcpu);
3812 set_exception_intercept(svm, NM_VECTOR);
3813 update_cr0_intercept(svm);
3816 static struct kvm_x86_ops svm_x86_ops = {
3817 .cpu_has_kvm_support = has_svm,
3818 .disabled_by_bios = is_disabled,
3819 .hardware_setup = svm_hardware_setup,
3820 .hardware_unsetup = svm_hardware_unsetup,
3821 .check_processor_compatibility = svm_check_processor_compat,
3822 .hardware_enable = svm_hardware_enable,
3823 .hardware_disable = svm_hardware_disable,
3824 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3826 .vcpu_create = svm_create_vcpu,
3827 .vcpu_free = svm_free_vcpu,
3828 .vcpu_reset = svm_vcpu_reset,
3830 .prepare_guest_switch = svm_prepare_guest_switch,
3831 .vcpu_load = svm_vcpu_load,
3832 .vcpu_put = svm_vcpu_put,
3834 .set_guest_debug = svm_guest_debug,
3835 .get_msr = svm_get_msr,
3836 .set_msr = svm_set_msr,
3837 .get_segment_base = svm_get_segment_base,
3838 .get_segment = svm_get_segment,
3839 .set_segment = svm_set_segment,
3840 .get_cpl = svm_get_cpl,
3841 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3842 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3843 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3844 .set_cr0 = svm_set_cr0,
3845 .set_cr3 = svm_set_cr3,
3846 .set_cr4 = svm_set_cr4,
3847 .set_efer = svm_set_efer,
3848 .get_idt = svm_get_idt,
3849 .set_idt = svm_set_idt,
3850 .get_gdt = svm_get_gdt,
3851 .set_gdt = svm_set_gdt,
3852 .set_dr7 = svm_set_dr7,
3853 .cache_reg = svm_cache_reg,
3854 .get_rflags = svm_get_rflags,
3855 .set_rflags = svm_set_rflags,
3856 .fpu_activate = svm_fpu_activate,
3857 .fpu_deactivate = svm_fpu_deactivate,
3859 .tlb_flush = svm_flush_tlb,
3861 .run = svm_vcpu_run,
3862 .handle_exit = handle_exit,
3863 .skip_emulated_instruction = skip_emulated_instruction,
3864 .set_interrupt_shadow = svm_set_interrupt_shadow,
3865 .get_interrupt_shadow = svm_get_interrupt_shadow,
3866 .patch_hypercall = svm_patch_hypercall,
3867 .set_irq = svm_set_irq,
3868 .set_nmi = svm_inject_nmi,
3869 .queue_exception = svm_queue_exception,
3870 .cancel_injection = svm_cancel_injection,
3871 .interrupt_allowed = svm_interrupt_allowed,
3872 .nmi_allowed = svm_nmi_allowed,
3873 .get_nmi_mask = svm_get_nmi_mask,
3874 .set_nmi_mask = svm_set_nmi_mask,
3875 .enable_nmi_window = enable_nmi_window,
3876 .enable_irq_window = enable_irq_window,
3877 .update_cr8_intercept = update_cr8_intercept,
3879 .set_tss_addr = svm_set_tss_addr,
3880 .get_tdp_level = get_npt_level,
3881 .get_mt_mask = svm_get_mt_mask,
3883 .get_exit_info = svm_get_exit_info,
3884 .exit_reasons_str = svm_exit_reasons_str,
3886 .get_lpage_level = svm_get_lpage_level,
3888 .cpuid_update = svm_cpuid_update,
3890 .rdtscp_supported = svm_rdtscp_supported,
3892 .set_supported_cpuid = svm_set_supported_cpuid,
3894 .has_wbinvd_exit = svm_has_wbinvd_exit,
3896 .write_tsc_offset = svm_write_tsc_offset,
3897 .adjust_tsc_offset = svm_adjust_tsc_offset,
3899 .set_tdp_cr3 = set_tdp_cr3,
3902 static int __init svm_init(void)
3904 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3905 __alignof__(struct vcpu_svm), THIS_MODULE);
3908 static void __exit svm_exit(void)
3913 module_init(svm_init)
3914 module_exit(svm_exit)