1 #define pr_fmt(fmt) "SVM: " fmt
3 #include <linux/kvm_host.h>
7 #include "kvm_cache_regs.h"
12 #include <linux/module.h>
13 #include <linux/mod_devicetable.h>
14 #include <linux/kernel.h>
15 #include <linux/vmalloc.h>
16 #include <linux/highmem.h>
17 #include <linux/amd-iommu.h>
18 #include <linux/sched.h>
19 #include <linux/trace_events.h>
20 #include <linux/slab.h>
21 #include <linux/hashtable.h>
22 #include <linux/objtool.h>
23 #include <linux/psp-sev.h>
24 #include <linux/file.h>
25 #include <linux/pagemap.h>
26 #include <linux/swap.h>
27 #include <linux/rwsem.h>
30 #include <asm/perf_event.h>
31 #include <asm/tlbflush.h>
33 #include <asm/debugreg.h>
34 #include <asm/kvm_para.h>
35 #include <asm/irq_remapping.h>
36 #include <asm/spec-ctrl.h>
37 #include <asm/cpu_device_id.h>
38 #include <asm/traps.h>
40 #include <asm/virtext.h>
46 #include "kvm_onhyperv.h"
47 #include "svm_onhyperv.h"
49 MODULE_AUTHOR("Qumranet");
50 MODULE_LICENSE("GPL");
53 static const struct x86_cpu_id svm_cpu_id[] = {
54 X86_MATCH_FEATURE(X86_FEATURE_SVM, NULL),
57 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
60 #define SEG_TYPE_LDT 2
61 #define SEG_TYPE_BUSY_TSS16 3
63 #define SVM_FEATURE_LBRV (1 << 1)
64 #define SVM_FEATURE_SVML (1 << 2)
65 #define SVM_FEATURE_TSC_RATE (1 << 4)
66 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
67 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
68 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
69 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
71 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
73 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
74 #define TSC_RATIO_MIN 0x0000000000000001ULL
75 #define TSC_RATIO_MAX 0x000000ffffffffffULL
77 static bool erratum_383_found __read_mostly;
79 u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
82 * Set osvw_len to higher value when updated Revision Guides
83 * are published and we know what the new status bits are
85 static uint64_t osvw_len = 4, osvw_status;
87 static DEFINE_PER_CPU(u64, current_tsc_ratio);
88 #define TSC_RATIO_DEFAULT 0x0100000000ULL
90 static const struct svm_direct_access_msrs {
91 u32 index; /* Index of the MSR */
92 bool always; /* True if intercept is initially cleared */
93 } direct_access_msrs[MAX_DIRECT_ACCESS_MSRS] = {
94 { .index = MSR_STAR, .always = true },
95 { .index = MSR_IA32_SYSENTER_CS, .always = true },
96 { .index = MSR_IA32_SYSENTER_EIP, .always = false },
97 { .index = MSR_IA32_SYSENTER_ESP, .always = false },
99 { .index = MSR_GS_BASE, .always = true },
100 { .index = MSR_FS_BASE, .always = true },
101 { .index = MSR_KERNEL_GS_BASE, .always = true },
102 { .index = MSR_LSTAR, .always = true },
103 { .index = MSR_CSTAR, .always = true },
104 { .index = MSR_SYSCALL_MASK, .always = true },
106 { .index = MSR_IA32_SPEC_CTRL, .always = false },
107 { .index = MSR_IA32_PRED_CMD, .always = false },
108 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
109 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
110 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
111 { .index = MSR_IA32_LASTINTTOIP, .always = false },
112 { .index = MSR_EFER, .always = false },
113 { .index = MSR_IA32_CR_PAT, .always = false },
114 { .index = MSR_AMD64_SEV_ES_GHCB, .always = true },
115 { .index = MSR_INVALID, .always = false },
119 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
120 * pause_filter_count: On processors that support Pause filtering(indicated
121 * by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
122 * count value. On VMRUN this value is loaded into an internal counter.
123 * Each time a pause instruction is executed, this counter is decremented
124 * until it reaches zero at which time a #VMEXIT is generated if pause
125 * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause
126 * Intercept Filtering for more details.
127 * This also indicate if ple logic enabled.
129 * pause_filter_thresh: In addition, some processor families support advanced
130 * pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
131 * the amount of time a guest is allowed to execute in a pause loop.
132 * In this mode, a 16-bit pause filter threshold field is added in the
133 * VMCB. The threshold value is a cycle count that is used to reset the
134 * pause counter. As with simple pause filtering, VMRUN loads the pause
135 * count value from VMCB into an internal counter. Then, on each pause
136 * instruction the hardware checks the elapsed number of cycles since
137 * the most recent pause instruction against the pause filter threshold.
138 * If the elapsed cycle count is greater than the pause filter threshold,
139 * then the internal pause count is reloaded from the VMCB and execution
140 * continues. If the elapsed cycle count is less than the pause filter
141 * threshold, then the internal pause count is decremented. If the count
142 * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
143 * triggered. If advanced pause filtering is supported and pause filter
144 * threshold field is set to zero, the filter will operate in the simpler,
148 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
149 module_param(pause_filter_thresh, ushort, 0444);
151 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
152 module_param(pause_filter_count, ushort, 0444);
154 /* Default doubles per-vcpu window every exit. */
155 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
156 module_param(pause_filter_count_grow, ushort, 0444);
158 /* Default resets per-vcpu window every exit to pause_filter_count. */
159 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
160 module_param(pause_filter_count_shrink, ushort, 0444);
162 /* Default is to compute the maximum so we can never overflow. */
163 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
164 module_param(pause_filter_count_max, ushort, 0444);
167 * Use nested page tables by default. Note, NPT may get forced off by
168 * svm_hardware_setup() if it's unsupported by hardware or the host kernel.
170 bool npt_enabled = true;
171 module_param_named(npt, npt_enabled, bool, 0444);
173 /* allow nested virtualization in KVM/SVM */
174 static int nested = true;
175 module_param(nested, int, S_IRUGO);
177 /* enable/disable Next RIP Save */
178 static int nrips = true;
179 module_param(nrips, int, 0444);
181 /* enable/disable Virtual VMLOAD VMSAVE */
182 static int vls = true;
183 module_param(vls, int, 0444);
185 /* enable/disable Virtual GIF */
186 static int vgif = true;
187 module_param(vgif, int, 0444);
190 * enable / disable AVIC. Because the defaults differ for APICv
191 * support between VMX and SVM we cannot use module_param_named.
194 module_param(avic, bool, 0444);
196 bool __read_mostly dump_invalid_vmcb;
197 module_param(dump_invalid_vmcb, bool, 0644);
200 bool intercept_smi = true;
201 module_param(intercept_smi, bool, 0444);
204 static bool svm_gp_erratum_intercept = true;
206 static u8 rsm_ins_bytes[] = "\x0f\xaa";
208 static unsigned long iopm_base;
210 struct kvm_ldttss_desc {
213 unsigned base1:8, type:5, dpl:2, p:1;
214 unsigned limit1:4, zero0:3, g:1, base2:8;
217 } __attribute__((packed));
219 DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
222 * Only MSR_TSC_AUX is switched via the user return hook. EFER is switched via
223 * the VMCB, and the SYSCALL/SYSENTER MSRs are handled by VMLOAD/VMSAVE.
225 * RDTSCP and RDPID are not used in the kernel, specifically to allow KVM to
226 * defer the restoration of TSC_AUX until the CPU returns to userspace.
228 static int tsc_aux_uret_slot __read_mostly = -1;
230 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
232 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
233 #define MSRS_RANGE_SIZE 2048
234 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
236 u32 svm_msrpm_offset(u32 msr)
241 for (i = 0; i < NUM_MSR_MAPS; i++) {
242 if (msr < msrpm_ranges[i] ||
243 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
246 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
247 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
249 /* Now we have the u8 offset - but need the u32 offset */
253 /* MSR not in any range */
257 #define MAX_INST_SIZE 15
259 static int get_max_npt_level(void)
262 return pgtable_l5_enabled() ? PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
264 return PT32E_ROOT_LEVEL;
268 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
270 struct vcpu_svm *svm = to_svm(vcpu);
271 u64 old_efer = vcpu->arch.efer;
272 vcpu->arch.efer = efer;
275 /* Shadow paging assumes NX to be available. */
278 if (!(efer & EFER_LMA))
282 if ((old_efer & EFER_SVME) != (efer & EFER_SVME)) {
283 if (!(efer & EFER_SVME)) {
284 svm_leave_nested(svm);
285 svm_set_gif(svm, true);
286 /* #GP intercept is still needed for vmware backdoor */
287 if (!enable_vmware_backdoor)
288 clr_exception_intercept(svm, GP_VECTOR);
291 * Free the nested guest state, unless we are in SMM.
292 * In this case we will return to the nested guest
293 * as soon as we leave SMM.
296 svm_free_nested(svm);
299 int ret = svm_allocate_nested(svm);
302 vcpu->arch.efer = old_efer;
306 if (svm_gp_erratum_intercept)
307 set_exception_intercept(svm, GP_VECTOR);
311 svm->vmcb->save.efer = efer | EFER_SVME;
312 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
316 static int is_external_interrupt(u32 info)
318 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
319 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
322 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
324 struct vcpu_svm *svm = to_svm(vcpu);
327 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
328 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
332 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
334 struct vcpu_svm *svm = to_svm(vcpu);
337 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
339 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
343 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
345 struct vcpu_svm *svm = to_svm(vcpu);
348 * SEV-ES does not expose the next RIP. The RIP update is controlled by
349 * the type of exit and the #VC handler in the guest.
351 if (sev_es_guest(vcpu->kvm))
354 if (nrips && svm->vmcb->control.next_rip != 0) {
355 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
356 svm->next_rip = svm->vmcb->control.next_rip;
359 if (!svm->next_rip) {
360 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
363 kvm_rip_write(vcpu, svm->next_rip);
367 svm_set_interrupt_shadow(vcpu, 0);
372 static void svm_queue_exception(struct kvm_vcpu *vcpu)
374 struct vcpu_svm *svm = to_svm(vcpu);
375 unsigned nr = vcpu->arch.exception.nr;
376 bool has_error_code = vcpu->arch.exception.has_error_code;
377 u32 error_code = vcpu->arch.exception.error_code;
379 kvm_deliver_exception_payload(vcpu);
381 if (nr == BP_VECTOR && !nrips) {
382 unsigned long rip, old_rip = kvm_rip_read(vcpu);
385 * For guest debugging where we have to reinject #BP if some
386 * INT3 is guest-owned:
387 * Emulate nRIP by moving RIP forward. Will fail if injection
388 * raises a fault that is not intercepted. Still better than
389 * failing in all cases.
391 (void)skip_emulated_instruction(vcpu);
392 rip = kvm_rip_read(vcpu);
393 svm->int3_rip = rip + svm->vmcb->save.cs.base;
394 svm->int3_injected = rip - old_rip;
397 svm->vmcb->control.event_inj = nr
399 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
400 | SVM_EVTINJ_TYPE_EXEPT;
401 svm->vmcb->control.event_inj_err = error_code;
404 static void svm_init_erratum_383(void)
410 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
413 /* Use _safe variants to not break nested virtualization */
414 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
420 low = lower_32_bits(val);
421 high = upper_32_bits(val);
423 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
425 erratum_383_found = true;
428 static void svm_init_osvw(struct kvm_vcpu *vcpu)
431 * Guests should see errata 400 and 415 as fixed (assuming that
432 * HLT and IO instructions are intercepted).
434 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
435 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
438 * By increasing VCPU's osvw.length to 3 we are telling the guest that
439 * all osvw.status bits inside that length, including bit 0 (which is
440 * reserved for erratum 298), are valid. However, if host processor's
441 * osvw_len is 0 then osvw_status[0] carries no information. We need to
442 * be conservative here and therefore we tell the guest that erratum 298
443 * is present (because we really don't know).
445 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
446 vcpu->arch.osvw.status |= 1;
449 static int has_svm(void)
453 if (!cpu_has_svm(&msg)) {
454 printk(KERN_INFO "has_svm: %s\n", msg);
459 pr_info("KVM is unsupported when running as an SEV guest\n");
466 static void svm_hardware_disable(void)
468 /* Make sure we clean up behind us */
469 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
470 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
474 amd_pmu_disable_virt();
477 static int svm_hardware_enable(void)
480 struct svm_cpu_data *sd;
482 struct desc_struct *gdt;
483 int me = raw_smp_processor_id();
485 rdmsrl(MSR_EFER, efer);
486 if (efer & EFER_SVME)
490 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
493 sd = per_cpu(svm_data, me);
495 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
499 sd->asid_generation = 1;
500 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
501 sd->next_asid = sd->max_asid + 1;
502 sd->min_asid = max_sev_asid + 1;
504 gdt = get_current_gdt_rw();
505 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
507 wrmsrl(MSR_EFER, efer | EFER_SVME);
509 wrmsrl(MSR_VM_HSAVE_PA, __sme_page_pa(sd->save_area));
511 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
512 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
513 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
520 * Note that it is possible to have a system with mixed processor
521 * revisions and therefore different OSVW bits. If bits are not the same
522 * on different processors then choose the worst case (i.e. if erratum
523 * is present on one processor and not on another then assume that the
524 * erratum is present everywhere).
526 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
527 uint64_t len, status = 0;
530 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
532 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
536 osvw_status = osvw_len = 0;
540 osvw_status |= status;
541 osvw_status &= (1ULL << osvw_len) - 1;
544 osvw_status = osvw_len = 0;
546 svm_init_erratum_383();
548 amd_pmu_enable_virt();
553 static void svm_cpu_uninit(int cpu)
555 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
560 per_cpu(svm_data, cpu) = NULL;
561 kfree(sd->sev_vmcbs);
562 __free_page(sd->save_area);
566 static int svm_cpu_init(int cpu)
568 struct svm_cpu_data *sd;
571 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
575 sd->save_area = alloc_page(GFP_KERNEL);
579 clear_page(page_address(sd->save_area));
581 ret = sev_cpu_init(sd);
585 per_cpu(svm_data, cpu) = sd;
590 __free_page(sd->save_area);
597 static int direct_access_msr_slot(u32 msr)
601 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
602 if (direct_access_msrs[i].index == msr)
608 static void set_shadow_msr_intercept(struct kvm_vcpu *vcpu, u32 msr, int read,
611 struct vcpu_svm *svm = to_svm(vcpu);
612 int slot = direct_access_msr_slot(msr);
617 /* Set the shadow bitmaps to the desired intercept states */
619 set_bit(slot, svm->shadow_msr_intercept.read);
621 clear_bit(slot, svm->shadow_msr_intercept.read);
624 set_bit(slot, svm->shadow_msr_intercept.write);
626 clear_bit(slot, svm->shadow_msr_intercept.write);
629 static bool valid_msr_intercept(u32 index)
631 return direct_access_msr_slot(index) != -ENOENT;
634 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
641 msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
644 offset = svm_msrpm_offset(msr);
645 bit_write = 2 * (msr & 0x0f) + 1;
648 BUG_ON(offset == MSR_INVALID);
650 return !!test_bit(bit_write, &tmp);
653 static void set_msr_interception_bitmap(struct kvm_vcpu *vcpu, u32 *msrpm,
654 u32 msr, int read, int write)
656 u8 bit_read, bit_write;
661 * If this warning triggers extend the direct_access_msrs list at the
662 * beginning of the file
664 WARN_ON(!valid_msr_intercept(msr));
666 /* Enforce non allowed MSRs to trap */
667 if (read && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ))
670 if (write && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE))
673 offset = svm_msrpm_offset(msr);
674 bit_read = 2 * (msr & 0x0f);
675 bit_write = 2 * (msr & 0x0f) + 1;
678 BUG_ON(offset == MSR_INVALID);
680 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
681 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
685 svm_hv_vmcb_dirty_nested_enlightenments(vcpu);
689 void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr,
692 set_shadow_msr_intercept(vcpu, msr, read, write);
693 set_msr_interception_bitmap(vcpu, msrpm, msr, read, write);
696 u32 *svm_vcpu_alloc_msrpm(void)
698 unsigned int order = get_order(MSRPM_SIZE);
699 struct page *pages = alloc_pages(GFP_KERNEL_ACCOUNT, order);
705 msrpm = page_address(pages);
706 memset(msrpm, 0xff, PAGE_SIZE * (1 << order));
711 void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm)
715 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
716 if (!direct_access_msrs[i].always)
718 set_msr_interception(vcpu, msrpm, direct_access_msrs[i].index, 1, 1);
723 void svm_vcpu_free_msrpm(u32 *msrpm)
725 __free_pages(virt_to_page(msrpm), get_order(MSRPM_SIZE));
728 static void svm_msr_filter_changed(struct kvm_vcpu *vcpu)
730 struct vcpu_svm *svm = to_svm(vcpu);
734 * Set intercept permissions for all direct access MSRs again. They
735 * will automatically get filtered through the MSR filter, so we are
736 * back in sync after this.
738 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
739 u32 msr = direct_access_msrs[i].index;
740 u32 read = test_bit(i, svm->shadow_msr_intercept.read);
741 u32 write = test_bit(i, svm->shadow_msr_intercept.write);
743 set_msr_interception_bitmap(vcpu, svm->msrpm, msr, read, write);
747 static void add_msr_offset(u32 offset)
751 for (i = 0; i < MSRPM_OFFSETS; ++i) {
753 /* Offset already in list? */
754 if (msrpm_offsets[i] == offset)
757 /* Slot used by another offset? */
758 if (msrpm_offsets[i] != MSR_INVALID)
761 /* Add offset to list */
762 msrpm_offsets[i] = offset;
768 * If this BUG triggers the msrpm_offsets table has an overflow. Just
769 * increase MSRPM_OFFSETS in this case.
774 static void init_msrpm_offsets(void)
778 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
780 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
783 offset = svm_msrpm_offset(direct_access_msrs[i].index);
784 BUG_ON(offset == MSR_INVALID);
786 add_msr_offset(offset);
790 static void svm_enable_lbrv(struct kvm_vcpu *vcpu)
792 struct vcpu_svm *svm = to_svm(vcpu);
794 svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
795 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
796 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
797 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
798 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
801 static void svm_disable_lbrv(struct kvm_vcpu *vcpu)
803 struct vcpu_svm *svm = to_svm(vcpu);
805 svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
806 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
807 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
808 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
809 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
812 void disable_nmi_singlestep(struct vcpu_svm *svm)
814 svm->nmi_singlestep = false;
816 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
817 /* Clear our flags if they were not set by the guest */
818 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
819 svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
820 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
821 svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
825 static void grow_ple_window(struct kvm_vcpu *vcpu)
827 struct vcpu_svm *svm = to_svm(vcpu);
828 struct vmcb_control_area *control = &svm->vmcb->control;
829 int old = control->pause_filter_count;
831 control->pause_filter_count = __grow_ple_window(old,
833 pause_filter_count_grow,
834 pause_filter_count_max);
836 if (control->pause_filter_count != old) {
837 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
838 trace_kvm_ple_window_update(vcpu->vcpu_id,
839 control->pause_filter_count, old);
843 static void shrink_ple_window(struct kvm_vcpu *vcpu)
845 struct vcpu_svm *svm = to_svm(vcpu);
846 struct vmcb_control_area *control = &svm->vmcb->control;
847 int old = control->pause_filter_count;
849 control->pause_filter_count =
850 __shrink_ple_window(old,
852 pause_filter_count_shrink,
854 if (control->pause_filter_count != old) {
855 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
856 trace_kvm_ple_window_update(vcpu->vcpu_id,
857 control->pause_filter_count, old);
862 * The default MMIO mask is a single bit (excluding the present bit),
863 * which could conflict with the memory encryption bit. Check for
864 * memory encryption support and override the default MMIO mask if
865 * memory encryption is enabled.
867 static __init void svm_adjust_mmio_mask(void)
869 unsigned int enc_bit, mask_bit;
872 /* If there is no memory encryption support, use existing mask */
873 if (cpuid_eax(0x80000000) < 0x8000001f)
876 /* If memory encryption is not enabled, use existing mask */
877 rdmsrl(MSR_AMD64_SYSCFG, msr);
878 if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT))
881 enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
882 mask_bit = boot_cpu_data.x86_phys_bits;
884 /* Increment the mask bit if it is the same as the encryption bit */
885 if (enc_bit == mask_bit)
889 * If the mask bit location is below 52, then some bits above the
890 * physical addressing limit will always be reserved, so use the
891 * rsvd_bits() function to generate the mask. This mask, along with
892 * the present bit, will be used to generate a page fault with
895 * If the mask bit location is 52 (or above), then clear the mask.
897 mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
899 kvm_mmu_set_mmio_spte_mask(mask, mask, PT_WRITABLE_MASK | PT_USER_MASK);
902 static void svm_hardware_teardown(void)
906 sev_hardware_teardown();
908 for_each_possible_cpu(cpu)
911 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT),
912 get_order(IOPM_SIZE));
916 static __init void svm_set_cpu_caps(void)
922 /* CPUID 0x80000001 and 0x8000000A (SVM features) */
924 kvm_cpu_cap_set(X86_FEATURE_SVM);
927 kvm_cpu_cap_set(X86_FEATURE_NRIPS);
930 kvm_cpu_cap_set(X86_FEATURE_NPT);
932 /* Nested VM can receive #VMEXIT instead of triggering #GP */
933 kvm_cpu_cap_set(X86_FEATURE_SVME_ADDR_CHK);
936 /* CPUID 0x80000008 */
937 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
938 boot_cpu_has(X86_FEATURE_AMD_SSBD))
939 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
941 /* CPUID 0x8000001F (SME/SEV features) */
945 static __init int svm_hardware_setup(void)
948 struct page *iopm_pages;
951 unsigned int order = get_order(IOPM_SIZE);
954 * NX is required for shadow paging and for NPT if the NX huge pages
955 * mitigation is enabled.
957 if (!boot_cpu_has(X86_FEATURE_NX)) {
958 pr_err_ratelimited("NX (Execute Disable) not supported\n");
961 kvm_enable_efer_bits(EFER_NX);
963 iopm_pages = alloc_pages(GFP_KERNEL, order);
968 iopm_va = page_address(iopm_pages);
969 memset(iopm_va, 0xff, PAGE_SIZE * (1 << order));
970 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
972 init_msrpm_offsets();
974 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
976 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
977 kvm_enable_efer_bits(EFER_FFXSR);
979 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
980 kvm_has_tsc_control = true;
981 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
982 kvm_tsc_scaling_ratio_frac_bits = 32;
985 tsc_aux_uret_slot = kvm_add_user_return_msr(MSR_TSC_AUX);
987 /* Check for pause filtering support */
988 if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
989 pause_filter_count = 0;
990 pause_filter_thresh = 0;
991 } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
992 pause_filter_thresh = 0;
996 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
997 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1001 * KVM's MMU doesn't support using 2-level paging for itself, and thus
1002 * NPT isn't supported if the host is using 2-level paging since host
1003 * CR4 is unchanged on VMRUN.
1005 if (!IS_ENABLED(CONFIG_X86_64) && !IS_ENABLED(CONFIG_X86_PAE))
1006 npt_enabled = false;
1008 if (!boot_cpu_has(X86_FEATURE_NPT))
1009 npt_enabled = false;
1011 /* Force VM NPT level equal to the host's max NPT level */
1012 kvm_configure_mmu(npt_enabled, get_max_npt_level(),
1013 get_max_npt_level(), PG_LEVEL_1G);
1014 pr_info("kvm: Nested Paging %sabled\n", npt_enabled ? "en" : "dis");
1016 /* Note, SEV setup consumes npt_enabled. */
1017 sev_hardware_setup();
1019 svm_hv_hardware_setup();
1021 svm_adjust_mmio_mask();
1023 for_each_possible_cpu(cpu) {
1024 r = svm_cpu_init(cpu);
1030 if (!boot_cpu_has(X86_FEATURE_NRIPS))
1034 enable_apicv = avic = avic && npt_enabled && boot_cpu_has(X86_FEATURE_AVIC);
1037 pr_info("AVIC enabled\n");
1039 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1044 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1045 !IS_ENABLED(CONFIG_X86_64)) {
1048 pr_info("Virtual VMLOAD VMSAVE supported\n");
1052 if (boot_cpu_has(X86_FEATURE_SVME_ADDR_CHK))
1053 svm_gp_erratum_intercept = false;
1056 if (!boot_cpu_has(X86_FEATURE_VGIF))
1059 pr_info("Virtual GIF supported\n");
1065 * It seems that on AMD processors PTE's accessed bit is
1066 * being set by the CPU hardware before the NPF vmexit.
1067 * This is not expected behaviour and our tests fail because
1069 * A workaround here is to disable support for
1070 * GUEST_MAXPHYADDR < HOST_MAXPHYADDR if NPT is enabled.
1071 * In this case userspace can know if there is support using
1072 * KVM_CAP_SMALLER_MAXPHYADDR extension and decide how to handle
1074 * If future AMD CPU models change the behaviour described above,
1075 * this variable can be changed accordingly
1077 allow_smaller_maxphyaddr = !npt_enabled;
1082 svm_hardware_teardown();
1086 static void init_seg(struct vmcb_seg *seg)
1089 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1090 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1091 seg->limit = 0xffff;
1095 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1098 seg->attrib = SVM_SELECTOR_P_MASK | type;
1099 seg->limit = 0xffff;
1103 static u64 svm_get_l2_tsc_offset(struct kvm_vcpu *vcpu)
1105 struct vcpu_svm *svm = to_svm(vcpu);
1107 return svm->nested.ctl.tsc_offset;
1110 static u64 svm_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu)
1112 return kvm_default_tsc_scaling_ratio;
1115 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1117 struct vcpu_svm *svm = to_svm(vcpu);
1119 svm->vmcb01.ptr->control.tsc_offset = vcpu->arch.l1_tsc_offset;
1120 svm->vmcb->control.tsc_offset = offset;
1121 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1124 static void svm_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 multiplier)
1126 wrmsrl(MSR_AMD64_TSC_RATIO, multiplier);
1129 /* Evaluate instruction intercepts that depend on guest CPUID features. */
1130 static void svm_recalc_instruction_intercepts(struct kvm_vcpu *vcpu,
1131 struct vcpu_svm *svm)
1134 * Intercept INVPCID if shadow paging is enabled to sync/free shadow
1135 * roots, or if INVPCID is disabled in the guest to inject #UD.
1137 if (kvm_cpu_cap_has(X86_FEATURE_INVPCID)) {
1139 !guest_cpuid_has(&svm->vcpu, X86_FEATURE_INVPCID))
1140 svm_set_intercept(svm, INTERCEPT_INVPCID);
1142 svm_clr_intercept(svm, INTERCEPT_INVPCID);
1145 if (kvm_cpu_cap_has(X86_FEATURE_RDTSCP)) {
1146 if (guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
1147 svm_clr_intercept(svm, INTERCEPT_RDTSCP);
1149 svm_set_intercept(svm, INTERCEPT_RDTSCP);
1153 static void init_vmcb(struct kvm_vcpu *vcpu)
1155 struct vcpu_svm *svm = to_svm(vcpu);
1156 struct vmcb_control_area *control = &svm->vmcb->control;
1157 struct vmcb_save_area *save = &svm->vmcb->save;
1159 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1160 svm_set_intercept(svm, INTERCEPT_CR3_READ);
1161 svm_set_intercept(svm, INTERCEPT_CR4_READ);
1162 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1163 svm_set_intercept(svm, INTERCEPT_CR3_WRITE);
1164 svm_set_intercept(svm, INTERCEPT_CR4_WRITE);
1165 if (!kvm_vcpu_apicv_active(vcpu))
1166 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
1168 set_dr_intercepts(svm);
1170 set_exception_intercept(svm, PF_VECTOR);
1171 set_exception_intercept(svm, UD_VECTOR);
1172 set_exception_intercept(svm, MC_VECTOR);
1173 set_exception_intercept(svm, AC_VECTOR);
1174 set_exception_intercept(svm, DB_VECTOR);
1176 * Guest access to VMware backdoor ports could legitimately
1177 * trigger #GP because of TSS I/O permission bitmap.
1178 * We intercept those #GP and allow access to them anyway
1181 if (enable_vmware_backdoor)
1182 set_exception_intercept(svm, GP_VECTOR);
1184 svm_set_intercept(svm, INTERCEPT_INTR);
1185 svm_set_intercept(svm, INTERCEPT_NMI);
1188 svm_set_intercept(svm, INTERCEPT_SMI);
1190 svm_set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1191 svm_set_intercept(svm, INTERCEPT_RDPMC);
1192 svm_set_intercept(svm, INTERCEPT_CPUID);
1193 svm_set_intercept(svm, INTERCEPT_INVD);
1194 svm_set_intercept(svm, INTERCEPT_INVLPG);
1195 svm_set_intercept(svm, INTERCEPT_INVLPGA);
1196 svm_set_intercept(svm, INTERCEPT_IOIO_PROT);
1197 svm_set_intercept(svm, INTERCEPT_MSR_PROT);
1198 svm_set_intercept(svm, INTERCEPT_TASK_SWITCH);
1199 svm_set_intercept(svm, INTERCEPT_SHUTDOWN);
1200 svm_set_intercept(svm, INTERCEPT_VMRUN);
1201 svm_set_intercept(svm, INTERCEPT_VMMCALL);
1202 svm_set_intercept(svm, INTERCEPT_VMLOAD);
1203 svm_set_intercept(svm, INTERCEPT_VMSAVE);
1204 svm_set_intercept(svm, INTERCEPT_STGI);
1205 svm_set_intercept(svm, INTERCEPT_CLGI);
1206 svm_set_intercept(svm, INTERCEPT_SKINIT);
1207 svm_set_intercept(svm, INTERCEPT_WBINVD);
1208 svm_set_intercept(svm, INTERCEPT_XSETBV);
1209 svm_set_intercept(svm, INTERCEPT_RDPRU);
1210 svm_set_intercept(svm, INTERCEPT_RSM);
1212 if (!kvm_mwait_in_guest(vcpu->kvm)) {
1213 svm_set_intercept(svm, INTERCEPT_MONITOR);
1214 svm_set_intercept(svm, INTERCEPT_MWAIT);
1217 if (!kvm_hlt_in_guest(vcpu->kvm))
1218 svm_set_intercept(svm, INTERCEPT_HLT);
1220 control->iopm_base_pa = __sme_set(iopm_base);
1221 control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1222 control->int_ctl = V_INTR_MASKING_MASK;
1224 init_seg(&save->es);
1225 init_seg(&save->ss);
1226 init_seg(&save->ds);
1227 init_seg(&save->fs);
1228 init_seg(&save->gs);
1230 save->cs.selector = 0xf000;
1231 save->cs.base = 0xffff0000;
1232 /* Executable/Readable Code Segment */
1233 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1234 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1235 save->cs.limit = 0xffff;
1237 save->gdtr.base = 0;
1238 save->gdtr.limit = 0xffff;
1239 save->idtr.base = 0;
1240 save->idtr.limit = 0xffff;
1242 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1243 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1246 /* Setup VMCB for Nested Paging */
1247 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1248 svm_clr_intercept(svm, INTERCEPT_INVLPG);
1249 clr_exception_intercept(svm, PF_VECTOR);
1250 svm_clr_intercept(svm, INTERCEPT_CR3_READ);
1251 svm_clr_intercept(svm, INTERCEPT_CR3_WRITE);
1252 save->g_pat = vcpu->arch.pat;
1255 svm->current_vmcb->asid_generation = 0;
1258 svm->nested.vmcb12_gpa = INVALID_GPA;
1259 svm->nested.last_vmcb12_gpa = INVALID_GPA;
1261 if (!kvm_pause_in_guest(vcpu->kvm)) {
1262 control->pause_filter_count = pause_filter_count;
1263 if (pause_filter_thresh)
1264 control->pause_filter_thresh = pause_filter_thresh;
1265 svm_set_intercept(svm, INTERCEPT_PAUSE);
1267 svm_clr_intercept(svm, INTERCEPT_PAUSE);
1270 svm_recalc_instruction_intercepts(vcpu, svm);
1273 * If the host supports V_SPEC_CTRL then disable the interception
1274 * of MSR_IA32_SPEC_CTRL.
1276 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL))
1277 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
1279 if (kvm_vcpu_apicv_active(vcpu))
1280 avic_init_vmcb(svm);
1283 svm_clr_intercept(svm, INTERCEPT_STGI);
1284 svm_clr_intercept(svm, INTERCEPT_CLGI);
1285 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1288 if (sev_guest(vcpu->kvm)) {
1289 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1290 clr_exception_intercept(svm, UD_VECTOR);
1292 if (sev_es_guest(vcpu->kvm)) {
1293 /* Perform SEV-ES specific VMCB updates */
1294 sev_es_init_vmcb(svm);
1298 svm_hv_init_vmcb(svm->vmcb);
1300 vmcb_mark_all_dirty(svm->vmcb);
1306 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1308 struct vcpu_svm *svm = to_svm(vcpu);
1311 svm->virt_spec_ctrl = 0;
1316 void svm_switch_vmcb(struct vcpu_svm *svm, struct kvm_vmcb_info *target_vmcb)
1318 svm->current_vmcb = target_vmcb;
1319 svm->vmcb = target_vmcb->ptr;
1322 static int svm_create_vcpu(struct kvm_vcpu *vcpu)
1324 struct vcpu_svm *svm;
1325 struct page *vmcb01_page;
1326 struct page *vmsa_page = NULL;
1329 BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0);
1333 vmcb01_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1337 if (sev_es_guest(vcpu->kvm)) {
1339 * SEV-ES guests require a separate VMSA page used to contain
1340 * the encrypted register state of the guest.
1342 vmsa_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1344 goto error_free_vmcb_page;
1347 * SEV-ES guests maintain an encrypted version of their FPU
1348 * state which is restored and saved on VMRUN and VMEXIT.
1349 * Free the fpu structure to prevent KVM from attempting to
1350 * access the FPU state.
1352 kvm_free_guest_fpu(vcpu);
1355 err = avic_init_vcpu(svm);
1357 goto error_free_vmsa_page;
1359 /* We initialize this flag to true to make sure that the is_running
1360 * bit would be set the first time the vcpu is loaded.
1362 if (irqchip_in_kernel(vcpu->kvm) && kvm_apicv_activated(vcpu->kvm))
1363 svm->avic_is_running = true;
1365 svm->msrpm = svm_vcpu_alloc_msrpm();
1368 goto error_free_vmsa_page;
1371 svm->vmcb01.ptr = page_address(vmcb01_page);
1372 svm->vmcb01.pa = __sme_set(page_to_pfn(vmcb01_page) << PAGE_SHIFT);
1375 svm->vmsa = page_address(vmsa_page);
1377 svm->guest_state_loaded = false;
1379 svm_switch_vmcb(svm, &svm->vmcb01);
1382 svm_vcpu_init_msrpm(vcpu, svm->msrpm);
1384 svm_init_osvw(vcpu);
1385 vcpu->arch.microcode_version = 0x01000065;
1387 if (sev_es_guest(vcpu->kvm))
1388 /* Perform SEV-ES specific VMCB creation updates */
1389 sev_es_create_vcpu(svm);
1393 error_free_vmsa_page:
1395 __free_page(vmsa_page);
1396 error_free_vmcb_page:
1397 __free_page(vmcb01_page);
1402 static void svm_clear_current_vmcb(struct vmcb *vmcb)
1406 for_each_online_cpu(i)
1407 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
1410 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1412 struct vcpu_svm *svm = to_svm(vcpu);
1415 * The vmcb page can be recycled, causing a false negative in
1416 * svm_vcpu_load(). So, ensure that no logical CPU has this
1417 * vmcb page recorded as its current vmcb.
1419 svm_clear_current_vmcb(svm->vmcb);
1421 svm_free_nested(svm);
1423 sev_free_vcpu(vcpu);
1425 __free_page(pfn_to_page(__sme_clr(svm->vmcb01.pa) >> PAGE_SHIFT));
1426 __free_pages(virt_to_page(svm->msrpm), get_order(MSRPM_SIZE));
1429 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
1431 struct vcpu_svm *svm = to_svm(vcpu);
1432 struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
1434 if (sev_es_guest(vcpu->kvm))
1435 sev_es_unmap_ghcb(svm);
1437 if (svm->guest_state_loaded)
1441 * Save additional host state that will be restored on VMEXIT (sev-es)
1442 * or subsequent vmload of host save area.
1444 if (sev_es_guest(vcpu->kvm)) {
1445 sev_es_prepare_guest_switch(svm, vcpu->cpu);
1447 vmsave(__sme_page_pa(sd->save_area));
1450 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1451 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1452 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1453 __this_cpu_write(current_tsc_ratio, tsc_ratio);
1454 wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1458 if (likely(tsc_aux_uret_slot >= 0))
1459 kvm_set_user_return_msr(tsc_aux_uret_slot, svm->tsc_aux, -1ull);
1461 svm->guest_state_loaded = true;
1464 static void svm_prepare_host_switch(struct kvm_vcpu *vcpu)
1466 to_svm(vcpu)->guest_state_loaded = false;
1469 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1471 struct vcpu_svm *svm = to_svm(vcpu);
1472 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
1474 if (sd->current_vmcb != svm->vmcb) {
1475 sd->current_vmcb = svm->vmcb;
1476 indirect_branch_prediction_barrier();
1478 if (kvm_vcpu_apicv_active(vcpu))
1479 avic_vcpu_load(vcpu, cpu);
1482 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1484 if (kvm_vcpu_apicv_active(vcpu))
1485 avic_vcpu_put(vcpu);
1487 svm_prepare_host_switch(vcpu);
1489 ++vcpu->stat.host_state_reload;
1492 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1494 struct vcpu_svm *svm = to_svm(vcpu);
1495 unsigned long rflags = svm->vmcb->save.rflags;
1497 if (svm->nmi_singlestep) {
1498 /* Hide our flags if they were not set by the guest */
1499 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1500 rflags &= ~X86_EFLAGS_TF;
1501 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1502 rflags &= ~X86_EFLAGS_RF;
1507 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1509 if (to_svm(vcpu)->nmi_singlestep)
1510 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1513 * Any change of EFLAGS.VM is accompanied by a reload of SS
1514 * (caused by either a task switch or an inter-privilege IRET),
1515 * so we do not need to update the CPL here.
1517 to_svm(vcpu)->vmcb->save.rflags = rflags;
1520 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1523 case VCPU_EXREG_PDPTR:
1524 BUG_ON(!npt_enabled);
1525 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1528 KVM_BUG_ON(1, vcpu->kvm);
1532 static void svm_set_vintr(struct vcpu_svm *svm)
1534 struct vmcb_control_area *control;
1537 * The following fields are ignored when AVIC is enabled
1539 WARN_ON(kvm_apicv_activated(svm->vcpu.kvm));
1541 svm_set_intercept(svm, INTERCEPT_VINTR);
1544 * This is just a dummy VINTR to actually cause a vmexit to happen.
1545 * Actual injection of virtual interrupts happens through EVENTINJ.
1547 control = &svm->vmcb->control;
1548 control->int_vector = 0x0;
1549 control->int_ctl &= ~V_INTR_PRIO_MASK;
1550 control->int_ctl |= V_IRQ_MASK |
1551 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1552 vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1555 static void svm_clear_vintr(struct vcpu_svm *svm)
1557 svm_clr_intercept(svm, INTERCEPT_VINTR);
1559 /* Drop int_ctl fields related to VINTR injection. */
1560 svm->vmcb->control.int_ctl &= ~V_IRQ_INJECTION_BITS_MASK;
1561 if (is_guest_mode(&svm->vcpu)) {
1562 svm->vmcb01.ptr->control.int_ctl &= ~V_IRQ_INJECTION_BITS_MASK;
1564 WARN_ON((svm->vmcb->control.int_ctl & V_TPR_MASK) !=
1565 (svm->nested.ctl.int_ctl & V_TPR_MASK));
1567 svm->vmcb->control.int_ctl |= svm->nested.ctl.int_ctl &
1568 V_IRQ_INJECTION_BITS_MASK;
1570 svm->vmcb->control.int_vector = svm->nested.ctl.int_vector;
1573 vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1576 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1578 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1579 struct vmcb_save_area *save01 = &to_svm(vcpu)->vmcb01.ptr->save;
1582 case VCPU_SREG_CS: return &save->cs;
1583 case VCPU_SREG_DS: return &save->ds;
1584 case VCPU_SREG_ES: return &save->es;
1585 case VCPU_SREG_FS: return &save01->fs;
1586 case VCPU_SREG_GS: return &save01->gs;
1587 case VCPU_SREG_SS: return &save->ss;
1588 case VCPU_SREG_TR: return &save01->tr;
1589 case VCPU_SREG_LDTR: return &save01->ldtr;
1595 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1597 struct vmcb_seg *s = svm_seg(vcpu, seg);
1602 static void svm_get_segment(struct kvm_vcpu *vcpu,
1603 struct kvm_segment *var, int seg)
1605 struct vmcb_seg *s = svm_seg(vcpu, seg);
1607 var->base = s->base;
1608 var->limit = s->limit;
1609 var->selector = s->selector;
1610 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1611 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1612 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1613 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1614 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1615 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1616 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1619 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1620 * However, the SVM spec states that the G bit is not observed by the
1621 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1622 * So let's synthesize a legal G bit for all segments, this helps
1623 * running KVM nested. It also helps cross-vendor migration, because
1624 * Intel's vmentry has a check on the 'G' bit.
1626 var->g = s->limit > 0xfffff;
1629 * AMD's VMCB does not have an explicit unusable field, so emulate it
1630 * for cross vendor migration purposes by "not present"
1632 var->unusable = !var->present;
1637 * Work around a bug where the busy flag in the tr selector
1647 * The accessed bit must always be set in the segment
1648 * descriptor cache, although it can be cleared in the
1649 * descriptor, the cached bit always remains at 1. Since
1650 * Intel has a check on this, set it here to support
1651 * cross-vendor migration.
1658 * On AMD CPUs sometimes the DB bit in the segment
1659 * descriptor is left as 1, although the whole segment has
1660 * been made unusable. Clear it here to pass an Intel VMX
1661 * entry check when cross vendor migrating.
1665 /* This is symmetric with svm_set_segment() */
1666 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1671 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1673 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1678 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1680 struct vcpu_svm *svm = to_svm(vcpu);
1682 dt->size = svm->vmcb->save.idtr.limit;
1683 dt->address = svm->vmcb->save.idtr.base;
1686 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1688 struct vcpu_svm *svm = to_svm(vcpu);
1690 svm->vmcb->save.idtr.limit = dt->size;
1691 svm->vmcb->save.idtr.base = dt->address ;
1692 vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1695 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1697 struct vcpu_svm *svm = to_svm(vcpu);
1699 dt->size = svm->vmcb->save.gdtr.limit;
1700 dt->address = svm->vmcb->save.gdtr.base;
1703 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1705 struct vcpu_svm *svm = to_svm(vcpu);
1707 svm->vmcb->save.gdtr.limit = dt->size;
1708 svm->vmcb->save.gdtr.base = dt->address ;
1709 vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1712 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1714 struct vcpu_svm *svm = to_svm(vcpu);
1717 #ifdef CONFIG_X86_64
1718 if (vcpu->arch.efer & EFER_LME && !vcpu->arch.guest_state_protected) {
1719 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1720 vcpu->arch.efer |= EFER_LMA;
1721 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1724 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1725 vcpu->arch.efer &= ~EFER_LMA;
1726 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1730 vcpu->arch.cr0 = cr0;
1733 hcr0 |= X86_CR0_PG | X86_CR0_WP;
1736 * re-enable caching here because the QEMU bios
1737 * does not do it - this results in some delay at
1740 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1741 hcr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1743 svm->vmcb->save.cr0 = hcr0;
1744 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1747 * SEV-ES guests must always keep the CR intercepts cleared. CR
1748 * tracking is done using the CR write traps.
1750 if (sev_es_guest(vcpu->kvm))
1754 /* Selective CR0 write remains on. */
1755 svm_clr_intercept(svm, INTERCEPT_CR0_READ);
1756 svm_clr_intercept(svm, INTERCEPT_CR0_WRITE);
1758 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1759 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1763 static bool svm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1768 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1770 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1771 unsigned long old_cr4 = vcpu->arch.cr4;
1773 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1774 svm_flush_tlb(vcpu);
1776 vcpu->arch.cr4 = cr4;
1779 cr4 |= host_cr4_mce;
1780 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1781 vmcb_mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1783 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
1784 kvm_update_cpuid_runtime(vcpu);
1787 static void svm_set_segment(struct kvm_vcpu *vcpu,
1788 struct kvm_segment *var, int seg)
1790 struct vcpu_svm *svm = to_svm(vcpu);
1791 struct vmcb_seg *s = svm_seg(vcpu, seg);
1793 s->base = var->base;
1794 s->limit = var->limit;
1795 s->selector = var->selector;
1796 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1797 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1798 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1799 s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
1800 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1801 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1802 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1803 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1806 * This is always accurate, except if SYSRET returned to a segment
1807 * with SS.DPL != 3. Intel does not have this quirk, and always
1808 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1809 * would entail passing the CPL to userspace and back.
1811 if (seg == VCPU_SREG_SS)
1812 /* This is symmetric with svm_get_segment() */
1813 svm->vmcb->save.cpl = (var->dpl & 3);
1815 vmcb_mark_dirty(svm->vmcb, VMCB_SEG);
1818 static void svm_update_exception_bitmap(struct kvm_vcpu *vcpu)
1820 struct vcpu_svm *svm = to_svm(vcpu);
1822 clr_exception_intercept(svm, BP_VECTOR);
1824 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1825 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1826 set_exception_intercept(svm, BP_VECTOR);
1830 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1832 if (sd->next_asid > sd->max_asid) {
1833 ++sd->asid_generation;
1834 sd->next_asid = sd->min_asid;
1835 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1836 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
1839 svm->current_vmcb->asid_generation = sd->asid_generation;
1840 svm->asid = sd->next_asid++;
1843 static void svm_set_dr6(struct vcpu_svm *svm, unsigned long value)
1845 struct vmcb *vmcb = svm->vmcb;
1847 if (svm->vcpu.arch.guest_state_protected)
1850 if (unlikely(value != vmcb->save.dr6)) {
1851 vmcb->save.dr6 = value;
1852 vmcb_mark_dirty(vmcb, VMCB_DR);
1856 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1858 struct vcpu_svm *svm = to_svm(vcpu);
1860 if (vcpu->arch.guest_state_protected)
1863 get_debugreg(vcpu->arch.db[0], 0);
1864 get_debugreg(vcpu->arch.db[1], 1);
1865 get_debugreg(vcpu->arch.db[2], 2);
1866 get_debugreg(vcpu->arch.db[3], 3);
1868 * We cannot reset svm->vmcb->save.dr6 to DR6_ACTIVE_LOW here,
1869 * because db_interception might need it. We can do it before vmentry.
1871 vcpu->arch.dr6 = svm->vmcb->save.dr6;
1872 vcpu->arch.dr7 = svm->vmcb->save.dr7;
1873 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1874 set_dr_intercepts(svm);
1877 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1879 struct vcpu_svm *svm = to_svm(vcpu);
1881 if (vcpu->arch.guest_state_protected)
1884 svm->vmcb->save.dr7 = value;
1885 vmcb_mark_dirty(svm->vmcb, VMCB_DR);
1888 static int pf_interception(struct kvm_vcpu *vcpu)
1890 struct vcpu_svm *svm = to_svm(vcpu);
1892 u64 fault_address = svm->vmcb->control.exit_info_2;
1893 u64 error_code = svm->vmcb->control.exit_info_1;
1895 return kvm_handle_page_fault(vcpu, error_code, fault_address,
1896 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1897 svm->vmcb->control.insn_bytes : NULL,
1898 svm->vmcb->control.insn_len);
1901 static int npf_interception(struct kvm_vcpu *vcpu)
1903 struct vcpu_svm *svm = to_svm(vcpu);
1905 u64 fault_address = svm->vmcb->control.exit_info_2;
1906 u64 error_code = svm->vmcb->control.exit_info_1;
1908 trace_kvm_page_fault(fault_address, error_code);
1909 return kvm_mmu_page_fault(vcpu, fault_address, error_code,
1910 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1911 svm->vmcb->control.insn_bytes : NULL,
1912 svm->vmcb->control.insn_len);
1915 static int db_interception(struct kvm_vcpu *vcpu)
1917 struct kvm_run *kvm_run = vcpu->run;
1918 struct vcpu_svm *svm = to_svm(vcpu);
1920 if (!(vcpu->guest_debug &
1921 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1922 !svm->nmi_singlestep) {
1923 u32 payload = svm->vmcb->save.dr6 ^ DR6_ACTIVE_LOW;
1924 kvm_queue_exception_p(vcpu, DB_VECTOR, payload);
1928 if (svm->nmi_singlestep) {
1929 disable_nmi_singlestep(svm);
1930 /* Make sure we check for pending NMIs upon entry */
1931 kvm_make_request(KVM_REQ_EVENT, vcpu);
1934 if (vcpu->guest_debug &
1935 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1936 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1937 kvm_run->debug.arch.dr6 = svm->vmcb->save.dr6;
1938 kvm_run->debug.arch.dr7 = svm->vmcb->save.dr7;
1939 kvm_run->debug.arch.pc =
1940 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1941 kvm_run->debug.arch.exception = DB_VECTOR;
1948 static int bp_interception(struct kvm_vcpu *vcpu)
1950 struct vcpu_svm *svm = to_svm(vcpu);
1951 struct kvm_run *kvm_run = vcpu->run;
1953 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1954 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1955 kvm_run->debug.arch.exception = BP_VECTOR;
1959 static int ud_interception(struct kvm_vcpu *vcpu)
1961 return handle_ud(vcpu);
1964 static int ac_interception(struct kvm_vcpu *vcpu)
1966 kvm_queue_exception_e(vcpu, AC_VECTOR, 0);
1970 static bool is_erratum_383(void)
1975 if (!erratum_383_found)
1978 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1982 /* Bit 62 may or may not be set for this mce */
1983 value &= ~(1ULL << 62);
1985 if (value != 0xb600000000010015ULL)
1988 /* Clear MCi_STATUS registers */
1989 for (i = 0; i < 6; ++i)
1990 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1992 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1996 value &= ~(1ULL << 2);
1997 low = lower_32_bits(value);
1998 high = upper_32_bits(value);
2000 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2003 /* Flush tlb to evict multi-match entries */
2009 static void svm_handle_mce(struct kvm_vcpu *vcpu)
2011 if (is_erratum_383()) {
2013 * Erratum 383 triggered. Guest state is corrupt so kill the
2016 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2018 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2024 * On an #MC intercept the MCE handler is not called automatically in
2025 * the host. So do it by hand here.
2027 kvm_machine_check();
2030 static int mc_interception(struct kvm_vcpu *vcpu)
2035 static int shutdown_interception(struct kvm_vcpu *vcpu)
2037 struct kvm_run *kvm_run = vcpu->run;
2038 struct vcpu_svm *svm = to_svm(vcpu);
2041 * The VM save area has already been encrypted so it
2042 * cannot be reinitialized - just terminate.
2044 if (sev_es_guest(vcpu->kvm))
2048 * VMCB is undefined after a SHUTDOWN intercept. INIT the vCPU to put
2049 * the VMCB in a known good state. Unfortuately, KVM doesn't have
2050 * KVM_MP_STATE_SHUTDOWN and can't add it without potentially breaking
2051 * userspace. At a platform view, INIT is acceptable behavior as
2052 * there exist bare metal platforms that automatically INIT the CPU
2053 * in response to shutdown.
2055 clear_page(svm->vmcb);
2056 kvm_vcpu_reset(vcpu, true);
2058 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2062 static int io_interception(struct kvm_vcpu *vcpu)
2064 struct vcpu_svm *svm = to_svm(vcpu);
2065 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2066 int size, in, string;
2069 ++vcpu->stat.io_exits;
2070 string = (io_info & SVM_IOIO_STR_MASK) != 0;
2071 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2072 port = io_info >> 16;
2073 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2076 if (sev_es_guest(vcpu->kvm))
2077 return sev_es_string_io(svm, size, port, in);
2079 return kvm_emulate_instruction(vcpu, 0);
2082 svm->next_rip = svm->vmcb->control.exit_info_2;
2084 return kvm_fast_pio(vcpu, size, port, in);
2087 static int nmi_interception(struct kvm_vcpu *vcpu)
2092 static int smi_interception(struct kvm_vcpu *vcpu)
2097 static int intr_interception(struct kvm_vcpu *vcpu)
2099 ++vcpu->stat.irq_exits;
2103 static int vmload_vmsave_interception(struct kvm_vcpu *vcpu, bool vmload)
2105 struct vcpu_svm *svm = to_svm(vcpu);
2106 struct vmcb *vmcb12;
2107 struct kvm_host_map map;
2110 if (nested_svm_check_permissions(vcpu))
2113 ret = kvm_vcpu_map(vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
2116 kvm_inject_gp(vcpu, 0);
2122 ret = kvm_skip_emulated_instruction(vcpu);
2125 svm_copy_vmloadsave_state(svm->vmcb, vmcb12);
2126 svm->sysenter_eip_hi = 0;
2127 svm->sysenter_esp_hi = 0;
2129 svm_copy_vmloadsave_state(vmcb12, svm->vmcb);
2132 kvm_vcpu_unmap(vcpu, &map, true);
2137 static int vmload_interception(struct kvm_vcpu *vcpu)
2139 return vmload_vmsave_interception(vcpu, true);
2142 static int vmsave_interception(struct kvm_vcpu *vcpu)
2144 return vmload_vmsave_interception(vcpu, false);
2147 static int vmrun_interception(struct kvm_vcpu *vcpu)
2149 if (nested_svm_check_permissions(vcpu))
2152 return nested_svm_vmrun(vcpu);
2162 /* Return NONE_SVM_INSTR if not SVM instrs, otherwise return decode result */
2163 static int svm_instr_opcode(struct kvm_vcpu *vcpu)
2165 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
2167 if (ctxt->b != 0x1 || ctxt->opcode_len != 2)
2168 return NONE_SVM_INSTR;
2170 switch (ctxt->modrm) {
2171 case 0xd8: /* VMRUN */
2172 return SVM_INSTR_VMRUN;
2173 case 0xda: /* VMLOAD */
2174 return SVM_INSTR_VMLOAD;
2175 case 0xdb: /* VMSAVE */
2176 return SVM_INSTR_VMSAVE;
2181 return NONE_SVM_INSTR;
2184 static int emulate_svm_instr(struct kvm_vcpu *vcpu, int opcode)
2186 const int guest_mode_exit_codes[] = {
2187 [SVM_INSTR_VMRUN] = SVM_EXIT_VMRUN,
2188 [SVM_INSTR_VMLOAD] = SVM_EXIT_VMLOAD,
2189 [SVM_INSTR_VMSAVE] = SVM_EXIT_VMSAVE,
2191 int (*const svm_instr_handlers[])(struct kvm_vcpu *vcpu) = {
2192 [SVM_INSTR_VMRUN] = vmrun_interception,
2193 [SVM_INSTR_VMLOAD] = vmload_interception,
2194 [SVM_INSTR_VMSAVE] = vmsave_interception,
2196 struct vcpu_svm *svm = to_svm(vcpu);
2199 if (is_guest_mode(vcpu)) {
2200 /* Returns '1' or -errno on failure, '0' on success. */
2201 ret = nested_svm_simple_vmexit(svm, guest_mode_exit_codes[opcode]);
2206 return svm_instr_handlers[opcode](vcpu);
2210 * #GP handling code. Note that #GP can be triggered under the following two
2212 * 1) SVM VM-related instructions (VMRUN/VMSAVE/VMLOAD) that trigger #GP on
2213 * some AMD CPUs when EAX of these instructions are in the reserved memory
2214 * regions (e.g. SMM memory on host).
2215 * 2) VMware backdoor
2217 static int gp_interception(struct kvm_vcpu *vcpu)
2219 struct vcpu_svm *svm = to_svm(vcpu);
2220 u32 error_code = svm->vmcb->control.exit_info_1;
2223 /* Both #GP cases have zero error_code */
2227 /* All SVM instructions expect page aligned RAX */
2228 if (svm->vmcb->save.rax & ~PAGE_MASK)
2231 /* Decode the instruction for usage later */
2232 if (x86_decode_emulated_instruction(vcpu, 0, NULL, 0) != EMULATION_OK)
2235 opcode = svm_instr_opcode(vcpu);
2237 if (opcode == NONE_SVM_INSTR) {
2238 if (!enable_vmware_backdoor)
2242 * VMware backdoor emulation on #GP interception only handles
2243 * IN{S}, OUT{S}, and RDPMC.
2245 if (!is_guest_mode(vcpu))
2246 return kvm_emulate_instruction(vcpu,
2247 EMULTYPE_VMWARE_GP | EMULTYPE_NO_DECODE);
2249 return emulate_svm_instr(vcpu, opcode);
2252 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2256 void svm_set_gif(struct vcpu_svm *svm, bool value)
2260 * If VGIF is enabled, the STGI intercept is only added to
2261 * detect the opening of the SMI/NMI window; remove it now.
2262 * Likewise, clear the VINTR intercept, we will set it
2263 * again while processing KVM_REQ_EVENT if needed.
2265 if (vgif_enabled(svm))
2266 svm_clr_intercept(svm, INTERCEPT_STGI);
2267 if (svm_is_intercept(svm, INTERCEPT_VINTR))
2268 svm_clear_vintr(svm);
2271 if (svm->vcpu.arch.smi_pending ||
2272 svm->vcpu.arch.nmi_pending ||
2273 kvm_cpu_has_injectable_intr(&svm->vcpu))
2274 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2279 * After a CLGI no interrupts should come. But if vGIF is
2280 * in use, we still rely on the VINTR intercept (rather than
2281 * STGI) to detect an open interrupt window.
2283 if (!vgif_enabled(svm))
2284 svm_clear_vintr(svm);
2288 static int stgi_interception(struct kvm_vcpu *vcpu)
2292 if (nested_svm_check_permissions(vcpu))
2295 ret = kvm_skip_emulated_instruction(vcpu);
2296 svm_set_gif(to_svm(vcpu), true);
2300 static int clgi_interception(struct kvm_vcpu *vcpu)
2304 if (nested_svm_check_permissions(vcpu))
2307 ret = kvm_skip_emulated_instruction(vcpu);
2308 svm_set_gif(to_svm(vcpu), false);
2312 static int invlpga_interception(struct kvm_vcpu *vcpu)
2314 gva_t gva = kvm_rax_read(vcpu);
2315 u32 asid = kvm_rcx_read(vcpu);
2317 /* FIXME: Handle an address size prefix. */
2318 if (!is_long_mode(vcpu))
2321 trace_kvm_invlpga(to_svm(vcpu)->vmcb->save.rip, asid, gva);
2323 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2324 kvm_mmu_invlpg(vcpu, gva);
2326 return kvm_skip_emulated_instruction(vcpu);
2329 static int skinit_interception(struct kvm_vcpu *vcpu)
2331 trace_kvm_skinit(to_svm(vcpu)->vmcb->save.rip, kvm_rax_read(vcpu));
2333 kvm_queue_exception(vcpu, UD_VECTOR);
2337 static int task_switch_interception(struct kvm_vcpu *vcpu)
2339 struct vcpu_svm *svm = to_svm(vcpu);
2342 int int_type = svm->vmcb->control.exit_int_info &
2343 SVM_EXITINTINFO_TYPE_MASK;
2344 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2346 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2348 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2349 bool has_error_code = false;
2352 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2354 if (svm->vmcb->control.exit_info_2 &
2355 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2356 reason = TASK_SWITCH_IRET;
2357 else if (svm->vmcb->control.exit_info_2 &
2358 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2359 reason = TASK_SWITCH_JMP;
2361 reason = TASK_SWITCH_GATE;
2363 reason = TASK_SWITCH_CALL;
2365 if (reason == TASK_SWITCH_GATE) {
2367 case SVM_EXITINTINFO_TYPE_NMI:
2368 vcpu->arch.nmi_injected = false;
2370 case SVM_EXITINTINFO_TYPE_EXEPT:
2371 if (svm->vmcb->control.exit_info_2 &
2372 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2373 has_error_code = true;
2375 (u32)svm->vmcb->control.exit_info_2;
2377 kvm_clear_exception_queue(vcpu);
2379 case SVM_EXITINTINFO_TYPE_INTR:
2380 kvm_clear_interrupt_queue(vcpu);
2387 if (reason != TASK_SWITCH_GATE ||
2388 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2389 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2390 (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
2391 if (!skip_emulated_instruction(vcpu))
2395 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2398 return kvm_task_switch(vcpu, tss_selector, int_vec, reason,
2399 has_error_code, error_code);
2402 static int iret_interception(struct kvm_vcpu *vcpu)
2404 struct vcpu_svm *svm = to_svm(vcpu);
2406 ++vcpu->stat.nmi_window_exits;
2407 vcpu->arch.hflags |= HF_IRET_MASK;
2408 if (!sev_es_guest(vcpu->kvm)) {
2409 svm_clr_intercept(svm, INTERCEPT_IRET);
2410 svm->nmi_iret_rip = kvm_rip_read(vcpu);
2412 kvm_make_request(KVM_REQ_EVENT, vcpu);
2416 static int invlpg_interception(struct kvm_vcpu *vcpu)
2418 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2419 return kvm_emulate_instruction(vcpu, 0);
2421 kvm_mmu_invlpg(vcpu, to_svm(vcpu)->vmcb->control.exit_info_1);
2422 return kvm_skip_emulated_instruction(vcpu);
2425 static int emulate_on_interception(struct kvm_vcpu *vcpu)
2427 return kvm_emulate_instruction(vcpu, 0);
2430 static int rsm_interception(struct kvm_vcpu *vcpu)
2432 return kvm_emulate_instruction_from_buffer(vcpu, rsm_ins_bytes, 2);
2435 static bool check_selective_cr0_intercepted(struct kvm_vcpu *vcpu,
2438 struct vcpu_svm *svm = to_svm(vcpu);
2439 unsigned long cr0 = vcpu->arch.cr0;
2442 if (!is_guest_mode(vcpu) ||
2443 (!(vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_SELECTIVE_CR0))))
2446 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2447 val &= ~SVM_CR0_SELECTIVE_MASK;
2450 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2451 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2457 #define CR_VALID (1ULL << 63)
2459 static int cr_interception(struct kvm_vcpu *vcpu)
2461 struct vcpu_svm *svm = to_svm(vcpu);
2466 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2467 return emulate_on_interception(vcpu);
2469 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2470 return emulate_on_interception(vcpu);
2472 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2473 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2474 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2476 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2479 if (cr >= 16) { /* mov to cr */
2481 val = kvm_register_read(vcpu, reg);
2482 trace_kvm_cr_write(cr, val);
2485 if (!check_selective_cr0_intercepted(vcpu, val))
2486 err = kvm_set_cr0(vcpu, val);
2492 err = kvm_set_cr3(vcpu, val);
2495 err = kvm_set_cr4(vcpu, val);
2498 err = kvm_set_cr8(vcpu, val);
2501 WARN(1, "unhandled write to CR%d", cr);
2502 kvm_queue_exception(vcpu, UD_VECTOR);
2505 } else { /* mov from cr */
2508 val = kvm_read_cr0(vcpu);
2511 val = vcpu->arch.cr2;
2514 val = kvm_read_cr3(vcpu);
2517 val = kvm_read_cr4(vcpu);
2520 val = kvm_get_cr8(vcpu);
2523 WARN(1, "unhandled read from CR%d", cr);
2524 kvm_queue_exception(vcpu, UD_VECTOR);
2527 kvm_register_write(vcpu, reg, val);
2528 trace_kvm_cr_read(cr, val);
2530 return kvm_complete_insn_gp(vcpu, err);
2533 static int cr_trap(struct kvm_vcpu *vcpu)
2535 struct vcpu_svm *svm = to_svm(vcpu);
2536 unsigned long old_value, new_value;
2540 new_value = (unsigned long)svm->vmcb->control.exit_info_1;
2542 cr = svm->vmcb->control.exit_code - SVM_EXIT_CR0_WRITE_TRAP;
2545 old_value = kvm_read_cr0(vcpu);
2546 svm_set_cr0(vcpu, new_value);
2548 kvm_post_set_cr0(vcpu, old_value, new_value);
2551 old_value = kvm_read_cr4(vcpu);
2552 svm_set_cr4(vcpu, new_value);
2554 kvm_post_set_cr4(vcpu, old_value, new_value);
2557 ret = kvm_set_cr8(vcpu, new_value);
2560 WARN(1, "unhandled CR%d write trap", cr);
2561 kvm_queue_exception(vcpu, UD_VECTOR);
2565 return kvm_complete_insn_gp(vcpu, ret);
2568 static int dr_interception(struct kvm_vcpu *vcpu)
2570 struct vcpu_svm *svm = to_svm(vcpu);
2575 if (vcpu->guest_debug == 0) {
2577 * No more DR vmexits; force a reload of the debug registers
2578 * and reenter on this instruction. The next vmexit will
2579 * retrieve the full state of the debug registers.
2581 clr_dr_intercepts(svm);
2582 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2586 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2587 return emulate_on_interception(vcpu);
2589 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2590 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2591 if (dr >= 16) { /* mov to DRn */
2593 val = kvm_register_read(vcpu, reg);
2594 err = kvm_set_dr(vcpu, dr, val);
2596 kvm_get_dr(vcpu, dr, &val);
2597 kvm_register_write(vcpu, reg, val);
2600 return kvm_complete_insn_gp(vcpu, err);
2603 static int cr8_write_interception(struct kvm_vcpu *vcpu)
2607 u8 cr8_prev = kvm_get_cr8(vcpu);
2608 /* instruction emulation calls kvm_set_cr8() */
2609 r = cr_interception(vcpu);
2610 if (lapic_in_kernel(vcpu))
2612 if (cr8_prev <= kvm_get_cr8(vcpu))
2614 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
2618 static int efer_trap(struct kvm_vcpu *vcpu)
2620 struct msr_data msr_info;
2624 * Clear the EFER_SVME bit from EFER. The SVM code always sets this
2625 * bit in svm_set_efer(), but __kvm_valid_efer() checks it against
2626 * whether the guest has X86_FEATURE_SVM - this avoids a failure if
2627 * the guest doesn't have X86_FEATURE_SVM.
2629 msr_info.host_initiated = false;
2630 msr_info.index = MSR_EFER;
2631 msr_info.data = to_svm(vcpu)->vmcb->control.exit_info_1 & ~EFER_SVME;
2632 ret = kvm_set_msr_common(vcpu, &msr_info);
2634 return kvm_complete_insn_gp(vcpu, ret);
2637 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
2641 switch (msr->index) {
2642 case MSR_F10H_DECFG:
2643 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
2644 msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
2646 case MSR_IA32_PERF_CAPABILITIES:
2649 return KVM_MSR_RET_INVALID;
2655 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2657 struct vcpu_svm *svm = to_svm(vcpu);
2659 switch (msr_info->index) {
2661 msr_info->data = svm->vmcb01.ptr->save.star;
2663 #ifdef CONFIG_X86_64
2665 msr_info->data = svm->vmcb01.ptr->save.lstar;
2668 msr_info->data = svm->vmcb01.ptr->save.cstar;
2670 case MSR_KERNEL_GS_BASE:
2671 msr_info->data = svm->vmcb01.ptr->save.kernel_gs_base;
2673 case MSR_SYSCALL_MASK:
2674 msr_info->data = svm->vmcb01.ptr->save.sfmask;
2677 case MSR_IA32_SYSENTER_CS:
2678 msr_info->data = svm->vmcb01.ptr->save.sysenter_cs;
2680 case MSR_IA32_SYSENTER_EIP:
2681 msr_info->data = (u32)svm->vmcb01.ptr->save.sysenter_eip;
2682 if (guest_cpuid_is_intel(vcpu))
2683 msr_info->data |= (u64)svm->sysenter_eip_hi << 32;
2685 case MSR_IA32_SYSENTER_ESP:
2686 msr_info->data = svm->vmcb01.ptr->save.sysenter_esp;
2687 if (guest_cpuid_is_intel(vcpu))
2688 msr_info->data |= (u64)svm->sysenter_esp_hi << 32;
2691 msr_info->data = svm->tsc_aux;
2694 * Nobody will change the following 5 values in the VMCB so we can
2695 * safely return them on rdmsr. They will always be 0 until LBRV is
2698 case MSR_IA32_DEBUGCTLMSR:
2699 msr_info->data = svm->vmcb->save.dbgctl;
2701 case MSR_IA32_LASTBRANCHFROMIP:
2702 msr_info->data = svm->vmcb->save.br_from;
2704 case MSR_IA32_LASTBRANCHTOIP:
2705 msr_info->data = svm->vmcb->save.br_to;
2707 case MSR_IA32_LASTINTFROMIP:
2708 msr_info->data = svm->vmcb->save.last_excp_from;
2710 case MSR_IA32_LASTINTTOIP:
2711 msr_info->data = svm->vmcb->save.last_excp_to;
2713 case MSR_VM_HSAVE_PA:
2714 msr_info->data = svm->nested.hsave_msr;
2717 msr_info->data = svm->nested.vm_cr_msr;
2719 case MSR_IA32_SPEC_CTRL:
2720 if (!msr_info->host_initiated &&
2721 !guest_has_spec_ctrl_msr(vcpu))
2724 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL))
2725 msr_info->data = svm->vmcb->save.spec_ctrl;
2727 msr_info->data = svm->spec_ctrl;
2729 case MSR_AMD64_VIRT_SPEC_CTRL:
2730 if (!msr_info->host_initiated &&
2731 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2734 msr_info->data = svm->virt_spec_ctrl;
2736 case MSR_F15H_IC_CFG: {
2740 family = guest_cpuid_family(vcpu);
2741 model = guest_cpuid_model(vcpu);
2743 if (family < 0 || model < 0)
2744 return kvm_get_msr_common(vcpu, msr_info);
2748 if (family == 0x15 &&
2749 (model >= 0x2 && model < 0x20))
2750 msr_info->data = 0x1E;
2753 case MSR_F10H_DECFG:
2754 msr_info->data = svm->msr_decfg;
2757 return kvm_get_msr_common(vcpu, msr_info);
2762 static int svm_complete_emulated_msr(struct kvm_vcpu *vcpu, int err)
2764 struct vcpu_svm *svm = to_svm(vcpu);
2765 if (!err || !sev_es_guest(vcpu->kvm) || WARN_ON_ONCE(!svm->ghcb))
2766 return kvm_complete_insn_gp(vcpu, err);
2768 ghcb_set_sw_exit_info_1(svm->ghcb, 1);
2769 ghcb_set_sw_exit_info_2(svm->ghcb,
2771 SVM_EVTINJ_TYPE_EXEPT |
2776 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2778 struct vcpu_svm *svm = to_svm(vcpu);
2779 int svm_dis, chg_mask;
2781 if (data & ~SVM_VM_CR_VALID_MASK)
2784 chg_mask = SVM_VM_CR_VALID_MASK;
2786 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2787 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2789 svm->nested.vm_cr_msr &= ~chg_mask;
2790 svm->nested.vm_cr_msr |= (data & chg_mask);
2792 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2794 /* check for svm_disable while efer.svme is set */
2795 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2801 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2803 struct vcpu_svm *svm = to_svm(vcpu);
2806 u32 ecx = msr->index;
2807 u64 data = msr->data;
2809 case MSR_IA32_CR_PAT:
2810 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2812 vcpu->arch.pat = data;
2813 svm->vmcb01.ptr->save.g_pat = data;
2814 if (is_guest_mode(vcpu))
2815 nested_vmcb02_compute_g_pat(svm);
2816 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
2818 case MSR_IA32_SPEC_CTRL:
2819 if (!msr->host_initiated &&
2820 !guest_has_spec_ctrl_msr(vcpu))
2823 if (kvm_spec_ctrl_test_value(data))
2826 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL))
2827 svm->vmcb->save.spec_ctrl = data;
2829 svm->spec_ctrl = data;
2835 * When it's written (to non-zero) for the first time, pass
2839 * The handling of the MSR bitmap for L2 guests is done in
2840 * nested_svm_vmrun_msrpm.
2841 * We update the L1 MSR bit as well since it will end up
2842 * touching the MSR anyway now.
2844 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
2846 case MSR_IA32_PRED_CMD:
2847 if (!msr->host_initiated &&
2848 !guest_has_pred_cmd_msr(vcpu))
2851 if (data & ~PRED_CMD_IBPB)
2853 if (!boot_cpu_has(X86_FEATURE_IBPB))
2858 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2859 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
2861 case MSR_AMD64_VIRT_SPEC_CTRL:
2862 if (!msr->host_initiated &&
2863 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2866 if (data & ~SPEC_CTRL_SSBD)
2869 svm->virt_spec_ctrl = data;
2872 svm->vmcb01.ptr->save.star = data;
2874 #ifdef CONFIG_X86_64
2876 svm->vmcb01.ptr->save.lstar = data;
2879 svm->vmcb01.ptr->save.cstar = data;
2881 case MSR_KERNEL_GS_BASE:
2882 svm->vmcb01.ptr->save.kernel_gs_base = data;
2884 case MSR_SYSCALL_MASK:
2885 svm->vmcb01.ptr->save.sfmask = data;
2888 case MSR_IA32_SYSENTER_CS:
2889 svm->vmcb01.ptr->save.sysenter_cs = data;
2891 case MSR_IA32_SYSENTER_EIP:
2892 svm->vmcb01.ptr->save.sysenter_eip = (u32)data;
2894 * We only intercept the MSR_IA32_SYSENTER_{EIP|ESP} msrs
2895 * when we spoof an Intel vendor ID (for cross vendor migration).
2896 * In this case we use this intercept to track the high
2897 * 32 bit part of these msrs to support Intel's
2898 * implementation of SYSENTER/SYSEXIT.
2900 svm->sysenter_eip_hi = guest_cpuid_is_intel(vcpu) ? (data >> 32) : 0;
2902 case MSR_IA32_SYSENTER_ESP:
2903 svm->vmcb01.ptr->save.sysenter_esp = (u32)data;
2904 svm->sysenter_esp_hi = guest_cpuid_is_intel(vcpu) ? (data >> 32) : 0;
2908 * TSC_AUX is usually changed only during boot and never read
2909 * directly. Intercept TSC_AUX instead of exposing it to the
2910 * guest via direct_access_msrs, and switch it via user return.
2913 r = kvm_set_user_return_msr(tsc_aux_uret_slot, data, -1ull);
2918 svm->tsc_aux = data;
2920 case MSR_IA32_DEBUGCTLMSR:
2921 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2922 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2926 if (data & DEBUGCTL_RESERVED_BITS)
2929 svm->vmcb->save.dbgctl = data;
2930 vmcb_mark_dirty(svm->vmcb, VMCB_LBR);
2931 if (data & (1ULL<<0))
2932 svm_enable_lbrv(vcpu);
2934 svm_disable_lbrv(vcpu);
2936 case MSR_VM_HSAVE_PA:
2938 * Old kernels did not validate the value written to
2939 * MSR_VM_HSAVE_PA. Allow KVM_SET_MSR to set an invalid
2940 * value to allow live migrating buggy or malicious guests
2941 * originating from those kernels.
2943 if (!msr->host_initiated && !page_address_valid(vcpu, data))
2946 svm->nested.hsave_msr = data & PAGE_MASK;
2949 return svm_set_vm_cr(vcpu, data);
2951 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2953 case MSR_F10H_DECFG: {
2954 struct kvm_msr_entry msr_entry;
2956 msr_entry.index = msr->index;
2957 if (svm_get_msr_feature(&msr_entry))
2960 /* Check the supported bits */
2961 if (data & ~msr_entry.data)
2964 /* Don't allow the guest to change a bit, #GP */
2965 if (!msr->host_initiated && (data ^ msr_entry.data))
2968 svm->msr_decfg = data;
2972 return kvm_set_msr_common(vcpu, msr);
2977 static int msr_interception(struct kvm_vcpu *vcpu)
2979 if (to_svm(vcpu)->vmcb->control.exit_info_1)
2980 return kvm_emulate_wrmsr(vcpu);
2982 return kvm_emulate_rdmsr(vcpu);
2985 static int interrupt_window_interception(struct kvm_vcpu *vcpu)
2987 kvm_make_request(KVM_REQ_EVENT, vcpu);
2988 svm_clear_vintr(to_svm(vcpu));
2991 * For AVIC, the only reason to end up here is ExtINTs.
2992 * In this case AVIC was temporarily disabled for
2993 * requesting the IRQ window and we have to re-enable it.
2995 kvm_request_apicv_update(vcpu->kvm, true, APICV_INHIBIT_REASON_IRQWIN);
2997 ++vcpu->stat.irq_window_exits;
3001 static int pause_interception(struct kvm_vcpu *vcpu)
3006 * CPL is not made available for an SEV-ES guest, therefore
3007 * vcpu->arch.preempted_in_kernel can never be true. Just
3008 * set in_kernel to false as well.
3010 in_kernel = !sev_es_guest(vcpu->kvm) && svm_get_cpl(vcpu) == 0;
3012 if (!kvm_pause_in_guest(vcpu->kvm))
3013 grow_ple_window(vcpu);
3015 kvm_vcpu_on_spin(vcpu, in_kernel);
3016 return kvm_skip_emulated_instruction(vcpu);
3019 static int invpcid_interception(struct kvm_vcpu *vcpu)
3021 struct vcpu_svm *svm = to_svm(vcpu);
3025 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
3026 kvm_queue_exception(vcpu, UD_VECTOR);
3031 * For an INVPCID intercept:
3032 * EXITINFO1 provides the linear address of the memory operand.
3033 * EXITINFO2 provides the contents of the register operand.
3035 type = svm->vmcb->control.exit_info_2;
3036 gva = svm->vmcb->control.exit_info_1;
3039 kvm_inject_gp(vcpu, 0);
3043 return kvm_handle_invpcid(vcpu, type, gva);
3046 static int (*const svm_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3047 [SVM_EXIT_READ_CR0] = cr_interception,
3048 [SVM_EXIT_READ_CR3] = cr_interception,
3049 [SVM_EXIT_READ_CR4] = cr_interception,
3050 [SVM_EXIT_READ_CR8] = cr_interception,
3051 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
3052 [SVM_EXIT_WRITE_CR0] = cr_interception,
3053 [SVM_EXIT_WRITE_CR3] = cr_interception,
3054 [SVM_EXIT_WRITE_CR4] = cr_interception,
3055 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
3056 [SVM_EXIT_READ_DR0] = dr_interception,
3057 [SVM_EXIT_READ_DR1] = dr_interception,
3058 [SVM_EXIT_READ_DR2] = dr_interception,
3059 [SVM_EXIT_READ_DR3] = dr_interception,
3060 [SVM_EXIT_READ_DR4] = dr_interception,
3061 [SVM_EXIT_READ_DR5] = dr_interception,
3062 [SVM_EXIT_READ_DR6] = dr_interception,
3063 [SVM_EXIT_READ_DR7] = dr_interception,
3064 [SVM_EXIT_WRITE_DR0] = dr_interception,
3065 [SVM_EXIT_WRITE_DR1] = dr_interception,
3066 [SVM_EXIT_WRITE_DR2] = dr_interception,
3067 [SVM_EXIT_WRITE_DR3] = dr_interception,
3068 [SVM_EXIT_WRITE_DR4] = dr_interception,
3069 [SVM_EXIT_WRITE_DR5] = dr_interception,
3070 [SVM_EXIT_WRITE_DR6] = dr_interception,
3071 [SVM_EXIT_WRITE_DR7] = dr_interception,
3072 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
3073 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
3074 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
3075 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
3076 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
3077 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
3078 [SVM_EXIT_EXCP_BASE + GP_VECTOR] = gp_interception,
3079 [SVM_EXIT_INTR] = intr_interception,
3080 [SVM_EXIT_NMI] = nmi_interception,
3081 [SVM_EXIT_SMI] = smi_interception,
3082 [SVM_EXIT_VINTR] = interrupt_window_interception,
3083 [SVM_EXIT_RDPMC] = kvm_emulate_rdpmc,
3084 [SVM_EXIT_CPUID] = kvm_emulate_cpuid,
3085 [SVM_EXIT_IRET] = iret_interception,
3086 [SVM_EXIT_INVD] = kvm_emulate_invd,
3087 [SVM_EXIT_PAUSE] = pause_interception,
3088 [SVM_EXIT_HLT] = kvm_emulate_halt,
3089 [SVM_EXIT_INVLPG] = invlpg_interception,
3090 [SVM_EXIT_INVLPGA] = invlpga_interception,
3091 [SVM_EXIT_IOIO] = io_interception,
3092 [SVM_EXIT_MSR] = msr_interception,
3093 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
3094 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3095 [SVM_EXIT_VMRUN] = vmrun_interception,
3096 [SVM_EXIT_VMMCALL] = kvm_emulate_hypercall,
3097 [SVM_EXIT_VMLOAD] = vmload_interception,
3098 [SVM_EXIT_VMSAVE] = vmsave_interception,
3099 [SVM_EXIT_STGI] = stgi_interception,
3100 [SVM_EXIT_CLGI] = clgi_interception,
3101 [SVM_EXIT_SKINIT] = skinit_interception,
3102 [SVM_EXIT_RDTSCP] = kvm_handle_invalid_op,
3103 [SVM_EXIT_WBINVD] = kvm_emulate_wbinvd,
3104 [SVM_EXIT_MONITOR] = kvm_emulate_monitor,
3105 [SVM_EXIT_MWAIT] = kvm_emulate_mwait,
3106 [SVM_EXIT_XSETBV] = kvm_emulate_xsetbv,
3107 [SVM_EXIT_RDPRU] = kvm_handle_invalid_op,
3108 [SVM_EXIT_EFER_WRITE_TRAP] = efer_trap,
3109 [SVM_EXIT_CR0_WRITE_TRAP] = cr_trap,
3110 [SVM_EXIT_CR4_WRITE_TRAP] = cr_trap,
3111 [SVM_EXIT_CR8_WRITE_TRAP] = cr_trap,
3112 [SVM_EXIT_INVPCID] = invpcid_interception,
3113 [SVM_EXIT_NPF] = npf_interception,
3114 [SVM_EXIT_RSM] = rsm_interception,
3115 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
3116 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
3117 [SVM_EXIT_VMGEXIT] = sev_handle_vmgexit,
3120 static void dump_vmcb(struct kvm_vcpu *vcpu)
3122 struct vcpu_svm *svm = to_svm(vcpu);
3123 struct vmcb_control_area *control = &svm->vmcb->control;
3124 struct vmcb_save_area *save = &svm->vmcb->save;
3125 struct vmcb_save_area *save01 = &svm->vmcb01.ptr->save;
3127 if (!dump_invalid_vmcb) {
3128 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
3132 pr_err("VMCB %p, last attempted VMRUN on CPU %d\n",
3133 svm->current_vmcb->ptr, vcpu->arch.last_vmentry_cpu);
3134 pr_err("VMCB Control Area:\n");
3135 pr_err("%-20s%04x\n", "cr_read:", control->intercepts[INTERCEPT_CR] & 0xffff);
3136 pr_err("%-20s%04x\n", "cr_write:", control->intercepts[INTERCEPT_CR] >> 16);
3137 pr_err("%-20s%04x\n", "dr_read:", control->intercepts[INTERCEPT_DR] & 0xffff);
3138 pr_err("%-20s%04x\n", "dr_write:", control->intercepts[INTERCEPT_DR] >> 16);
3139 pr_err("%-20s%08x\n", "exceptions:", control->intercepts[INTERCEPT_EXCEPTION]);
3140 pr_err("%-20s%08x %08x\n", "intercepts:",
3141 control->intercepts[INTERCEPT_WORD3],
3142 control->intercepts[INTERCEPT_WORD4]);
3143 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3144 pr_err("%-20s%d\n", "pause filter threshold:",
3145 control->pause_filter_thresh);
3146 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3147 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3148 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3149 pr_err("%-20s%d\n", "asid:", control->asid);
3150 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3151 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3152 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3153 pr_err("%-20s%08x\n", "int_state:", control->int_state);
3154 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3155 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3156 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3157 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3158 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3159 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3160 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3161 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
3162 pr_err("%-20s%016llx\n", "ghcb:", control->ghcb_gpa);
3163 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3164 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3165 pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
3166 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3167 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
3168 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
3169 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
3170 pr_err("%-20s%016llx\n", "vmsa_pa:", control->vmsa_pa);
3171 pr_err("VMCB State Save Area:\n");
3172 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3174 save->es.selector, save->es.attrib,
3175 save->es.limit, save->es.base);
3176 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3178 save->cs.selector, save->cs.attrib,
3179 save->cs.limit, save->cs.base);
3180 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3182 save->ss.selector, save->ss.attrib,
3183 save->ss.limit, save->ss.base);
3184 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3186 save->ds.selector, save->ds.attrib,
3187 save->ds.limit, save->ds.base);
3188 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3190 save01->fs.selector, save01->fs.attrib,
3191 save01->fs.limit, save01->fs.base);
3192 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3194 save01->gs.selector, save01->gs.attrib,
3195 save01->gs.limit, save01->gs.base);
3196 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3198 save->gdtr.selector, save->gdtr.attrib,
3199 save->gdtr.limit, save->gdtr.base);
3200 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3202 save01->ldtr.selector, save01->ldtr.attrib,
3203 save01->ldtr.limit, save01->ldtr.base);
3204 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3206 save->idtr.selector, save->idtr.attrib,
3207 save->idtr.limit, save->idtr.base);
3208 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3210 save01->tr.selector, save01->tr.attrib,
3211 save01->tr.limit, save01->tr.base);
3212 pr_err("cpl: %d efer: %016llx\n",
3213 save->cpl, save->efer);
3214 pr_err("%-15s %016llx %-13s %016llx\n",
3215 "cr0:", save->cr0, "cr2:", save->cr2);
3216 pr_err("%-15s %016llx %-13s %016llx\n",
3217 "cr3:", save->cr3, "cr4:", save->cr4);
3218 pr_err("%-15s %016llx %-13s %016llx\n",
3219 "dr6:", save->dr6, "dr7:", save->dr7);
3220 pr_err("%-15s %016llx %-13s %016llx\n",
3221 "rip:", save->rip, "rflags:", save->rflags);
3222 pr_err("%-15s %016llx %-13s %016llx\n",
3223 "rsp:", save->rsp, "rax:", save->rax);
3224 pr_err("%-15s %016llx %-13s %016llx\n",
3225 "star:", save01->star, "lstar:", save01->lstar);
3226 pr_err("%-15s %016llx %-13s %016llx\n",
3227 "cstar:", save01->cstar, "sfmask:", save01->sfmask);
3228 pr_err("%-15s %016llx %-13s %016llx\n",
3229 "kernel_gs_base:", save01->kernel_gs_base,
3230 "sysenter_cs:", save01->sysenter_cs);
3231 pr_err("%-15s %016llx %-13s %016llx\n",
3232 "sysenter_esp:", save01->sysenter_esp,
3233 "sysenter_eip:", save01->sysenter_eip);
3234 pr_err("%-15s %016llx %-13s %016llx\n",
3235 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3236 pr_err("%-15s %016llx %-13s %016llx\n",
3237 "br_from:", save->br_from, "br_to:", save->br_to);
3238 pr_err("%-15s %016llx %-13s %016llx\n",
3239 "excp_from:", save->last_excp_from,
3240 "excp_to:", save->last_excp_to);
3243 static bool svm_check_exit_valid(struct kvm_vcpu *vcpu, u64 exit_code)
3245 return (exit_code < ARRAY_SIZE(svm_exit_handlers) &&
3246 svm_exit_handlers[exit_code]);
3249 static int svm_handle_invalid_exit(struct kvm_vcpu *vcpu, u64 exit_code)
3251 vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%llx\n", exit_code);
3253 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3254 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
3255 vcpu->run->internal.ndata = 2;
3256 vcpu->run->internal.data[0] = exit_code;
3257 vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
3261 int svm_invoke_exit_handler(struct kvm_vcpu *vcpu, u64 exit_code)
3263 if (!svm_check_exit_valid(vcpu, exit_code))
3264 return svm_handle_invalid_exit(vcpu, exit_code);
3266 #ifdef CONFIG_RETPOLINE
3267 if (exit_code == SVM_EXIT_MSR)
3268 return msr_interception(vcpu);
3269 else if (exit_code == SVM_EXIT_VINTR)
3270 return interrupt_window_interception(vcpu);
3271 else if (exit_code == SVM_EXIT_INTR)
3272 return intr_interception(vcpu);
3273 else if (exit_code == SVM_EXIT_HLT)
3274 return kvm_emulate_halt(vcpu);
3275 else if (exit_code == SVM_EXIT_NPF)
3276 return npf_interception(vcpu);
3278 return svm_exit_handlers[exit_code](vcpu);
3281 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2,
3282 u32 *intr_info, u32 *error_code)
3284 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3286 *info1 = control->exit_info_1;
3287 *info2 = control->exit_info_2;
3288 *intr_info = control->exit_int_info;
3289 if ((*intr_info & SVM_EXITINTINFO_VALID) &&
3290 (*intr_info & SVM_EXITINTINFO_VALID_ERR))
3291 *error_code = control->exit_int_info_err;
3296 static int handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
3298 struct vcpu_svm *svm = to_svm(vcpu);
3299 struct kvm_run *kvm_run = vcpu->run;
3300 u32 exit_code = svm->vmcb->control.exit_code;
3302 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
3304 /* SEV-ES guests must use the CR write traps to track CR registers. */
3305 if (!sev_es_guest(vcpu->kvm)) {
3306 if (!svm_is_intercept(svm, INTERCEPT_CR0_WRITE))
3307 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3309 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3312 if (is_guest_mode(vcpu)) {
3315 trace_kvm_nested_vmexit(exit_code, vcpu, KVM_ISA_SVM);
3317 vmexit = nested_svm_exit_special(svm);
3319 if (vmexit == NESTED_EXIT_CONTINUE)
3320 vmexit = nested_svm_exit_handled(svm);
3322 if (vmexit == NESTED_EXIT_DONE)
3326 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3327 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3328 kvm_run->fail_entry.hardware_entry_failure_reason
3329 = svm->vmcb->control.exit_code;
3330 kvm_run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
3335 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3336 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3337 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3338 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3339 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
3341 __func__, svm->vmcb->control.exit_int_info,
3344 if (exit_fastpath != EXIT_FASTPATH_NONE)
3347 return svm_invoke_exit_handler(vcpu, exit_code);
3350 static void reload_tss(struct kvm_vcpu *vcpu)
3352 struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3354 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3358 static void pre_svm_run(struct kvm_vcpu *vcpu)
3360 struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3361 struct vcpu_svm *svm = to_svm(vcpu);
3364 * If the previous vmrun of the vmcb occurred on a different physical
3365 * cpu, then mark the vmcb dirty and assign a new asid. Hardware's
3366 * vmcb clean bits are per logical CPU, as are KVM's asid assignments.
3368 if (unlikely(svm->current_vmcb->cpu != vcpu->cpu)) {
3369 svm->current_vmcb->asid_generation = 0;
3370 vmcb_mark_all_dirty(svm->vmcb);
3371 svm->current_vmcb->cpu = vcpu->cpu;
3374 if (sev_guest(vcpu->kvm))
3375 return pre_sev_run(svm, vcpu->cpu);
3377 /* FIXME: handle wraparound of asid_generation */
3378 if (svm->current_vmcb->asid_generation != sd->asid_generation)
3382 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3384 struct vcpu_svm *svm = to_svm(vcpu);
3386 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3387 vcpu->arch.hflags |= HF_NMI_MASK;
3388 if (!sev_es_guest(vcpu->kvm))
3389 svm_set_intercept(svm, INTERCEPT_IRET);
3390 ++vcpu->stat.nmi_injections;
3393 static void svm_set_irq(struct kvm_vcpu *vcpu)
3395 struct vcpu_svm *svm = to_svm(vcpu);
3397 BUG_ON(!(gif_set(svm)));
3399 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3400 ++vcpu->stat.irq_injections;
3402 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3403 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3406 static void svm_update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3408 struct vcpu_svm *svm = to_svm(vcpu);
3411 * SEV-ES guests must always keep the CR intercepts cleared. CR
3412 * tracking is done using the CR write traps.
3414 if (sev_es_guest(vcpu->kvm))
3417 if (nested_svm_virtualize_tpr(vcpu))
3420 svm_clr_intercept(svm, INTERCEPT_CR8_WRITE);
3426 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
3429 bool svm_nmi_blocked(struct kvm_vcpu *vcpu)
3431 struct vcpu_svm *svm = to_svm(vcpu);
3432 struct vmcb *vmcb = svm->vmcb;
3438 if (is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3441 ret = (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
3442 (vcpu->arch.hflags & HF_NMI_MASK);
3447 static int svm_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3449 struct vcpu_svm *svm = to_svm(vcpu);
3450 if (svm->nested.nested_run_pending)
3453 /* An NMI must not be injected into L2 if it's supposed to VM-Exit. */
3454 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3457 return !svm_nmi_blocked(vcpu);
3460 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3462 return !!(vcpu->arch.hflags & HF_NMI_MASK);
3465 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3467 struct vcpu_svm *svm = to_svm(vcpu);
3470 vcpu->arch.hflags |= HF_NMI_MASK;
3471 if (!sev_es_guest(vcpu->kvm))
3472 svm_set_intercept(svm, INTERCEPT_IRET);
3474 vcpu->arch.hflags &= ~HF_NMI_MASK;
3475 if (!sev_es_guest(vcpu->kvm))
3476 svm_clr_intercept(svm, INTERCEPT_IRET);
3480 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu)
3482 struct vcpu_svm *svm = to_svm(vcpu);
3483 struct vmcb *vmcb = svm->vmcb;
3488 if (sev_es_guest(vcpu->kvm)) {
3490 * SEV-ES guests to not expose RFLAGS. Use the VMCB interrupt mask
3491 * bit to determine the state of the IF flag.
3493 if (!(vmcb->control.int_state & SVM_GUEST_INTERRUPT_MASK))
3495 } else if (is_guest_mode(vcpu)) {
3496 /* As long as interrupts are being delivered... */
3497 if ((svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK)
3498 ? !(svm->vmcb01.ptr->save.rflags & X86_EFLAGS_IF)
3499 : !(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3502 /* ... vmexits aren't blocked by the interrupt shadow */
3503 if (nested_exit_on_intr(svm))
3506 if (!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3510 return (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK);
3513 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3515 struct vcpu_svm *svm = to_svm(vcpu);
3516 if (svm->nested.nested_run_pending)
3520 * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
3521 * e.g. if the IRQ arrived asynchronously after checking nested events.
3523 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(svm))
3526 return !svm_interrupt_blocked(vcpu);
3529 static void svm_enable_irq_window(struct kvm_vcpu *vcpu)
3531 struct vcpu_svm *svm = to_svm(vcpu);
3534 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3535 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3536 * get that intercept, this function will be called again though and
3537 * we'll get the vintr intercept. However, if the vGIF feature is
3538 * enabled, the STGI interception will not occur. Enable the irq
3539 * window under the assumption that the hardware will set the GIF.
3541 if (vgif_enabled(svm) || gif_set(svm)) {
3543 * IRQ window is not needed when AVIC is enabled,
3544 * unless we have pending ExtINT since it cannot be injected
3545 * via AVIC. In such case, we need to temporarily disable AVIC,
3546 * and fallback to injecting IRQ via V_IRQ.
3548 kvm_request_apicv_update(vcpu->kvm, false, APICV_INHIBIT_REASON_IRQWIN);
3553 static void svm_enable_nmi_window(struct kvm_vcpu *vcpu)
3555 struct vcpu_svm *svm = to_svm(vcpu);
3557 if ((vcpu->arch.hflags & (HF_NMI_MASK | HF_IRET_MASK)) == HF_NMI_MASK)
3558 return; /* IRET will cause a vm exit */
3560 if (!gif_set(svm)) {
3561 if (vgif_enabled(svm))
3562 svm_set_intercept(svm, INTERCEPT_STGI);
3563 return; /* STGI will cause a vm exit */
3567 * Something prevents NMI from been injected. Single step over possible
3568 * problem (IRET or exception injection or interrupt shadow)
3570 svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
3571 svm->nmi_singlestep = true;
3572 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3575 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3580 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
3585 void svm_flush_tlb(struct kvm_vcpu *vcpu)
3587 struct vcpu_svm *svm = to_svm(vcpu);
3590 * Flush only the current ASID even if the TLB flush was invoked via
3591 * kvm_flush_remote_tlbs(). Although flushing remote TLBs requires all
3592 * ASIDs to be flushed, KVM uses a single ASID for L1 and L2, and
3593 * unconditionally does a TLB flush on both nested VM-Enter and nested
3594 * VM-Exit (via kvm_mmu_reset_context()).
3596 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3597 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3599 svm->current_vmcb->asid_generation--;
3602 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
3604 struct vcpu_svm *svm = to_svm(vcpu);
3606 invlpga(gva, svm->vmcb->control.asid);
3609 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3611 struct vcpu_svm *svm = to_svm(vcpu);
3613 if (nested_svm_virtualize_tpr(vcpu))
3616 if (!svm_is_intercept(svm, INTERCEPT_CR8_WRITE)) {
3617 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3618 kvm_set_cr8(vcpu, cr8);
3622 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3624 struct vcpu_svm *svm = to_svm(vcpu);
3627 if (nested_svm_virtualize_tpr(vcpu) ||
3628 kvm_vcpu_apicv_active(vcpu))
3631 cr8 = kvm_get_cr8(vcpu);
3632 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3633 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3636 static void svm_complete_interrupts(struct kvm_vcpu *vcpu)
3638 struct vcpu_svm *svm = to_svm(vcpu);
3641 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3642 unsigned int3_injected = svm->int3_injected;
3644 svm->int3_injected = 0;
3647 * If we've made progress since setting HF_IRET_MASK, we've
3648 * executed an IRET and can allow NMI injection.
3650 if ((vcpu->arch.hflags & HF_IRET_MASK) &&
3651 (sev_es_guest(vcpu->kvm) ||
3652 kvm_rip_read(vcpu) != svm->nmi_iret_rip)) {
3653 vcpu->arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3654 kvm_make_request(KVM_REQ_EVENT, vcpu);
3657 vcpu->arch.nmi_injected = false;
3658 kvm_clear_exception_queue(vcpu);
3659 kvm_clear_interrupt_queue(vcpu);
3661 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3664 kvm_make_request(KVM_REQ_EVENT, vcpu);
3666 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3667 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3670 case SVM_EXITINTINFO_TYPE_NMI:
3671 vcpu->arch.nmi_injected = true;
3673 case SVM_EXITINTINFO_TYPE_EXEPT:
3675 * Never re-inject a #VC exception.
3677 if (vector == X86_TRAP_VC)
3681 * In case of software exceptions, do not reinject the vector,
3682 * but re-execute the instruction instead. Rewind RIP first
3683 * if we emulated INT3 before.
3685 if (kvm_exception_is_soft(vector)) {
3686 if (vector == BP_VECTOR && int3_injected &&
3687 kvm_is_linear_rip(vcpu, svm->int3_rip))
3689 kvm_rip_read(vcpu) - int3_injected);
3692 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3693 u32 err = svm->vmcb->control.exit_int_info_err;
3694 kvm_requeue_exception_e(vcpu, vector, err);
3697 kvm_requeue_exception(vcpu, vector);
3699 case SVM_EXITINTINFO_TYPE_INTR:
3700 kvm_queue_interrupt(vcpu, vector, false);
3707 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3709 struct vcpu_svm *svm = to_svm(vcpu);
3710 struct vmcb_control_area *control = &svm->vmcb->control;
3712 control->exit_int_info = control->event_inj;
3713 control->exit_int_info_err = control->event_inj_err;
3714 control->event_inj = 0;
3715 svm_complete_interrupts(vcpu);
3718 static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
3720 if (to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_MSR &&
3721 to_svm(vcpu)->vmcb->control.exit_info_1)
3722 return handle_fastpath_set_msr_irqoff(vcpu);
3724 return EXIT_FASTPATH_NONE;
3727 static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu)
3729 struct vcpu_svm *svm = to_svm(vcpu);
3730 unsigned long vmcb_pa = svm->current_vmcb->pa;
3732 kvm_guest_enter_irqoff();
3734 if (sev_es_guest(vcpu->kvm)) {
3735 __svm_sev_es_vcpu_run(vmcb_pa);
3737 struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3740 * Use a single vmcb (vmcb01 because it's always valid) for
3741 * context switching guest state via VMLOAD/VMSAVE, that way
3742 * the state doesn't need to be copied between vmcb01 and
3743 * vmcb02 when switching vmcbs for nested virtualization.
3745 vmload(svm->vmcb01.pa);
3746 __svm_vcpu_run(vmcb_pa, (unsigned long *)&vcpu->arch.regs);
3747 vmsave(svm->vmcb01.pa);
3749 vmload(__sme_page_pa(sd->save_area));
3752 kvm_guest_exit_irqoff();
3755 static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu)
3757 struct vcpu_svm *svm = to_svm(vcpu);
3759 trace_kvm_entry(vcpu);
3761 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3762 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3763 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3766 * Disable singlestep if we're injecting an interrupt/exception.
3767 * We don't want our modified rflags to be pushed on the stack where
3768 * we might not be able to easily reset them if we disabled NMI
3771 if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
3773 * Event injection happens before external interrupts cause a
3774 * vmexit and interrupts are disabled here, so smp_send_reschedule
3775 * is enough to force an immediate vmexit.
3777 disable_nmi_singlestep(svm);
3778 smp_send_reschedule(vcpu->cpu);
3783 WARN_ON_ONCE(kvm_apicv_activated(vcpu->kvm) != kvm_vcpu_apicv_active(vcpu));
3785 sync_lapic_to_cr8(vcpu);
3787 if (unlikely(svm->asid != svm->vmcb->control.asid)) {
3788 svm->vmcb->control.asid = svm->asid;
3789 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
3791 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3793 svm_hv_update_vp_id(svm->vmcb, vcpu);
3796 * Run with all-zero DR6 unless needed, so that we can get the exact cause
3799 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
3800 svm_set_dr6(svm, vcpu->arch.dr6);
3802 svm_set_dr6(svm, DR6_ACTIVE_LOW);
3805 kvm_load_guest_xsave_state(vcpu);
3807 kvm_wait_lapic_expire(vcpu);
3810 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
3811 * it's non-zero. Since vmentry is serialising on affected CPUs, there
3812 * is no need to worry about the conditional branch over the wrmsr
3813 * being speculatively taken.
3815 if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL))
3816 x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
3818 svm_vcpu_enter_exit(vcpu);
3821 * We do not use IBRS in the kernel. If this vCPU has used the
3822 * SPEC_CTRL MSR it may have left it on; save the value and
3823 * turn it off. This is much more efficient than blindly adding
3824 * it to the atomic save/restore list. Especially as the former
3825 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
3827 * For non-nested case:
3828 * If the L01 MSR bitmap does not intercept the MSR, then we need to
3832 * If the L02 MSR bitmap does not intercept the MSR, then we need to
3835 if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL) &&
3836 unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
3837 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
3839 if (!sev_es_guest(vcpu->kvm))
3842 if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL))
3843 x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
3845 if (!sev_es_guest(vcpu->kvm)) {
3846 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3847 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3848 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3849 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3852 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3853 kvm_before_interrupt(vcpu);
3855 kvm_load_host_xsave_state(vcpu);
3858 /* Any pending NMI will happen here */
3860 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3861 kvm_after_interrupt(vcpu);
3863 sync_cr8_to_lapic(vcpu);
3866 if (is_guest_mode(vcpu)) {
3867 nested_sync_control_from_vmcb02(svm);
3869 /* Track VMRUNs that have made past consistency checking */
3870 if (svm->nested.nested_run_pending &&
3871 svm->vmcb->control.exit_code != SVM_EXIT_ERR)
3872 ++vcpu->stat.nested_run;
3874 svm->nested.nested_run_pending = 0;
3877 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3878 vmcb_mark_all_clean(svm->vmcb);
3880 /* if exit due to PF check for async PF */
3881 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3882 vcpu->arch.apf.host_apf_flags =
3883 kvm_read_and_reset_apf_flags();
3886 kvm_register_clear_available(vcpu, VCPU_EXREG_PDPTR);
3889 * We need to handle MC intercepts here before the vcpu has a chance to
3890 * change the physical cpu
3892 if (unlikely(svm->vmcb->control.exit_code ==
3893 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3894 svm_handle_mce(vcpu);
3896 svm_complete_interrupts(vcpu);
3898 if (is_guest_mode(vcpu))
3899 return EXIT_FASTPATH_NONE;
3901 return svm_exit_handlers_fastpath(vcpu);
3904 static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, hpa_t root_hpa,
3907 struct vcpu_svm *svm = to_svm(vcpu);
3911 svm->vmcb->control.nested_cr3 = __sme_set(root_hpa);
3912 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
3914 hv_track_root_tdp(vcpu, root_hpa);
3916 /* Loading L2's CR3 is handled by enter_svm_guest_mode. */
3917 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3919 cr3 = vcpu->arch.cr3;
3920 } else if (vcpu->arch.mmu->shadow_root_level >= PT64_ROOT_4LEVEL) {
3921 cr3 = __sme_set(root_hpa) | kvm_get_active_pcid(vcpu);
3923 /* PCID in the guest should be impossible with a 32-bit MMU. */
3924 WARN_ON_ONCE(kvm_get_active_pcid(vcpu));
3928 svm->vmcb->save.cr3 = cr3;
3929 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
3932 static int is_disabled(void)
3936 rdmsrl(MSR_VM_CR, vm_cr);
3937 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3944 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3947 * Patch in the VMMCALL instruction:
3949 hypercall[0] = 0x0f;
3950 hypercall[1] = 0x01;
3951 hypercall[2] = 0xd9;
3954 static int __init svm_check_processor_compat(void)
3959 static bool svm_cpu_has_accelerated_tpr(void)
3965 * The kvm parameter can be NULL (module initialization, or invocation before
3966 * VM creation). Be sure to check the kvm parameter before using it.
3968 static bool svm_has_emulated_msr(struct kvm *kvm, u32 index)
3971 case MSR_IA32_MCG_EXT_CTL:
3972 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3974 case MSR_IA32_SMBASE:
3975 /* SEV-ES guests do not support SMM, so report false */
3976 if (kvm && sev_es_guest(kvm))
3986 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3991 static void svm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
3993 struct vcpu_svm *svm = to_svm(vcpu);
3994 struct kvm_cpuid_entry2 *best;
3996 vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
3997 boot_cpu_has(X86_FEATURE_XSAVE) &&
3998 boot_cpu_has(X86_FEATURE_XSAVES);
4000 /* Update nrips enabled cache */
4001 svm->nrips_enabled = kvm_cpu_cap_has(X86_FEATURE_NRIPS) &&
4002 guest_cpuid_has(vcpu, X86_FEATURE_NRIPS);
4004 svm_recalc_instruction_intercepts(vcpu, svm);
4006 /* For sev guests, the memory encryption bit is not reserved in CR3. */
4007 if (sev_guest(vcpu->kvm)) {
4008 best = kvm_find_cpuid_entry(vcpu, 0x8000001F, 0);
4010 vcpu->arch.reserved_gpa_bits &= ~(1UL << (best->ebx & 0x3f));
4013 if (kvm_vcpu_apicv_active(vcpu)) {
4015 * AVIC does not work with an x2APIC mode guest. If the X2APIC feature
4016 * is exposed to the guest, disable AVIC.
4018 if (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC))
4019 kvm_request_apicv_update(vcpu->kvm, false,
4020 APICV_INHIBIT_REASON_X2APIC);
4023 * Currently, AVIC does not work with nested virtualization.
4024 * So, we disable AVIC when cpuid for SVM is set in the L1 guest.
4026 if (nested && guest_cpuid_has(vcpu, X86_FEATURE_SVM))
4027 kvm_request_apicv_update(vcpu->kvm, false,
4028 APICV_INHIBIT_REASON_NESTED);
4031 if (guest_cpuid_is_intel(vcpu)) {
4033 * We must intercept SYSENTER_EIP and SYSENTER_ESP
4034 * accesses because the processor only stores 32 bits.
4035 * For the same reason we cannot use virtual VMLOAD/VMSAVE.
4037 svm_set_intercept(svm, INTERCEPT_VMLOAD);
4038 svm_set_intercept(svm, INTERCEPT_VMSAVE);
4039 svm->vmcb->control.virt_ext &= ~VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
4041 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_EIP, 0, 0);
4042 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_ESP, 0, 0);
4045 * If hardware supports Virtual VMLOAD VMSAVE then enable it
4046 * in VMCB and clear intercepts to avoid #VMEXIT.
4049 svm_clr_intercept(svm, INTERCEPT_VMLOAD);
4050 svm_clr_intercept(svm, INTERCEPT_VMSAVE);
4051 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
4053 /* No need to intercept these MSRs */
4054 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
4055 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
4059 static bool svm_has_wbinvd_exit(void)
4064 #define PRE_EX(exit) { .exit_code = (exit), \
4065 .stage = X86_ICPT_PRE_EXCEPT, }
4066 #define POST_EX(exit) { .exit_code = (exit), \
4067 .stage = X86_ICPT_POST_EXCEPT, }
4068 #define POST_MEM(exit) { .exit_code = (exit), \
4069 .stage = X86_ICPT_POST_MEMACCESS, }
4071 static const struct __x86_intercept {
4073 enum x86_intercept_stage stage;
4074 } x86_intercept_map[] = {
4075 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
4076 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
4077 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
4078 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
4079 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
4080 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
4081 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
4082 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
4083 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
4084 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
4085 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
4086 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
4087 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
4088 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
4089 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
4090 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
4091 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
4092 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
4093 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
4094 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
4095 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
4096 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
4097 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
4098 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
4099 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
4100 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
4101 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
4102 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
4103 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
4104 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
4105 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
4106 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
4107 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
4108 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
4109 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
4110 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
4111 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
4112 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
4113 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
4114 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
4115 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
4116 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
4117 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
4118 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
4119 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
4120 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
4121 [x86_intercept_xsetbv] = PRE_EX(SVM_EXIT_XSETBV),
4128 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4129 struct x86_instruction_info *info,
4130 enum x86_intercept_stage stage,
4131 struct x86_exception *exception)
4133 struct vcpu_svm *svm = to_svm(vcpu);
4134 int vmexit, ret = X86EMUL_CONTINUE;
4135 struct __x86_intercept icpt_info;
4136 struct vmcb *vmcb = svm->vmcb;
4138 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4141 icpt_info = x86_intercept_map[info->intercept];
4143 if (stage != icpt_info.stage)
4146 switch (icpt_info.exit_code) {
4147 case SVM_EXIT_READ_CR0:
4148 if (info->intercept == x86_intercept_cr_read)
4149 icpt_info.exit_code += info->modrm_reg;
4151 case SVM_EXIT_WRITE_CR0: {
4152 unsigned long cr0, val;
4154 if (info->intercept == x86_intercept_cr_write)
4155 icpt_info.exit_code += info->modrm_reg;
4157 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
4158 info->intercept == x86_intercept_clts)
4161 if (!(vmcb_is_intercept(&svm->nested.ctl,
4162 INTERCEPT_SELECTIVE_CR0)))
4165 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4166 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
4168 if (info->intercept == x86_intercept_lmsw) {
4171 /* lmsw can't clear PE - catch this here */
4172 if (cr0 & X86_CR0_PE)
4177 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4181 case SVM_EXIT_READ_DR0:
4182 case SVM_EXIT_WRITE_DR0:
4183 icpt_info.exit_code += info->modrm_reg;
4186 if (info->intercept == x86_intercept_wrmsr)
4187 vmcb->control.exit_info_1 = 1;
4189 vmcb->control.exit_info_1 = 0;
4191 case SVM_EXIT_PAUSE:
4193 * We get this for NOP only, but pause
4194 * is rep not, check this here
4196 if (info->rep_prefix != REPE_PREFIX)
4199 case SVM_EXIT_IOIO: {
4203 if (info->intercept == x86_intercept_in ||
4204 info->intercept == x86_intercept_ins) {
4205 exit_info = ((info->src_val & 0xffff) << 16) |
4207 bytes = info->dst_bytes;
4209 exit_info = (info->dst_val & 0xffff) << 16;
4210 bytes = info->src_bytes;
4213 if (info->intercept == x86_intercept_outs ||
4214 info->intercept == x86_intercept_ins)
4215 exit_info |= SVM_IOIO_STR_MASK;
4217 if (info->rep_prefix)
4218 exit_info |= SVM_IOIO_REP_MASK;
4220 bytes = min(bytes, 4u);
4222 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4224 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4226 vmcb->control.exit_info_1 = exit_info;
4227 vmcb->control.exit_info_2 = info->next_rip;
4235 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
4236 if (static_cpu_has(X86_FEATURE_NRIPS))
4237 vmcb->control.next_rip = info->next_rip;
4238 vmcb->control.exit_code = icpt_info.exit_code;
4239 vmexit = nested_svm_exit_handled(svm);
4241 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4248 static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu)
4252 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
4254 if (!kvm_pause_in_guest(vcpu->kvm))
4255 shrink_ple_window(vcpu);
4258 static void svm_setup_mce(struct kvm_vcpu *vcpu)
4260 /* [63:9] are reserved. */
4261 vcpu->arch.mcg_cap &= 0x1ff;
4264 bool svm_smi_blocked(struct kvm_vcpu *vcpu)
4266 struct vcpu_svm *svm = to_svm(vcpu);
4268 /* Per APM Vol.2 15.22.2 "Response to SMI" */
4272 return is_smm(vcpu);
4275 static int svm_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4277 struct vcpu_svm *svm = to_svm(vcpu);
4278 if (svm->nested.nested_run_pending)
4281 /* An SMI must not be injected into L2 if it's supposed to VM-Exit. */
4282 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_smi(svm))
4285 return !svm_smi_blocked(vcpu);
4288 static int svm_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
4290 struct vcpu_svm *svm = to_svm(vcpu);
4291 struct kvm_host_map map_save;
4294 if (!is_guest_mode(vcpu))
4297 /* FED8h - SVM Guest */
4298 put_smstate(u64, smstate, 0x7ed8, 1);
4299 /* FEE0h - SVM Guest VMCB Physical Address */
4300 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb12_gpa);
4302 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4303 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4304 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4306 ret = nested_svm_vmexit(svm);
4311 * KVM uses VMCB01 to store L1 host state while L2 runs but
4312 * VMCB01 is going to be used during SMM and thus the state will
4313 * be lost. Temporary save non-VMLOAD/VMSAVE state to the host save
4314 * area pointed to by MSR_VM_HSAVE_PA. APM guarantees that the
4315 * format of the area is identical to guest save area offsetted
4316 * by 0x400 (matches the offset of 'struct vmcb_save_area'
4317 * within 'struct vmcb'). Note: HSAVE area may also be used by
4318 * L1 hypervisor to save additional host context (e.g. KVM does
4319 * that, see svm_prepare_guest_switch()) which must be
4322 if (kvm_vcpu_map(vcpu, gpa_to_gfn(svm->nested.hsave_msr),
4323 &map_save) == -EINVAL)
4326 BUILD_BUG_ON(offsetof(struct vmcb, save) != 0x400);
4328 svm_copy_vmrun_state(map_save.hva + 0x400,
4329 &svm->vmcb01.ptr->save);
4331 kvm_vcpu_unmap(vcpu, &map_save, true);
4335 static int svm_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
4337 struct vcpu_svm *svm = to_svm(vcpu);
4338 struct kvm_host_map map, map_save;
4339 u64 saved_efer, vmcb12_gpa;
4340 struct vmcb *vmcb12;
4343 if (!guest_cpuid_has(vcpu, X86_FEATURE_LM))
4346 /* Non-zero if SMI arrived while vCPU was in guest mode. */
4347 if (!GET_SMSTATE(u64, smstate, 0x7ed8))
4350 if (!guest_cpuid_has(vcpu, X86_FEATURE_SVM))
4353 saved_efer = GET_SMSTATE(u64, smstate, 0x7ed0);
4354 if (!(saved_efer & EFER_SVME))
4357 vmcb12_gpa = GET_SMSTATE(u64, smstate, 0x7ee0);
4358 if (kvm_vcpu_map(vcpu, gpa_to_gfn(vmcb12_gpa), &map) == -EINVAL)
4362 if (kvm_vcpu_map(vcpu, gpa_to_gfn(svm->nested.hsave_msr), &map_save) == -EINVAL)
4365 if (svm_allocate_nested(svm))
4369 * Restore L1 host state from L1 HSAVE area as VMCB01 was
4370 * used during SMM (see svm_enter_smm())
4373 svm_copy_vmrun_state(&svm->vmcb01.ptr->save, map_save.hva + 0x400);
4376 * Enter the nested guest now
4380 nested_load_control_from_vmcb12(svm, &vmcb12->control);
4381 ret = enter_svm_guest_mode(vcpu, vmcb12_gpa, vmcb12, false);
4384 kvm_vcpu_unmap(vcpu, &map_save, true);
4386 kvm_vcpu_unmap(vcpu, &map, true);
4390 static void svm_enable_smi_window(struct kvm_vcpu *vcpu)
4392 struct vcpu_svm *svm = to_svm(vcpu);
4394 if (!gif_set(svm)) {
4395 if (vgif_enabled(svm))
4396 svm_set_intercept(svm, INTERCEPT_STGI);
4397 /* STGI will cause a vm exit */
4399 /* We must be in SMM; RSM will cause a vmexit anyway. */
4403 static bool svm_can_emulate_instruction(struct kvm_vcpu *vcpu, void *insn, int insn_len)
4405 bool smep, smap, is_user;
4409 * When the guest is an SEV-ES guest, emulation is not possible.
4411 if (sev_es_guest(vcpu->kvm))
4415 * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
4418 * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is
4419 * possible that CPU microcode implementing DecodeAssist will fail
4420 * to read bytes of instruction which caused #NPF. In this case,
4421 * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly
4422 * return 0 instead of the correct guest instruction bytes.
4424 * This happens because CPU microcode reading instruction bytes
4425 * uses a special opcode which attempts to read data using CPL=0
4426 * privileges. The microcode reads CS:RIP and if it hits a SMAP
4427 * fault, it gives up and returns no instruction bytes.
4430 * We reach here in case CPU supports DecodeAssist, raised #NPF and
4431 * returned 0 in GuestIntrBytes field of the VMCB.
4432 * First, errata can only be triggered in case vCPU CR4.SMAP=1.
4433 * Second, if vCPU CR4.SMEP=1, errata could only be triggered
4434 * in case vCPU CPL==3 (Because otherwise guest would have triggered
4435 * a SMEP fault instead of #NPF).
4436 * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL.
4437 * As most guests enable SMAP if they have also enabled SMEP, use above
4438 * logic in order to attempt minimize false-positive of detecting errata
4439 * while still preserving all cases semantic correctness.
4442 * To determine what instruction the guest was executing, the hypervisor
4443 * will have to decode the instruction at the instruction pointer.
4445 * In non SEV guest, hypervisor will be able to read the guest
4446 * memory to decode the instruction pointer when insn_len is zero
4447 * so we return true to indicate that decoding is possible.
4449 * But in the SEV guest, the guest memory is encrypted with the
4450 * guest specific key and hypervisor will not be able to decode the
4451 * instruction pointer so we will not able to workaround it. Lets
4452 * print the error and request to kill the guest.
4454 if (likely(!insn || insn_len))
4458 * If RIP is invalid, go ahead with emulation which will cause an
4459 * internal error exit.
4461 if (!kvm_vcpu_gfn_to_memslot(vcpu, kvm_rip_read(vcpu) >> PAGE_SHIFT))
4464 cr4 = kvm_read_cr4(vcpu);
4465 smep = cr4 & X86_CR4_SMEP;
4466 smap = cr4 & X86_CR4_SMAP;
4467 is_user = svm_get_cpl(vcpu) == 3;
4468 if (smap && (!smep || is_user)) {
4469 if (!sev_guest(vcpu->kvm))
4472 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
4473 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4479 static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
4481 struct vcpu_svm *svm = to_svm(vcpu);
4484 * TODO: Last condition latch INIT signals on vCPU when
4485 * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
4486 * To properly emulate the INIT intercept,
4487 * svm_check_nested_events() should call nested_svm_vmexit()
4488 * if an INIT signal is pending.
4490 return !gif_set(svm) ||
4491 (vmcb_is_intercept(&svm->vmcb->control, INTERCEPT_INIT));
4494 static void svm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
4496 if (!sev_es_guest(vcpu->kvm))
4497 return kvm_vcpu_deliver_sipi_vector(vcpu, vector);
4499 sev_vcpu_deliver_sipi_vector(vcpu, vector);
4502 static void svm_vm_destroy(struct kvm *kvm)
4504 avic_vm_destroy(kvm);
4505 sev_vm_destroy(kvm);
4508 static int svm_vm_init(struct kvm *kvm)
4510 if (!pause_filter_count || !pause_filter_thresh)
4511 kvm->arch.pause_in_guest = true;
4514 int ret = avic_vm_init(kvm);
4522 static struct kvm_x86_ops svm_x86_ops __initdata = {
4523 .hardware_unsetup = svm_hardware_teardown,
4524 .hardware_enable = svm_hardware_enable,
4525 .hardware_disable = svm_hardware_disable,
4526 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4527 .has_emulated_msr = svm_has_emulated_msr,
4529 .vcpu_create = svm_create_vcpu,
4530 .vcpu_free = svm_free_vcpu,
4531 .vcpu_reset = svm_vcpu_reset,
4533 .vm_size = sizeof(struct kvm_svm),
4534 .vm_init = svm_vm_init,
4535 .vm_destroy = svm_vm_destroy,
4537 .prepare_guest_switch = svm_prepare_guest_switch,
4538 .vcpu_load = svm_vcpu_load,
4539 .vcpu_put = svm_vcpu_put,
4540 .vcpu_blocking = svm_vcpu_blocking,
4541 .vcpu_unblocking = svm_vcpu_unblocking,
4543 .update_exception_bitmap = svm_update_exception_bitmap,
4544 .get_msr_feature = svm_get_msr_feature,
4545 .get_msr = svm_get_msr,
4546 .set_msr = svm_set_msr,
4547 .get_segment_base = svm_get_segment_base,
4548 .get_segment = svm_get_segment,
4549 .set_segment = svm_set_segment,
4550 .get_cpl = svm_get_cpl,
4551 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4552 .set_cr0 = svm_set_cr0,
4553 .is_valid_cr4 = svm_is_valid_cr4,
4554 .set_cr4 = svm_set_cr4,
4555 .set_efer = svm_set_efer,
4556 .get_idt = svm_get_idt,
4557 .set_idt = svm_set_idt,
4558 .get_gdt = svm_get_gdt,
4559 .set_gdt = svm_set_gdt,
4560 .set_dr7 = svm_set_dr7,
4561 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4562 .cache_reg = svm_cache_reg,
4563 .get_rflags = svm_get_rflags,
4564 .set_rflags = svm_set_rflags,
4566 .tlb_flush_all = svm_flush_tlb,
4567 .tlb_flush_current = svm_flush_tlb,
4568 .tlb_flush_gva = svm_flush_tlb_gva,
4569 .tlb_flush_guest = svm_flush_tlb,
4571 .run = svm_vcpu_run,
4572 .handle_exit = handle_exit,
4573 .skip_emulated_instruction = skip_emulated_instruction,
4574 .update_emulated_instruction = NULL,
4575 .set_interrupt_shadow = svm_set_interrupt_shadow,
4576 .get_interrupt_shadow = svm_get_interrupt_shadow,
4577 .patch_hypercall = svm_patch_hypercall,
4578 .set_irq = svm_set_irq,
4579 .set_nmi = svm_inject_nmi,
4580 .queue_exception = svm_queue_exception,
4581 .cancel_injection = svm_cancel_injection,
4582 .interrupt_allowed = svm_interrupt_allowed,
4583 .nmi_allowed = svm_nmi_allowed,
4584 .get_nmi_mask = svm_get_nmi_mask,
4585 .set_nmi_mask = svm_set_nmi_mask,
4586 .enable_nmi_window = svm_enable_nmi_window,
4587 .enable_irq_window = svm_enable_irq_window,
4588 .update_cr8_intercept = svm_update_cr8_intercept,
4589 .set_virtual_apic_mode = svm_set_virtual_apic_mode,
4590 .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
4591 .check_apicv_inhibit_reasons = svm_check_apicv_inhibit_reasons,
4592 .load_eoi_exitmap = svm_load_eoi_exitmap,
4593 .hwapic_irr_update = svm_hwapic_irr_update,
4594 .hwapic_isr_update = svm_hwapic_isr_update,
4595 .sync_pir_to_irr = kvm_lapic_find_highest_irr,
4596 .apicv_post_state_restore = avic_post_state_restore,
4598 .set_tss_addr = svm_set_tss_addr,
4599 .set_identity_map_addr = svm_set_identity_map_addr,
4600 .get_mt_mask = svm_get_mt_mask,
4602 .get_exit_info = svm_get_exit_info,
4604 .vcpu_after_set_cpuid = svm_vcpu_after_set_cpuid,
4606 .has_wbinvd_exit = svm_has_wbinvd_exit,
4608 .get_l2_tsc_offset = svm_get_l2_tsc_offset,
4609 .get_l2_tsc_multiplier = svm_get_l2_tsc_multiplier,
4610 .write_tsc_offset = svm_write_tsc_offset,
4611 .write_tsc_multiplier = svm_write_tsc_multiplier,
4613 .load_mmu_pgd = svm_load_mmu_pgd,
4615 .check_intercept = svm_check_intercept,
4616 .handle_exit_irqoff = svm_handle_exit_irqoff,
4618 .request_immediate_exit = __kvm_request_immediate_exit,
4620 .sched_in = svm_sched_in,
4622 .pmu_ops = &amd_pmu_ops,
4623 .nested_ops = &svm_nested_ops,
4625 .deliver_posted_interrupt = svm_deliver_avic_intr,
4626 .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt,
4627 .update_pi_irte = svm_update_pi_irte,
4628 .setup_mce = svm_setup_mce,
4630 .smi_allowed = svm_smi_allowed,
4631 .enter_smm = svm_enter_smm,
4632 .leave_smm = svm_leave_smm,
4633 .enable_smi_window = svm_enable_smi_window,
4635 .mem_enc_op = svm_mem_enc_op,
4636 .mem_enc_reg_region = svm_register_enc_region,
4637 .mem_enc_unreg_region = svm_unregister_enc_region,
4639 .vm_copy_enc_context_from = svm_vm_copy_asid_from,
4641 .can_emulate_instruction = svm_can_emulate_instruction,
4643 .apic_init_signal_blocked = svm_apic_init_signal_blocked,
4645 .msr_filter_changed = svm_msr_filter_changed,
4646 .complete_emulated_msr = svm_complete_emulated_msr,
4648 .vcpu_deliver_sipi_vector = svm_vcpu_deliver_sipi_vector,
4651 static struct kvm_x86_init_ops svm_init_ops __initdata = {
4652 .cpu_has_kvm_support = has_svm,
4653 .disabled_by_bios = is_disabled,
4654 .hardware_setup = svm_hardware_setup,
4655 .check_processor_compatibility = svm_check_processor_compat,
4657 .runtime_ops = &svm_x86_ops,
4660 static int __init svm_init(void)
4662 __unused_size_checks();
4664 return kvm_init(&svm_init_ops, sizeof(struct vcpu_svm),
4665 __alignof__(struct vcpu_svm), THIS_MODULE);
4668 static void __exit svm_exit(void)
4673 module_init(svm_init)
4674 module_exit(svm_exit)