arch/x86/kvm/svm/svm.c

   1 #define pr_fmt(fmt) "SVM: " fmt
   2
   3 #include <linux/kvm_host.h>
   4
   5 #include "irq.h"
   6 #include "mmu.h"
   7 #include "kvm_cache_regs.h"
   8 #include "x86.h"
   9 #include "cpuid.h"
  10 #include "pmu.h"
  11
  12 #include <linux/module.h>
  13 #include <linux/mod_devicetable.h>
  14 #include <linux/kernel.h>
  15 #include <linux/vmalloc.h>
  16 #include <linux/highmem.h>
  17 #include <linux/amd-iommu.h>
  18 #include <linux/sched.h>
  19 #include <linux/trace_events.h>
  20 #include <linux/slab.h>
  21 #include <linux/hashtable.h>
  22 #include <linux/frame.h>
  23 #include <linux/psp-sev.h>
  24 #include <linux/file.h>
  25 #include <linux/pagemap.h>
  26 #include <linux/swap.h>
  27 #include <linux/rwsem.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/perf_event.h>
  31 #include <asm/tlbflush.h>
  32 #include <asm/desc.h>
  33 #include <asm/debugreg.h>
  34 #include <asm/kvm_para.h>
  35 #include <asm/irq_remapping.h>
  36 #include <asm/mce.h>
  37 #include <asm/spec-ctrl.h>
  38 #include <asm/cpu_device_id.h>
  39
  40 #include <asm/virtext.h>
  41 #include "trace.h"
  42
  43 #include "svm.h"
  44
  45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  46
  47 MODULE_AUTHOR("Qumranet");
  48 MODULE_LICENSE("GPL");
  49
  50 #ifdef MODULE
  51 static const struct x86_cpu_id svm_cpu_id[] = {
  52         X86_MATCH_FEATURE(X86_FEATURE_SVM, NULL),
  53         {}
  54 };
  55 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  56 #endif
  57
  58 #define IOPM_ALLOC_ORDER 2
  59 #define MSRPM_ALLOC_ORDER 1
  60
  61 #define SEG_TYPE_LDT 2
  62 #define SEG_TYPE_BUSY_TSS16 3
  63
  64 #define SVM_FEATURE_LBRV           (1 <<  1)
  65 #define SVM_FEATURE_SVML           (1 <<  2)
  66 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  67 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  68 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  69 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  70 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  71
  72 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  73
  74 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  75 #define TSC_RATIO_MIN           0x0000000000000001ULL
  76 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  77
  78 static bool erratum_383_found __read_mostly;
  79
  80 u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
  81
  82 /*
  83  * Set osvw_len to higher value when updated Revision Guides
  84  * are published and we know what the new status bits are
  85  */
  86 static uint64_t osvw_len = 4, osvw_status;
  87
  88 static DEFINE_PER_CPU(u64, current_tsc_ratio);
  89 #define TSC_RATIO_DEFAULT       0x0100000000ULL
  90
  91 static const struct svm_direct_access_msrs {
  92         u32 index;   /* Index of the MSR */
  93         bool always; /* True if intercept is always on */
  94 } direct_access_msrs[] = {
  95         { .index = MSR_STAR,                            .always = true  },
  96         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
  97 #ifdef CONFIG_X86_64
  98         { .index = MSR_GS_BASE,                         .always = true  },
  99         { .index = MSR_FS_BASE,                         .always = true  },
 100         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 101         { .index = MSR_LSTAR,                           .always = true  },
 102         { .index = MSR_CSTAR,                           .always = true  },
 103         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 104 #endif
 105         { .index = MSR_IA32_SPEC_CTRL,                  .always = false },
 106         { .index = MSR_IA32_PRED_CMD,                   .always = false },
 107         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 108         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 109         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 110         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 111         { .index = MSR_INVALID,                         .always = false },
 112 };
 113
 114 /* enable NPT for AMD64 and X86 with PAE */
 115 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 116 bool npt_enabled = true;
 117 #else
 118 bool npt_enabled;
 119 #endif
 120
 121 /*
 122  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 123  * pause_filter_count: On processors that support Pause filtering(indicated
 124  *      by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
 125  *      count value. On VMRUN this value is loaded into an internal counter.
 126  *      Each time a pause instruction is executed, this counter is decremented
 127  *      until it reaches zero at which time a #VMEXIT is generated if pause
 128  *      intercept is enabled. Refer to  AMD APM Vol 2 Section 15.14.4 Pause
 129  *      Intercept Filtering for more details.
 130  *      This also indicate if ple logic enabled.
 131  *
 132  * pause_filter_thresh: In addition, some processor families support advanced
 133  *      pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
 134  *      the amount of time a guest is allowed to execute in a pause loop.
 135  *      In this mode, a 16-bit pause filter threshold field is added in the
 136  *      VMCB. The threshold value is a cycle count that is used to reset the
 137  *      pause counter. As with simple pause filtering, VMRUN loads the pause
 138  *      count value from VMCB into an internal counter. Then, on each pause
 139  *      instruction the hardware checks the elapsed number of cycles since
 140  *      the most recent pause instruction against the pause filter threshold.
 141  *      If the elapsed cycle count is greater than the pause filter threshold,
 142  *      then the internal pause count is reloaded from the VMCB and execution
 143  *      continues. If the elapsed cycle count is less than the pause filter
 144  *      threshold, then the internal pause count is decremented. If the count
 145  *      value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
 146  *      triggered. If advanced pause filtering is supported and pause filter
 147  *      threshold field is set to zero, the filter will operate in the simpler,
 148  *      count only mode.
 149  */
 150
 151 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
 152 module_param(pause_filter_thresh, ushort, 0444);
 153
 154 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
 155 module_param(pause_filter_count, ushort, 0444);
 156
 157 /* Default doubles per-vcpu window every exit. */
 158 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 159 module_param(pause_filter_count_grow, ushort, 0444);
 160
 161 /* Default resets per-vcpu window every exit to pause_filter_count. */
 162 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 163 module_param(pause_filter_count_shrink, ushort, 0444);
 164
 165 /* Default is to compute the maximum so we can never overflow. */
 166 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
 167 module_param(pause_filter_count_max, ushort, 0444);
 168
 169 /* allow nested paging (virtualized MMU) for all guests */
 170 static int npt = true;
 171 module_param(npt, int, S_IRUGO);
 172
 173 /* allow nested virtualization in KVM/SVM */
 174 static int nested = true;
 175 module_param(nested, int, S_IRUGO);
 176
 177 /* enable/disable Next RIP Save */
 178 static int nrips = true;
 179 module_param(nrips, int, 0444);
 180
 181 /* enable/disable Virtual VMLOAD VMSAVE */
 182 static int vls = true;
 183 module_param(vls, int, 0444);
 184
 185 /* enable/disable Virtual GIF */
 186 static int vgif = true;
 187 module_param(vgif, int, 0444);
 188
 189 /* enable/disable SEV support */
 190 static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
 191 module_param(sev, int, 0444);
 192
 193 static bool __read_mostly dump_invalid_vmcb = 0;
 194 module_param(dump_invalid_vmcb, bool, 0644);
 195
 196 static u8 rsm_ins_bytes[] = "\x0f\xaa";
 197
 198 static void svm_complete_interrupts(struct vcpu_svm *svm);
 199
 200 static unsigned long iopm_base;
 201
 202 struct kvm_ldttss_desc {
 203         u16 limit0;
 204         u16 base0;
 205         unsigned base1:8, type:5, dpl:2, p:1;
 206         unsigned limit1:4, zero0:3, g:1, base2:8;
 207         u32 base3;
 208         u32 zero1;
 209 } __attribute__((packed));
 210
 211 DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 212
 213 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 214
 215 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 216 #define MSRS_RANGE_SIZE 2048
 217 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 218
 219 u32 svm_msrpm_offset(u32 msr)
 220 {
 221         u32 offset;
 222         int i;
 223
 224         for (i = 0; i < NUM_MSR_MAPS; i++) {
 225                 if (msr < msrpm_ranges[i] ||
 226                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 227                         continue;
 228
 229                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 230                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 231
 232                 /* Now we have the u8 offset - but need the u32 offset */
 233                 return offset / 4;
 234         }
 235
 236         /* MSR not in any range */
 237         return MSR_INVALID;
 238 }
 239
 240 #define MAX_INST_SIZE 15
 241
 242 static inline void clgi(void)
 243 {
 244         asm volatile (__ex("clgi"));
 245 }
 246
 247 static inline void stgi(void)
 248 {
 249         asm volatile (__ex("stgi"));
 250 }
 251
 252 static inline void invlpga(unsigned long addr, u32 asid)
 253 {
 254         asm volatile (__ex("invlpga %1, %0") : : "c"(asid), "a"(addr));
 255 }
 256
 257 static int get_npt_level(struct kvm_vcpu *vcpu)
 258 {
 259 #ifdef CONFIG_X86_64
 260         return PT64_ROOT_4LEVEL;
 261 #else
 262         return PT32E_ROOT_LEVEL;
 263 #endif
 264 }
 265
 266 void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 267 {
 268         struct vcpu_svm *svm = to_svm(vcpu);
 269         vcpu->arch.efer = efer;
 270
 271         if (!npt_enabled) {
 272                 /* Shadow paging assumes NX to be available.  */
 273                 efer |= EFER_NX;
 274
 275                 if (!(efer & EFER_LMA))
 276                         efer &= ~EFER_LME;
 277         }
 278
 279         if (!(efer & EFER_SVME)) {
 280                 svm_leave_nested(svm);
 281                 svm_set_gif(svm, true);
 282         }
 283
 284         svm->vmcb->save.efer = efer | EFER_SVME;
 285         mark_dirty(svm->vmcb, VMCB_CR);
 286 }
 287
 288 static int is_external_interrupt(u32 info)
 289 {
 290         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 291         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 292 }
 293
 294 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
 295 {
 296         struct vcpu_svm *svm = to_svm(vcpu);
 297         u32 ret = 0;
 298
 299         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 300                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 301         return ret;
 302 }
 303
 304 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 305 {
 306         struct vcpu_svm *svm = to_svm(vcpu);
 307
 308         if (mask == 0)
 309                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 310         else
 311                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 312
 313 }
 314
 315 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
 316 {
 317         struct vcpu_svm *svm = to_svm(vcpu);
 318
 319         if (nrips && svm->vmcb->control.next_rip != 0) {
 320                 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
 321                 svm->next_rip = svm->vmcb->control.next_rip;
 322         }
 323
 324         if (!svm->next_rip) {
 325                 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
 326                         return 0;
 327         } else {
 328                 kvm_rip_write(vcpu, svm->next_rip);
 329         }
 330         svm_set_interrupt_shadow(vcpu, 0);
 331
 332         return 1;
 333 }
 334
 335 static void svm_queue_exception(struct kvm_vcpu *vcpu)
 336 {
 337         struct vcpu_svm *svm = to_svm(vcpu);
 338         unsigned nr = vcpu->arch.exception.nr;
 339         bool has_error_code = vcpu->arch.exception.has_error_code;
 340         u32 error_code = vcpu->arch.exception.error_code;
 341
 342         kvm_deliver_exception_payload(&svm->vcpu);
 343
 344         if (nr == BP_VECTOR && !nrips) {
 345                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 346
 347                 /*
 348                  * For guest debugging where we have to reinject #BP if some
 349                  * INT3 is guest-owned:
 350                  * Emulate nRIP by moving RIP forward. Will fail if injection
 351                  * raises a fault that is not intercepted. Still better than
 352                  * failing in all cases.
 353                  */
 354                 (void)skip_emulated_instruction(&svm->vcpu);
 355                 rip = kvm_rip_read(&svm->vcpu);
 356                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 357                 svm->int3_injected = rip - old_rip;
 358         }
 359
 360         svm->vmcb->control.event_inj = nr
 361                 | SVM_EVTINJ_VALID
 362                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 363                 | SVM_EVTINJ_TYPE_EXEPT;
 364         svm->vmcb->control.event_inj_err = error_code;
 365 }
 366
 367 static void svm_init_erratum_383(void)
 368 {
 369         u32 low, high;
 370         int err;
 371         u64 val;
 372
 373         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 374                 return;
 375
 376         /* Use _safe variants to not break nested virtualization */
 377         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 378         if (err)
 379                 return;
 380
 381         val |= (1ULL << 47);
 382
 383         low  = lower_32_bits(val);
 384         high = upper_32_bits(val);
 385
 386         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 387
 388         erratum_383_found = true;
 389 }
 390
 391 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 392 {
 393         /*
 394          * Guests should see errata 400 and 415 as fixed (assuming that
 395          * HLT and IO instructions are intercepted).
 396          */
 397         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 398         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 399
 400         /*
 401          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 402          * all osvw.status bits inside that length, including bit 0 (which is
 403          * reserved for erratum 298), are valid. However, if host processor's
 404          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 405          * be conservative here and therefore we tell the guest that erratum 298
 406          * is present (because we really don't know).
 407          */
 408         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 409                 vcpu->arch.osvw.status |= 1;
 410 }
 411
 412 static int has_svm(void)
 413 {
 414         const char *msg;
 415
 416         if (!cpu_has_svm(&msg)) {
 417                 printk(KERN_INFO "has_svm: %s\n", msg);
 418                 return 0;
 419         }
 420
 421         return 1;
 422 }
 423
 424 static void svm_hardware_disable(void)
 425 {
 426         /* Make sure we clean up behind us */
 427         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 428                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 429
 430         cpu_svm_disable();
 431
 432         amd_pmu_disable_virt();
 433 }
 434
 435 static int svm_hardware_enable(void)
 436 {
 437
 438         struct svm_cpu_data *sd;
 439         uint64_t efer;
 440         struct desc_struct *gdt;
 441         int me = raw_smp_processor_id();
 442
 443         rdmsrl(MSR_EFER, efer);
 444         if (efer & EFER_SVME)
 445                 return -EBUSY;
 446
 447         if (!has_svm()) {
 448                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 449                 return -EINVAL;
 450         }
 451         sd = per_cpu(svm_data, me);
 452         if (!sd) {
 453                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 454                 return -EINVAL;
 455         }
 456
 457         sd->asid_generation = 1;
 458         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 459         sd->next_asid = sd->max_asid + 1;
 460         sd->min_asid = max_sev_asid + 1;
 461
 462         gdt = get_current_gdt_rw();
 463         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 464
 465         wrmsrl(MSR_EFER, efer | EFER_SVME);
 466
 467         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 468
 469         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 470                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 471                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
 472         }
 473
 474
 475         /*
 476          * Get OSVW bits.
 477          *
 478          * Note that it is possible to have a system with mixed processor
 479          * revisions and therefore different OSVW bits. If bits are not the same
 480          * on different processors then choose the worst case (i.e. if erratum
 481          * is present on one processor and not on another then assume that the
 482          * erratum is present everywhere).
 483          */
 484         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 485                 uint64_t len, status = 0;
 486                 int err;
 487
 488                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 489                 if (!err)
 490                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 491                                                       &err);
 492
 493                 if (err)
 494                         osvw_status = osvw_len = 0;
 495                 else {
 496                         if (len < osvw_len)
 497                                 osvw_len = len;
 498                         osvw_status |= status;
 499                         osvw_status &= (1ULL << osvw_len) - 1;
 500                 }
 501         } else
 502                 osvw_status = osvw_len = 0;
 503
 504         svm_init_erratum_383();
 505
 506         amd_pmu_enable_virt();
 507
 508         return 0;
 509 }
 510
 511 static void svm_cpu_uninit(int cpu)
 512 {
 513         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 514
 515         if (!sd)
 516                 return;
 517
 518         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 519         kfree(sd->sev_vmcbs);
 520         __free_page(sd->save_area);
 521         kfree(sd);
 522 }
 523
 524 static int svm_cpu_init(int cpu)
 525 {
 526         struct svm_cpu_data *sd;
 527
 528         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 529         if (!sd)
 530                 return -ENOMEM;
 531         sd->cpu = cpu;
 532         sd->save_area = alloc_page(GFP_KERNEL);
 533         if (!sd->save_area)
 534                 goto free_cpu_data;
 535
 536         if (svm_sev_enabled()) {
 537                 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
 538                                               sizeof(void *),
 539                                               GFP_KERNEL);
 540                 if (!sd->sev_vmcbs)
 541                         goto free_save_area;
 542         }
 543
 544         per_cpu(svm_data, cpu) = sd;
 545
 546         return 0;
 547
 548 free_save_area:
 549         __free_page(sd->save_area);
 550 free_cpu_data:
 551         kfree(sd);
 552         return -ENOMEM;
 553
 554 }
 555
 556 static bool valid_msr_intercept(u32 index)
 557 {
 558         int i;
 559
 560         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 561                 if (direct_access_msrs[i].index == index)
 562                         return true;
 563
 564         return false;
 565 }
 566
 567 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, unsigned msr)
 568 {
 569         u8 bit_write;
 570         unsigned long tmp;
 571         u32 offset;
 572         u32 *msrpm;
 573
 574         msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
 575                                       to_svm(vcpu)->msrpm;
 576
 577         offset    = svm_msrpm_offset(msr);
 578         bit_write = 2 * (msr & 0x0f) + 1;
 579         tmp       = msrpm[offset];
 580
 581         BUG_ON(offset == MSR_INVALID);
 582
 583         return !!test_bit(bit_write,  &tmp);
 584 }
 585
 586 static void set_msr_interception(u32 *msrpm, unsigned msr,
 587                                  int read, int write)
 588 {
 589         u8 bit_read, bit_write;
 590         unsigned long tmp;
 591         u32 offset;
 592
 593         /*
 594          * If this warning triggers extend the direct_access_msrs list at the
 595          * beginning of the file
 596          */
 597         WARN_ON(!valid_msr_intercept(msr));
 598
 599         offset    = svm_msrpm_offset(msr);
 600         bit_read  = 2 * (msr & 0x0f);
 601         bit_write = 2 * (msr & 0x0f) + 1;
 602         tmp       = msrpm[offset];
 603
 604         BUG_ON(offset == MSR_INVALID);
 605
 606         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 607         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 608
 609         msrpm[offset] = tmp;
 610 }
 611
 612 static void svm_vcpu_init_msrpm(u32 *msrpm)
 613 {
 614         int i;
 615
 616         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 617
 618         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 619                 if (!direct_access_msrs[i].always)
 620                         continue;
 621
 622                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
 623         }
 624 }
 625
 626 static void add_msr_offset(u32 offset)
 627 {
 628         int i;
 629
 630         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 631
 632                 /* Offset already in list? */
 633                 if (msrpm_offsets[i] == offset)
 634                         return;
 635
 636                 /* Slot used by another offset? */
 637                 if (msrpm_offsets[i] != MSR_INVALID)
 638                         continue;
 639
 640                 /* Add offset to list */
 641                 msrpm_offsets[i] = offset;
 642
 643                 return;
 644         }
 645
 646         /*
 647          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 648          * increase MSRPM_OFFSETS in this case.
 649          */
 650         BUG();
 651 }
 652
 653 static void init_msrpm_offsets(void)
 654 {
 655         int i;
 656
 657         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 658
 659         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 660                 u32 offset;
 661
 662                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 663                 BUG_ON(offset == MSR_INVALID);
 664
 665                 add_msr_offset(offset);
 666         }
 667 }
 668
 669 static void svm_enable_lbrv(struct vcpu_svm *svm)
 670 {
 671         u32 *msrpm = svm->msrpm;
 672
 673         svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
 674         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 675         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 676         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 677         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 678 }
 679
 680 static void svm_disable_lbrv(struct vcpu_svm *svm)
 681 {
 682         u32 *msrpm = svm->msrpm;
 683
 684         svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
 685         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 686         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 687         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 688         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 689 }
 690
 691 void disable_nmi_singlestep(struct vcpu_svm *svm)
 692 {
 693         svm->nmi_singlestep = false;
 694
 695         if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
 696                 /* Clear our flags if they were not set by the guest */
 697                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
 698                         svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
 699                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
 700                         svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
 701         }
 702 }
 703
 704 static void grow_ple_window(struct kvm_vcpu *vcpu)
 705 {
 706         struct vcpu_svm *svm = to_svm(vcpu);
 707         struct vmcb_control_area *control = &svm->vmcb->control;
 708         int old = control->pause_filter_count;
 709
 710         control->pause_filter_count = __grow_ple_window(old,
 711                                                         pause_filter_count,
 712                                                         pause_filter_count_grow,
 713                                                         pause_filter_count_max);
 714
 715         if (control->pause_filter_count != old) {
 716                 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 717                 trace_kvm_ple_window_update(vcpu->vcpu_id,
 718                                             control->pause_filter_count, old);
 719         }
 720 }
 721
 722 static void shrink_ple_window(struct kvm_vcpu *vcpu)
 723 {
 724         struct vcpu_svm *svm = to_svm(vcpu);
 725         struct vmcb_control_area *control = &svm->vmcb->control;
 726         int old = control->pause_filter_count;
 727
 728         control->pause_filter_count =
 729                                 __shrink_ple_window(old,
 730                                                     pause_filter_count,
 731                                                     pause_filter_count_shrink,
 732                                                     pause_filter_count);
 733         if (control->pause_filter_count != old) {
 734                 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 735                 trace_kvm_ple_window_update(vcpu->vcpu_id,
 736                                             control->pause_filter_count, old);
 737         }
 738 }
 739
 740 /*
 741  * The default MMIO mask is a single bit (excluding the present bit),
 742  * which could conflict with the memory encryption bit. Check for
 743  * memory encryption support and override the default MMIO mask if
 744  * memory encryption is enabled.
 745  */
 746 static __init void svm_adjust_mmio_mask(void)
 747 {
 748         unsigned int enc_bit, mask_bit;
 749         u64 msr, mask;
 750
 751         /* If there is no memory encryption support, use existing mask */
 752         if (cpuid_eax(0x80000000) < 0x8000001f)
 753                 return;
 754
 755         /* If memory encryption is not enabled, use existing mask */
 756         rdmsrl(MSR_K8_SYSCFG, msr);
 757         if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
 758                 return;
 759
 760         enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
 761         mask_bit = boot_cpu_data.x86_phys_bits;
 762
 763         /* Increment the mask bit if it is the same as the encryption bit */
 764         if (enc_bit == mask_bit)
 765                 mask_bit++;
 766
 767         /*
 768          * If the mask bit location is below 52, then some bits above the
 769          * physical addressing limit will always be reserved, so use the
 770          * rsvd_bits() function to generate the mask. This mask, along with
 771          * the present bit, will be used to generate a page fault with
 772          * PFER.RSV = 1.
 773          *
 774          * If the mask bit location is 52 (or above), then clear the mask.
 775          */
 776         mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
 777
 778         kvm_mmu_set_mmio_spte_mask(mask, PT_WRITABLE_MASK | PT_USER_MASK);
 779 }
 780
 781 static void svm_hardware_teardown(void)
 782 {
 783         int cpu;
 784
 785         if (svm_sev_enabled())
 786                 sev_hardware_teardown();
 787
 788         for_each_possible_cpu(cpu)
 789                 svm_cpu_uninit(cpu);
 790
 791         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 792         iopm_base = 0;
 793 }
 794
 795 static __init void svm_set_cpu_caps(void)
 796 {
 797         kvm_set_cpu_caps();
 798
 799         supported_xss = 0;
 800
 801         /* CPUID 0x80000001 and 0x8000000A (SVM features) */
 802         if (nested) {
 803                 kvm_cpu_cap_set(X86_FEATURE_SVM);
 804
 805                 if (nrips)
 806                         kvm_cpu_cap_set(X86_FEATURE_NRIPS);
 807
 808                 if (npt_enabled)
 809                         kvm_cpu_cap_set(X86_FEATURE_NPT);
 810         }
 811
 812         /* CPUID 0x80000008 */
 813         if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
 814             boot_cpu_has(X86_FEATURE_AMD_SSBD))
 815                 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
 816 }
 817
 818 static __init int svm_hardware_setup(void)
 819 {
 820         int cpu;
 821         struct page *iopm_pages;
 822         void *iopm_va;
 823         int r;
 824
 825         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 826
 827         if (!iopm_pages)
 828                 return -ENOMEM;
 829
 830         iopm_va = page_address(iopm_pages);
 831         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 832         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 833
 834         init_msrpm_offsets();
 835
 836         supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
 837
 838         if (boot_cpu_has(X86_FEATURE_NX))
 839                 kvm_enable_efer_bits(EFER_NX);
 840
 841         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 842                 kvm_enable_efer_bits(EFER_FFXSR);
 843
 844         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 845                 kvm_has_tsc_control = true;
 846                 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
 847                 kvm_tsc_scaling_ratio_frac_bits = 32;
 848         }
 849
 850         /* Check for pause filtering support */
 851         if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
 852                 pause_filter_count = 0;
 853                 pause_filter_thresh = 0;
 854         } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
 855                 pause_filter_thresh = 0;
 856         }
 857
 858         if (nested) {
 859                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 860                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
 861         }
 862
 863         if (sev) {
 864                 if (boot_cpu_has(X86_FEATURE_SEV) &&
 865                     IS_ENABLED(CONFIG_KVM_AMD_SEV)) {
 866                         r = sev_hardware_setup();
 867                         if (r)
 868                                 sev = false;
 869                 } else {
 870                         sev = false;
 871                 }
 872         }
 873
 874         svm_adjust_mmio_mask();
 875
 876         for_each_possible_cpu(cpu) {
 877                 r = svm_cpu_init(cpu);
 878                 if (r)
 879                         goto err;
 880         }
 881
 882         if (!boot_cpu_has(X86_FEATURE_NPT))
 883                 npt_enabled = false;
 884
 885         if (npt_enabled && !npt)
 886                 npt_enabled = false;
 887
 888         kvm_configure_mmu(npt_enabled, PG_LEVEL_1G);
 889         pr_info("kvm: Nested Paging %sabled\n", npt_enabled ? "en" : "dis");
 890
 891         if (nrips) {
 892                 if (!boot_cpu_has(X86_FEATURE_NRIPS))
 893                         nrips = false;
 894         }
 895
 896         if (avic) {
 897                 if (!npt_enabled ||
 898                     !boot_cpu_has(X86_FEATURE_AVIC) ||
 899                     !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
 900                         avic = false;
 901                 } else {
 902                         pr_info("AVIC enabled\n");
 903
 904                         amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
 905                 }
 906         }
 907
 908         if (vls) {
 909                 if (!npt_enabled ||
 910                     !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
 911                     !IS_ENABLED(CONFIG_X86_64)) {
 912                         vls = false;
 913                 } else {
 914                         pr_info("Virtual VMLOAD VMSAVE supported\n");
 915                 }
 916         }
 917
 918         if (vgif) {
 919                 if (!boot_cpu_has(X86_FEATURE_VGIF))
 920                         vgif = false;
 921                 else
 922                         pr_info("Virtual GIF supported\n");
 923         }
 924
 925         svm_set_cpu_caps();
 926
 927         return 0;
 928
 929 err:
 930         svm_hardware_teardown();
 931         return r;
 932 }
 933
 934 static void init_seg(struct vmcb_seg *seg)
 935 {
 936         seg->selector = 0;
 937         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 938                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 939         seg->limit = 0xffff;
 940         seg->base = 0;
 941 }
 942
 943 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 944 {
 945         seg->selector = 0;
 946         seg->attrib = SVM_SELECTOR_P_MASK | type;
 947         seg->limit = 0xffff;
 948         seg->base = 0;
 949 }
 950
 951 static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
 952 {
 953         struct vcpu_svm *svm = to_svm(vcpu);
 954         u64 g_tsc_offset = 0;
 955
 956         if (is_guest_mode(vcpu)) {
 957                 /* Write L1's TSC offset.  */
 958                 g_tsc_offset = svm->vmcb->control.tsc_offset -
 959                                svm->nested.hsave->control.tsc_offset;
 960                 svm->nested.hsave->control.tsc_offset = offset;
 961         }
 962
 963         trace_kvm_write_tsc_offset(vcpu->vcpu_id,
 964                                    svm->vmcb->control.tsc_offset - g_tsc_offset,
 965                                    offset);
 966
 967         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
 968
 969         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 970         return svm->vmcb->control.tsc_offset;
 971 }
 972
 973 static void init_vmcb(struct vcpu_svm *svm)
 974 {
 975         struct vmcb_control_area *control = &svm->vmcb->control;
 976         struct vmcb_save_area *save = &svm->vmcb->save;
 977
 978         svm->vcpu.arch.hflags = 0;
 979
 980         set_cr_intercept(svm, INTERCEPT_CR0_READ);
 981         set_cr_intercept(svm, INTERCEPT_CR3_READ);
 982         set_cr_intercept(svm, INTERCEPT_CR4_READ);
 983         set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
 984         set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
 985         set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
 986         if (!kvm_vcpu_apicv_active(&svm->vcpu))
 987                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
 988
 989         set_dr_intercepts(svm);
 990
 991         set_exception_intercept(svm, PF_VECTOR);
 992         set_exception_intercept(svm, UD_VECTOR);
 993         set_exception_intercept(svm, MC_VECTOR);
 994         set_exception_intercept(svm, AC_VECTOR);
 995         set_exception_intercept(svm, DB_VECTOR);
 996         /*
 997          * Guest access to VMware backdoor ports could legitimately
 998          * trigger #GP because of TSS I/O permission bitmap.
 999          * We intercept those #GP and allow access to them anyway
1000          * as VMware does.
1001          */
1002         if (enable_vmware_backdoor)
1003                 set_exception_intercept(svm, GP_VECTOR);
1004
1005         set_intercept(svm, INTERCEPT_INTR);
1006         set_intercept(svm, INTERCEPT_NMI);
1007         set_intercept(svm, INTERCEPT_SMI);
1008         set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1009         set_intercept(svm, INTERCEPT_RDPMC);
1010         set_intercept(svm, INTERCEPT_CPUID);
1011         set_intercept(svm, INTERCEPT_INVD);
1012         set_intercept(svm, INTERCEPT_INVLPG);
1013         set_intercept(svm, INTERCEPT_INVLPGA);
1014         set_intercept(svm, INTERCEPT_IOIO_PROT);
1015         set_intercept(svm, INTERCEPT_MSR_PROT);
1016         set_intercept(svm, INTERCEPT_TASK_SWITCH);
1017         set_intercept(svm, INTERCEPT_SHUTDOWN);
1018         set_intercept(svm, INTERCEPT_VMRUN);
1019         set_intercept(svm, INTERCEPT_VMMCALL);
1020         set_intercept(svm, INTERCEPT_VMLOAD);
1021         set_intercept(svm, INTERCEPT_VMSAVE);
1022         set_intercept(svm, INTERCEPT_STGI);
1023         set_intercept(svm, INTERCEPT_CLGI);
1024         set_intercept(svm, INTERCEPT_SKINIT);
1025         set_intercept(svm, INTERCEPT_WBINVD);
1026         set_intercept(svm, INTERCEPT_XSETBV);
1027         set_intercept(svm, INTERCEPT_RDPRU);
1028         set_intercept(svm, INTERCEPT_RSM);
1029
1030         if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1031                 set_intercept(svm, INTERCEPT_MONITOR);
1032                 set_intercept(svm, INTERCEPT_MWAIT);
1033         }
1034
1035         if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1036                 set_intercept(svm, INTERCEPT_HLT);
1037
1038         control->iopm_base_pa = __sme_set(iopm_base);
1039         control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1040         control->int_ctl = V_INTR_MASKING_MASK;
1041
1042         init_seg(&save->es);
1043         init_seg(&save->ss);
1044         init_seg(&save->ds);
1045         init_seg(&save->fs);
1046         init_seg(&save->gs);
1047
1048         save->cs.selector = 0xf000;
1049         save->cs.base = 0xffff0000;
1050         /* Executable/Readable Code Segment */
1051         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1052                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1053         save->cs.limit = 0xffff;
1054
1055         save->gdtr.limit = 0xffff;
1056         save->idtr.limit = 0xffff;
1057
1058         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1059         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1060
1061         svm_set_efer(&svm->vcpu, 0);
1062         save->dr6 = 0xffff0ff0;
1063         kvm_set_rflags(&svm->vcpu, 2);
1064         save->rip = 0x0000fff0;
1065         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1066
1067         /*
1068          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1069          * It also updates the guest-visible cr0 value.
1070          */
1071         svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1072         kvm_mmu_reset_context(&svm->vcpu);
1073
1074         save->cr4 = X86_CR4_PAE;
1075         /* rdx = ?? */
1076
1077         if (npt_enabled) {
1078                 /* Setup VMCB for Nested Paging */
1079                 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1080                 clr_intercept(svm, INTERCEPT_INVLPG);
1081                 clr_exception_intercept(svm, PF_VECTOR);
1082                 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1083                 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1084                 save->g_pat = svm->vcpu.arch.pat;
1085                 save->cr3 = 0;
1086                 save->cr4 = 0;
1087         }
1088         svm->asid_generation = 0;
1089
1090         svm->nested.vmcb = 0;
1091         svm->vcpu.arch.hflags = 0;
1092
1093         if (pause_filter_count) {
1094                 control->pause_filter_count = pause_filter_count;
1095                 if (pause_filter_thresh)
1096                         control->pause_filter_thresh = pause_filter_thresh;
1097                 set_intercept(svm, INTERCEPT_PAUSE);
1098         } else {
1099                 clr_intercept(svm, INTERCEPT_PAUSE);
1100         }
1101
1102         if (kvm_vcpu_apicv_active(&svm->vcpu))
1103                 avic_init_vmcb(svm);
1104
1105         /*
1106          * If hardware supports Virtual VMLOAD VMSAVE then enable it
1107          * in VMCB and clear intercepts to avoid #VMEXIT.
1108          */
1109         if (vls) {
1110                 clr_intercept(svm, INTERCEPT_VMLOAD);
1111                 clr_intercept(svm, INTERCEPT_VMSAVE);
1112                 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1113         }
1114
1115         if (vgif) {
1116                 clr_intercept(svm, INTERCEPT_STGI);
1117                 clr_intercept(svm, INTERCEPT_CLGI);
1118                 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1119         }
1120
1121         if (sev_guest(svm->vcpu.kvm)) {
1122                 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1123                 clr_exception_intercept(svm, UD_VECTOR);
1124         }
1125
1126         mark_all_dirty(svm->vmcb);
1127
1128         enable_gif(svm);
1129
1130 }
1131
1132 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1133 {
1134         struct vcpu_svm *svm = to_svm(vcpu);
1135         u32 dummy;
1136         u32 eax = 1;
1137
1138         svm->spec_ctrl = 0;
1139         svm->virt_spec_ctrl = 0;
1140
1141         if (!init_event) {
1142                 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1143                                            MSR_IA32_APICBASE_ENABLE;
1144                 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1145                         svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1146         }
1147         init_vmcb(svm);
1148
1149         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, false);
1150         kvm_rdx_write(vcpu, eax);
1151
1152         if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1153                 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1154 }
1155
1156 static int svm_create_vcpu(struct kvm_vcpu *vcpu)
1157 {
1158         struct vcpu_svm *svm;
1159         struct page *page;
1160         struct page *msrpm_pages;
1161         struct page *hsave_page;
1162         struct page *nested_msrpm_pages;
1163         int err;
1164
1165         BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0);
1166         svm = to_svm(vcpu);
1167
1168         err = -ENOMEM;
1169         page = alloc_page(GFP_KERNEL_ACCOUNT);
1170         if (!page)
1171                 goto out;
1172
1173         msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
1174         if (!msrpm_pages)
1175                 goto free_page1;
1176
1177         nested_msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
1178         if (!nested_msrpm_pages)
1179                 goto free_page2;
1180
1181         hsave_page = alloc_page(GFP_KERNEL_ACCOUNT);
1182         if (!hsave_page)
1183                 goto free_page3;
1184
1185         err = avic_init_vcpu(svm);
1186         if (err)
1187                 goto free_page4;
1188
1189         /* We initialize this flag to true to make sure that the is_running
1190          * bit would be set the first time the vcpu is loaded.
1191          */
1192         if (irqchip_in_kernel(vcpu->kvm) && kvm_apicv_activated(vcpu->kvm))
1193                 svm->avic_is_running = true;
1194
1195         svm->nested.hsave = page_address(hsave_page);
1196         clear_page(svm->nested.hsave);
1197
1198         svm->msrpm = page_address(msrpm_pages);
1199         svm_vcpu_init_msrpm(svm->msrpm);
1200
1201         svm->nested.msrpm = page_address(nested_msrpm_pages);
1202         svm_vcpu_init_msrpm(svm->nested.msrpm);
1203
1204         svm->vmcb = page_address(page);
1205         clear_page(svm->vmcb);
1206         svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT);
1207         svm->asid_generation = 0;
1208         init_vmcb(svm);
1209
1210         svm_init_osvw(vcpu);
1211         vcpu->arch.microcode_version = 0x01000065;
1212
1213         return 0;
1214
1215 free_page4:
1216         __free_page(hsave_page);
1217 free_page3:
1218         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1219 free_page2:
1220         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1221 free_page1:
1222         __free_page(page);
1223 out:
1224         return err;
1225 }
1226
1227 static void svm_clear_current_vmcb(struct vmcb *vmcb)
1228 {
1229         int i;
1230
1231         for_each_online_cpu(i)
1232                 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
1233 }
1234
1235 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1236 {
1237         struct vcpu_svm *svm = to_svm(vcpu);
1238
1239         /*
1240          * The vmcb page can be recycled, causing a false negative in
1241          * svm_vcpu_load(). So, ensure that no logical CPU has this
1242          * vmcb page recorded as its current vmcb.
1243          */
1244         svm_clear_current_vmcb(svm->vmcb);
1245
1246         __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
1247         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1248         __free_page(virt_to_page(svm->nested.hsave));
1249         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1250 }
1251
1252 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1253 {
1254         struct vcpu_svm *svm = to_svm(vcpu);
1255         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
1256         int i;
1257
1258         if (unlikely(cpu != vcpu->cpu)) {
1259                 svm->asid_generation = 0;
1260                 mark_all_dirty(svm->vmcb);
1261         }
1262
1263 #ifdef CONFIG_X86_64
1264         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1265 #endif
1266         savesegment(fs, svm->host.fs);
1267         savesegment(gs, svm->host.gs);
1268         svm->host.ldt = kvm_read_ldt();
1269
1270         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1271                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1272
1273         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1274                 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1275                 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1276                         __this_cpu_write(current_tsc_ratio, tsc_ratio);
1277                         wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1278                 }
1279         }
1280         /* This assumes that the kernel never uses MSR_TSC_AUX */
1281         if (static_cpu_has(X86_FEATURE_RDTSCP))
1282                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
1283
1284         if (sd->current_vmcb != svm->vmcb) {
1285                 sd->current_vmcb = svm->vmcb;
1286                 indirect_branch_prediction_barrier();
1287         }
1288         avic_vcpu_load(vcpu, cpu);
1289 }
1290
1291 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1292 {
1293         struct vcpu_svm *svm = to_svm(vcpu);
1294         int i;
1295
1296         avic_vcpu_put(vcpu);
1297
1298         ++vcpu->stat.host_state_reload;
1299         kvm_load_ldt(svm->host.ldt);
1300 #ifdef CONFIG_X86_64
1301         loadsegment(fs, svm->host.fs);
1302         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
1303         load_gs_index(svm->host.gs);
1304 #else
1305 #ifdef CONFIG_X86_32_LAZY_GS
1306         loadsegment(gs, svm->host.gs);
1307 #endif
1308 #endif
1309         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1310                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1311 }
1312
1313 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1314 {
1315         struct vcpu_svm *svm = to_svm(vcpu);
1316         unsigned long rflags = svm->vmcb->save.rflags;
1317
1318         if (svm->nmi_singlestep) {
1319                 /* Hide our flags if they were not set by the guest */
1320                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1321                         rflags &= ~X86_EFLAGS_TF;
1322                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1323                         rflags &= ~X86_EFLAGS_RF;
1324         }
1325         return rflags;
1326 }
1327
1328 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1329 {
1330         if (to_svm(vcpu)->nmi_singlestep)
1331                 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1332
1333        /*
1334         * Any change of EFLAGS.VM is accompanied by a reload of SS
1335         * (caused by either a task switch or an inter-privilege IRET),
1336         * so we do not need to update the CPL here.
1337         */
1338         to_svm(vcpu)->vmcb->save.rflags = rflags;
1339 }
1340
1341 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1342 {
1343         switch (reg) {
1344         case VCPU_EXREG_PDPTR:
1345                 BUG_ON(!npt_enabled);
1346                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1347                 break;
1348         default:
1349                 WARN_ON_ONCE(1);
1350         }
1351 }
1352
1353 static void svm_set_vintr(struct vcpu_svm *svm)
1354 {
1355         struct vmcb_control_area *control;
1356
1357         /* The following fields are ignored when AVIC is enabled */
1358         WARN_ON(kvm_vcpu_apicv_active(&svm->vcpu));
1359         set_intercept(svm, INTERCEPT_VINTR);
1360
1361         /*
1362          * This is just a dummy VINTR to actually cause a vmexit to happen.
1363          * Actual injection of virtual interrupts happens through EVENTINJ.
1364          */
1365         control = &svm->vmcb->control;
1366         control->int_vector = 0x0;
1367         control->int_ctl &= ~V_INTR_PRIO_MASK;
1368         control->int_ctl |= V_IRQ_MASK |
1369                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1370         mark_dirty(svm->vmcb, VMCB_INTR);
1371 }
1372
1373 static void svm_clear_vintr(struct vcpu_svm *svm)
1374 {
1375         const u32 mask = V_TPR_MASK | V_GIF_ENABLE_MASK | V_GIF_MASK | V_INTR_MASKING_MASK;
1376         clr_intercept(svm, INTERCEPT_VINTR);
1377
1378         /* Drop int_ctl fields related to VINTR injection.  */
1379         svm->vmcb->control.int_ctl &= mask;
1380         if (is_guest_mode(&svm->vcpu)) {
1381                 svm->nested.hsave->control.int_ctl &= mask;
1382
1383                 WARN_ON((svm->vmcb->control.int_ctl & V_TPR_MASK) !=
1384                         (svm->nested.ctl.int_ctl & V_TPR_MASK));
1385                 svm->vmcb->control.int_ctl |= svm->nested.ctl.int_ctl & ~mask;
1386         }
1387
1388         mark_dirty(svm->vmcb, VMCB_INTR);
1389 }
1390
1391 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1392 {
1393         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1394
1395         switch (seg) {
1396         case VCPU_SREG_CS: return &save->cs;
1397         case VCPU_SREG_DS: return &save->ds;
1398         case VCPU_SREG_ES: return &save->es;
1399         case VCPU_SREG_FS: return &save->fs;
1400         case VCPU_SREG_GS: return &save->gs;
1401         case VCPU_SREG_SS: return &save->ss;
1402         case VCPU_SREG_TR: return &save->tr;
1403         case VCPU_SREG_LDTR: return &save->ldtr;
1404         }
1405         BUG();
1406         return NULL;
1407 }
1408
1409 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1410 {
1411         struct vmcb_seg *s = svm_seg(vcpu, seg);
1412
1413         return s->base;
1414 }
1415
1416 static void svm_get_segment(struct kvm_vcpu *vcpu,
1417                             struct kvm_segment *var, int seg)
1418 {
1419         struct vmcb_seg *s = svm_seg(vcpu, seg);
1420
1421         var->base = s->base;
1422         var->limit = s->limit;
1423         var->selector = s->selector;
1424         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1425         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1426         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1427         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1428         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1429         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1430         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1431
1432         /*
1433          * AMD CPUs circa 2014 track the G bit for all segments except CS.
1434          * However, the SVM spec states that the G bit is not observed by the
1435          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1436          * So let's synthesize a legal G bit for all segments, this helps
1437          * running KVM nested. It also helps cross-vendor migration, because
1438          * Intel's vmentry has a check on the 'G' bit.
1439          */
1440         var->g = s->limit > 0xfffff;
1441
1442         /*
1443          * AMD's VMCB does not have an explicit unusable field, so emulate it
1444          * for cross vendor migration purposes by "not present"
1445          */
1446         var->unusable = !var->present;
1447
1448         switch (seg) {
1449         case VCPU_SREG_TR:
1450                 /*
1451                  * Work around a bug where the busy flag in the tr selector
1452                  * isn't exposed
1453                  */
1454                 var->type |= 0x2;
1455                 break;
1456         case VCPU_SREG_DS:
1457         case VCPU_SREG_ES:
1458         case VCPU_SREG_FS:
1459         case VCPU_SREG_GS:
1460                 /*
1461                  * The accessed bit must always be set in the segment
1462                  * descriptor cache, although it can be cleared in the
1463                  * descriptor, the cached bit always remains at 1. Since
1464                  * Intel has a check on this, set it here to support
1465                  * cross-vendor migration.
1466                  */
1467                 if (!var->unusable)
1468                         var->type |= 0x1;
1469                 break;
1470         case VCPU_SREG_SS:
1471                 /*
1472                  * On AMD CPUs sometimes the DB bit in the segment
1473                  * descriptor is left as 1, although the whole segment has
1474                  * been made unusable. Clear it here to pass an Intel VMX
1475                  * entry check when cross vendor migrating.
1476                  */
1477                 if (var->unusable)
1478                         var->db = 0;
1479                 /* This is symmetric with svm_set_segment() */
1480                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1481                 break;
1482         }
1483 }
1484
1485 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1486 {
1487         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1488
1489         return save->cpl;
1490 }
1491
1492 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1493 {
1494         struct vcpu_svm *svm = to_svm(vcpu);
1495
1496         dt->size = svm->vmcb->save.idtr.limit;
1497         dt->address = svm->vmcb->save.idtr.base;
1498 }
1499
1500 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1501 {
1502         struct vcpu_svm *svm = to_svm(vcpu);
1503
1504         svm->vmcb->save.idtr.limit = dt->size;
1505         svm->vmcb->save.idtr.base = dt->address ;
1506         mark_dirty(svm->vmcb, VMCB_DT);
1507 }
1508
1509 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1510 {
1511         struct vcpu_svm *svm = to_svm(vcpu);
1512
1513         dt->size = svm->vmcb->save.gdtr.limit;
1514         dt->address = svm->vmcb->save.gdtr.base;
1515 }
1516
1517 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1518 {
1519         struct vcpu_svm *svm = to_svm(vcpu);
1520
1521         svm->vmcb->save.gdtr.limit = dt->size;
1522         svm->vmcb->save.gdtr.base = dt->address ;
1523         mark_dirty(svm->vmcb, VMCB_DT);
1524 }
1525
1526 static void update_cr0_intercept(struct vcpu_svm *svm)
1527 {
1528         ulong gcr0 = svm->vcpu.arch.cr0;
1529         u64 *hcr0 = &svm->vmcb->save.cr0;
1530
1531         *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1532                 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1533
1534         mark_dirty(svm->vmcb, VMCB_CR);
1535
1536         if (gcr0 == *hcr0) {
1537                 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1538                 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1539         } else {
1540                 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1541                 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1542         }
1543 }
1544
1545 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1546 {
1547         struct vcpu_svm *svm = to_svm(vcpu);
1548
1549 #ifdef CONFIG_X86_64
1550         if (vcpu->arch.efer & EFER_LME) {
1551                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1552                         vcpu->arch.efer |= EFER_LMA;
1553                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1554                 }
1555
1556                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1557                         vcpu->arch.efer &= ~EFER_LMA;
1558                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1559                 }
1560         }
1561 #endif
1562         vcpu->arch.cr0 = cr0;
1563
1564         if (!npt_enabled)
1565                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1566
1567         /*
1568          * re-enable caching here because the QEMU bios
1569          * does not do it - this results in some delay at
1570          * reboot
1571          */
1572         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1573                 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1574         svm->vmcb->save.cr0 = cr0;
1575         mark_dirty(svm->vmcb, VMCB_CR);
1576         update_cr0_intercept(svm);
1577 }
1578
1579 int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1580 {
1581         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1582         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1583
1584         if (cr4 & X86_CR4_VMXE)
1585                 return 1;
1586
1587         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1588                 svm_flush_tlb(vcpu);
1589
1590         vcpu->arch.cr4 = cr4;
1591         if (!npt_enabled)
1592                 cr4 |= X86_CR4_PAE;
1593         cr4 |= host_cr4_mce;
1594         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1595         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1596         return 0;
1597 }
1598
1599 static void svm_set_segment(struct kvm_vcpu *vcpu,
1600                             struct kvm_segment *var, int seg)
1601 {
1602         struct vcpu_svm *svm = to_svm(vcpu);
1603         struct vmcb_seg *s = svm_seg(vcpu, seg);
1604
1605         s->base = var->base;
1606         s->limit = var->limit;
1607         s->selector = var->selector;
1608         s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1609         s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1610         s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1611         s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
1612         s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1613         s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1614         s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1615         s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1616
1617         /*
1618          * This is always accurate, except if SYSRET returned to a segment
1619          * with SS.DPL != 3.  Intel does not have this quirk, and always
1620          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1621          * would entail passing the CPL to userspace and back.
1622          */
1623         if (seg == VCPU_SREG_SS)
1624                 /* This is symmetric with svm_get_segment() */
1625                 svm->vmcb->save.cpl = (var->dpl & 3);
1626
1627         mark_dirty(svm->vmcb, VMCB_SEG);
1628 }
1629
1630 static void update_bp_intercept(struct kvm_vcpu *vcpu)
1631 {
1632         struct vcpu_svm *svm = to_svm(vcpu);
1633
1634         clr_exception_intercept(svm, BP_VECTOR);
1635
1636         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1637                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1638                         set_exception_intercept(svm, BP_VECTOR);
1639         } else
1640                 vcpu->guest_debug = 0;
1641 }
1642
1643 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1644 {
1645         if (sd->next_asid > sd->max_asid) {
1646                 ++sd->asid_generation;
1647                 sd->next_asid = sd->min_asid;
1648                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1649         }
1650
1651         svm->asid_generation = sd->asid_generation;
1652         svm->vmcb->control.asid = sd->next_asid++;
1653
1654         mark_dirty(svm->vmcb, VMCB_ASID);
1655 }
1656
1657 static void svm_set_dr6(struct vcpu_svm *svm, unsigned long value)
1658 {
1659         struct vmcb *vmcb = svm->vmcb;
1660
1661         if (unlikely(value != vmcb->save.dr6)) {
1662                 vmcb->save.dr6 = value;
1663                 mark_dirty(vmcb, VMCB_DR);
1664         }
1665 }
1666
1667 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1668 {
1669         struct vcpu_svm *svm = to_svm(vcpu);
1670
1671         get_debugreg(vcpu->arch.db[0], 0);
1672         get_debugreg(vcpu->arch.db[1], 1);
1673         get_debugreg(vcpu->arch.db[2], 2);
1674         get_debugreg(vcpu->arch.db[3], 3);
1675         /*
1676          * We cannot reset svm->vmcb->save.dr6 to DR6_FIXED_1|DR6_RTM here,
1677          * because db_interception might need it.  We can do it before vmentry.
1678          */
1679         vcpu->arch.dr6 = svm->vmcb->save.dr6;
1680         vcpu->arch.dr7 = svm->vmcb->save.dr7;
1681         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1682         set_dr_intercepts(svm);
1683 }
1684
1685 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1686 {
1687         struct vcpu_svm *svm = to_svm(vcpu);
1688
1689         svm->vmcb->save.dr7 = value;
1690         mark_dirty(svm->vmcb, VMCB_DR);
1691 }
1692
1693 static int pf_interception(struct vcpu_svm *svm)
1694 {
1695         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1696         u64 error_code = svm->vmcb->control.exit_info_1;
1697
1698         return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
1699                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1700                         svm->vmcb->control.insn_bytes : NULL,
1701                         svm->vmcb->control.insn_len);
1702 }
1703
1704 static int npf_interception(struct vcpu_svm *svm)
1705 {
1706         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1707         u64 error_code = svm->vmcb->control.exit_info_1;
1708
1709         trace_kvm_page_fault(fault_address, error_code);
1710         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1711                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1712                         svm->vmcb->control.insn_bytes : NULL,
1713                         svm->vmcb->control.insn_len);
1714 }
1715
1716 static int db_interception(struct vcpu_svm *svm)
1717 {
1718         struct kvm_run *kvm_run = svm->vcpu.run;
1719         struct kvm_vcpu *vcpu = &svm->vcpu;
1720
1721         if (!(svm->vcpu.guest_debug &
1722               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1723                 !svm->nmi_singlestep) {
1724                 u32 payload = (svm->vmcb->save.dr6 ^ DR6_RTM) & ~DR6_FIXED_1;
1725                 kvm_queue_exception_p(&svm->vcpu, DB_VECTOR, payload);
1726                 return 1;
1727         }
1728
1729         if (svm->nmi_singlestep) {
1730                 disable_nmi_singlestep(svm);
1731                 /* Make sure we check for pending NMIs upon entry */
1732                 kvm_make_request(KVM_REQ_EVENT, vcpu);
1733         }
1734
1735         if (svm->vcpu.guest_debug &
1736             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1737                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1738                 kvm_run->debug.arch.dr6 = svm->vmcb->save.dr6;
1739                 kvm_run->debug.arch.dr7 = svm->vmcb->save.dr7;
1740                 kvm_run->debug.arch.pc =
1741                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1742                 kvm_run->debug.arch.exception = DB_VECTOR;
1743                 return 0;
1744         }
1745
1746         return 1;
1747 }
1748
1749 static int bp_interception(struct vcpu_svm *svm)
1750 {
1751         struct kvm_run *kvm_run = svm->vcpu.run;
1752
1753         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1754         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1755         kvm_run->debug.arch.exception = BP_VECTOR;
1756         return 0;
1757 }
1758
1759 static int ud_interception(struct vcpu_svm *svm)
1760 {
1761         return handle_ud(&svm->vcpu);
1762 }
1763
1764 static int ac_interception(struct vcpu_svm *svm)
1765 {
1766         kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
1767         return 1;
1768 }
1769
1770 static int gp_interception(struct vcpu_svm *svm)
1771 {
1772         struct kvm_vcpu *vcpu = &svm->vcpu;
1773         u32 error_code = svm->vmcb->control.exit_info_1;
1774
1775         WARN_ON_ONCE(!enable_vmware_backdoor);
1776
1777         /*
1778          * VMware backdoor emulation on #GP interception only handles IN{S},
1779          * OUT{S}, and RDPMC, none of which generate a non-zero error code.
1780          */
1781         if (error_code) {
1782                 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
1783                 return 1;
1784         }
1785         return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
1786 }
1787
1788 static bool is_erratum_383(void)
1789 {
1790         int err, i;
1791         u64 value;
1792
1793         if (!erratum_383_found)
1794                 return false;
1795
1796         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1797         if (err)
1798                 return false;
1799
1800         /* Bit 62 may or may not be set for this mce */
1801         value &= ~(1ULL << 62);
1802
1803         if (value != 0xb600000000010015ULL)
1804                 return false;
1805
1806         /* Clear MCi_STATUS registers */
1807         for (i = 0; i < 6; ++i)
1808                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1809
1810         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1811         if (!err) {
1812                 u32 low, high;
1813
1814                 value &= ~(1ULL << 2);
1815                 low    = lower_32_bits(value);
1816                 high   = upper_32_bits(value);
1817
1818                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1819         }
1820
1821         /* Flush tlb to evict multi-match entries */
1822         __flush_tlb_all();
1823
1824         return true;
1825 }
1826
1827 /*
1828  * Trigger machine check on the host. We assume all the MSRs are already set up
1829  * by the CPU and that we still run on the same CPU as the MCE occurred on.
1830  * We pass a fake environment to the machine check handler because we want
1831  * the guest to be always treated like user space, no matter what context
1832  * it used internally.
1833  */
1834 static void kvm_machine_check(void)
1835 {
1836 #if defined(CONFIG_X86_MCE)
1837         struct pt_regs regs = {
1838                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
1839                 .flags = X86_EFLAGS_IF,
1840         };
1841
1842         do_machine_check(&regs);
1843 #endif
1844 }
1845
1846 static void svm_handle_mce(struct vcpu_svm *svm)
1847 {
1848         if (is_erratum_383()) {
1849                 /*
1850                  * Erratum 383 triggered. Guest state is corrupt so kill the
1851                  * guest.
1852                  */
1853                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1854
1855                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1856
1857                 return;
1858         }
1859
1860         /*
1861          * On an #MC intercept the MCE handler is not called automatically in
1862          * the host. So do it by hand here.
1863          */
1864         kvm_machine_check();
1865 }
1866
1867 static int mc_interception(struct vcpu_svm *svm)
1868 {
1869         return 1;
1870 }
1871
1872 static int shutdown_interception(struct vcpu_svm *svm)
1873 {
1874         struct kvm_run *kvm_run = svm->vcpu.run;
1875
1876         /*
1877          * VMCB is undefined after a SHUTDOWN intercept
1878          * so reinitialize it.
1879          */
1880         clear_page(svm->vmcb);
1881         init_vmcb(svm);
1882
1883         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1884         return 0;
1885 }
1886
1887 static int io_interception(struct vcpu_svm *svm)
1888 {
1889         struct kvm_vcpu *vcpu = &svm->vcpu;
1890         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1891         int size, in, string;
1892         unsigned port;
1893
1894         ++svm->vcpu.stat.io_exits;
1895         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1896         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1897         if (string)
1898                 return kvm_emulate_instruction(vcpu, 0);
1899
1900         port = io_info >> 16;
1901         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1902         svm->next_rip = svm->vmcb->control.exit_info_2;
1903
1904         return kvm_fast_pio(&svm->vcpu, size, port, in);
1905 }
1906
1907 static int nmi_interception(struct vcpu_svm *svm)
1908 {
1909         return 1;
1910 }
1911
1912 static int intr_interception(struct vcpu_svm *svm)
1913 {
1914         ++svm->vcpu.stat.irq_exits;
1915         return 1;
1916 }
1917
1918 static int nop_on_interception(struct vcpu_svm *svm)
1919 {
1920         return 1;
1921 }
1922
1923 static int halt_interception(struct vcpu_svm *svm)
1924 {
1925         return kvm_emulate_halt(&svm->vcpu);
1926 }
1927
1928 static int vmmcall_interception(struct vcpu_svm *svm)
1929 {
1930         return kvm_emulate_hypercall(&svm->vcpu);
1931 }
1932
1933 static int vmload_interception(struct vcpu_svm *svm)
1934 {
1935         struct vmcb *nested_vmcb;
1936         struct kvm_host_map map;
1937         int ret;
1938
1939         if (nested_svm_check_permissions(svm))
1940                 return 1;
1941
1942         ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
1943         if (ret) {
1944                 if (ret == -EINVAL)
1945                         kvm_inject_gp(&svm->vcpu, 0);
1946                 return 1;
1947         }
1948
1949         nested_vmcb = map.hva;
1950
1951         ret = kvm_skip_emulated_instruction(&svm->vcpu);
1952
1953         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
1954         kvm_vcpu_unmap(&svm->vcpu, &map, true);
1955
1956         return ret;
1957 }
1958
1959 static int vmsave_interception(struct vcpu_svm *svm)
1960 {
1961         struct vmcb *nested_vmcb;
1962         struct kvm_host_map map;
1963         int ret;
1964
1965         if (nested_svm_check_permissions(svm))
1966                 return 1;
1967
1968         ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
1969         if (ret) {
1970                 if (ret == -EINVAL)
1971                         kvm_inject_gp(&svm->vcpu, 0);
1972                 return 1;
1973         }
1974
1975         nested_vmcb = map.hva;
1976
1977         ret = kvm_skip_emulated_instruction(&svm->vcpu);
1978
1979         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
1980         kvm_vcpu_unmap(&svm->vcpu, &map, true);
1981
1982         return ret;
1983 }
1984
1985 static int vmrun_interception(struct vcpu_svm *svm)
1986 {
1987         if (nested_svm_check_permissions(svm))
1988                 return 1;
1989
1990         return nested_svm_vmrun(svm);
1991 }
1992
1993 void svm_set_gif(struct vcpu_svm *svm, bool value)
1994 {
1995         if (value) {
1996                 /*
1997                  * If VGIF is enabled, the STGI intercept is only added to
1998                  * detect the opening of the SMI/NMI window; remove it now.
1999                  * Likewise, clear the VINTR intercept, we will set it
2000                  * again while processing KVM_REQ_EVENT if needed.
2001                  */
2002                 if (vgif_enabled(svm))
2003                         clr_intercept(svm, INTERCEPT_STGI);
2004                 if (is_intercept(svm, INTERCEPT_VINTR))
2005                         svm_clear_vintr(svm);
2006
2007                 enable_gif(svm);
2008                 if (svm->vcpu.arch.smi_pending ||
2009                     svm->vcpu.arch.nmi_pending ||
2010                     kvm_cpu_has_injectable_intr(&svm->vcpu))
2011                         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2012         } else {
2013                 disable_gif(svm);
2014
2015                 /*
2016                  * After a CLGI no interrupts should come.  But if vGIF is
2017                  * in use, we still rely on the VINTR intercept (rather than
2018                  * STGI) to detect an open interrupt window.
2019                 */
2020                 if (!vgif_enabled(svm))
2021                         svm_clear_vintr(svm);
2022         }
2023 }
2024
2025 static int stgi_interception(struct vcpu_svm *svm)
2026 {
2027         int ret;
2028
2029         if (nested_svm_check_permissions(svm))
2030                 return 1;
2031
2032         ret = kvm_skip_emulated_instruction(&svm->vcpu);
2033         svm_set_gif(svm, true);
2034         return ret;
2035 }
2036
2037 static int clgi_interception(struct vcpu_svm *svm)
2038 {
2039         int ret;
2040
2041         if (nested_svm_check_permissions(svm))
2042                 return 1;
2043
2044         ret = kvm_skip_emulated_instruction(&svm->vcpu);
2045         svm_set_gif(svm, false);
2046         return ret;
2047 }
2048
2049 static int invlpga_interception(struct vcpu_svm *svm)
2050 {
2051         struct kvm_vcpu *vcpu = &svm->vcpu;
2052
2053         trace_kvm_invlpga(svm->vmcb->save.rip, kvm_rcx_read(&svm->vcpu),
2054                           kvm_rax_read(&svm->vcpu));
2055
2056         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2057         kvm_mmu_invlpg(vcpu, kvm_rax_read(&svm->vcpu));
2058
2059         return kvm_skip_emulated_instruction(&svm->vcpu);
2060 }
2061
2062 static int skinit_interception(struct vcpu_svm *svm)
2063 {
2064         trace_kvm_skinit(svm->vmcb->save.rip, kvm_rax_read(&svm->vcpu));
2065
2066         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2067         return 1;
2068 }
2069
2070 static int wbinvd_interception(struct vcpu_svm *svm)
2071 {
2072         return kvm_emulate_wbinvd(&svm->vcpu);
2073 }
2074
2075 static int xsetbv_interception(struct vcpu_svm *svm)
2076 {
2077         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2078         u32 index = kvm_rcx_read(&svm->vcpu);
2079
2080         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2081                 return kvm_skip_emulated_instruction(&svm->vcpu);
2082         }
2083
2084         return 1;
2085 }
2086
2087 static int rdpru_interception(struct vcpu_svm *svm)
2088 {
2089         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2090         return 1;
2091 }
2092
2093 static int task_switch_interception(struct vcpu_svm *svm)
2094 {
2095         u16 tss_selector;
2096         int reason;
2097         int int_type = svm->vmcb->control.exit_int_info &
2098                 SVM_EXITINTINFO_TYPE_MASK;
2099         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2100         uint32_t type =
2101                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2102         uint32_t idt_v =
2103                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2104         bool has_error_code = false;
2105         u32 error_code = 0;
2106
2107         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2108
2109         if (svm->vmcb->control.exit_info_2 &
2110             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2111                 reason = TASK_SWITCH_IRET;
2112         else if (svm->vmcb->control.exit_info_2 &
2113                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2114                 reason = TASK_SWITCH_JMP;
2115         else if (idt_v)
2116                 reason = TASK_SWITCH_GATE;
2117         else
2118                 reason = TASK_SWITCH_CALL;
2119
2120         if (reason == TASK_SWITCH_GATE) {
2121                 switch (type) {
2122                 case SVM_EXITINTINFO_TYPE_NMI:
2123                         svm->vcpu.arch.nmi_injected = false;
2124                         break;
2125                 case SVM_EXITINTINFO_TYPE_EXEPT:
2126                         if (svm->vmcb->control.exit_info_2 &
2127                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2128                                 has_error_code = true;
2129                                 error_code =
2130                                         (u32)svm->vmcb->control.exit_info_2;
2131                         }
2132                         kvm_clear_exception_queue(&svm->vcpu);
2133                         break;
2134                 case SVM_EXITINTINFO_TYPE_INTR:
2135                         kvm_clear_interrupt_queue(&svm->vcpu);
2136                         break;
2137                 default:
2138                         break;
2139                 }
2140         }
2141
2142         if (reason != TASK_SWITCH_GATE ||
2143             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2144             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2145              (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
2146                 if (!skip_emulated_instruction(&svm->vcpu))
2147                         return 0;
2148         }
2149
2150         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2151                 int_vec = -1;
2152
2153         return kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2154                                has_error_code, error_code);
2155 }
2156
2157 static int cpuid_interception(struct vcpu_svm *svm)
2158 {
2159         return kvm_emulate_cpuid(&svm->vcpu);
2160 }
2161
2162 static int iret_interception(struct vcpu_svm *svm)
2163 {
2164         ++svm->vcpu.stat.nmi_window_exits;
2165         clr_intercept(svm, INTERCEPT_IRET);
2166         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2167         svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2168         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2169         return 1;
2170 }
2171
2172 static int invlpg_interception(struct vcpu_svm *svm)
2173 {
2174         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2175                 return kvm_emulate_instruction(&svm->vcpu, 0);
2176
2177         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2178         return kvm_skip_emulated_instruction(&svm->vcpu);
2179 }
2180
2181 static int emulate_on_interception(struct vcpu_svm *svm)
2182 {
2183         return kvm_emulate_instruction(&svm->vcpu, 0);
2184 }
2185
2186 static int rsm_interception(struct vcpu_svm *svm)
2187 {
2188         return kvm_emulate_instruction_from_buffer(&svm->vcpu, rsm_ins_bytes, 2);
2189 }
2190
2191 static int rdpmc_interception(struct vcpu_svm *svm)
2192 {
2193         int err;
2194
2195         if (!nrips)
2196                 return emulate_on_interception(svm);
2197
2198         err = kvm_rdpmc(&svm->vcpu);
2199         return kvm_complete_insn_gp(&svm->vcpu, err);
2200 }
2201
2202 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
2203                                             unsigned long val)
2204 {
2205         unsigned long cr0 = svm->vcpu.arch.cr0;
2206         bool ret = false;
2207         u64 intercept;
2208
2209         intercept = svm->nested.ctl.intercept;
2210
2211         if (!is_guest_mode(&svm->vcpu) ||
2212             (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
2213                 return false;
2214
2215         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2216         val &= ~SVM_CR0_SELECTIVE_MASK;
2217
2218         if (cr0 ^ val) {
2219                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2220                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2221         }
2222
2223         return ret;
2224 }
2225
2226 #define CR_VALID (1ULL << 63)
2227
2228 static int cr_interception(struct vcpu_svm *svm)
2229 {
2230         int reg, cr;
2231         unsigned long val;
2232         int err;
2233
2234         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2235                 return emulate_on_interception(svm);
2236
2237         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2238                 return emulate_on_interception(svm);
2239
2240         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2241         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2242                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2243         else
2244                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2245
2246         err = 0;
2247         if (cr >= 16) { /* mov to cr */
2248                 cr -= 16;
2249                 val = kvm_register_read(&svm->vcpu, reg);
2250                 switch (cr) {
2251                 case 0:
2252                         if (!check_selective_cr0_intercepted(svm, val))
2253                                 err = kvm_set_cr0(&svm->vcpu, val);
2254                         else
2255                                 return 1;
2256
2257                         break;
2258                 case 3:
2259                         err = kvm_set_cr3(&svm->vcpu, val);
2260                         break;
2261                 case 4:
2262                         err = kvm_set_cr4(&svm->vcpu, val);
2263                         break;
2264                 case 8:
2265                         err = kvm_set_cr8(&svm->vcpu, val);
2266                         break;
2267                 default:
2268                         WARN(1, "unhandled write to CR%d", cr);
2269                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2270                         return 1;
2271                 }
2272         } else { /* mov from cr */
2273                 switch (cr) {
2274                 case 0:
2275                         val = kvm_read_cr0(&svm->vcpu);
2276                         break;
2277                 case 2:
2278                         val = svm->vcpu.arch.cr2;
2279                         break;
2280                 case 3:
2281                         val = kvm_read_cr3(&svm->vcpu);
2282                         break;
2283                 case 4:
2284                         val = kvm_read_cr4(&svm->vcpu);
2285                         break;
2286                 case 8:
2287                         val = kvm_get_cr8(&svm->vcpu);
2288                         break;
2289                 default:
2290                         WARN(1, "unhandled read from CR%d", cr);
2291                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2292                         return 1;
2293                 }
2294                 kvm_register_write(&svm->vcpu, reg, val);
2295         }
2296         return kvm_complete_insn_gp(&svm->vcpu, err);
2297 }
2298
2299 static int dr_interception(struct vcpu_svm *svm)
2300 {
2301         int reg, dr;
2302         unsigned long val;
2303
2304         if (svm->vcpu.guest_debug == 0) {
2305                 /*
2306                  * No more DR vmexits; force a reload of the debug registers
2307                  * and reenter on this instruction.  The next vmexit will
2308                  * retrieve the full state of the debug registers.
2309                  */
2310                 clr_dr_intercepts(svm);
2311                 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2312                 return 1;
2313         }
2314
2315         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2316                 return emulate_on_interception(svm);
2317
2318         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2319         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2320
2321         if (dr >= 16) { /* mov to DRn */
2322                 if (!kvm_require_dr(&svm->vcpu, dr - 16))
2323                         return 1;
2324                 val = kvm_register_read(&svm->vcpu, reg);
2325                 kvm_set_dr(&svm->vcpu, dr - 16, val);
2326         } else {
2327                 if (!kvm_require_dr(&svm->vcpu, dr))
2328                         return 1;
2329                 kvm_get_dr(&svm->vcpu, dr, &val);
2330                 kvm_register_write(&svm->vcpu, reg, val);
2331         }
2332
2333         return kvm_skip_emulated_instruction(&svm->vcpu);
2334 }
2335
2336 static int cr8_write_interception(struct vcpu_svm *svm)
2337 {
2338         struct kvm_run *kvm_run = svm->vcpu.run;
2339         int r;
2340
2341         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2342         /* instruction emulation calls kvm_set_cr8() */
2343         r = cr_interception(svm);
2344         if (lapic_in_kernel(&svm->vcpu))
2345                 return r;
2346         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2347                 return r;
2348         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2349         return 0;
2350 }
2351
2352 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
2353 {
2354         msr->data = 0;
2355
2356         switch (msr->index) {
2357         case MSR_F10H_DECFG:
2358                 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
2359                         msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
2360                 break;
2361         default:
2362                 return 1;
2363         }
2364
2365         return 0;
2366 }
2367
2368 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2369 {
2370         struct vcpu_svm *svm = to_svm(vcpu);
2371
2372         switch (msr_info->index) {
2373         case MSR_STAR:
2374                 msr_info->data = svm->vmcb->save.star;
2375                 break;
2376 #ifdef CONFIG_X86_64
2377         case MSR_LSTAR:
2378                 msr_info->data = svm->vmcb->save.lstar;
2379                 break;
2380         case MSR_CSTAR:
2381                 msr_info->data = svm->vmcb->save.cstar;
2382                 break;
2383         case MSR_KERNEL_GS_BASE:
2384                 msr_info->data = svm->vmcb->save.kernel_gs_base;
2385                 break;
2386         case MSR_SYSCALL_MASK:
2387                 msr_info->data = svm->vmcb->save.sfmask;
2388                 break;
2389 #endif
2390         case MSR_IA32_SYSENTER_CS:
2391                 msr_info->data = svm->vmcb->save.sysenter_cs;
2392                 break;
2393         case MSR_IA32_SYSENTER_EIP:
2394                 msr_info->data = svm->sysenter_eip;
2395                 break;
2396         case MSR_IA32_SYSENTER_ESP:
2397                 msr_info->data = svm->sysenter_esp;
2398                 break;
2399         case MSR_TSC_AUX:
2400                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2401                         return 1;
2402                 msr_info->data = svm->tsc_aux;
2403                 break;
2404         /*
2405          * Nobody will change the following 5 values in the VMCB so we can
2406          * safely return them on rdmsr. They will always be 0 until LBRV is
2407          * implemented.
2408          */
2409         case MSR_IA32_DEBUGCTLMSR:
2410                 msr_info->data = svm->vmcb->save.dbgctl;
2411                 break;
2412         case MSR_IA32_LASTBRANCHFROMIP:
2413                 msr_info->data = svm->vmcb->save.br_from;
2414                 break;
2415         case MSR_IA32_LASTBRANCHTOIP:
2416                 msr_info->data = svm->vmcb->save.br_to;
2417                 break;
2418         case MSR_IA32_LASTINTFROMIP:
2419                 msr_info->data = svm->vmcb->save.last_excp_from;
2420                 break;
2421         case MSR_IA32_LASTINTTOIP:
2422                 msr_info->data = svm->vmcb->save.last_excp_to;
2423                 break;
2424         case MSR_VM_HSAVE_PA:
2425                 msr_info->data = svm->nested.hsave_msr;
2426                 break;
2427         case MSR_VM_CR:
2428                 msr_info->data = svm->nested.vm_cr_msr;
2429                 break;
2430         case MSR_IA32_SPEC_CTRL:
2431                 if (!msr_info->host_initiated &&
2432                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
2433                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_STIBP) &&
2434                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
2435                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
2436                         return 1;
2437
2438                 msr_info->data = svm->spec_ctrl;
2439                 break;
2440         case MSR_AMD64_VIRT_SPEC_CTRL:
2441                 if (!msr_info->host_initiated &&
2442                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2443                         return 1;
2444
2445                 msr_info->data = svm->virt_spec_ctrl;
2446                 break;
2447         case MSR_F15H_IC_CFG: {
2448
2449                 int family, model;
2450
2451                 family = guest_cpuid_family(vcpu);
2452                 model  = guest_cpuid_model(vcpu);
2453
2454                 if (family < 0 || model < 0)
2455                         return kvm_get_msr_common(vcpu, msr_info);
2456
2457                 msr_info->data = 0;
2458
2459                 if (family == 0x15 &&
2460                     (model >= 0x2 && model < 0x20))
2461                         msr_info->data = 0x1E;
2462                 }
2463                 break;
2464         case MSR_F10H_DECFG:
2465                 msr_info->data = svm->msr_decfg;
2466                 break;
2467         default:
2468                 return kvm_get_msr_common(vcpu, msr_info);
2469         }
2470         return 0;
2471 }
2472
2473 static int rdmsr_interception(struct vcpu_svm *svm)
2474 {
2475         return kvm_emulate_rdmsr(&svm->vcpu);
2476 }
2477
2478 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2479 {
2480         struct vcpu_svm *svm = to_svm(vcpu);
2481         int svm_dis, chg_mask;
2482
2483         if (data & ~SVM_VM_CR_VALID_MASK)
2484                 return 1;
2485
2486         chg_mask = SVM_VM_CR_VALID_MASK;
2487
2488         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2489                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2490
2491         svm->nested.vm_cr_msr &= ~chg_mask;
2492         svm->nested.vm_cr_msr |= (data & chg_mask);
2493
2494         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2495
2496         /* check for svm_disable while efer.svme is set */
2497         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2498                 return 1;
2499
2500         return 0;
2501 }
2502
2503 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2504 {
2505         struct vcpu_svm *svm = to_svm(vcpu);
2506
2507         u32 ecx = msr->index;
2508         u64 data = msr->data;
2509         switch (ecx) {
2510         case MSR_IA32_CR_PAT:
2511                 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2512                         return 1;
2513                 vcpu->arch.pat = data;
2514                 svm->vmcb->save.g_pat = data;
2515                 mark_dirty(svm->vmcb, VMCB_NPT);
2516                 break;
2517         case MSR_IA32_SPEC_CTRL:
2518                 if (!msr->host_initiated &&
2519                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
2520                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_STIBP) &&
2521                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
2522                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
2523                         return 1;
2524
2525                 if (data & ~kvm_spec_ctrl_valid_bits(vcpu))
2526                         return 1;
2527
2528                 svm->spec_ctrl = data;
2529                 if (!data)
2530                         break;
2531
2532                 /*
2533                  * For non-nested:
2534                  * When it's written (to non-zero) for the first time, pass
2535                  * it through.
2536                  *
2537                  * For nested:
2538                  * The handling of the MSR bitmap for L2 guests is done in
2539                  * nested_svm_vmrun_msrpm.
2540                  * We update the L1 MSR bit as well since it will end up
2541                  * touching the MSR anyway now.
2542                  */
2543                 set_msr_interception(svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
2544                 break;
2545         case MSR_IA32_PRED_CMD:
2546                 if (!msr->host_initiated &&
2547                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB))
2548                         return 1;
2549
2550                 if (data & ~PRED_CMD_IBPB)
2551                         return 1;
2552                 if (!boot_cpu_has(X86_FEATURE_AMD_IBPB))
2553                         return 1;
2554                 if (!data)
2555                         break;
2556
2557                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2558                 set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
2559                 break;
2560         case MSR_AMD64_VIRT_SPEC_CTRL:
2561                 if (!msr->host_initiated &&
2562                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2563                         return 1;
2564
2565                 if (data & ~SPEC_CTRL_SSBD)
2566                         return 1;
2567
2568                 svm->virt_spec_ctrl = data;
2569                 break;
2570         case MSR_STAR:
2571                 svm->vmcb->save.star = data;
2572                 break;
2573 #ifdef CONFIG_X86_64
2574         case MSR_LSTAR:
2575                 svm->vmcb->save.lstar = data;
2576                 break;
2577         case MSR_CSTAR:
2578                 svm->vmcb->save.cstar = data;
2579                 break;
2580         case MSR_KERNEL_GS_BASE:
2581                 svm->vmcb->save.kernel_gs_base = data;
2582                 break;
2583         case MSR_SYSCALL_MASK:
2584                 svm->vmcb->save.sfmask = data;
2585                 break;
2586 #endif
2587         case MSR_IA32_SYSENTER_CS:
2588                 svm->vmcb->save.sysenter_cs = data;
2589                 break;
2590         case MSR_IA32_SYSENTER_EIP:
2591                 svm->sysenter_eip = data;
2592                 svm->vmcb->save.sysenter_eip = data;
2593                 break;
2594         case MSR_IA32_SYSENTER_ESP:
2595                 svm->sysenter_esp = data;
2596                 svm->vmcb->save.sysenter_esp = data;
2597                 break;
2598         case MSR_TSC_AUX:
2599                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2600                         return 1;
2601
2602                 /*
2603                  * This is rare, so we update the MSR here instead of using
2604                  * direct_access_msrs.  Doing that would require a rdmsr in
2605                  * svm_vcpu_put.
2606                  */
2607                 svm->tsc_aux = data;
2608                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2609                 break;
2610         case MSR_IA32_DEBUGCTLMSR:
2611                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2612                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2613                                     __func__, data);
2614                         break;
2615                 }
2616                 if (data & DEBUGCTL_RESERVED_BITS)
2617                         return 1;
2618
2619                 svm->vmcb->save.dbgctl = data;
2620                 mark_dirty(svm->vmcb, VMCB_LBR);
2621                 if (data & (1ULL<<0))
2622                         svm_enable_lbrv(svm);
2623                 else
2624                         svm_disable_lbrv(svm);
2625                 break;
2626         case MSR_VM_HSAVE_PA:
2627                 svm->nested.hsave_msr = data;
2628                 break;
2629         case MSR_VM_CR:
2630                 return svm_set_vm_cr(vcpu, data);
2631         case MSR_VM_IGNNE:
2632                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2633                 break;
2634         case MSR_F10H_DECFG: {
2635                 struct kvm_msr_entry msr_entry;
2636
2637                 msr_entry.index = msr->index;
2638                 if (svm_get_msr_feature(&msr_entry))
2639                         return 1;
2640
2641                 /* Check the supported bits */
2642                 if (data & ~msr_entry.data)
2643                         return 1;
2644
2645                 /* Don't allow the guest to change a bit, #GP */
2646                 if (!msr->host_initiated && (data ^ msr_entry.data))
2647                         return 1;
2648
2649                 svm->msr_decfg = data;
2650                 break;
2651         }
2652         case MSR_IA32_APICBASE:
2653                 if (kvm_vcpu_apicv_active(vcpu))
2654                         avic_update_vapic_bar(to_svm(vcpu), data);
2655                 /* Fall through */
2656         default:
2657                 return kvm_set_msr_common(vcpu, msr);
2658         }
2659         return 0;
2660 }
2661
2662 static int wrmsr_interception(struct vcpu_svm *svm)
2663 {
2664         return kvm_emulate_wrmsr(&svm->vcpu);
2665 }
2666
2667 static int msr_interception(struct vcpu_svm *svm)
2668 {
2669         if (svm->vmcb->control.exit_info_1)
2670                 return wrmsr_interception(svm);
2671         else
2672                 return rdmsr_interception(svm);
2673 }
2674
2675 static int interrupt_window_interception(struct vcpu_svm *svm)
2676 {
2677         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2678         svm_clear_vintr(svm);
2679
2680         /*
2681          * For AVIC, the only reason to end up here is ExtINTs.
2682          * In this case AVIC was temporarily disabled for
2683          * requesting the IRQ window and we have to re-enable it.
2684          */
2685         svm_toggle_avic_for_irq_window(&svm->vcpu, true);
2686
2687         ++svm->vcpu.stat.irq_window_exits;
2688         return 1;
2689 }
2690
2691 static int pause_interception(struct vcpu_svm *svm)
2692 {
2693         struct kvm_vcpu *vcpu = &svm->vcpu;
2694         bool in_kernel = (svm_get_cpl(vcpu) == 0);
2695
2696         if (pause_filter_thresh)
2697                 grow_ple_window(vcpu);
2698
2699         kvm_vcpu_on_spin(vcpu, in_kernel);
2700         return 1;
2701 }
2702
2703 static int nop_interception(struct vcpu_svm *svm)
2704 {
2705         return kvm_skip_emulated_instruction(&(svm->vcpu));
2706 }
2707
2708 static int monitor_interception(struct vcpu_svm *svm)
2709 {
2710         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
2711         return nop_interception(svm);
2712 }
2713
2714 static int mwait_interception(struct vcpu_svm *svm)
2715 {
2716         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
2717         return nop_interception(svm);
2718 }
2719
2720 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
2721         [SVM_EXIT_READ_CR0]                     = cr_interception,
2722         [SVM_EXIT_READ_CR3]                     = cr_interception,
2723         [SVM_EXIT_READ_CR4]                     = cr_interception,
2724         [SVM_EXIT_READ_CR8]                     = cr_interception,
2725         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
2726         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
2727         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
2728         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
2729         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2730         [SVM_EXIT_READ_DR0]                     = dr_interception,
2731         [SVM_EXIT_READ_DR1]                     = dr_interception,
2732         [SVM_EXIT_READ_DR2]                     = dr_interception,
2733         [SVM_EXIT_READ_DR3]                     = dr_interception,
2734         [SVM_EXIT_READ_DR4]                     = dr_interception,
2735         [SVM_EXIT_READ_DR5]                     = dr_interception,
2736         [SVM_EXIT_READ_DR6]                     = dr_interception,
2737         [SVM_EXIT_READ_DR7]                     = dr_interception,
2738         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
2739         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
2740         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
2741         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
2742         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
2743         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
2744         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
2745         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
2746         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2747         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2748         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2749         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2750         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2751         [SVM_EXIT_EXCP_BASE + AC_VECTOR]        = ac_interception,
2752         [SVM_EXIT_EXCP_BASE + GP_VECTOR]        = gp_interception,
2753         [SVM_EXIT_INTR]                         = intr_interception,
2754         [SVM_EXIT_NMI]                          = nmi_interception,
2755         [SVM_EXIT_SMI]                          = nop_on_interception,
2756         [SVM_EXIT_INIT]                         = nop_on_interception,
2757         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2758         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
2759         [SVM_EXIT_CPUID]                        = cpuid_interception,
2760         [SVM_EXIT_IRET]                         = iret_interception,
2761         [SVM_EXIT_INVD]                         = emulate_on_interception,
2762         [SVM_EXIT_PAUSE]                        = pause_interception,
2763         [SVM_EXIT_HLT]                          = halt_interception,
2764         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2765         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
2766         [SVM_EXIT_IOIO]                         = io_interception,
2767         [SVM_EXIT_MSR]                          = msr_interception,
2768         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2769         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2770         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2771         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2772         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2773         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2774         [SVM_EXIT_STGI]                         = stgi_interception,
2775         [SVM_EXIT_CLGI]                         = clgi_interception,
2776         [SVM_EXIT_SKINIT]                       = skinit_interception,
2777         [SVM_EXIT_WBINVD]                       = wbinvd_interception,
2778         [SVM_EXIT_MONITOR]                      = monitor_interception,
2779         [SVM_EXIT_MWAIT]                        = mwait_interception,
2780         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
2781         [SVM_EXIT_RDPRU]                        = rdpru_interception,
2782         [SVM_EXIT_NPF]                          = npf_interception,
2783         [SVM_EXIT_RSM]                          = rsm_interception,
2784         [SVM_EXIT_AVIC_INCOMPLETE_IPI]          = avic_incomplete_ipi_interception,
2785         [SVM_EXIT_AVIC_UNACCELERATED_ACCESS]    = avic_unaccelerated_access_interception,
2786 };
2787
2788 static void dump_vmcb(struct kvm_vcpu *vcpu)
2789 {
2790         struct vcpu_svm *svm = to_svm(vcpu);
2791         struct vmcb_control_area *control = &svm->vmcb->control;
2792         struct vmcb_save_area *save = &svm->vmcb->save;
2793
2794         if (!dump_invalid_vmcb) {
2795                 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
2796                 return;
2797         }
2798
2799         pr_err("VMCB Control Area:\n");
2800         pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
2801         pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
2802         pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
2803         pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
2804         pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
2805         pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
2806         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
2807         pr_err("%-20s%d\n", "pause filter threshold:",
2808                control->pause_filter_thresh);
2809         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
2810         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
2811         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
2812         pr_err("%-20s%d\n", "asid:", control->asid);
2813         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
2814         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
2815         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
2816         pr_err("%-20s%08x\n", "int_state:", control->int_state);
2817         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
2818         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
2819         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
2820         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
2821         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
2822         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
2823         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
2824         pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
2825         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
2826         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
2827         pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
2828         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
2829         pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
2830         pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
2831         pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
2832         pr_err("VMCB State Save Area:\n");
2833         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2834                "es:",
2835                save->es.selector, save->es.attrib,
2836                save->es.limit, save->es.base);
2837         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2838                "cs:",
2839                save->cs.selector, save->cs.attrib,
2840                save->cs.limit, save->cs.base);
2841         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2842                "ss:",
2843                save->ss.selector, save->ss.attrib,
2844                save->ss.limit, save->ss.base);
2845         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2846                "ds:",
2847                save->ds.selector, save->ds.attrib,
2848                save->ds.limit, save->ds.base);
2849         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2850                "fs:",
2851                save->fs.selector, save->fs.attrib,
2852                save->fs.limit, save->fs.base);
2853         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2854                "gs:",
2855                save->gs.selector, save->gs.attrib,
2856                save->gs.limit, save->gs.base);
2857         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2858                "gdtr:",
2859                save->gdtr.selector, save->gdtr.attrib,
2860                save->gdtr.limit, save->gdtr.base);
2861         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2862                "ldtr:",
2863                save->ldtr.selector, save->ldtr.attrib,
2864                save->ldtr.limit, save->ldtr.base);
2865         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2866                "idtr:",
2867                save->idtr.selector, save->idtr.attrib,
2868                save->idtr.limit, save->idtr.base);
2869         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2870                "tr:",
2871                save->tr.selector, save->tr.attrib,
2872                save->tr.limit, save->tr.base);
2873         pr_err("cpl:            %d                efer:         %016llx\n",
2874                 save->cpl, save->efer);
2875         pr_err("%-15s %016llx %-13s %016llx\n",
2876                "cr0:", save->cr0, "cr2:", save->cr2);
2877         pr_err("%-15s %016llx %-13s %016llx\n",
2878                "cr3:", save->cr3, "cr4:", save->cr4);
2879         pr_err("%-15s %016llx %-13s %016llx\n",
2880                "dr6:", save->dr6, "dr7:", save->dr7);
2881         pr_err("%-15s %016llx %-13s %016llx\n",
2882                "rip:", save->rip, "rflags:", save->rflags);
2883         pr_err("%-15s %016llx %-13s %016llx\n",
2884                "rsp:", save->rsp, "rax:", save->rax);
2885         pr_err("%-15s %016llx %-13s %016llx\n",
2886                "star:", save->star, "lstar:", save->lstar);
2887         pr_err("%-15s %016llx %-13s %016llx\n",
2888                "cstar:", save->cstar, "sfmask:", save->sfmask);
2889         pr_err("%-15s %016llx %-13s %016llx\n",
2890                "kernel_gs_base:", save->kernel_gs_base,
2891                "sysenter_cs:", save->sysenter_cs);
2892         pr_err("%-15s %016llx %-13s %016llx\n",
2893                "sysenter_esp:", save->sysenter_esp,
2894                "sysenter_eip:", save->sysenter_eip);
2895         pr_err("%-15s %016llx %-13s %016llx\n",
2896                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
2897         pr_err("%-15s %016llx %-13s %016llx\n",
2898                "br_from:", save->br_from, "br_to:", save->br_to);
2899         pr_err("%-15s %016llx %-13s %016llx\n",
2900                "excp_from:", save->last_excp_from,
2901                "excp_to:", save->last_excp_to);
2902 }
2903
2904 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
2905 {
2906         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
2907
2908         *info1 = control->exit_info_1;
2909         *info2 = control->exit_info_2;
2910 }
2911
2912 static int handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
2913 {
2914         struct vcpu_svm *svm = to_svm(vcpu);
2915         struct kvm_run *kvm_run = vcpu->run;
2916         u32 exit_code = svm->vmcb->control.exit_code;
2917
2918         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
2919
2920         if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
2921                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2922         if (npt_enabled)
2923                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2924
2925         svm_complete_interrupts(svm);
2926
2927         if (is_guest_mode(vcpu)) {
2928                 int vmexit;
2929
2930                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2931                                         svm->vmcb->control.exit_info_1,
2932                                         svm->vmcb->control.exit_info_2,
2933                                         svm->vmcb->control.exit_int_info,
2934                                         svm->vmcb->control.exit_int_info_err,
2935                                         KVM_ISA_SVM);
2936
2937                 vmexit = nested_svm_exit_special(svm);
2938
2939                 if (vmexit == NESTED_EXIT_CONTINUE)
2940                         vmexit = nested_svm_exit_handled(svm);
2941
2942                 if (vmexit == NESTED_EXIT_DONE)
2943                         return 1;
2944         }
2945
2946         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2947                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2948                 kvm_run->fail_entry.hardware_entry_failure_reason
2949                         = svm->vmcb->control.exit_code;
2950                 dump_vmcb(vcpu);
2951                 return 0;
2952         }
2953
2954         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2955             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2956             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
2957             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
2958                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
2959                        "exit_code 0x%x\n",
2960                        __func__, svm->vmcb->control.exit_int_info,
2961                        exit_code);
2962
2963         if (exit_fastpath != EXIT_FASTPATH_NONE)
2964                 return 1;
2965
2966         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2967             || !svm_exit_handlers[exit_code]) {
2968                 vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%x\n", exit_code);
2969                 dump_vmcb(vcpu);
2970                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2971                 vcpu->run->internal.suberror =
2972                         KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
2973                 vcpu->run->internal.ndata = 1;
2974                 vcpu->run->internal.data[0] = exit_code;
2975                 return 0;
2976         }
2977
2978 #ifdef CONFIG_RETPOLINE
2979         if (exit_code == SVM_EXIT_MSR)
2980                 return msr_interception(svm);
2981         else if (exit_code == SVM_EXIT_VINTR)
2982                 return interrupt_window_interception(svm);
2983         else if (exit_code == SVM_EXIT_INTR)
2984                 return intr_interception(svm);
2985         else if (exit_code == SVM_EXIT_HLT)
2986                 return halt_interception(svm);
2987         else if (exit_code == SVM_EXIT_NPF)
2988                 return npf_interception(svm);
2989 #endif
2990         return svm_exit_handlers[exit_code](svm);
2991 }
2992
2993 static void reload_tss(struct kvm_vcpu *vcpu)
2994 {
2995         int cpu = raw_smp_processor_id();
2996
2997         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2998         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
2999         load_TR_desc();
3000 }
3001
3002 static void pre_svm_run(struct vcpu_svm *svm)
3003 {
3004         int cpu = raw_smp_processor_id();
3005
3006         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3007
3008         if (sev_guest(svm->vcpu.kvm))
3009                 return pre_sev_run(svm, cpu);
3010
3011         /* FIXME: handle wraparound of asid_generation */
3012         if (svm->asid_generation != sd->asid_generation)
3013                 new_asid(svm, sd);
3014 }
3015
3016 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3017 {
3018         struct vcpu_svm *svm = to_svm(vcpu);
3019
3020         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3021         vcpu->arch.hflags |= HF_NMI_MASK;
3022         set_intercept(svm, INTERCEPT_IRET);
3023         ++vcpu->stat.nmi_injections;
3024 }
3025
3026 static void svm_set_irq(struct kvm_vcpu *vcpu)
3027 {
3028         struct vcpu_svm *svm = to_svm(vcpu);
3029
3030         BUG_ON(!(gif_set(svm)));
3031
3032         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3033         ++vcpu->stat.irq_injections;
3034
3035         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3036                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3037 }
3038
3039 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3040 {
3041         struct vcpu_svm *svm = to_svm(vcpu);
3042
3043         if (svm_nested_virtualize_tpr(vcpu))
3044                 return;
3045
3046         clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3047
3048         if (irr == -1)
3049                 return;
3050
3051         if (tpr >= irr)
3052                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3053 }
3054
3055 bool svm_nmi_blocked(struct kvm_vcpu *vcpu)
3056 {
3057         struct vcpu_svm *svm = to_svm(vcpu);
3058         struct vmcb *vmcb = svm->vmcb;
3059         bool ret;
3060
3061         if (!gif_set(svm))
3062                 return true;
3063
3064         if (is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3065                 return false;
3066
3067         ret = (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
3068               (svm->vcpu.arch.hflags & HF_NMI_MASK);
3069
3070         return ret;
3071 }
3072
3073 static int svm_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3074 {
3075         struct vcpu_svm *svm = to_svm(vcpu);
3076         if (svm->nested.nested_run_pending)
3077                 return -EBUSY;
3078
3079         /* An NMI must not be injected into L2 if it's supposed to VM-Exit.  */
3080         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3081                 return -EBUSY;
3082
3083         return !svm_nmi_blocked(vcpu);
3084 }
3085
3086 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3087 {
3088         struct vcpu_svm *svm = to_svm(vcpu);
3089
3090         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3091 }
3092
3093 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3094 {
3095         struct vcpu_svm *svm = to_svm(vcpu);
3096
3097         if (masked) {
3098                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3099                 set_intercept(svm, INTERCEPT_IRET);
3100         } else {
3101                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3102                 clr_intercept(svm, INTERCEPT_IRET);
3103         }
3104 }
3105
3106 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu)
3107 {
3108         struct vcpu_svm *svm = to_svm(vcpu);
3109         struct vmcb *vmcb = svm->vmcb;
3110
3111         if (!gif_set(svm))
3112                 return true;
3113
3114         if (is_guest_mode(vcpu)) {
3115                 /* As long as interrupts are being delivered...  */
3116                 if ((svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK)
3117                     ? !(svm->nested.hsave->save.rflags & X86_EFLAGS_IF)
3118                     : !(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3119                         return true;
3120
3121                 /* ... vmexits aren't blocked by the interrupt shadow  */
3122                 if (nested_exit_on_intr(svm))
3123                         return false;
3124         } else {
3125                 if (!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3126                         return true;
3127         }
3128
3129         return (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK);
3130 }
3131
3132 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3133 {
3134         struct vcpu_svm *svm = to_svm(vcpu);
3135         if (svm->nested.nested_run_pending)
3136                 return -EBUSY;
3137
3138         /*
3139          * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
3140          * e.g. if the IRQ arrived asynchronously after checking nested events.
3141          */
3142         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(svm))
3143                 return -EBUSY;
3144
3145         return !svm_interrupt_blocked(vcpu);
3146 }
3147
3148 static void enable_irq_window(struct kvm_vcpu *vcpu)
3149 {
3150         struct vcpu_svm *svm = to_svm(vcpu);
3151
3152         /*
3153          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3154          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
3155          * get that intercept, this function will be called again though and
3156          * we'll get the vintr intercept. However, if the vGIF feature is
3157          * enabled, the STGI interception will not occur. Enable the irq
3158          * window under the assumption that the hardware will set the GIF.
3159          */
3160         if (vgif_enabled(svm) || gif_set(svm)) {
3161                 /*
3162                  * IRQ window is not needed when AVIC is enabled,
3163                  * unless we have pending ExtINT since it cannot be injected
3164                  * via AVIC. In such case, we need to temporarily disable AVIC,
3165                  * and fallback to injecting IRQ via V_IRQ.
3166                  */
3167                 svm_toggle_avic_for_irq_window(vcpu, false);
3168                 svm_set_vintr(svm);
3169         }
3170 }
3171
3172 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3173 {
3174         struct vcpu_svm *svm = to_svm(vcpu);
3175
3176         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3177             == HF_NMI_MASK)
3178                 return; /* IRET will cause a vm exit */
3179
3180         if (!gif_set(svm)) {
3181                 if (vgif_enabled(svm))
3182                         set_intercept(svm, INTERCEPT_STGI);
3183                 return; /* STGI will cause a vm exit */
3184         }
3185
3186         /*
3187          * Something prevents NMI from been injected. Single step over possible
3188          * problem (IRET or exception injection or interrupt shadow)
3189          */
3190         svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
3191         svm->nmi_singlestep = true;
3192         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3193 }
3194
3195 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3196 {
3197         return 0;
3198 }
3199
3200 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
3201 {
3202         return 0;
3203 }
3204
3205 void svm_flush_tlb(struct kvm_vcpu *vcpu)
3206 {
3207         struct vcpu_svm *svm = to_svm(vcpu);
3208
3209         /*
3210          * Flush only the current ASID even if the TLB flush was invoked via
3211          * kvm_flush_remote_tlbs().  Although flushing remote TLBs requires all
3212          * ASIDs to be flushed, KVM uses a single ASID for L1 and L2, and
3213          * unconditionally does a TLB flush on both nested VM-Enter and nested
3214          * VM-Exit (via kvm_mmu_reset_context()).
3215          */
3216         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3217                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3218         else
3219                 svm->asid_generation--;
3220 }
3221
3222 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
3223 {
3224         struct vcpu_svm *svm = to_svm(vcpu);
3225
3226         invlpga(gva, svm->vmcb->control.asid);
3227 }
3228
3229 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3230 {
3231 }
3232
3233 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3234 {
3235         struct vcpu_svm *svm = to_svm(vcpu);
3236
3237         if (svm_nested_virtualize_tpr(vcpu))
3238                 return;
3239
3240         if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3241                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3242                 kvm_set_cr8(vcpu, cr8);
3243         }
3244 }
3245
3246 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3247 {
3248         struct vcpu_svm *svm = to_svm(vcpu);
3249         u64 cr8;
3250
3251         if (svm_nested_virtualize_tpr(vcpu) ||
3252             kvm_vcpu_apicv_active(vcpu))
3253                 return;
3254
3255         cr8 = kvm_get_cr8(vcpu);
3256         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3257         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3258 }
3259
3260 static void svm_complete_interrupts(struct vcpu_svm *svm)
3261 {
3262         u8 vector;
3263         int type;
3264         u32 exitintinfo = svm->vmcb->control.exit_int_info;
3265         unsigned int3_injected = svm->int3_injected;
3266
3267         svm->int3_injected = 0;
3268
3269         /*
3270          * If we've made progress since setting HF_IRET_MASK, we've
3271          * executed an IRET and can allow NMI injection.
3272          */
3273         if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3274             && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3275                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3276                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3277         }
3278
3279         svm->vcpu.arch.nmi_injected = false;
3280         kvm_clear_exception_queue(&svm->vcpu);
3281         kvm_clear_interrupt_queue(&svm->vcpu);
3282
3283         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3284                 return;
3285
3286         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3287
3288         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3289         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3290
3291         switch (type) {
3292         case SVM_EXITINTINFO_TYPE_NMI:
3293                 svm->vcpu.arch.nmi_injected = true;
3294                 break;
3295         case SVM_EXITINTINFO_TYPE_EXEPT:
3296                 /*
3297                  * In case of software exceptions, do not reinject the vector,
3298                  * but re-execute the instruction instead. Rewind RIP first
3299                  * if we emulated INT3 before.
3300                  */
3301                 if (kvm_exception_is_soft(vector)) {
3302                         if (vector == BP_VECTOR && int3_injected &&
3303                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3304                                 kvm_rip_write(&svm->vcpu,
3305                                               kvm_rip_read(&svm->vcpu) -
3306                                               int3_injected);
3307                         break;
3308                 }
3309                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3310                         u32 err = svm->vmcb->control.exit_int_info_err;
3311                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
3312
3313                 } else
3314                         kvm_requeue_exception(&svm->vcpu, vector);
3315                 break;
3316         case SVM_EXITINTINFO_TYPE_INTR:
3317                 kvm_queue_interrupt(&svm->vcpu, vector, false);
3318                 break;
3319         default:
3320                 break;
3321         }
3322 }
3323
3324 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3325 {
3326         struct vcpu_svm *svm = to_svm(vcpu);
3327         struct vmcb_control_area *control = &svm->vmcb->control;
3328
3329         control->exit_int_info = control->event_inj;
3330         control->exit_int_info_err = control->event_inj_err;
3331         control->event_inj = 0;
3332         svm_complete_interrupts(svm);
3333 }
3334
3335 static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
3336 {
3337         if (!is_guest_mode(vcpu) &&
3338             to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_MSR &&
3339             to_svm(vcpu)->vmcb->control.exit_info_1)
3340                 return handle_fastpath_set_msr_irqoff(vcpu);
3341
3342         return EXIT_FASTPATH_NONE;
3343 }
3344
3345 void __svm_vcpu_run(unsigned long vmcb_pa, unsigned long *regs);
3346
3347 static fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu)
3348 {
3349         fastpath_t exit_fastpath;
3350         struct vcpu_svm *svm = to_svm(vcpu);
3351
3352         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3353         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3354         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3355
3356         /*
3357          * Disable singlestep if we're injecting an interrupt/exception.
3358          * We don't want our modified rflags to be pushed on the stack where
3359          * we might not be able to easily reset them if we disabled NMI
3360          * singlestep later.
3361          */
3362         if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
3363                 /*
3364                  * Event injection happens before external interrupts cause a
3365                  * vmexit and interrupts are disabled here, so smp_send_reschedule
3366                  * is enough to force an immediate vmexit.
3367                  */
3368                 disable_nmi_singlestep(svm);
3369                 smp_send_reschedule(vcpu->cpu);
3370         }
3371
3372         pre_svm_run(svm);
3373
3374         sync_lapic_to_cr8(vcpu);
3375
3376         svm->vmcb->save.cr2 = vcpu->arch.cr2;
3377
3378         /*
3379          * Run with all-zero DR6 unless needed, so that we can get the exact cause
3380          * of a #DB.
3381          */
3382         if (unlikely(svm->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
3383                 svm_set_dr6(svm, vcpu->arch.dr6);
3384         else
3385                 svm_set_dr6(svm, DR6_FIXED_1 | DR6_RTM);
3386
3387         clgi();
3388         kvm_load_guest_xsave_state(vcpu);
3389
3390         if (lapic_in_kernel(vcpu) &&
3391                 vcpu->arch.apic->lapic_timer.timer_advance_ns)
3392                 kvm_wait_lapic_expire(vcpu);
3393
3394         /*
3395          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
3396          * it's non-zero. Since vmentry is serialising on affected CPUs, there
3397          * is no need to worry about the conditional branch over the wrmsr
3398          * being speculatively taken.
3399          */
3400         x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
3401
3402         __svm_vcpu_run(svm->vmcb_pa, (unsigned long *)&svm->vcpu.arch.regs);
3403
3404 #ifdef CONFIG_X86_64
3405         wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3406 #else
3407         loadsegment(fs, svm->host.fs);
3408 #ifndef CONFIG_X86_32_LAZY_GS
3409         loadsegment(gs, svm->host.gs);
3410 #endif
3411 #endif
3412
3413         /*
3414          * We do not use IBRS in the kernel. If this vCPU has used the
3415          * SPEC_CTRL MSR it may have left it on; save the value and
3416          * turn it off. This is much more efficient than blindly adding
3417          * it to the atomic save/restore list. Especially as the former
3418          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
3419          *
3420          * For non-nested case:
3421          * If the L01 MSR bitmap does not intercept the MSR, then we need to
3422          * save it.
3423          *
3424          * For nested case:
3425          * If the L02 MSR bitmap does not intercept the MSR, then we need to
3426          * save it.
3427          */
3428         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
3429                 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
3430
3431         reload_tss(vcpu);
3432
3433         x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
3434
3435         vcpu->arch.cr2 = svm->vmcb->save.cr2;
3436         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3437         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3438         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3439
3440         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3441                 kvm_before_interrupt(&svm->vcpu);
3442
3443         kvm_load_host_xsave_state(vcpu);
3444         stgi();
3445
3446         /* Any pending NMI will happen here */
3447         exit_fastpath = svm_exit_handlers_fastpath(vcpu);
3448
3449         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3450                 kvm_after_interrupt(&svm->vcpu);
3451
3452         sync_cr8_to_lapic(vcpu);
3453
3454         svm->next_rip = 0;
3455         if (is_guest_mode(&svm->vcpu)) {
3456                 sync_nested_vmcb_control(svm);
3457                 svm->nested.nested_run_pending = 0;
3458         }
3459
3460         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3461
3462         /* if exit due to PF check for async PF */
3463         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3464                 svm->vcpu.arch.apf.host_apf_flags =
3465                         kvm_read_and_reset_apf_flags();
3466
3467         if (npt_enabled) {
3468                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3469                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3470         }
3471
3472         /*
3473          * We need to handle MC intercepts here before the vcpu has a chance to
3474          * change the physical cpu
3475          */
3476         if (unlikely(svm->vmcb->control.exit_code ==
3477                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
3478                 svm_handle_mce(svm);
3479
3480         mark_all_clean(svm->vmcb);
3481         return exit_fastpath;
3482 }
3483
3484 static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long root)
3485 {
3486         struct vcpu_svm *svm = to_svm(vcpu);
3487         unsigned long cr3;
3488
3489         cr3 = __sme_set(root);
3490         if (npt_enabled) {
3491                 svm->vmcb->control.nested_cr3 = cr3;
3492                 mark_dirty(svm->vmcb, VMCB_NPT);
3493
3494                 /* Loading L2's CR3 is handled by enter_svm_guest_mode.  */
3495                 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3496                         return;
3497                 cr3 = vcpu->arch.cr3;
3498         }
3499
3500         svm->vmcb->save.cr3 = cr3;
3501         mark_dirty(svm->vmcb, VMCB_CR);
3502 }
3503
3504 static int is_disabled(void)
3505 {
3506         u64 vm_cr;
3507
3508         rdmsrl(MSR_VM_CR, vm_cr);
3509         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3510                 return 1;
3511
3512         return 0;
3513 }
3514
3515 static void
3516 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3517 {
3518         /*
3519          * Patch in the VMMCALL instruction:
3520          */
3521         hypercall[0] = 0x0f;
3522         hypercall[1] = 0x01;
3523         hypercall[2] = 0xd9;
3524 }
3525
3526 static int __init svm_check_processor_compat(void)
3527 {
3528         return 0;
3529 }
3530
3531 static bool svm_cpu_has_accelerated_tpr(void)
3532 {
3533         return false;
3534 }
3535
3536 static bool svm_has_emulated_msr(u32 index)
3537 {
3538         switch (index) {
3539         case MSR_IA32_MCG_EXT_CTL:
3540         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3541                 return false;
3542         default:
3543                 break;
3544         }
3545
3546         return true;
3547 }
3548
3549 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3550 {
3551         return 0;
3552 }
3553
3554 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3555 {
3556         struct vcpu_svm *svm = to_svm(vcpu);
3557
3558         vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
3559                                     boot_cpu_has(X86_FEATURE_XSAVE) &&
3560                                     boot_cpu_has(X86_FEATURE_XSAVES);
3561
3562         /* Update nrips enabled cache */
3563         svm->nrips_enabled = kvm_cpu_cap_has(X86_FEATURE_NRIPS) &&
3564                              guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
3565
3566         if (!kvm_vcpu_apicv_active(vcpu))
3567                 return;
3568
3569         /*
3570          * AVIC does not work with an x2APIC mode guest. If the X2APIC feature
3571          * is exposed to the guest, disable AVIC.
3572          */
3573         if (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC))
3574                 kvm_request_apicv_update(vcpu->kvm, false,
3575                                          APICV_INHIBIT_REASON_X2APIC);
3576
3577         /*
3578          * Currently, AVIC does not work with nested virtualization.
3579          * So, we disable AVIC when cpuid for SVM is set in the L1 guest.
3580          */
3581         if (nested && guest_cpuid_has(vcpu, X86_FEATURE_SVM))
3582                 kvm_request_apicv_update(vcpu->kvm, false,
3583                                          APICV_INHIBIT_REASON_NESTED);
3584 }
3585
3586 static bool svm_has_wbinvd_exit(void)
3587 {
3588         return true;
3589 }
3590
3591 #define PRE_EX(exit)  { .exit_code = (exit), \
3592                         .stage = X86_ICPT_PRE_EXCEPT, }
3593 #define POST_EX(exit) { .exit_code = (exit), \
3594                         .stage = X86_ICPT_POST_EXCEPT, }
3595 #define POST_MEM(exit) { .exit_code = (exit), \
3596                         .stage = X86_ICPT_POST_MEMACCESS, }
3597
3598 static const struct __x86_intercept {
3599         u32 exit_code;
3600         enum x86_intercept_stage stage;
3601 } x86_intercept_map[] = {
3602         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
3603         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
3604         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
3605         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
3606         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
3607         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
3608         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
3609         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
3610         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
3611         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
3612         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
3613         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
3614         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
3615         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
3616         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
3617         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
3618         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
3619         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
3620         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
3621         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
3622         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
3623         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
3624         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
3625         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
3626         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
3627         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
3628         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
3629         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
3630         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
3631         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
3632         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
3633         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
3634         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
3635         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
3636         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
3637         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
3638         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
3639         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
3640         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
3641         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
3642         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
3643         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
3644         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
3645         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
3646         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
3647         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
3648         [x86_intercept_xsetbv]          = PRE_EX(SVM_EXIT_XSETBV),
3649 };
3650
3651 #undef PRE_EX
3652 #undef POST_EX
3653 #undef POST_MEM
3654
3655 static int svm_check_intercept(struct kvm_vcpu *vcpu,
3656                                struct x86_instruction_info *info,
3657                                enum x86_intercept_stage stage,
3658                                struct x86_exception *exception)
3659 {
3660         struct vcpu_svm *svm = to_svm(vcpu);
3661         int vmexit, ret = X86EMUL_CONTINUE;
3662         struct __x86_intercept icpt_info;
3663         struct vmcb *vmcb = svm->vmcb;
3664
3665         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
3666                 goto out;
3667
3668         icpt_info = x86_intercept_map[info->intercept];
3669
3670         if (stage != icpt_info.stage)
3671                 goto out;
3672
3673         switch (icpt_info.exit_code) {
3674         case SVM_EXIT_READ_CR0:
3675                 if (info->intercept == x86_intercept_cr_read)
3676                         icpt_info.exit_code += info->modrm_reg;
3677                 break;
3678         case SVM_EXIT_WRITE_CR0: {
3679                 unsigned long cr0, val;
3680                 u64 intercept;
3681
3682                 if (info->intercept == x86_intercept_cr_write)
3683                         icpt_info.exit_code += info->modrm_reg;
3684
3685                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
3686                     info->intercept == x86_intercept_clts)
3687                         break;
3688
3689                 intercept = svm->nested.ctl.intercept;
3690
3691                 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
3692                         break;
3693
3694                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
3695                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
3696
3697                 if (info->intercept == x86_intercept_lmsw) {
3698                         cr0 &= 0xfUL;
3699                         val &= 0xfUL;
3700                         /* lmsw can't clear PE - catch this here */
3701                         if (cr0 & X86_CR0_PE)
3702                                 val |= X86_CR0_PE;
3703                 }
3704
3705                 if (cr0 ^ val)
3706                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3707
3708                 break;
3709         }
3710         case SVM_EXIT_READ_DR0:
3711         case SVM_EXIT_WRITE_DR0:
3712                 icpt_info.exit_code += info->modrm_reg;
3713                 break;
3714         case SVM_EXIT_MSR:
3715                 if (info->intercept == x86_intercept_wrmsr)
3716                         vmcb->control.exit_info_1 = 1;
3717                 else
3718                         vmcb->control.exit_info_1 = 0;
3719                 break;
3720         case SVM_EXIT_PAUSE:
3721                 /*
3722                  * We get this for NOP only, but pause
3723                  * is rep not, check this here
3724                  */
3725                 if (info->rep_prefix != REPE_PREFIX)
3726                         goto out;
3727                 break;
3728         case SVM_EXIT_IOIO: {
3729                 u64 exit_info;
3730                 u32 bytes;
3731
3732                 if (info->intercept == x86_intercept_in ||
3733                     info->intercept == x86_intercept_ins) {
3734                         exit_info = ((info->src_val & 0xffff) << 16) |
3735                                 SVM_IOIO_TYPE_MASK;
3736                         bytes = info->dst_bytes;
3737                 } else {
3738                         exit_info = (info->dst_val & 0xffff) << 16;
3739                         bytes = info->src_bytes;
3740                 }
3741
3742                 if (info->intercept == x86_intercept_outs ||
3743                     info->intercept == x86_intercept_ins)
3744                         exit_info |= SVM_IOIO_STR_MASK;
3745
3746                 if (info->rep_prefix)
3747                         exit_info |= SVM_IOIO_REP_MASK;
3748
3749                 bytes = min(bytes, 4u);
3750
3751                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
3752
3753                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
3754
3755                 vmcb->control.exit_info_1 = exit_info;
3756                 vmcb->control.exit_info_2 = info->next_rip;
3757
3758                 break;
3759         }
3760         default:
3761                 break;
3762         }
3763
3764         /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
3765         if (static_cpu_has(X86_FEATURE_NRIPS))
3766                 vmcb->control.next_rip  = info->next_rip;
3767         vmcb->control.exit_code = icpt_info.exit_code;
3768         vmexit = nested_svm_exit_handled(svm);
3769
3770         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
3771                                            : X86EMUL_CONTINUE;
3772
3773 out:
3774         return ret;
3775 }
3776
3777 static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu)
3778 {
3779 }
3780
3781 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
3782 {
3783         if (pause_filter_thresh)
3784                 shrink_ple_window(vcpu);
3785 }
3786
3787 static void svm_setup_mce(struct kvm_vcpu *vcpu)
3788 {
3789         /* [63:9] are reserved. */
3790         vcpu->arch.mcg_cap &= 0x1ff;
3791 }
3792
3793 bool svm_smi_blocked(struct kvm_vcpu *vcpu)
3794 {
3795         struct vcpu_svm *svm = to_svm(vcpu);
3796
3797         /* Per APM Vol.2 15.22.2 "Response to SMI" */
3798         if (!gif_set(svm))
3799                 return true;
3800
3801         return is_smm(vcpu);
3802 }
3803
3804 static int svm_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3805 {
3806         struct vcpu_svm *svm = to_svm(vcpu);
3807         if (svm->nested.nested_run_pending)
3808                 return -EBUSY;
3809
3810         /* An SMI must not be injected into L2 if it's supposed to VM-Exit.  */
3811         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_smi(svm))
3812                 return -EBUSY;
3813
3814         return !svm_smi_blocked(vcpu);
3815 }
3816
3817 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
3818 {
3819         struct vcpu_svm *svm = to_svm(vcpu);
3820         int ret;
3821
3822         if (is_guest_mode(vcpu)) {
3823                 /* FED8h - SVM Guest */
3824                 put_smstate(u64, smstate, 0x7ed8, 1);
3825                 /* FEE0h - SVM Guest VMCB Physical Address */
3826                 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb);
3827
3828                 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3829                 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3830                 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3831
3832                 ret = nested_svm_vmexit(svm);
3833                 if (ret)
3834                         return ret;
3835         }
3836         return 0;
3837 }
3838
3839 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
3840 {
3841         struct vcpu_svm *svm = to_svm(vcpu);
3842         struct vmcb *nested_vmcb;
3843         struct kvm_host_map map;
3844         u64 guest;
3845         u64 vmcb;
3846
3847         guest = GET_SMSTATE(u64, smstate, 0x7ed8);
3848         vmcb = GET_SMSTATE(u64, smstate, 0x7ee0);
3849
3850         if (guest) {
3851                 if (kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(vmcb), &map) == -EINVAL)
3852                         return 1;
3853                 nested_vmcb = map.hva;
3854                 enter_svm_guest_mode(svm, vmcb, nested_vmcb);
3855                 kvm_vcpu_unmap(&svm->vcpu, &map, true);
3856         }
3857         return 0;
3858 }
3859
3860 static void enable_smi_window(struct kvm_vcpu *vcpu)
3861 {
3862         struct vcpu_svm *svm = to_svm(vcpu);
3863
3864         if (!gif_set(svm)) {
3865                 if (vgif_enabled(svm))
3866                         set_intercept(svm, INTERCEPT_STGI);
3867                 /* STGI will cause a vm exit */
3868         } else {
3869                 /* We must be in SMM; RSM will cause a vmexit anyway.  */
3870         }
3871 }
3872
3873 static bool svm_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
3874 {
3875         unsigned long cr4 = kvm_read_cr4(vcpu);
3876         bool smep = cr4 & X86_CR4_SMEP;
3877         bool smap = cr4 & X86_CR4_SMAP;
3878         bool is_user = svm_get_cpl(vcpu) == 3;
3879
3880         /*
3881          * If RIP is invalid, go ahead with emulation which will cause an
3882          * internal error exit.
3883          */
3884         if (!kvm_vcpu_gfn_to_memslot(vcpu, kvm_rip_read(vcpu) >> PAGE_SHIFT))
3885                 return true;
3886
3887         /*
3888          * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
3889          *
3890          * Errata:
3891          * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is
3892          * possible that CPU microcode implementing DecodeAssist will fail
3893          * to read bytes of instruction which caused #NPF. In this case,
3894          * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly
3895          * return 0 instead of the correct guest instruction bytes.
3896          *
3897          * This happens because CPU microcode reading instruction bytes
3898          * uses a special opcode which attempts to read data using CPL=0
3899          * priviledges. The microcode reads CS:RIP and if it hits a SMAP
3900          * fault, it gives up and returns no instruction bytes.
3901          *
3902          * Detection:
3903          * We reach here in case CPU supports DecodeAssist, raised #NPF and
3904          * returned 0 in GuestIntrBytes field of the VMCB.
3905          * First, errata can only be triggered in case vCPU CR4.SMAP=1.
3906          * Second, if vCPU CR4.SMEP=1, errata could only be triggered
3907          * in case vCPU CPL==3 (Because otherwise guest would have triggered
3908          * a SMEP fault instead of #NPF).
3909          * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL.
3910          * As most guests enable SMAP if they have also enabled SMEP, use above
3911          * logic in order to attempt minimize false-positive of detecting errata
3912          * while still preserving all cases semantic correctness.
3913          *
3914          * Workaround:
3915          * To determine what instruction the guest was executing, the hypervisor
3916          * will have to decode the instruction at the instruction pointer.
3917          *
3918          * In non SEV guest, hypervisor will be able to read the guest
3919          * memory to decode the instruction pointer when insn_len is zero
3920          * so we return true to indicate that decoding is possible.
3921          *
3922          * But in the SEV guest, the guest memory is encrypted with the
3923          * guest specific key and hypervisor will not be able to decode the
3924          * instruction pointer so we will not able to workaround it. Lets
3925          * print the error and request to kill the guest.
3926          */
3927         if (smap && (!smep || is_user)) {
3928                 if (!sev_guest(vcpu->kvm))
3929                         return true;
3930
3931                 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
3932                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3933         }
3934
3935         return false;
3936 }
3937
3938 static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
3939 {
3940         struct vcpu_svm *svm = to_svm(vcpu);
3941
3942         /*
3943          * TODO: Last condition latch INIT signals on vCPU when
3944          * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
3945          * To properly emulate the INIT intercept,
3946          * svm_check_nested_events() should call nested_svm_vmexit()
3947          * if an INIT signal is pending.
3948          */
3949         return !gif_set(svm) ||
3950                    (svm->vmcb->control.intercept & (1ULL << INTERCEPT_INIT));
3951 }
3952
3953 static void svm_vm_destroy(struct kvm *kvm)
3954 {
3955         avic_vm_destroy(kvm);
3956         sev_vm_destroy(kvm);
3957 }
3958
3959 static int svm_vm_init(struct kvm *kvm)
3960 {
3961         if (avic) {
3962                 int ret = avic_vm_init(kvm);
3963                 if (ret)
3964                         return ret;
3965         }
3966
3967         kvm_apicv_init(kvm, avic);
3968         return 0;
3969 }
3970
3971 static struct kvm_x86_ops svm_x86_ops __initdata = {
3972         .hardware_unsetup = svm_hardware_teardown,
3973         .hardware_enable = svm_hardware_enable,
3974         .hardware_disable = svm_hardware_disable,
3975         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3976         .has_emulated_msr = svm_has_emulated_msr,
3977
3978         .vcpu_create = svm_create_vcpu,
3979         .vcpu_free = svm_free_vcpu,
3980         .vcpu_reset = svm_vcpu_reset,
3981
3982         .vm_size = sizeof(struct kvm_svm),
3983         .vm_init = svm_vm_init,
3984         .vm_destroy = svm_vm_destroy,
3985
3986         .prepare_guest_switch = svm_prepare_guest_switch,
3987         .vcpu_load = svm_vcpu_load,
3988         .vcpu_put = svm_vcpu_put,
3989         .vcpu_blocking = svm_vcpu_blocking,
3990         .vcpu_unblocking = svm_vcpu_unblocking,
3991
3992         .update_bp_intercept = update_bp_intercept,
3993         .get_msr_feature = svm_get_msr_feature,
3994         .get_msr = svm_get_msr,
3995         .set_msr = svm_set_msr,
3996         .get_segment_base = svm_get_segment_base,
3997         .get_segment = svm_get_segment,
3998         .set_segment = svm_set_segment,
3999         .get_cpl = svm_get_cpl,
4000         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4001         .set_cr0 = svm_set_cr0,
4002         .set_cr4 = svm_set_cr4,
4003         .set_efer = svm_set_efer,
4004         .get_idt = svm_get_idt,
4005         .set_idt = svm_set_idt,
4006         .get_gdt = svm_get_gdt,
4007         .set_gdt = svm_set_gdt,
4008         .set_dr7 = svm_set_dr7,
4009         .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4010         .cache_reg = svm_cache_reg,
4011         .get_rflags = svm_get_rflags,
4012         .set_rflags = svm_set_rflags,
4013
4014         .tlb_flush_all = svm_flush_tlb,
4015         .tlb_flush_current = svm_flush_tlb,
4016         .tlb_flush_gva = svm_flush_tlb_gva,
4017         .tlb_flush_guest = svm_flush_tlb,
4018
4019         .run = svm_vcpu_run,
4020         .handle_exit = handle_exit,
4021         .skip_emulated_instruction = skip_emulated_instruction,
4022         .update_emulated_instruction = NULL,
4023         .set_interrupt_shadow = svm_set_interrupt_shadow,
4024         .get_interrupt_shadow = svm_get_interrupt_shadow,
4025         .patch_hypercall = svm_patch_hypercall,
4026         .set_irq = svm_set_irq,
4027         .set_nmi = svm_inject_nmi,
4028         .queue_exception = svm_queue_exception,
4029         .cancel_injection = svm_cancel_injection,
4030         .interrupt_allowed = svm_interrupt_allowed,
4031         .nmi_allowed = svm_nmi_allowed,
4032         .get_nmi_mask = svm_get_nmi_mask,
4033         .set_nmi_mask = svm_set_nmi_mask,
4034         .enable_nmi_window = enable_nmi_window,
4035         .enable_irq_window = enable_irq_window,
4036         .update_cr8_intercept = update_cr8_intercept,
4037         .set_virtual_apic_mode = svm_set_virtual_apic_mode,
4038         .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
4039         .check_apicv_inhibit_reasons = svm_check_apicv_inhibit_reasons,
4040         .pre_update_apicv_exec_ctrl = svm_pre_update_apicv_exec_ctrl,
4041         .load_eoi_exitmap = svm_load_eoi_exitmap,
4042         .hwapic_irr_update = svm_hwapic_irr_update,
4043         .hwapic_isr_update = svm_hwapic_isr_update,
4044         .sync_pir_to_irr = kvm_lapic_find_highest_irr,
4045         .apicv_post_state_restore = avic_post_state_restore,
4046
4047         .set_tss_addr = svm_set_tss_addr,
4048         .set_identity_map_addr = svm_set_identity_map_addr,
4049         .get_tdp_level = get_npt_level,
4050         .get_mt_mask = svm_get_mt_mask,
4051
4052         .get_exit_info = svm_get_exit_info,
4053
4054         .cpuid_update = svm_cpuid_update,
4055
4056         .has_wbinvd_exit = svm_has_wbinvd_exit,
4057
4058         .write_l1_tsc_offset = svm_write_l1_tsc_offset,
4059
4060         .load_mmu_pgd = svm_load_mmu_pgd,
4061
4062         .check_intercept = svm_check_intercept,
4063         .handle_exit_irqoff = svm_handle_exit_irqoff,
4064
4065         .request_immediate_exit = __kvm_request_immediate_exit,
4066
4067         .sched_in = svm_sched_in,
4068
4069         .pmu_ops = &amd_pmu_ops,
4070         .nested_ops = &svm_nested_ops,
4071
4072         .deliver_posted_interrupt = svm_deliver_avic_intr,
4073         .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt,
4074         .update_pi_irte = svm_update_pi_irte,
4075         .setup_mce = svm_setup_mce,
4076
4077         .smi_allowed = svm_smi_allowed,
4078         .pre_enter_smm = svm_pre_enter_smm,
4079         .pre_leave_smm = svm_pre_leave_smm,
4080         .enable_smi_window = enable_smi_window,
4081
4082         .mem_enc_op = svm_mem_enc_op,
4083         .mem_enc_reg_region = svm_register_enc_region,
4084         .mem_enc_unreg_region = svm_unregister_enc_region,
4085
4086         .need_emulation_on_page_fault = svm_need_emulation_on_page_fault,
4087
4088         .apic_init_signal_blocked = svm_apic_init_signal_blocked,
4089 };
4090
4091 static struct kvm_x86_init_ops svm_init_ops __initdata = {
4092         .cpu_has_kvm_support = has_svm,
4093         .disabled_by_bios = is_disabled,
4094         .hardware_setup = svm_hardware_setup,
4095         .check_processor_compatibility = svm_check_processor_compat,
4096
4097         .runtime_ops = &svm_x86_ops,
4098 };
4099
4100 static int __init svm_init(void)
4101 {
4102         return kvm_init(&svm_init_ops, sizeof(struct vcpu_svm),
4103                         __alignof__(struct vcpu_svm), THIS_MODULE);
4104 }
4105
4106 static void __exit svm_exit(void)
4107 {
4108         kvm_exit();
4109 }
4110
4111 module_init(svm_init)
4112 module_exit(svm_exit)