arch/x86/kvm/svm/svm.c

   1 #define pr_fmt(fmt) "SVM: " fmt
   2
   3 #include <linux/kvm_host.h>
   4
   5 #include "irq.h"
   6 #include "mmu.h"
   7 #include "kvm_cache_regs.h"
   8 #include "x86.h"
   9 #include "cpuid.h"
  10 #include "pmu.h"
  11
  12 #include <linux/module.h>
  13 #include <linux/mod_devicetable.h>
  14 #include <linux/kernel.h>
  15 #include <linux/vmalloc.h>
  16 #include <linux/highmem.h>
  17 #include <linux/amd-iommu.h>
  18 #include <linux/sched.h>
  19 #include <linux/trace_events.h>
  20 #include <linux/slab.h>
  21 #include <linux/hashtable.h>
  22 #include <linux/objtool.h>
  23 #include <linux/psp-sev.h>
  24 #include <linux/file.h>
  25 #include <linux/pagemap.h>
  26 #include <linux/swap.h>
  27 #include <linux/rwsem.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/perf_event.h>
  31 #include <asm/tlbflush.h>
  32 #include <asm/desc.h>
  33 #include <asm/debugreg.h>
  34 #include <asm/kvm_para.h>
  35 #include <asm/irq_remapping.h>
  36 #include <asm/spec-ctrl.h>
  37 #include <asm/cpu_device_id.h>
  38 #include <asm/traps.h>
  39
  40 #include <asm/virtext.h>
  41 #include "trace.h"
  42
  43 #include "svm.h"
  44 #include "svm_ops.h"
  45
  46 #include "kvm_onhyperv.h"
  47 #include "svm_onhyperv.h"
  48
  49 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  50
  51 MODULE_AUTHOR("Qumranet");
  52 MODULE_LICENSE("GPL");
  53
  54 #ifdef MODULE
  55 static const struct x86_cpu_id svm_cpu_id[] = {
  56         X86_MATCH_FEATURE(X86_FEATURE_SVM, NULL),
  57         {}
  58 };
  59 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  60 #endif
  61
  62 #define SEG_TYPE_LDT 2
  63 #define SEG_TYPE_BUSY_TSS16 3
  64
  65 #define SVM_FEATURE_LBRV           (1 <<  1)
  66 #define SVM_FEATURE_SVML           (1 <<  2)
  67 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  68 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  69 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  70 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  71 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  72
  73 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  74
  75 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  76 #define TSC_RATIO_MIN           0x0000000000000001ULL
  77 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  78
  79 static bool erratum_383_found __read_mostly;
  80
  81 u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
  82
  83 /*
  84  * Set osvw_len to higher value when updated Revision Guides
  85  * are published and we know what the new status bits are
  86  */
  87 static uint64_t osvw_len = 4, osvw_status;
  88
  89 static DEFINE_PER_CPU(u64, current_tsc_ratio);
  90 #define TSC_RATIO_DEFAULT       0x0100000000ULL
  91
  92 static const struct svm_direct_access_msrs {
  93         u32 index;   /* Index of the MSR */
  94         bool always; /* True if intercept is initially cleared */
  95 } direct_access_msrs[MAX_DIRECT_ACCESS_MSRS] = {
  96         { .index = MSR_STAR,                            .always = true  },
  97         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
  98         { .index = MSR_IA32_SYSENTER_EIP,               .always = false },
  99         { .index = MSR_IA32_SYSENTER_ESP,               .always = false },
 100 #ifdef CONFIG_X86_64
 101         { .index = MSR_GS_BASE,                         .always = true  },
 102         { .index = MSR_FS_BASE,                         .always = true  },
 103         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 104         { .index = MSR_LSTAR,                           .always = true  },
 105         { .index = MSR_CSTAR,                           .always = true  },
 106         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 107 #endif
 108         { .index = MSR_IA32_SPEC_CTRL,                  .always = false },
 109         { .index = MSR_IA32_PRED_CMD,                   .always = false },
 110         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 111         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 112         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 113         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 114         { .index = MSR_EFER,                            .always = false },
 115         { .index = MSR_IA32_CR_PAT,                     .always = false },
 116         { .index = MSR_AMD64_SEV_ES_GHCB,               .always = true  },
 117         { .index = MSR_INVALID,                         .always = false },
 118 };
 119
 120 /*
 121  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 122  * pause_filter_count: On processors that support Pause filtering(indicated
 123  *      by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
 124  *      count value. On VMRUN this value is loaded into an internal counter.
 125  *      Each time a pause instruction is executed, this counter is decremented
 126  *      until it reaches zero at which time a #VMEXIT is generated if pause
 127  *      intercept is enabled. Refer to  AMD APM Vol 2 Section 15.14.4 Pause
 128  *      Intercept Filtering for more details.
 129  *      This also indicate if ple logic enabled.
 130  *
 131  * pause_filter_thresh: In addition, some processor families support advanced
 132  *      pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
 133  *      the amount of time a guest is allowed to execute in a pause loop.
 134  *      In this mode, a 16-bit pause filter threshold field is added in the
 135  *      VMCB. The threshold value is a cycle count that is used to reset the
 136  *      pause counter. As with simple pause filtering, VMRUN loads the pause
 137  *      count value from VMCB into an internal counter. Then, on each pause
 138  *      instruction the hardware checks the elapsed number of cycles since
 139  *      the most recent pause instruction against the pause filter threshold.
 140  *      If the elapsed cycle count is greater than the pause filter threshold,
 141  *      then the internal pause count is reloaded from the VMCB and execution
 142  *      continues. If the elapsed cycle count is less than the pause filter
 143  *      threshold, then the internal pause count is decremented. If the count
 144  *      value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
 145  *      triggered. If advanced pause filtering is supported and pause filter
 146  *      threshold field is set to zero, the filter will operate in the simpler,
 147  *      count only mode.
 148  */
 149
 150 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
 151 module_param(pause_filter_thresh, ushort, 0444);
 152
 153 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
 154 module_param(pause_filter_count, ushort, 0444);
 155
 156 /* Default doubles per-vcpu window every exit. */
 157 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 158 module_param(pause_filter_count_grow, ushort, 0444);
 159
 160 /* Default resets per-vcpu window every exit to pause_filter_count. */
 161 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 162 module_param(pause_filter_count_shrink, ushort, 0444);
 163
 164 /* Default is to compute the maximum so we can never overflow. */
 165 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
 166 module_param(pause_filter_count_max, ushort, 0444);
 167
 168 /*
 169  * Use nested page tables by default.  Note, NPT may get forced off by
 170  * svm_hardware_setup() if it's unsupported by hardware or the host kernel.
 171  */
 172 bool npt_enabled = true;
 173 module_param_named(npt, npt_enabled, bool, 0444);
 174
 175 /* allow nested virtualization in KVM/SVM */
 176 static int nested = true;
 177 module_param(nested, int, S_IRUGO);
 178
 179 /* enable/disable Next RIP Save */
 180 static int nrips = true;
 181 module_param(nrips, int, 0444);
 182
 183 /* enable/disable Virtual VMLOAD VMSAVE */
 184 static int vls = true;
 185 module_param(vls, int, 0444);
 186
 187 /* enable/disable Virtual GIF */
 188 static int vgif = true;
 189 module_param(vgif, int, 0444);
 190
 191 /*
 192  * enable / disable AVIC.  Because the defaults differ for APICv
 193  * support between VMX and SVM we cannot use module_param_named.
 194  */
 195 static bool avic;
 196 module_param(avic, bool, 0444);
 197
 198 bool __read_mostly dump_invalid_vmcb;
 199 module_param(dump_invalid_vmcb, bool, 0644);
 200
 201
 202 bool intercept_smi = true;
 203 module_param(intercept_smi, bool, 0444);
 204
 205
 206 static bool svm_gp_erratum_intercept = true;
 207
 208 static u8 rsm_ins_bytes[] = "\x0f\xaa";
 209
 210 static unsigned long iopm_base;
 211
 212 struct kvm_ldttss_desc {
 213         u16 limit0;
 214         u16 base0;
 215         unsigned base1:8, type:5, dpl:2, p:1;
 216         unsigned limit1:4, zero0:3, g:1, base2:8;
 217         u32 base3;
 218         u32 zero1;
 219 } __attribute__((packed));
 220
 221 DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 222
 223 /*
 224  * Only MSR_TSC_AUX is switched via the user return hook.  EFER is switched via
 225  * the VMCB, and the SYSCALL/SYSENTER MSRs are handled by VMLOAD/VMSAVE.
 226  *
 227  * RDTSCP and RDPID are not used in the kernel, specifically to allow KVM to
 228  * defer the restoration of TSC_AUX until the CPU returns to userspace.
 229  */
 230 static int tsc_aux_uret_slot __read_mostly = -1;
 231
 232 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 233
 234 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 235 #define MSRS_RANGE_SIZE 2048
 236 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 237
 238 u32 svm_msrpm_offset(u32 msr)
 239 {
 240         u32 offset;
 241         int i;
 242
 243         for (i = 0; i < NUM_MSR_MAPS; i++) {
 244                 if (msr < msrpm_ranges[i] ||
 245                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 246                         continue;
 247
 248                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 249                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 250
 251                 /* Now we have the u8 offset - but need the u32 offset */
 252                 return offset / 4;
 253         }
 254
 255         /* MSR not in any range */
 256         return MSR_INVALID;
 257 }
 258
 259 #define MAX_INST_SIZE 15
 260
 261 static int get_max_npt_level(void)
 262 {
 263 #ifdef CONFIG_X86_64
 264         return PT64_ROOT_4LEVEL;
 265 #else
 266         return PT32E_ROOT_LEVEL;
 267 #endif
 268 }
 269
 270 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 271 {
 272         struct vcpu_svm *svm = to_svm(vcpu);
 273         u64 old_efer = vcpu->arch.efer;
 274         vcpu->arch.efer = efer;
 275
 276         if (!npt_enabled) {
 277                 /* Shadow paging assumes NX to be available.  */
 278                 efer |= EFER_NX;
 279
 280                 if (!(efer & EFER_LMA))
 281                         efer &= ~EFER_LME;
 282         }
 283
 284         if ((old_efer & EFER_SVME) != (efer & EFER_SVME)) {
 285                 if (!(efer & EFER_SVME)) {
 286                         svm_leave_nested(svm);
 287                         svm_set_gif(svm, true);
 288                         /* #GP intercept is still needed for vmware backdoor */
 289                         if (!enable_vmware_backdoor)
 290                                 clr_exception_intercept(svm, GP_VECTOR);
 291
 292                         /*
 293                          * Free the nested guest state, unless we are in SMM.
 294                          * In this case we will return to the nested guest
 295                          * as soon as we leave SMM.
 296                          */
 297                         if (!is_smm(vcpu))
 298                                 svm_free_nested(svm);
 299
 300                 } else {
 301                         int ret = svm_allocate_nested(svm);
 302
 303                         if (ret) {
 304                                 vcpu->arch.efer = old_efer;
 305                                 return ret;
 306                         }
 307
 308                         if (svm_gp_erratum_intercept)
 309                                 set_exception_intercept(svm, GP_VECTOR);
 310                 }
 311         }
 312
 313         svm->vmcb->save.efer = efer | EFER_SVME;
 314         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
 315         return 0;
 316 }
 317
 318 static int is_external_interrupt(u32 info)
 319 {
 320         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 321         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 322 }
 323
 324 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
 325 {
 326         struct vcpu_svm *svm = to_svm(vcpu);
 327         u32 ret = 0;
 328
 329         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 330                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 331         return ret;
 332 }
 333
 334 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 335 {
 336         struct vcpu_svm *svm = to_svm(vcpu);
 337
 338         if (mask == 0)
 339                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 340         else
 341                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 342
 343 }
 344
 345 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
 346 {
 347         struct vcpu_svm *svm = to_svm(vcpu);
 348
 349         /*
 350          * SEV-ES does not expose the next RIP. The RIP update is controlled by
 351          * the type of exit and the #VC handler in the guest.
 352          */
 353         if (sev_es_guest(vcpu->kvm))
 354                 goto done;
 355
 356         if (nrips && svm->vmcb->control.next_rip != 0) {
 357                 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
 358                 svm->next_rip = svm->vmcb->control.next_rip;
 359         }
 360
 361         if (!svm->next_rip) {
 362                 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
 363                         return 0;
 364         } else {
 365                 kvm_rip_write(vcpu, svm->next_rip);
 366         }
 367
 368 done:
 369         svm_set_interrupt_shadow(vcpu, 0);
 370
 371         return 1;
 372 }
 373
 374 static void svm_queue_exception(struct kvm_vcpu *vcpu)
 375 {
 376         struct vcpu_svm *svm = to_svm(vcpu);
 377         unsigned nr = vcpu->arch.exception.nr;
 378         bool has_error_code = vcpu->arch.exception.has_error_code;
 379         u32 error_code = vcpu->arch.exception.error_code;
 380
 381         kvm_deliver_exception_payload(vcpu);
 382
 383         if (nr == BP_VECTOR && !nrips) {
 384                 unsigned long rip, old_rip = kvm_rip_read(vcpu);
 385
 386                 /*
 387                  * For guest debugging where we have to reinject #BP if some
 388                  * INT3 is guest-owned:
 389                  * Emulate nRIP by moving RIP forward. Will fail if injection
 390                  * raises a fault that is not intercepted. Still better than
 391                  * failing in all cases.
 392                  */
 393                 (void)skip_emulated_instruction(vcpu);
 394                 rip = kvm_rip_read(vcpu);
 395                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 396                 svm->int3_injected = rip - old_rip;
 397         }
 398
 399         svm->vmcb->control.event_inj = nr
 400                 | SVM_EVTINJ_VALID
 401                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 402                 | SVM_EVTINJ_TYPE_EXEPT;
 403         svm->vmcb->control.event_inj_err = error_code;
 404 }
 405
 406 static void svm_init_erratum_383(void)
 407 {
 408         u32 low, high;
 409         int err;
 410         u64 val;
 411
 412         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 413                 return;
 414
 415         /* Use _safe variants to not break nested virtualization */
 416         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 417         if (err)
 418                 return;
 419
 420         val |= (1ULL << 47);
 421
 422         low  = lower_32_bits(val);
 423         high = upper_32_bits(val);
 424
 425         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 426
 427         erratum_383_found = true;
 428 }
 429
 430 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 431 {
 432         /*
 433          * Guests should see errata 400 and 415 as fixed (assuming that
 434          * HLT and IO instructions are intercepted).
 435          */
 436         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 437         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 438
 439         /*
 440          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 441          * all osvw.status bits inside that length, including bit 0 (which is
 442          * reserved for erratum 298), are valid. However, if host processor's
 443          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 444          * be conservative here and therefore we tell the guest that erratum 298
 445          * is present (because we really don't know).
 446          */
 447         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 448                 vcpu->arch.osvw.status |= 1;
 449 }
 450
 451 static int has_svm(void)
 452 {
 453         const char *msg;
 454
 455         if (!cpu_has_svm(&msg)) {
 456                 printk(KERN_INFO "has_svm: %s\n", msg);
 457                 return 0;
 458         }
 459
 460         if (sev_active()) {
 461                 pr_info("KVM is unsupported when running as an SEV guest\n");
 462                 return 0;
 463         }
 464
 465         if (pgtable_l5_enabled()) {
 466                 pr_info("KVM doesn't yet support 5-level paging on AMD SVM\n");
 467                 return 0;
 468         }
 469
 470         return 1;
 471 }
 472
 473 static void svm_hardware_disable(void)
 474 {
 475         /* Make sure we clean up behind us */
 476         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 477                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 478
 479         cpu_svm_disable();
 480
 481         amd_pmu_disable_virt();
 482 }
 483
 484 static int svm_hardware_enable(void)
 485 {
 486
 487         struct svm_cpu_data *sd;
 488         uint64_t efer;
 489         struct desc_struct *gdt;
 490         int me = raw_smp_processor_id();
 491
 492         rdmsrl(MSR_EFER, efer);
 493         if (efer & EFER_SVME)
 494                 return -EBUSY;
 495
 496         if (!has_svm()) {
 497                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 498                 return -EINVAL;
 499         }
 500         sd = per_cpu(svm_data, me);
 501         if (!sd) {
 502                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 503                 return -EINVAL;
 504         }
 505
 506         sd->asid_generation = 1;
 507         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 508         sd->next_asid = sd->max_asid + 1;
 509         sd->min_asid = max_sev_asid + 1;
 510
 511         gdt = get_current_gdt_rw();
 512         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 513
 514         wrmsrl(MSR_EFER, efer | EFER_SVME);
 515
 516         wrmsrl(MSR_VM_HSAVE_PA, __sme_page_pa(sd->save_area));
 517
 518         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 519                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 520                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
 521         }
 522
 523
 524         /*
 525          * Get OSVW bits.
 526          *
 527          * Note that it is possible to have a system with mixed processor
 528          * revisions and therefore different OSVW bits. If bits are not the same
 529          * on different processors then choose the worst case (i.e. if erratum
 530          * is present on one processor and not on another then assume that the
 531          * erratum is present everywhere).
 532          */
 533         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 534                 uint64_t len, status = 0;
 535                 int err;
 536
 537                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 538                 if (!err)
 539                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 540                                                       &err);
 541
 542                 if (err)
 543                         osvw_status = osvw_len = 0;
 544                 else {
 545                         if (len < osvw_len)
 546                                 osvw_len = len;
 547                         osvw_status |= status;
 548                         osvw_status &= (1ULL << osvw_len) - 1;
 549                 }
 550         } else
 551                 osvw_status = osvw_len = 0;
 552
 553         svm_init_erratum_383();
 554
 555         amd_pmu_enable_virt();
 556
 557         return 0;
 558 }
 559
 560 static void svm_cpu_uninit(int cpu)
 561 {
 562         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
 563
 564         if (!sd)
 565                 return;
 566
 567         per_cpu(svm_data, cpu) = NULL;
 568         kfree(sd->sev_vmcbs);
 569         __free_page(sd->save_area);
 570         kfree(sd);
 571 }
 572
 573 static int svm_cpu_init(int cpu)
 574 {
 575         struct svm_cpu_data *sd;
 576         int ret = -ENOMEM;
 577
 578         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 579         if (!sd)
 580                 return ret;
 581         sd->cpu = cpu;
 582         sd->save_area = alloc_page(GFP_KERNEL);
 583         if (!sd->save_area)
 584                 goto free_cpu_data;
 585
 586         clear_page(page_address(sd->save_area));
 587
 588         ret = sev_cpu_init(sd);
 589         if (ret)
 590                 goto free_save_area;
 591
 592         per_cpu(svm_data, cpu) = sd;
 593
 594         return 0;
 595
 596 free_save_area:
 597         __free_page(sd->save_area);
 598 free_cpu_data:
 599         kfree(sd);
 600         return ret;
 601
 602 }
 603
 604 static int direct_access_msr_slot(u32 msr)
 605 {
 606         u32 i;
 607
 608         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 609                 if (direct_access_msrs[i].index == msr)
 610                         return i;
 611
 612         return -ENOENT;
 613 }
 614
 615 static void set_shadow_msr_intercept(struct kvm_vcpu *vcpu, u32 msr, int read,
 616                                      int write)
 617 {
 618         struct vcpu_svm *svm = to_svm(vcpu);
 619         int slot = direct_access_msr_slot(msr);
 620
 621         if (slot == -ENOENT)
 622                 return;
 623
 624         /* Set the shadow bitmaps to the desired intercept states */
 625         if (read)
 626                 set_bit(slot, svm->shadow_msr_intercept.read);
 627         else
 628                 clear_bit(slot, svm->shadow_msr_intercept.read);
 629
 630         if (write)
 631                 set_bit(slot, svm->shadow_msr_intercept.write);
 632         else
 633                 clear_bit(slot, svm->shadow_msr_intercept.write);
 634 }
 635
 636 static bool valid_msr_intercept(u32 index)
 637 {
 638         return direct_access_msr_slot(index) != -ENOENT;
 639 }
 640
 641 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
 642 {
 643         u8 bit_write;
 644         unsigned long tmp;
 645         u32 offset;
 646         u32 *msrpm;
 647
 648         msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
 649                                       to_svm(vcpu)->msrpm;
 650
 651         offset    = svm_msrpm_offset(msr);
 652         bit_write = 2 * (msr & 0x0f) + 1;
 653         tmp       = msrpm[offset];
 654
 655         BUG_ON(offset == MSR_INVALID);
 656
 657         return !!test_bit(bit_write,  &tmp);
 658 }
 659
 660 static void set_msr_interception_bitmap(struct kvm_vcpu *vcpu, u32 *msrpm,
 661                                         u32 msr, int read, int write)
 662 {
 663         u8 bit_read, bit_write;
 664         unsigned long tmp;
 665         u32 offset;
 666
 667         /*
 668          * If this warning triggers extend the direct_access_msrs list at the
 669          * beginning of the file
 670          */
 671         WARN_ON(!valid_msr_intercept(msr));
 672
 673         /* Enforce non allowed MSRs to trap */
 674         if (read && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ))
 675                 read = 0;
 676
 677         if (write && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE))
 678                 write = 0;
 679
 680         offset    = svm_msrpm_offset(msr);
 681         bit_read  = 2 * (msr & 0x0f);
 682         bit_write = 2 * (msr & 0x0f) + 1;
 683         tmp       = msrpm[offset];
 684
 685         BUG_ON(offset == MSR_INVALID);
 686
 687         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 688         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 689
 690         msrpm[offset] = tmp;
 691
 692         svm_hv_vmcb_dirty_nested_enlightenments(vcpu);
 693
 694 }
 695
 696 void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr,
 697                           int read, int write)
 698 {
 699         set_shadow_msr_intercept(vcpu, msr, read, write);
 700         set_msr_interception_bitmap(vcpu, msrpm, msr, read, write);
 701 }
 702
 703 u32 *svm_vcpu_alloc_msrpm(void)
 704 {
 705         unsigned int order = get_order(MSRPM_SIZE);
 706         struct page *pages = alloc_pages(GFP_KERNEL_ACCOUNT, order);
 707         u32 *msrpm;
 708
 709         if (!pages)
 710                 return NULL;
 711
 712         msrpm = page_address(pages);
 713         memset(msrpm, 0xff, PAGE_SIZE * (1 << order));
 714
 715         return msrpm;
 716 }
 717
 718 void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm)
 719 {
 720         int i;
 721
 722         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 723                 if (!direct_access_msrs[i].always)
 724                         continue;
 725                 set_msr_interception(vcpu, msrpm, direct_access_msrs[i].index, 1, 1);
 726         }
 727 }
 728
 729
 730 void svm_vcpu_free_msrpm(u32 *msrpm)
 731 {
 732         __free_pages(virt_to_page(msrpm), get_order(MSRPM_SIZE));
 733 }
 734
 735 static void svm_msr_filter_changed(struct kvm_vcpu *vcpu)
 736 {
 737         struct vcpu_svm *svm = to_svm(vcpu);
 738         u32 i;
 739
 740         /*
 741          * Set intercept permissions for all direct access MSRs again. They
 742          * will automatically get filtered through the MSR filter, so we are
 743          * back in sync after this.
 744          */
 745         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 746                 u32 msr = direct_access_msrs[i].index;
 747                 u32 read = test_bit(i, svm->shadow_msr_intercept.read);
 748                 u32 write = test_bit(i, svm->shadow_msr_intercept.write);
 749
 750                 set_msr_interception_bitmap(vcpu, svm->msrpm, msr, read, write);
 751         }
 752 }
 753
 754 static void add_msr_offset(u32 offset)
 755 {
 756         int i;
 757
 758         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 759
 760                 /* Offset already in list? */
 761                 if (msrpm_offsets[i] == offset)
 762                         return;
 763
 764                 /* Slot used by another offset? */
 765                 if (msrpm_offsets[i] != MSR_INVALID)
 766                         continue;
 767
 768                 /* Add offset to list */
 769                 msrpm_offsets[i] = offset;
 770
 771                 return;
 772         }
 773
 774         /*
 775          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 776          * increase MSRPM_OFFSETS in this case.
 777          */
 778         BUG();
 779 }
 780
 781 static void init_msrpm_offsets(void)
 782 {
 783         int i;
 784
 785         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 786
 787         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 788                 u32 offset;
 789
 790                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 791                 BUG_ON(offset == MSR_INVALID);
 792
 793                 add_msr_offset(offset);
 794         }
 795 }
 796
 797 static void svm_enable_lbrv(struct kvm_vcpu *vcpu)
 798 {
 799         struct vcpu_svm *svm = to_svm(vcpu);
 800
 801         svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
 802         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 803         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 804         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 805         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 806 }
 807
 808 static void svm_disable_lbrv(struct kvm_vcpu *vcpu)
 809 {
 810         struct vcpu_svm *svm = to_svm(vcpu);
 811
 812         svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
 813         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 814         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 815         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 816         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 817 }
 818
 819 void disable_nmi_singlestep(struct vcpu_svm *svm)
 820 {
 821         svm->nmi_singlestep = false;
 822
 823         if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
 824                 /* Clear our flags if they were not set by the guest */
 825                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
 826                         svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
 827                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
 828                         svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
 829         }
 830 }
 831
 832 static void grow_ple_window(struct kvm_vcpu *vcpu)
 833 {
 834         struct vcpu_svm *svm = to_svm(vcpu);
 835         struct vmcb_control_area *control = &svm->vmcb->control;
 836         int old = control->pause_filter_count;
 837
 838         control->pause_filter_count = __grow_ple_window(old,
 839                                                         pause_filter_count,
 840                                                         pause_filter_count_grow,
 841                                                         pause_filter_count_max);
 842
 843         if (control->pause_filter_count != old) {
 844                 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 845                 trace_kvm_ple_window_update(vcpu->vcpu_id,
 846                                             control->pause_filter_count, old);
 847         }
 848 }
 849
 850 static void shrink_ple_window(struct kvm_vcpu *vcpu)
 851 {
 852         struct vcpu_svm *svm = to_svm(vcpu);
 853         struct vmcb_control_area *control = &svm->vmcb->control;
 854         int old = control->pause_filter_count;
 855
 856         control->pause_filter_count =
 857                                 __shrink_ple_window(old,
 858                                                     pause_filter_count,
 859                                                     pause_filter_count_shrink,
 860                                                     pause_filter_count);
 861         if (control->pause_filter_count != old) {
 862                 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 863                 trace_kvm_ple_window_update(vcpu->vcpu_id,
 864                                             control->pause_filter_count, old);
 865         }
 866 }
 867
 868 /*
 869  * The default MMIO mask is a single bit (excluding the present bit),
 870  * which could conflict with the memory encryption bit. Check for
 871  * memory encryption support and override the default MMIO mask if
 872  * memory encryption is enabled.
 873  */
 874 static __init void svm_adjust_mmio_mask(void)
 875 {
 876         unsigned int enc_bit, mask_bit;
 877         u64 msr, mask;
 878
 879         /* If there is no memory encryption support, use existing mask */
 880         if (cpuid_eax(0x80000000) < 0x8000001f)
 881                 return;
 882
 883         /* If memory encryption is not enabled, use existing mask */
 884         rdmsrl(MSR_AMD64_SYSCFG, msr);
 885         if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT))
 886                 return;
 887
 888         enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
 889         mask_bit = boot_cpu_data.x86_phys_bits;
 890
 891         /* Increment the mask bit if it is the same as the encryption bit */
 892         if (enc_bit == mask_bit)
 893                 mask_bit++;
 894
 895         /*
 896          * If the mask bit location is below 52, then some bits above the
 897          * physical addressing limit will always be reserved, so use the
 898          * rsvd_bits() function to generate the mask. This mask, along with
 899          * the present bit, will be used to generate a page fault with
 900          * PFER.RSV = 1.
 901          *
 902          * If the mask bit location is 52 (or above), then clear the mask.
 903          */
 904         mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
 905
 906         kvm_mmu_set_mmio_spte_mask(mask, mask, PT_WRITABLE_MASK | PT_USER_MASK);
 907 }
 908
 909 static void svm_hardware_teardown(void)
 910 {
 911         int cpu;
 912
 913         sev_hardware_teardown();
 914
 915         for_each_possible_cpu(cpu)
 916                 svm_cpu_uninit(cpu);
 917
 918         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT),
 919         get_order(IOPM_SIZE));
 920         iopm_base = 0;
 921 }
 922
 923 static __init void svm_set_cpu_caps(void)
 924 {
 925         kvm_set_cpu_caps();
 926
 927         supported_xss = 0;
 928
 929         /* CPUID 0x80000001 and 0x8000000A (SVM features) */
 930         if (nested) {
 931                 kvm_cpu_cap_set(X86_FEATURE_SVM);
 932
 933                 if (nrips)
 934                         kvm_cpu_cap_set(X86_FEATURE_NRIPS);
 935
 936                 if (npt_enabled)
 937                         kvm_cpu_cap_set(X86_FEATURE_NPT);
 938
 939                 /* Nested VM can receive #VMEXIT instead of triggering #GP */
 940                 kvm_cpu_cap_set(X86_FEATURE_SVME_ADDR_CHK);
 941         }
 942
 943         /* CPUID 0x80000008 */
 944         if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
 945             boot_cpu_has(X86_FEATURE_AMD_SSBD))
 946                 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
 947
 948         /* CPUID 0x8000001F (SME/SEV features) */
 949         sev_set_cpu_caps();
 950 }
 951
 952 static __init int svm_hardware_setup(void)
 953 {
 954         int cpu;
 955         struct page *iopm_pages;
 956         void *iopm_va;
 957         int r;
 958         unsigned int order = get_order(IOPM_SIZE);
 959
 960         /*
 961          * NX is required for shadow paging and for NPT if the NX huge pages
 962          * mitigation is enabled.
 963          */
 964         if (!boot_cpu_has(X86_FEATURE_NX)) {
 965                 pr_err_ratelimited("NX (Execute Disable) not supported\n");
 966                 return -EOPNOTSUPP;
 967         }
 968         kvm_enable_efer_bits(EFER_NX);
 969
 970         iopm_pages = alloc_pages(GFP_KERNEL, order);
 971
 972         if (!iopm_pages)
 973                 return -ENOMEM;
 974
 975         iopm_va = page_address(iopm_pages);
 976         memset(iopm_va, 0xff, PAGE_SIZE * (1 << order));
 977         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 978
 979         init_msrpm_offsets();
 980
 981         supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
 982
 983         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 984                 kvm_enable_efer_bits(EFER_FFXSR);
 985
 986         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 987                 kvm_has_tsc_control = true;
 988                 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
 989                 kvm_tsc_scaling_ratio_frac_bits = 32;
 990         }
 991
 992         tsc_aux_uret_slot = kvm_add_user_return_msr(MSR_TSC_AUX);
 993
 994         /* Check for pause filtering support */
 995         if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
 996                 pause_filter_count = 0;
 997                 pause_filter_thresh = 0;
 998         } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
 999                 pause_filter_thresh = 0;
1000         }
1001
1002         if (nested) {
1003                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1004                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1005         }
1006
1007         /*
1008          * KVM's MMU doesn't support using 2-level paging for itself, and thus
1009          * NPT isn't supported if the host is using 2-level paging since host
1010          * CR4 is unchanged on VMRUN.
1011          */
1012         if (!IS_ENABLED(CONFIG_X86_64) && !IS_ENABLED(CONFIG_X86_PAE))
1013                 npt_enabled = false;
1014
1015         if (!boot_cpu_has(X86_FEATURE_NPT))
1016                 npt_enabled = false;
1017
1018         kvm_configure_mmu(npt_enabled, get_max_npt_level(), PG_LEVEL_1G);
1019         pr_info("kvm: Nested Paging %sabled\n", npt_enabled ? "en" : "dis");
1020
1021         /* Note, SEV setup consumes npt_enabled. */
1022         sev_hardware_setup();
1023
1024         svm_hv_hardware_setup();
1025
1026         svm_adjust_mmio_mask();
1027
1028         for_each_possible_cpu(cpu) {
1029                 r = svm_cpu_init(cpu);
1030                 if (r)
1031                         goto err;
1032         }
1033
1034         if (nrips) {
1035                 if (!boot_cpu_has(X86_FEATURE_NRIPS))
1036                         nrips = false;
1037         }
1038
1039         enable_apicv = avic = avic && npt_enabled && boot_cpu_has(X86_FEATURE_AVIC);
1040
1041         if (enable_apicv) {
1042                 pr_info("AVIC enabled\n");
1043
1044                 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1045         }
1046
1047         if (vls) {
1048                 if (!npt_enabled ||
1049                     !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1050                     !IS_ENABLED(CONFIG_X86_64)) {
1051                         vls = false;
1052                 } else {
1053                         pr_info("Virtual VMLOAD VMSAVE supported\n");
1054                 }
1055         }
1056
1057         if (boot_cpu_has(X86_FEATURE_SVME_ADDR_CHK))
1058                 svm_gp_erratum_intercept = false;
1059
1060         if (vgif) {
1061                 if (!boot_cpu_has(X86_FEATURE_VGIF))
1062                         vgif = false;
1063                 else
1064                         pr_info("Virtual GIF supported\n");
1065         }
1066
1067         svm_set_cpu_caps();
1068
1069         /*
1070          * It seems that on AMD processors PTE's accessed bit is
1071          * being set by the CPU hardware before the NPF vmexit.
1072          * This is not expected behaviour and our tests fail because
1073          * of it.
1074          * A workaround here is to disable support for
1075          * GUEST_MAXPHYADDR < HOST_MAXPHYADDR if NPT is enabled.
1076          * In this case userspace can know if there is support using
1077          * KVM_CAP_SMALLER_MAXPHYADDR extension and decide how to handle
1078          * it
1079          * If future AMD CPU models change the behaviour described above,
1080          * this variable can be changed accordingly
1081          */
1082         allow_smaller_maxphyaddr = !npt_enabled;
1083
1084         return 0;
1085
1086 err:
1087         svm_hardware_teardown();
1088         return r;
1089 }
1090
1091 static void init_seg(struct vmcb_seg *seg)
1092 {
1093         seg->selector = 0;
1094         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1095                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1096         seg->limit = 0xffff;
1097         seg->base = 0;
1098 }
1099
1100 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1101 {
1102         seg->selector = 0;
1103         seg->attrib = SVM_SELECTOR_P_MASK | type;
1104         seg->limit = 0xffff;
1105         seg->base = 0;
1106 }
1107
1108 static u64 svm_get_l2_tsc_offset(struct kvm_vcpu *vcpu)
1109 {
1110         struct vcpu_svm *svm = to_svm(vcpu);
1111
1112         return svm->nested.ctl.tsc_offset;
1113 }
1114
1115 static u64 svm_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu)
1116 {
1117         return kvm_default_tsc_scaling_ratio;
1118 }
1119
1120 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1121 {
1122         struct vcpu_svm *svm = to_svm(vcpu);
1123
1124         svm->vmcb01.ptr->control.tsc_offset = vcpu->arch.l1_tsc_offset;
1125         svm->vmcb->control.tsc_offset = offset;
1126         vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1127 }
1128
1129 static void svm_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 multiplier)
1130 {
1131         wrmsrl(MSR_AMD64_TSC_RATIO, multiplier);
1132 }
1133
1134 /* Evaluate instruction intercepts that depend on guest CPUID features. */
1135 static void svm_recalc_instruction_intercepts(struct kvm_vcpu *vcpu,
1136                                               struct vcpu_svm *svm)
1137 {
1138         /*
1139          * Intercept INVPCID if shadow paging is enabled to sync/free shadow
1140          * roots, or if INVPCID is disabled in the guest to inject #UD.
1141          */
1142         if (kvm_cpu_cap_has(X86_FEATURE_INVPCID)) {
1143                 if (!npt_enabled ||
1144                     !guest_cpuid_has(&svm->vcpu, X86_FEATURE_INVPCID))
1145                         svm_set_intercept(svm, INTERCEPT_INVPCID);
1146                 else
1147                         svm_clr_intercept(svm, INTERCEPT_INVPCID);
1148         }
1149
1150         if (kvm_cpu_cap_has(X86_FEATURE_RDTSCP)) {
1151                 if (guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
1152                         svm_clr_intercept(svm, INTERCEPT_RDTSCP);
1153                 else
1154                         svm_set_intercept(svm, INTERCEPT_RDTSCP);
1155         }
1156 }
1157
1158 static void init_vmcb(struct kvm_vcpu *vcpu)
1159 {
1160         struct vcpu_svm *svm = to_svm(vcpu);
1161         struct vmcb_control_area *control = &svm->vmcb->control;
1162         struct vmcb_save_area *save = &svm->vmcb->save;
1163
1164         vcpu->arch.hflags = 0;
1165
1166         svm_set_intercept(svm, INTERCEPT_CR0_READ);
1167         svm_set_intercept(svm, INTERCEPT_CR3_READ);
1168         svm_set_intercept(svm, INTERCEPT_CR4_READ);
1169         svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1170         svm_set_intercept(svm, INTERCEPT_CR3_WRITE);
1171         svm_set_intercept(svm, INTERCEPT_CR4_WRITE);
1172         if (!kvm_vcpu_apicv_active(vcpu))
1173                 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
1174
1175         set_dr_intercepts(svm);
1176
1177         set_exception_intercept(svm, PF_VECTOR);
1178         set_exception_intercept(svm, UD_VECTOR);
1179         set_exception_intercept(svm, MC_VECTOR);
1180         set_exception_intercept(svm, AC_VECTOR);
1181         set_exception_intercept(svm, DB_VECTOR);
1182         /*
1183          * Guest access to VMware backdoor ports could legitimately
1184          * trigger #GP because of TSS I/O permission bitmap.
1185          * We intercept those #GP and allow access to them anyway
1186          * as VMware does.
1187          */
1188         if (enable_vmware_backdoor)
1189                 set_exception_intercept(svm, GP_VECTOR);
1190
1191         svm_set_intercept(svm, INTERCEPT_INTR);
1192         svm_set_intercept(svm, INTERCEPT_NMI);
1193
1194         if (intercept_smi)
1195                 svm_set_intercept(svm, INTERCEPT_SMI);
1196
1197         svm_set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1198         svm_set_intercept(svm, INTERCEPT_RDPMC);
1199         svm_set_intercept(svm, INTERCEPT_CPUID);
1200         svm_set_intercept(svm, INTERCEPT_INVD);
1201         svm_set_intercept(svm, INTERCEPT_INVLPG);
1202         svm_set_intercept(svm, INTERCEPT_INVLPGA);
1203         svm_set_intercept(svm, INTERCEPT_IOIO_PROT);
1204         svm_set_intercept(svm, INTERCEPT_MSR_PROT);
1205         svm_set_intercept(svm, INTERCEPT_TASK_SWITCH);
1206         svm_set_intercept(svm, INTERCEPT_SHUTDOWN);
1207         svm_set_intercept(svm, INTERCEPT_VMRUN);
1208         svm_set_intercept(svm, INTERCEPT_VMMCALL);
1209         svm_set_intercept(svm, INTERCEPT_VMLOAD);
1210         svm_set_intercept(svm, INTERCEPT_VMSAVE);
1211         svm_set_intercept(svm, INTERCEPT_STGI);
1212         svm_set_intercept(svm, INTERCEPT_CLGI);
1213         svm_set_intercept(svm, INTERCEPT_SKINIT);
1214         svm_set_intercept(svm, INTERCEPT_WBINVD);
1215         svm_set_intercept(svm, INTERCEPT_XSETBV);
1216         svm_set_intercept(svm, INTERCEPT_RDPRU);
1217         svm_set_intercept(svm, INTERCEPT_RSM);
1218
1219         if (!kvm_mwait_in_guest(vcpu->kvm)) {
1220                 svm_set_intercept(svm, INTERCEPT_MONITOR);
1221                 svm_set_intercept(svm, INTERCEPT_MWAIT);
1222         }
1223
1224         if (!kvm_hlt_in_guest(vcpu->kvm))
1225                 svm_set_intercept(svm, INTERCEPT_HLT);
1226
1227         control->iopm_base_pa = __sme_set(iopm_base);
1228         control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1229         control->int_ctl = V_INTR_MASKING_MASK;
1230
1231         init_seg(&save->es);
1232         init_seg(&save->ss);
1233         init_seg(&save->ds);
1234         init_seg(&save->fs);
1235         init_seg(&save->gs);
1236
1237         save->cs.selector = 0xf000;
1238         save->cs.base = 0xffff0000;
1239         /* Executable/Readable Code Segment */
1240         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1241                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1242         save->cs.limit = 0xffff;
1243
1244         save->gdtr.limit = 0xffff;
1245         save->idtr.limit = 0xffff;
1246
1247         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1248         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1249
1250         svm_set_cr4(vcpu, 0);
1251         svm_set_efer(vcpu, 0);
1252         save->dr6 = 0xffff0ff0;
1253         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
1254         save->rip = 0x0000fff0;
1255         vcpu->arch.regs[VCPU_REGS_RIP] = save->rip;
1256
1257         /*
1258          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1259          * It also updates the guest-visible cr0 value.
1260          */
1261         svm_set_cr0(vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1262         kvm_mmu_reset_context(vcpu);
1263
1264         save->cr4 = X86_CR4_PAE;
1265         /* rdx = ?? */
1266
1267         if (npt_enabled) {
1268                 /* Setup VMCB for Nested Paging */
1269                 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1270                 svm_clr_intercept(svm, INTERCEPT_INVLPG);
1271                 clr_exception_intercept(svm, PF_VECTOR);
1272                 svm_clr_intercept(svm, INTERCEPT_CR3_READ);
1273                 svm_clr_intercept(svm, INTERCEPT_CR3_WRITE);
1274                 save->g_pat = vcpu->arch.pat;
1275                 save->cr3 = 0;
1276                 save->cr4 = 0;
1277         }
1278         svm->current_vmcb->asid_generation = 0;
1279         svm->asid = 0;
1280
1281         svm->nested.vmcb12_gpa = INVALID_GPA;
1282         svm->nested.last_vmcb12_gpa = INVALID_GPA;
1283         vcpu->arch.hflags = 0;
1284
1285         if (!kvm_pause_in_guest(vcpu->kvm)) {
1286                 control->pause_filter_count = pause_filter_count;
1287                 if (pause_filter_thresh)
1288                         control->pause_filter_thresh = pause_filter_thresh;
1289                 svm_set_intercept(svm, INTERCEPT_PAUSE);
1290         } else {
1291                 svm_clr_intercept(svm, INTERCEPT_PAUSE);
1292         }
1293
1294         svm_recalc_instruction_intercepts(vcpu, svm);
1295
1296         /*
1297          * If the host supports V_SPEC_CTRL then disable the interception
1298          * of MSR_IA32_SPEC_CTRL.
1299          */
1300         if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL))
1301                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
1302
1303         if (kvm_vcpu_apicv_active(vcpu))
1304                 avic_init_vmcb(svm);
1305
1306         if (vgif) {
1307                 svm_clr_intercept(svm, INTERCEPT_STGI);
1308                 svm_clr_intercept(svm, INTERCEPT_CLGI);
1309                 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1310         }
1311
1312         if (sev_guest(vcpu->kvm)) {
1313                 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1314                 clr_exception_intercept(svm, UD_VECTOR);
1315
1316                 if (sev_es_guest(vcpu->kvm)) {
1317                         /* Perform SEV-ES specific VMCB updates */
1318                         sev_es_init_vmcb(svm);
1319                 }
1320         }
1321
1322         svm_hv_init_vmcb(svm->vmcb);
1323
1324         vmcb_mark_all_dirty(svm->vmcb);
1325
1326         enable_gif(svm);
1327
1328 }
1329
1330 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1331 {
1332         struct vcpu_svm *svm = to_svm(vcpu);
1333         u32 dummy;
1334         u32 eax = 1;
1335
1336         svm->spec_ctrl = 0;
1337         svm->virt_spec_ctrl = 0;
1338
1339         if (!init_event) {
1340                 vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1341                                        MSR_IA32_APICBASE_ENABLE;
1342                 if (kvm_vcpu_is_reset_bsp(vcpu))
1343                         vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
1344         }
1345         init_vmcb(vcpu);
1346
1347         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, false);
1348         kvm_rdx_write(vcpu, eax);
1349
1350         if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1351                 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1352 }
1353
1354 void svm_switch_vmcb(struct vcpu_svm *svm, struct kvm_vmcb_info *target_vmcb)
1355 {
1356         svm->current_vmcb = target_vmcb;
1357         svm->vmcb = target_vmcb->ptr;
1358 }
1359
1360 static int svm_create_vcpu(struct kvm_vcpu *vcpu)
1361 {
1362         struct vcpu_svm *svm;
1363         struct page *vmcb01_page;
1364         struct page *vmsa_page = NULL;
1365         int err;
1366
1367         BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0);
1368         svm = to_svm(vcpu);
1369
1370         err = -ENOMEM;
1371         vmcb01_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1372         if (!vmcb01_page)
1373                 goto out;
1374
1375         if (sev_es_guest(vcpu->kvm)) {
1376                 /*
1377                  * SEV-ES guests require a separate VMSA page used to contain
1378                  * the encrypted register state of the guest.
1379                  */
1380                 vmsa_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1381                 if (!vmsa_page)
1382                         goto error_free_vmcb_page;
1383
1384                 /*
1385                  * SEV-ES guests maintain an encrypted version of their FPU
1386                  * state which is restored and saved on VMRUN and VMEXIT.
1387                  * Free the fpu structure to prevent KVM from attempting to
1388                  * access the FPU state.
1389                  */
1390                 kvm_free_guest_fpu(vcpu);
1391         }
1392
1393         err = avic_init_vcpu(svm);
1394         if (err)
1395                 goto error_free_vmsa_page;
1396
1397         /* We initialize this flag to true to make sure that the is_running
1398          * bit would be set the first time the vcpu is loaded.
1399          */
1400         if (irqchip_in_kernel(vcpu->kvm) && kvm_apicv_activated(vcpu->kvm))
1401                 svm->avic_is_running = true;
1402
1403         svm->msrpm = svm_vcpu_alloc_msrpm();
1404         if (!svm->msrpm) {
1405                 err = -ENOMEM;
1406                 goto error_free_vmsa_page;
1407         }
1408
1409         svm_vcpu_init_msrpm(vcpu, svm->msrpm);
1410
1411         svm->vmcb01.ptr = page_address(vmcb01_page);
1412         svm->vmcb01.pa = __sme_set(page_to_pfn(vmcb01_page) << PAGE_SHIFT);
1413
1414         if (vmsa_page)
1415                 svm->vmsa = page_address(vmsa_page);
1416
1417         svm->guest_state_loaded = false;
1418
1419         svm_switch_vmcb(svm, &svm->vmcb01);
1420         init_vmcb(vcpu);
1421
1422         svm_init_osvw(vcpu);
1423         vcpu->arch.microcode_version = 0x01000065;
1424
1425         if (sev_es_guest(vcpu->kvm))
1426                 /* Perform SEV-ES specific VMCB creation updates */
1427                 sev_es_create_vcpu(svm);
1428
1429         return 0;
1430
1431 error_free_vmsa_page:
1432         if (vmsa_page)
1433                 __free_page(vmsa_page);
1434 error_free_vmcb_page:
1435         __free_page(vmcb01_page);
1436 out:
1437         return err;
1438 }
1439
1440 static void svm_clear_current_vmcb(struct vmcb *vmcb)
1441 {
1442         int i;
1443
1444         for_each_online_cpu(i)
1445                 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
1446 }
1447
1448 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1449 {
1450         struct vcpu_svm *svm = to_svm(vcpu);
1451
1452         /*
1453          * The vmcb page can be recycled, causing a false negative in
1454          * svm_vcpu_load(). So, ensure that no logical CPU has this
1455          * vmcb page recorded as its current vmcb.
1456          */
1457         svm_clear_current_vmcb(svm->vmcb);
1458
1459         svm_free_nested(svm);
1460
1461         sev_free_vcpu(vcpu);
1462
1463         __free_page(pfn_to_page(__sme_clr(svm->vmcb01.pa) >> PAGE_SHIFT));
1464         __free_pages(virt_to_page(svm->msrpm), get_order(MSRPM_SIZE));
1465 }
1466
1467 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
1468 {
1469         struct vcpu_svm *svm = to_svm(vcpu);
1470         struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
1471
1472         if (sev_es_guest(vcpu->kvm))
1473                 sev_es_unmap_ghcb(svm);
1474
1475         if (svm->guest_state_loaded)
1476                 return;
1477
1478         /*
1479          * Save additional host state that will be restored on VMEXIT (sev-es)
1480          * or subsequent vmload of host save area.
1481          */
1482         if (sev_es_guest(vcpu->kvm)) {
1483                 sev_es_prepare_guest_switch(svm, vcpu->cpu);
1484         } else {
1485                 vmsave(__sme_page_pa(sd->save_area));
1486         }
1487
1488         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1489                 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1490                 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1491                         __this_cpu_write(current_tsc_ratio, tsc_ratio);
1492                         wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1493                 }
1494         }
1495
1496         if (likely(tsc_aux_uret_slot >= 0))
1497                 kvm_set_user_return_msr(tsc_aux_uret_slot, svm->tsc_aux, -1ull);
1498
1499         svm->guest_state_loaded = true;
1500 }
1501
1502 static void svm_prepare_host_switch(struct kvm_vcpu *vcpu)
1503 {
1504         to_svm(vcpu)->guest_state_loaded = false;
1505 }
1506
1507 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1508 {
1509         struct vcpu_svm *svm = to_svm(vcpu);
1510         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
1511
1512         if (sd->current_vmcb != svm->vmcb) {
1513                 sd->current_vmcb = svm->vmcb;
1514                 indirect_branch_prediction_barrier();
1515         }
1516         avic_vcpu_load(vcpu, cpu);
1517 }
1518
1519 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1520 {
1521         avic_vcpu_put(vcpu);
1522         svm_prepare_host_switch(vcpu);
1523
1524         ++vcpu->stat.host_state_reload;
1525 }
1526
1527 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1528 {
1529         struct vcpu_svm *svm = to_svm(vcpu);
1530         unsigned long rflags = svm->vmcb->save.rflags;
1531
1532         if (svm->nmi_singlestep) {
1533                 /* Hide our flags if they were not set by the guest */
1534                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1535                         rflags &= ~X86_EFLAGS_TF;
1536                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1537                         rflags &= ~X86_EFLAGS_RF;
1538         }
1539         return rflags;
1540 }
1541
1542 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1543 {
1544         if (to_svm(vcpu)->nmi_singlestep)
1545                 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1546
1547        /*
1548         * Any change of EFLAGS.VM is accompanied by a reload of SS
1549         * (caused by either a task switch or an inter-privilege IRET),
1550         * so we do not need to update the CPL here.
1551         */
1552         to_svm(vcpu)->vmcb->save.rflags = rflags;
1553 }
1554
1555 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1556 {
1557         switch (reg) {
1558         case VCPU_EXREG_PDPTR:
1559                 BUG_ON(!npt_enabled);
1560                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1561                 break;
1562         default:
1563                 WARN_ON_ONCE(1);
1564         }
1565 }
1566
1567 static void svm_set_vintr(struct vcpu_svm *svm)
1568 {
1569         struct vmcb_control_area *control;
1570
1571         /* The following fields are ignored when AVIC is enabled */
1572         WARN_ON(kvm_vcpu_apicv_active(&svm->vcpu));
1573         svm_set_intercept(svm, INTERCEPT_VINTR);
1574
1575         /*
1576          * This is just a dummy VINTR to actually cause a vmexit to happen.
1577          * Actual injection of virtual interrupts happens through EVENTINJ.
1578          */
1579         control = &svm->vmcb->control;
1580         control->int_vector = 0x0;
1581         control->int_ctl &= ~V_INTR_PRIO_MASK;
1582         control->int_ctl |= V_IRQ_MASK |
1583                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1584         vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1585 }
1586
1587 static void svm_clear_vintr(struct vcpu_svm *svm)
1588 {
1589         const u32 mask = V_TPR_MASK | V_GIF_ENABLE_MASK | V_GIF_MASK | V_INTR_MASKING_MASK;
1590         svm_clr_intercept(svm, INTERCEPT_VINTR);
1591
1592         /* Drop int_ctl fields related to VINTR injection.  */
1593         svm->vmcb->control.int_ctl &= mask;
1594         if (is_guest_mode(&svm->vcpu)) {
1595                 svm->vmcb01.ptr->control.int_ctl &= mask;
1596
1597                 WARN_ON((svm->vmcb->control.int_ctl & V_TPR_MASK) !=
1598                         (svm->nested.ctl.int_ctl & V_TPR_MASK));
1599                 svm->vmcb->control.int_ctl |= svm->nested.ctl.int_ctl & ~mask;
1600         }
1601
1602         vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1603 }
1604
1605 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1606 {
1607         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1608         struct vmcb_save_area *save01 = &to_svm(vcpu)->vmcb01.ptr->save;
1609
1610         switch (seg) {
1611         case VCPU_SREG_CS: return &save->cs;
1612         case VCPU_SREG_DS: return &save->ds;
1613         case VCPU_SREG_ES: return &save->es;
1614         case VCPU_SREG_FS: return &save01->fs;
1615         case VCPU_SREG_GS: return &save01->gs;
1616         case VCPU_SREG_SS: return &save->ss;
1617         case VCPU_SREG_TR: return &save01->tr;
1618         case VCPU_SREG_LDTR: return &save01->ldtr;
1619         }
1620         BUG();
1621         return NULL;
1622 }
1623
1624 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1625 {
1626         struct vmcb_seg *s = svm_seg(vcpu, seg);
1627
1628         return s->base;
1629 }
1630
1631 static void svm_get_segment(struct kvm_vcpu *vcpu,
1632                             struct kvm_segment *var, int seg)
1633 {
1634         struct vmcb_seg *s = svm_seg(vcpu, seg);
1635
1636         var->base = s->base;
1637         var->limit = s->limit;
1638         var->selector = s->selector;
1639         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1640         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1641         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1642         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1643         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1644         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1645         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1646
1647         /*
1648          * AMD CPUs circa 2014 track the G bit for all segments except CS.
1649          * However, the SVM spec states that the G bit is not observed by the
1650          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1651          * So let's synthesize a legal G bit for all segments, this helps
1652          * running KVM nested. It also helps cross-vendor migration, because
1653          * Intel's vmentry has a check on the 'G' bit.
1654          */
1655         var->g = s->limit > 0xfffff;
1656
1657         /*
1658          * AMD's VMCB does not have an explicit unusable field, so emulate it
1659          * for cross vendor migration purposes by "not present"
1660          */
1661         var->unusable = !var->present;
1662
1663         switch (seg) {
1664         case VCPU_SREG_TR:
1665                 /*
1666                  * Work around a bug where the busy flag in the tr selector
1667                  * isn't exposed
1668                  */
1669                 var->type |= 0x2;
1670                 break;
1671         case VCPU_SREG_DS:
1672         case VCPU_SREG_ES:
1673         case VCPU_SREG_FS:
1674         case VCPU_SREG_GS:
1675                 /*
1676                  * The accessed bit must always be set in the segment
1677                  * descriptor cache, although it can be cleared in the
1678                  * descriptor, the cached bit always remains at 1. Since
1679                  * Intel has a check on this, set it here to support
1680                  * cross-vendor migration.
1681                  */
1682                 if (!var->unusable)
1683                         var->type |= 0x1;
1684                 break;
1685         case VCPU_SREG_SS:
1686                 /*
1687                  * On AMD CPUs sometimes the DB bit in the segment
1688                  * descriptor is left as 1, although the whole segment has
1689                  * been made unusable. Clear it here to pass an Intel VMX
1690                  * entry check when cross vendor migrating.
1691                  */
1692                 if (var->unusable)
1693                         var->db = 0;
1694                 /* This is symmetric with svm_set_segment() */
1695                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1696                 break;
1697         }
1698 }
1699
1700 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1701 {
1702         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1703
1704         return save->cpl;
1705 }
1706
1707 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1708 {
1709         struct vcpu_svm *svm = to_svm(vcpu);
1710
1711         dt->size = svm->vmcb->save.idtr.limit;
1712         dt->address = svm->vmcb->save.idtr.base;
1713 }
1714
1715 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1716 {
1717         struct vcpu_svm *svm = to_svm(vcpu);
1718
1719         svm->vmcb->save.idtr.limit = dt->size;
1720         svm->vmcb->save.idtr.base = dt->address ;
1721         vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1722 }
1723
1724 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1725 {
1726         struct vcpu_svm *svm = to_svm(vcpu);
1727
1728         dt->size = svm->vmcb->save.gdtr.limit;
1729         dt->address = svm->vmcb->save.gdtr.base;
1730 }
1731
1732 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1733 {
1734         struct vcpu_svm *svm = to_svm(vcpu);
1735
1736         svm->vmcb->save.gdtr.limit = dt->size;
1737         svm->vmcb->save.gdtr.base = dt->address ;
1738         vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1739 }
1740
1741 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1742 {
1743         struct vcpu_svm *svm = to_svm(vcpu);
1744         u64 hcr0 = cr0;
1745
1746 #ifdef CONFIG_X86_64
1747         if (vcpu->arch.efer & EFER_LME && !vcpu->arch.guest_state_protected) {
1748                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1749                         vcpu->arch.efer |= EFER_LMA;
1750                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1751                 }
1752
1753                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1754                         vcpu->arch.efer &= ~EFER_LMA;
1755                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1756                 }
1757         }
1758 #endif
1759         vcpu->arch.cr0 = cr0;
1760
1761         if (!npt_enabled)
1762                 hcr0 |= X86_CR0_PG | X86_CR0_WP;
1763
1764         /*
1765          * re-enable caching here because the QEMU bios
1766          * does not do it - this results in some delay at
1767          * reboot
1768          */
1769         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1770                 hcr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1771
1772         svm->vmcb->save.cr0 = hcr0;
1773         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1774
1775         /*
1776          * SEV-ES guests must always keep the CR intercepts cleared. CR
1777          * tracking is done using the CR write traps.
1778          */
1779         if (sev_es_guest(vcpu->kvm))
1780                 return;
1781
1782         if (hcr0 == cr0) {
1783                 /* Selective CR0 write remains on.  */
1784                 svm_clr_intercept(svm, INTERCEPT_CR0_READ);
1785                 svm_clr_intercept(svm, INTERCEPT_CR0_WRITE);
1786         } else {
1787                 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1788                 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1789         }
1790 }
1791
1792 static bool svm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1793 {
1794         return true;
1795 }
1796
1797 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1798 {
1799         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1800         unsigned long old_cr4 = vcpu->arch.cr4;
1801
1802         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1803                 svm_flush_tlb(vcpu);
1804
1805         vcpu->arch.cr4 = cr4;
1806         if (!npt_enabled)
1807                 cr4 |= X86_CR4_PAE;
1808         cr4 |= host_cr4_mce;
1809         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1810         vmcb_mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1811
1812         if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
1813                 kvm_update_cpuid_runtime(vcpu);
1814 }
1815
1816 static void svm_set_segment(struct kvm_vcpu *vcpu,
1817                             struct kvm_segment *var, int seg)
1818 {
1819         struct vcpu_svm *svm = to_svm(vcpu);
1820         struct vmcb_seg *s = svm_seg(vcpu, seg);
1821
1822         s->base = var->base;
1823         s->limit = var->limit;
1824         s->selector = var->selector;
1825         s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1826         s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1827         s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1828         s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
1829         s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1830         s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1831         s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1832         s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1833
1834         /*
1835          * This is always accurate, except if SYSRET returned to a segment
1836          * with SS.DPL != 3.  Intel does not have this quirk, and always
1837          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1838          * would entail passing the CPL to userspace and back.
1839          */
1840         if (seg == VCPU_SREG_SS)
1841                 /* This is symmetric with svm_get_segment() */
1842                 svm->vmcb->save.cpl = (var->dpl & 3);
1843
1844         vmcb_mark_dirty(svm->vmcb, VMCB_SEG);
1845 }
1846
1847 static void svm_update_exception_bitmap(struct kvm_vcpu *vcpu)
1848 {
1849         struct vcpu_svm *svm = to_svm(vcpu);
1850
1851         clr_exception_intercept(svm, BP_VECTOR);
1852
1853         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1854                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1855                         set_exception_intercept(svm, BP_VECTOR);
1856         }
1857 }
1858
1859 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1860 {
1861         if (sd->next_asid > sd->max_asid) {
1862                 ++sd->asid_generation;
1863                 sd->next_asid = sd->min_asid;
1864                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1865                 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
1866         }
1867
1868         svm->current_vmcb->asid_generation = sd->asid_generation;
1869         svm->asid = sd->next_asid++;
1870 }
1871
1872 static void svm_set_dr6(struct vcpu_svm *svm, unsigned long value)
1873 {
1874         struct vmcb *vmcb = svm->vmcb;
1875
1876         if (svm->vcpu.arch.guest_state_protected)
1877                 return;
1878
1879         if (unlikely(value != vmcb->save.dr6)) {
1880                 vmcb->save.dr6 = value;
1881                 vmcb_mark_dirty(vmcb, VMCB_DR);
1882         }
1883 }
1884
1885 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1886 {
1887         struct vcpu_svm *svm = to_svm(vcpu);
1888
1889         if (vcpu->arch.guest_state_protected)
1890                 return;
1891
1892         get_debugreg(vcpu->arch.db[0], 0);
1893         get_debugreg(vcpu->arch.db[1], 1);
1894         get_debugreg(vcpu->arch.db[2], 2);
1895         get_debugreg(vcpu->arch.db[3], 3);
1896         /*
1897          * We cannot reset svm->vmcb->save.dr6 to DR6_ACTIVE_LOW here,
1898          * because db_interception might need it.  We can do it before vmentry.
1899          */
1900         vcpu->arch.dr6 = svm->vmcb->save.dr6;
1901         vcpu->arch.dr7 = svm->vmcb->save.dr7;
1902         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1903         set_dr_intercepts(svm);
1904 }
1905
1906 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1907 {
1908         struct vcpu_svm *svm = to_svm(vcpu);
1909
1910         if (vcpu->arch.guest_state_protected)
1911                 return;
1912
1913         svm->vmcb->save.dr7 = value;
1914         vmcb_mark_dirty(svm->vmcb, VMCB_DR);
1915 }
1916
1917 static int pf_interception(struct kvm_vcpu *vcpu)
1918 {
1919         struct vcpu_svm *svm = to_svm(vcpu);
1920
1921         u64 fault_address = svm->vmcb->control.exit_info_2;
1922         u64 error_code = svm->vmcb->control.exit_info_1;
1923
1924         return kvm_handle_page_fault(vcpu, error_code, fault_address,
1925                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1926                         svm->vmcb->control.insn_bytes : NULL,
1927                         svm->vmcb->control.insn_len);
1928 }
1929
1930 static int npf_interception(struct kvm_vcpu *vcpu)
1931 {
1932         struct vcpu_svm *svm = to_svm(vcpu);
1933
1934         u64 fault_address = svm->vmcb->control.exit_info_2;
1935         u64 error_code = svm->vmcb->control.exit_info_1;
1936
1937         trace_kvm_page_fault(fault_address, error_code);
1938         return kvm_mmu_page_fault(vcpu, fault_address, error_code,
1939                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1940                         svm->vmcb->control.insn_bytes : NULL,
1941                         svm->vmcb->control.insn_len);
1942 }
1943
1944 static int db_interception(struct kvm_vcpu *vcpu)
1945 {
1946         struct kvm_run *kvm_run = vcpu->run;
1947         struct vcpu_svm *svm = to_svm(vcpu);
1948
1949         if (!(vcpu->guest_debug &
1950               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1951                 !svm->nmi_singlestep) {
1952                 u32 payload = svm->vmcb->save.dr6 ^ DR6_ACTIVE_LOW;
1953                 kvm_queue_exception_p(vcpu, DB_VECTOR, payload);
1954                 return 1;
1955         }
1956
1957         if (svm->nmi_singlestep) {
1958                 disable_nmi_singlestep(svm);
1959                 /* Make sure we check for pending NMIs upon entry */
1960                 kvm_make_request(KVM_REQ_EVENT, vcpu);
1961         }
1962
1963         if (vcpu->guest_debug &
1964             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1965                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1966                 kvm_run->debug.arch.dr6 = svm->vmcb->save.dr6;
1967                 kvm_run->debug.arch.dr7 = svm->vmcb->save.dr7;
1968                 kvm_run->debug.arch.pc =
1969                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1970                 kvm_run->debug.arch.exception = DB_VECTOR;
1971                 return 0;
1972         }
1973
1974         return 1;
1975 }
1976
1977 static int bp_interception(struct kvm_vcpu *vcpu)
1978 {
1979         struct vcpu_svm *svm = to_svm(vcpu);
1980         struct kvm_run *kvm_run = vcpu->run;
1981
1982         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1983         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1984         kvm_run->debug.arch.exception = BP_VECTOR;
1985         return 0;
1986 }
1987
1988 static int ud_interception(struct kvm_vcpu *vcpu)
1989 {
1990         return handle_ud(vcpu);
1991 }
1992
1993 static int ac_interception(struct kvm_vcpu *vcpu)
1994 {
1995         kvm_queue_exception_e(vcpu, AC_VECTOR, 0);
1996         return 1;
1997 }
1998
1999 static bool is_erratum_383(void)
2000 {
2001         int err, i;
2002         u64 value;
2003
2004         if (!erratum_383_found)
2005                 return false;
2006
2007         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2008         if (err)
2009                 return false;
2010
2011         /* Bit 62 may or may not be set for this mce */
2012         value &= ~(1ULL << 62);
2013
2014         if (value != 0xb600000000010015ULL)
2015                 return false;
2016
2017         /* Clear MCi_STATUS registers */
2018         for (i = 0; i < 6; ++i)
2019                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2020
2021         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2022         if (!err) {
2023                 u32 low, high;
2024
2025                 value &= ~(1ULL << 2);
2026                 low    = lower_32_bits(value);
2027                 high   = upper_32_bits(value);
2028
2029                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2030         }
2031
2032         /* Flush tlb to evict multi-match entries */
2033         __flush_tlb_all();
2034
2035         return true;
2036 }
2037
2038 static void svm_handle_mce(struct kvm_vcpu *vcpu)
2039 {
2040         if (is_erratum_383()) {
2041                 /*
2042                  * Erratum 383 triggered. Guest state is corrupt so kill the
2043                  * guest.
2044                  */
2045                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2046
2047                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2048
2049                 return;
2050         }
2051
2052         /*
2053          * On an #MC intercept the MCE handler is not called automatically in
2054          * the host. So do it by hand here.
2055          */
2056         kvm_machine_check();
2057 }
2058
2059 static int mc_interception(struct kvm_vcpu *vcpu)
2060 {
2061         return 1;
2062 }
2063
2064 static int shutdown_interception(struct kvm_vcpu *vcpu)
2065 {
2066         struct kvm_run *kvm_run = vcpu->run;
2067         struct vcpu_svm *svm = to_svm(vcpu);
2068
2069         /*
2070          * The VM save area has already been encrypted so it
2071          * cannot be reinitialized - just terminate.
2072          */
2073         if (sev_es_guest(vcpu->kvm))
2074                 return -EINVAL;
2075
2076         /*
2077          * VMCB is undefined after a SHUTDOWN intercept
2078          * so reinitialize it.
2079          */
2080         clear_page(svm->vmcb);
2081         init_vmcb(vcpu);
2082
2083         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2084         return 0;
2085 }
2086
2087 static int io_interception(struct kvm_vcpu *vcpu)
2088 {
2089         struct vcpu_svm *svm = to_svm(vcpu);
2090         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2091         int size, in, string;
2092         unsigned port;
2093
2094         ++vcpu->stat.io_exits;
2095         string = (io_info & SVM_IOIO_STR_MASK) != 0;
2096         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2097         port = io_info >> 16;
2098         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2099
2100         if (string) {
2101                 if (sev_es_guest(vcpu->kvm))
2102                         return sev_es_string_io(svm, size, port, in);
2103                 else
2104                         return kvm_emulate_instruction(vcpu, 0);
2105         }
2106
2107         svm->next_rip = svm->vmcb->control.exit_info_2;
2108
2109         return kvm_fast_pio(vcpu, size, port, in);
2110 }
2111
2112 static int nmi_interception(struct kvm_vcpu *vcpu)
2113 {
2114         return 1;
2115 }
2116
2117 static int smi_interception(struct kvm_vcpu *vcpu)
2118 {
2119         return 1;
2120 }
2121
2122 static int intr_interception(struct kvm_vcpu *vcpu)
2123 {
2124         ++vcpu->stat.irq_exits;
2125         return 1;
2126 }
2127
2128 static int vmload_vmsave_interception(struct kvm_vcpu *vcpu, bool vmload)
2129 {
2130         struct vcpu_svm *svm = to_svm(vcpu);
2131         struct vmcb *vmcb12;
2132         struct kvm_host_map map;
2133         int ret;
2134
2135         if (nested_svm_check_permissions(vcpu))
2136                 return 1;
2137
2138         ret = kvm_vcpu_map(vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
2139         if (ret) {
2140                 if (ret == -EINVAL)
2141                         kvm_inject_gp(vcpu, 0);
2142                 return 1;
2143         }
2144
2145         vmcb12 = map.hva;
2146
2147         ret = kvm_skip_emulated_instruction(vcpu);
2148
2149         if (vmload) {
2150                 nested_svm_vmloadsave(vmcb12, svm->vmcb);
2151                 svm->sysenter_eip_hi = 0;
2152                 svm->sysenter_esp_hi = 0;
2153         } else
2154                 nested_svm_vmloadsave(svm->vmcb, vmcb12);
2155
2156         kvm_vcpu_unmap(vcpu, &map, true);
2157
2158         return ret;
2159 }
2160
2161 static int vmload_interception(struct kvm_vcpu *vcpu)
2162 {
2163         return vmload_vmsave_interception(vcpu, true);
2164 }
2165
2166 static int vmsave_interception(struct kvm_vcpu *vcpu)
2167 {
2168         return vmload_vmsave_interception(vcpu, false);
2169 }
2170
2171 static int vmrun_interception(struct kvm_vcpu *vcpu)
2172 {
2173         if (nested_svm_check_permissions(vcpu))
2174                 return 1;
2175
2176         return nested_svm_vmrun(vcpu);
2177 }
2178
2179 enum {
2180         NONE_SVM_INSTR,
2181         SVM_INSTR_VMRUN,
2182         SVM_INSTR_VMLOAD,
2183         SVM_INSTR_VMSAVE,
2184 };
2185
2186 /* Return NONE_SVM_INSTR if not SVM instrs, otherwise return decode result */
2187 static int svm_instr_opcode(struct kvm_vcpu *vcpu)
2188 {
2189         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
2190
2191         if (ctxt->b != 0x1 || ctxt->opcode_len != 2)
2192                 return NONE_SVM_INSTR;
2193
2194         switch (ctxt->modrm) {
2195         case 0xd8: /* VMRUN */
2196                 return SVM_INSTR_VMRUN;
2197         case 0xda: /* VMLOAD */
2198                 return SVM_INSTR_VMLOAD;
2199         case 0xdb: /* VMSAVE */
2200                 return SVM_INSTR_VMSAVE;
2201         default:
2202                 break;
2203         }
2204
2205         return NONE_SVM_INSTR;
2206 }
2207
2208 static int emulate_svm_instr(struct kvm_vcpu *vcpu, int opcode)
2209 {
2210         const int guest_mode_exit_codes[] = {
2211                 [SVM_INSTR_VMRUN] = SVM_EXIT_VMRUN,
2212                 [SVM_INSTR_VMLOAD] = SVM_EXIT_VMLOAD,
2213                 [SVM_INSTR_VMSAVE] = SVM_EXIT_VMSAVE,
2214         };
2215         int (*const svm_instr_handlers[])(struct kvm_vcpu *vcpu) = {
2216                 [SVM_INSTR_VMRUN] = vmrun_interception,
2217                 [SVM_INSTR_VMLOAD] = vmload_interception,
2218                 [SVM_INSTR_VMSAVE] = vmsave_interception,
2219         };
2220         struct vcpu_svm *svm = to_svm(vcpu);
2221         int ret;
2222
2223         if (is_guest_mode(vcpu)) {
2224                 /* Returns '1' or -errno on failure, '0' on success. */
2225                 ret = nested_svm_simple_vmexit(svm, guest_mode_exit_codes[opcode]);
2226                 if (ret)
2227                         return ret;
2228                 return 1;
2229         }
2230         return svm_instr_handlers[opcode](vcpu);
2231 }
2232
2233 /*
2234  * #GP handling code. Note that #GP can be triggered under the following two
2235  * cases:
2236  *   1) SVM VM-related instructions (VMRUN/VMSAVE/VMLOAD) that trigger #GP on
2237  *      some AMD CPUs when EAX of these instructions are in the reserved memory
2238  *      regions (e.g. SMM memory on host).
2239  *   2) VMware backdoor
2240  */
2241 static int gp_interception(struct kvm_vcpu *vcpu)
2242 {
2243         struct vcpu_svm *svm = to_svm(vcpu);
2244         u32 error_code = svm->vmcb->control.exit_info_1;
2245         int opcode;
2246
2247         /* Both #GP cases have zero error_code */
2248         if (error_code)
2249                 goto reinject;
2250
2251         /* Decode the instruction for usage later */
2252         if (x86_decode_emulated_instruction(vcpu, 0, NULL, 0) != EMULATION_OK)
2253                 goto reinject;
2254
2255         opcode = svm_instr_opcode(vcpu);
2256
2257         if (opcode == NONE_SVM_INSTR) {
2258                 if (!enable_vmware_backdoor)
2259                         goto reinject;
2260
2261                 /*
2262                  * VMware backdoor emulation on #GP interception only handles
2263                  * IN{S}, OUT{S}, and RDPMC.
2264                  */
2265                 if (!is_guest_mode(vcpu))
2266                         return kvm_emulate_instruction(vcpu,
2267                                 EMULTYPE_VMWARE_GP | EMULTYPE_NO_DECODE);
2268         } else
2269                 return emulate_svm_instr(vcpu, opcode);
2270
2271 reinject:
2272         kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2273         return 1;
2274 }
2275
2276 void svm_set_gif(struct vcpu_svm *svm, bool value)
2277 {
2278         if (value) {
2279                 /*
2280                  * If VGIF is enabled, the STGI intercept is only added to
2281                  * detect the opening of the SMI/NMI window; remove it now.
2282                  * Likewise, clear the VINTR intercept, we will set it
2283                  * again while processing KVM_REQ_EVENT if needed.
2284                  */
2285                 if (vgif_enabled(svm))
2286                         svm_clr_intercept(svm, INTERCEPT_STGI);
2287                 if (svm_is_intercept(svm, INTERCEPT_VINTR))
2288                         svm_clear_vintr(svm);
2289
2290                 enable_gif(svm);
2291                 if (svm->vcpu.arch.smi_pending ||
2292                     svm->vcpu.arch.nmi_pending ||
2293                     kvm_cpu_has_injectable_intr(&svm->vcpu))
2294                         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2295         } else {
2296                 disable_gif(svm);
2297
2298                 /*
2299                  * After a CLGI no interrupts should come.  But if vGIF is
2300                  * in use, we still rely on the VINTR intercept (rather than
2301                  * STGI) to detect an open interrupt window.
2302                 */
2303                 if (!vgif_enabled(svm))
2304                         svm_clear_vintr(svm);
2305         }
2306 }
2307
2308 static int stgi_interception(struct kvm_vcpu *vcpu)
2309 {
2310         int ret;
2311
2312         if (nested_svm_check_permissions(vcpu))
2313                 return 1;
2314
2315         ret = kvm_skip_emulated_instruction(vcpu);
2316         svm_set_gif(to_svm(vcpu), true);
2317         return ret;
2318 }
2319
2320 static int clgi_interception(struct kvm_vcpu *vcpu)
2321 {
2322         int ret;
2323
2324         if (nested_svm_check_permissions(vcpu))
2325                 return 1;
2326
2327         ret = kvm_skip_emulated_instruction(vcpu);
2328         svm_set_gif(to_svm(vcpu), false);
2329         return ret;
2330 }
2331
2332 static int invlpga_interception(struct kvm_vcpu *vcpu)
2333 {
2334         gva_t gva = kvm_rax_read(vcpu);
2335         u32 asid = kvm_rcx_read(vcpu);
2336
2337         /* FIXME: Handle an address size prefix. */
2338         if (!is_long_mode(vcpu))
2339                 gva = (u32)gva;
2340
2341         trace_kvm_invlpga(to_svm(vcpu)->vmcb->save.rip, asid, gva);
2342
2343         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2344         kvm_mmu_invlpg(vcpu, gva);
2345
2346         return kvm_skip_emulated_instruction(vcpu);
2347 }
2348
2349 static int skinit_interception(struct kvm_vcpu *vcpu)
2350 {
2351         trace_kvm_skinit(to_svm(vcpu)->vmcb->save.rip, kvm_rax_read(vcpu));
2352
2353         kvm_queue_exception(vcpu, UD_VECTOR);
2354         return 1;
2355 }
2356
2357 static int task_switch_interception(struct kvm_vcpu *vcpu)
2358 {
2359         struct vcpu_svm *svm = to_svm(vcpu);
2360         u16 tss_selector;
2361         int reason;
2362         int int_type = svm->vmcb->control.exit_int_info &
2363                 SVM_EXITINTINFO_TYPE_MASK;
2364         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2365         uint32_t type =
2366                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2367         uint32_t idt_v =
2368                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2369         bool has_error_code = false;
2370         u32 error_code = 0;
2371
2372         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2373
2374         if (svm->vmcb->control.exit_info_2 &
2375             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2376                 reason = TASK_SWITCH_IRET;
2377         else if (svm->vmcb->control.exit_info_2 &
2378                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2379                 reason = TASK_SWITCH_JMP;
2380         else if (idt_v)
2381                 reason = TASK_SWITCH_GATE;
2382         else
2383                 reason = TASK_SWITCH_CALL;
2384
2385         if (reason == TASK_SWITCH_GATE) {
2386                 switch (type) {
2387                 case SVM_EXITINTINFO_TYPE_NMI:
2388                         vcpu->arch.nmi_injected = false;
2389                         break;
2390                 case SVM_EXITINTINFO_TYPE_EXEPT:
2391                         if (svm->vmcb->control.exit_info_2 &
2392                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2393                                 has_error_code = true;
2394                                 error_code =
2395                                         (u32)svm->vmcb->control.exit_info_2;
2396                         }
2397                         kvm_clear_exception_queue(vcpu);
2398                         break;
2399                 case SVM_EXITINTINFO_TYPE_INTR:
2400                         kvm_clear_interrupt_queue(vcpu);
2401                         break;
2402                 default:
2403                         break;
2404                 }
2405         }
2406
2407         if (reason != TASK_SWITCH_GATE ||
2408             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2409             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2410              (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
2411                 if (!skip_emulated_instruction(vcpu))
2412                         return 0;
2413         }
2414
2415         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2416                 int_vec = -1;
2417
2418         return kvm_task_switch(vcpu, tss_selector, int_vec, reason,
2419                                has_error_code, error_code);
2420 }
2421
2422 static int iret_interception(struct kvm_vcpu *vcpu)
2423 {
2424         struct vcpu_svm *svm = to_svm(vcpu);
2425
2426         ++vcpu->stat.nmi_window_exits;
2427         vcpu->arch.hflags |= HF_IRET_MASK;
2428         if (!sev_es_guest(vcpu->kvm)) {
2429                 svm_clr_intercept(svm, INTERCEPT_IRET);
2430                 svm->nmi_iret_rip = kvm_rip_read(vcpu);
2431         }
2432         kvm_make_request(KVM_REQ_EVENT, vcpu);
2433         return 1;
2434 }
2435
2436 static int invlpg_interception(struct kvm_vcpu *vcpu)
2437 {
2438         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2439                 return kvm_emulate_instruction(vcpu, 0);
2440
2441         kvm_mmu_invlpg(vcpu, to_svm(vcpu)->vmcb->control.exit_info_1);
2442         return kvm_skip_emulated_instruction(vcpu);
2443 }
2444
2445 static int emulate_on_interception(struct kvm_vcpu *vcpu)
2446 {
2447         return kvm_emulate_instruction(vcpu, 0);
2448 }
2449
2450 static int rsm_interception(struct kvm_vcpu *vcpu)
2451 {
2452         return kvm_emulate_instruction_from_buffer(vcpu, rsm_ins_bytes, 2);
2453 }
2454
2455 static bool check_selective_cr0_intercepted(struct kvm_vcpu *vcpu,
2456                                             unsigned long val)
2457 {
2458         struct vcpu_svm *svm = to_svm(vcpu);
2459         unsigned long cr0 = vcpu->arch.cr0;
2460         bool ret = false;
2461
2462         if (!is_guest_mode(vcpu) ||
2463             (!(vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_SELECTIVE_CR0))))
2464                 return false;
2465
2466         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2467         val &= ~SVM_CR0_SELECTIVE_MASK;
2468
2469         if (cr0 ^ val) {
2470                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2471                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2472         }
2473
2474         return ret;
2475 }
2476
2477 #define CR_VALID (1ULL << 63)
2478
2479 static int cr_interception(struct kvm_vcpu *vcpu)
2480 {
2481         struct vcpu_svm *svm = to_svm(vcpu);
2482         int reg, cr;
2483         unsigned long val;
2484         int err;
2485
2486         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2487                 return emulate_on_interception(vcpu);
2488
2489         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2490                 return emulate_on_interception(vcpu);
2491
2492         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2493         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2494                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2495         else
2496                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2497
2498         err = 0;
2499         if (cr >= 16) { /* mov to cr */
2500                 cr -= 16;
2501                 val = kvm_register_read(vcpu, reg);
2502                 trace_kvm_cr_write(cr, val);
2503                 switch (cr) {
2504                 case 0:
2505                         if (!check_selective_cr0_intercepted(vcpu, val))
2506                                 err = kvm_set_cr0(vcpu, val);
2507                         else
2508                                 return 1;
2509
2510                         break;
2511                 case 3:
2512                         err = kvm_set_cr3(vcpu, val);
2513                         break;
2514                 case 4:
2515                         err = kvm_set_cr4(vcpu, val);
2516                         break;
2517                 case 8:
2518                         err = kvm_set_cr8(vcpu, val);
2519                         break;
2520                 default:
2521                         WARN(1, "unhandled write to CR%d", cr);
2522                         kvm_queue_exception(vcpu, UD_VECTOR);
2523                         return 1;
2524                 }
2525         } else { /* mov from cr */
2526                 switch (cr) {
2527                 case 0:
2528                         val = kvm_read_cr0(vcpu);
2529                         break;
2530                 case 2:
2531                         val = vcpu->arch.cr2;
2532                         break;
2533                 case 3:
2534                         val = kvm_read_cr3(vcpu);
2535                         break;
2536                 case 4:
2537                         val = kvm_read_cr4(vcpu);
2538                         break;
2539                 case 8:
2540                         val = kvm_get_cr8(vcpu);
2541                         break;
2542                 default:
2543                         WARN(1, "unhandled read from CR%d", cr);
2544                         kvm_queue_exception(vcpu, UD_VECTOR);
2545                         return 1;
2546                 }
2547                 kvm_register_write(vcpu, reg, val);
2548                 trace_kvm_cr_read(cr, val);
2549         }
2550         return kvm_complete_insn_gp(vcpu, err);
2551 }
2552
2553 static int cr_trap(struct kvm_vcpu *vcpu)
2554 {
2555         struct vcpu_svm *svm = to_svm(vcpu);
2556         unsigned long old_value, new_value;
2557         unsigned int cr;
2558         int ret = 0;
2559
2560         new_value = (unsigned long)svm->vmcb->control.exit_info_1;
2561
2562         cr = svm->vmcb->control.exit_code - SVM_EXIT_CR0_WRITE_TRAP;
2563         switch (cr) {
2564         case 0:
2565                 old_value = kvm_read_cr0(vcpu);
2566                 svm_set_cr0(vcpu, new_value);
2567
2568                 kvm_post_set_cr0(vcpu, old_value, new_value);
2569                 break;
2570         case 4:
2571                 old_value = kvm_read_cr4(vcpu);
2572                 svm_set_cr4(vcpu, new_value);
2573
2574                 kvm_post_set_cr4(vcpu, old_value, new_value);
2575                 break;
2576         case 8:
2577                 ret = kvm_set_cr8(vcpu, new_value);
2578                 break;
2579         default:
2580                 WARN(1, "unhandled CR%d write trap", cr);
2581                 kvm_queue_exception(vcpu, UD_VECTOR);
2582                 return 1;
2583         }
2584
2585         return kvm_complete_insn_gp(vcpu, ret);
2586 }
2587
2588 static int dr_interception(struct kvm_vcpu *vcpu)
2589 {
2590         struct vcpu_svm *svm = to_svm(vcpu);
2591         int reg, dr;
2592         unsigned long val;
2593         int err = 0;
2594
2595         if (vcpu->guest_debug == 0) {
2596                 /*
2597                  * No more DR vmexits; force a reload of the debug registers
2598                  * and reenter on this instruction.  The next vmexit will
2599                  * retrieve the full state of the debug registers.
2600                  */
2601                 clr_dr_intercepts(svm);
2602                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2603                 return 1;
2604         }
2605
2606         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2607                 return emulate_on_interception(vcpu);
2608
2609         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2610         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2611         if (dr >= 16) { /* mov to DRn  */
2612                 dr -= 16;
2613                 val = kvm_register_read(vcpu, reg);
2614                 err = kvm_set_dr(vcpu, dr, val);
2615         } else {
2616                 kvm_get_dr(vcpu, dr, &val);
2617                 kvm_register_write(vcpu, reg, val);
2618         }
2619
2620         return kvm_complete_insn_gp(vcpu, err);
2621 }
2622
2623 static int cr8_write_interception(struct kvm_vcpu *vcpu)
2624 {
2625         int r;
2626
2627         u8 cr8_prev = kvm_get_cr8(vcpu);
2628         /* instruction emulation calls kvm_set_cr8() */
2629         r = cr_interception(vcpu);
2630         if (lapic_in_kernel(vcpu))
2631                 return r;
2632         if (cr8_prev <= kvm_get_cr8(vcpu))
2633                 return r;
2634         vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
2635         return 0;
2636 }
2637
2638 static int efer_trap(struct kvm_vcpu *vcpu)
2639 {
2640         struct msr_data msr_info;
2641         int ret;
2642
2643         /*
2644          * Clear the EFER_SVME bit from EFER. The SVM code always sets this
2645          * bit in svm_set_efer(), but __kvm_valid_efer() checks it against
2646          * whether the guest has X86_FEATURE_SVM - this avoids a failure if
2647          * the guest doesn't have X86_FEATURE_SVM.
2648          */
2649         msr_info.host_initiated = false;
2650         msr_info.index = MSR_EFER;
2651         msr_info.data = to_svm(vcpu)->vmcb->control.exit_info_1 & ~EFER_SVME;
2652         ret = kvm_set_msr_common(vcpu, &msr_info);
2653
2654         return kvm_complete_insn_gp(vcpu, ret);
2655 }
2656
2657 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
2658 {
2659         msr->data = 0;
2660
2661         switch (msr->index) {
2662         case MSR_F10H_DECFG:
2663                 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
2664                         msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
2665                 break;
2666         case MSR_IA32_PERF_CAPABILITIES:
2667                 return 0;
2668         default:
2669                 return KVM_MSR_RET_INVALID;
2670         }
2671
2672         return 0;
2673 }
2674
2675 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2676 {
2677         struct vcpu_svm *svm = to_svm(vcpu);
2678
2679         switch (msr_info->index) {
2680         case MSR_STAR:
2681                 msr_info->data = svm->vmcb01.ptr->save.star;
2682                 break;
2683 #ifdef CONFIG_X86_64
2684         case MSR_LSTAR:
2685                 msr_info->data = svm->vmcb01.ptr->save.lstar;
2686                 break;
2687         case MSR_CSTAR:
2688                 msr_info->data = svm->vmcb01.ptr->save.cstar;
2689                 break;
2690         case MSR_KERNEL_GS_BASE:
2691                 msr_info->data = svm->vmcb01.ptr->save.kernel_gs_base;
2692                 break;
2693         case MSR_SYSCALL_MASK:
2694                 msr_info->data = svm->vmcb01.ptr->save.sfmask;
2695                 break;
2696 #endif
2697         case MSR_IA32_SYSENTER_CS:
2698                 msr_info->data = svm->vmcb01.ptr->save.sysenter_cs;
2699                 break;
2700         case MSR_IA32_SYSENTER_EIP:
2701                 msr_info->data = (u32)svm->vmcb01.ptr->save.sysenter_eip;
2702                 if (guest_cpuid_is_intel(vcpu))
2703                         msr_info->data |= (u64)svm->sysenter_eip_hi << 32;
2704                 break;
2705         case MSR_IA32_SYSENTER_ESP:
2706                 msr_info->data = svm->vmcb01.ptr->save.sysenter_esp;
2707                 if (guest_cpuid_is_intel(vcpu))
2708                         msr_info->data |= (u64)svm->sysenter_esp_hi << 32;
2709                 break;
2710         case MSR_TSC_AUX:
2711                 msr_info->data = svm->tsc_aux;
2712                 break;
2713         /*
2714          * Nobody will change the following 5 values in the VMCB so we can
2715          * safely return them on rdmsr. They will always be 0 until LBRV is
2716          * implemented.
2717          */
2718         case MSR_IA32_DEBUGCTLMSR:
2719                 msr_info->data = svm->vmcb->save.dbgctl;
2720                 break;
2721         case MSR_IA32_LASTBRANCHFROMIP:
2722                 msr_info->data = svm->vmcb->save.br_from;
2723                 break;
2724         case MSR_IA32_LASTBRANCHTOIP:
2725                 msr_info->data = svm->vmcb->save.br_to;
2726                 break;
2727         case MSR_IA32_LASTINTFROMIP:
2728                 msr_info->data = svm->vmcb->save.last_excp_from;
2729                 break;
2730         case MSR_IA32_LASTINTTOIP:
2731                 msr_info->data = svm->vmcb->save.last_excp_to;
2732                 break;
2733         case MSR_VM_HSAVE_PA:
2734                 msr_info->data = svm->nested.hsave_msr;
2735                 break;
2736         case MSR_VM_CR:
2737                 msr_info->data = svm->nested.vm_cr_msr;
2738                 break;
2739         case MSR_IA32_SPEC_CTRL:
2740                 if (!msr_info->host_initiated &&
2741                     !guest_has_spec_ctrl_msr(vcpu))
2742                         return 1;
2743
2744                 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL))
2745                         msr_info->data = svm->vmcb->save.spec_ctrl;
2746                 else
2747                         msr_info->data = svm->spec_ctrl;
2748                 break;
2749         case MSR_AMD64_VIRT_SPEC_CTRL:
2750                 if (!msr_info->host_initiated &&
2751                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2752                         return 1;
2753
2754                 msr_info->data = svm->virt_spec_ctrl;
2755                 break;
2756         case MSR_F15H_IC_CFG: {
2757
2758                 int family, model;
2759
2760                 family = guest_cpuid_family(vcpu);
2761                 model  = guest_cpuid_model(vcpu);
2762
2763                 if (family < 0 || model < 0)
2764                         return kvm_get_msr_common(vcpu, msr_info);
2765
2766                 msr_info->data = 0;
2767
2768                 if (family == 0x15 &&
2769                     (model >= 0x2 && model < 0x20))
2770                         msr_info->data = 0x1E;
2771                 }
2772                 break;
2773         case MSR_F10H_DECFG:
2774                 msr_info->data = svm->msr_decfg;
2775                 break;
2776         default:
2777                 return kvm_get_msr_common(vcpu, msr_info);
2778         }
2779         return 0;
2780 }
2781
2782 static int svm_complete_emulated_msr(struct kvm_vcpu *vcpu, int err)
2783 {
2784         struct vcpu_svm *svm = to_svm(vcpu);
2785         if (!err || !sev_es_guest(vcpu->kvm) || WARN_ON_ONCE(!svm->ghcb))
2786                 return kvm_complete_insn_gp(vcpu, err);
2787
2788         ghcb_set_sw_exit_info_1(svm->ghcb, 1);
2789         ghcb_set_sw_exit_info_2(svm->ghcb,
2790                                 X86_TRAP_GP |
2791                                 SVM_EVTINJ_TYPE_EXEPT |
2792                                 SVM_EVTINJ_VALID);
2793         return 1;
2794 }
2795
2796 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2797 {
2798         struct vcpu_svm *svm = to_svm(vcpu);
2799         int svm_dis, chg_mask;
2800
2801         if (data & ~SVM_VM_CR_VALID_MASK)
2802                 return 1;
2803
2804         chg_mask = SVM_VM_CR_VALID_MASK;
2805
2806         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2807                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2808
2809         svm->nested.vm_cr_msr &= ~chg_mask;
2810         svm->nested.vm_cr_msr |= (data & chg_mask);
2811
2812         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2813
2814         /* check for svm_disable while efer.svme is set */
2815         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2816                 return 1;
2817
2818         return 0;
2819 }
2820
2821 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2822 {
2823         struct vcpu_svm *svm = to_svm(vcpu);
2824         int r;
2825
2826         u32 ecx = msr->index;
2827         u64 data = msr->data;
2828         switch (ecx) {
2829         case MSR_IA32_CR_PAT:
2830                 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2831                         return 1;
2832                 vcpu->arch.pat = data;
2833                 svm->vmcb01.ptr->save.g_pat = data;
2834                 if (is_guest_mode(vcpu))
2835                         nested_vmcb02_compute_g_pat(svm);
2836                 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
2837                 break;
2838         case MSR_IA32_SPEC_CTRL:
2839                 if (!msr->host_initiated &&
2840                     !guest_has_spec_ctrl_msr(vcpu))
2841                         return 1;
2842
2843                 if (kvm_spec_ctrl_test_value(data))
2844                         return 1;
2845
2846                 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL))
2847                         svm->vmcb->save.spec_ctrl = data;
2848                 else
2849                         svm->spec_ctrl = data;
2850                 if (!data)
2851                         break;
2852
2853                 /*
2854                  * For non-nested:
2855                  * When it's written (to non-zero) for the first time, pass
2856                  * it through.
2857                  *
2858                  * For nested:
2859                  * The handling of the MSR bitmap for L2 guests is done in
2860                  * nested_svm_vmrun_msrpm.
2861                  * We update the L1 MSR bit as well since it will end up
2862                  * touching the MSR anyway now.
2863                  */
2864                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
2865                 break;
2866         case MSR_IA32_PRED_CMD:
2867                 if (!msr->host_initiated &&
2868                     !guest_has_pred_cmd_msr(vcpu))
2869                         return 1;
2870
2871                 if (data & ~PRED_CMD_IBPB)
2872                         return 1;
2873                 if (!boot_cpu_has(X86_FEATURE_IBPB))
2874                         return 1;
2875                 if (!data)
2876                         break;
2877
2878                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2879                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
2880                 break;
2881         case MSR_AMD64_VIRT_SPEC_CTRL:
2882                 if (!msr->host_initiated &&
2883                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2884                         return 1;
2885
2886                 if (data & ~SPEC_CTRL_SSBD)
2887                         return 1;
2888
2889                 svm->virt_spec_ctrl = data;
2890                 break;
2891         case MSR_STAR:
2892                 svm->vmcb01.ptr->save.star = data;
2893                 break;
2894 #ifdef CONFIG_X86_64
2895         case MSR_LSTAR:
2896                 svm->vmcb01.ptr->save.lstar = data;
2897                 break;
2898         case MSR_CSTAR:
2899                 svm->vmcb01.ptr->save.cstar = data;
2900                 break;
2901         case MSR_KERNEL_GS_BASE:
2902                 svm->vmcb01.ptr->save.kernel_gs_base = data;
2903                 break;
2904         case MSR_SYSCALL_MASK:
2905                 svm->vmcb01.ptr->save.sfmask = data;
2906                 break;
2907 #endif
2908         case MSR_IA32_SYSENTER_CS:
2909                 svm->vmcb01.ptr->save.sysenter_cs = data;
2910                 break;
2911         case MSR_IA32_SYSENTER_EIP:
2912                 svm->vmcb01.ptr->save.sysenter_eip = (u32)data;
2913                 /*
2914                  * We only intercept the MSR_IA32_SYSENTER_{EIP|ESP} msrs
2915                  * when we spoof an Intel vendor ID (for cross vendor migration).
2916                  * In this case we use this intercept to track the high
2917                  * 32 bit part of these msrs to support Intel's
2918                  * implementation of SYSENTER/SYSEXIT.
2919                  */
2920                 svm->sysenter_eip_hi = guest_cpuid_is_intel(vcpu) ? (data >> 32) : 0;
2921                 break;
2922         case MSR_IA32_SYSENTER_ESP:
2923                 svm->vmcb01.ptr->save.sysenter_esp = (u32)data;
2924                 svm->sysenter_esp_hi = guest_cpuid_is_intel(vcpu) ? (data >> 32) : 0;
2925                 break;
2926         case MSR_TSC_AUX:
2927                 /*
2928                  * TSC_AUX is usually changed only during boot and never read
2929                  * directly.  Intercept TSC_AUX instead of exposing it to the
2930                  * guest via direct_access_msrs, and switch it via user return.
2931                  */
2932                 preempt_disable();
2933                 r = kvm_set_user_return_msr(tsc_aux_uret_slot, data, -1ull);
2934                 preempt_enable();
2935                 if (r)
2936                         return 1;
2937
2938                 svm->tsc_aux = data;
2939                 break;
2940         case MSR_IA32_DEBUGCTLMSR:
2941                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2942                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2943                                     __func__, data);
2944                         break;
2945                 }
2946                 if (data & DEBUGCTL_RESERVED_BITS)
2947                         return 1;
2948
2949                 svm->vmcb->save.dbgctl = data;
2950                 vmcb_mark_dirty(svm->vmcb, VMCB_LBR);
2951                 if (data & (1ULL<<0))
2952                         svm_enable_lbrv(vcpu);
2953                 else
2954                         svm_disable_lbrv(vcpu);
2955                 break;
2956         case MSR_VM_HSAVE_PA:
2957                 /*
2958                  * Old kernels did not validate the value written to
2959                  * MSR_VM_HSAVE_PA.  Allow KVM_SET_MSR to set an invalid
2960                  * value to allow live migrating buggy or malicious guests
2961                  * originating from those kernels.
2962                  */
2963                 if (!msr->host_initiated && !page_address_valid(vcpu, data))
2964                         return 1;
2965
2966                 svm->nested.hsave_msr = data & PAGE_MASK;
2967                 break;
2968         case MSR_VM_CR:
2969                 return svm_set_vm_cr(vcpu, data);
2970         case MSR_VM_IGNNE:
2971                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2972                 break;
2973         case MSR_F10H_DECFG: {
2974                 struct kvm_msr_entry msr_entry;
2975
2976                 msr_entry.index = msr->index;
2977                 if (svm_get_msr_feature(&msr_entry))
2978                         return 1;
2979
2980                 /* Check the supported bits */
2981                 if (data & ~msr_entry.data)
2982                         return 1;
2983
2984                 /* Don't allow the guest to change a bit, #GP */
2985                 if (!msr->host_initiated && (data ^ msr_entry.data))
2986                         return 1;
2987
2988                 svm->msr_decfg = data;
2989                 break;
2990         }
2991         case MSR_IA32_APICBASE:
2992                 if (kvm_vcpu_apicv_active(vcpu))
2993                         avic_update_vapic_bar(to_svm(vcpu), data);
2994                 fallthrough;
2995         default:
2996                 return kvm_set_msr_common(vcpu, msr);
2997         }
2998         return 0;
2999 }
3000
3001 static int msr_interception(struct kvm_vcpu *vcpu)
3002 {
3003         if (to_svm(vcpu)->vmcb->control.exit_info_1)
3004                 return kvm_emulate_wrmsr(vcpu);
3005         else
3006                 return kvm_emulate_rdmsr(vcpu);
3007 }
3008
3009 static int interrupt_window_interception(struct kvm_vcpu *vcpu)
3010 {
3011         kvm_make_request(KVM_REQ_EVENT, vcpu);
3012         svm_clear_vintr(to_svm(vcpu));
3013
3014         /*
3015          * For AVIC, the only reason to end up here is ExtINTs.
3016          * In this case AVIC was temporarily disabled for
3017          * requesting the IRQ window and we have to re-enable it.
3018          */
3019         svm_toggle_avic_for_irq_window(vcpu, true);
3020
3021         ++vcpu->stat.irq_window_exits;
3022         return 1;
3023 }
3024
3025 static int pause_interception(struct kvm_vcpu *vcpu)
3026 {
3027         bool in_kernel;
3028
3029         /*
3030          * CPL is not made available for an SEV-ES guest, therefore
3031          * vcpu->arch.preempted_in_kernel can never be true.  Just
3032          * set in_kernel to false as well.
3033          */
3034         in_kernel = !sev_es_guest(vcpu->kvm) && svm_get_cpl(vcpu) == 0;
3035
3036         if (!kvm_pause_in_guest(vcpu->kvm))
3037                 grow_ple_window(vcpu);
3038
3039         kvm_vcpu_on_spin(vcpu, in_kernel);
3040         return kvm_skip_emulated_instruction(vcpu);
3041 }
3042
3043 static int invpcid_interception(struct kvm_vcpu *vcpu)
3044 {
3045         struct vcpu_svm *svm = to_svm(vcpu);
3046         unsigned long type;
3047         gva_t gva;
3048
3049         if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
3050                 kvm_queue_exception(vcpu, UD_VECTOR);
3051                 return 1;
3052         }
3053
3054         /*
3055          * For an INVPCID intercept:
3056          * EXITINFO1 provides the linear address of the memory operand.
3057          * EXITINFO2 provides the contents of the register operand.
3058          */
3059         type = svm->vmcb->control.exit_info_2;
3060         gva = svm->vmcb->control.exit_info_1;
3061
3062         if (type > 3) {
3063                 kvm_inject_gp(vcpu, 0);
3064                 return 1;
3065         }
3066
3067         return kvm_handle_invpcid(vcpu, type, gva);
3068 }
3069
3070 static int (*const svm_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3071         [SVM_EXIT_READ_CR0]                     = cr_interception,
3072         [SVM_EXIT_READ_CR3]                     = cr_interception,
3073         [SVM_EXIT_READ_CR4]                     = cr_interception,
3074         [SVM_EXIT_READ_CR8]                     = cr_interception,
3075         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
3076         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
3077         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
3078         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
3079         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
3080         [SVM_EXIT_READ_DR0]                     = dr_interception,
3081         [SVM_EXIT_READ_DR1]                     = dr_interception,
3082         [SVM_EXIT_READ_DR2]                     = dr_interception,
3083         [SVM_EXIT_READ_DR3]                     = dr_interception,
3084         [SVM_EXIT_READ_DR4]                     = dr_interception,
3085         [SVM_EXIT_READ_DR5]                     = dr_interception,
3086         [SVM_EXIT_READ_DR6]                     = dr_interception,
3087         [SVM_EXIT_READ_DR7]                     = dr_interception,
3088         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
3089         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
3090         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
3091         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
3092         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
3093         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
3094         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
3095         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
3096         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
3097         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
3098         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
3099         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
3100         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
3101         [SVM_EXIT_EXCP_BASE + AC_VECTOR]        = ac_interception,
3102         [SVM_EXIT_EXCP_BASE + GP_VECTOR]        = gp_interception,
3103         [SVM_EXIT_INTR]                         = intr_interception,
3104         [SVM_EXIT_NMI]                          = nmi_interception,
3105         [SVM_EXIT_SMI]                          = smi_interception,
3106         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
3107         [SVM_EXIT_RDPMC]                        = kvm_emulate_rdpmc,
3108         [SVM_EXIT_CPUID]                        = kvm_emulate_cpuid,
3109         [SVM_EXIT_IRET]                         = iret_interception,
3110         [SVM_EXIT_INVD]                         = kvm_emulate_invd,
3111         [SVM_EXIT_PAUSE]                        = pause_interception,
3112         [SVM_EXIT_HLT]                          = kvm_emulate_halt,
3113         [SVM_EXIT_INVLPG]                       = invlpg_interception,
3114         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
3115         [SVM_EXIT_IOIO]                         = io_interception,
3116         [SVM_EXIT_MSR]                          = msr_interception,
3117         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
3118         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
3119         [SVM_EXIT_VMRUN]                        = vmrun_interception,
3120         [SVM_EXIT_VMMCALL]                      = kvm_emulate_hypercall,
3121         [SVM_EXIT_VMLOAD]                       = vmload_interception,
3122         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
3123         [SVM_EXIT_STGI]                         = stgi_interception,
3124         [SVM_EXIT_CLGI]                         = clgi_interception,
3125         [SVM_EXIT_SKINIT]                       = skinit_interception,
3126         [SVM_EXIT_RDTSCP]                       = kvm_handle_invalid_op,
3127         [SVM_EXIT_WBINVD]                       = kvm_emulate_wbinvd,
3128         [SVM_EXIT_MONITOR]                      = kvm_emulate_monitor,
3129         [SVM_EXIT_MWAIT]                        = kvm_emulate_mwait,
3130         [SVM_EXIT_XSETBV]                       = kvm_emulate_xsetbv,
3131         [SVM_EXIT_RDPRU]                        = kvm_handle_invalid_op,
3132         [SVM_EXIT_EFER_WRITE_TRAP]              = efer_trap,
3133         [SVM_EXIT_CR0_WRITE_TRAP]               = cr_trap,
3134         [SVM_EXIT_CR4_WRITE_TRAP]               = cr_trap,
3135         [SVM_EXIT_CR8_WRITE_TRAP]               = cr_trap,
3136         [SVM_EXIT_INVPCID]                      = invpcid_interception,
3137         [SVM_EXIT_NPF]                          = npf_interception,
3138         [SVM_EXIT_RSM]                          = rsm_interception,
3139         [SVM_EXIT_AVIC_INCOMPLETE_IPI]          = avic_incomplete_ipi_interception,
3140         [SVM_EXIT_AVIC_UNACCELERATED_ACCESS]    = avic_unaccelerated_access_interception,
3141         [SVM_EXIT_VMGEXIT]                      = sev_handle_vmgexit,
3142 };
3143
3144 static void dump_vmcb(struct kvm_vcpu *vcpu)
3145 {
3146         struct vcpu_svm *svm = to_svm(vcpu);
3147         struct vmcb_control_area *control = &svm->vmcb->control;
3148         struct vmcb_save_area *save = &svm->vmcb->save;
3149         struct vmcb_save_area *save01 = &svm->vmcb01.ptr->save;
3150
3151         if (!dump_invalid_vmcb) {
3152                 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
3153                 return;
3154         }
3155
3156         pr_err("VMCB %p, last attempted VMRUN on CPU %d\n",
3157                svm->current_vmcb->ptr, vcpu->arch.last_vmentry_cpu);
3158         pr_err("VMCB Control Area:\n");
3159         pr_err("%-20s%04x\n", "cr_read:", control->intercepts[INTERCEPT_CR] & 0xffff);
3160         pr_err("%-20s%04x\n", "cr_write:", control->intercepts[INTERCEPT_CR] >> 16);
3161         pr_err("%-20s%04x\n", "dr_read:", control->intercepts[INTERCEPT_DR] & 0xffff);
3162         pr_err("%-20s%04x\n", "dr_write:", control->intercepts[INTERCEPT_DR] >> 16);
3163         pr_err("%-20s%08x\n", "exceptions:", control->intercepts[INTERCEPT_EXCEPTION]);
3164         pr_err("%-20s%08x %08x\n", "intercepts:",
3165               control->intercepts[INTERCEPT_WORD3],
3166                control->intercepts[INTERCEPT_WORD4]);
3167         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3168         pr_err("%-20s%d\n", "pause filter threshold:",
3169                control->pause_filter_thresh);
3170         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3171         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3172         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3173         pr_err("%-20s%d\n", "asid:", control->asid);
3174         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3175         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3176         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3177         pr_err("%-20s%08x\n", "int_state:", control->int_state);
3178         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3179         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3180         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3181         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3182         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3183         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3184         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3185         pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
3186         pr_err("%-20s%016llx\n", "ghcb:", control->ghcb_gpa);
3187         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3188         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3189         pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
3190         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3191         pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
3192         pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
3193         pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
3194         pr_err("%-20s%016llx\n", "vmsa_pa:", control->vmsa_pa);
3195         pr_err("VMCB State Save Area:\n");
3196         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3197                "es:",
3198                save->es.selector, save->es.attrib,
3199                save->es.limit, save->es.base);
3200         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3201                "cs:",
3202                save->cs.selector, save->cs.attrib,
3203                save->cs.limit, save->cs.base);
3204         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3205                "ss:",
3206                save->ss.selector, save->ss.attrib,
3207                save->ss.limit, save->ss.base);
3208         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3209                "ds:",
3210                save->ds.selector, save->ds.attrib,
3211                save->ds.limit, save->ds.base);
3212         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3213                "fs:",
3214                save01->fs.selector, save01->fs.attrib,
3215                save01->fs.limit, save01->fs.base);
3216         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3217                "gs:",
3218                save01->gs.selector, save01->gs.attrib,
3219                save01->gs.limit, save01->gs.base);
3220         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3221                "gdtr:",
3222                save->gdtr.selector, save->gdtr.attrib,
3223                save->gdtr.limit, save->gdtr.base);
3224         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3225                "ldtr:",
3226                save01->ldtr.selector, save01->ldtr.attrib,
3227                save01->ldtr.limit, save01->ldtr.base);
3228         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3229                "idtr:",
3230                save->idtr.selector, save->idtr.attrib,
3231                save->idtr.limit, save->idtr.base);
3232         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3233                "tr:",
3234                save01->tr.selector, save01->tr.attrib,
3235                save01->tr.limit, save01->tr.base);
3236         pr_err("cpl:            %d                efer:         %016llx\n",
3237                 save->cpl, save->efer);
3238         pr_err("%-15s %016llx %-13s %016llx\n",
3239                "cr0:", save->cr0, "cr2:", save->cr2);
3240         pr_err("%-15s %016llx %-13s %016llx\n",
3241                "cr3:", save->cr3, "cr4:", save->cr4);
3242         pr_err("%-15s %016llx %-13s %016llx\n",
3243                "dr6:", save->dr6, "dr7:", save->dr7);
3244         pr_err("%-15s %016llx %-13s %016llx\n",
3245                "rip:", save->rip, "rflags:", save->rflags);
3246         pr_err("%-15s %016llx %-13s %016llx\n",
3247                "rsp:", save->rsp, "rax:", save->rax);
3248         pr_err("%-15s %016llx %-13s %016llx\n",
3249                "star:", save01->star, "lstar:", save01->lstar);
3250         pr_err("%-15s %016llx %-13s %016llx\n",
3251                "cstar:", save01->cstar, "sfmask:", save01->sfmask);
3252         pr_err("%-15s %016llx %-13s %016llx\n",
3253                "kernel_gs_base:", save01->kernel_gs_base,
3254                "sysenter_cs:", save01->sysenter_cs);
3255         pr_err("%-15s %016llx %-13s %016llx\n",
3256                "sysenter_esp:", save01->sysenter_esp,
3257                "sysenter_eip:", save01->sysenter_eip);
3258         pr_err("%-15s %016llx %-13s %016llx\n",
3259                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3260         pr_err("%-15s %016llx %-13s %016llx\n",
3261                "br_from:", save->br_from, "br_to:", save->br_to);
3262         pr_err("%-15s %016llx %-13s %016llx\n",
3263                "excp_from:", save->last_excp_from,
3264                "excp_to:", save->last_excp_to);
3265 }
3266
3267 static int svm_handle_invalid_exit(struct kvm_vcpu *vcpu, u64 exit_code)
3268 {
3269         if (exit_code < ARRAY_SIZE(svm_exit_handlers) &&
3270             svm_exit_handlers[exit_code])
3271                 return 0;
3272
3273         vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%llx\n", exit_code);
3274         dump_vmcb(vcpu);
3275         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3276         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
3277         vcpu->run->internal.ndata = 2;
3278         vcpu->run->internal.data[0] = exit_code;
3279         vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
3280
3281         return -EINVAL;
3282 }
3283
3284 int svm_invoke_exit_handler(struct kvm_vcpu *vcpu, u64 exit_code)
3285 {
3286         if (svm_handle_invalid_exit(vcpu, exit_code))
3287                 return 0;
3288
3289 #ifdef CONFIG_RETPOLINE
3290         if (exit_code == SVM_EXIT_MSR)
3291                 return msr_interception(vcpu);
3292         else if (exit_code == SVM_EXIT_VINTR)
3293                 return interrupt_window_interception(vcpu);
3294         else if (exit_code == SVM_EXIT_INTR)
3295                 return intr_interception(vcpu);
3296         else if (exit_code == SVM_EXIT_HLT)
3297                 return kvm_emulate_halt(vcpu);
3298         else if (exit_code == SVM_EXIT_NPF)
3299                 return npf_interception(vcpu);
3300 #endif
3301         return svm_exit_handlers[exit_code](vcpu);
3302 }
3303
3304 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2,
3305                               u32 *intr_info, u32 *error_code)
3306 {
3307         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3308
3309         *info1 = control->exit_info_1;
3310         *info2 = control->exit_info_2;
3311         *intr_info = control->exit_int_info;
3312         if ((*intr_info & SVM_EXITINTINFO_VALID) &&
3313             (*intr_info & SVM_EXITINTINFO_VALID_ERR))
3314                 *error_code = control->exit_int_info_err;
3315         else
3316                 *error_code = 0;
3317 }
3318
3319 static int handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
3320 {
3321         struct vcpu_svm *svm = to_svm(vcpu);
3322         struct kvm_run *kvm_run = vcpu->run;
3323         u32 exit_code = svm->vmcb->control.exit_code;
3324
3325         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
3326
3327         /* SEV-ES guests must use the CR write traps to track CR registers. */
3328         if (!sev_es_guest(vcpu->kvm)) {
3329                 if (!svm_is_intercept(svm, INTERCEPT_CR0_WRITE))
3330                         vcpu->arch.cr0 = svm->vmcb->save.cr0;
3331                 if (npt_enabled)
3332                         vcpu->arch.cr3 = svm->vmcb->save.cr3;
3333         }
3334
3335         if (is_guest_mode(vcpu)) {
3336                 int vmexit;
3337
3338                 trace_kvm_nested_vmexit(exit_code, vcpu, KVM_ISA_SVM);
3339
3340                 vmexit = nested_svm_exit_special(svm);
3341
3342                 if (vmexit == NESTED_EXIT_CONTINUE)
3343                         vmexit = nested_svm_exit_handled(svm);
3344
3345                 if (vmexit == NESTED_EXIT_DONE)
3346                         return 1;
3347         }
3348
3349         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3350                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3351                 kvm_run->fail_entry.hardware_entry_failure_reason
3352                         = svm->vmcb->control.exit_code;
3353                 kvm_run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
3354                 dump_vmcb(vcpu);
3355                 return 0;
3356         }
3357
3358         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3359             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3360             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3361             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3362                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
3363                        "exit_code 0x%x\n",
3364                        __func__, svm->vmcb->control.exit_int_info,
3365                        exit_code);
3366
3367         if (exit_fastpath != EXIT_FASTPATH_NONE)
3368                 return 1;
3369
3370         return svm_invoke_exit_handler(vcpu, exit_code);
3371 }
3372
3373 static void reload_tss(struct kvm_vcpu *vcpu)
3374 {
3375         struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3376
3377         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3378         load_TR_desc();
3379 }
3380
3381 static void pre_svm_run(struct kvm_vcpu *vcpu)
3382 {
3383         struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3384         struct vcpu_svm *svm = to_svm(vcpu);
3385
3386         /*
3387          * If the previous vmrun of the vmcb occurred on a different physical
3388          * cpu, then mark the vmcb dirty and assign a new asid.  Hardware's
3389          * vmcb clean bits are per logical CPU, as are KVM's asid assignments.
3390          */
3391         if (unlikely(svm->current_vmcb->cpu != vcpu->cpu)) {
3392                 svm->current_vmcb->asid_generation = 0;
3393                 vmcb_mark_all_dirty(svm->vmcb);
3394                 svm->current_vmcb->cpu = vcpu->cpu;
3395         }
3396
3397         if (sev_guest(vcpu->kvm))
3398                 return pre_sev_run(svm, vcpu->cpu);
3399
3400         /* FIXME: handle wraparound of asid_generation */
3401         if (svm->current_vmcb->asid_generation != sd->asid_generation)
3402                 new_asid(svm, sd);
3403 }
3404
3405 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3406 {
3407         struct vcpu_svm *svm = to_svm(vcpu);
3408
3409         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3410         vcpu->arch.hflags |= HF_NMI_MASK;
3411         if (!sev_es_guest(vcpu->kvm))
3412                 svm_set_intercept(svm, INTERCEPT_IRET);
3413         ++vcpu->stat.nmi_injections;
3414 }
3415
3416 static void svm_set_irq(struct kvm_vcpu *vcpu)
3417 {
3418         struct vcpu_svm *svm = to_svm(vcpu);
3419
3420         BUG_ON(!(gif_set(svm)));
3421
3422         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3423         ++vcpu->stat.irq_injections;
3424
3425         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3426                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3427 }
3428
3429 static void svm_update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3430 {
3431         struct vcpu_svm *svm = to_svm(vcpu);
3432
3433         /*
3434          * SEV-ES guests must always keep the CR intercepts cleared. CR
3435          * tracking is done using the CR write traps.
3436          */
3437         if (sev_es_guest(vcpu->kvm))
3438                 return;
3439
3440         if (nested_svm_virtualize_tpr(vcpu))
3441                 return;
3442
3443         svm_clr_intercept(svm, INTERCEPT_CR8_WRITE);
3444
3445         if (irr == -1)
3446                 return;
3447
3448         if (tpr >= irr)
3449                 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
3450 }
3451
3452 bool svm_nmi_blocked(struct kvm_vcpu *vcpu)
3453 {
3454         struct vcpu_svm *svm = to_svm(vcpu);
3455         struct vmcb *vmcb = svm->vmcb;
3456         bool ret;
3457
3458         if (!gif_set(svm))
3459                 return true;
3460
3461         if (is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3462                 return false;
3463
3464         ret = (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
3465               (vcpu->arch.hflags & HF_NMI_MASK);
3466
3467         return ret;
3468 }
3469
3470 static int svm_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3471 {
3472         struct vcpu_svm *svm = to_svm(vcpu);
3473         if (svm->nested.nested_run_pending)
3474                 return -EBUSY;
3475
3476         /* An NMI must not be injected into L2 if it's supposed to VM-Exit.  */
3477         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3478                 return -EBUSY;
3479
3480         return !svm_nmi_blocked(vcpu);
3481 }
3482
3483 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3484 {
3485         return !!(vcpu->arch.hflags & HF_NMI_MASK);
3486 }
3487
3488 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3489 {
3490         struct vcpu_svm *svm = to_svm(vcpu);
3491
3492         if (masked) {
3493                 vcpu->arch.hflags |= HF_NMI_MASK;
3494                 if (!sev_es_guest(vcpu->kvm))
3495                         svm_set_intercept(svm, INTERCEPT_IRET);
3496         } else {
3497                 vcpu->arch.hflags &= ~HF_NMI_MASK;
3498                 if (!sev_es_guest(vcpu->kvm))
3499                         svm_clr_intercept(svm, INTERCEPT_IRET);
3500         }
3501 }
3502
3503 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu)
3504 {
3505         struct vcpu_svm *svm = to_svm(vcpu);
3506         struct vmcb *vmcb = svm->vmcb;
3507
3508         if (!gif_set(svm))
3509                 return true;
3510
3511         if (sev_es_guest(vcpu->kvm)) {
3512                 /*
3513                  * SEV-ES guests to not expose RFLAGS. Use the VMCB interrupt mask
3514                  * bit to determine the state of the IF flag.
3515                  */
3516                 if (!(vmcb->control.int_state & SVM_GUEST_INTERRUPT_MASK))
3517                         return true;
3518         } else if (is_guest_mode(vcpu)) {
3519                 /* As long as interrupts are being delivered...  */
3520                 if ((svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK)
3521                     ? !(svm->vmcb01.ptr->save.rflags & X86_EFLAGS_IF)
3522                     : !(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3523                         return true;
3524
3525                 /* ... vmexits aren't blocked by the interrupt shadow  */
3526                 if (nested_exit_on_intr(svm))
3527                         return false;
3528         } else {
3529                 if (!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3530                         return true;
3531         }
3532
3533         return (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK);
3534 }
3535
3536 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3537 {
3538         struct vcpu_svm *svm = to_svm(vcpu);
3539         if (svm->nested.nested_run_pending)
3540                 return -EBUSY;
3541
3542         /*
3543          * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
3544          * e.g. if the IRQ arrived asynchronously after checking nested events.
3545          */
3546         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(svm))
3547                 return -EBUSY;
3548
3549         return !svm_interrupt_blocked(vcpu);
3550 }
3551
3552 static void svm_enable_irq_window(struct kvm_vcpu *vcpu)
3553 {
3554         struct vcpu_svm *svm = to_svm(vcpu);
3555
3556         /*
3557          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3558          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
3559          * get that intercept, this function will be called again though and
3560          * we'll get the vintr intercept. However, if the vGIF feature is
3561          * enabled, the STGI interception will not occur. Enable the irq
3562          * window under the assumption that the hardware will set the GIF.
3563          */
3564         if (vgif_enabled(svm) || gif_set(svm)) {
3565                 /*
3566                  * IRQ window is not needed when AVIC is enabled,
3567                  * unless we have pending ExtINT since it cannot be injected
3568                  * via AVIC. In such case, we need to temporarily disable AVIC,
3569                  * and fallback to injecting IRQ via V_IRQ.
3570                  */
3571                 svm_toggle_avic_for_irq_window(vcpu, false);
3572                 svm_set_vintr(svm);
3573         }
3574 }
3575
3576 static void svm_enable_nmi_window(struct kvm_vcpu *vcpu)
3577 {
3578         struct vcpu_svm *svm = to_svm(vcpu);
3579
3580         if ((vcpu->arch.hflags & (HF_NMI_MASK | HF_IRET_MASK)) == HF_NMI_MASK)
3581                 return; /* IRET will cause a vm exit */
3582
3583         if (!gif_set(svm)) {
3584                 if (vgif_enabled(svm))
3585                         svm_set_intercept(svm, INTERCEPT_STGI);
3586                 return; /* STGI will cause a vm exit */
3587         }
3588
3589         /*
3590          * Something prevents NMI from been injected. Single step over possible
3591          * problem (IRET or exception injection or interrupt shadow)
3592          */
3593         svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
3594         svm->nmi_singlestep = true;
3595         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3596 }
3597
3598 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3599 {
3600         return 0;
3601 }
3602
3603 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
3604 {
3605         return 0;
3606 }
3607
3608 void svm_flush_tlb(struct kvm_vcpu *vcpu)
3609 {
3610         struct vcpu_svm *svm = to_svm(vcpu);
3611
3612         /*
3613          * Flush only the current ASID even if the TLB flush was invoked via
3614          * kvm_flush_remote_tlbs().  Although flushing remote TLBs requires all
3615          * ASIDs to be flushed, KVM uses a single ASID for L1 and L2, and
3616          * unconditionally does a TLB flush on both nested VM-Enter and nested
3617          * VM-Exit (via kvm_mmu_reset_context()).
3618          */
3619         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3620                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3621         else
3622                 svm->current_vmcb->asid_generation--;
3623 }
3624
3625 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
3626 {
3627         struct vcpu_svm *svm = to_svm(vcpu);
3628
3629         invlpga(gva, svm->vmcb->control.asid);
3630 }
3631
3632 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3633 {
3634         struct vcpu_svm *svm = to_svm(vcpu);
3635
3636         if (nested_svm_virtualize_tpr(vcpu))
3637                 return;
3638
3639         if (!svm_is_intercept(svm, INTERCEPT_CR8_WRITE)) {
3640                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3641                 kvm_set_cr8(vcpu, cr8);
3642         }
3643 }
3644
3645 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3646 {
3647         struct vcpu_svm *svm = to_svm(vcpu);
3648         u64 cr8;
3649
3650         if (nested_svm_virtualize_tpr(vcpu) ||
3651             kvm_vcpu_apicv_active(vcpu))
3652                 return;
3653
3654         cr8 = kvm_get_cr8(vcpu);
3655         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3656         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3657 }
3658
3659 static void svm_complete_interrupts(struct kvm_vcpu *vcpu)
3660 {
3661         struct vcpu_svm *svm = to_svm(vcpu);
3662         u8 vector;
3663         int type;
3664         u32 exitintinfo = svm->vmcb->control.exit_int_info;
3665         unsigned int3_injected = svm->int3_injected;
3666
3667         svm->int3_injected = 0;
3668
3669         /*
3670          * If we've made progress since setting HF_IRET_MASK, we've
3671          * executed an IRET and can allow NMI injection.
3672          */
3673         if ((vcpu->arch.hflags & HF_IRET_MASK) &&
3674             (sev_es_guest(vcpu->kvm) ||
3675              kvm_rip_read(vcpu) != svm->nmi_iret_rip)) {
3676                 vcpu->arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3677                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3678         }
3679
3680         vcpu->arch.nmi_injected = false;
3681         kvm_clear_exception_queue(vcpu);
3682         kvm_clear_interrupt_queue(vcpu);
3683
3684         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3685                 return;
3686
3687         kvm_make_request(KVM_REQ_EVENT, vcpu);
3688
3689         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3690         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3691
3692         switch (type) {
3693         case SVM_EXITINTINFO_TYPE_NMI:
3694                 vcpu->arch.nmi_injected = true;
3695                 break;
3696         case SVM_EXITINTINFO_TYPE_EXEPT:
3697                 /*
3698                  * Never re-inject a #VC exception.
3699                  */
3700                 if (vector == X86_TRAP_VC)
3701                         break;
3702
3703                 /*
3704                  * In case of software exceptions, do not reinject the vector,
3705                  * but re-execute the instruction instead. Rewind RIP first
3706                  * if we emulated INT3 before.
3707                  */
3708                 if (kvm_exception_is_soft(vector)) {
3709                         if (vector == BP_VECTOR && int3_injected &&
3710                             kvm_is_linear_rip(vcpu, svm->int3_rip))
3711                                 kvm_rip_write(vcpu,
3712                                               kvm_rip_read(vcpu) - int3_injected);
3713                         break;
3714                 }
3715                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3716                         u32 err = svm->vmcb->control.exit_int_info_err;
3717                         kvm_requeue_exception_e(vcpu, vector, err);
3718
3719                 } else
3720                         kvm_requeue_exception(vcpu, vector);
3721                 break;
3722         case SVM_EXITINTINFO_TYPE_INTR:
3723                 kvm_queue_interrupt(vcpu, vector, false);
3724                 break;
3725         default:
3726                 break;
3727         }
3728 }
3729
3730 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3731 {
3732         struct vcpu_svm *svm = to_svm(vcpu);
3733         struct vmcb_control_area *control = &svm->vmcb->control;
3734
3735         control->exit_int_info = control->event_inj;
3736         control->exit_int_info_err = control->event_inj_err;
3737         control->event_inj = 0;
3738         svm_complete_interrupts(vcpu);
3739 }
3740
3741 static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
3742 {
3743         if (to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_MSR &&
3744             to_svm(vcpu)->vmcb->control.exit_info_1)
3745                 return handle_fastpath_set_msr_irqoff(vcpu);
3746
3747         return EXIT_FASTPATH_NONE;
3748 }
3749
3750 static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu)
3751 {
3752         struct vcpu_svm *svm = to_svm(vcpu);
3753         unsigned long vmcb_pa = svm->current_vmcb->pa;
3754
3755         kvm_guest_enter_irqoff();
3756
3757         if (sev_es_guest(vcpu->kvm)) {
3758                 __svm_sev_es_vcpu_run(vmcb_pa);
3759         } else {
3760                 struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3761
3762                 /*
3763                  * Use a single vmcb (vmcb01 because it's always valid) for
3764                  * context switching guest state via VMLOAD/VMSAVE, that way
3765                  * the state doesn't need to be copied between vmcb01 and
3766                  * vmcb02 when switching vmcbs for nested virtualization.
3767                  */
3768                 vmload(svm->vmcb01.pa);
3769                 __svm_vcpu_run(vmcb_pa, (unsigned long *)&vcpu->arch.regs);
3770                 vmsave(svm->vmcb01.pa);
3771
3772                 vmload(__sme_page_pa(sd->save_area));
3773         }
3774
3775         kvm_guest_exit_irqoff();
3776 }
3777
3778 static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu)
3779 {
3780         struct vcpu_svm *svm = to_svm(vcpu);
3781
3782         trace_kvm_entry(vcpu);
3783
3784         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3785         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3786         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3787
3788         /*
3789          * Disable singlestep if we're injecting an interrupt/exception.
3790          * We don't want our modified rflags to be pushed on the stack where
3791          * we might not be able to easily reset them if we disabled NMI
3792          * singlestep later.
3793          */
3794         if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
3795                 /*
3796                  * Event injection happens before external interrupts cause a
3797                  * vmexit and interrupts are disabled here, so smp_send_reschedule
3798                  * is enough to force an immediate vmexit.
3799                  */
3800                 disable_nmi_singlestep(svm);
3801                 smp_send_reschedule(vcpu->cpu);
3802         }
3803
3804         pre_svm_run(vcpu);
3805
3806         sync_lapic_to_cr8(vcpu);
3807
3808         if (unlikely(svm->asid != svm->vmcb->control.asid)) {
3809                 svm->vmcb->control.asid = svm->asid;
3810                 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
3811         }
3812         svm->vmcb->save.cr2 = vcpu->arch.cr2;
3813
3814         svm_hv_update_vp_id(svm->vmcb, vcpu);
3815
3816         /*
3817          * Run with all-zero DR6 unless needed, so that we can get the exact cause
3818          * of a #DB.
3819          */
3820         if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
3821                 svm_set_dr6(svm, vcpu->arch.dr6);
3822         else
3823                 svm_set_dr6(svm, DR6_ACTIVE_LOW);
3824
3825         clgi();
3826         kvm_load_guest_xsave_state(vcpu);
3827
3828         kvm_wait_lapic_expire(vcpu);
3829
3830         /*
3831          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
3832          * it's non-zero. Since vmentry is serialising on affected CPUs, there
3833          * is no need to worry about the conditional branch over the wrmsr
3834          * being speculatively taken.
3835          */
3836         if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL))
3837                 x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
3838
3839         svm_vcpu_enter_exit(vcpu);
3840
3841         /*
3842          * We do not use IBRS in the kernel. If this vCPU has used the
3843          * SPEC_CTRL MSR it may have left it on; save the value and
3844          * turn it off. This is much more efficient than blindly adding
3845          * it to the atomic save/restore list. Especially as the former
3846          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
3847          *
3848          * For non-nested case:
3849          * If the L01 MSR bitmap does not intercept the MSR, then we need to
3850          * save it.
3851          *
3852          * For nested case:
3853          * If the L02 MSR bitmap does not intercept the MSR, then we need to
3854          * save it.
3855          */
3856         if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL) &&
3857             unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
3858                 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
3859
3860         if (!sev_es_guest(vcpu->kvm))
3861                 reload_tss(vcpu);
3862
3863         if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL))
3864                 x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
3865
3866         if (!sev_es_guest(vcpu->kvm)) {
3867                 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3868                 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3869                 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3870                 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3871         }
3872
3873         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3874                 kvm_before_interrupt(vcpu);
3875
3876         kvm_load_host_xsave_state(vcpu);
3877         stgi();
3878
3879         /* Any pending NMI will happen here */
3880
3881         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3882                 kvm_after_interrupt(vcpu);
3883
3884         sync_cr8_to_lapic(vcpu);
3885
3886         svm->next_rip = 0;
3887         if (is_guest_mode(vcpu)) {
3888                 nested_sync_control_from_vmcb02(svm);
3889
3890                 /* Track VMRUNs that have made past consistency checking */
3891                 if (svm->nested.nested_run_pending &&
3892                     svm->vmcb->control.exit_code != SVM_EXIT_ERR)
3893                         ++vcpu->stat.nested_run;
3894
3895                 svm->nested.nested_run_pending = 0;
3896         }
3897
3898         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3899         vmcb_mark_all_clean(svm->vmcb);
3900
3901         /* if exit due to PF check for async PF */
3902         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3903                 vcpu->arch.apf.host_apf_flags =
3904                         kvm_read_and_reset_apf_flags();
3905
3906         if (npt_enabled)
3907                 kvm_register_clear_available(vcpu, VCPU_EXREG_PDPTR);
3908
3909         /*
3910          * We need to handle MC intercepts here before the vcpu has a chance to
3911          * change the physical cpu
3912          */
3913         if (unlikely(svm->vmcb->control.exit_code ==
3914                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
3915                 svm_handle_mce(vcpu);
3916
3917         svm_complete_interrupts(vcpu);
3918
3919         if (is_guest_mode(vcpu))
3920                 return EXIT_FASTPATH_NONE;
3921
3922         return svm_exit_handlers_fastpath(vcpu);
3923 }
3924
3925 static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, hpa_t root_hpa,
3926                              int root_level)
3927 {
3928         struct vcpu_svm *svm = to_svm(vcpu);
3929         unsigned long cr3;
3930
3931         if (npt_enabled) {
3932                 svm->vmcb->control.nested_cr3 = __sme_set(root_hpa);
3933                 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
3934
3935                 hv_track_root_tdp(vcpu, root_hpa);
3936
3937                 /* Loading L2's CR3 is handled by enter_svm_guest_mode.  */
3938                 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3939                         return;
3940                 cr3 = vcpu->arch.cr3;
3941         } else if (vcpu->arch.mmu->shadow_root_level >= PT64_ROOT_4LEVEL) {
3942                 cr3 = __sme_set(root_hpa) | kvm_get_active_pcid(vcpu);
3943         } else {
3944                 /* PCID in the guest should be impossible with a 32-bit MMU. */
3945                 WARN_ON_ONCE(kvm_get_active_pcid(vcpu));
3946                 cr3 = root_hpa;
3947         }
3948
3949         svm->vmcb->save.cr3 = cr3;
3950         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
3951 }
3952
3953 static int is_disabled(void)
3954 {
3955         u64 vm_cr;
3956
3957         rdmsrl(MSR_VM_CR, vm_cr);
3958         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3959                 return 1;
3960
3961         return 0;
3962 }
3963
3964 static void
3965 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3966 {
3967         /*
3968          * Patch in the VMMCALL instruction:
3969          */
3970         hypercall[0] = 0x0f;
3971         hypercall[1] = 0x01;
3972         hypercall[2] = 0xd9;
3973 }
3974
3975 static int __init svm_check_processor_compat(void)
3976 {
3977         return 0;
3978 }
3979
3980 static bool svm_cpu_has_accelerated_tpr(void)
3981 {
3982         return false;
3983 }
3984
3985 /*
3986  * The kvm parameter can be NULL (module initialization, or invocation before
3987  * VM creation). Be sure to check the kvm parameter before using it.
3988  */
3989 static bool svm_has_emulated_msr(struct kvm *kvm, u32 index)
3990 {
3991         switch (index) {
3992         case MSR_IA32_MCG_EXT_CTL:
3993         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3994                 return false;
3995         case MSR_IA32_SMBASE:
3996                 /* SEV-ES guests do not support SMM, so report false */
3997                 if (kvm && sev_es_guest(kvm))
3998                         return false;
3999                 break;
4000         default:
4001                 break;
4002         }
4003
4004         return true;
4005 }
4006
4007 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4008 {
4009         return 0;
4010 }
4011
4012 static void svm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
4013 {
4014         struct vcpu_svm *svm = to_svm(vcpu);
4015         struct kvm_cpuid_entry2 *best;
4016
4017         vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4018                                     boot_cpu_has(X86_FEATURE_XSAVE) &&
4019                                     boot_cpu_has(X86_FEATURE_XSAVES);
4020
4021         /* Update nrips enabled cache */
4022         svm->nrips_enabled = kvm_cpu_cap_has(X86_FEATURE_NRIPS) &&
4023                              guest_cpuid_has(vcpu, X86_FEATURE_NRIPS);
4024
4025         svm_recalc_instruction_intercepts(vcpu, svm);
4026
4027         /* For sev guests, the memory encryption bit is not reserved in CR3.  */
4028         if (sev_guest(vcpu->kvm)) {
4029                 best = kvm_find_cpuid_entry(vcpu, 0x8000001F, 0);
4030                 if (best)
4031                         vcpu->arch.reserved_gpa_bits &= ~(1UL << (best->ebx & 0x3f));
4032         }
4033
4034         if (kvm_vcpu_apicv_active(vcpu)) {
4035                 /*
4036                  * AVIC does not work with an x2APIC mode guest. If the X2APIC feature
4037                  * is exposed to the guest, disable AVIC.
4038                  */
4039                 if (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC))
4040                         kvm_request_apicv_update(vcpu->kvm, false,
4041                                                  APICV_INHIBIT_REASON_X2APIC);
4042
4043                 /*
4044                  * Currently, AVIC does not work with nested virtualization.
4045                  * So, we disable AVIC when cpuid for SVM is set in the L1 guest.
4046                  */
4047                 if (nested && guest_cpuid_has(vcpu, X86_FEATURE_SVM))
4048                         kvm_request_apicv_update(vcpu->kvm, false,
4049                                                  APICV_INHIBIT_REASON_NESTED);
4050         }
4051
4052         if (guest_cpuid_is_intel(vcpu)) {
4053                 /*
4054                  * We must intercept SYSENTER_EIP and SYSENTER_ESP
4055                  * accesses because the processor only stores 32 bits.
4056                  * For the same reason we cannot use virtual VMLOAD/VMSAVE.
4057                  */
4058                 svm_set_intercept(svm, INTERCEPT_VMLOAD);
4059                 svm_set_intercept(svm, INTERCEPT_VMSAVE);
4060                 svm->vmcb->control.virt_ext &= ~VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
4061
4062                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_EIP, 0, 0);
4063                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_ESP, 0, 0);
4064         } else {
4065                 /*
4066                  * If hardware supports Virtual VMLOAD VMSAVE then enable it
4067                  * in VMCB and clear intercepts to avoid #VMEXIT.
4068                  */
4069                 if (vls) {
4070                         svm_clr_intercept(svm, INTERCEPT_VMLOAD);
4071                         svm_clr_intercept(svm, INTERCEPT_VMSAVE);
4072                         svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
4073                 }
4074                 /* No need to intercept these MSRs */
4075                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
4076                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
4077         }
4078 }
4079
4080 static bool svm_has_wbinvd_exit(void)
4081 {
4082         return true;
4083 }
4084
4085 #define PRE_EX(exit)  { .exit_code = (exit), \
4086                         .stage = X86_ICPT_PRE_EXCEPT, }
4087 #define POST_EX(exit) { .exit_code = (exit), \
4088                         .stage = X86_ICPT_POST_EXCEPT, }
4089 #define POST_MEM(exit) { .exit_code = (exit), \
4090                         .stage = X86_ICPT_POST_MEMACCESS, }
4091
4092 static const struct __x86_intercept {
4093         u32 exit_code;
4094         enum x86_intercept_stage stage;
4095 } x86_intercept_map[] = {
4096         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
4097         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
4098         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
4099         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
4100         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
4101         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
4102         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
4103         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
4104         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
4105         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
4106         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
4107         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
4108         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
4109         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
4110         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
4111         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
4112         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
4113         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
4114         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
4115         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
4116         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
4117         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
4118         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
4119         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
4120         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
4121         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
4122         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
4123         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
4124         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
4125         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
4126         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
4127         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
4128         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
4129         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
4130         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
4131         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
4132         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
4133         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
4134         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
4135         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
4136         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
4137         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
4138         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
4139         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
4140         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
4141         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
4142         [x86_intercept_xsetbv]          = PRE_EX(SVM_EXIT_XSETBV),
4143 };
4144
4145 #undef PRE_EX
4146 #undef POST_EX
4147 #undef POST_MEM
4148
4149 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4150                                struct x86_instruction_info *info,
4151                                enum x86_intercept_stage stage,
4152                                struct x86_exception *exception)
4153 {
4154         struct vcpu_svm *svm = to_svm(vcpu);
4155         int vmexit, ret = X86EMUL_CONTINUE;
4156         struct __x86_intercept icpt_info;
4157         struct vmcb *vmcb = svm->vmcb;
4158
4159         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4160                 goto out;
4161
4162         icpt_info = x86_intercept_map[info->intercept];
4163
4164         if (stage != icpt_info.stage)
4165                 goto out;
4166
4167         switch (icpt_info.exit_code) {
4168         case SVM_EXIT_READ_CR0:
4169                 if (info->intercept == x86_intercept_cr_read)
4170                         icpt_info.exit_code += info->modrm_reg;
4171                 break;
4172         case SVM_EXIT_WRITE_CR0: {
4173                 unsigned long cr0, val;
4174
4175                 if (info->intercept == x86_intercept_cr_write)
4176                         icpt_info.exit_code += info->modrm_reg;
4177
4178                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
4179                     info->intercept == x86_intercept_clts)
4180                         break;
4181
4182                 if (!(vmcb_is_intercept(&svm->nested.ctl,
4183                                         INTERCEPT_SELECTIVE_CR0)))
4184                         break;
4185
4186                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4187                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
4188
4189                 if (info->intercept == x86_intercept_lmsw) {
4190                         cr0 &= 0xfUL;
4191                         val &= 0xfUL;
4192                         /* lmsw can't clear PE - catch this here */
4193                         if (cr0 & X86_CR0_PE)
4194                                 val |= X86_CR0_PE;
4195                 }
4196
4197                 if (cr0 ^ val)
4198                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4199
4200                 break;
4201         }
4202         case SVM_EXIT_READ_DR0:
4203         case SVM_EXIT_WRITE_DR0:
4204                 icpt_info.exit_code += info->modrm_reg;
4205                 break;
4206         case SVM_EXIT_MSR:
4207                 if (info->intercept == x86_intercept_wrmsr)
4208                         vmcb->control.exit_info_1 = 1;
4209                 else
4210                         vmcb->control.exit_info_1 = 0;
4211                 break;
4212         case SVM_EXIT_PAUSE:
4213                 /*
4214                  * We get this for NOP only, but pause
4215                  * is rep not, check this here
4216                  */
4217                 if (info->rep_prefix != REPE_PREFIX)
4218                         goto out;
4219                 break;
4220         case SVM_EXIT_IOIO: {
4221                 u64 exit_info;
4222                 u32 bytes;
4223
4224                 if (info->intercept == x86_intercept_in ||
4225                     info->intercept == x86_intercept_ins) {
4226                         exit_info = ((info->src_val & 0xffff) << 16) |
4227                                 SVM_IOIO_TYPE_MASK;
4228                         bytes = info->dst_bytes;
4229                 } else {
4230                         exit_info = (info->dst_val & 0xffff) << 16;
4231                         bytes = info->src_bytes;
4232                 }
4233
4234                 if (info->intercept == x86_intercept_outs ||
4235                     info->intercept == x86_intercept_ins)
4236                         exit_info |= SVM_IOIO_STR_MASK;
4237
4238                 if (info->rep_prefix)
4239                         exit_info |= SVM_IOIO_REP_MASK;
4240
4241                 bytes = min(bytes, 4u);
4242
4243                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4244
4245                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4246
4247                 vmcb->control.exit_info_1 = exit_info;
4248                 vmcb->control.exit_info_2 = info->next_rip;
4249
4250                 break;
4251         }
4252         default:
4253                 break;
4254         }
4255
4256         /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
4257         if (static_cpu_has(X86_FEATURE_NRIPS))
4258                 vmcb->control.next_rip  = info->next_rip;
4259         vmcb->control.exit_code = icpt_info.exit_code;
4260         vmexit = nested_svm_exit_handled(svm);
4261
4262         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4263                                            : X86EMUL_CONTINUE;
4264
4265 out:
4266         return ret;
4267 }
4268
4269 static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu)
4270 {
4271 }
4272
4273 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
4274 {
4275         if (!kvm_pause_in_guest(vcpu->kvm))
4276                 shrink_ple_window(vcpu);
4277 }
4278
4279 static void svm_setup_mce(struct kvm_vcpu *vcpu)
4280 {
4281         /* [63:9] are reserved. */
4282         vcpu->arch.mcg_cap &= 0x1ff;
4283 }
4284
4285 bool svm_smi_blocked(struct kvm_vcpu *vcpu)
4286 {
4287         struct vcpu_svm *svm = to_svm(vcpu);
4288
4289         /* Per APM Vol.2 15.22.2 "Response to SMI" */
4290         if (!gif_set(svm))
4291                 return true;
4292
4293         return is_smm(vcpu);
4294 }
4295
4296 static int svm_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4297 {
4298         struct vcpu_svm *svm = to_svm(vcpu);
4299         if (svm->nested.nested_run_pending)
4300                 return -EBUSY;
4301
4302         /* An SMI must not be injected into L2 if it's supposed to VM-Exit.  */
4303         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_smi(svm))
4304                 return -EBUSY;
4305
4306         return !svm_smi_blocked(vcpu);
4307 }
4308
4309 static int svm_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
4310 {
4311         struct vcpu_svm *svm = to_svm(vcpu);
4312         struct kvm_host_map map_save;
4313         int ret;
4314
4315         if (is_guest_mode(vcpu)) {
4316                 /* FED8h - SVM Guest */
4317                 put_smstate(u64, smstate, 0x7ed8, 1);
4318                 /* FEE0h - SVM Guest VMCB Physical Address */
4319                 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb12_gpa);
4320
4321                 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4322                 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4323                 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4324
4325                 ret = nested_svm_vmexit(svm);
4326                 if (ret)
4327                         return ret;
4328
4329                 /*
4330                  * KVM uses VMCB01 to store L1 host state while L2 runs but
4331                  * VMCB01 is going to be used during SMM and thus the state will
4332                  * be lost. Temporary save non-VMLOAD/VMSAVE state to the host save
4333                  * area pointed to by MSR_VM_HSAVE_PA. APM guarantees that the
4334                  * format of the area is identical to guest save area offsetted
4335                  * by 0x400 (matches the offset of 'struct vmcb_save_area'
4336                  * within 'struct vmcb'). Note: HSAVE area may also be used by
4337                  * L1 hypervisor to save additional host context (e.g. KVM does
4338                  * that, see svm_prepare_guest_switch()) which must be
4339                  * preserved.
4340                  */
4341                 if (kvm_vcpu_map(vcpu, gpa_to_gfn(svm->nested.hsave_msr),
4342                                  &map_save) == -EINVAL)
4343                         return 1;
4344
4345                 BUILD_BUG_ON(offsetof(struct vmcb, save) != 0x400);
4346
4347                 svm_copy_vmrun_state(&svm->vmcb01.ptr->save,
4348                                      map_save.hva + 0x400);
4349
4350                 kvm_vcpu_unmap(vcpu, &map_save, true);
4351         }
4352         return 0;
4353 }
4354
4355 static int svm_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
4356 {
4357         struct vcpu_svm *svm = to_svm(vcpu);
4358         struct kvm_host_map map, map_save;
4359         int ret = 0;
4360
4361         if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) {
4362                 u64 saved_efer = GET_SMSTATE(u64, smstate, 0x7ed0);
4363                 u64 guest = GET_SMSTATE(u64, smstate, 0x7ed8);
4364                 u64 vmcb12_gpa = GET_SMSTATE(u64, smstate, 0x7ee0);
4365                 struct vmcb *vmcb12;
4366
4367                 if (guest) {
4368                         if (!guest_cpuid_has(vcpu, X86_FEATURE_SVM))
4369                                 return 1;
4370
4371                         if (!(saved_efer & EFER_SVME))
4372                                 return 1;
4373
4374                         if (kvm_vcpu_map(vcpu,
4375                                          gpa_to_gfn(vmcb12_gpa), &map) == -EINVAL)
4376                                 return 1;
4377
4378                         if (svm_allocate_nested(svm))
4379                                 return 1;
4380
4381                         vmcb12 = map.hva;
4382
4383                         nested_load_control_from_vmcb12(svm, &vmcb12->control);
4384
4385                         ret = enter_svm_guest_mode(vcpu, vmcb12_gpa, vmcb12);
4386                         kvm_vcpu_unmap(vcpu, &map, true);
4387
4388                         /*
4389                          * Restore L1 host state from L1 HSAVE area as VMCB01 was
4390                          * used during SMM (see svm_enter_smm())
4391                          */
4392                         if (kvm_vcpu_map(vcpu, gpa_to_gfn(svm->nested.hsave_msr),
4393                                          &map_save) == -EINVAL)
4394                                 return 1;
4395
4396                         svm_copy_vmrun_state(map_save.hva + 0x400,
4397                                              &svm->vmcb01.ptr->save);
4398
4399                         kvm_vcpu_unmap(vcpu, &map_save, true);
4400                 }
4401         }
4402
4403         return ret;
4404 }
4405
4406 static void svm_enable_smi_window(struct kvm_vcpu *vcpu)
4407 {
4408         struct vcpu_svm *svm = to_svm(vcpu);
4409
4410         if (!gif_set(svm)) {
4411                 if (vgif_enabled(svm))
4412                         svm_set_intercept(svm, INTERCEPT_STGI);
4413                 /* STGI will cause a vm exit */
4414         } else {
4415                 /* We must be in SMM; RSM will cause a vmexit anyway.  */
4416         }
4417 }
4418
4419 static bool svm_can_emulate_instruction(struct kvm_vcpu *vcpu, void *insn, int insn_len)
4420 {
4421         bool smep, smap, is_user;
4422         unsigned long cr4;
4423
4424         /*
4425          * When the guest is an SEV-ES guest, emulation is not possible.
4426          */
4427         if (sev_es_guest(vcpu->kvm))
4428                 return false;
4429
4430         /*
4431          * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
4432          *
4433          * Errata:
4434          * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is
4435          * possible that CPU microcode implementing DecodeAssist will fail
4436          * to read bytes of instruction which caused #NPF. In this case,
4437          * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly
4438          * return 0 instead of the correct guest instruction bytes.
4439          *
4440          * This happens because CPU microcode reading instruction bytes
4441          * uses a special opcode which attempts to read data using CPL=0
4442          * privileges. The microcode reads CS:RIP and if it hits a SMAP
4443          * fault, it gives up and returns no instruction bytes.
4444          *
4445          * Detection:
4446          * We reach here in case CPU supports DecodeAssist, raised #NPF and
4447          * returned 0 in GuestIntrBytes field of the VMCB.
4448          * First, errata can only be triggered in case vCPU CR4.SMAP=1.
4449          * Second, if vCPU CR4.SMEP=1, errata could only be triggered
4450          * in case vCPU CPL==3 (Because otherwise guest would have triggered
4451          * a SMEP fault instead of #NPF).
4452          * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL.
4453          * As most guests enable SMAP if they have also enabled SMEP, use above
4454          * logic in order to attempt minimize false-positive of detecting errata
4455          * while still preserving all cases semantic correctness.
4456          *
4457          * Workaround:
4458          * To determine what instruction the guest was executing, the hypervisor
4459          * will have to decode the instruction at the instruction pointer.
4460          *
4461          * In non SEV guest, hypervisor will be able to read the guest
4462          * memory to decode the instruction pointer when insn_len is zero
4463          * so we return true to indicate that decoding is possible.
4464          *
4465          * But in the SEV guest, the guest memory is encrypted with the
4466          * guest specific key and hypervisor will not be able to decode the
4467          * instruction pointer so we will not able to workaround it. Lets
4468          * print the error and request to kill the guest.
4469          */
4470         if (likely(!insn || insn_len))
4471                 return true;
4472
4473         /*
4474          * If RIP is invalid, go ahead with emulation which will cause an
4475          * internal error exit.
4476          */
4477         if (!kvm_vcpu_gfn_to_memslot(vcpu, kvm_rip_read(vcpu) >> PAGE_SHIFT))
4478                 return true;
4479
4480         cr4 = kvm_read_cr4(vcpu);
4481         smep = cr4 & X86_CR4_SMEP;
4482         smap = cr4 & X86_CR4_SMAP;
4483         is_user = svm_get_cpl(vcpu) == 3;
4484         if (smap && (!smep || is_user)) {
4485                 if (!sev_guest(vcpu->kvm))
4486                         return true;
4487
4488                 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
4489                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4490         }
4491
4492         return false;
4493 }
4494
4495 static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
4496 {
4497         struct vcpu_svm *svm = to_svm(vcpu);
4498
4499         /*
4500          * TODO: Last condition latch INIT signals on vCPU when
4501          * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
4502          * To properly emulate the INIT intercept,
4503          * svm_check_nested_events() should call nested_svm_vmexit()
4504          * if an INIT signal is pending.
4505          */
4506         return !gif_set(svm) ||
4507                    (vmcb_is_intercept(&svm->vmcb->control, INTERCEPT_INIT));
4508 }
4509
4510 static void svm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
4511 {
4512         if (!sev_es_guest(vcpu->kvm))
4513                 return kvm_vcpu_deliver_sipi_vector(vcpu, vector);
4514
4515         sev_vcpu_deliver_sipi_vector(vcpu, vector);
4516 }
4517
4518 static void svm_vm_destroy(struct kvm *kvm)
4519 {
4520         avic_vm_destroy(kvm);
4521         sev_vm_destroy(kvm);
4522 }
4523
4524 static int svm_vm_init(struct kvm *kvm)
4525 {
4526         if (!pause_filter_count || !pause_filter_thresh)
4527                 kvm->arch.pause_in_guest = true;
4528
4529         if (enable_apicv) {
4530                 int ret = avic_vm_init(kvm);
4531                 if (ret)
4532                         return ret;
4533         }
4534
4535         return 0;
4536 }
4537
4538 static struct kvm_x86_ops svm_x86_ops __initdata = {
4539         .hardware_unsetup = svm_hardware_teardown,
4540         .hardware_enable = svm_hardware_enable,
4541         .hardware_disable = svm_hardware_disable,
4542         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4543         .has_emulated_msr = svm_has_emulated_msr,
4544
4545         .vcpu_create = svm_create_vcpu,
4546         .vcpu_free = svm_free_vcpu,
4547         .vcpu_reset = svm_vcpu_reset,
4548
4549         .vm_size = sizeof(struct kvm_svm),
4550         .vm_init = svm_vm_init,
4551         .vm_destroy = svm_vm_destroy,
4552
4553         .prepare_guest_switch = svm_prepare_guest_switch,
4554         .vcpu_load = svm_vcpu_load,
4555         .vcpu_put = svm_vcpu_put,
4556         .vcpu_blocking = svm_vcpu_blocking,
4557         .vcpu_unblocking = svm_vcpu_unblocking,
4558
4559         .update_exception_bitmap = svm_update_exception_bitmap,
4560         .get_msr_feature = svm_get_msr_feature,
4561         .get_msr = svm_get_msr,
4562         .set_msr = svm_set_msr,
4563         .get_segment_base = svm_get_segment_base,
4564         .get_segment = svm_get_segment,
4565         .set_segment = svm_set_segment,
4566         .get_cpl = svm_get_cpl,
4567         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4568         .set_cr0 = svm_set_cr0,
4569         .is_valid_cr4 = svm_is_valid_cr4,
4570         .set_cr4 = svm_set_cr4,
4571         .set_efer = svm_set_efer,
4572         .get_idt = svm_get_idt,
4573         .set_idt = svm_set_idt,
4574         .get_gdt = svm_get_gdt,
4575         .set_gdt = svm_set_gdt,
4576         .set_dr7 = svm_set_dr7,
4577         .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4578         .cache_reg = svm_cache_reg,
4579         .get_rflags = svm_get_rflags,
4580         .set_rflags = svm_set_rflags,
4581
4582         .tlb_flush_all = svm_flush_tlb,
4583         .tlb_flush_current = svm_flush_tlb,
4584         .tlb_flush_gva = svm_flush_tlb_gva,
4585         .tlb_flush_guest = svm_flush_tlb,
4586
4587         .run = svm_vcpu_run,
4588         .handle_exit = handle_exit,
4589         .skip_emulated_instruction = skip_emulated_instruction,
4590         .update_emulated_instruction = NULL,
4591         .set_interrupt_shadow = svm_set_interrupt_shadow,
4592         .get_interrupt_shadow = svm_get_interrupt_shadow,
4593         .patch_hypercall = svm_patch_hypercall,
4594         .set_irq = svm_set_irq,
4595         .set_nmi = svm_inject_nmi,
4596         .queue_exception = svm_queue_exception,
4597         .cancel_injection = svm_cancel_injection,
4598         .interrupt_allowed = svm_interrupt_allowed,
4599         .nmi_allowed = svm_nmi_allowed,
4600         .get_nmi_mask = svm_get_nmi_mask,
4601         .set_nmi_mask = svm_set_nmi_mask,
4602         .enable_nmi_window = svm_enable_nmi_window,
4603         .enable_irq_window = svm_enable_irq_window,
4604         .update_cr8_intercept = svm_update_cr8_intercept,
4605         .set_virtual_apic_mode = svm_set_virtual_apic_mode,
4606         .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
4607         .check_apicv_inhibit_reasons = svm_check_apicv_inhibit_reasons,
4608         .pre_update_apicv_exec_ctrl = svm_pre_update_apicv_exec_ctrl,
4609         .load_eoi_exitmap = svm_load_eoi_exitmap,
4610         .hwapic_irr_update = svm_hwapic_irr_update,
4611         .hwapic_isr_update = svm_hwapic_isr_update,
4612         .sync_pir_to_irr = kvm_lapic_find_highest_irr,
4613         .apicv_post_state_restore = avic_post_state_restore,
4614
4615         .set_tss_addr = svm_set_tss_addr,
4616         .set_identity_map_addr = svm_set_identity_map_addr,
4617         .get_mt_mask = svm_get_mt_mask,
4618
4619         .get_exit_info = svm_get_exit_info,
4620
4621         .vcpu_after_set_cpuid = svm_vcpu_after_set_cpuid,
4622
4623         .has_wbinvd_exit = svm_has_wbinvd_exit,
4624
4625         .get_l2_tsc_offset = svm_get_l2_tsc_offset,
4626         .get_l2_tsc_multiplier = svm_get_l2_tsc_multiplier,
4627         .write_tsc_offset = svm_write_tsc_offset,
4628         .write_tsc_multiplier = svm_write_tsc_multiplier,
4629
4630         .load_mmu_pgd = svm_load_mmu_pgd,
4631
4632         .check_intercept = svm_check_intercept,
4633         .handle_exit_irqoff = svm_handle_exit_irqoff,
4634
4635         .request_immediate_exit = __kvm_request_immediate_exit,
4636
4637         .sched_in = svm_sched_in,
4638
4639         .pmu_ops = &amd_pmu_ops,
4640         .nested_ops = &svm_nested_ops,
4641
4642         .deliver_posted_interrupt = svm_deliver_avic_intr,
4643         .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt,
4644         .update_pi_irte = svm_update_pi_irte,
4645         .setup_mce = svm_setup_mce,
4646
4647         .smi_allowed = svm_smi_allowed,
4648         .enter_smm = svm_enter_smm,
4649         .leave_smm = svm_leave_smm,
4650         .enable_smi_window = svm_enable_smi_window,
4651
4652         .mem_enc_op = svm_mem_enc_op,
4653         .mem_enc_reg_region = svm_register_enc_region,
4654         .mem_enc_unreg_region = svm_unregister_enc_region,
4655
4656         .vm_copy_enc_context_from = svm_vm_copy_asid_from,
4657
4658         .can_emulate_instruction = svm_can_emulate_instruction,
4659
4660         .apic_init_signal_blocked = svm_apic_init_signal_blocked,
4661
4662         .msr_filter_changed = svm_msr_filter_changed,
4663         .complete_emulated_msr = svm_complete_emulated_msr,
4664
4665         .vcpu_deliver_sipi_vector = svm_vcpu_deliver_sipi_vector,
4666 };
4667
4668 static struct kvm_x86_init_ops svm_init_ops __initdata = {
4669         .cpu_has_kvm_support = has_svm,
4670         .disabled_by_bios = is_disabled,
4671         .hardware_setup = svm_hardware_setup,
4672         .check_processor_compatibility = svm_check_processor_compat,
4673
4674         .runtime_ops = &svm_x86_ops,
4675 };
4676
4677 static int __init svm_init(void)
4678 {
4679         __unused_size_checks();
4680
4681         return kvm_init(&svm_init_ops, sizeof(struct vcpu_svm),
4682                         __alignof__(struct vcpu_svm), THIS_MODULE);
4683 }
4684
4685 static void __exit svm_exit(void)
4686 {
4687         kvm_exit();
4688 }
4689
4690 module_init(svm_init)
4691 module_exit(svm_exit)