arch/x86/kvm/pmu.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Kernel-based Virtual Machine -- Performance Monitoring Unit support
   4  *
   5  * Copyright 2015 Red Hat, Inc. and/or its affiliates.
   6  *
   7  * Authors:
   8  *   Avi Kivity   <avi@redhat.com>
   9  *   Gleb Natapov <gleb@redhat.com>
  10  *   Wei Huang    <wei@redhat.com>
  11  */
  12 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13
  14 #include <linux/types.h>
  15 #include <linux/kvm_host.h>
  16 #include <linux/perf_event.h>
  17 #include <linux/bsearch.h>
  18 #include <linux/sort.h>
  19 #include <asm/perf_event.h>
  20 #include <asm/cpu_device_id.h>
  21 #include "x86.h"
  22 #include "cpuid.h"
  23 #include "lapic.h"
  24 #include "pmu.h"
  25
  26 /* This is enough to filter the vast majority of currently defined events. */
  27 #define KVM_PMU_EVENT_FILTER_MAX_EVENTS 300
  28
  29 struct x86_pmu_capability __read_mostly kvm_pmu_cap;
  30 EXPORT_SYMBOL_GPL(kvm_pmu_cap);
  31
  32 /* Precise Distribution of Instructions Retired (PDIR) */
  33 static const struct x86_cpu_id vmx_pebs_pdir_cpu[] = {
  34         X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, NULL),
  35         X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, NULL),
  36         /* Instruction-Accurate PDIR (PDIR++) */
  37         X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, NULL),
  38         {}
  39 };
  40
  41 /* Precise Distribution (PDist) */
  42 static const struct x86_cpu_id vmx_pebs_pdist_cpu[] = {
  43         X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, NULL),
  44         {}
  45 };
  46
  47 /* NOTE:
  48  * - Each perf counter is defined as "struct kvm_pmc";
  49  * - There are two types of perf counters: general purpose (gp) and fixed.
  50  *   gp counters are stored in gp_counters[] and fixed counters are stored
  51  *   in fixed_counters[] respectively. Both of them are part of "struct
  52  *   kvm_pmu";
  53  * - pmu.c understands the difference between gp counters and fixed counters.
  54  *   However AMD doesn't support fixed-counters;
  55  * - There are three types of index to access perf counters (PMC):
  56  *     1. MSR (named msr): For example Intel has MSR_IA32_PERFCTRn and AMD
  57  *        has MSR_K7_PERFCTRn and, for families 15H and later,
  58  *        MSR_F15H_PERF_CTRn, where MSR_F15H_PERF_CTR[0-3] are
  59  *        aliased to MSR_K7_PERFCTRn.
  60  *     2. MSR Index (named idx): This normally is used by RDPMC instruction.
  61  *        For instance AMD RDPMC instruction uses 0000_0003h in ECX to access
  62  *        C001_0007h (MSR_K7_PERCTR3). Intel has a similar mechanism, except
  63  *        that it also supports fixed counters. idx can be used to as index to
  64  *        gp and fixed counters.
  65  *     3. Global PMC Index (named pmc): pmc is an index specific to PMU
  66  *        code. Each pmc, stored in kvm_pmc.idx field, is unique across
  67  *        all perf counters (both gp and fixed). The mapping relationship
  68  *        between pmc and perf counters is as the following:
  69  *        * Intel: [0 .. KVM_INTEL_PMC_MAX_GENERIC-1] <=> gp counters
  70  *                 [INTEL_PMC_IDX_FIXED .. INTEL_PMC_IDX_FIXED + 2] <=> fixed
  71  *        * AMD:   [0 .. AMD64_NUM_COUNTERS-1] and, for families 15H
  72  *          and later, [0 .. AMD64_NUM_COUNTERS_CORE-1] <=> gp counters
  73  */
  74
  75 static struct kvm_pmu_ops kvm_pmu_ops __read_mostly;
  76
  77 #define KVM_X86_PMU_OP(func)                                         \
  78         DEFINE_STATIC_CALL_NULL(kvm_x86_pmu_##func,                          \
  79                                 *(((struct kvm_pmu_ops *)0)->func));
  80 #define KVM_X86_PMU_OP_OPTIONAL KVM_X86_PMU_OP
  81 #include <asm/kvm-x86-pmu-ops.h>
  82
  83 void kvm_pmu_ops_update(const struct kvm_pmu_ops *pmu_ops)
  84 {
  85         memcpy(&kvm_pmu_ops, pmu_ops, sizeof(kvm_pmu_ops));
  86
  87 #define __KVM_X86_PMU_OP(func) \
  88         static_call_update(kvm_x86_pmu_##func, kvm_pmu_ops.func);
  89 #define KVM_X86_PMU_OP(func) \
  90         WARN_ON(!kvm_pmu_ops.func); __KVM_X86_PMU_OP(func)
  91 #define KVM_X86_PMU_OP_OPTIONAL __KVM_X86_PMU_OP
  92 #include <asm/kvm-x86-pmu-ops.h>
  93 #undef __KVM_X86_PMU_OP
  94 }
  95
  96 static inline void __kvm_perf_overflow(struct kvm_pmc *pmc, bool in_pmi)
  97 {
  98         struct kvm_pmu *pmu = pmc_to_pmu(pmc);
  99         bool skip_pmi = false;
 100
 101         if (pmc->perf_event && pmc->perf_event->attr.precise_ip) {
 102                 if (!in_pmi) {
 103                         /*
 104                          * TODO: KVM is currently _choosing_ to not generate records
 105                          * for emulated instructions, avoiding BUFFER_OVF PMI when
 106                          * there are no records. Strictly speaking, it should be done
 107                          * as well in the right context to improve sampling accuracy.
 108                          */
 109                         skip_pmi = true;
 110                 } else {
 111                         /* Indicate PEBS overflow PMI to guest. */
 112                         skip_pmi = __test_and_set_bit(GLOBAL_STATUS_BUFFER_OVF_BIT,
 113                                                       (unsigned long *)&pmu->global_status);
 114                 }
 115         } else {
 116                 __set_bit(pmc->idx, (unsigned long *)&pmu->global_status);
 117         }
 118
 119         if (pmc->intr && !skip_pmi)
 120                 kvm_make_request(KVM_REQ_PMI, pmc->vcpu);
 121 }
 122
 123 static void kvm_perf_overflow(struct perf_event *perf_event,
 124                               struct perf_sample_data *data,
 125                               struct pt_regs *regs)
 126 {
 127         struct kvm_pmc *pmc = perf_event->overflow_handler_context;
 128
 129         /*
 130          * Ignore overflow events for counters that are scheduled to be
 131          * reprogrammed, e.g. if a PMI for the previous event races with KVM's
 132          * handling of a related guest WRMSR.
 133          */
 134         if (test_and_set_bit(pmc->idx, pmc_to_pmu(pmc)->reprogram_pmi))
 135                 return;
 136
 137         __kvm_perf_overflow(pmc, true);
 138
 139         kvm_make_request(KVM_REQ_PMU, pmc->vcpu);
 140 }
 141
 142 static u64 pmc_get_pebs_precise_level(struct kvm_pmc *pmc)
 143 {
 144         /*
 145          * For some model specific pebs counters with special capabilities
 146          * (PDIR, PDIR++, PDIST), KVM needs to raise the event precise
 147          * level to the maximum value (currently 3, backwards compatible)
 148          * so that the perf subsystem would assign specific hardware counter
 149          * with that capability for vPMC.
 150          */
 151         if ((pmc->idx == 0 && x86_match_cpu(vmx_pebs_pdist_cpu)) ||
 152             (pmc->idx == 32 && x86_match_cpu(vmx_pebs_pdir_cpu)))
 153                 return 3;
 154
 155         /*
 156          * The non-zero precision level of guest event makes the ordinary
 157          * guest event becomes a guest PEBS event and triggers the host
 158          * PEBS PMI handler to determine whether the PEBS overflow PMI
 159          * comes from the host counters or the guest.
 160          */
 161         return 1;
 162 }
 163
 164 static int pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type, u64 config,
 165                                  bool exclude_user, bool exclude_kernel,
 166                                  bool intr)
 167 {
 168         struct kvm_pmu *pmu = pmc_to_pmu(pmc);
 169         struct perf_event *event;
 170         struct perf_event_attr attr = {
 171                 .type = type,
 172                 .size = sizeof(attr),
 173                 .pinned = true,
 174                 .exclude_idle = true,
 175                 .exclude_host = 1,
 176                 .exclude_user = exclude_user,
 177                 .exclude_kernel = exclude_kernel,
 178                 .config = config,
 179         };
 180         bool pebs = test_bit(pmc->idx, (unsigned long *)&pmu->pebs_enable);
 181
 182         attr.sample_period = get_sample_period(pmc, pmc->counter);
 183
 184         if ((attr.config & HSW_IN_TX_CHECKPOINTED) &&
 185             guest_cpuid_is_intel(pmc->vcpu)) {
 186                 /*
 187                  * HSW_IN_TX_CHECKPOINTED is not supported with nonzero
 188                  * period. Just clear the sample period so at least
 189                  * allocating the counter doesn't fail.
 190                  */
 191                 attr.sample_period = 0;
 192         }
 193         if (pebs) {
 194                 /*
 195                  * For most PEBS hardware events, the difference in the software
 196                  * precision levels of guest and host PEBS events will not affect
 197                  * the accuracy of the PEBS profiling result, because the "event IP"
 198                  * in the PEBS record is calibrated on the guest side.
 199                  */
 200                 attr.precise_ip = pmc_get_pebs_precise_level(pmc);
 201         }
 202
 203         event = perf_event_create_kernel_counter(&attr, -1, current,
 204                                                  kvm_perf_overflow, pmc);
 205         if (IS_ERR(event)) {
 206                 pr_debug_ratelimited("kvm_pmu: event creation failed %ld for pmc->idx = %d\n",
 207                             PTR_ERR(event), pmc->idx);
 208                 return PTR_ERR(event);
 209         }
 210
 211         pmc->perf_event = event;
 212         pmc_to_pmu(pmc)->event_count++;
 213         pmc->is_paused = false;
 214         pmc->intr = intr || pebs;
 215         return 0;
 216 }
 217
 218 static void pmc_pause_counter(struct kvm_pmc *pmc)
 219 {
 220         u64 counter = pmc->counter;
 221
 222         if (!pmc->perf_event || pmc->is_paused)
 223                 return;
 224
 225         /* update counter, reset event value to avoid redundant accumulation */
 226         counter += perf_event_pause(pmc->perf_event, true);
 227         pmc->counter = counter & pmc_bitmask(pmc);
 228         pmc->is_paused = true;
 229 }
 230
 231 static bool pmc_resume_counter(struct kvm_pmc *pmc)
 232 {
 233         if (!pmc->perf_event)
 234                 return false;
 235
 236         /* recalibrate sample period and check if it's accepted by perf core */
 237         if (is_sampling_event(pmc->perf_event) &&
 238             perf_event_period(pmc->perf_event,
 239                               get_sample_period(pmc, pmc->counter)))
 240                 return false;
 241
 242         if (test_bit(pmc->idx, (unsigned long *)&pmc_to_pmu(pmc)->pebs_enable) !=
 243             (!!pmc->perf_event->attr.precise_ip))
 244                 return false;
 245
 246         /* reuse perf_event to serve as pmc_reprogram_counter() does*/
 247         perf_event_enable(pmc->perf_event);
 248         pmc->is_paused = false;
 249
 250         return true;
 251 }
 252
 253 static int filter_cmp(const void *pa, const void *pb, u64 mask)
 254 {
 255         u64 a = *(u64 *)pa & mask;
 256         u64 b = *(u64 *)pb & mask;
 257
 258         return (a > b) - (a < b);
 259 }
 260
 261
 262 static int filter_sort_cmp(const void *pa, const void *pb)
 263 {
 264         return filter_cmp(pa, pb, (KVM_PMU_MASKED_ENTRY_EVENT_SELECT |
 265                                    KVM_PMU_MASKED_ENTRY_EXCLUDE));
 266 }
 267
 268 /*
 269  * For the event filter, searching is done on the 'includes' list and
 270  * 'excludes' list separately rather than on the 'events' list (which
 271  * has both).  As a result the exclude bit can be ignored.
 272  */
 273 static int filter_event_cmp(const void *pa, const void *pb)
 274 {
 275         return filter_cmp(pa, pb, (KVM_PMU_MASKED_ENTRY_EVENT_SELECT));
 276 }
 277
 278 static int find_filter_index(u64 *events, u64 nevents, u64 key)
 279 {
 280         u64 *fe = bsearch(&key, events, nevents, sizeof(events[0]),
 281                           filter_event_cmp);
 282
 283         if (!fe)
 284                 return -1;
 285
 286         return fe - events;
 287 }
 288
 289 static bool is_filter_entry_match(u64 filter_event, u64 umask)
 290 {
 291         u64 mask = filter_event >> (KVM_PMU_MASKED_ENTRY_UMASK_MASK_SHIFT - 8);
 292         u64 match = filter_event & KVM_PMU_MASKED_ENTRY_UMASK_MATCH;
 293
 294         BUILD_BUG_ON((KVM_PMU_ENCODE_MASKED_ENTRY(0, 0xff, 0, false) >>
 295                      (KVM_PMU_MASKED_ENTRY_UMASK_MASK_SHIFT - 8)) !=
 296                      ARCH_PERFMON_EVENTSEL_UMASK);
 297
 298         return (umask & mask) == match;
 299 }
 300
 301 static bool filter_contains_match(u64 *events, u64 nevents, u64 eventsel)
 302 {
 303         u64 event_select = eventsel & kvm_pmu_ops.EVENTSEL_EVENT;
 304         u64 umask = eventsel & ARCH_PERFMON_EVENTSEL_UMASK;
 305         int i, index;
 306
 307         index = find_filter_index(events, nevents, event_select);
 308         if (index < 0)
 309                 return false;
 310
 311         /*
 312          * Entries are sorted by the event select.  Walk the list in both
 313          * directions to process all entries with the targeted event select.
 314          */
 315         for (i = index; i < nevents; i++) {
 316                 if (filter_event_cmp(&events[i], &event_select))
 317                         break;
 318
 319                 if (is_filter_entry_match(events[i], umask))
 320                         return true;
 321         }
 322
 323         for (i = index - 1; i >= 0; i--) {
 324                 if (filter_event_cmp(&events[i], &event_select))
 325                         break;
 326
 327                 if (is_filter_entry_match(events[i], umask))
 328                         return true;
 329         }
 330
 331         return false;
 332 }
 333
 334 static bool is_gp_event_allowed(struct kvm_x86_pmu_event_filter *f,
 335                                 u64 eventsel)
 336 {
 337         if (filter_contains_match(f->includes, f->nr_includes, eventsel) &&
 338             !filter_contains_match(f->excludes, f->nr_excludes, eventsel))
 339                 return f->action == KVM_PMU_EVENT_ALLOW;
 340
 341         return f->action == KVM_PMU_EVENT_DENY;
 342 }
 343
 344 static bool is_fixed_event_allowed(struct kvm_x86_pmu_event_filter *filter,
 345                                    int idx)
 346 {
 347         int fixed_idx = idx - INTEL_PMC_IDX_FIXED;
 348
 349         if (filter->action == KVM_PMU_EVENT_DENY &&
 350             test_bit(fixed_idx, (ulong *)&filter->fixed_counter_bitmap))
 351                 return false;
 352         if (filter->action == KVM_PMU_EVENT_ALLOW &&
 353             !test_bit(fixed_idx, (ulong *)&filter->fixed_counter_bitmap))
 354                 return false;
 355
 356         return true;
 357 }
 358
 359 static bool check_pmu_event_filter(struct kvm_pmc *pmc)
 360 {
 361         struct kvm_x86_pmu_event_filter *filter;
 362         struct kvm *kvm = pmc->vcpu->kvm;
 363
 364         filter = srcu_dereference(kvm->arch.pmu_event_filter, &kvm->srcu);
 365         if (!filter)
 366                 return true;
 367
 368         if (pmc_is_gp(pmc))
 369                 return is_gp_event_allowed(filter, pmc->eventsel);
 370
 371         return is_fixed_event_allowed(filter, pmc->idx);
 372 }
 373
 374 static bool pmc_event_is_allowed(struct kvm_pmc *pmc)
 375 {
 376         return pmc_is_globally_enabled(pmc) && pmc_speculative_in_use(pmc) &&
 377                static_call(kvm_x86_pmu_hw_event_available)(pmc) &&
 378                check_pmu_event_filter(pmc);
 379 }
 380
 381 static void reprogram_counter(struct kvm_pmc *pmc)
 382 {
 383         struct kvm_pmu *pmu = pmc_to_pmu(pmc);
 384         u64 eventsel = pmc->eventsel;
 385         u64 new_config = eventsel;
 386         u8 fixed_ctr_ctrl;
 387
 388         pmc_pause_counter(pmc);
 389
 390         if (!pmc_event_is_allowed(pmc))
 391                 goto reprogram_complete;
 392
 393         if (pmc->counter < pmc->prev_counter)
 394                 __kvm_perf_overflow(pmc, false);
 395
 396         if (eventsel & ARCH_PERFMON_EVENTSEL_PIN_CONTROL)
 397                 printk_once("kvm pmu: pin control bit is ignored\n");
 398
 399         if (pmc_is_fixed(pmc)) {
 400                 fixed_ctr_ctrl = fixed_ctrl_field(pmu->fixed_ctr_ctrl,
 401                                                   pmc->idx - INTEL_PMC_IDX_FIXED);
 402                 if (fixed_ctr_ctrl & 0x1)
 403                         eventsel |= ARCH_PERFMON_EVENTSEL_OS;
 404                 if (fixed_ctr_ctrl & 0x2)
 405                         eventsel |= ARCH_PERFMON_EVENTSEL_USR;
 406                 if (fixed_ctr_ctrl & 0x8)
 407                         eventsel |= ARCH_PERFMON_EVENTSEL_INT;
 408                 new_config = (u64)fixed_ctr_ctrl;
 409         }
 410
 411         if (pmc->current_config == new_config && pmc_resume_counter(pmc))
 412                 goto reprogram_complete;
 413
 414         pmc_release_perf_event(pmc);
 415
 416         pmc->current_config = new_config;
 417
 418         /*
 419          * If reprogramming fails, e.g. due to contention, leave the counter's
 420          * regprogram bit set, i.e. opportunistically try again on the next PMU
 421          * refresh.  Don't make a new request as doing so can stall the guest
 422          * if reprogramming repeatedly fails.
 423          */
 424         if (pmc_reprogram_counter(pmc, PERF_TYPE_RAW,
 425                                   (eventsel & pmu->raw_event_mask),
 426                                   !(eventsel & ARCH_PERFMON_EVENTSEL_USR),
 427                                   !(eventsel & ARCH_PERFMON_EVENTSEL_OS),
 428                                   eventsel & ARCH_PERFMON_EVENTSEL_INT))
 429                 return;
 430
 431 reprogram_complete:
 432         clear_bit(pmc->idx, (unsigned long *)&pmc_to_pmu(pmc)->reprogram_pmi);
 433         pmc->prev_counter = 0;
 434 }
 435
 436 void kvm_pmu_handle_event(struct kvm_vcpu *vcpu)
 437 {
 438         struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
 439         int bit;
 440
 441         for_each_set_bit(bit, pmu->reprogram_pmi, X86_PMC_IDX_MAX) {
 442                 struct kvm_pmc *pmc = static_call(kvm_x86_pmu_pmc_idx_to_pmc)(pmu, bit);
 443
 444                 if (unlikely(!pmc)) {
 445                         clear_bit(bit, pmu->reprogram_pmi);
 446                         continue;
 447                 }
 448
 449                 reprogram_counter(pmc);
 450         }
 451
 452         /*
 453          * Unused perf_events are only released if the corresponding MSRs
 454          * weren't accessed during the last vCPU time slice. kvm_arch_sched_in
 455          * triggers KVM_REQ_PMU if cleanup is needed.
 456          */
 457         if (unlikely(pmu->need_cleanup))
 458                 kvm_pmu_cleanup(vcpu);
 459 }
 460
 461 /* check if idx is a valid index to access PMU */
 462 bool kvm_pmu_is_valid_rdpmc_ecx(struct kvm_vcpu *vcpu, unsigned int idx)
 463 {
 464         return static_call(kvm_x86_pmu_is_valid_rdpmc_ecx)(vcpu, idx);
 465 }
 466
 467 bool is_vmware_backdoor_pmc(u32 pmc_idx)
 468 {
 469         switch (pmc_idx) {
 470         case VMWARE_BACKDOOR_PMC_HOST_TSC:
 471         case VMWARE_BACKDOOR_PMC_REAL_TIME:
 472         case VMWARE_BACKDOOR_PMC_APPARENT_TIME:
 473                 return true;
 474         }
 475         return false;
 476 }
 477
 478 static int kvm_pmu_rdpmc_vmware(struct kvm_vcpu *vcpu, unsigned idx, u64 *data)
 479 {
 480         u64 ctr_val;
 481
 482         switch (idx) {
 483         case VMWARE_BACKDOOR_PMC_HOST_TSC:
 484                 ctr_val = rdtsc();
 485                 break;
 486         case VMWARE_BACKDOOR_PMC_REAL_TIME:
 487                 ctr_val = ktime_get_boottime_ns();
 488                 break;
 489         case VMWARE_BACKDOOR_PMC_APPARENT_TIME:
 490                 ctr_val = ktime_get_boottime_ns() +
 491                         vcpu->kvm->arch.kvmclock_offset;
 492                 break;
 493         default:
 494                 return 1;
 495         }
 496
 497         *data = ctr_val;
 498         return 0;
 499 }
 500
 501 int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned idx, u64 *data)
 502 {
 503         bool fast_mode = idx & (1u << 31);
 504         struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
 505         struct kvm_pmc *pmc;
 506         u64 mask = fast_mode ? ~0u : ~0ull;
 507
 508         if (!pmu->version)
 509                 return 1;
 510
 511         if (is_vmware_backdoor_pmc(idx))
 512                 return kvm_pmu_rdpmc_vmware(vcpu, idx, data);
 513
 514         pmc = static_call(kvm_x86_pmu_rdpmc_ecx_to_pmc)(vcpu, idx, &mask);
 515         if (!pmc)
 516                 return 1;
 517
 518         if (!kvm_is_cr4_bit_set(vcpu, X86_CR4_PCE) &&
 519             (static_call(kvm_x86_get_cpl)(vcpu) != 0) &&
 520             kvm_is_cr0_bit_set(vcpu, X86_CR0_PE))
 521                 return 1;
 522
 523         *data = pmc_read_counter(pmc) & mask;
 524         return 0;
 525 }
 526
 527 void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu)
 528 {
 529         if (lapic_in_kernel(vcpu)) {
 530                 static_call_cond(kvm_x86_pmu_deliver_pmi)(vcpu);
 531                 kvm_apic_local_deliver(vcpu->arch.apic, APIC_LVTPC);
 532         }
 533 }
 534
 535 bool kvm_pmu_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr)
 536 {
 537         switch (msr) {
 538         case MSR_CORE_PERF_GLOBAL_STATUS:
 539         case MSR_CORE_PERF_GLOBAL_CTRL:
 540         case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
 541                 return kvm_pmu_has_perf_global_ctrl(vcpu_to_pmu(vcpu));
 542         default:
 543                 break;
 544         }
 545         return static_call(kvm_x86_pmu_msr_idx_to_pmc)(vcpu, msr) ||
 546                 static_call(kvm_x86_pmu_is_valid_msr)(vcpu, msr);
 547 }
 548
 549 static void kvm_pmu_mark_pmc_in_use(struct kvm_vcpu *vcpu, u32 msr)
 550 {
 551         struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
 552         struct kvm_pmc *pmc = static_call(kvm_x86_pmu_msr_idx_to_pmc)(vcpu, msr);
 553
 554         if (pmc)
 555                 __set_bit(pmc->idx, pmu->pmc_in_use);
 556 }
 557
 558 int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 559 {
 560         struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
 561         u32 msr = msr_info->index;
 562
 563         switch (msr) {
 564         case MSR_CORE_PERF_GLOBAL_STATUS:
 565         case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS:
 566                 msr_info->data = pmu->global_status;
 567                 break;
 568         case MSR_AMD64_PERF_CNTR_GLOBAL_CTL:
 569         case MSR_CORE_PERF_GLOBAL_CTRL:
 570                 msr_info->data = pmu->global_ctrl;
 571                 break;
 572         case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR:
 573         case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
 574                 msr_info->data = 0;
 575                 break;
 576         default:
 577                 return static_call(kvm_x86_pmu_get_msr)(vcpu, msr_info);
 578         }
 579
 580         return 0;
 581 }
 582
 583 int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 584 {
 585         struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
 586         u32 msr = msr_info->index;
 587         u64 data = msr_info->data;
 588         u64 diff;
 589
 590         /*
 591          * Note, AMD ignores writes to reserved bits and read-only PMU MSRs,
 592          * whereas Intel generates #GP on attempts to write reserved/RO MSRs.
 593          */
 594         switch (msr) {
 595         case MSR_CORE_PERF_GLOBAL_STATUS:
 596                 if (!msr_info->host_initiated)
 597                         return 1; /* RO MSR */
 598                 fallthrough;
 599         case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS:
 600                 /* Per PPR, Read-only MSR. Writes are ignored. */
 601                 if (!msr_info->host_initiated)
 602                         break;
 603
 604                 if (data & pmu->global_status_mask)
 605                         return 1;
 606
 607                 pmu->global_status = data;
 608                 break;
 609         case MSR_AMD64_PERF_CNTR_GLOBAL_CTL:
 610                 data &= ~pmu->global_ctrl_mask;
 611                 fallthrough;
 612         case MSR_CORE_PERF_GLOBAL_CTRL:
 613                 if (!kvm_valid_perf_global_ctrl(pmu, data))
 614                         return 1;
 615
 616                 if (pmu->global_ctrl != data) {
 617                         diff = pmu->global_ctrl ^ data;
 618                         pmu->global_ctrl = data;
 619                         reprogram_counters(pmu, diff);
 620                 }
 621                 break;
 622         case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
 623                 /*
 624                  * GLOBAL_OVF_CTRL, a.k.a. GLOBAL STATUS_RESET, clears bits in
 625                  * GLOBAL_STATUS, and so the set of reserved bits is the same.
 626                  */
 627                 if (data & pmu->global_status_mask)
 628                         return 1;
 629                 fallthrough;
 630         case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR:
 631                 if (!msr_info->host_initiated)
 632                         pmu->global_status &= ~data;
 633                 break;
 634         default:
 635                 kvm_pmu_mark_pmc_in_use(vcpu, msr_info->index);
 636                 return static_call(kvm_x86_pmu_set_msr)(vcpu, msr_info);
 637         }
 638
 639         return 0;
 640 }
 641
 642 /* refresh PMU settings. This function generally is called when underlying
 643  * settings are changed (such as changes of PMU CPUID by guest VMs), which
 644  * should rarely happen.
 645  */
 646 void kvm_pmu_refresh(struct kvm_vcpu *vcpu)
 647 {
 648         if (KVM_BUG_ON(kvm_vcpu_has_run(vcpu), vcpu->kvm))
 649                 return;
 650
 651         bitmap_zero(vcpu_to_pmu(vcpu)->all_valid_pmc_idx, X86_PMC_IDX_MAX);
 652         static_call(kvm_x86_pmu_refresh)(vcpu);
 653 }
 654
 655 void kvm_pmu_reset(struct kvm_vcpu *vcpu)
 656 {
 657         static_call(kvm_x86_pmu_reset)(vcpu);
 658 }
 659
 660 void kvm_pmu_init(struct kvm_vcpu *vcpu)
 661 {
 662         struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
 663
 664         memset(pmu, 0, sizeof(*pmu));
 665         static_call(kvm_x86_pmu_init)(vcpu);
 666         pmu->event_count = 0;
 667         pmu->need_cleanup = false;
 668         kvm_pmu_refresh(vcpu);
 669 }
 670
 671 /* Release perf_events for vPMCs that have been unused for a full time slice.  */
 672 void kvm_pmu_cleanup(struct kvm_vcpu *vcpu)
 673 {
 674         struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
 675         struct kvm_pmc *pmc = NULL;
 676         DECLARE_BITMAP(bitmask, X86_PMC_IDX_MAX);
 677         int i;
 678
 679         pmu->need_cleanup = false;
 680
 681         bitmap_andnot(bitmask, pmu->all_valid_pmc_idx,
 682                       pmu->pmc_in_use, X86_PMC_IDX_MAX);
 683
 684         for_each_set_bit(i, bitmask, X86_PMC_IDX_MAX) {
 685                 pmc = static_call(kvm_x86_pmu_pmc_idx_to_pmc)(pmu, i);
 686
 687                 if (pmc && pmc->perf_event && !pmc_speculative_in_use(pmc))
 688                         pmc_stop_counter(pmc);
 689         }
 690
 691         static_call_cond(kvm_x86_pmu_cleanup)(vcpu);
 692
 693         bitmap_zero(pmu->pmc_in_use, X86_PMC_IDX_MAX);
 694 }
 695
 696 void kvm_pmu_destroy(struct kvm_vcpu *vcpu)
 697 {
 698         kvm_pmu_reset(vcpu);
 699 }
 700
 701 static void kvm_pmu_incr_counter(struct kvm_pmc *pmc)
 702 {
 703         pmc->prev_counter = pmc->counter;
 704         pmc->counter = (pmc->counter + 1) & pmc_bitmask(pmc);
 705         kvm_pmu_request_counter_reprogram(pmc);
 706 }
 707
 708 static inline bool eventsel_match_perf_hw_id(struct kvm_pmc *pmc,
 709         unsigned int perf_hw_id)
 710 {
 711         return !((pmc->eventsel ^ perf_get_hw_event_config(perf_hw_id)) &
 712                 AMD64_RAW_EVENT_MASK_NB);
 713 }
 714
 715 static inline bool cpl_is_matched(struct kvm_pmc *pmc)
 716 {
 717         bool select_os, select_user;
 718         u64 config;
 719
 720         if (pmc_is_gp(pmc)) {
 721                 config = pmc->eventsel;
 722                 select_os = config & ARCH_PERFMON_EVENTSEL_OS;
 723                 select_user = config & ARCH_PERFMON_EVENTSEL_USR;
 724         } else {
 725                 config = fixed_ctrl_field(pmc_to_pmu(pmc)->fixed_ctr_ctrl,
 726                                           pmc->idx - INTEL_PMC_IDX_FIXED);
 727                 select_os = config & 0x1;
 728                 select_user = config & 0x2;
 729         }
 730
 731         return (static_call(kvm_x86_get_cpl)(pmc->vcpu) == 0) ? select_os : select_user;
 732 }
 733
 734 void kvm_pmu_trigger_event(struct kvm_vcpu *vcpu, u64 perf_hw_id)
 735 {
 736         struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
 737         struct kvm_pmc *pmc;
 738         int i;
 739
 740         for_each_set_bit(i, pmu->all_valid_pmc_idx, X86_PMC_IDX_MAX) {
 741                 pmc = static_call(kvm_x86_pmu_pmc_idx_to_pmc)(pmu, i);
 742
 743                 if (!pmc || !pmc_event_is_allowed(pmc))
 744                         continue;
 745
 746                 /* Ignore checks for edge detect, pin control, invert and CMASK bits */
 747                 if (eventsel_match_perf_hw_id(pmc, perf_hw_id) && cpl_is_matched(pmc))
 748                         kvm_pmu_incr_counter(pmc);
 749         }
 750 }
 751 EXPORT_SYMBOL_GPL(kvm_pmu_trigger_event);
 752
 753 static bool is_masked_filter_valid(const struct kvm_x86_pmu_event_filter *filter)
 754 {
 755         u64 mask = kvm_pmu_ops.EVENTSEL_EVENT |
 756                    KVM_PMU_MASKED_ENTRY_UMASK_MASK |
 757                    KVM_PMU_MASKED_ENTRY_UMASK_MATCH |
 758                    KVM_PMU_MASKED_ENTRY_EXCLUDE;
 759         int i;
 760
 761         for (i = 0; i < filter->nevents; i++) {
 762                 if (filter->events[i] & ~mask)
 763                         return false;
 764         }
 765
 766         return true;
 767 }
 768
 769 static void convert_to_masked_filter(struct kvm_x86_pmu_event_filter *filter)
 770 {
 771         int i, j;
 772
 773         for (i = 0, j = 0; i < filter->nevents; i++) {
 774                 /*
 775                  * Skip events that are impossible to match against a guest
 776                  * event.  When filtering, only the event select + unit mask
 777                  * of the guest event is used.  To maintain backwards
 778                  * compatibility, impossible filters can't be rejected :-(
 779                  */
 780                 if (filter->events[i] & ~(kvm_pmu_ops.EVENTSEL_EVENT |
 781                                           ARCH_PERFMON_EVENTSEL_UMASK))
 782                         continue;
 783                 /*
 784                  * Convert userspace events to a common in-kernel event so
 785                  * only one code path is needed to support both events.  For
 786                  * the in-kernel events use masked events because they are
 787                  * flexible enough to handle both cases.  To convert to masked
 788                  * events all that's needed is to add an "all ones" umask_mask,
 789                  * (unmasked filter events don't support EXCLUDE).
 790                  */
 791                 filter->events[j++] = filter->events[i] |
 792                                       (0xFFULL << KVM_PMU_MASKED_ENTRY_UMASK_MASK_SHIFT);
 793         }
 794
 795         filter->nevents = j;
 796 }
 797
 798 static int prepare_filter_lists(struct kvm_x86_pmu_event_filter *filter)
 799 {
 800         int i;
 801
 802         if (!(filter->flags & KVM_PMU_EVENT_FLAG_MASKED_EVENTS))
 803                 convert_to_masked_filter(filter);
 804         else if (!is_masked_filter_valid(filter))
 805                 return -EINVAL;
 806
 807         /*
 808          * Sort entries by event select and includes vs. excludes so that all
 809          * entries for a given event select can be processed efficiently during
 810          * filtering.  The EXCLUDE flag uses a more significant bit than the
 811          * event select, and so the sorted list is also effectively split into
 812          * includes and excludes sub-lists.
 813          */
 814         sort(&filter->events, filter->nevents, sizeof(filter->events[0]),
 815              filter_sort_cmp, NULL);
 816
 817         i = filter->nevents;
 818         /* Find the first EXCLUDE event (only supported for masked events). */
 819         if (filter->flags & KVM_PMU_EVENT_FLAG_MASKED_EVENTS) {
 820                 for (i = 0; i < filter->nevents; i++) {
 821                         if (filter->events[i] & KVM_PMU_MASKED_ENTRY_EXCLUDE)
 822                                 break;
 823                 }
 824         }
 825
 826         filter->nr_includes = i;
 827         filter->nr_excludes = filter->nevents - filter->nr_includes;
 828         filter->includes = filter->events;
 829         filter->excludes = filter->events + filter->nr_includes;
 830
 831         return 0;
 832 }
 833
 834 int kvm_vm_ioctl_set_pmu_event_filter(struct kvm *kvm, void __user *argp)
 835 {
 836         struct kvm_pmu_event_filter __user *user_filter = argp;
 837         struct kvm_x86_pmu_event_filter *filter;
 838         struct kvm_pmu_event_filter tmp;
 839         struct kvm_vcpu *vcpu;
 840         unsigned long i;
 841         size_t size;
 842         int r;
 843
 844         if (copy_from_user(&tmp, user_filter, sizeof(tmp)))
 845                 return -EFAULT;
 846
 847         if (tmp.action != KVM_PMU_EVENT_ALLOW &&
 848             tmp.action != KVM_PMU_EVENT_DENY)
 849                 return -EINVAL;
 850
 851         if (tmp.flags & ~KVM_PMU_EVENT_FLAGS_VALID_MASK)
 852                 return -EINVAL;
 853
 854         if (tmp.nevents > KVM_PMU_EVENT_FILTER_MAX_EVENTS)
 855                 return -E2BIG;
 856
 857         size = struct_size(filter, events, tmp.nevents);
 858         filter = kzalloc(size, GFP_KERNEL_ACCOUNT);
 859         if (!filter)
 860                 return -ENOMEM;
 861
 862         filter->action = tmp.action;
 863         filter->nevents = tmp.nevents;
 864         filter->fixed_counter_bitmap = tmp.fixed_counter_bitmap;
 865         filter->flags = tmp.flags;
 866
 867         r = -EFAULT;
 868         if (copy_from_user(filter->events, user_filter->events,
 869                            sizeof(filter->events[0]) * filter->nevents))
 870                 goto cleanup;
 871
 872         r = prepare_filter_lists(filter);
 873         if (r)
 874                 goto cleanup;
 875
 876         mutex_lock(&kvm->lock);
 877         filter = rcu_replace_pointer(kvm->arch.pmu_event_filter, filter,
 878                                      mutex_is_locked(&kvm->lock));
 879         mutex_unlock(&kvm->lock);
 880         synchronize_srcu_expedited(&kvm->srcu);
 881
 882         BUILD_BUG_ON(sizeof(((struct kvm_pmu *)0)->reprogram_pmi) >
 883                      sizeof(((struct kvm_pmu *)0)->__reprogram_pmi));
 884
 885         kvm_for_each_vcpu(i, vcpu, kvm)
 886                 atomic64_set(&vcpu_to_pmu(vcpu)->__reprogram_pmi, -1ull);
 887
 888         kvm_make_all_cpus_request(kvm, KVM_REQ_PMU);
 889
 890         r = 0;
 891 cleanup:
 892         kfree(filter);
 893         return r;
 894 }