2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
22 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
23 * so the code in this file is compiled twice, once per pte size.
27 #define pt_element_t u64
28 #define guest_walker guest_walker64
29 #define FNAME(name) paging##64_##name
30 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
31 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
32 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
33 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
34 #define PT_LEVEL_BITS PT64_LEVEL_BITS
36 #define PT_MAX_FULL_LEVELS 4
37 #define CMPXCHG cmpxchg
39 #define CMPXCHG cmpxchg64
40 #define PT_MAX_FULL_LEVELS 2
43 #define pt_element_t u32
44 #define guest_walker guest_walker32
45 #define FNAME(name) paging##32_##name
46 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
47 #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
48 #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
49 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
50 #define PT_LEVEL_BITS PT32_LEVEL_BITS
51 #define PT_MAX_FULL_LEVELS 2
52 #define CMPXCHG cmpxchg
54 #error Invalid PTTYPE value
57 #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
58 #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
61 * The guest_walker structure emulates the behavior of the hardware page
67 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
68 pt_element_t ptes[PT_MAX_FULL_LEVELS];
69 pt_element_t prefetch_ptes[PTE_PREFETCH_NUM];
70 gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
71 pt_element_t __user *ptep_user[PT_MAX_FULL_LEVELS];
75 struct x86_exception fault;
78 static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
80 return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
83 static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
84 pt_element_t __user *ptep_user, unsigned index,
85 pt_element_t orig_pte, pt_element_t new_pte)
92 npages = get_user_pages_fast((unsigned long)ptep_user, 1, 1, &page);
93 /* Check if the user is doing something meaningless. */
94 if (unlikely(npages != 1))
97 table = kmap_atomic(page);
98 ret = CMPXCHG(&table[index], orig_pte, new_pte);
101 kvm_release_page_dirty(page);
103 return (ret != orig_pte);
106 static int FNAME(update_accessed_dirty_bits)(struct kvm_vcpu *vcpu,
108 struct guest_walker *walker,
111 unsigned level, index;
112 pt_element_t pte, orig_pte;
113 pt_element_t __user *ptep_user;
117 for (level = walker->max_level; level >= walker->level; --level) {
118 pte = orig_pte = walker->ptes[level - 1];
119 table_gfn = walker->table_gfn[level - 1];
120 ptep_user = walker->ptep_user[level - 1];
121 index = offset_in_page(ptep_user) / sizeof(pt_element_t);
122 if (!(pte & PT_ACCESSED_MASK)) {
123 trace_kvm_mmu_set_accessed_bit(table_gfn, index, sizeof(pte));
124 pte |= PT_ACCESSED_MASK;
126 if (level == walker->level && write_fault && !is_dirty_gpte(pte)) {
127 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
128 pte |= PT_DIRTY_MASK;
133 ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, orig_pte, pte);
137 mark_page_dirty(vcpu->kvm, table_gfn);
138 walker->ptes[level] = pte;
144 * Fetch a guest pte for a guest virtual address
146 static int FNAME(walk_addr_generic)(struct guest_walker *walker,
147 struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
148 gva_t addr, u32 access)
152 pt_element_t __user *uninitialized_var(ptep_user);
154 unsigned index, pt_access, pte_access, accessed_dirty, shift;
157 const int write_fault = access & PFERR_WRITE_MASK;
158 const int user_fault = access & PFERR_USER_MASK;
159 const int fetch_fault = access & PFERR_FETCH_MASK;
164 trace_kvm_mmu_pagetable_walk(addr, access);
166 walker->level = mmu->root_level;
167 pte = mmu->get_cr3(vcpu);
170 if (walker->level == PT32E_ROOT_LEVEL) {
171 pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3);
172 trace_kvm_mmu_paging_element(pte, walker->level);
173 if (!is_present_gpte(pte))
178 walker->max_level = walker->level;
179 ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
180 (mmu->get_cr3(vcpu) & CR3_NONPAE_RESERVED_BITS) == 0);
182 accessed_dirty = PT_ACCESSED_MASK;
183 pt_access = pte_access = ACC_ALL;
188 unsigned long host_addr;
190 pt_access &= pte_access;
193 index = PT_INDEX(addr, walker->level);
195 table_gfn = gpte_to_gfn(pte);
196 offset = index * sizeof(pt_element_t);
197 pte_gpa = gfn_to_gpa(table_gfn) + offset;
198 walker->table_gfn[walker->level - 1] = table_gfn;
199 walker->pte_gpa[walker->level - 1] = pte_gpa;
201 real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn),
202 PFERR_USER_MASK|PFERR_WRITE_MASK);
203 if (unlikely(real_gfn == UNMAPPED_GVA))
205 real_gfn = gpa_to_gfn(real_gfn);
207 host_addr = gfn_to_hva(vcpu->kvm, real_gfn);
208 if (unlikely(kvm_is_error_hva(host_addr)))
211 ptep_user = (pt_element_t __user *)((void *)host_addr + offset);
212 if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte))))
214 walker->ptep_user[walker->level - 1] = ptep_user;
216 trace_kvm_mmu_paging_element(pte, walker->level);
218 if (unlikely(!is_present_gpte(pte)))
221 if (unlikely(is_rsvd_bits_set(&vcpu->arch.mmu, pte,
223 errcode |= PFERR_RSVD_MASK | PFERR_PRESENT_MASK;
227 accessed_dirty &= pte;
228 pte_access = pt_access & gpte_access(vcpu, pte);
230 walker->ptes[walker->level - 1] = pte;
231 } while (!is_last_gpte(mmu, walker->level, pte));
233 if (unlikely(permission_fault(mmu, pte_access, access))) {
234 errcode |= PFERR_PRESENT_MASK;
238 gfn = gpte_to_gfn_lvl(pte, walker->level);
239 gfn += (addr & PT_LVL_OFFSET_MASK(walker->level)) >> PAGE_SHIFT;
241 if (PTTYPE == 32 && walker->level == PT_DIRECTORY_LEVEL && is_cpuid_PSE36())
242 gfn += pse36_gfn_delta(pte);
244 real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), access);
245 if (real_gpa == UNMAPPED_GVA)
248 walker->gfn = real_gpa >> PAGE_SHIFT;
251 protect_clean_gpte(&pte_access, pte);
254 * On a write fault, fold the dirty bit into accessed_dirty by shifting it one
257 * On a read fault, do nothing.
259 shift = write_fault >> ilog2(PFERR_WRITE_MASK);
260 shift *= PT_DIRTY_SHIFT - PT_ACCESSED_SHIFT;
261 accessed_dirty &= pte >> shift;
263 if (unlikely(!accessed_dirty)) {
264 ret = FNAME(update_accessed_dirty_bits)(vcpu, mmu, walker, write_fault);
265 if (unlikely(ret < 0))
271 walker->pt_access = pt_access;
272 walker->pte_access = pte_access;
273 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
274 __func__, (u64)pte, pte_access, pt_access);
278 errcode |= write_fault | user_fault;
279 if (fetch_fault && (mmu->nx ||
280 kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)))
281 errcode |= PFERR_FETCH_MASK;
283 walker->fault.vector = PF_VECTOR;
284 walker->fault.error_code_valid = true;
285 walker->fault.error_code = errcode;
286 walker->fault.address = addr;
287 walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu;
289 trace_kvm_mmu_walker_error(walker->fault.error_code);
293 static int FNAME(walk_addr)(struct guest_walker *walker,
294 struct kvm_vcpu *vcpu, gva_t addr, u32 access)
296 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr,
300 static int FNAME(walk_addr_nested)(struct guest_walker *walker,
301 struct kvm_vcpu *vcpu, gva_t addr,
304 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu,
309 FNAME(prefetch_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
310 u64 *spte, pt_element_t gpte, bool no_dirty_log)
316 if (prefetch_invalid_gpte(vcpu, sp, spte, gpte))
319 pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
321 gfn = gpte_to_gfn(gpte);
322 pte_access = sp->role.access & gpte_access(vcpu, gpte);
323 protect_clean_gpte(&pte_access, gpte);
324 pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn,
325 no_dirty_log && (pte_access & ACC_WRITE_MASK));
326 if (is_error_pfn(pfn))
330 * we call mmu_set_spte() with host_writable = true because
331 * pte_prefetch_gfn_to_pfn always gets a writable pfn.
333 mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0,
334 NULL, PT_PAGE_TABLE_LEVEL, gfn, pfn, true, true);
339 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
340 u64 *spte, const void *pte)
342 pt_element_t gpte = *(const pt_element_t *)pte;
344 FNAME(prefetch_gpte)(vcpu, sp, spte, gpte, false);
347 static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu,
348 struct guest_walker *gw, int level)
350 pt_element_t curr_pte;
351 gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1];
355 if (level == PT_PAGE_TABLE_LEVEL) {
356 mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1;
357 base_gpa = pte_gpa & ~mask;
358 index = (pte_gpa - base_gpa) / sizeof(pt_element_t);
360 r = kvm_read_guest_atomic(vcpu->kvm, base_gpa,
361 gw->prefetch_ptes, sizeof(gw->prefetch_ptes));
362 curr_pte = gw->prefetch_ptes[index];
364 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa,
365 &curr_pte, sizeof(curr_pte));
367 return r || curr_pte != gw->ptes[level - 1];
370 static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw,
373 struct kvm_mmu_page *sp;
374 pt_element_t *gptep = gw->prefetch_ptes;
378 sp = page_header(__pa(sptep));
380 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
384 return __direct_pte_prefetch(vcpu, sp, sptep);
386 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
389 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
393 if (is_shadow_present_pte(*spte))
396 if (!FNAME(prefetch_gpte)(vcpu, sp, spte, gptep[i], true))
402 * Fetch a shadow pte for a specific level in the paging hierarchy.
403 * If the guest tries to write a write-protected page, we need to
404 * emulate this operation, return 1 to indicate this case.
406 static int FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
407 struct guest_walker *gw,
408 int user_fault, int write_fault, int hlevel,
409 pfn_t pfn, bool map_writable, bool prefault)
411 struct kvm_mmu_page *sp = NULL;
412 struct kvm_shadow_walk_iterator it;
413 unsigned direct_access, access = gw->pt_access;
414 int top_level, emulate = 0;
416 if (!is_present_gpte(gw->ptes[gw->level - 1]))
419 direct_access = gw->pte_access;
421 top_level = vcpu->arch.mmu.root_level;
422 if (top_level == PT32E_ROOT_LEVEL)
423 top_level = PT32_ROOT_LEVEL;
425 * Verify that the top-level gpte is still there. Since the page
426 * is a root page, it is either write protected (and cannot be
427 * changed from now on) or it is invalid (in which case, we don't
428 * really care if it changes underneath us after this point).
430 if (FNAME(gpte_changed)(vcpu, gw, top_level))
431 goto out_gpte_changed;
433 for (shadow_walk_init(&it, vcpu, addr);
434 shadow_walk_okay(&it) && it.level > gw->level;
435 shadow_walk_next(&it)) {
438 clear_sp_write_flooding_count(it.sptep);
439 drop_large_spte(vcpu, it.sptep);
442 if (!is_shadow_present_pte(*it.sptep)) {
443 table_gfn = gw->table_gfn[it.level - 2];
444 sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1,
445 false, access, it.sptep);
449 * Verify that the gpte in the page we've just write
450 * protected is still there.
452 if (FNAME(gpte_changed)(vcpu, gw, it.level - 1))
453 goto out_gpte_changed;
456 link_shadow_page(it.sptep, sp);
460 shadow_walk_okay(&it) && it.level > hlevel;
461 shadow_walk_next(&it)) {
464 clear_sp_write_flooding_count(it.sptep);
465 validate_direct_spte(vcpu, it.sptep, direct_access);
467 drop_large_spte(vcpu, it.sptep);
469 if (is_shadow_present_pte(*it.sptep))
472 direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
474 sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1,
475 true, direct_access, it.sptep);
476 link_shadow_page(it.sptep, sp);
479 clear_sp_write_flooding_count(it.sptep);
480 mmu_set_spte(vcpu, it.sptep, access, gw->pte_access,
481 user_fault, write_fault, &emulate, it.level,
482 gw->gfn, pfn, prefault, map_writable);
483 FNAME(pte_prefetch)(vcpu, gw, it.sptep);
489 kvm_mmu_put_page(sp, it.sptep);
490 kvm_release_pfn_clean(pfn);
495 * Page fault handler. There are several causes for a page fault:
496 * - there is no shadow pte for the guest pte
497 * - write access through a shadow pte marked read only so that we can set
499 * - write access to a shadow pte marked read only so we can update the page
500 * dirty bitmap, when userspace requests it
501 * - mmio access; in this case we will never install a present shadow pte
502 * - normal guest page fault due to the guest pte marked not present, not
503 * writable, or not executable
505 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
506 * a negative value on error.
508 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code,
511 int write_fault = error_code & PFERR_WRITE_MASK;
512 int user_fault = error_code & PFERR_USER_MASK;
513 struct guest_walker walker;
516 int level = PT_PAGE_TABLE_LEVEL;
518 unsigned long mmu_seq;
521 pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
523 if (unlikely(error_code & PFERR_RSVD_MASK))
524 return handle_mmio_page_fault(vcpu, addr, error_code,
525 mmu_is_nested(vcpu));
527 r = mmu_topup_memory_caches(vcpu);
532 * Look up the guest pte for the faulting address.
534 r = FNAME(walk_addr)(&walker, vcpu, addr, error_code);
537 * The page is not mapped by the guest. Let the guest handle it.
540 pgprintk("%s: guest page fault\n", __func__);
542 inject_page_fault(vcpu, &walker.fault);
547 if (walker.level >= PT_DIRECTORY_LEVEL)
548 force_pt_level = mapping_level_dirty_bitmap(vcpu, walker.gfn);
551 if (!force_pt_level) {
552 level = min(walker.level, mapping_level(vcpu, walker.gfn));
553 walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
556 mmu_seq = vcpu->kvm->mmu_notifier_seq;
559 if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault,
563 if (handle_abnormal_pfn(vcpu, mmu_is_nested(vcpu) ? 0 : addr,
564 walker.gfn, pfn, walker.pte_access, &r))
567 spin_lock(&vcpu->kvm->mmu_lock);
568 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
571 kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT);
572 kvm_mmu_free_some_pages(vcpu);
574 transparent_hugepage_adjust(vcpu, &walker.gfn, &pfn, &level);
575 r = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
576 level, pfn, map_writable, prefault);
577 ++vcpu->stat.pf_fixed;
578 kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT);
579 spin_unlock(&vcpu->kvm->mmu_lock);
584 spin_unlock(&vcpu->kvm->mmu_lock);
585 kvm_release_pfn_clean(pfn);
589 static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp)
593 WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL);
596 offset = sp->role.quadrant << PT64_LEVEL_BITS;
598 return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
601 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
603 struct kvm_shadow_walk_iterator iterator;
604 struct kvm_mmu_page *sp;
608 vcpu_clear_mmio_info(vcpu, gva);
611 * No need to check return value here, rmap_can_add() can
612 * help us to skip pte prefetch later.
614 mmu_topup_memory_caches(vcpu);
616 spin_lock(&vcpu->kvm->mmu_lock);
617 for_each_shadow_entry(vcpu, gva, iterator) {
618 level = iterator.level;
619 sptep = iterator.sptep;
621 sp = page_header(__pa(sptep));
622 if (is_last_spte(*sptep, level)) {
629 pte_gpa = FNAME(get_level1_sp_gpa)(sp);
630 pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
632 if (mmu_page_zap_pte(vcpu->kvm, sp, sptep))
633 kvm_flush_remote_tlbs(vcpu->kvm);
635 if (!rmap_can_add(vcpu))
638 if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
639 sizeof(pt_element_t)))
642 FNAME(update_pte)(vcpu, sp, sptep, &gpte);
645 if (!is_shadow_present_pte(*sptep) || !sp->unsync_children)
648 spin_unlock(&vcpu->kvm->mmu_lock);
651 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access,
652 struct x86_exception *exception)
654 struct guest_walker walker;
655 gpa_t gpa = UNMAPPED_GVA;
658 r = FNAME(walk_addr)(&walker, vcpu, vaddr, access);
661 gpa = gfn_to_gpa(walker.gfn);
662 gpa |= vaddr & ~PAGE_MASK;
663 } else if (exception)
664 *exception = walker.fault;
669 static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr,
671 struct x86_exception *exception)
673 struct guest_walker walker;
674 gpa_t gpa = UNMAPPED_GVA;
677 r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access);
680 gpa = gfn_to_gpa(walker.gfn);
681 gpa |= vaddr & ~PAGE_MASK;
682 } else if (exception)
683 *exception = walker.fault;
689 * Using the cached information from sp->gfns is safe because:
690 * - The spte has a reference to the struct page, so the pfn for a given gfn
691 * can't change unless all sptes pointing to it are nuked first.
694 * We should flush all tlbs if spte is dropped even though guest is
695 * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page
696 * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't
697 * used by guest then tlbs are not flushed, so guest is allowed to access the
699 * And we increase kvm->tlbs_dirty to delay tlbs flush in this case.
701 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
703 int i, nr_present = 0;
707 /* direct kvm_mmu_page can not be unsync. */
708 BUG_ON(sp->role.direct);
710 first_pte_gpa = FNAME(get_level1_sp_gpa)(sp);
712 for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
721 pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
723 if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
724 sizeof(pt_element_t)))
727 if (prefetch_invalid_gpte(vcpu, sp, &sp->spt[i], gpte)) {
728 vcpu->kvm->tlbs_dirty++;
732 gfn = gpte_to_gfn(gpte);
733 pte_access = sp->role.access;
734 pte_access &= gpte_access(vcpu, gpte);
735 protect_clean_gpte(&pte_access, gpte);
737 if (sync_mmio_spte(&sp->spt[i], gfn, pte_access, &nr_present))
740 if (gfn != sp->gfns[i]) {
741 drop_spte(vcpu->kvm, &sp->spt[i]);
742 vcpu->kvm->tlbs_dirty++;
748 host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE;
750 set_spte(vcpu, &sp->spt[i], pte_access, 0, 0,
751 PT_PAGE_TABLE_LEVEL, gfn,
752 spte_to_pfn(sp->spt[i]), true, false,
762 #undef PT_BASE_ADDR_MASK
764 #undef PT_LVL_ADDR_MASK
765 #undef PT_LVL_OFFSET_MASK
767 #undef PT_MAX_FULL_LEVELS
769 #undef gpte_to_gfn_lvl