2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
22 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
23 * so the code in this file is compiled twice, once per pte size.
27 * This is used to catch non optimized PT_GUEST_(DIRTY|ACCESS)_SHIFT macro
28 * uses for EPT without A/D paging type.
30 extern u64 __pure __using_nonexistent_pte_bit(void)
31 __compiletime_error("wrong use of PT_GUEST_(DIRTY|ACCESS)_SHIFT");
34 #define pt_element_t u64
35 #define guest_walker guest_walker64
36 #define FNAME(name) paging##64_##name
37 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
38 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
39 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
40 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
41 #define PT_LEVEL_BITS PT64_LEVEL_BITS
42 #define PT_GUEST_ACCESSED_MASK PT_ACCESSED_MASK
43 #define PT_GUEST_DIRTY_MASK PT_DIRTY_MASK
44 #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
45 #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
47 #define PT_MAX_FULL_LEVELS 4
48 #define CMPXCHG cmpxchg
50 #define CMPXCHG cmpxchg64
51 #define PT_MAX_FULL_LEVELS 2
54 #define pt_element_t u32
55 #define guest_walker guest_walker32
56 #define FNAME(name) paging##32_##name
57 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
58 #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
59 #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
60 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
61 #define PT_LEVEL_BITS PT32_LEVEL_BITS
62 #define PT_MAX_FULL_LEVELS 2
63 #define PT_GUEST_ACCESSED_MASK PT_ACCESSED_MASK
64 #define PT_GUEST_DIRTY_MASK PT_DIRTY_MASK
65 #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
66 #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
67 #define CMPXCHG cmpxchg
68 #elif PTTYPE == PTTYPE_EPT
69 #define pt_element_t u64
70 #define guest_walker guest_walkerEPT
71 #define FNAME(name) ept_##name
72 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
73 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
74 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
75 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
76 #define PT_LEVEL_BITS PT64_LEVEL_BITS
77 #define PT_GUEST_ACCESSED_MASK 0
78 #define PT_GUEST_DIRTY_MASK 0
79 #define PT_GUEST_DIRTY_SHIFT __using_nonexistent_pte_bit()
80 #define PT_GUEST_ACCESSED_SHIFT __using_nonexistent_pte_bit()
81 #define CMPXCHG cmpxchg64
82 #define PT_MAX_FULL_LEVELS 4
84 #error Invalid PTTYPE value
87 #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
88 #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
91 * The guest_walker structure emulates the behavior of the hardware page
97 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
98 pt_element_t ptes[PT_MAX_FULL_LEVELS];
99 pt_element_t prefetch_ptes[PTE_PREFETCH_NUM];
100 gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
101 pt_element_t __user *ptep_user[PT_MAX_FULL_LEVELS];
102 bool pte_writable[PT_MAX_FULL_LEVELS];
106 struct x86_exception fault;
109 static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
111 return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
114 static inline void FNAME(protect_clean_gpte)(unsigned *access, unsigned gpte)
118 /* dirty bit is not supported, so no need to track it */
119 if (!PT_GUEST_DIRTY_MASK)
122 BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK);
124 mask = (unsigned)~ACC_WRITE_MASK;
125 /* Allow write access to dirty gptes */
126 mask |= (gpte >> (PT_GUEST_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) &
131 static inline int FNAME(is_present_gpte)(unsigned long pte)
133 #if PTTYPE != PTTYPE_EPT
134 return is_present_gpte(pte);
140 static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
141 pt_element_t __user *ptep_user, unsigned index,
142 pt_element_t orig_pte, pt_element_t new_pte)
149 npages = get_user_pages_fast((unsigned long)ptep_user, 1, 1, &page);
150 /* Check if the user is doing something meaningless. */
151 if (unlikely(npages != 1))
154 table = kmap_atomic(page);
155 ret = CMPXCHG(&table[index], orig_pte, new_pte);
156 kunmap_atomic(table);
158 kvm_release_page_dirty(page);
160 return (ret != orig_pte);
163 static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu,
164 struct kvm_mmu_page *sp, u64 *spte,
167 if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL))
170 if (!FNAME(is_present_gpte)(gpte))
173 /* if accessed bit is not supported prefetch non accessed gpte */
174 if (PT_GUEST_ACCESSED_MASK && !(gpte & PT_GUEST_ACCESSED_MASK))
180 drop_spte(vcpu->kvm, spte);
184 static inline unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, u64 gpte)
187 #if PTTYPE == PTTYPE_EPT
188 access = ((gpte & VMX_EPT_WRITABLE_MASK) ? ACC_WRITE_MASK : 0) |
189 ((gpte & VMX_EPT_EXECUTABLE_MASK) ? ACC_EXEC_MASK : 0) |
192 BUILD_BUG_ON(ACC_EXEC_MASK != PT_PRESENT_MASK);
193 BUILD_BUG_ON(ACC_EXEC_MASK != 1);
194 access = gpte & (PT_WRITABLE_MASK | PT_USER_MASK | PT_PRESENT_MASK);
195 /* Combine NX with P (which is set here) to get ACC_EXEC_MASK. */
196 access ^= (gpte >> PT64_NX_SHIFT);
202 static int FNAME(update_accessed_dirty_bits)(struct kvm_vcpu *vcpu,
204 struct guest_walker *walker,
207 unsigned level, index;
208 pt_element_t pte, orig_pte;
209 pt_element_t __user *ptep_user;
213 /* dirty/accessed bits are not supported, so no need to update them */
214 if (!PT_GUEST_DIRTY_MASK)
217 for (level = walker->max_level; level >= walker->level; --level) {
218 pte = orig_pte = walker->ptes[level - 1];
219 table_gfn = walker->table_gfn[level - 1];
220 ptep_user = walker->ptep_user[level - 1];
221 index = offset_in_page(ptep_user) / sizeof(pt_element_t);
222 if (!(pte & PT_GUEST_ACCESSED_MASK)) {
223 trace_kvm_mmu_set_accessed_bit(table_gfn, index, sizeof(pte));
224 pte |= PT_GUEST_ACCESSED_MASK;
226 if (level == walker->level && write_fault &&
227 !(pte & PT_GUEST_DIRTY_MASK)) {
228 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
229 pte |= PT_GUEST_DIRTY_MASK;
235 * If the slot is read-only, simply do not process the accessed
236 * and dirty bits. This is the correct thing to do if the slot
237 * is ROM, and page tables in read-as-ROM/write-as-MMIO slots
238 * are only supported if the accessed and dirty bits are already
239 * set in the ROM (so that MMIO writes are never needed).
241 * Note that NPT does not allow this at all and faults, since
242 * it always wants nested page table entries for the guest
243 * page tables to be writable. And EPT works but will simply
244 * overwrite the read-only memory to set the accessed and dirty
247 if (unlikely(!walker->pte_writable[level - 1]))
250 ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, orig_pte, pte);
254 kvm_vcpu_mark_page_dirty(vcpu, table_gfn);
255 walker->ptes[level - 1] = pte;
260 static inline unsigned FNAME(gpte_pkeys)(struct kvm_vcpu *vcpu, u64 gpte)
264 pte_t pte = {.pte = gpte};
266 pkeys = pte_flags_pkey(pte_flags(pte));
272 * Fetch a guest pte for a guest virtual address
274 static int FNAME(walk_addr_generic)(struct guest_walker *walker,
275 struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
276 gva_t addr, u32 access)
280 pt_element_t __user *uninitialized_var(ptep_user);
282 unsigned index, pt_access, pte_access, accessed_dirty, pte_pkey;
285 const int write_fault = access & PFERR_WRITE_MASK;
286 const int user_fault = access & PFERR_USER_MASK;
287 const int fetch_fault = access & PFERR_FETCH_MASK;
292 trace_kvm_mmu_pagetable_walk(addr, access);
294 walker->level = mmu->root_level;
295 pte = mmu->get_cr3(vcpu);
298 if (walker->level == PT32E_ROOT_LEVEL) {
299 pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3);
300 trace_kvm_mmu_paging_element(pte, walker->level);
301 if (!FNAME(is_present_gpte)(pte))
306 walker->max_level = walker->level;
307 ASSERT(!(is_long_mode(vcpu) && !is_pae(vcpu)));
309 accessed_dirty = PT_GUEST_ACCESSED_MASK;
310 pt_access = pte_access = ACC_ALL;
315 unsigned long host_addr;
317 pt_access &= pte_access;
320 index = PT_INDEX(addr, walker->level);
322 table_gfn = gpte_to_gfn(pte);
323 offset = index * sizeof(pt_element_t);
324 pte_gpa = gfn_to_gpa(table_gfn) + offset;
325 walker->table_gfn[walker->level - 1] = table_gfn;
326 walker->pte_gpa[walker->level - 1] = pte_gpa;
328 real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn),
329 PFERR_USER_MASK|PFERR_WRITE_MASK,
333 * FIXME: This can happen if emulation (for of an INS/OUTS
334 * instruction) triggers a nested page fault. The exit
335 * qualification / exit info field will incorrectly have
336 * "guest page access" as the nested page fault's cause,
337 * instead of "guest page structure access". To fix this,
338 * the x86_exception struct should be augmented with enough
339 * information to fix the exit_qualification or exit_info_1
342 if (unlikely(real_gfn == UNMAPPED_GVA))
345 real_gfn = gpa_to_gfn(real_gfn);
347 host_addr = kvm_vcpu_gfn_to_hva_prot(vcpu, real_gfn,
348 &walker->pte_writable[walker->level - 1]);
349 if (unlikely(kvm_is_error_hva(host_addr)))
352 ptep_user = (pt_element_t __user *)((void *)host_addr + offset);
353 if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte))))
355 walker->ptep_user[walker->level - 1] = ptep_user;
357 trace_kvm_mmu_paging_element(pte, walker->level);
359 if (unlikely(!FNAME(is_present_gpte)(pte)))
362 if (unlikely(is_rsvd_bits_set(mmu, pte, walker->level))) {
363 errcode |= PFERR_RSVD_MASK | PFERR_PRESENT_MASK;
367 accessed_dirty &= pte;
368 pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);
370 walker->ptes[walker->level - 1] = pte;
371 } while (!is_last_gpte(mmu, walker->level, pte));
373 pte_pkey = FNAME(gpte_pkeys)(vcpu, pte);
374 errcode = permission_fault(vcpu, mmu, pte_access, pte_pkey, access);
375 if (unlikely(errcode))
378 gfn = gpte_to_gfn_lvl(pte, walker->level);
379 gfn += (addr & PT_LVL_OFFSET_MASK(walker->level)) >> PAGE_SHIFT;
381 if (PTTYPE == 32 && walker->level == PT_DIRECTORY_LEVEL && is_cpuid_PSE36())
382 gfn += pse36_gfn_delta(pte);
384 real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), access, &walker->fault);
385 if (real_gpa == UNMAPPED_GVA)
388 walker->gfn = real_gpa >> PAGE_SHIFT;
391 FNAME(protect_clean_gpte)(&pte_access, pte);
394 * On a write fault, fold the dirty bit into accessed_dirty.
395 * For modes without A/D bits support accessed_dirty will be
398 accessed_dirty &= pte >>
399 (PT_GUEST_DIRTY_SHIFT - PT_GUEST_ACCESSED_SHIFT);
401 if (unlikely(!accessed_dirty)) {
402 ret = FNAME(update_accessed_dirty_bits)(vcpu, mmu, walker, write_fault);
403 if (unlikely(ret < 0))
409 walker->pt_access = pt_access;
410 walker->pte_access = pte_access;
411 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
412 __func__, (u64)pte, pte_access, pt_access);
416 errcode |= write_fault | user_fault;
417 if (fetch_fault && (mmu->nx ||
418 kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)))
419 errcode |= PFERR_FETCH_MASK;
421 walker->fault.vector = PF_VECTOR;
422 walker->fault.error_code_valid = true;
423 walker->fault.error_code = errcode;
425 #if PTTYPE == PTTYPE_EPT
427 * Use PFERR_RSVD_MASK in error_code to to tell if EPT
428 * misconfiguration requires to be injected. The detection is
429 * done by is_rsvd_bits_set() above.
431 * We set up the value of exit_qualification to inject:
432 * [2:0] - Derive from [2:0] of real exit_qualification at EPT violation
433 * [5:3] - Calculated by the page walk of the guest EPT page tables
434 * [7:8] - Derived from [7:8] of real exit_qualification
436 * The other bits are set to 0.
438 if (!(errcode & PFERR_RSVD_MASK)) {
439 vcpu->arch.exit_qualification &= 0x187;
440 vcpu->arch.exit_qualification |= ((pt_access & pte) & 0x7) << 3;
443 walker->fault.address = addr;
444 walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu;
446 trace_kvm_mmu_walker_error(walker->fault.error_code);
450 static int FNAME(walk_addr)(struct guest_walker *walker,
451 struct kvm_vcpu *vcpu, gva_t addr, u32 access)
453 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr,
457 #if PTTYPE != PTTYPE_EPT
458 static int FNAME(walk_addr_nested)(struct guest_walker *walker,
459 struct kvm_vcpu *vcpu, gva_t addr,
462 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu,
468 FNAME(prefetch_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
469 u64 *spte, pt_element_t gpte, bool no_dirty_log)
475 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte))
478 pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
480 gfn = gpte_to_gfn(gpte);
481 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
482 FNAME(protect_clean_gpte)(&pte_access, gpte);
483 pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn,
484 no_dirty_log && (pte_access & ACC_WRITE_MASK));
485 if (is_error_pfn(pfn))
489 * we call mmu_set_spte() with host_writable = true because
490 * pte_prefetch_gfn_to_pfn always gets a writable pfn.
492 mmu_set_spte(vcpu, spte, pte_access, 0, PT_PAGE_TABLE_LEVEL, gfn, pfn,
498 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
499 u64 *spte, const void *pte)
501 pt_element_t gpte = *(const pt_element_t *)pte;
503 FNAME(prefetch_gpte)(vcpu, sp, spte, gpte, false);
506 static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu,
507 struct guest_walker *gw, int level)
509 pt_element_t curr_pte;
510 gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1];
514 if (level == PT_PAGE_TABLE_LEVEL) {
515 mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1;
516 base_gpa = pte_gpa & ~mask;
517 index = (pte_gpa - base_gpa) / sizeof(pt_element_t);
519 r = kvm_vcpu_read_guest_atomic(vcpu, base_gpa,
520 gw->prefetch_ptes, sizeof(gw->prefetch_ptes));
521 curr_pte = gw->prefetch_ptes[index];
523 r = kvm_vcpu_read_guest_atomic(vcpu, pte_gpa,
524 &curr_pte, sizeof(curr_pte));
526 return r || curr_pte != gw->ptes[level - 1];
529 static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw,
532 struct kvm_mmu_page *sp;
533 pt_element_t *gptep = gw->prefetch_ptes;
537 sp = page_header(__pa(sptep));
539 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
543 return __direct_pte_prefetch(vcpu, sp, sptep);
545 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
548 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
552 if (is_shadow_present_pte(*spte))
555 if (!FNAME(prefetch_gpte)(vcpu, sp, spte, gptep[i], true))
561 * Fetch a shadow pte for a specific level in the paging hierarchy.
562 * If the guest tries to write a write-protected page, we need to
563 * emulate this operation, return 1 to indicate this case.
565 static int FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
566 struct guest_walker *gw,
567 int write_fault, int hlevel,
568 kvm_pfn_t pfn, bool map_writable, bool prefault)
570 struct kvm_mmu_page *sp = NULL;
571 struct kvm_shadow_walk_iterator it;
572 unsigned direct_access, access = gw->pt_access;
573 int top_level, emulate;
575 direct_access = gw->pte_access;
577 top_level = vcpu->arch.mmu.root_level;
578 if (top_level == PT32E_ROOT_LEVEL)
579 top_level = PT32_ROOT_LEVEL;
581 * Verify that the top-level gpte is still there. Since the page
582 * is a root page, it is either write protected (and cannot be
583 * changed from now on) or it is invalid (in which case, we don't
584 * really care if it changes underneath us after this point).
586 if (FNAME(gpte_changed)(vcpu, gw, top_level))
587 goto out_gpte_changed;
589 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
590 goto out_gpte_changed;
592 for (shadow_walk_init(&it, vcpu, addr);
593 shadow_walk_okay(&it) && it.level > gw->level;
594 shadow_walk_next(&it)) {
597 clear_sp_write_flooding_count(it.sptep);
598 drop_large_spte(vcpu, it.sptep);
601 if (!is_shadow_present_pte(*it.sptep)) {
602 table_gfn = gw->table_gfn[it.level - 2];
603 sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1,
608 * Verify that the gpte in the page we've just write
609 * protected is still there.
611 if (FNAME(gpte_changed)(vcpu, gw, it.level - 1))
612 goto out_gpte_changed;
615 link_shadow_page(vcpu, it.sptep, sp);
619 shadow_walk_okay(&it) && it.level > hlevel;
620 shadow_walk_next(&it)) {
623 clear_sp_write_flooding_count(it.sptep);
624 validate_direct_spte(vcpu, it.sptep, direct_access);
626 drop_large_spte(vcpu, it.sptep);
628 if (is_shadow_present_pte(*it.sptep))
631 direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
633 sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1,
634 true, direct_access);
635 link_shadow_page(vcpu, it.sptep, sp);
638 clear_sp_write_flooding_count(it.sptep);
639 emulate = mmu_set_spte(vcpu, it.sptep, gw->pte_access, write_fault,
640 it.level, gw->gfn, pfn, prefault, map_writable);
641 FNAME(pte_prefetch)(vcpu, gw, it.sptep);
646 kvm_release_pfn_clean(pfn);
651 * To see whether the mapped gfn can write its page table in the current
654 * It is the helper function of FNAME(page_fault). When guest uses large page
655 * size to map the writable gfn which is used as current page table, we should
656 * force kvm to use small page size to map it because new shadow page will be
657 * created when kvm establishes shadow page table that stop kvm using large
658 * page size. Do it early can avoid unnecessary #PF and emulation.
660 * @write_fault_to_shadow_pgtable will return true if the fault gfn is
661 * currently used as its page table.
663 * Note: the PDPT page table is not checked for PAE-32 bit guest. It is ok
664 * since the PDPT is always shadowed, that means, we can not use large page
665 * size to map the gfn which is used as PDPT.
668 FNAME(is_self_change_mapping)(struct kvm_vcpu *vcpu,
669 struct guest_walker *walker, int user_fault,
670 bool *write_fault_to_shadow_pgtable)
673 gfn_t mask = ~(KVM_PAGES_PER_HPAGE(walker->level) - 1);
674 bool self_changed = false;
676 if (!(walker->pte_access & ACC_WRITE_MASK ||
677 (!is_write_protection(vcpu) && !user_fault)))
680 for (level = walker->level; level <= walker->max_level; level++) {
681 gfn_t gfn = walker->gfn ^ walker->table_gfn[level - 1];
683 self_changed |= !(gfn & mask);
684 *write_fault_to_shadow_pgtable |= !gfn;
691 * Page fault handler. There are several causes for a page fault:
692 * - there is no shadow pte for the guest pte
693 * - write access through a shadow pte marked read only so that we can set
695 * - write access to a shadow pte marked read only so we can update the page
696 * dirty bitmap, when userspace requests it
697 * - mmio access; in this case we will never install a present shadow pte
698 * - normal guest page fault due to the guest pte marked not present, not
699 * writable, or not executable
701 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
702 * a negative value on error.
704 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code,
707 int write_fault = error_code & PFERR_WRITE_MASK;
708 int user_fault = error_code & PFERR_USER_MASK;
709 struct guest_walker walker;
712 int level = PT_PAGE_TABLE_LEVEL;
713 bool force_pt_level = false;
714 unsigned long mmu_seq;
715 bool map_writable, is_self_change_mapping;
717 pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
719 r = mmu_topup_memory_caches(vcpu);
724 * If PFEC.RSVD is set, this is a shadow page fault.
725 * The bit needs to be cleared before walking guest page tables.
727 error_code &= ~PFERR_RSVD_MASK;
730 * Look up the guest pte for the faulting address.
732 r = FNAME(walk_addr)(&walker, vcpu, addr, error_code);
735 * The page is not mapped by the guest. Let the guest handle it.
738 pgprintk("%s: guest page fault\n", __func__);
740 inject_page_fault(vcpu, &walker.fault);
745 if (page_fault_handle_page_track(vcpu, error_code, walker.gfn)) {
746 shadow_page_table_clear_flood(vcpu, addr);
750 vcpu->arch.write_fault_to_shadow_pgtable = false;
752 is_self_change_mapping = FNAME(is_self_change_mapping)(vcpu,
753 &walker, user_fault, &vcpu->arch.write_fault_to_shadow_pgtable);
755 if (walker.level >= PT_DIRECTORY_LEVEL && !is_self_change_mapping) {
756 level = mapping_level(vcpu, walker.gfn, &force_pt_level);
757 if (likely(!force_pt_level)) {
758 level = min(walker.level, level);
759 walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
762 force_pt_level = true;
764 mmu_seq = vcpu->kvm->mmu_notifier_seq;
767 if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault,
771 if (handle_abnormal_pfn(vcpu, mmu_is_nested(vcpu) ? 0 : addr,
772 walker.gfn, pfn, walker.pte_access, &r))
776 * Do not change pte_access if the pfn is a mmio page, otherwise
777 * we will cache the incorrect access into mmio spte.
779 if (write_fault && !(walker.pte_access & ACC_WRITE_MASK) &&
780 !is_write_protection(vcpu) && !user_fault &&
781 !is_noslot_pfn(pfn)) {
782 walker.pte_access |= ACC_WRITE_MASK;
783 walker.pte_access &= ~ACC_USER_MASK;
786 * If we converted a user page to a kernel page,
787 * so that the kernel can write to it when cr0.wp=0,
788 * then we should prevent the kernel from executing it
789 * if SMEP is enabled.
791 if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))
792 walker.pte_access &= ~ACC_EXEC_MASK;
795 spin_lock(&vcpu->kvm->mmu_lock);
796 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
799 kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT);
800 make_mmu_pages_available(vcpu);
802 transparent_hugepage_adjust(vcpu, &walker.gfn, &pfn, &level);
803 r = FNAME(fetch)(vcpu, addr, &walker, write_fault,
804 level, pfn, map_writable, prefault);
805 ++vcpu->stat.pf_fixed;
806 kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT);
807 spin_unlock(&vcpu->kvm->mmu_lock);
812 spin_unlock(&vcpu->kvm->mmu_lock);
813 kvm_release_pfn_clean(pfn);
817 static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp)
821 WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL);
824 offset = sp->role.quadrant << PT64_LEVEL_BITS;
826 return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
829 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
831 struct kvm_shadow_walk_iterator iterator;
832 struct kvm_mmu_page *sp;
836 vcpu_clear_mmio_info(vcpu, gva);
839 * No need to check return value here, rmap_can_add() can
840 * help us to skip pte prefetch later.
842 mmu_topup_memory_caches(vcpu);
844 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) {
849 spin_lock(&vcpu->kvm->mmu_lock);
850 for_each_shadow_entry(vcpu, gva, iterator) {
851 level = iterator.level;
852 sptep = iterator.sptep;
854 sp = page_header(__pa(sptep));
855 if (is_last_spte(*sptep, level)) {
862 pte_gpa = FNAME(get_level1_sp_gpa)(sp);
863 pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
865 if (mmu_page_zap_pte(vcpu->kvm, sp, sptep))
866 kvm_flush_remote_tlbs(vcpu->kvm);
868 if (!rmap_can_add(vcpu))
871 if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte,
872 sizeof(pt_element_t)))
875 FNAME(update_pte)(vcpu, sp, sptep, &gpte);
878 if (!is_shadow_present_pte(*sptep) || !sp->unsync_children)
881 spin_unlock(&vcpu->kvm->mmu_lock);
884 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access,
885 struct x86_exception *exception)
887 struct guest_walker walker;
888 gpa_t gpa = UNMAPPED_GVA;
891 r = FNAME(walk_addr)(&walker, vcpu, vaddr, access);
894 gpa = gfn_to_gpa(walker.gfn);
895 gpa |= vaddr & ~PAGE_MASK;
896 } else if (exception)
897 *exception = walker.fault;
902 #if PTTYPE != PTTYPE_EPT
903 static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr,
905 struct x86_exception *exception)
907 struct guest_walker walker;
908 gpa_t gpa = UNMAPPED_GVA;
911 r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access);
914 gpa = gfn_to_gpa(walker.gfn);
915 gpa |= vaddr & ~PAGE_MASK;
916 } else if (exception)
917 *exception = walker.fault;
924 * Using the cached information from sp->gfns is safe because:
925 * - The spte has a reference to the struct page, so the pfn for a given gfn
926 * can't change unless all sptes pointing to it are nuked first.
929 * We should flush all tlbs if spte is dropped even though guest is
930 * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page
931 * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't
932 * used by guest then tlbs are not flushed, so guest is allowed to access the
934 * And we increase kvm->tlbs_dirty to delay tlbs flush in this case.
936 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
938 int i, nr_present = 0;
942 /* direct kvm_mmu_page can not be unsync. */
943 BUG_ON(sp->role.direct);
945 first_pte_gpa = FNAME(get_level1_sp_gpa)(sp);
947 for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
956 pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
958 if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte,
959 sizeof(pt_element_t)))
962 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) {
963 vcpu->kvm->tlbs_dirty++;
967 gfn = gpte_to_gfn(gpte);
968 pte_access = sp->role.access;
969 pte_access &= FNAME(gpte_access)(vcpu, gpte);
970 FNAME(protect_clean_gpte)(&pte_access, gpte);
972 if (sync_mmio_spte(vcpu, &sp->spt[i], gfn, pte_access,
976 if (gfn != sp->gfns[i]) {
977 drop_spte(vcpu->kvm, &sp->spt[i]);
978 vcpu->kvm->tlbs_dirty++;
984 host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE;
986 set_spte(vcpu, &sp->spt[i], pte_access,
987 PT_PAGE_TABLE_LEVEL, gfn,
988 spte_to_pfn(sp->spt[i]), true, false,
998 #undef PT_BASE_ADDR_MASK
1000 #undef PT_LVL_ADDR_MASK
1001 #undef PT_LVL_OFFSET_MASK
1002 #undef PT_LEVEL_BITS
1003 #undef PT_MAX_FULL_LEVELS
1005 #undef gpte_to_gfn_lvl
1007 #undef PT_GUEST_ACCESSED_MASK
1008 #undef PT_GUEST_DIRTY_MASK
1009 #undef PT_GUEST_DIRTY_SHIFT
1010 #undef PT_GUEST_ACCESSED_SHIFT