2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
26 #include <linux/kvm_host.h>
27 #include <linux/types.h>
28 #include <linux/string.h>
30 #include <linux/highmem.h>
31 #include <linux/module.h>
32 #include <linux/swap.h>
33 #include <linux/hugetlb.h>
34 #include <linux/compiler.h>
35 #include <linux/srcu.h>
36 #include <linux/slab.h>
37 #include <linux/uaccess.h>
40 #include <asm/cmpxchg.h>
45 * When setting this variable to true it enables Two-Dimensional-Paging
46 * where the hardware walks 2 page tables:
47 * 1. the guest-virtual to guest-physical
48 * 2. while doing 1. it walks guest-physical to host-physical
49 * If the hardware supports that we don't need to do shadow paging.
51 bool tdp_enabled = false;
55 AUDIT_POST_PAGE_FAULT,
66 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
67 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
71 #define pgprintk(x...) do { } while (0)
72 #define rmap_printk(x...) do { } while (0)
78 module_param(dbg, bool, 0644);
82 #define ASSERT(x) do { } while (0)
86 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
87 __FILE__, __LINE__, #x); \
91 #define PTE_PREFETCH_NUM 8
93 #define PT_FIRST_AVAIL_BITS_SHIFT 10
94 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
96 #define PT64_LEVEL_BITS 9
98 #define PT64_LEVEL_SHIFT(level) \
99 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
101 #define PT64_INDEX(address, level)\
102 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
105 #define PT32_LEVEL_BITS 10
107 #define PT32_LEVEL_SHIFT(level) \
108 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
110 #define PT32_LVL_OFFSET_MASK(level) \
111 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
112 * PT32_LEVEL_BITS))) - 1))
114 #define PT32_INDEX(address, level)\
115 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
118 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
119 #define PT64_DIR_BASE_ADDR_MASK \
120 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
121 #define PT64_LVL_ADDR_MASK(level) \
122 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
123 * PT64_LEVEL_BITS))) - 1))
124 #define PT64_LVL_OFFSET_MASK(level) \
125 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
126 * PT64_LEVEL_BITS))) - 1))
128 #define PT32_BASE_ADDR_MASK PAGE_MASK
129 #define PT32_DIR_BASE_ADDR_MASK \
130 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
131 #define PT32_LVL_ADDR_MASK(level) \
132 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
133 * PT32_LEVEL_BITS))) - 1))
135 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \
136 | shadow_x_mask | shadow_nx_mask)
138 #define ACC_EXEC_MASK 1
139 #define ACC_WRITE_MASK PT_WRITABLE_MASK
140 #define ACC_USER_MASK PT_USER_MASK
141 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
143 #include <trace/events/kvm.h>
145 #define CREATE_TRACE_POINTS
146 #include "mmutrace.h"
148 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
149 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
151 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
153 /* make pte_list_desc fit well in cache line */
154 #define PTE_LIST_EXT 3
156 struct pte_list_desc {
157 u64 *sptes[PTE_LIST_EXT];
158 struct pte_list_desc *more;
161 struct kvm_shadow_walk_iterator {
169 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
170 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
171 shadow_walk_okay(&(_walker)); \
172 shadow_walk_next(&(_walker)))
174 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
175 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
176 shadow_walk_okay(&(_walker)) && \
177 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
178 __shadow_walk_next(&(_walker), spte))
180 static struct kmem_cache *pte_list_desc_cache;
181 static struct kmem_cache *mmu_page_header_cache;
182 static struct percpu_counter kvm_total_used_mmu_pages;
184 static u64 __read_mostly shadow_nx_mask;
185 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
186 static u64 __read_mostly shadow_user_mask;
187 static u64 __read_mostly shadow_accessed_mask;
188 static u64 __read_mostly shadow_dirty_mask;
189 static u64 __read_mostly shadow_mmio_mask;
191 static void mmu_spte_set(u64 *sptep, u64 spte);
192 static void mmu_free_roots(struct kvm_vcpu *vcpu);
194 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask)
196 shadow_mmio_mask = mmio_mask;
198 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
201 * the low bit of the generation number is always presumed to be zero.
202 * This disables mmio caching during memslot updates. The concept is
203 * similar to a seqcount but instead of retrying the access we just punt
204 * and ignore the cache.
206 * spte bits 3-11 are used as bits 1-9 of the generation number,
207 * the bits 52-61 are used as bits 10-19 of the generation number.
209 #define MMIO_SPTE_GEN_LOW_SHIFT 2
210 #define MMIO_SPTE_GEN_HIGH_SHIFT 52
212 #define MMIO_GEN_SHIFT 20
213 #define MMIO_GEN_LOW_SHIFT 10
214 #define MMIO_GEN_LOW_MASK ((1 << MMIO_GEN_LOW_SHIFT) - 2)
215 #define MMIO_GEN_MASK ((1 << MMIO_GEN_SHIFT) - 1)
216 #define MMIO_MAX_GEN ((1 << MMIO_GEN_SHIFT) - 1)
218 static u64 generation_mmio_spte_mask(unsigned int gen)
222 WARN_ON(gen > MMIO_MAX_GEN);
224 mask = (gen & MMIO_GEN_LOW_MASK) << MMIO_SPTE_GEN_LOW_SHIFT;
225 mask |= ((u64)gen >> MMIO_GEN_LOW_SHIFT) << MMIO_SPTE_GEN_HIGH_SHIFT;
229 static unsigned int get_mmio_spte_generation(u64 spte)
233 spte &= ~shadow_mmio_mask;
235 gen = (spte >> MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_GEN_LOW_MASK;
236 gen |= (spte >> MMIO_SPTE_GEN_HIGH_SHIFT) << MMIO_GEN_LOW_SHIFT;
240 static unsigned int kvm_current_mmio_generation(struct kvm *kvm)
243 * Init kvm generation close to MMIO_MAX_GEN to easily test the
244 * code of handling generation number wrap-around.
246 return (kvm_memslots(kvm)->generation +
247 MMIO_MAX_GEN - 150) & MMIO_GEN_MASK;
250 static void mark_mmio_spte(struct kvm *kvm, u64 *sptep, u64 gfn,
253 unsigned int gen = kvm_current_mmio_generation(kvm);
254 u64 mask = generation_mmio_spte_mask(gen);
256 access &= ACC_WRITE_MASK | ACC_USER_MASK;
257 mask |= shadow_mmio_mask | access | gfn << PAGE_SHIFT;
259 trace_mark_mmio_spte(sptep, gfn, access, gen);
260 mmu_spte_set(sptep, mask);
263 static bool is_mmio_spte(u64 spte)
265 return (spte & shadow_mmio_mask) == shadow_mmio_mask;
268 static gfn_t get_mmio_spte_gfn(u64 spte)
270 u64 mask = generation_mmio_spte_mask(MMIO_MAX_GEN) | shadow_mmio_mask;
271 return (spte & ~mask) >> PAGE_SHIFT;
274 static unsigned get_mmio_spte_access(u64 spte)
276 u64 mask = generation_mmio_spte_mask(MMIO_MAX_GEN) | shadow_mmio_mask;
277 return (spte & ~mask) & ~PAGE_MASK;
280 static bool set_mmio_spte(struct kvm *kvm, u64 *sptep, gfn_t gfn,
281 pfn_t pfn, unsigned access)
283 if (unlikely(is_noslot_pfn(pfn))) {
284 mark_mmio_spte(kvm, sptep, gfn, access);
291 static bool check_mmio_spte(struct kvm *kvm, u64 spte)
293 unsigned int kvm_gen, spte_gen;
295 kvm_gen = kvm_current_mmio_generation(kvm);
296 spte_gen = get_mmio_spte_generation(spte);
298 trace_check_mmio_spte(spte, kvm_gen, spte_gen);
299 return likely(kvm_gen == spte_gen);
302 static inline u64 rsvd_bits(int s, int e)
304 return ((1ULL << (e - s + 1)) - 1) << s;
307 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
308 u64 dirty_mask, u64 nx_mask, u64 x_mask)
310 shadow_user_mask = user_mask;
311 shadow_accessed_mask = accessed_mask;
312 shadow_dirty_mask = dirty_mask;
313 shadow_nx_mask = nx_mask;
314 shadow_x_mask = x_mask;
316 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
318 static int is_cpuid_PSE36(void)
323 static int is_nx(struct kvm_vcpu *vcpu)
325 return vcpu->arch.efer & EFER_NX;
328 static int is_shadow_present_pte(u64 pte)
330 return pte & PT_PRESENT_MASK && !is_mmio_spte(pte);
333 static int is_large_pte(u64 pte)
335 return pte & PT_PAGE_SIZE_MASK;
338 static int is_rmap_spte(u64 pte)
340 return is_shadow_present_pte(pte);
343 static int is_last_spte(u64 pte, int level)
345 if (level == PT_PAGE_TABLE_LEVEL)
347 if (is_large_pte(pte))
352 static pfn_t spte_to_pfn(u64 pte)
354 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
357 static gfn_t pse36_gfn_delta(u32 gpte)
359 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
361 return (gpte & PT32_DIR_PSE36_MASK) << shift;
365 static void __set_spte(u64 *sptep, u64 spte)
370 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
375 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
377 return xchg(sptep, spte);
380 static u64 __get_spte_lockless(u64 *sptep)
382 return ACCESS_ONCE(*sptep);
385 static bool __check_direct_spte_mmio_pf(u64 spte)
387 /* It is valid if the spte is zapped. */
399 static void count_spte_clear(u64 *sptep, u64 spte)
401 struct kvm_mmu_page *sp = page_header(__pa(sptep));
403 if (is_shadow_present_pte(spte))
406 /* Ensure the spte is completely set before we increase the count */
408 sp->clear_spte_count++;
411 static void __set_spte(u64 *sptep, u64 spte)
413 union split_spte *ssptep, sspte;
415 ssptep = (union split_spte *)sptep;
416 sspte = (union split_spte)spte;
418 ssptep->spte_high = sspte.spte_high;
421 * If we map the spte from nonpresent to present, We should store
422 * the high bits firstly, then set present bit, so cpu can not
423 * fetch this spte while we are setting the spte.
427 ssptep->spte_low = sspte.spte_low;
430 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
432 union split_spte *ssptep, sspte;
434 ssptep = (union split_spte *)sptep;
435 sspte = (union split_spte)spte;
437 ssptep->spte_low = sspte.spte_low;
440 * If we map the spte from present to nonpresent, we should clear
441 * present bit firstly to avoid vcpu fetch the old high bits.
445 ssptep->spte_high = sspte.spte_high;
446 count_spte_clear(sptep, spte);
449 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
451 union split_spte *ssptep, sspte, orig;
453 ssptep = (union split_spte *)sptep;
454 sspte = (union split_spte)spte;
456 /* xchg acts as a barrier before the setting of the high bits */
457 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
458 orig.spte_high = ssptep->spte_high;
459 ssptep->spte_high = sspte.spte_high;
460 count_spte_clear(sptep, spte);
466 * The idea using the light way get the spte on x86_32 guest is from
467 * gup_get_pte(arch/x86/mm/gup.c).
469 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
470 * coalesces them and we are running out of the MMU lock. Therefore
471 * we need to protect against in-progress updates of the spte.
473 * Reading the spte while an update is in progress may get the old value
474 * for the high part of the spte. The race is fine for a present->non-present
475 * change (because the high part of the spte is ignored for non-present spte),
476 * but for a present->present change we must reread the spte.
478 * All such changes are done in two steps (present->non-present and
479 * non-present->present), hence it is enough to count the number of
480 * present->non-present updates: if it changed while reading the spte,
481 * we might have hit the race. This is done using clear_spte_count.
483 static u64 __get_spte_lockless(u64 *sptep)
485 struct kvm_mmu_page *sp = page_header(__pa(sptep));
486 union split_spte spte, *orig = (union split_spte *)sptep;
490 count = sp->clear_spte_count;
493 spte.spte_low = orig->spte_low;
496 spte.spte_high = orig->spte_high;
499 if (unlikely(spte.spte_low != orig->spte_low ||
500 count != sp->clear_spte_count))
506 static bool __check_direct_spte_mmio_pf(u64 spte)
508 union split_spte sspte = (union split_spte)spte;
509 u32 high_mmio_mask = shadow_mmio_mask >> 32;
511 /* It is valid if the spte is zapped. */
515 /* It is valid if the spte is being zapped. */
516 if (sspte.spte_low == 0ull &&
517 (sspte.spte_high & high_mmio_mask) == high_mmio_mask)
524 static bool spte_is_locklessly_modifiable(u64 spte)
526 return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) ==
527 (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE);
530 static bool spte_has_volatile_bits(u64 spte)
533 * Always atomicly update spte if it can be updated
534 * out of mmu-lock, it can ensure dirty bit is not lost,
535 * also, it can help us to get a stable is_writable_pte()
536 * to ensure tlb flush is not missed.
538 if (spte_is_locklessly_modifiable(spte))
541 if (!shadow_accessed_mask)
544 if (!is_shadow_present_pte(spte))
547 if ((spte & shadow_accessed_mask) &&
548 (!is_writable_pte(spte) || (spte & shadow_dirty_mask)))
554 static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask)
556 return (old_spte & bit_mask) && !(new_spte & bit_mask);
559 /* Rules for using mmu_spte_set:
560 * Set the sptep from nonpresent to present.
561 * Note: the sptep being assigned *must* be either not present
562 * or in a state where the hardware will not attempt to update
565 static void mmu_spte_set(u64 *sptep, u64 new_spte)
567 WARN_ON(is_shadow_present_pte(*sptep));
568 __set_spte(sptep, new_spte);
571 /* Rules for using mmu_spte_update:
572 * Update the state bits, it means the mapped pfn is not changged.
574 * Whenever we overwrite a writable spte with a read-only one we
575 * should flush remote TLBs. Otherwise rmap_write_protect
576 * will find a read-only spte, even though the writable spte
577 * might be cached on a CPU's TLB, the return value indicates this
580 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
582 u64 old_spte = *sptep;
585 WARN_ON(!is_rmap_spte(new_spte));
587 if (!is_shadow_present_pte(old_spte)) {
588 mmu_spte_set(sptep, new_spte);
592 if (!spte_has_volatile_bits(old_spte))
593 __update_clear_spte_fast(sptep, new_spte);
595 old_spte = __update_clear_spte_slow(sptep, new_spte);
598 * For the spte updated out of mmu-lock is safe, since
599 * we always atomicly update it, see the comments in
600 * spte_has_volatile_bits().
602 if (is_writable_pte(old_spte) && !is_writable_pte(new_spte))
605 if (!shadow_accessed_mask)
608 if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask))
609 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
610 if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask))
611 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
617 * Rules for using mmu_spte_clear_track_bits:
618 * It sets the sptep from present to nonpresent, and track the
619 * state bits, it is used to clear the last level sptep.
621 static int mmu_spte_clear_track_bits(u64 *sptep)
624 u64 old_spte = *sptep;
626 if (!spte_has_volatile_bits(old_spte))
627 __update_clear_spte_fast(sptep, 0ull);
629 old_spte = __update_clear_spte_slow(sptep, 0ull);
631 if (!is_rmap_spte(old_spte))
634 pfn = spte_to_pfn(old_spte);
637 * KVM does not hold the refcount of the page used by
638 * kvm mmu, before reclaiming the page, we should
639 * unmap it from mmu first.
641 WARN_ON(!kvm_is_mmio_pfn(pfn) && !page_count(pfn_to_page(pfn)));
643 if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
644 kvm_set_pfn_accessed(pfn);
645 if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask))
646 kvm_set_pfn_dirty(pfn);
651 * Rules for using mmu_spte_clear_no_track:
652 * Directly clear spte without caring the state bits of sptep,
653 * it is used to set the upper level spte.
655 static void mmu_spte_clear_no_track(u64 *sptep)
657 __update_clear_spte_fast(sptep, 0ull);
660 static u64 mmu_spte_get_lockless(u64 *sptep)
662 return __get_spte_lockless(sptep);
665 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
668 * Prevent page table teardown by making any free-er wait during
669 * kvm_flush_remote_tlbs() IPI to all active vcpus.
672 vcpu->mode = READING_SHADOW_PAGE_TABLES;
674 * Make sure a following spte read is not reordered ahead of the write
680 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
683 * Make sure the write to vcpu->mode is not reordered in front of
684 * reads to sptes. If it does, kvm_commit_zap_page() can see us
685 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
688 vcpu->mode = OUTSIDE_GUEST_MODE;
692 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
693 struct kmem_cache *base_cache, int min)
697 if (cache->nobjs >= min)
699 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
700 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
703 cache->objects[cache->nobjs++] = obj;
708 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
713 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
714 struct kmem_cache *cache)
717 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
720 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
725 if (cache->nobjs >= min)
727 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
728 page = (void *)__get_free_page(GFP_KERNEL);
731 cache->objects[cache->nobjs++] = page;
736 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
739 free_page((unsigned long)mc->objects[--mc->nobjs]);
742 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
746 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
747 pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
750 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
753 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
754 mmu_page_header_cache, 4);
759 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
761 mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
762 pte_list_desc_cache);
763 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
764 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
765 mmu_page_header_cache);
768 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
773 p = mc->objects[--mc->nobjs];
777 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
779 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
782 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
784 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
787 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
789 if (!sp->role.direct)
790 return sp->gfns[index];
792 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
795 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
798 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
800 sp->gfns[index] = gfn;
804 * Return the pointer to the large page information for a given gfn,
805 * handling slots that are not large page aligned.
807 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
808 struct kvm_memory_slot *slot,
813 idx = gfn_to_index(gfn, slot->base_gfn, level);
814 return &slot->arch.lpage_info[level - 2][idx];
817 static void account_shadowed(struct kvm *kvm, gfn_t gfn)
819 struct kvm_memory_slot *slot;
820 struct kvm_lpage_info *linfo;
823 slot = gfn_to_memslot(kvm, gfn);
824 for (i = PT_DIRECTORY_LEVEL;
825 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
826 linfo = lpage_info_slot(gfn, slot, i);
827 linfo->write_count += 1;
829 kvm->arch.indirect_shadow_pages++;
832 static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
834 struct kvm_memory_slot *slot;
835 struct kvm_lpage_info *linfo;
838 slot = gfn_to_memslot(kvm, gfn);
839 for (i = PT_DIRECTORY_LEVEL;
840 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
841 linfo = lpage_info_slot(gfn, slot, i);
842 linfo->write_count -= 1;
843 WARN_ON(linfo->write_count < 0);
845 kvm->arch.indirect_shadow_pages--;
848 static int has_wrprotected_page(struct kvm *kvm,
852 struct kvm_memory_slot *slot;
853 struct kvm_lpage_info *linfo;
855 slot = gfn_to_memslot(kvm, gfn);
857 linfo = lpage_info_slot(gfn, slot, level);
858 return linfo->write_count;
864 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
866 unsigned long page_size;
869 page_size = kvm_host_page_size(kvm, gfn);
871 for (i = PT_PAGE_TABLE_LEVEL;
872 i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
873 if (page_size >= KVM_HPAGE_SIZE(i))
882 static struct kvm_memory_slot *
883 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
886 struct kvm_memory_slot *slot;
888 slot = gfn_to_memslot(vcpu->kvm, gfn);
889 if (!slot || slot->flags & KVM_MEMSLOT_INVALID ||
890 (no_dirty_log && slot->dirty_bitmap))
896 static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn)
898 return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true);
901 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
903 int host_level, level, max_level;
905 host_level = host_mapping_level(vcpu->kvm, large_gfn);
907 if (host_level == PT_PAGE_TABLE_LEVEL)
910 max_level = min(kvm_x86_ops->get_lpage_level(), host_level);
912 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
913 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
920 * Pte mapping structures:
922 * If pte_list bit zero is zero, then pte_list point to the spte.
924 * If pte_list bit zero is one, (then pte_list & ~1) points to a struct
925 * pte_list_desc containing more mappings.
927 * Returns the number of pte entries before the spte was added or zero if
928 * the spte was not added.
931 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
932 unsigned long *pte_list)
934 struct pte_list_desc *desc;
938 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
939 *pte_list = (unsigned long)spte;
940 } else if (!(*pte_list & 1)) {
941 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
942 desc = mmu_alloc_pte_list_desc(vcpu);
943 desc->sptes[0] = (u64 *)*pte_list;
944 desc->sptes[1] = spte;
945 *pte_list = (unsigned long)desc | 1;
948 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
949 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
950 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
952 count += PTE_LIST_EXT;
954 if (desc->sptes[PTE_LIST_EXT-1]) {
955 desc->more = mmu_alloc_pte_list_desc(vcpu);
958 for (i = 0; desc->sptes[i]; ++i)
960 desc->sptes[i] = spte;
966 pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc,
967 int i, struct pte_list_desc *prev_desc)
971 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
973 desc->sptes[i] = desc->sptes[j];
974 desc->sptes[j] = NULL;
977 if (!prev_desc && !desc->more)
978 *pte_list = (unsigned long)desc->sptes[0];
981 prev_desc->more = desc->more;
983 *pte_list = (unsigned long)desc->more | 1;
984 mmu_free_pte_list_desc(desc);
987 static void pte_list_remove(u64 *spte, unsigned long *pte_list)
989 struct pte_list_desc *desc;
990 struct pte_list_desc *prev_desc;
994 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
996 } else if (!(*pte_list & 1)) {
997 rmap_printk("pte_list_remove: %p 1->0\n", spte);
998 if ((u64 *)*pte_list != spte) {
999 printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte);
1004 rmap_printk("pte_list_remove: %p many->many\n", spte);
1005 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
1008 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
1009 if (desc->sptes[i] == spte) {
1010 pte_list_desc_remove_entry(pte_list,
1018 pr_err("pte_list_remove: %p many->many\n", spte);
1023 typedef void (*pte_list_walk_fn) (u64 *spte);
1024 static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn)
1026 struct pte_list_desc *desc;
1032 if (!(*pte_list & 1))
1033 return fn((u64 *)*pte_list);
1035 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
1037 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
1043 static unsigned long *__gfn_to_rmap(gfn_t gfn, int level,
1044 struct kvm_memory_slot *slot)
1048 idx = gfn_to_index(gfn, slot->base_gfn, level);
1049 return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx];
1053 * Take gfn and return the reverse mapping to it.
1055 static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
1057 struct kvm_memory_slot *slot;
1059 slot = gfn_to_memslot(kvm, gfn);
1060 return __gfn_to_rmap(gfn, level, slot);
1063 static bool rmap_can_add(struct kvm_vcpu *vcpu)
1065 struct kvm_mmu_memory_cache *cache;
1067 cache = &vcpu->arch.mmu_pte_list_desc_cache;
1068 return mmu_memory_cache_free_objects(cache);
1071 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1073 struct kvm_mmu_page *sp;
1074 unsigned long *rmapp;
1076 sp = page_header(__pa(spte));
1077 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1078 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1079 return pte_list_add(vcpu, spte, rmapp);
1082 static void rmap_remove(struct kvm *kvm, u64 *spte)
1084 struct kvm_mmu_page *sp;
1086 unsigned long *rmapp;
1088 sp = page_header(__pa(spte));
1089 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1090 rmapp = gfn_to_rmap(kvm, gfn, sp->role.level);
1091 pte_list_remove(spte, rmapp);
1095 * Used by the following functions to iterate through the sptes linked by a
1096 * rmap. All fields are private and not assumed to be used outside.
1098 struct rmap_iterator {
1099 /* private fields */
1100 struct pte_list_desc *desc; /* holds the sptep if not NULL */
1101 int pos; /* index of the sptep */
1105 * Iteration must be started by this function. This should also be used after
1106 * removing/dropping sptes from the rmap link because in such cases the
1107 * information in the itererator may not be valid.
1109 * Returns sptep if found, NULL otherwise.
1111 static u64 *rmap_get_first(unsigned long rmap, struct rmap_iterator *iter)
1121 iter->desc = (struct pte_list_desc *)(rmap & ~1ul);
1123 return iter->desc->sptes[iter->pos];
1127 * Must be used with a valid iterator: e.g. after rmap_get_first().
1129 * Returns sptep if found, NULL otherwise.
1131 static u64 *rmap_get_next(struct rmap_iterator *iter)
1134 if (iter->pos < PTE_LIST_EXT - 1) {
1138 sptep = iter->desc->sptes[iter->pos];
1143 iter->desc = iter->desc->more;
1147 /* desc->sptes[0] cannot be NULL */
1148 return iter->desc->sptes[iter->pos];
1155 static void drop_spte(struct kvm *kvm, u64 *sptep)
1157 if (mmu_spte_clear_track_bits(sptep))
1158 rmap_remove(kvm, sptep);
1162 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1164 if (is_large_pte(*sptep)) {
1165 WARN_ON(page_header(__pa(sptep))->role.level ==
1166 PT_PAGE_TABLE_LEVEL);
1167 drop_spte(kvm, sptep);
1175 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1177 if (__drop_large_spte(vcpu->kvm, sptep))
1178 kvm_flush_remote_tlbs(vcpu->kvm);
1182 * Write-protect on the specified @sptep, @pt_protect indicates whether
1183 * spte writ-protection is caused by protecting shadow page table.
1184 * @flush indicates whether tlb need be flushed.
1186 * Note: write protection is difference between drity logging and spte
1188 * - for dirty logging, the spte can be set to writable at anytime if
1189 * its dirty bitmap is properly set.
1190 * - for spte protection, the spte can be writable only after unsync-ing
1193 * Return true if the spte is dropped.
1196 spte_write_protect(struct kvm *kvm, u64 *sptep, bool *flush, bool pt_protect)
1200 if (!is_writable_pte(spte) &&
1201 !(pt_protect && spte_is_locklessly_modifiable(spte)))
1204 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1206 if (__drop_large_spte(kvm, sptep)) {
1212 spte &= ~SPTE_MMU_WRITEABLE;
1213 spte = spte & ~PT_WRITABLE_MASK;
1215 *flush |= mmu_spte_update(sptep, spte);
1219 static bool __rmap_write_protect(struct kvm *kvm, unsigned long *rmapp,
1223 struct rmap_iterator iter;
1226 for (sptep = rmap_get_first(*rmapp, &iter); sptep;) {
1227 BUG_ON(!(*sptep & PT_PRESENT_MASK));
1228 if (spte_write_protect(kvm, sptep, &flush, pt_protect)) {
1229 sptep = rmap_get_first(*rmapp, &iter);
1233 sptep = rmap_get_next(&iter);
1240 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1241 * @kvm: kvm instance
1242 * @slot: slot to protect
1243 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1244 * @mask: indicates which pages we should protect
1246 * Used when we do not need to care about huge page mappings: e.g. during dirty
1247 * logging we do not have any such mappings.
1249 void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1250 struct kvm_memory_slot *slot,
1251 gfn_t gfn_offset, unsigned long mask)
1253 unsigned long *rmapp;
1256 rmapp = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1257 PT_PAGE_TABLE_LEVEL, slot);
1258 __rmap_write_protect(kvm, rmapp, false);
1260 /* clear the first set bit */
1265 static bool rmap_write_protect(struct kvm *kvm, u64 gfn)
1267 struct kvm_memory_slot *slot;
1268 unsigned long *rmapp;
1270 bool write_protected = false;
1272 slot = gfn_to_memslot(kvm, gfn);
1274 for (i = PT_PAGE_TABLE_LEVEL;
1275 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
1276 rmapp = __gfn_to_rmap(gfn, i, slot);
1277 write_protected |= __rmap_write_protect(kvm, rmapp, true);
1280 return write_protected;
1283 static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
1284 struct kvm_memory_slot *slot, unsigned long data)
1287 struct rmap_iterator iter;
1288 int need_tlb_flush = 0;
1290 while ((sptep = rmap_get_first(*rmapp, &iter))) {
1291 BUG_ON(!(*sptep & PT_PRESENT_MASK));
1292 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", sptep, *sptep);
1294 drop_spte(kvm, sptep);
1298 return need_tlb_flush;
1301 static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
1302 struct kvm_memory_slot *slot, unsigned long data)
1305 struct rmap_iterator iter;
1308 pte_t *ptep = (pte_t *)data;
1311 WARN_ON(pte_huge(*ptep));
1312 new_pfn = pte_pfn(*ptep);
1314 for (sptep = rmap_get_first(*rmapp, &iter); sptep;) {
1315 BUG_ON(!is_shadow_present_pte(*sptep));
1316 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", sptep, *sptep);
1320 if (pte_write(*ptep)) {
1321 drop_spte(kvm, sptep);
1322 sptep = rmap_get_first(*rmapp, &iter);
1324 new_spte = *sptep & ~PT64_BASE_ADDR_MASK;
1325 new_spte |= (u64)new_pfn << PAGE_SHIFT;
1327 new_spte &= ~PT_WRITABLE_MASK;
1328 new_spte &= ~SPTE_HOST_WRITEABLE;
1329 new_spte &= ~shadow_accessed_mask;
1331 mmu_spte_clear_track_bits(sptep);
1332 mmu_spte_set(sptep, new_spte);
1333 sptep = rmap_get_next(&iter);
1338 kvm_flush_remote_tlbs(kvm);
1343 static int kvm_handle_hva_range(struct kvm *kvm,
1344 unsigned long start,
1347 int (*handler)(struct kvm *kvm,
1348 unsigned long *rmapp,
1349 struct kvm_memory_slot *slot,
1350 unsigned long data))
1354 struct kvm_memslots *slots;
1355 struct kvm_memory_slot *memslot;
1357 slots = kvm_memslots(kvm);
1359 kvm_for_each_memslot(memslot, slots) {
1360 unsigned long hva_start, hva_end;
1361 gfn_t gfn_start, gfn_end;
1363 hva_start = max(start, memslot->userspace_addr);
1364 hva_end = min(end, memslot->userspace_addr +
1365 (memslot->npages << PAGE_SHIFT));
1366 if (hva_start >= hva_end)
1369 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1370 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1372 gfn_start = hva_to_gfn_memslot(hva_start, memslot);
1373 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1375 for (j = PT_PAGE_TABLE_LEVEL;
1376 j < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++j) {
1377 unsigned long idx, idx_end;
1378 unsigned long *rmapp;
1381 * {idx(page_j) | page_j intersects with
1382 * [hva_start, hva_end)} = {idx, idx+1, ..., idx_end}.
1384 idx = gfn_to_index(gfn_start, memslot->base_gfn, j);
1385 idx_end = gfn_to_index(gfn_end - 1, memslot->base_gfn, j);
1387 rmapp = __gfn_to_rmap(gfn_start, j, memslot);
1389 for (; idx <= idx_end; ++idx)
1390 ret |= handler(kvm, rmapp++, memslot, data);
1397 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1399 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
1400 struct kvm_memory_slot *slot,
1401 unsigned long data))
1403 return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1406 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
1408 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
1411 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)
1413 return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1416 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1418 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1421 static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1422 struct kvm_memory_slot *slot, unsigned long data)
1425 struct rmap_iterator uninitialized_var(iter);
1429 * In case of absence of EPT Access and Dirty Bits supports,
1430 * emulate the accessed bit for EPT, by checking if this page has
1431 * an EPT mapping, and clearing it if it does. On the next access,
1432 * a new EPT mapping will be established.
1433 * This has some overhead, but not as much as the cost of swapping
1434 * out actively used pages or breaking up actively used hugepages.
1436 if (!shadow_accessed_mask) {
1437 young = kvm_unmap_rmapp(kvm, rmapp, slot, data);
1441 for (sptep = rmap_get_first(*rmapp, &iter); sptep;
1442 sptep = rmap_get_next(&iter)) {
1443 BUG_ON(!is_shadow_present_pte(*sptep));
1445 if (*sptep & shadow_accessed_mask) {
1447 clear_bit((ffs(shadow_accessed_mask) - 1),
1448 (unsigned long *)sptep);
1452 /* @data has hva passed to kvm_age_hva(). */
1453 trace_kvm_age_page(data, slot, young);
1457 static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1458 struct kvm_memory_slot *slot, unsigned long data)
1461 struct rmap_iterator iter;
1465 * If there's no access bit in the secondary pte set by the
1466 * hardware it's up to gup-fast/gup to set the access bit in
1467 * the primary pte or in the page structure.
1469 if (!shadow_accessed_mask)
1472 for (sptep = rmap_get_first(*rmapp, &iter); sptep;
1473 sptep = rmap_get_next(&iter)) {
1474 BUG_ON(!is_shadow_present_pte(*sptep));
1476 if (*sptep & shadow_accessed_mask) {
1485 #define RMAP_RECYCLE_THRESHOLD 1000
1487 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1489 unsigned long *rmapp;
1490 struct kvm_mmu_page *sp;
1492 sp = page_header(__pa(spte));
1494 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1496 kvm_unmap_rmapp(vcpu->kvm, rmapp, NULL, 0);
1497 kvm_flush_remote_tlbs(vcpu->kvm);
1500 int kvm_age_hva(struct kvm *kvm, unsigned long hva)
1502 return kvm_handle_hva(kvm, hva, hva, kvm_age_rmapp);
1505 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1507 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1511 static int is_empty_shadow_page(u64 *spt)
1516 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1517 if (is_shadow_present_pte(*pos)) {
1518 printk(KERN_ERR "%s: %p %llx\n", __func__,
1527 * This value is the sum of all of the kvm instances's
1528 * kvm->arch.n_used_mmu_pages values. We need a global,
1529 * aggregate version in order to make the slab shrinker
1532 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1534 kvm->arch.n_used_mmu_pages += nr;
1535 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1538 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1540 ASSERT(is_empty_shadow_page(sp->spt));
1541 hlist_del(&sp->hash_link);
1542 list_del(&sp->link);
1543 free_page((unsigned long)sp->spt);
1544 if (!sp->role.direct)
1545 free_page((unsigned long)sp->gfns);
1546 kmem_cache_free(mmu_page_header_cache, sp);
1549 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1551 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
1554 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1555 struct kvm_mmu_page *sp, u64 *parent_pte)
1560 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1563 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1566 pte_list_remove(parent_pte, &sp->parent_ptes);
1569 static void drop_parent_pte(struct kvm_mmu_page *sp,
1572 mmu_page_remove_parent_pte(sp, parent_pte);
1573 mmu_spte_clear_no_track(parent_pte);
1576 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
1577 u64 *parent_pte, int direct)
1579 struct kvm_mmu_page *sp;
1581 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1582 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1584 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1585 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1588 * The active_mmu_pages list is the FIFO list, do not move the
1589 * page until it is zapped. kvm_zap_obsolete_pages depends on
1590 * this feature. See the comments in kvm_zap_obsolete_pages().
1592 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1593 sp->parent_ptes = 0;
1594 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1595 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1599 static void mark_unsync(u64 *spte);
1600 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1602 pte_list_walk(&sp->parent_ptes, mark_unsync);
1605 static void mark_unsync(u64 *spte)
1607 struct kvm_mmu_page *sp;
1610 sp = page_header(__pa(spte));
1611 index = spte - sp->spt;
1612 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1614 if (sp->unsync_children++)
1616 kvm_mmu_mark_parents_unsync(sp);
1619 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1620 struct kvm_mmu_page *sp)
1625 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1629 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1630 struct kvm_mmu_page *sp, u64 *spte,
1636 #define KVM_PAGE_ARRAY_NR 16
1638 struct kvm_mmu_pages {
1639 struct mmu_page_and_offset {
1640 struct kvm_mmu_page *sp;
1642 } page[KVM_PAGE_ARRAY_NR];
1646 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1652 for (i=0; i < pvec->nr; i++)
1653 if (pvec->page[i].sp == sp)
1656 pvec->page[pvec->nr].sp = sp;
1657 pvec->page[pvec->nr].idx = idx;
1659 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1662 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1663 struct kvm_mmu_pages *pvec)
1665 int i, ret, nr_unsync_leaf = 0;
1667 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1668 struct kvm_mmu_page *child;
1669 u64 ent = sp->spt[i];
1671 if (!is_shadow_present_pte(ent) || is_large_pte(ent))
1672 goto clear_child_bitmap;
1674 child = page_header(ent & PT64_BASE_ADDR_MASK);
1676 if (child->unsync_children) {
1677 if (mmu_pages_add(pvec, child, i))
1680 ret = __mmu_unsync_walk(child, pvec);
1682 goto clear_child_bitmap;
1684 nr_unsync_leaf += ret;
1687 } else if (child->unsync) {
1689 if (mmu_pages_add(pvec, child, i))
1692 goto clear_child_bitmap;
1697 __clear_bit(i, sp->unsync_child_bitmap);
1698 sp->unsync_children--;
1699 WARN_ON((int)sp->unsync_children < 0);
1703 return nr_unsync_leaf;
1706 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1707 struct kvm_mmu_pages *pvec)
1709 if (!sp->unsync_children)
1712 mmu_pages_add(pvec, sp, 0);
1713 return __mmu_unsync_walk(sp, pvec);
1716 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1718 WARN_ON(!sp->unsync);
1719 trace_kvm_mmu_sync_page(sp);
1721 --kvm->stat.mmu_unsync;
1724 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1725 struct list_head *invalid_list);
1726 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1727 struct list_head *invalid_list);
1730 * NOTE: we should pay more attention on the zapped-obsolete page
1731 * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk
1732 * since it has been deleted from active_mmu_pages but still can be found
1735 * for_each_gfn_indirect_valid_sp has skipped that kind of page and
1736 * kvm_mmu_get_page(), the only user of for_each_gfn_sp(), has skipped
1737 * all the obsolete pages.
1739 #define for_each_gfn_sp(_kvm, _sp, _gfn) \
1740 hlist_for_each_entry(_sp, \
1741 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \
1742 if ((_sp)->gfn != (_gfn)) {} else
1744 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
1745 for_each_gfn_sp(_kvm, _sp, _gfn) \
1746 if ((_sp)->role.direct || (_sp)->role.invalid) {} else
1748 /* @sp->gfn should be write-protected at the call site */
1749 static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1750 struct list_head *invalid_list, bool clear_unsync)
1752 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
1753 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1758 kvm_unlink_unsync_page(vcpu->kvm, sp);
1760 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1761 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1765 kvm_mmu_flush_tlb(vcpu);
1769 static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
1770 struct kvm_mmu_page *sp)
1772 LIST_HEAD(invalid_list);
1775 ret = __kvm_sync_page(vcpu, sp, &invalid_list, false);
1777 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1782 #ifdef CONFIG_KVM_MMU_AUDIT
1783 #include "mmu_audit.c"
1785 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1786 static void mmu_audit_disable(void) { }
1789 static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1790 struct list_head *invalid_list)
1792 return __kvm_sync_page(vcpu, sp, invalid_list, true);
1795 /* @gfn should be write-protected at the call site */
1796 static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
1798 struct kvm_mmu_page *s;
1799 LIST_HEAD(invalid_list);
1802 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
1806 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1807 kvm_unlink_unsync_page(vcpu->kvm, s);
1808 if ((s->role.cr4_pae != !!is_pae(vcpu)) ||
1809 (vcpu->arch.mmu.sync_page(vcpu, s))) {
1810 kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list);
1816 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1818 kvm_mmu_flush_tlb(vcpu);
1821 struct mmu_page_path {
1822 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1823 unsigned int idx[PT64_ROOT_LEVEL-1];
1826 #define for_each_sp(pvec, sp, parents, i) \
1827 for (i = mmu_pages_next(&pvec, &parents, -1), \
1828 sp = pvec.page[i].sp; \
1829 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1830 i = mmu_pages_next(&pvec, &parents, i))
1832 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1833 struct mmu_page_path *parents,
1838 for (n = i+1; n < pvec->nr; n++) {
1839 struct kvm_mmu_page *sp = pvec->page[n].sp;
1841 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1842 parents->idx[0] = pvec->page[n].idx;
1846 parents->parent[sp->role.level-2] = sp;
1847 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1853 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1855 struct kvm_mmu_page *sp;
1856 unsigned int level = 0;
1859 unsigned int idx = parents->idx[level];
1861 sp = parents->parent[level];
1865 --sp->unsync_children;
1866 WARN_ON((int)sp->unsync_children < 0);
1867 __clear_bit(idx, sp->unsync_child_bitmap);
1869 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
1872 static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1873 struct mmu_page_path *parents,
1874 struct kvm_mmu_pages *pvec)
1876 parents->parent[parent->role.level-1] = NULL;
1880 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1881 struct kvm_mmu_page *parent)
1884 struct kvm_mmu_page *sp;
1885 struct mmu_page_path parents;
1886 struct kvm_mmu_pages pages;
1887 LIST_HEAD(invalid_list);
1889 kvm_mmu_pages_init(parent, &parents, &pages);
1890 while (mmu_unsync_walk(parent, &pages)) {
1891 bool protected = false;
1893 for_each_sp(pages, sp, parents, i)
1894 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1897 kvm_flush_remote_tlbs(vcpu->kvm);
1899 for_each_sp(pages, sp, parents, i) {
1900 kvm_sync_page(vcpu, sp, &invalid_list);
1901 mmu_pages_clear_parents(&parents);
1903 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1904 cond_resched_lock(&vcpu->kvm->mmu_lock);
1905 kvm_mmu_pages_init(parent, &parents, &pages);
1909 static void init_shadow_page_table(struct kvm_mmu_page *sp)
1913 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1917 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
1919 sp->write_flooding_count = 0;
1922 static void clear_sp_write_flooding_count(u64 *spte)
1924 struct kvm_mmu_page *sp = page_header(__pa(spte));
1926 __clear_sp_write_flooding_count(sp);
1929 static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
1931 return unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
1934 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1942 union kvm_mmu_page_role role;
1944 struct kvm_mmu_page *sp;
1945 bool need_sync = false;
1947 role = vcpu->arch.mmu.base_role;
1949 role.direct = direct;
1952 role.access = access;
1953 if (!vcpu->arch.mmu.direct_map
1954 && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
1955 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1956 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1957 role.quadrant = quadrant;
1959 for_each_gfn_sp(vcpu->kvm, sp, gfn) {
1960 if (is_obsolete_sp(vcpu->kvm, sp))
1963 if (!need_sync && sp->unsync)
1966 if (sp->role.word != role.word)
1969 if (sp->unsync && kvm_sync_page_transient(vcpu, sp))
1972 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1973 if (sp->unsync_children) {
1974 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1975 kvm_mmu_mark_parents_unsync(sp);
1976 } else if (sp->unsync)
1977 kvm_mmu_mark_parents_unsync(sp);
1979 __clear_sp_write_flooding_count(sp);
1980 trace_kvm_mmu_get_page(sp, false);
1983 ++vcpu->kvm->stat.mmu_cache_miss;
1984 sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct);
1989 hlist_add_head(&sp->hash_link,
1990 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
1992 if (rmap_write_protect(vcpu->kvm, gfn))
1993 kvm_flush_remote_tlbs(vcpu->kvm);
1994 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
1995 kvm_sync_pages(vcpu, gfn);
1997 account_shadowed(vcpu->kvm, gfn);
1999 sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
2000 init_shadow_page_table(sp);
2001 trace_kvm_mmu_get_page(sp, true);
2005 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2006 struct kvm_vcpu *vcpu, u64 addr)
2008 iterator->addr = addr;
2009 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
2010 iterator->level = vcpu->arch.mmu.shadow_root_level;
2012 if (iterator->level == PT64_ROOT_LEVEL &&
2013 vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
2014 !vcpu->arch.mmu.direct_map)
2017 if (iterator->level == PT32E_ROOT_LEVEL) {
2018 iterator->shadow_addr
2019 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
2020 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2022 if (!iterator->shadow_addr)
2023 iterator->level = 0;
2027 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2029 if (iterator->level < PT_PAGE_TABLE_LEVEL)
2032 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2033 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2037 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2040 if (is_last_spte(spte, iterator->level)) {
2041 iterator->level = 0;
2045 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2049 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2051 return __shadow_walk_next(iterator, *iterator->sptep);
2054 static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp, bool accessed)
2058 BUILD_BUG_ON(VMX_EPT_READABLE_MASK != PT_PRESENT_MASK ||
2059 VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2061 spte = __pa(sp->spt) | PT_PRESENT_MASK | PT_WRITABLE_MASK |
2062 shadow_user_mask | shadow_x_mask;
2065 spte |= shadow_accessed_mask;
2067 mmu_spte_set(sptep, spte);
2070 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2071 unsigned direct_access)
2073 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2074 struct kvm_mmu_page *child;
2077 * For the direct sp, if the guest pte's dirty bit
2078 * changed form clean to dirty, it will corrupt the
2079 * sp's access: allow writable in the read-only sp,
2080 * so we should update the spte at this point to get
2081 * a new sp with the correct access.
2083 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
2084 if (child->role.access == direct_access)
2087 drop_parent_pte(child, sptep);
2088 kvm_flush_remote_tlbs(vcpu->kvm);
2092 static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2096 struct kvm_mmu_page *child;
2099 if (is_shadow_present_pte(pte)) {
2100 if (is_last_spte(pte, sp->role.level)) {
2101 drop_spte(kvm, spte);
2102 if (is_large_pte(pte))
2105 child = page_header(pte & PT64_BASE_ADDR_MASK);
2106 drop_parent_pte(child, spte);
2111 if (is_mmio_spte(pte))
2112 mmu_spte_clear_no_track(spte);
2117 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
2118 struct kvm_mmu_page *sp)
2122 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2123 mmu_page_zap_pte(kvm, sp, sp->spt + i);
2126 static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
2128 mmu_page_remove_parent_pte(sp, parent_pte);
2131 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2134 struct rmap_iterator iter;
2136 while ((sptep = rmap_get_first(sp->parent_ptes, &iter)))
2137 drop_parent_pte(sp, sptep);
2140 static int mmu_zap_unsync_children(struct kvm *kvm,
2141 struct kvm_mmu_page *parent,
2142 struct list_head *invalid_list)
2145 struct mmu_page_path parents;
2146 struct kvm_mmu_pages pages;
2148 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
2151 kvm_mmu_pages_init(parent, &parents, &pages);
2152 while (mmu_unsync_walk(parent, &pages)) {
2153 struct kvm_mmu_page *sp;
2155 for_each_sp(pages, sp, parents, i) {
2156 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2157 mmu_pages_clear_parents(&parents);
2160 kvm_mmu_pages_init(parent, &parents, &pages);
2166 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2167 struct list_head *invalid_list)
2171 trace_kvm_mmu_prepare_zap_page(sp);
2172 ++kvm->stat.mmu_shadow_zapped;
2173 ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
2174 kvm_mmu_page_unlink_children(kvm, sp);
2175 kvm_mmu_unlink_parents(kvm, sp);
2177 if (!sp->role.invalid && !sp->role.direct)
2178 unaccount_shadowed(kvm, sp->gfn);
2181 kvm_unlink_unsync_page(kvm, sp);
2182 if (!sp->root_count) {
2185 list_move(&sp->link, invalid_list);
2186 kvm_mod_used_mmu_pages(kvm, -1);
2188 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2191 * The obsolete pages can not be used on any vcpus.
2192 * See the comments in kvm_mmu_invalidate_zap_all_pages().
2194 if (!sp->role.invalid && !is_obsolete_sp(kvm, sp))
2195 kvm_reload_remote_mmus(kvm);
2198 sp->role.invalid = 1;
2202 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2203 struct list_head *invalid_list)
2205 struct kvm_mmu_page *sp, *nsp;
2207 if (list_empty(invalid_list))
2211 * wmb: make sure everyone sees our modifications to the page tables
2212 * rmb: make sure we see changes to vcpu->mode
2217 * Wait for all vcpus to exit guest mode and/or lockless shadow
2220 kvm_flush_remote_tlbs(kvm);
2222 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2223 WARN_ON(!sp->role.invalid || sp->root_count);
2224 kvm_mmu_free_page(sp);
2228 static bool prepare_zap_oldest_mmu_page(struct kvm *kvm,
2229 struct list_head *invalid_list)
2231 struct kvm_mmu_page *sp;
2233 if (list_empty(&kvm->arch.active_mmu_pages))
2236 sp = list_entry(kvm->arch.active_mmu_pages.prev,
2237 struct kvm_mmu_page, link);
2238 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2244 * Changing the number of mmu pages allocated to the vm
2245 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2247 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
2249 LIST_HEAD(invalid_list);
2251 spin_lock(&kvm->mmu_lock);
2253 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2254 /* Need to free some mmu pages to achieve the goal. */
2255 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages)
2256 if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list))
2259 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2260 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2263 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2265 spin_unlock(&kvm->mmu_lock);
2268 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2270 struct kvm_mmu_page *sp;
2271 LIST_HEAD(invalid_list);
2274 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2276 spin_lock(&kvm->mmu_lock);
2277 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2278 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2281 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2283 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2284 spin_unlock(&kvm->mmu_lock);
2288 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2291 * The function is based on mtrr_type_lookup() in
2292 * arch/x86/kernel/cpu/mtrr/generic.c
2294 static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
2299 u8 prev_match, curr_match;
2300 int num_var_ranges = KVM_NR_VAR_MTRR;
2302 if (!mtrr_state->enabled)
2305 /* Make end inclusive end, instead of exclusive */
2308 /* Look in fixed ranges. Just return the type as per start */
2309 if (mtrr_state->have_fixed && (start < 0x100000)) {
2312 if (start < 0x80000) {
2314 idx += (start >> 16);
2315 return mtrr_state->fixed_ranges[idx];
2316 } else if (start < 0xC0000) {
2318 idx += ((start - 0x80000) >> 14);
2319 return mtrr_state->fixed_ranges[idx];
2320 } else if (start < 0x1000000) {
2322 idx += ((start - 0xC0000) >> 12);
2323 return mtrr_state->fixed_ranges[idx];
2328 * Look in variable ranges
2329 * Look of multiple ranges matching this address and pick type
2330 * as per MTRR precedence
2332 if (!(mtrr_state->enabled & 2))
2333 return mtrr_state->def_type;
2336 for (i = 0; i < num_var_ranges; ++i) {
2337 unsigned short start_state, end_state;
2339 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
2342 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
2343 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
2344 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
2345 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
2347 start_state = ((start & mask) == (base & mask));
2348 end_state = ((end & mask) == (base & mask));
2349 if (start_state != end_state)
2352 if ((start & mask) != (base & mask))
2355 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
2356 if (prev_match == 0xFF) {
2357 prev_match = curr_match;
2361 if (prev_match == MTRR_TYPE_UNCACHABLE ||
2362 curr_match == MTRR_TYPE_UNCACHABLE)
2363 return MTRR_TYPE_UNCACHABLE;
2365 if ((prev_match == MTRR_TYPE_WRBACK &&
2366 curr_match == MTRR_TYPE_WRTHROUGH) ||
2367 (prev_match == MTRR_TYPE_WRTHROUGH &&
2368 curr_match == MTRR_TYPE_WRBACK)) {
2369 prev_match = MTRR_TYPE_WRTHROUGH;
2370 curr_match = MTRR_TYPE_WRTHROUGH;
2373 if (prev_match != curr_match)
2374 return MTRR_TYPE_UNCACHABLE;
2377 if (prev_match != 0xFF)
2380 return mtrr_state->def_type;
2383 u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
2387 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
2388 (gfn << PAGE_SHIFT) + PAGE_SIZE);
2389 if (mtrr == 0xfe || mtrr == 0xff)
2390 mtrr = MTRR_TYPE_WRBACK;
2393 EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
2395 static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2397 trace_kvm_mmu_unsync_page(sp);
2398 ++vcpu->kvm->stat.mmu_unsync;
2401 kvm_mmu_mark_parents_unsync(sp);
2404 static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
2406 struct kvm_mmu_page *s;
2408 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
2411 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
2412 __kvm_unsync_page(vcpu, s);
2416 static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2419 struct kvm_mmu_page *s;
2420 bool need_unsync = false;
2422 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
2426 if (s->role.level != PT_PAGE_TABLE_LEVEL)
2433 kvm_unsync_pages(vcpu, gfn);
2437 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2438 unsigned pte_access, int level,
2439 gfn_t gfn, pfn_t pfn, bool speculative,
2440 bool can_unsync, bool host_writable)
2445 if (set_mmio_spte(vcpu->kvm, sptep, gfn, pfn, pte_access))
2448 spte = PT_PRESENT_MASK;
2450 spte |= shadow_accessed_mask;
2452 if (pte_access & ACC_EXEC_MASK)
2453 spte |= shadow_x_mask;
2455 spte |= shadow_nx_mask;
2457 if (pte_access & ACC_USER_MASK)
2458 spte |= shadow_user_mask;
2460 if (level > PT_PAGE_TABLE_LEVEL)
2461 spte |= PT_PAGE_SIZE_MASK;
2463 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2464 kvm_is_mmio_pfn(pfn));
2467 spte |= SPTE_HOST_WRITEABLE;
2469 pte_access &= ~ACC_WRITE_MASK;
2471 spte |= (u64)pfn << PAGE_SHIFT;
2473 if (pte_access & ACC_WRITE_MASK) {
2476 * Other vcpu creates new sp in the window between
2477 * mapping_level() and acquiring mmu-lock. We can
2478 * allow guest to retry the access, the mapping can
2479 * be fixed if guest refault.
2481 if (level > PT_PAGE_TABLE_LEVEL &&
2482 has_wrprotected_page(vcpu->kvm, gfn, level))
2485 spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE;
2488 * Optimization: for pte sync, if spte was writable the hash
2489 * lookup is unnecessary (and expensive). Write protection
2490 * is responsibility of mmu_get_page / kvm_sync_page.
2491 * Same reasoning can be applied to dirty page accounting.
2493 if (!can_unsync && is_writable_pte(*sptep))
2496 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2497 pgprintk("%s: found shadow page for %llx, marking ro\n",
2500 pte_access &= ~ACC_WRITE_MASK;
2501 spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE);
2505 if (pte_access & ACC_WRITE_MASK)
2506 mark_page_dirty(vcpu->kvm, gfn);
2509 if (mmu_spte_update(sptep, spte))
2510 kvm_flush_remote_tlbs(vcpu->kvm);
2515 static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2516 unsigned pte_access, int write_fault, int *emulate,
2517 int level, gfn_t gfn, pfn_t pfn, bool speculative,
2520 int was_rmapped = 0;
2523 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2524 *sptep, write_fault, gfn);
2526 if (is_rmap_spte(*sptep)) {
2528 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2529 * the parent of the now unreachable PTE.
2531 if (level > PT_PAGE_TABLE_LEVEL &&
2532 !is_large_pte(*sptep)) {
2533 struct kvm_mmu_page *child;
2536 child = page_header(pte & PT64_BASE_ADDR_MASK);
2537 drop_parent_pte(child, sptep);
2538 kvm_flush_remote_tlbs(vcpu->kvm);
2539 } else if (pfn != spte_to_pfn(*sptep)) {
2540 pgprintk("hfn old %llx new %llx\n",
2541 spte_to_pfn(*sptep), pfn);
2542 drop_spte(vcpu->kvm, sptep);
2543 kvm_flush_remote_tlbs(vcpu->kvm);
2548 if (set_spte(vcpu, sptep, pte_access, level, gfn, pfn, speculative,
2549 true, host_writable)) {
2552 kvm_mmu_flush_tlb(vcpu);
2555 if (unlikely(is_mmio_spte(*sptep) && emulate))
2558 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2559 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2560 is_large_pte(*sptep)? "2MB" : "4kB",
2561 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
2563 if (!was_rmapped && is_large_pte(*sptep))
2564 ++vcpu->kvm->stat.lpages;
2566 if (is_shadow_present_pte(*sptep)) {
2568 rmap_count = rmap_add(vcpu, sptep, gfn);
2569 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2570 rmap_recycle(vcpu, sptep, gfn);
2574 kvm_release_pfn_clean(pfn);
2577 static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2580 struct kvm_memory_slot *slot;
2582 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2584 return KVM_PFN_ERR_FAULT;
2586 return gfn_to_pfn_memslot_atomic(slot, gfn);
2589 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2590 struct kvm_mmu_page *sp,
2591 u64 *start, u64 *end)
2593 struct page *pages[PTE_PREFETCH_NUM];
2594 unsigned access = sp->role.access;
2598 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2599 if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK))
2602 ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start);
2606 for (i = 0; i < ret; i++, gfn++, start++)
2607 mmu_set_spte(vcpu, start, access, 0, NULL,
2608 sp->role.level, gfn, page_to_pfn(pages[i]),
2614 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2615 struct kvm_mmu_page *sp, u64 *sptep)
2617 u64 *spte, *start = NULL;
2620 WARN_ON(!sp->role.direct);
2622 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2625 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2626 if (is_shadow_present_pte(*spte) || spte == sptep) {
2629 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2637 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2639 struct kvm_mmu_page *sp;
2642 * Since it's no accessed bit on EPT, it's no way to
2643 * distinguish between actually accessed translations
2644 * and prefetched, so disable pte prefetch if EPT is
2647 if (!shadow_accessed_mask)
2650 sp = page_header(__pa(sptep));
2651 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2654 __direct_pte_prefetch(vcpu, sp, sptep);
2657 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
2658 int map_writable, int level, gfn_t gfn, pfn_t pfn,
2661 struct kvm_shadow_walk_iterator iterator;
2662 struct kvm_mmu_page *sp;
2666 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2669 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2670 if (iterator.level == level) {
2671 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL,
2672 write, &emulate, level, gfn, pfn,
2673 prefault, map_writable);
2674 direct_pte_prefetch(vcpu, iterator.sptep);
2675 ++vcpu->stat.pf_fixed;
2679 drop_large_spte(vcpu, iterator.sptep);
2680 if (!is_shadow_present_pte(*iterator.sptep)) {
2681 u64 base_addr = iterator.addr;
2683 base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2684 pseudo_gfn = base_addr >> PAGE_SHIFT;
2685 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2687 1, ACC_ALL, iterator.sptep);
2689 link_shadow_page(iterator.sptep, sp, true);
2695 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2699 info.si_signo = SIGBUS;
2701 info.si_code = BUS_MCEERR_AR;
2702 info.si_addr = (void __user *)address;
2703 info.si_addr_lsb = PAGE_SHIFT;
2705 send_sig_info(SIGBUS, &info, tsk);
2708 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, pfn_t pfn)
2711 * Do not cache the mmio info caused by writing the readonly gfn
2712 * into the spte otherwise read access on readonly gfn also can
2713 * caused mmio page fault and treat it as mmio access.
2714 * Return 1 to tell kvm to emulate it.
2716 if (pfn == KVM_PFN_ERR_RO_FAULT)
2719 if (pfn == KVM_PFN_ERR_HWPOISON) {
2720 kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current);
2727 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
2728 gfn_t *gfnp, pfn_t *pfnp, int *levelp)
2732 int level = *levelp;
2735 * Check if it's a transparent hugepage. If this would be an
2736 * hugetlbfs page, level wouldn't be set to
2737 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2740 if (!is_error_noslot_pfn(pfn) && !kvm_is_mmio_pfn(pfn) &&
2741 level == PT_PAGE_TABLE_LEVEL &&
2742 PageTransCompound(pfn_to_page(pfn)) &&
2743 !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) {
2746 * mmu_notifier_retry was successful and we hold the
2747 * mmu_lock here, so the pmd can't become splitting
2748 * from under us, and in turn
2749 * __split_huge_page_refcount() can't run from under
2750 * us and we can safely transfer the refcount from
2751 * PG_tail to PG_head as we switch the pfn to tail to
2754 *levelp = level = PT_DIRECTORY_LEVEL;
2755 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2756 VM_BUG_ON((gfn & mask) != (pfn & mask));
2760 kvm_release_pfn_clean(pfn);
2768 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2769 pfn_t pfn, unsigned access, int *ret_val)
2773 /* The pfn is invalid, report the error! */
2774 if (unlikely(is_error_pfn(pfn))) {
2775 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2779 if (unlikely(is_noslot_pfn(pfn)))
2780 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
2787 static bool page_fault_can_be_fast(u32 error_code)
2790 * Do not fix the mmio spte with invalid generation number which
2791 * need to be updated by slow page fault path.
2793 if (unlikely(error_code & PFERR_RSVD_MASK))
2797 * #PF can be fast only if the shadow page table is present and it
2798 * is caused by write-protect, that means we just need change the
2799 * W bit of the spte which can be done out of mmu-lock.
2801 if (!(error_code & PFERR_PRESENT_MASK) ||
2802 !(error_code & PFERR_WRITE_MASK))
2809 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 spte)
2811 struct kvm_mmu_page *sp = page_header(__pa(sptep));
2814 WARN_ON(!sp->role.direct);
2817 * The gfn of direct spte is stable since it is calculated
2820 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
2822 if (cmpxchg64(sptep, spte, spte | PT_WRITABLE_MASK) == spte)
2823 mark_page_dirty(vcpu->kvm, gfn);
2830 * - true: let the vcpu to access on the same address again.
2831 * - false: let the real page fault path to fix it.
2833 static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
2836 struct kvm_shadow_walk_iterator iterator;
2840 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2843 if (!page_fault_can_be_fast(error_code))
2846 walk_shadow_page_lockless_begin(vcpu);
2847 for_each_shadow_entry_lockless(vcpu, gva, iterator, spte)
2848 if (!is_shadow_present_pte(spte) || iterator.level < level)
2852 * If the mapping has been changed, let the vcpu fault on the
2853 * same address again.
2855 if (!is_rmap_spte(spte)) {
2860 if (!is_last_spte(spte, level))
2864 * Check if it is a spurious fault caused by TLB lazily flushed.
2866 * Need not check the access of upper level table entries since
2867 * they are always ACC_ALL.
2869 if (is_writable_pte(spte)) {
2875 * Currently, to simplify the code, only the spte write-protected
2876 * by dirty-log can be fast fixed.
2878 if (!spte_is_locklessly_modifiable(spte))
2882 * Currently, fast page fault only works for direct mapping since
2883 * the gfn is not stable for indirect shadow page.
2884 * See Documentation/virtual/kvm/locking.txt to get more detail.
2886 ret = fast_pf_fix_direct_spte(vcpu, iterator.sptep, spte);
2888 trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep,
2890 walk_shadow_page_lockless_end(vcpu);
2895 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
2896 gva_t gva, pfn_t *pfn, bool write, bool *writable);
2897 static void make_mmu_pages_available(struct kvm_vcpu *vcpu);
2899 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code,
2900 gfn_t gfn, bool prefault)
2906 unsigned long mmu_seq;
2907 bool map_writable, write = error_code & PFERR_WRITE_MASK;
2909 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
2910 if (likely(!force_pt_level)) {
2911 level = mapping_level(vcpu, gfn);
2913 * This path builds a PAE pagetable - so we can map
2914 * 2mb pages at maximum. Therefore check if the level
2915 * is larger than that.
2917 if (level > PT_DIRECTORY_LEVEL)
2918 level = PT_DIRECTORY_LEVEL;
2920 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2922 level = PT_PAGE_TABLE_LEVEL;
2924 if (fast_page_fault(vcpu, v, level, error_code))
2927 mmu_seq = vcpu->kvm->mmu_notifier_seq;
2930 if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
2933 if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
2936 spin_lock(&vcpu->kvm->mmu_lock);
2937 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
2939 make_mmu_pages_available(vcpu);
2940 if (likely(!force_pt_level))
2941 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
2942 r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn,
2944 spin_unlock(&vcpu->kvm->mmu_lock);
2950 spin_unlock(&vcpu->kvm->mmu_lock);
2951 kvm_release_pfn_clean(pfn);
2956 static void mmu_free_roots(struct kvm_vcpu *vcpu)
2959 struct kvm_mmu_page *sp;
2960 LIST_HEAD(invalid_list);
2962 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2965 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
2966 (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
2967 vcpu->arch.mmu.direct_map)) {
2968 hpa_t root = vcpu->arch.mmu.root_hpa;
2970 spin_lock(&vcpu->kvm->mmu_lock);
2971 sp = page_header(root);
2973 if (!sp->root_count && sp->role.invalid) {
2974 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
2975 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2977 spin_unlock(&vcpu->kvm->mmu_lock);
2978 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2982 spin_lock(&vcpu->kvm->mmu_lock);
2983 for (i = 0; i < 4; ++i) {
2984 hpa_t root = vcpu->arch.mmu.pae_root[i];
2987 root &= PT64_BASE_ADDR_MASK;
2988 sp = page_header(root);
2990 if (!sp->root_count && sp->role.invalid)
2991 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2994 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
2996 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2997 spin_unlock(&vcpu->kvm->mmu_lock);
2998 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
3001 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3005 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
3006 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3013 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3015 struct kvm_mmu_page *sp;
3018 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3019 spin_lock(&vcpu->kvm->mmu_lock);
3020 make_mmu_pages_available(vcpu);
3021 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL,
3024 spin_unlock(&vcpu->kvm->mmu_lock);
3025 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
3026 } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
3027 for (i = 0; i < 4; ++i) {
3028 hpa_t root = vcpu->arch.mmu.pae_root[i];
3030 ASSERT(!VALID_PAGE(root));
3031 spin_lock(&vcpu->kvm->mmu_lock);
3032 make_mmu_pages_available(vcpu);
3033 sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
3035 PT32_ROOT_LEVEL, 1, ACC_ALL,
3037 root = __pa(sp->spt);
3039 spin_unlock(&vcpu->kvm->mmu_lock);
3040 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
3042 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3049 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3051 struct kvm_mmu_page *sp;
3056 root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
3058 if (mmu_check_root(vcpu, root_gfn))
3062 * Do we shadow a long mode page table? If so we need to
3063 * write-protect the guests page table root.
3065 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3066 hpa_t root = vcpu->arch.mmu.root_hpa;
3068 ASSERT(!VALID_PAGE(root));
3070 spin_lock(&vcpu->kvm->mmu_lock);
3071 make_mmu_pages_available(vcpu);
3072 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
3074 root = __pa(sp->spt);
3076 spin_unlock(&vcpu->kvm->mmu_lock);
3077 vcpu->arch.mmu.root_hpa = root;
3082 * We shadow a 32 bit page table. This may be a legacy 2-level
3083 * or a PAE 3-level page table. In either case we need to be aware that
3084 * the shadow page table may be a PAE or a long mode page table.
3086 pm_mask = PT_PRESENT_MASK;
3087 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
3088 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3090 for (i = 0; i < 4; ++i) {
3091 hpa_t root = vcpu->arch.mmu.pae_root[i];
3093 ASSERT(!VALID_PAGE(root));
3094 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
3095 pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i);
3096 if (!is_present_gpte(pdptr)) {
3097 vcpu->arch.mmu.pae_root[i] = 0;
3100 root_gfn = pdptr >> PAGE_SHIFT;
3101 if (mmu_check_root(vcpu, root_gfn))
3104 spin_lock(&vcpu->kvm->mmu_lock);
3105 make_mmu_pages_available(vcpu);
3106 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
3109 root = __pa(sp->spt);
3111 spin_unlock(&vcpu->kvm->mmu_lock);
3113 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
3115 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3118 * If we shadow a 32 bit page table with a long mode page
3119 * table we enter this path.
3121 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3122 if (vcpu->arch.mmu.lm_root == NULL) {
3124 * The additional page necessary for this is only
3125 * allocated on demand.
3130 lm_root = (void*)get_zeroed_page(GFP_KERNEL);
3131 if (lm_root == NULL)
3134 lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
3136 vcpu->arch.mmu.lm_root = lm_root;
3139 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
3145 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3147 if (vcpu->arch.mmu.direct_map)
3148 return mmu_alloc_direct_roots(vcpu);
3150 return mmu_alloc_shadow_roots(vcpu);
3153 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
3156 struct kvm_mmu_page *sp;
3158 if (vcpu->arch.mmu.direct_map)
3161 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3164 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3165 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3166 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3167 hpa_t root = vcpu->arch.mmu.root_hpa;
3168 sp = page_header(root);
3169 mmu_sync_children(vcpu, sp);
3170 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3173 for (i = 0; i < 4; ++i) {
3174 hpa_t root = vcpu->arch.mmu.pae_root[i];
3176 if (root && VALID_PAGE(root)) {
3177 root &= PT64_BASE_ADDR_MASK;
3178 sp = page_header(root);
3179 mmu_sync_children(vcpu, sp);
3182 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3185 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3187 spin_lock(&vcpu->kvm->mmu_lock);
3188 mmu_sync_roots(vcpu);
3189 spin_unlock(&vcpu->kvm->mmu_lock);
3191 EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots);
3193 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
3194 u32 access, struct x86_exception *exception)
3197 exception->error_code = 0;
3201 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
3203 struct x86_exception *exception)
3206 exception->error_code = 0;
3207 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access);
3210 static bool quickly_check_mmio_pf(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3213 return vcpu_match_mmio_gpa(vcpu, addr);
3215 return vcpu_match_mmio_gva(vcpu, addr);
3220 * On direct hosts, the last spte is only allows two states
3221 * for mmio page fault:
3222 * - It is the mmio spte
3223 * - It is zapped or it is being zapped.
3225 * This function completely checks the spte when the last spte
3226 * is not the mmio spte.
3228 static bool check_direct_spte_mmio_pf(u64 spte)
3230 return __check_direct_spte_mmio_pf(spte);
3233 static u64 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr)
3235 struct kvm_shadow_walk_iterator iterator;
3238 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3241 walk_shadow_page_lockless_begin(vcpu);
3242 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte)
3243 if (!is_shadow_present_pte(spte))
3245 walk_shadow_page_lockless_end(vcpu);
3250 int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3254 if (quickly_check_mmio_pf(vcpu, addr, direct))
3255 return RET_MMIO_PF_EMULATE;
3257 spte = walk_shadow_page_get_mmio_spte(vcpu, addr);
3259 if (is_mmio_spte(spte)) {
3260 gfn_t gfn = get_mmio_spte_gfn(spte);
3261 unsigned access = get_mmio_spte_access(spte);
3263 if (!check_mmio_spte(vcpu->kvm, spte))
3264 return RET_MMIO_PF_INVALID;
3269 trace_handle_mmio_page_fault(addr, gfn, access);
3270 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3271 return RET_MMIO_PF_EMULATE;
3275 * It's ok if the gva is remapped by other cpus on shadow guest,
3276 * it's a BUG if the gfn is not a mmio page.
3278 if (direct && !check_direct_spte_mmio_pf(spte))
3279 return RET_MMIO_PF_BUG;
3282 * If the page table is zapped by other cpus, let CPU fault again on
3285 return RET_MMIO_PF_RETRY;
3287 EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common);
3289 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr,
3290 u32 error_code, bool direct)
3294 ret = handle_mmio_page_fault_common(vcpu, addr, direct);
3295 WARN_ON(ret == RET_MMIO_PF_BUG);
3299 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3300 u32 error_code, bool prefault)
3305 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
3307 if (unlikely(error_code & PFERR_RSVD_MASK)) {
3308 r = handle_mmio_page_fault(vcpu, gva, error_code, true);
3310 if (likely(r != RET_MMIO_PF_INVALID))
3314 r = mmu_topup_memory_caches(vcpu);
3319 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3321 gfn = gva >> PAGE_SHIFT;
3323 return nonpaging_map(vcpu, gva & PAGE_MASK,
3324 error_code, gfn, prefault);
3327 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
3329 struct kvm_arch_async_pf arch;
3331 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3333 arch.direct_map = vcpu->arch.mmu.direct_map;
3334 arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
3336 return kvm_setup_async_pf(vcpu, gva, gfn, &arch);
3339 static bool can_do_async_pf(struct kvm_vcpu *vcpu)
3341 if (unlikely(!irqchip_in_kernel(vcpu->kvm) ||
3342 kvm_event_needs_reinjection(vcpu)))
3345 return kvm_x86_ops->interrupt_allowed(vcpu);
3348 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3349 gva_t gva, pfn_t *pfn, bool write, bool *writable)
3353 *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable);
3356 return false; /* *pfn has correct page already */
3358 if (!prefault && can_do_async_pf(vcpu)) {
3359 trace_kvm_try_async_get_page(gva, gfn);
3360 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3361 trace_kvm_async_pf_doublefault(gva, gfn);
3362 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3364 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
3368 *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable);
3373 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
3380 gfn_t gfn = gpa >> PAGE_SHIFT;
3381 unsigned long mmu_seq;
3382 int write = error_code & PFERR_WRITE_MASK;
3386 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3388 if (unlikely(error_code & PFERR_RSVD_MASK)) {
3389 r = handle_mmio_page_fault(vcpu, gpa, error_code, true);
3391 if (likely(r != RET_MMIO_PF_INVALID))
3395 r = mmu_topup_memory_caches(vcpu);
3399 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
3400 if (likely(!force_pt_level)) {
3401 level = mapping_level(vcpu, gfn);
3402 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3404 level = PT_PAGE_TABLE_LEVEL;
3406 if (fast_page_fault(vcpu, gpa, level, error_code))
3409 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3412 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3415 if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
3418 spin_lock(&vcpu->kvm->mmu_lock);
3419 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3421 make_mmu_pages_available(vcpu);
3422 if (likely(!force_pt_level))
3423 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3424 r = __direct_map(vcpu, gpa, write, map_writable,
3425 level, gfn, pfn, prefault);
3426 spin_unlock(&vcpu->kvm->mmu_lock);
3431 spin_unlock(&vcpu->kvm->mmu_lock);
3432 kvm_release_pfn_clean(pfn);
3436 static void nonpaging_init_context(struct kvm_vcpu *vcpu,
3437 struct kvm_mmu *context)
3439 context->page_fault = nonpaging_page_fault;
3440 context->gva_to_gpa = nonpaging_gva_to_gpa;
3441 context->sync_page = nonpaging_sync_page;
3442 context->invlpg = nonpaging_invlpg;
3443 context->update_pte = nonpaging_update_pte;
3444 context->root_level = 0;
3445 context->shadow_root_level = PT32E_ROOT_LEVEL;
3446 context->root_hpa = INVALID_PAGE;
3447 context->direct_map = true;
3448 context->nx = false;
3451 void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3453 ++vcpu->stat.tlb_flush;
3454 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
3456 EXPORT_SYMBOL_GPL(kvm_mmu_flush_tlb);
3458 void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu)
3460 mmu_free_roots(vcpu);
3463 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3465 return kvm_read_cr3(vcpu);
3468 static void inject_page_fault(struct kvm_vcpu *vcpu,
3469 struct x86_exception *fault)
3471 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
3474 static bool sync_mmio_spte(struct kvm *kvm, u64 *sptep, gfn_t gfn,
3475 unsigned access, int *nr_present)
3477 if (unlikely(is_mmio_spte(*sptep))) {
3478 if (gfn != get_mmio_spte_gfn(*sptep)) {
3479 mmu_spte_clear_no_track(sptep);
3484 mark_mmio_spte(kvm, sptep, gfn, access);
3491 static inline bool is_last_gpte(struct kvm_mmu *mmu, unsigned level, unsigned gpte)
3496 index |= (gpte & PT_PAGE_SIZE_MASK) >> (PT_PAGE_SIZE_SHIFT - 2);
3497 return mmu->last_pte_bitmap & (1 << index);
3500 #define PTTYPE_EPT 18 /* arbitrary */
3501 #define PTTYPE PTTYPE_EPT
3502 #include "paging_tmpl.h"
3506 #include "paging_tmpl.h"
3510 #include "paging_tmpl.h"
3513 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3514 struct kvm_mmu *context)
3516 int maxphyaddr = cpuid_maxphyaddr(vcpu);
3517 u64 exb_bit_rsvd = 0;
3519 context->bad_mt_xwr = 0;
3522 exb_bit_rsvd = rsvd_bits(63, 63);
3523 switch (context->root_level) {
3524 case PT32_ROOT_LEVEL:
3525 /* no rsvd bits for 2 level 4K page table entries */
3526 context->rsvd_bits_mask[0][1] = 0;
3527 context->rsvd_bits_mask[0][0] = 0;
3528 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3530 if (!is_pse(vcpu)) {
3531 context->rsvd_bits_mask[1][1] = 0;
3535 if (is_cpuid_PSE36())
3536 /* 36bits PSE 4MB page */
3537 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
3539 /* 32 bits PSE 4MB page */
3540 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
3542 case PT32E_ROOT_LEVEL:
3543 context->rsvd_bits_mask[0][2] =
3544 rsvd_bits(maxphyaddr, 63) |
3545 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
3546 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3547 rsvd_bits(maxphyaddr, 62); /* PDE */
3548 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3549 rsvd_bits(maxphyaddr, 62); /* PTE */
3550 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3551 rsvd_bits(maxphyaddr, 62) |
3552 rsvd_bits(13, 20); /* large page */
3553 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3555 case PT64_ROOT_LEVEL:
3556 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
3557 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3558 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
3559 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3560 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3561 rsvd_bits(maxphyaddr, 51);
3562 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3563 rsvd_bits(maxphyaddr, 51);
3564 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
3565 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
3566 rsvd_bits(maxphyaddr, 51) |
3568 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3569 rsvd_bits(maxphyaddr, 51) |
3570 rsvd_bits(13, 20); /* large page */
3571 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3576 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
3577 struct kvm_mmu *context, bool execonly)
3579 int maxphyaddr = cpuid_maxphyaddr(vcpu);
3582 context->rsvd_bits_mask[0][3] =
3583 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
3584 context->rsvd_bits_mask[0][2] =
3585 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
3586 context->rsvd_bits_mask[0][1] =
3587 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
3588 context->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51);
3591 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
3592 context->rsvd_bits_mask[1][2] =
3593 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29);
3594 context->rsvd_bits_mask[1][1] =
3595 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20);
3596 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3598 for (pte = 0; pte < 64; pte++) {
3599 int rwx_bits = pte & 7;
3601 if (mt == 0x2 || mt == 0x3 || mt == 0x7 ||
3602 rwx_bits == 0x2 || rwx_bits == 0x6 ||
3603 (rwx_bits == 0x4 && !execonly))
3604 context->bad_mt_xwr |= (1ull << pte);
3608 static void update_permission_bitmask(struct kvm_vcpu *vcpu,
3609 struct kvm_mmu *mmu, bool ept)
3611 unsigned bit, byte, pfec;
3613 bool fault, x, w, u, wf, uf, ff, smep;
3615 smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3616 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
3619 wf = pfec & PFERR_WRITE_MASK;
3620 uf = pfec & PFERR_USER_MASK;
3621 ff = pfec & PFERR_FETCH_MASK;
3622 for (bit = 0; bit < 8; ++bit) {
3623 x = bit & ACC_EXEC_MASK;
3624 w = bit & ACC_WRITE_MASK;
3625 u = bit & ACC_USER_MASK;
3628 /* Not really needed: !nx will cause pte.nx to fault */
3630 /* Allow supervisor writes if !cr0.wp */
3631 w |= !is_write_protection(vcpu) && !uf;
3632 /* Disallow supervisor fetches of user code if cr4.smep */
3633 x &= !(smep && u && !uf);
3635 /* Not really needed: no U/S accesses on ept */
3638 fault = (ff && !x) || (uf && !u) || (wf && !w);
3639 map |= fault << bit;
3641 mmu->permissions[byte] = map;
3645 static void update_last_pte_bitmap(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
3648 unsigned level, root_level = mmu->root_level;
3649 const unsigned ps_set_index = 1 << 2; /* bit 2 of index: ps */
3651 if (root_level == PT32E_ROOT_LEVEL)
3653 /* PT_PAGE_TABLE_LEVEL always terminates */
3654 map = 1 | (1 << ps_set_index);
3655 for (level = PT_DIRECTORY_LEVEL; level <= root_level; ++level) {
3656 if (level <= PT_PDPE_LEVEL
3657 && (mmu->root_level >= PT32E_ROOT_LEVEL || is_pse(vcpu)))
3658 map |= 1 << (ps_set_index | (level - 1));
3660 mmu->last_pte_bitmap = map;
3663 static void paging64_init_context_common(struct kvm_vcpu *vcpu,
3664 struct kvm_mmu *context,
3667 context->nx = is_nx(vcpu);
3668 context->root_level = level;
3670 reset_rsvds_bits_mask(vcpu, context);
3671 update_permission_bitmask(vcpu, context, false);
3672 update_last_pte_bitmap(vcpu, context);
3674 ASSERT(is_pae(vcpu));
3675 context->page_fault = paging64_page_fault;
3676 context->gva_to_gpa = paging64_gva_to_gpa;
3677 context->sync_page = paging64_sync_page;
3678 context->invlpg = paging64_invlpg;
3679 context->update_pte = paging64_update_pte;
3680 context->shadow_root_level = level;
3681 context->root_hpa = INVALID_PAGE;
3682 context->direct_map = false;
3685 static void paging64_init_context(struct kvm_vcpu *vcpu,
3686 struct kvm_mmu *context)
3688 paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
3691 static void paging32_init_context(struct kvm_vcpu *vcpu,
3692 struct kvm_mmu *context)
3694 context->nx = false;
3695 context->root_level = PT32_ROOT_LEVEL;
3697 reset_rsvds_bits_mask(vcpu, context);
3698 update_permission_bitmask(vcpu, context, false);
3699 update_last_pte_bitmap(vcpu, context);
3701 context->page_fault = paging32_page_fault;
3702 context->gva_to_gpa = paging32_gva_to_gpa;
3703 context->sync_page = paging32_sync_page;
3704 context->invlpg = paging32_invlpg;
3705 context->update_pte = paging32_update_pte;
3706 context->shadow_root_level = PT32E_ROOT_LEVEL;
3707 context->root_hpa = INVALID_PAGE;
3708 context->direct_map = false;
3711 static void paging32E_init_context(struct kvm_vcpu *vcpu,
3712 struct kvm_mmu *context)
3714 paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
3717 static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
3719 struct kvm_mmu *context = vcpu->arch.walk_mmu;
3721 context->base_role.word = 0;
3722 context->page_fault = tdp_page_fault;
3723 context->sync_page = nonpaging_sync_page;
3724 context->invlpg = nonpaging_invlpg;
3725 context->update_pte = nonpaging_update_pte;
3726 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
3727 context->root_hpa = INVALID_PAGE;
3728 context->direct_map = true;
3729 context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
3730 context->get_cr3 = get_cr3;
3731 context->get_pdptr = kvm_pdptr_read;
3732 context->inject_page_fault = kvm_inject_page_fault;
3734 if (!is_paging(vcpu)) {
3735 context->nx = false;
3736 context->gva_to_gpa = nonpaging_gva_to_gpa;
3737 context->root_level = 0;
3738 } else if (is_long_mode(vcpu)) {
3739 context->nx = is_nx(vcpu);
3740 context->root_level = PT64_ROOT_LEVEL;
3741 reset_rsvds_bits_mask(vcpu, context);
3742 context->gva_to_gpa = paging64_gva_to_gpa;
3743 } else if (is_pae(vcpu)) {
3744 context->nx = is_nx(vcpu);
3745 context->root_level = PT32E_ROOT_LEVEL;
3746 reset_rsvds_bits_mask(vcpu, context);
3747 context->gva_to_gpa = paging64_gva_to_gpa;
3749 context->nx = false;
3750 context->root_level = PT32_ROOT_LEVEL;
3751 reset_rsvds_bits_mask(vcpu, context);
3752 context->gva_to_gpa = paging32_gva_to_gpa;
3755 update_permission_bitmask(vcpu, context, false);
3756 update_last_pte_bitmap(vcpu, context);
3759 void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
3761 bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3763 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3765 if (!is_paging(vcpu))
3766 nonpaging_init_context(vcpu, context);
3767 else if (is_long_mode(vcpu))
3768 paging64_init_context(vcpu, context);
3769 else if (is_pae(vcpu))
3770 paging32E_init_context(vcpu, context);
3772 paging32_init_context(vcpu, context);
3774 vcpu->arch.mmu.base_role.nxe = is_nx(vcpu);
3775 vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu);
3776 vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu);
3777 vcpu->arch.mmu.base_role.smep_andnot_wp
3778 = smep && !is_write_protection(vcpu);
3780 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
3782 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context,
3786 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3788 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
3791 context->page_fault = ept_page_fault;
3792 context->gva_to_gpa = ept_gva_to_gpa;
3793 context->sync_page = ept_sync_page;
3794 context->invlpg = ept_invlpg;
3795 context->update_pte = ept_update_pte;
3796 context->root_level = context->shadow_root_level;
3797 context->root_hpa = INVALID_PAGE;
3798 context->direct_map = false;
3800 update_permission_bitmask(vcpu, context, true);
3801 reset_rsvds_bits_mask_ept(vcpu, context, execonly);
3803 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
3805 static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
3807 kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu);
3808 vcpu->arch.walk_mmu->set_cr3 = kvm_x86_ops->set_cr3;
3809 vcpu->arch.walk_mmu->get_cr3 = get_cr3;
3810 vcpu->arch.walk_mmu->get_pdptr = kvm_pdptr_read;
3811 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
3814 static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
3816 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
3818 g_context->get_cr3 = get_cr3;
3819 g_context->get_pdptr = kvm_pdptr_read;
3820 g_context->inject_page_fault = kvm_inject_page_fault;
3823 * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The
3824 * translation of l2_gpa to l1_gpa addresses is done using the
3825 * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa
3826 * functions between mmu and nested_mmu are swapped.
3828 if (!is_paging(vcpu)) {
3829 g_context->nx = false;
3830 g_context->root_level = 0;
3831 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
3832 } else if (is_long_mode(vcpu)) {
3833 g_context->nx = is_nx(vcpu);
3834 g_context->root_level = PT64_ROOT_LEVEL;
3835 reset_rsvds_bits_mask(vcpu, g_context);
3836 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3837 } else if (is_pae(vcpu)) {
3838 g_context->nx = is_nx(vcpu);
3839 g_context->root_level = PT32E_ROOT_LEVEL;
3840 reset_rsvds_bits_mask(vcpu, g_context);
3841 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3843 g_context->nx = false;
3844 g_context->root_level = PT32_ROOT_LEVEL;
3845 reset_rsvds_bits_mask(vcpu, g_context);
3846 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
3849 update_permission_bitmask(vcpu, g_context, false);
3850 update_last_pte_bitmap(vcpu, g_context);
3853 static void init_kvm_mmu(struct kvm_vcpu *vcpu)
3855 if (mmu_is_nested(vcpu))
3856 return init_kvm_nested_mmu(vcpu);
3857 else if (tdp_enabled)
3858 return init_kvm_tdp_mmu(vcpu);
3860 return init_kvm_softmmu(vcpu);
3863 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
3867 kvm_mmu_unload(vcpu);
3870 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
3872 int kvm_mmu_load(struct kvm_vcpu *vcpu)
3876 r = mmu_topup_memory_caches(vcpu);
3879 r = mmu_alloc_roots(vcpu);
3880 kvm_mmu_sync_roots(vcpu);
3883 /* set_cr3() should ensure TLB has been flushed */
3884 vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
3888 EXPORT_SYMBOL_GPL(kvm_mmu_load);
3890 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
3892 mmu_free_roots(vcpu);
3893 WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3895 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
3897 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
3898 struct kvm_mmu_page *sp, u64 *spte,
3901 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
3902 ++vcpu->kvm->stat.mmu_pde_zapped;
3906 ++vcpu->kvm->stat.mmu_pte_updated;
3907 vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
3910 static bool need_remote_flush(u64 old, u64 new)
3912 if (!is_shadow_present_pte(old))
3914 if (!is_shadow_present_pte(new))
3916 if ((old ^ new) & PT64_BASE_ADDR_MASK)
3918 old ^= shadow_nx_mask;
3919 new ^= shadow_nx_mask;
3920 return (old & ~new & PT64_PERM_MASK) != 0;
3923 static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page,
3924 bool remote_flush, bool local_flush)
3930 kvm_flush_remote_tlbs(vcpu->kvm);
3931 else if (local_flush)
3932 kvm_mmu_flush_tlb(vcpu);
3935 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
3936 const u8 *new, int *bytes)
3942 * Assume that the pte write on a page table of the same type
3943 * as the current vcpu paging mode since we update the sptes only
3944 * when they have the same mode.
3946 if (is_pae(vcpu) && *bytes == 4) {
3947 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
3950 r = kvm_read_guest(vcpu->kvm, *gpa, &gentry, 8);
3953 new = (const u8 *)&gentry;
3958 gentry = *(const u32 *)new;
3961 gentry = *(const u64 *)new;
3972 * If we're seeing too many writes to a page, it may no longer be a page table,
3973 * or we may be forking, in which case it is better to unmap the page.
3975 static bool detect_write_flooding(struct kvm_mmu_page *sp)
3978 * Skip write-flooding detected for the sp whose level is 1, because
3979 * it can become unsync, then the guest page is not write-protected.
3981 if (sp->role.level == PT_PAGE_TABLE_LEVEL)
3984 return ++sp->write_flooding_count >= 3;
3988 * Misaligned accesses are too much trouble to fix up; also, they usually
3989 * indicate a page is not used as a page table.
3991 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
3994 unsigned offset, pte_size, misaligned;
3996 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
3997 gpa, bytes, sp->role.word);
3999 offset = offset_in_page(gpa);
4000 pte_size = sp->role.cr4_pae ? 8 : 4;
4003 * Sometimes, the OS only writes the last one bytes to update status
4004 * bits, for example, in linux, andb instruction is used in clear_bit().
4006 if (!(offset & (pte_size - 1)) && bytes == 1)
4009 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
4010 misaligned |= bytes < 4;
4015 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
4017 unsigned page_offset, quadrant;
4021 page_offset = offset_in_page(gpa);
4022 level = sp->role.level;
4024 if (!sp->role.cr4_pae) {
4025 page_offset <<= 1; /* 32->64 */
4027 * A 32-bit pde maps 4MB while the shadow pdes map
4028 * only 2MB. So we need to double the offset again
4029 * and zap two pdes instead of one.
4031 if (level == PT32_ROOT_LEVEL) {
4032 page_offset &= ~7; /* kill rounding error */
4036 quadrant = page_offset >> PAGE_SHIFT;
4037 page_offset &= ~PAGE_MASK;
4038 if (quadrant != sp->role.quadrant)
4042 spte = &sp->spt[page_offset / sizeof(*spte)];
4046 void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
4047 const u8 *new, int bytes)
4049 gfn_t gfn = gpa >> PAGE_SHIFT;
4050 union kvm_mmu_page_role mask = { .word = 0 };
4051 struct kvm_mmu_page *sp;
4052 LIST_HEAD(invalid_list);
4053 u64 entry, gentry, *spte;
4055 bool remote_flush, local_flush, zap_page;
4058 * If we don't have indirect shadow pages, it means no page is
4059 * write-protected, so we can exit simply.
4061 if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
4064 zap_page = remote_flush = local_flush = false;
4066 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
4068 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes);
4071 * No need to care whether allocation memory is successful
4072 * or not since pte prefetch is skiped if it does not have
4073 * enough objects in the cache.
4075 mmu_topup_memory_caches(vcpu);
4077 spin_lock(&vcpu->kvm->mmu_lock);
4078 ++vcpu->kvm->stat.mmu_pte_write;
4079 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
4081 mask.cr0_wp = mask.cr4_pae = mask.nxe = 1;
4082 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
4083 if (detect_write_misaligned(sp, gpa, bytes) ||
4084 detect_write_flooding(sp)) {
4085 zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
4087 ++vcpu->kvm->stat.mmu_flooded;
4091 spte = get_written_sptes(sp, gpa, &npte);
4098 mmu_page_zap_pte(vcpu->kvm, sp, spte);
4100 !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
4101 & mask.word) && rmap_can_add(vcpu))
4102 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
4103 if (need_remote_flush(entry, *spte))
4104 remote_flush = true;
4108 mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush);
4109 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
4110 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
4111 spin_unlock(&vcpu->kvm->mmu_lock);
4114 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
4119 if (vcpu->arch.mmu.direct_map)
4122 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
4124 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4128 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
4130 static void make_mmu_pages_available(struct kvm_vcpu *vcpu)
4132 LIST_HEAD(invalid_list);
4134 if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES))
4137 while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) {
4138 if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list))
4141 ++vcpu->kvm->stat.mmu_recycled;
4143 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
4146 static bool is_mmio_page_fault(struct kvm_vcpu *vcpu, gva_t addr)
4148 if (vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu))
4149 return vcpu_match_mmio_gpa(vcpu, addr);
4151 return vcpu_match_mmio_gva(vcpu, addr);
4154 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code,
4155 void *insn, int insn_len)
4157 int r, emulation_type = EMULTYPE_RETRY;
4158 enum emulation_result er;
4160 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false);
4169 if (is_mmio_page_fault(vcpu, cr2))
4172 er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len);
4177 case EMULATE_USER_EXIT:
4178 ++vcpu->stat.mmio_exits;
4188 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
4190 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
4192 vcpu->arch.mmu.invlpg(vcpu, gva);
4193 kvm_mmu_flush_tlb(vcpu);
4194 ++vcpu->stat.invlpg;
4196 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
4198 void kvm_enable_tdp(void)
4202 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
4204 void kvm_disable_tdp(void)
4206 tdp_enabled = false;
4208 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
4210 static void free_mmu_pages(struct kvm_vcpu *vcpu)
4212 free_page((unsigned long)vcpu->arch.mmu.pae_root);
4213 if (vcpu->arch.mmu.lm_root != NULL)
4214 free_page((unsigned long)vcpu->arch.mmu.lm_root);
4217 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
4225 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
4226 * Therefore we need to allocate shadow page tables in the first
4227 * 4GB of memory, which happens to fit the DMA32 zone.
4229 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
4233 vcpu->arch.mmu.pae_root = page_address(page);
4234 for (i = 0; i < 4; ++i)
4235 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
4240 int kvm_mmu_create(struct kvm_vcpu *vcpu)
4244 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
4245 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
4246 vcpu->arch.mmu.translate_gpa = translate_gpa;
4247 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
4249 return alloc_mmu_pages(vcpu);
4252 void kvm_mmu_setup(struct kvm_vcpu *vcpu)
4255 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
4260 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
4262 struct kvm_memory_slot *memslot;
4266 memslot = id_to_memslot(kvm->memslots, slot);
4267 last_gfn = memslot->base_gfn + memslot->npages - 1;
4269 spin_lock(&kvm->mmu_lock);
4271 for (i = PT_PAGE_TABLE_LEVEL;
4272 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
4273 unsigned long *rmapp;
4274 unsigned long last_index, index;
4276 rmapp = memslot->arch.rmap[i - PT_PAGE_TABLE_LEVEL];
4277 last_index = gfn_to_index(last_gfn, memslot->base_gfn, i);
4279 for (index = 0; index <= last_index; ++index, ++rmapp) {
4281 __rmap_write_protect(kvm, rmapp, false);
4283 if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
4284 kvm_flush_remote_tlbs(kvm);
4285 cond_resched_lock(&kvm->mmu_lock);
4290 kvm_flush_remote_tlbs(kvm);
4291 spin_unlock(&kvm->mmu_lock);
4294 #define BATCH_ZAP_PAGES 10
4295 static void kvm_zap_obsolete_pages(struct kvm *kvm)
4297 struct kvm_mmu_page *sp, *node;
4301 list_for_each_entry_safe_reverse(sp, node,
4302 &kvm->arch.active_mmu_pages, link) {
4306 * No obsolete page exists before new created page since
4307 * active_mmu_pages is the FIFO list.
4309 if (!is_obsolete_sp(kvm, sp))
4313 * Since we are reversely walking the list and the invalid
4314 * list will be moved to the head, skip the invalid page
4315 * can help us to avoid the infinity list walking.
4317 if (sp->role.invalid)
4321 * Need not flush tlb since we only zap the sp with invalid
4322 * generation number.
4324 if (batch >= BATCH_ZAP_PAGES &&
4325 cond_resched_lock(&kvm->mmu_lock)) {
4330 ret = kvm_mmu_prepare_zap_page(kvm, sp,
4331 &kvm->arch.zapped_obsolete_pages);
4339 * Should flush tlb before free page tables since lockless-walking
4340 * may use the pages.
4342 kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
4346 * Fast invalidate all shadow pages and use lock-break technique
4347 * to zap obsolete pages.
4349 * It's required when memslot is being deleted or VM is being
4350 * destroyed, in these cases, we should ensure that KVM MMU does
4351 * not use any resource of the being-deleted slot or all slots
4352 * after calling the function.
4354 void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm)
4356 spin_lock(&kvm->mmu_lock);
4357 trace_kvm_mmu_invalidate_zap_all_pages(kvm);
4358 kvm->arch.mmu_valid_gen++;
4361 * Notify all vcpus to reload its shadow page table
4362 * and flush TLB. Then all vcpus will switch to new
4363 * shadow page table with the new mmu_valid_gen.
4365 * Note: we should do this under the protection of
4366 * mmu-lock, otherwise, vcpu would purge shadow page
4367 * but miss tlb flush.
4369 kvm_reload_remote_mmus(kvm);
4371 kvm_zap_obsolete_pages(kvm);
4372 spin_unlock(&kvm->mmu_lock);
4375 static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
4377 return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
4380 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm)
4383 * The very rare case: if the generation-number is round,
4384 * zap all shadow pages.
4386 if (unlikely(kvm_current_mmio_generation(kvm) == 0)) {
4387 printk_ratelimited(KERN_INFO "kvm: zapping shadow pages for mmio generation wraparound\n");
4388 kvm_mmu_invalidate_zap_all_pages(kvm);
4392 static unsigned long
4393 mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
4396 int nr_to_scan = sc->nr_to_scan;
4397 unsigned long freed = 0;
4399 spin_lock(&kvm_lock);
4401 list_for_each_entry(kvm, &vm_list, vm_list) {
4403 LIST_HEAD(invalid_list);
4406 * Never scan more than sc->nr_to_scan VM instances.
4407 * Will not hit this condition practically since we do not try
4408 * to shrink more than one VM and it is very unlikely to see
4409 * !n_used_mmu_pages so many times.
4414 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
4415 * here. We may skip a VM instance errorneosly, but we do not
4416 * want to shrink a VM that only started to populate its MMU
4419 if (!kvm->arch.n_used_mmu_pages &&
4420 !kvm_has_zapped_obsolete_pages(kvm))
4423 idx = srcu_read_lock(&kvm->srcu);
4424 spin_lock(&kvm->mmu_lock);
4426 if (kvm_has_zapped_obsolete_pages(kvm)) {
4427 kvm_mmu_commit_zap_page(kvm,
4428 &kvm->arch.zapped_obsolete_pages);
4432 if (prepare_zap_oldest_mmu_page(kvm, &invalid_list))
4434 kvm_mmu_commit_zap_page(kvm, &invalid_list);
4437 spin_unlock(&kvm->mmu_lock);
4438 srcu_read_unlock(&kvm->srcu, idx);
4441 * unfair on small ones
4442 * per-vm shrinkers cry out
4443 * sadness comes quickly
4445 list_move_tail(&kvm->vm_list, &vm_list);
4449 spin_unlock(&kvm_lock);
4453 static unsigned long
4454 mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
4456 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
4459 static struct shrinker mmu_shrinker = {
4460 .count_objects = mmu_shrink_count,
4461 .scan_objects = mmu_shrink_scan,
4462 .seeks = DEFAULT_SEEKS * 10,
4465 static void mmu_destroy_caches(void)
4467 if (pte_list_desc_cache)
4468 kmem_cache_destroy(pte_list_desc_cache);
4469 if (mmu_page_header_cache)
4470 kmem_cache_destroy(mmu_page_header_cache);
4473 int kvm_mmu_module_init(void)
4475 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
4476 sizeof(struct pte_list_desc),
4478 if (!pte_list_desc_cache)
4481 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
4482 sizeof(struct kvm_mmu_page),
4484 if (!mmu_page_header_cache)
4487 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0))
4490 register_shrinker(&mmu_shrinker);
4495 mmu_destroy_caches();
4500 * Caculate mmu pages needed for kvm.
4502 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
4504 unsigned int nr_mmu_pages;
4505 unsigned int nr_pages = 0;
4506 struct kvm_memslots *slots;
4507 struct kvm_memory_slot *memslot;
4509 slots = kvm_memslots(kvm);
4511 kvm_for_each_memslot(memslot, slots)
4512 nr_pages += memslot->npages;
4514 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
4515 nr_mmu_pages = max(nr_mmu_pages,
4516 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
4518 return nr_mmu_pages;
4521 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
4523 struct kvm_shadow_walk_iterator iterator;
4527 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4530 walk_shadow_page_lockless_begin(vcpu);
4531 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
4532 sptes[iterator.level-1] = spte;
4534 if (!is_shadow_present_pte(spte))
4537 walk_shadow_page_lockless_end(vcpu);
4541 EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
4543 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
4547 kvm_mmu_unload(vcpu);
4548 free_mmu_pages(vcpu);
4549 mmu_free_memory_caches(vcpu);
4552 void kvm_mmu_module_exit(void)
4554 mmu_destroy_caches();
4555 percpu_counter_destroy(&kvm_total_used_mmu_pages);
4556 unregister_shrinker(&mmu_shrinker);
4557 mmu_audit_disable();