2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
26 #include <linux/kvm_host.h>
27 #include <linux/types.h>
28 #include <linux/string.h>
30 #include <linux/highmem.h>
31 #include <linux/module.h>
32 #include <linux/swap.h>
33 #include <linux/hugetlb.h>
34 #include <linux/compiler.h>
35 #include <linux/srcu.h>
36 #include <linux/slab.h>
37 #include <linux/uaccess.h>
40 #include <asm/cmpxchg.h>
45 * When setting this variable to true it enables Two-Dimensional-Paging
46 * where the hardware walks 2 page tables:
47 * 1. the guest-virtual to guest-physical
48 * 2. while doing 1. it walks guest-physical to host-physical
49 * If the hardware supports that we don't need to do shadow paging.
51 bool tdp_enabled = false;
55 AUDIT_POST_PAGE_FAULT,
66 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
67 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
71 #define pgprintk(x...) do { } while (0)
72 #define rmap_printk(x...) do { } while (0)
78 module_param(dbg, bool, 0644);
82 #define ASSERT(x) do { } while (0)
86 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
87 __FILE__, __LINE__, #x); \
91 #define PTE_PREFETCH_NUM 8
93 #define PT_FIRST_AVAIL_BITS_SHIFT 10
94 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
96 #define PT64_LEVEL_BITS 9
98 #define PT64_LEVEL_SHIFT(level) \
99 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
101 #define PT64_INDEX(address, level)\
102 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
105 #define PT32_LEVEL_BITS 10
107 #define PT32_LEVEL_SHIFT(level) \
108 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
110 #define PT32_LVL_OFFSET_MASK(level) \
111 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
112 * PT32_LEVEL_BITS))) - 1))
114 #define PT32_INDEX(address, level)\
115 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
118 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
119 #define PT64_DIR_BASE_ADDR_MASK \
120 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
121 #define PT64_LVL_ADDR_MASK(level) \
122 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
123 * PT64_LEVEL_BITS))) - 1))
124 #define PT64_LVL_OFFSET_MASK(level) \
125 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
126 * PT64_LEVEL_BITS))) - 1))
128 #define PT32_BASE_ADDR_MASK PAGE_MASK
129 #define PT32_DIR_BASE_ADDR_MASK \
130 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
131 #define PT32_LVL_ADDR_MASK(level) \
132 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
133 * PT32_LEVEL_BITS))) - 1))
135 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
138 #define ACC_EXEC_MASK 1
139 #define ACC_WRITE_MASK PT_WRITABLE_MASK
140 #define ACC_USER_MASK PT_USER_MASK
141 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
143 #include <trace/events/kvm.h>
145 #define CREATE_TRACE_POINTS
146 #include "mmutrace.h"
148 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
149 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
151 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
153 /* make pte_list_desc fit well in cache line */
154 #define PTE_LIST_EXT 3
156 struct pte_list_desc {
157 u64 *sptes[PTE_LIST_EXT];
158 struct pte_list_desc *more;
161 struct kvm_shadow_walk_iterator {
169 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
170 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
171 shadow_walk_okay(&(_walker)); \
172 shadow_walk_next(&(_walker)))
174 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
175 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
176 shadow_walk_okay(&(_walker)) && \
177 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
178 __shadow_walk_next(&(_walker), spte))
180 static struct kmem_cache *pte_list_desc_cache;
181 static struct kmem_cache *mmu_page_header_cache;
182 static struct percpu_counter kvm_total_used_mmu_pages;
184 static u64 __read_mostly shadow_nx_mask;
185 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
186 static u64 __read_mostly shadow_user_mask;
187 static u64 __read_mostly shadow_accessed_mask;
188 static u64 __read_mostly shadow_dirty_mask;
189 static u64 __read_mostly shadow_mmio_mask;
191 static void mmu_spte_set(u64 *sptep, u64 spte);
192 static void mmu_free_roots(struct kvm_vcpu *vcpu);
194 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask)
196 shadow_mmio_mask = mmio_mask;
198 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
200 static void mark_mmio_spte(u64 *sptep, u64 gfn, unsigned access)
202 access &= ACC_WRITE_MASK | ACC_USER_MASK;
204 trace_mark_mmio_spte(sptep, gfn, access);
205 mmu_spte_set(sptep, shadow_mmio_mask | access | gfn << PAGE_SHIFT);
208 static bool is_mmio_spte(u64 spte)
210 return (spte & shadow_mmio_mask) == shadow_mmio_mask;
213 static gfn_t get_mmio_spte_gfn(u64 spte)
215 return (spte & ~shadow_mmio_mask) >> PAGE_SHIFT;
218 static unsigned get_mmio_spte_access(u64 spte)
220 return (spte & ~shadow_mmio_mask) & ~PAGE_MASK;
223 static bool set_mmio_spte(u64 *sptep, gfn_t gfn, pfn_t pfn, unsigned access)
225 if (unlikely(is_noslot_pfn(pfn))) {
226 mark_mmio_spte(sptep, gfn, access);
233 static inline u64 rsvd_bits(int s, int e)
235 return ((1ULL << (e - s + 1)) - 1) << s;
238 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
239 u64 dirty_mask, u64 nx_mask, u64 x_mask)
241 shadow_user_mask = user_mask;
242 shadow_accessed_mask = accessed_mask;
243 shadow_dirty_mask = dirty_mask;
244 shadow_nx_mask = nx_mask;
245 shadow_x_mask = x_mask;
247 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
249 static int is_cpuid_PSE36(void)
254 static int is_nx(struct kvm_vcpu *vcpu)
256 return vcpu->arch.efer & EFER_NX;
259 static int is_shadow_present_pte(u64 pte)
261 return pte & PT_PRESENT_MASK && !is_mmio_spte(pte);
264 static int is_large_pte(u64 pte)
266 return pte & PT_PAGE_SIZE_MASK;
269 static int is_dirty_gpte(unsigned long pte)
271 return pte & PT_DIRTY_MASK;
274 static int is_rmap_spte(u64 pte)
276 return is_shadow_present_pte(pte);
279 static int is_last_spte(u64 pte, int level)
281 if (level == PT_PAGE_TABLE_LEVEL)
283 if (is_large_pte(pte))
288 static pfn_t spte_to_pfn(u64 pte)
290 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
293 static gfn_t pse36_gfn_delta(u32 gpte)
295 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
297 return (gpte & PT32_DIR_PSE36_MASK) << shift;
301 static void __set_spte(u64 *sptep, u64 spte)
306 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
311 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
313 return xchg(sptep, spte);
316 static u64 __get_spte_lockless(u64 *sptep)
318 return ACCESS_ONCE(*sptep);
321 static bool __check_direct_spte_mmio_pf(u64 spte)
323 /* It is valid if the spte is zapped. */
335 static void count_spte_clear(u64 *sptep, u64 spte)
337 struct kvm_mmu_page *sp = page_header(__pa(sptep));
339 if (is_shadow_present_pte(spte))
342 /* Ensure the spte is completely set before we increase the count */
344 sp->clear_spte_count++;
347 static void __set_spte(u64 *sptep, u64 spte)
349 union split_spte *ssptep, sspte;
351 ssptep = (union split_spte *)sptep;
352 sspte = (union split_spte)spte;
354 ssptep->spte_high = sspte.spte_high;
357 * If we map the spte from nonpresent to present, We should store
358 * the high bits firstly, then set present bit, so cpu can not
359 * fetch this spte while we are setting the spte.
363 ssptep->spte_low = sspte.spte_low;
366 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
368 union split_spte *ssptep, sspte;
370 ssptep = (union split_spte *)sptep;
371 sspte = (union split_spte)spte;
373 ssptep->spte_low = sspte.spte_low;
376 * If we map the spte from present to nonpresent, we should clear
377 * present bit firstly to avoid vcpu fetch the old high bits.
381 ssptep->spte_high = sspte.spte_high;
382 count_spte_clear(sptep, spte);
385 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
387 union split_spte *ssptep, sspte, orig;
389 ssptep = (union split_spte *)sptep;
390 sspte = (union split_spte)spte;
392 /* xchg acts as a barrier before the setting of the high bits */
393 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
394 orig.spte_high = ssptep->spte_high;
395 ssptep->spte_high = sspte.spte_high;
396 count_spte_clear(sptep, spte);
402 * The idea using the light way get the spte on x86_32 guest is from
403 * gup_get_pte(arch/x86/mm/gup.c).
404 * The difference is we can not catch the spte tlb flush if we leave
405 * guest mode, so we emulate it by increase clear_spte_count when spte
408 static u64 __get_spte_lockless(u64 *sptep)
410 struct kvm_mmu_page *sp = page_header(__pa(sptep));
411 union split_spte spte, *orig = (union split_spte *)sptep;
415 count = sp->clear_spte_count;
418 spte.spte_low = orig->spte_low;
421 spte.spte_high = orig->spte_high;
424 if (unlikely(spte.spte_low != orig->spte_low ||
425 count != sp->clear_spte_count))
431 static bool __check_direct_spte_mmio_pf(u64 spte)
433 union split_spte sspte = (union split_spte)spte;
434 u32 high_mmio_mask = shadow_mmio_mask >> 32;
436 /* It is valid if the spte is zapped. */
440 /* It is valid if the spte is being zapped. */
441 if (sspte.spte_low == 0ull &&
442 (sspte.spte_high & high_mmio_mask) == high_mmio_mask)
449 static bool spte_is_locklessly_modifiable(u64 spte)
451 return !(~spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE));
454 static bool spte_has_volatile_bits(u64 spte)
457 * Always atomicly update spte if it can be updated
458 * out of mmu-lock, it can ensure dirty bit is not lost,
459 * also, it can help us to get a stable is_writable_pte()
460 * to ensure tlb flush is not missed.
462 if (spte_is_locklessly_modifiable(spte))
465 if (!shadow_accessed_mask)
468 if (!is_shadow_present_pte(spte))
471 if ((spte & shadow_accessed_mask) &&
472 (!is_writable_pte(spte) || (spte & shadow_dirty_mask)))
478 static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask)
480 return (old_spte & bit_mask) && !(new_spte & bit_mask);
483 /* Rules for using mmu_spte_set:
484 * Set the sptep from nonpresent to present.
485 * Note: the sptep being assigned *must* be either not present
486 * or in a state where the hardware will not attempt to update
489 static void mmu_spte_set(u64 *sptep, u64 new_spte)
491 WARN_ON(is_shadow_present_pte(*sptep));
492 __set_spte(sptep, new_spte);
495 /* Rules for using mmu_spte_update:
496 * Update the state bits, it means the mapped pfn is not changged.
498 * Whenever we overwrite a writable spte with a read-only one we
499 * should flush remote TLBs. Otherwise rmap_write_protect
500 * will find a read-only spte, even though the writable spte
501 * might be cached on a CPU's TLB, the return value indicates this
504 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
506 u64 old_spte = *sptep;
509 WARN_ON(!is_rmap_spte(new_spte));
511 if (!is_shadow_present_pte(old_spte)) {
512 mmu_spte_set(sptep, new_spte);
516 if (!spte_has_volatile_bits(old_spte))
517 __update_clear_spte_fast(sptep, new_spte);
519 old_spte = __update_clear_spte_slow(sptep, new_spte);
522 * For the spte updated out of mmu-lock is safe, since
523 * we always atomicly update it, see the comments in
524 * spte_has_volatile_bits().
526 if (is_writable_pte(old_spte) && !is_writable_pte(new_spte))
529 if (!shadow_accessed_mask)
532 if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask))
533 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
534 if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask))
535 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
541 * Rules for using mmu_spte_clear_track_bits:
542 * It sets the sptep from present to nonpresent, and track the
543 * state bits, it is used to clear the last level sptep.
545 static int mmu_spte_clear_track_bits(u64 *sptep)
548 u64 old_spte = *sptep;
550 if (!spte_has_volatile_bits(old_spte))
551 __update_clear_spte_fast(sptep, 0ull);
553 old_spte = __update_clear_spte_slow(sptep, 0ull);
555 if (!is_rmap_spte(old_spte))
558 pfn = spte_to_pfn(old_spte);
561 * KVM does not hold the refcount of the page used by
562 * kvm mmu, before reclaiming the page, we should
563 * unmap it from mmu first.
565 WARN_ON(!kvm_is_mmio_pfn(pfn) && !page_count(pfn_to_page(pfn)));
567 if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
568 kvm_set_pfn_accessed(pfn);
569 if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask))
570 kvm_set_pfn_dirty(pfn);
575 * Rules for using mmu_spte_clear_no_track:
576 * Directly clear spte without caring the state bits of sptep,
577 * it is used to set the upper level spte.
579 static void mmu_spte_clear_no_track(u64 *sptep)
581 __update_clear_spte_fast(sptep, 0ull);
584 static u64 mmu_spte_get_lockless(u64 *sptep)
586 return __get_spte_lockless(sptep);
589 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
592 * Prevent page table teardown by making any free-er wait during
593 * kvm_flush_remote_tlbs() IPI to all active vcpus.
596 vcpu->mode = READING_SHADOW_PAGE_TABLES;
598 * Make sure a following spte read is not reordered ahead of the write
604 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
607 * Make sure the write to vcpu->mode is not reordered in front of
608 * reads to sptes. If it does, kvm_commit_zap_page() can see us
609 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
612 vcpu->mode = OUTSIDE_GUEST_MODE;
616 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
617 struct kmem_cache *base_cache, int min)
621 if (cache->nobjs >= min)
623 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
624 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
627 cache->objects[cache->nobjs++] = obj;
632 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
637 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
638 struct kmem_cache *cache)
641 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
644 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
649 if (cache->nobjs >= min)
651 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
652 page = (void *)__get_free_page(GFP_KERNEL);
655 cache->objects[cache->nobjs++] = page;
660 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
663 free_page((unsigned long)mc->objects[--mc->nobjs]);
666 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
670 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
671 pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
674 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
677 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
678 mmu_page_header_cache, 4);
683 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
685 mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
686 pte_list_desc_cache);
687 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
688 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
689 mmu_page_header_cache);
692 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
697 p = mc->objects[--mc->nobjs];
701 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
703 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
706 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
708 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
711 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
713 if (!sp->role.direct)
714 return sp->gfns[index];
716 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
719 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
722 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
724 sp->gfns[index] = gfn;
728 * Return the pointer to the large page information for a given gfn,
729 * handling slots that are not large page aligned.
731 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
732 struct kvm_memory_slot *slot,
737 idx = gfn_to_index(gfn, slot->base_gfn, level);
738 return &slot->arch.lpage_info[level - 2][idx];
741 static void account_shadowed(struct kvm *kvm, gfn_t gfn)
743 struct kvm_memory_slot *slot;
744 struct kvm_lpage_info *linfo;
747 slot = gfn_to_memslot(kvm, gfn);
748 for (i = PT_DIRECTORY_LEVEL;
749 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
750 linfo = lpage_info_slot(gfn, slot, i);
751 linfo->write_count += 1;
753 kvm->arch.indirect_shadow_pages++;
756 static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
758 struct kvm_memory_slot *slot;
759 struct kvm_lpage_info *linfo;
762 slot = gfn_to_memslot(kvm, gfn);
763 for (i = PT_DIRECTORY_LEVEL;
764 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
765 linfo = lpage_info_slot(gfn, slot, i);
766 linfo->write_count -= 1;
767 WARN_ON(linfo->write_count < 0);
769 kvm->arch.indirect_shadow_pages--;
772 static int has_wrprotected_page(struct kvm *kvm,
776 struct kvm_memory_slot *slot;
777 struct kvm_lpage_info *linfo;
779 slot = gfn_to_memslot(kvm, gfn);
781 linfo = lpage_info_slot(gfn, slot, level);
782 return linfo->write_count;
788 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
790 unsigned long page_size;
793 page_size = kvm_host_page_size(kvm, gfn);
795 for (i = PT_PAGE_TABLE_LEVEL;
796 i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
797 if (page_size >= KVM_HPAGE_SIZE(i))
806 static struct kvm_memory_slot *
807 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
810 struct kvm_memory_slot *slot;
812 slot = gfn_to_memslot(vcpu->kvm, gfn);
813 if (!slot || slot->flags & KVM_MEMSLOT_INVALID ||
814 (no_dirty_log && slot->dirty_bitmap))
820 static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn)
822 return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true);
825 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
827 int host_level, level, max_level;
829 host_level = host_mapping_level(vcpu->kvm, large_gfn);
831 if (host_level == PT_PAGE_TABLE_LEVEL)
834 max_level = kvm_x86_ops->get_lpage_level() < host_level ?
835 kvm_x86_ops->get_lpage_level() : host_level;
837 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
838 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
845 * Pte mapping structures:
847 * If pte_list bit zero is zero, then pte_list point to the spte.
849 * If pte_list bit zero is one, (then pte_list & ~1) points to a struct
850 * pte_list_desc containing more mappings.
852 * Returns the number of pte entries before the spte was added or zero if
853 * the spte was not added.
856 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
857 unsigned long *pte_list)
859 struct pte_list_desc *desc;
863 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
864 *pte_list = (unsigned long)spte;
865 } else if (!(*pte_list & 1)) {
866 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
867 desc = mmu_alloc_pte_list_desc(vcpu);
868 desc->sptes[0] = (u64 *)*pte_list;
869 desc->sptes[1] = spte;
870 *pte_list = (unsigned long)desc | 1;
873 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
874 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
875 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
877 count += PTE_LIST_EXT;
879 if (desc->sptes[PTE_LIST_EXT-1]) {
880 desc->more = mmu_alloc_pte_list_desc(vcpu);
883 for (i = 0; desc->sptes[i]; ++i)
885 desc->sptes[i] = spte;
891 pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc,
892 int i, struct pte_list_desc *prev_desc)
896 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
898 desc->sptes[i] = desc->sptes[j];
899 desc->sptes[j] = NULL;
902 if (!prev_desc && !desc->more)
903 *pte_list = (unsigned long)desc->sptes[0];
906 prev_desc->more = desc->more;
908 *pte_list = (unsigned long)desc->more | 1;
909 mmu_free_pte_list_desc(desc);
912 static void pte_list_remove(u64 *spte, unsigned long *pte_list)
914 struct pte_list_desc *desc;
915 struct pte_list_desc *prev_desc;
919 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
921 } else if (!(*pte_list & 1)) {
922 rmap_printk("pte_list_remove: %p 1->0\n", spte);
923 if ((u64 *)*pte_list != spte) {
924 printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte);
929 rmap_printk("pte_list_remove: %p many->many\n", spte);
930 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
933 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
934 if (desc->sptes[i] == spte) {
935 pte_list_desc_remove_entry(pte_list,
943 pr_err("pte_list_remove: %p many->many\n", spte);
948 typedef void (*pte_list_walk_fn) (u64 *spte);
949 static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn)
951 struct pte_list_desc *desc;
957 if (!(*pte_list & 1))
958 return fn((u64 *)*pte_list);
960 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
962 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
968 static unsigned long *__gfn_to_rmap(gfn_t gfn, int level,
969 struct kvm_memory_slot *slot)
973 idx = gfn_to_index(gfn, slot->base_gfn, level);
974 return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx];
978 * Take gfn and return the reverse mapping to it.
980 static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
982 struct kvm_memory_slot *slot;
984 slot = gfn_to_memslot(kvm, gfn);
985 return __gfn_to_rmap(gfn, level, slot);
988 static bool rmap_can_add(struct kvm_vcpu *vcpu)
990 struct kvm_mmu_memory_cache *cache;
992 cache = &vcpu->arch.mmu_pte_list_desc_cache;
993 return mmu_memory_cache_free_objects(cache);
996 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
998 struct kvm_mmu_page *sp;
999 unsigned long *rmapp;
1001 sp = page_header(__pa(spte));
1002 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1003 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1004 return pte_list_add(vcpu, spte, rmapp);
1007 static void rmap_remove(struct kvm *kvm, u64 *spte)
1009 struct kvm_mmu_page *sp;
1011 unsigned long *rmapp;
1013 sp = page_header(__pa(spte));
1014 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1015 rmapp = gfn_to_rmap(kvm, gfn, sp->role.level);
1016 pte_list_remove(spte, rmapp);
1020 * Used by the following functions to iterate through the sptes linked by a
1021 * rmap. All fields are private and not assumed to be used outside.
1023 struct rmap_iterator {
1024 /* private fields */
1025 struct pte_list_desc *desc; /* holds the sptep if not NULL */
1026 int pos; /* index of the sptep */
1030 * Iteration must be started by this function. This should also be used after
1031 * removing/dropping sptes from the rmap link because in such cases the
1032 * information in the itererator may not be valid.
1034 * Returns sptep if found, NULL otherwise.
1036 static u64 *rmap_get_first(unsigned long rmap, struct rmap_iterator *iter)
1046 iter->desc = (struct pte_list_desc *)(rmap & ~1ul);
1048 return iter->desc->sptes[iter->pos];
1052 * Must be used with a valid iterator: e.g. after rmap_get_first().
1054 * Returns sptep if found, NULL otherwise.
1056 static u64 *rmap_get_next(struct rmap_iterator *iter)
1059 if (iter->pos < PTE_LIST_EXT - 1) {
1063 sptep = iter->desc->sptes[iter->pos];
1068 iter->desc = iter->desc->more;
1072 /* desc->sptes[0] cannot be NULL */
1073 return iter->desc->sptes[iter->pos];
1080 static void drop_spte(struct kvm *kvm, u64 *sptep)
1082 if (mmu_spte_clear_track_bits(sptep))
1083 rmap_remove(kvm, sptep);
1087 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1089 if (is_large_pte(*sptep)) {
1090 WARN_ON(page_header(__pa(sptep))->role.level ==
1091 PT_PAGE_TABLE_LEVEL);
1092 drop_spte(kvm, sptep);
1100 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1102 if (__drop_large_spte(vcpu->kvm, sptep))
1103 kvm_flush_remote_tlbs(vcpu->kvm);
1107 * Write-protect on the specified @sptep, @pt_protect indicates whether
1108 * spte writ-protection is caused by protecting shadow page table.
1109 * @flush indicates whether tlb need be flushed.
1111 * Note: write protection is difference between drity logging and spte
1113 * - for dirty logging, the spte can be set to writable at anytime if
1114 * its dirty bitmap is properly set.
1115 * - for spte protection, the spte can be writable only after unsync-ing
1118 * Return true if the spte is dropped.
1121 spte_write_protect(struct kvm *kvm, u64 *sptep, bool *flush, bool pt_protect)
1125 if (!is_writable_pte(spte) &&
1126 !(pt_protect && spte_is_locklessly_modifiable(spte)))
1129 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1131 if (__drop_large_spte(kvm, sptep)) {
1137 spte &= ~SPTE_MMU_WRITEABLE;
1138 spte = spte & ~PT_WRITABLE_MASK;
1140 *flush |= mmu_spte_update(sptep, spte);
1144 static bool __rmap_write_protect(struct kvm *kvm, unsigned long *rmapp,
1148 struct rmap_iterator iter;
1151 for (sptep = rmap_get_first(*rmapp, &iter); sptep;) {
1152 BUG_ON(!(*sptep & PT_PRESENT_MASK));
1153 if (spte_write_protect(kvm, sptep, &flush, pt_protect)) {
1154 sptep = rmap_get_first(*rmapp, &iter);
1158 sptep = rmap_get_next(&iter);
1165 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1166 * @kvm: kvm instance
1167 * @slot: slot to protect
1168 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1169 * @mask: indicates which pages we should protect
1171 * Used when we do not need to care about huge page mappings: e.g. during dirty
1172 * logging we do not have any such mappings.
1174 void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1175 struct kvm_memory_slot *slot,
1176 gfn_t gfn_offset, unsigned long mask)
1178 unsigned long *rmapp;
1181 rmapp = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1182 PT_PAGE_TABLE_LEVEL, slot);
1183 __rmap_write_protect(kvm, rmapp, false);
1185 /* clear the first set bit */
1190 static bool rmap_write_protect(struct kvm *kvm, u64 gfn)
1192 struct kvm_memory_slot *slot;
1193 unsigned long *rmapp;
1195 bool write_protected = false;
1197 slot = gfn_to_memslot(kvm, gfn);
1199 for (i = PT_PAGE_TABLE_LEVEL;
1200 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
1201 rmapp = __gfn_to_rmap(gfn, i, slot);
1202 write_protected |= __rmap_write_protect(kvm, rmapp, true);
1205 return write_protected;
1208 static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
1209 struct kvm_memory_slot *slot, unsigned long data)
1212 struct rmap_iterator iter;
1213 int need_tlb_flush = 0;
1215 while ((sptep = rmap_get_first(*rmapp, &iter))) {
1216 BUG_ON(!(*sptep & PT_PRESENT_MASK));
1217 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", sptep, *sptep);
1219 drop_spte(kvm, sptep);
1223 return need_tlb_flush;
1226 static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
1227 struct kvm_memory_slot *slot, unsigned long data)
1230 struct rmap_iterator iter;
1233 pte_t *ptep = (pte_t *)data;
1236 WARN_ON(pte_huge(*ptep));
1237 new_pfn = pte_pfn(*ptep);
1239 for (sptep = rmap_get_first(*rmapp, &iter); sptep;) {
1240 BUG_ON(!is_shadow_present_pte(*sptep));
1241 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", sptep, *sptep);
1245 if (pte_write(*ptep)) {
1246 drop_spte(kvm, sptep);
1247 sptep = rmap_get_first(*rmapp, &iter);
1249 new_spte = *sptep & ~PT64_BASE_ADDR_MASK;
1250 new_spte |= (u64)new_pfn << PAGE_SHIFT;
1252 new_spte &= ~PT_WRITABLE_MASK;
1253 new_spte &= ~SPTE_HOST_WRITEABLE;
1254 new_spte &= ~shadow_accessed_mask;
1256 mmu_spte_clear_track_bits(sptep);
1257 mmu_spte_set(sptep, new_spte);
1258 sptep = rmap_get_next(&iter);
1263 kvm_flush_remote_tlbs(kvm);
1268 static int kvm_handle_hva_range(struct kvm *kvm,
1269 unsigned long start,
1272 int (*handler)(struct kvm *kvm,
1273 unsigned long *rmapp,
1274 struct kvm_memory_slot *slot,
1275 unsigned long data))
1279 struct kvm_memslots *slots;
1280 struct kvm_memory_slot *memslot;
1282 slots = kvm_memslots(kvm);
1284 kvm_for_each_memslot(memslot, slots) {
1285 unsigned long hva_start, hva_end;
1286 gfn_t gfn_start, gfn_end;
1288 hva_start = max(start, memslot->userspace_addr);
1289 hva_end = min(end, memslot->userspace_addr +
1290 (memslot->npages << PAGE_SHIFT));
1291 if (hva_start >= hva_end)
1294 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1295 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1297 gfn_start = hva_to_gfn_memslot(hva_start, memslot);
1298 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1300 for (j = PT_PAGE_TABLE_LEVEL;
1301 j < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++j) {
1302 unsigned long idx, idx_end;
1303 unsigned long *rmapp;
1306 * {idx(page_j) | page_j intersects with
1307 * [hva_start, hva_end)} = {idx, idx+1, ..., idx_end}.
1309 idx = gfn_to_index(gfn_start, memslot->base_gfn, j);
1310 idx_end = gfn_to_index(gfn_end - 1, memslot->base_gfn, j);
1312 rmapp = __gfn_to_rmap(gfn_start, j, memslot);
1314 for (; idx <= idx_end; ++idx)
1315 ret |= handler(kvm, rmapp++, memslot, data);
1322 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1324 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
1325 struct kvm_memory_slot *slot,
1326 unsigned long data))
1328 return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1331 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
1333 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
1336 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)
1338 return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1341 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1343 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1346 static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1347 struct kvm_memory_slot *slot, unsigned long data)
1350 struct rmap_iterator uninitialized_var(iter);
1354 * In case of absence of EPT Access and Dirty Bits supports,
1355 * emulate the accessed bit for EPT, by checking if this page has
1356 * an EPT mapping, and clearing it if it does. On the next access,
1357 * a new EPT mapping will be established.
1358 * This has some overhead, but not as much as the cost of swapping
1359 * out actively used pages or breaking up actively used hugepages.
1361 if (!shadow_accessed_mask) {
1362 young = kvm_unmap_rmapp(kvm, rmapp, slot, data);
1366 for (sptep = rmap_get_first(*rmapp, &iter); sptep;
1367 sptep = rmap_get_next(&iter)) {
1368 BUG_ON(!is_shadow_present_pte(*sptep));
1370 if (*sptep & shadow_accessed_mask) {
1372 clear_bit((ffs(shadow_accessed_mask) - 1),
1373 (unsigned long *)sptep);
1377 /* @data has hva passed to kvm_age_hva(). */
1378 trace_kvm_age_page(data, slot, young);
1382 static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1383 struct kvm_memory_slot *slot, unsigned long data)
1386 struct rmap_iterator iter;
1390 * If there's no access bit in the secondary pte set by the
1391 * hardware it's up to gup-fast/gup to set the access bit in
1392 * the primary pte or in the page structure.
1394 if (!shadow_accessed_mask)
1397 for (sptep = rmap_get_first(*rmapp, &iter); sptep;
1398 sptep = rmap_get_next(&iter)) {
1399 BUG_ON(!is_shadow_present_pte(*sptep));
1401 if (*sptep & shadow_accessed_mask) {
1410 #define RMAP_RECYCLE_THRESHOLD 1000
1412 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1414 unsigned long *rmapp;
1415 struct kvm_mmu_page *sp;
1417 sp = page_header(__pa(spte));
1419 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1421 kvm_unmap_rmapp(vcpu->kvm, rmapp, NULL, 0);
1422 kvm_flush_remote_tlbs(vcpu->kvm);
1425 int kvm_age_hva(struct kvm *kvm, unsigned long hva)
1427 return kvm_handle_hva(kvm, hva, hva, kvm_age_rmapp);
1430 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1432 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1436 static int is_empty_shadow_page(u64 *spt)
1441 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1442 if (is_shadow_present_pte(*pos)) {
1443 printk(KERN_ERR "%s: %p %llx\n", __func__,
1452 * This value is the sum of all of the kvm instances's
1453 * kvm->arch.n_used_mmu_pages values. We need a global,
1454 * aggregate version in order to make the slab shrinker
1457 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1459 kvm->arch.n_used_mmu_pages += nr;
1460 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1464 * Remove the sp from shadow page cache, after call it,
1465 * we can not find this sp from the cache, and the shadow
1466 * page table is still valid.
1467 * It should be under the protection of mmu lock.
1469 static void kvm_mmu_isolate_page(struct kvm_mmu_page *sp)
1471 ASSERT(is_empty_shadow_page(sp->spt));
1472 hlist_del(&sp->hash_link);
1473 if (!sp->role.direct)
1474 free_page((unsigned long)sp->gfns);
1478 * Free the shadow page table and the sp, we can do it
1479 * out of the protection of mmu lock.
1481 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1483 list_del(&sp->link);
1484 free_page((unsigned long)sp->spt);
1485 kmem_cache_free(mmu_page_header_cache, sp);
1488 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1490 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
1493 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1494 struct kvm_mmu_page *sp, u64 *parent_pte)
1499 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1502 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1505 pte_list_remove(parent_pte, &sp->parent_ptes);
1508 static void drop_parent_pte(struct kvm_mmu_page *sp,
1511 mmu_page_remove_parent_pte(sp, parent_pte);
1512 mmu_spte_clear_no_track(parent_pte);
1515 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
1516 u64 *parent_pte, int direct)
1518 struct kvm_mmu_page *sp;
1519 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1520 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1522 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1523 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1524 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1525 sp->parent_ptes = 0;
1526 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1527 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1531 static void mark_unsync(u64 *spte);
1532 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1534 pte_list_walk(&sp->parent_ptes, mark_unsync);
1537 static void mark_unsync(u64 *spte)
1539 struct kvm_mmu_page *sp;
1542 sp = page_header(__pa(spte));
1543 index = spte - sp->spt;
1544 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1546 if (sp->unsync_children++)
1548 kvm_mmu_mark_parents_unsync(sp);
1551 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1552 struct kvm_mmu_page *sp)
1557 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1561 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1562 struct kvm_mmu_page *sp, u64 *spte,
1568 #define KVM_PAGE_ARRAY_NR 16
1570 struct kvm_mmu_pages {
1571 struct mmu_page_and_offset {
1572 struct kvm_mmu_page *sp;
1574 } page[KVM_PAGE_ARRAY_NR];
1578 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1584 for (i=0; i < pvec->nr; i++)
1585 if (pvec->page[i].sp == sp)
1588 pvec->page[pvec->nr].sp = sp;
1589 pvec->page[pvec->nr].idx = idx;
1591 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1594 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1595 struct kvm_mmu_pages *pvec)
1597 int i, ret, nr_unsync_leaf = 0;
1599 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1600 struct kvm_mmu_page *child;
1601 u64 ent = sp->spt[i];
1603 if (!is_shadow_present_pte(ent) || is_large_pte(ent))
1604 goto clear_child_bitmap;
1606 child = page_header(ent & PT64_BASE_ADDR_MASK);
1608 if (child->unsync_children) {
1609 if (mmu_pages_add(pvec, child, i))
1612 ret = __mmu_unsync_walk(child, pvec);
1614 goto clear_child_bitmap;
1616 nr_unsync_leaf += ret;
1619 } else if (child->unsync) {
1621 if (mmu_pages_add(pvec, child, i))
1624 goto clear_child_bitmap;
1629 __clear_bit(i, sp->unsync_child_bitmap);
1630 sp->unsync_children--;
1631 WARN_ON((int)sp->unsync_children < 0);
1635 return nr_unsync_leaf;
1638 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1639 struct kvm_mmu_pages *pvec)
1641 if (!sp->unsync_children)
1644 mmu_pages_add(pvec, sp, 0);
1645 return __mmu_unsync_walk(sp, pvec);
1648 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1650 WARN_ON(!sp->unsync);
1651 trace_kvm_mmu_sync_page(sp);
1653 --kvm->stat.mmu_unsync;
1656 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1657 struct list_head *invalid_list);
1658 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1659 struct list_head *invalid_list);
1661 #define for_each_gfn_sp(kvm, sp, gfn, pos) \
1662 hlist_for_each_entry(sp, pos, \
1663 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1664 if ((sp)->gfn != (gfn)) {} else
1666 #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos) \
1667 hlist_for_each_entry(sp, pos, \
1668 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1669 if ((sp)->gfn != (gfn) || (sp)->role.direct || \
1670 (sp)->role.invalid) {} else
1672 /* @sp->gfn should be write-protected at the call site */
1673 static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1674 struct list_head *invalid_list, bool clear_unsync)
1676 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
1677 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1682 kvm_unlink_unsync_page(vcpu->kvm, sp);
1684 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1685 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1689 kvm_mmu_flush_tlb(vcpu);
1693 static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
1694 struct kvm_mmu_page *sp)
1696 LIST_HEAD(invalid_list);
1699 ret = __kvm_sync_page(vcpu, sp, &invalid_list, false);
1701 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1706 #ifdef CONFIG_KVM_MMU_AUDIT
1707 #include "mmu_audit.c"
1709 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1710 static void mmu_audit_disable(void) { }
1713 static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1714 struct list_head *invalid_list)
1716 return __kvm_sync_page(vcpu, sp, invalid_list, true);
1719 /* @gfn should be write-protected at the call site */
1720 static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
1722 struct kvm_mmu_page *s;
1723 struct hlist_node *node;
1724 LIST_HEAD(invalid_list);
1727 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
1731 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1732 kvm_unlink_unsync_page(vcpu->kvm, s);
1733 if ((s->role.cr4_pae != !!is_pae(vcpu)) ||
1734 (vcpu->arch.mmu.sync_page(vcpu, s))) {
1735 kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list);
1741 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1743 kvm_mmu_flush_tlb(vcpu);
1746 struct mmu_page_path {
1747 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1748 unsigned int idx[PT64_ROOT_LEVEL-1];
1751 #define for_each_sp(pvec, sp, parents, i) \
1752 for (i = mmu_pages_next(&pvec, &parents, -1), \
1753 sp = pvec.page[i].sp; \
1754 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1755 i = mmu_pages_next(&pvec, &parents, i))
1757 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1758 struct mmu_page_path *parents,
1763 for (n = i+1; n < pvec->nr; n++) {
1764 struct kvm_mmu_page *sp = pvec->page[n].sp;
1766 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1767 parents->idx[0] = pvec->page[n].idx;
1771 parents->parent[sp->role.level-2] = sp;
1772 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1778 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1780 struct kvm_mmu_page *sp;
1781 unsigned int level = 0;
1784 unsigned int idx = parents->idx[level];
1786 sp = parents->parent[level];
1790 --sp->unsync_children;
1791 WARN_ON((int)sp->unsync_children < 0);
1792 __clear_bit(idx, sp->unsync_child_bitmap);
1794 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
1797 static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1798 struct mmu_page_path *parents,
1799 struct kvm_mmu_pages *pvec)
1801 parents->parent[parent->role.level-1] = NULL;
1805 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1806 struct kvm_mmu_page *parent)
1809 struct kvm_mmu_page *sp;
1810 struct mmu_page_path parents;
1811 struct kvm_mmu_pages pages;
1812 LIST_HEAD(invalid_list);
1814 kvm_mmu_pages_init(parent, &parents, &pages);
1815 while (mmu_unsync_walk(parent, &pages)) {
1816 bool protected = false;
1818 for_each_sp(pages, sp, parents, i)
1819 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1822 kvm_flush_remote_tlbs(vcpu->kvm);
1824 for_each_sp(pages, sp, parents, i) {
1825 kvm_sync_page(vcpu, sp, &invalid_list);
1826 mmu_pages_clear_parents(&parents);
1828 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1829 cond_resched_lock(&vcpu->kvm->mmu_lock);
1830 kvm_mmu_pages_init(parent, &parents, &pages);
1834 static void init_shadow_page_table(struct kvm_mmu_page *sp)
1838 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1842 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
1844 sp->write_flooding_count = 0;
1847 static void clear_sp_write_flooding_count(u64 *spte)
1849 struct kvm_mmu_page *sp = page_header(__pa(spte));
1851 __clear_sp_write_flooding_count(sp);
1854 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1862 union kvm_mmu_page_role role;
1864 struct kvm_mmu_page *sp;
1865 struct hlist_node *node;
1866 bool need_sync = false;
1868 role = vcpu->arch.mmu.base_role;
1870 role.direct = direct;
1873 role.access = access;
1874 if (!vcpu->arch.mmu.direct_map
1875 && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
1876 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1877 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1878 role.quadrant = quadrant;
1880 for_each_gfn_sp(vcpu->kvm, sp, gfn, node) {
1881 if (!need_sync && sp->unsync)
1884 if (sp->role.word != role.word)
1887 if (sp->unsync && kvm_sync_page_transient(vcpu, sp))
1890 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1891 if (sp->unsync_children) {
1892 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1893 kvm_mmu_mark_parents_unsync(sp);
1894 } else if (sp->unsync)
1895 kvm_mmu_mark_parents_unsync(sp);
1897 __clear_sp_write_flooding_count(sp);
1898 trace_kvm_mmu_get_page(sp, false);
1901 ++vcpu->kvm->stat.mmu_cache_miss;
1902 sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct);
1907 hlist_add_head(&sp->hash_link,
1908 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
1910 if (rmap_write_protect(vcpu->kvm, gfn))
1911 kvm_flush_remote_tlbs(vcpu->kvm);
1912 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
1913 kvm_sync_pages(vcpu, gfn);
1915 account_shadowed(vcpu->kvm, gfn);
1917 init_shadow_page_table(sp);
1918 trace_kvm_mmu_get_page(sp, true);
1922 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1923 struct kvm_vcpu *vcpu, u64 addr)
1925 iterator->addr = addr;
1926 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1927 iterator->level = vcpu->arch.mmu.shadow_root_level;
1929 if (iterator->level == PT64_ROOT_LEVEL &&
1930 vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
1931 !vcpu->arch.mmu.direct_map)
1934 if (iterator->level == PT32E_ROOT_LEVEL) {
1935 iterator->shadow_addr
1936 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1937 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1939 if (!iterator->shadow_addr)
1940 iterator->level = 0;
1944 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1946 if (iterator->level < PT_PAGE_TABLE_LEVEL)
1949 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1950 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1954 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
1957 if (is_last_spte(spte, iterator->level)) {
1958 iterator->level = 0;
1962 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
1966 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1968 return __shadow_walk_next(iterator, *iterator->sptep);
1971 static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp)
1975 spte = __pa(sp->spt)
1976 | PT_PRESENT_MASK | PT_ACCESSED_MASK
1977 | PT_WRITABLE_MASK | PT_USER_MASK;
1978 mmu_spte_set(sptep, spte);
1981 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1982 unsigned direct_access)
1984 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
1985 struct kvm_mmu_page *child;
1988 * For the direct sp, if the guest pte's dirty bit
1989 * changed form clean to dirty, it will corrupt the
1990 * sp's access: allow writable in the read-only sp,
1991 * so we should update the spte at this point to get
1992 * a new sp with the correct access.
1994 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
1995 if (child->role.access == direct_access)
1998 drop_parent_pte(child, sptep);
1999 kvm_flush_remote_tlbs(vcpu->kvm);
2003 static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2007 struct kvm_mmu_page *child;
2010 if (is_shadow_present_pte(pte)) {
2011 if (is_last_spte(pte, sp->role.level)) {
2012 drop_spte(kvm, spte);
2013 if (is_large_pte(pte))
2016 child = page_header(pte & PT64_BASE_ADDR_MASK);
2017 drop_parent_pte(child, spte);
2022 if (is_mmio_spte(pte))
2023 mmu_spte_clear_no_track(spte);
2028 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
2029 struct kvm_mmu_page *sp)
2033 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2034 mmu_page_zap_pte(kvm, sp, sp->spt + i);
2037 static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
2039 mmu_page_remove_parent_pte(sp, parent_pte);
2042 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2045 struct rmap_iterator iter;
2047 while ((sptep = rmap_get_first(sp->parent_ptes, &iter)))
2048 drop_parent_pte(sp, sptep);
2051 static int mmu_zap_unsync_children(struct kvm *kvm,
2052 struct kvm_mmu_page *parent,
2053 struct list_head *invalid_list)
2056 struct mmu_page_path parents;
2057 struct kvm_mmu_pages pages;
2059 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
2062 kvm_mmu_pages_init(parent, &parents, &pages);
2063 while (mmu_unsync_walk(parent, &pages)) {
2064 struct kvm_mmu_page *sp;
2066 for_each_sp(pages, sp, parents, i) {
2067 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2068 mmu_pages_clear_parents(&parents);
2071 kvm_mmu_pages_init(parent, &parents, &pages);
2077 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2078 struct list_head *invalid_list)
2082 trace_kvm_mmu_prepare_zap_page(sp);
2083 ++kvm->stat.mmu_shadow_zapped;
2084 ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
2085 kvm_mmu_page_unlink_children(kvm, sp);
2086 kvm_mmu_unlink_parents(kvm, sp);
2087 if (!sp->role.invalid && !sp->role.direct)
2088 unaccount_shadowed(kvm, sp->gfn);
2090 kvm_unlink_unsync_page(kvm, sp);
2091 if (!sp->root_count) {
2094 list_move(&sp->link, invalid_list);
2095 kvm_mod_used_mmu_pages(kvm, -1);
2097 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2098 kvm_reload_remote_mmus(kvm);
2101 sp->role.invalid = 1;
2105 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2106 struct list_head *invalid_list)
2108 struct kvm_mmu_page *sp;
2110 if (list_empty(invalid_list))
2114 * wmb: make sure everyone sees our modifications to the page tables
2115 * rmb: make sure we see changes to vcpu->mode
2120 * Wait for all vcpus to exit guest mode and/or lockless shadow
2123 kvm_flush_remote_tlbs(kvm);
2126 sp = list_first_entry(invalid_list, struct kvm_mmu_page, link);
2127 WARN_ON(!sp->role.invalid || sp->root_count);
2128 kvm_mmu_isolate_page(sp);
2129 kvm_mmu_free_page(sp);
2130 } while (!list_empty(invalid_list));
2134 * Changing the number of mmu pages allocated to the vm
2135 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2137 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
2139 LIST_HEAD(invalid_list);
2141 * If we set the number of mmu pages to be smaller be than the
2142 * number of actived pages , we must to free some mmu pages before we
2146 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2147 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages &&
2148 !list_empty(&kvm->arch.active_mmu_pages)) {
2149 struct kvm_mmu_page *page;
2151 page = container_of(kvm->arch.active_mmu_pages.prev,
2152 struct kvm_mmu_page, link);
2153 kvm_mmu_prepare_zap_page(kvm, page, &invalid_list);
2155 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2156 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2159 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2162 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2164 struct kvm_mmu_page *sp;
2165 struct hlist_node *node;
2166 LIST_HEAD(invalid_list);
2169 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2171 spin_lock(&kvm->mmu_lock);
2172 for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
2173 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2176 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2178 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2179 spin_unlock(&kvm->mmu_lock);
2183 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2186 * The function is based on mtrr_type_lookup() in
2187 * arch/x86/kernel/cpu/mtrr/generic.c
2189 static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
2194 u8 prev_match, curr_match;
2195 int num_var_ranges = KVM_NR_VAR_MTRR;
2197 if (!mtrr_state->enabled)
2200 /* Make end inclusive end, instead of exclusive */
2203 /* Look in fixed ranges. Just return the type as per start */
2204 if (mtrr_state->have_fixed && (start < 0x100000)) {
2207 if (start < 0x80000) {
2209 idx += (start >> 16);
2210 return mtrr_state->fixed_ranges[idx];
2211 } else if (start < 0xC0000) {
2213 idx += ((start - 0x80000) >> 14);
2214 return mtrr_state->fixed_ranges[idx];
2215 } else if (start < 0x1000000) {
2217 idx += ((start - 0xC0000) >> 12);
2218 return mtrr_state->fixed_ranges[idx];
2223 * Look in variable ranges
2224 * Look of multiple ranges matching this address and pick type
2225 * as per MTRR precedence
2227 if (!(mtrr_state->enabled & 2))
2228 return mtrr_state->def_type;
2231 for (i = 0; i < num_var_ranges; ++i) {
2232 unsigned short start_state, end_state;
2234 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
2237 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
2238 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
2239 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
2240 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
2242 start_state = ((start & mask) == (base & mask));
2243 end_state = ((end & mask) == (base & mask));
2244 if (start_state != end_state)
2247 if ((start & mask) != (base & mask))
2250 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
2251 if (prev_match == 0xFF) {
2252 prev_match = curr_match;
2256 if (prev_match == MTRR_TYPE_UNCACHABLE ||
2257 curr_match == MTRR_TYPE_UNCACHABLE)
2258 return MTRR_TYPE_UNCACHABLE;
2260 if ((prev_match == MTRR_TYPE_WRBACK &&
2261 curr_match == MTRR_TYPE_WRTHROUGH) ||
2262 (prev_match == MTRR_TYPE_WRTHROUGH &&
2263 curr_match == MTRR_TYPE_WRBACK)) {
2264 prev_match = MTRR_TYPE_WRTHROUGH;
2265 curr_match = MTRR_TYPE_WRTHROUGH;
2268 if (prev_match != curr_match)
2269 return MTRR_TYPE_UNCACHABLE;
2272 if (prev_match != 0xFF)
2275 return mtrr_state->def_type;
2278 u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
2282 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
2283 (gfn << PAGE_SHIFT) + PAGE_SIZE);
2284 if (mtrr == 0xfe || mtrr == 0xff)
2285 mtrr = MTRR_TYPE_WRBACK;
2288 EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
2290 static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2292 trace_kvm_mmu_unsync_page(sp);
2293 ++vcpu->kvm->stat.mmu_unsync;
2296 kvm_mmu_mark_parents_unsync(sp);
2299 static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
2301 struct kvm_mmu_page *s;
2302 struct hlist_node *node;
2304 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
2307 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
2308 __kvm_unsync_page(vcpu, s);
2312 static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2315 struct kvm_mmu_page *s;
2316 struct hlist_node *node;
2317 bool need_unsync = false;
2319 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
2323 if (s->role.level != PT_PAGE_TABLE_LEVEL)
2326 if (!need_unsync && !s->unsync) {
2331 kvm_unsync_pages(vcpu, gfn);
2335 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2336 unsigned pte_access, int level,
2337 gfn_t gfn, pfn_t pfn, bool speculative,
2338 bool can_unsync, bool host_writable)
2343 if (set_mmio_spte(sptep, gfn, pfn, pte_access))
2346 spte = PT_PRESENT_MASK;
2348 spte |= shadow_accessed_mask;
2350 if (pte_access & ACC_EXEC_MASK)
2351 spte |= shadow_x_mask;
2353 spte |= shadow_nx_mask;
2355 if (pte_access & ACC_USER_MASK)
2356 spte |= shadow_user_mask;
2358 if (level > PT_PAGE_TABLE_LEVEL)
2359 spte |= PT_PAGE_SIZE_MASK;
2361 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2362 kvm_is_mmio_pfn(pfn));
2365 spte |= SPTE_HOST_WRITEABLE;
2367 pte_access &= ~ACC_WRITE_MASK;
2369 spte |= (u64)pfn << PAGE_SHIFT;
2371 if (pte_access & ACC_WRITE_MASK) {
2374 * Other vcpu creates new sp in the window between
2375 * mapping_level() and acquiring mmu-lock. We can
2376 * allow guest to retry the access, the mapping can
2377 * be fixed if guest refault.
2379 if (level > PT_PAGE_TABLE_LEVEL &&
2380 has_wrprotected_page(vcpu->kvm, gfn, level))
2383 spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE;
2386 * Optimization: for pte sync, if spte was writable the hash
2387 * lookup is unnecessary (and expensive). Write protection
2388 * is responsibility of mmu_get_page / kvm_sync_page.
2389 * Same reasoning can be applied to dirty page accounting.
2391 if (!can_unsync && is_writable_pte(*sptep))
2394 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2395 pgprintk("%s: found shadow page for %llx, marking ro\n",
2398 pte_access &= ~ACC_WRITE_MASK;
2399 spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE);
2403 if (pte_access & ACC_WRITE_MASK)
2404 mark_page_dirty(vcpu->kvm, gfn);
2407 if (mmu_spte_update(sptep, spte))
2408 kvm_flush_remote_tlbs(vcpu->kvm);
2413 static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2414 unsigned pt_access, unsigned pte_access,
2415 int write_fault, int *emulate, int level, gfn_t gfn,
2416 pfn_t pfn, bool speculative, bool host_writable)
2418 int was_rmapped = 0;
2421 pgprintk("%s: spte %llx access %x write_fault %d gfn %llx\n",
2422 __func__, *sptep, pt_access,
2425 if (is_rmap_spte(*sptep)) {
2427 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2428 * the parent of the now unreachable PTE.
2430 if (level > PT_PAGE_TABLE_LEVEL &&
2431 !is_large_pte(*sptep)) {
2432 struct kvm_mmu_page *child;
2435 child = page_header(pte & PT64_BASE_ADDR_MASK);
2436 drop_parent_pte(child, sptep);
2437 kvm_flush_remote_tlbs(vcpu->kvm);
2438 } else if (pfn != spte_to_pfn(*sptep)) {
2439 pgprintk("hfn old %llx new %llx\n",
2440 spte_to_pfn(*sptep), pfn);
2441 drop_spte(vcpu->kvm, sptep);
2442 kvm_flush_remote_tlbs(vcpu->kvm);
2447 if (set_spte(vcpu, sptep, pte_access, level, gfn, pfn, speculative,
2448 true, host_writable)) {
2451 kvm_mmu_flush_tlb(vcpu);
2454 if (unlikely(is_mmio_spte(*sptep) && emulate))
2457 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2458 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2459 is_large_pte(*sptep)? "2MB" : "4kB",
2460 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
2462 if (!was_rmapped && is_large_pte(*sptep))
2463 ++vcpu->kvm->stat.lpages;
2465 if (is_shadow_present_pte(*sptep)) {
2467 rmap_count = rmap_add(vcpu, sptep, gfn);
2468 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2469 rmap_recycle(vcpu, sptep, gfn);
2473 kvm_release_pfn_clean(pfn);
2476 static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
2478 mmu_free_roots(vcpu);
2481 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
2485 bit7 = (gpte >> 7) & 1;
2486 return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0;
2489 static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2492 struct kvm_memory_slot *slot;
2494 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2496 return KVM_PFN_ERR_FAULT;
2498 return gfn_to_pfn_memslot_atomic(slot, gfn);
2501 static bool prefetch_invalid_gpte(struct kvm_vcpu *vcpu,
2502 struct kvm_mmu_page *sp, u64 *spte,
2505 if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL))
2508 if (!is_present_gpte(gpte))
2511 if (!(gpte & PT_ACCESSED_MASK))
2517 drop_spte(vcpu->kvm, spte);
2521 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2522 struct kvm_mmu_page *sp,
2523 u64 *start, u64 *end)
2525 struct page *pages[PTE_PREFETCH_NUM];
2526 unsigned access = sp->role.access;
2530 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2531 if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK))
2534 ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start);
2538 for (i = 0; i < ret; i++, gfn++, start++)
2539 mmu_set_spte(vcpu, start, ACC_ALL, access, 0, NULL,
2540 sp->role.level, gfn, page_to_pfn(pages[i]),
2546 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2547 struct kvm_mmu_page *sp, u64 *sptep)
2549 u64 *spte, *start = NULL;
2552 WARN_ON(!sp->role.direct);
2554 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2557 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2558 if (is_shadow_present_pte(*spte) || spte == sptep) {
2561 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2569 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2571 struct kvm_mmu_page *sp;
2574 * Since it's no accessed bit on EPT, it's no way to
2575 * distinguish between actually accessed translations
2576 * and prefetched, so disable pte prefetch if EPT is
2579 if (!shadow_accessed_mask)
2582 sp = page_header(__pa(sptep));
2583 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2586 __direct_pte_prefetch(vcpu, sp, sptep);
2589 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
2590 int map_writable, int level, gfn_t gfn, pfn_t pfn,
2593 struct kvm_shadow_walk_iterator iterator;
2594 struct kvm_mmu_page *sp;
2598 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2599 if (iterator.level == level) {
2600 unsigned pte_access = ACC_ALL;
2602 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, pte_access,
2603 write, &emulate, level, gfn, pfn,
2604 prefault, map_writable);
2605 direct_pte_prefetch(vcpu, iterator.sptep);
2606 ++vcpu->stat.pf_fixed;
2610 if (!is_shadow_present_pte(*iterator.sptep)) {
2611 u64 base_addr = iterator.addr;
2613 base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2614 pseudo_gfn = base_addr >> PAGE_SHIFT;
2615 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2617 1, ACC_ALL, iterator.sptep);
2619 mmu_spte_set(iterator.sptep,
2621 | PT_PRESENT_MASK | PT_WRITABLE_MASK
2622 | shadow_user_mask | shadow_x_mask
2623 | shadow_accessed_mask);
2629 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2633 info.si_signo = SIGBUS;
2635 info.si_code = BUS_MCEERR_AR;
2636 info.si_addr = (void __user *)address;
2637 info.si_addr_lsb = PAGE_SHIFT;
2639 send_sig_info(SIGBUS, &info, tsk);
2642 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, pfn_t pfn)
2645 * Do not cache the mmio info caused by writing the readonly gfn
2646 * into the spte otherwise read access on readonly gfn also can
2647 * caused mmio page fault and treat it as mmio access.
2648 * Return 1 to tell kvm to emulate it.
2650 if (pfn == KVM_PFN_ERR_RO_FAULT)
2653 if (pfn == KVM_PFN_ERR_HWPOISON) {
2654 kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current);
2661 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
2662 gfn_t *gfnp, pfn_t *pfnp, int *levelp)
2666 int level = *levelp;
2669 * Check if it's a transparent hugepage. If this would be an
2670 * hugetlbfs page, level wouldn't be set to
2671 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2674 if (!is_error_noslot_pfn(pfn) && !kvm_is_mmio_pfn(pfn) &&
2675 level == PT_PAGE_TABLE_LEVEL &&
2676 PageTransCompound(pfn_to_page(pfn)) &&
2677 !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) {
2680 * mmu_notifier_retry was successful and we hold the
2681 * mmu_lock here, so the pmd can't become splitting
2682 * from under us, and in turn
2683 * __split_huge_page_refcount() can't run from under
2684 * us and we can safely transfer the refcount from
2685 * PG_tail to PG_head as we switch the pfn to tail to
2688 *levelp = level = PT_DIRECTORY_LEVEL;
2689 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2690 VM_BUG_ON((gfn & mask) != (pfn & mask));
2694 kvm_release_pfn_clean(pfn);
2702 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2703 pfn_t pfn, unsigned access, int *ret_val)
2707 /* The pfn is invalid, report the error! */
2708 if (unlikely(is_error_pfn(pfn))) {
2709 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2713 if (unlikely(is_noslot_pfn(pfn)))
2714 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
2721 static bool page_fault_can_be_fast(struct kvm_vcpu *vcpu, u32 error_code)
2724 * #PF can be fast only if the shadow page table is present and it
2725 * is caused by write-protect, that means we just need change the
2726 * W bit of the spte which can be done out of mmu-lock.
2728 if (!(error_code & PFERR_PRESENT_MASK) ||
2729 !(error_code & PFERR_WRITE_MASK))
2736 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 spte)
2738 struct kvm_mmu_page *sp = page_header(__pa(sptep));
2741 WARN_ON(!sp->role.direct);
2744 * The gfn of direct spte is stable since it is calculated
2747 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
2749 if (cmpxchg64(sptep, spte, spte | PT_WRITABLE_MASK) == spte)
2750 mark_page_dirty(vcpu->kvm, gfn);
2757 * - true: let the vcpu to access on the same address again.
2758 * - false: let the real page fault path to fix it.
2760 static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
2763 struct kvm_shadow_walk_iterator iterator;
2767 if (!page_fault_can_be_fast(vcpu, error_code))
2770 walk_shadow_page_lockless_begin(vcpu);
2771 for_each_shadow_entry_lockless(vcpu, gva, iterator, spte)
2772 if (!is_shadow_present_pte(spte) || iterator.level < level)
2776 * If the mapping has been changed, let the vcpu fault on the
2777 * same address again.
2779 if (!is_rmap_spte(spte)) {
2784 if (!is_last_spte(spte, level))
2788 * Check if it is a spurious fault caused by TLB lazily flushed.
2790 * Need not check the access of upper level table entries since
2791 * they are always ACC_ALL.
2793 if (is_writable_pte(spte)) {
2799 * Currently, to simplify the code, only the spte write-protected
2800 * by dirty-log can be fast fixed.
2802 if (!spte_is_locklessly_modifiable(spte))
2806 * Currently, fast page fault only works for direct mapping since
2807 * the gfn is not stable for indirect shadow page.
2808 * See Documentation/virtual/kvm/locking.txt to get more detail.
2810 ret = fast_pf_fix_direct_spte(vcpu, iterator.sptep, spte);
2812 trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep,
2814 walk_shadow_page_lockless_end(vcpu);
2819 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
2820 gva_t gva, pfn_t *pfn, bool write, bool *writable);
2822 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code,
2823 gfn_t gfn, bool prefault)
2829 unsigned long mmu_seq;
2830 bool map_writable, write = error_code & PFERR_WRITE_MASK;
2832 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
2833 if (likely(!force_pt_level)) {
2834 level = mapping_level(vcpu, gfn);
2836 * This path builds a PAE pagetable - so we can map
2837 * 2mb pages at maximum. Therefore check if the level
2838 * is larger than that.
2840 if (level > PT_DIRECTORY_LEVEL)
2841 level = PT_DIRECTORY_LEVEL;
2843 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2845 level = PT_PAGE_TABLE_LEVEL;
2847 if (fast_page_fault(vcpu, v, level, error_code))
2850 mmu_seq = vcpu->kvm->mmu_notifier_seq;
2853 if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
2856 if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
2859 spin_lock(&vcpu->kvm->mmu_lock);
2860 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
2862 kvm_mmu_free_some_pages(vcpu);
2863 if (likely(!force_pt_level))
2864 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
2865 r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn,
2867 spin_unlock(&vcpu->kvm->mmu_lock);
2873 spin_unlock(&vcpu->kvm->mmu_lock);
2874 kvm_release_pfn_clean(pfn);
2879 static void mmu_free_roots(struct kvm_vcpu *vcpu)
2882 struct kvm_mmu_page *sp;
2883 LIST_HEAD(invalid_list);
2885 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2887 spin_lock(&vcpu->kvm->mmu_lock);
2888 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
2889 (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
2890 vcpu->arch.mmu.direct_map)) {
2891 hpa_t root = vcpu->arch.mmu.root_hpa;
2893 sp = page_header(root);
2895 if (!sp->root_count && sp->role.invalid) {
2896 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
2897 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2899 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2900 spin_unlock(&vcpu->kvm->mmu_lock);
2903 for (i = 0; i < 4; ++i) {
2904 hpa_t root = vcpu->arch.mmu.pae_root[i];
2907 root &= PT64_BASE_ADDR_MASK;
2908 sp = page_header(root);
2910 if (!sp->root_count && sp->role.invalid)
2911 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2914 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
2916 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2917 spin_unlock(&vcpu->kvm->mmu_lock);
2918 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2921 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2925 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
2926 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2933 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
2935 struct kvm_mmu_page *sp;
2938 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2939 spin_lock(&vcpu->kvm->mmu_lock);
2940 kvm_mmu_free_some_pages(vcpu);
2941 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL,
2944 spin_unlock(&vcpu->kvm->mmu_lock);
2945 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
2946 } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
2947 for (i = 0; i < 4; ++i) {
2948 hpa_t root = vcpu->arch.mmu.pae_root[i];
2950 ASSERT(!VALID_PAGE(root));
2951 spin_lock(&vcpu->kvm->mmu_lock);
2952 kvm_mmu_free_some_pages(vcpu);
2953 sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
2955 PT32_ROOT_LEVEL, 1, ACC_ALL,
2957 root = __pa(sp->spt);
2959 spin_unlock(&vcpu->kvm->mmu_lock);
2960 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
2962 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
2969 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
2971 struct kvm_mmu_page *sp;
2976 root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
2978 if (mmu_check_root(vcpu, root_gfn))
2982 * Do we shadow a long mode page table? If so we need to
2983 * write-protect the guests page table root.
2985 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
2986 hpa_t root = vcpu->arch.mmu.root_hpa;
2988 ASSERT(!VALID_PAGE(root));
2990 spin_lock(&vcpu->kvm->mmu_lock);
2991 kvm_mmu_free_some_pages(vcpu);
2992 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
2994 root = __pa(sp->spt);
2996 spin_unlock(&vcpu->kvm->mmu_lock);
2997 vcpu->arch.mmu.root_hpa = root;
3002 * We shadow a 32 bit page table. This may be a legacy 2-level
3003 * or a PAE 3-level page table. In either case we need to be aware that
3004 * the shadow page table may be a PAE or a long mode page table.
3006 pm_mask = PT_PRESENT_MASK;
3007 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
3008 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3010 for (i = 0; i < 4; ++i) {
3011 hpa_t root = vcpu->arch.mmu.pae_root[i];
3013 ASSERT(!VALID_PAGE(root));
3014 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
3015 pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i);
3016 if (!is_present_gpte(pdptr)) {
3017 vcpu->arch.mmu.pae_root[i] = 0;
3020 root_gfn = pdptr >> PAGE_SHIFT;
3021 if (mmu_check_root(vcpu, root_gfn))
3024 spin_lock(&vcpu->kvm->mmu_lock);
3025 kvm_mmu_free_some_pages(vcpu);
3026 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
3029 root = __pa(sp->spt);
3031 spin_unlock(&vcpu->kvm->mmu_lock);
3033 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
3035 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3038 * If we shadow a 32 bit page table with a long mode page
3039 * table we enter this path.
3041 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3042 if (vcpu->arch.mmu.lm_root == NULL) {
3044 * The additional page necessary for this is only
3045 * allocated on demand.
3050 lm_root = (void*)get_zeroed_page(GFP_KERNEL);
3051 if (lm_root == NULL)
3054 lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
3056 vcpu->arch.mmu.lm_root = lm_root;
3059 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
3065 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3067 if (vcpu->arch.mmu.direct_map)
3068 return mmu_alloc_direct_roots(vcpu);
3070 return mmu_alloc_shadow_roots(vcpu);
3073 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
3076 struct kvm_mmu_page *sp;
3078 if (vcpu->arch.mmu.direct_map)
3081 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3084 vcpu_clear_mmio_info(vcpu, ~0ul);
3085 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3086 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3087 hpa_t root = vcpu->arch.mmu.root_hpa;
3088 sp = page_header(root);
3089 mmu_sync_children(vcpu, sp);
3090 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3093 for (i = 0; i < 4; ++i) {
3094 hpa_t root = vcpu->arch.mmu.pae_root[i];
3096 if (root && VALID_PAGE(root)) {
3097 root &= PT64_BASE_ADDR_MASK;
3098 sp = page_header(root);
3099 mmu_sync_children(vcpu, sp);
3102 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3105 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3107 spin_lock(&vcpu->kvm->mmu_lock);
3108 mmu_sync_roots(vcpu);
3109 spin_unlock(&vcpu->kvm->mmu_lock);
3112 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
3113 u32 access, struct x86_exception *exception)
3116 exception->error_code = 0;
3120 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
3122 struct x86_exception *exception)
3125 exception->error_code = 0;
3126 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access);
3129 static bool quickly_check_mmio_pf(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3132 return vcpu_match_mmio_gpa(vcpu, addr);
3134 return vcpu_match_mmio_gva(vcpu, addr);
3139 * On direct hosts, the last spte is only allows two states
3140 * for mmio page fault:
3141 * - It is the mmio spte
3142 * - It is zapped or it is being zapped.
3144 * This function completely checks the spte when the last spte
3145 * is not the mmio spte.
3147 static bool check_direct_spte_mmio_pf(u64 spte)
3149 return __check_direct_spte_mmio_pf(spte);
3152 static u64 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr)
3154 struct kvm_shadow_walk_iterator iterator;
3157 walk_shadow_page_lockless_begin(vcpu);
3158 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte)
3159 if (!is_shadow_present_pte(spte))
3161 walk_shadow_page_lockless_end(vcpu);
3167 * If it is a real mmio page fault, return 1 and emulat the instruction
3168 * directly, return 0 to let CPU fault again on the address, -1 is
3169 * returned if bug is detected.
3171 int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3175 if (quickly_check_mmio_pf(vcpu, addr, direct))
3178 spte = walk_shadow_page_get_mmio_spte(vcpu, addr);
3180 if (is_mmio_spte(spte)) {
3181 gfn_t gfn = get_mmio_spte_gfn(spte);
3182 unsigned access = get_mmio_spte_access(spte);
3187 trace_handle_mmio_page_fault(addr, gfn, access);
3188 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3193 * It's ok if the gva is remapped by other cpus on shadow guest,
3194 * it's a BUG if the gfn is not a mmio page.
3196 if (direct && !check_direct_spte_mmio_pf(spte))
3200 * If the page table is zapped by other cpus, let CPU fault again on
3205 EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common);
3207 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr,
3208 u32 error_code, bool direct)
3212 ret = handle_mmio_page_fault_common(vcpu, addr, direct);
3217 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3218 u32 error_code, bool prefault)
3223 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
3225 if (unlikely(error_code & PFERR_RSVD_MASK))
3226 return handle_mmio_page_fault(vcpu, gva, error_code, true);
3228 r = mmu_topup_memory_caches(vcpu);
3233 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3235 gfn = gva >> PAGE_SHIFT;
3237 return nonpaging_map(vcpu, gva & PAGE_MASK,
3238 error_code, gfn, prefault);
3241 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
3243 struct kvm_arch_async_pf arch;
3245 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3247 arch.direct_map = vcpu->arch.mmu.direct_map;
3248 arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
3250 return kvm_setup_async_pf(vcpu, gva, gfn, &arch);
3253 static bool can_do_async_pf(struct kvm_vcpu *vcpu)
3255 if (unlikely(!irqchip_in_kernel(vcpu->kvm) ||
3256 kvm_event_needs_reinjection(vcpu)))
3259 return kvm_x86_ops->interrupt_allowed(vcpu);
3262 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3263 gva_t gva, pfn_t *pfn, bool write, bool *writable)
3267 *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable);
3270 return false; /* *pfn has correct page already */
3272 if (!prefault && can_do_async_pf(vcpu)) {
3273 trace_kvm_try_async_get_page(gva, gfn);
3274 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3275 trace_kvm_async_pf_doublefault(gva, gfn);
3276 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3278 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
3282 *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable);
3287 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
3294 gfn_t gfn = gpa >> PAGE_SHIFT;
3295 unsigned long mmu_seq;
3296 int write = error_code & PFERR_WRITE_MASK;
3300 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3302 if (unlikely(error_code & PFERR_RSVD_MASK))
3303 return handle_mmio_page_fault(vcpu, gpa, error_code, true);
3305 r = mmu_topup_memory_caches(vcpu);
3309 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
3310 if (likely(!force_pt_level)) {
3311 level = mapping_level(vcpu, gfn);
3312 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3314 level = PT_PAGE_TABLE_LEVEL;
3316 if (fast_page_fault(vcpu, gpa, level, error_code))
3319 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3322 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3325 if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
3328 spin_lock(&vcpu->kvm->mmu_lock);
3329 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3331 kvm_mmu_free_some_pages(vcpu);
3332 if (likely(!force_pt_level))
3333 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3334 r = __direct_map(vcpu, gpa, write, map_writable,
3335 level, gfn, pfn, prefault);
3336 spin_unlock(&vcpu->kvm->mmu_lock);
3341 spin_unlock(&vcpu->kvm->mmu_lock);
3342 kvm_release_pfn_clean(pfn);
3346 static void nonpaging_free(struct kvm_vcpu *vcpu)
3348 mmu_free_roots(vcpu);
3351 static int nonpaging_init_context(struct kvm_vcpu *vcpu,
3352 struct kvm_mmu *context)
3354 context->new_cr3 = nonpaging_new_cr3;
3355 context->page_fault = nonpaging_page_fault;
3356 context->gva_to_gpa = nonpaging_gva_to_gpa;
3357 context->free = nonpaging_free;
3358 context->sync_page = nonpaging_sync_page;
3359 context->invlpg = nonpaging_invlpg;
3360 context->update_pte = nonpaging_update_pte;
3361 context->root_level = 0;
3362 context->shadow_root_level = PT32E_ROOT_LEVEL;
3363 context->root_hpa = INVALID_PAGE;
3364 context->direct_map = true;
3365 context->nx = false;
3369 void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3371 ++vcpu->stat.tlb_flush;
3372 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
3375 static void paging_new_cr3(struct kvm_vcpu *vcpu)
3377 pgprintk("%s: cr3 %lx\n", __func__, kvm_read_cr3(vcpu));
3378 mmu_free_roots(vcpu);
3381 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3383 return kvm_read_cr3(vcpu);
3386 static void inject_page_fault(struct kvm_vcpu *vcpu,
3387 struct x86_exception *fault)
3389 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
3392 static void paging_free(struct kvm_vcpu *vcpu)
3394 nonpaging_free(vcpu);
3397 static inline void protect_clean_gpte(unsigned *access, unsigned gpte)
3401 BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK);
3403 mask = (unsigned)~ACC_WRITE_MASK;
3404 /* Allow write access to dirty gptes */
3405 mask |= (gpte >> (PT_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) & PT_WRITABLE_MASK;
3409 static bool sync_mmio_spte(u64 *sptep, gfn_t gfn, unsigned access,
3412 if (unlikely(is_mmio_spte(*sptep))) {
3413 if (gfn != get_mmio_spte_gfn(*sptep)) {
3414 mmu_spte_clear_no_track(sptep);
3419 mark_mmio_spte(sptep, gfn, access);
3426 static inline unsigned gpte_access(struct kvm_vcpu *vcpu, u64 gpte)
3430 access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
3431 access &= ~(gpte >> PT64_NX_SHIFT);
3436 static inline bool is_last_gpte(struct kvm_mmu *mmu, unsigned level, unsigned gpte)
3441 index |= (gpte & PT_PAGE_SIZE_MASK) >> (PT_PAGE_SIZE_SHIFT - 2);
3442 return mmu->last_pte_bitmap & (1 << index);
3446 #include "paging_tmpl.h"
3450 #include "paging_tmpl.h"
3453 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3454 struct kvm_mmu *context)
3456 int maxphyaddr = cpuid_maxphyaddr(vcpu);
3457 u64 exb_bit_rsvd = 0;
3460 exb_bit_rsvd = rsvd_bits(63, 63);
3461 switch (context->root_level) {
3462 case PT32_ROOT_LEVEL:
3463 /* no rsvd bits for 2 level 4K page table entries */
3464 context->rsvd_bits_mask[0][1] = 0;
3465 context->rsvd_bits_mask[0][0] = 0;
3466 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3468 if (!is_pse(vcpu)) {
3469 context->rsvd_bits_mask[1][1] = 0;
3473 if (is_cpuid_PSE36())
3474 /* 36bits PSE 4MB page */
3475 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
3477 /* 32 bits PSE 4MB page */
3478 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
3480 case PT32E_ROOT_LEVEL:
3481 context->rsvd_bits_mask[0][2] =
3482 rsvd_bits(maxphyaddr, 63) |
3483 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
3484 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3485 rsvd_bits(maxphyaddr, 62); /* PDE */
3486 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3487 rsvd_bits(maxphyaddr, 62); /* PTE */
3488 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3489 rsvd_bits(maxphyaddr, 62) |
3490 rsvd_bits(13, 20); /* large page */
3491 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3493 case PT64_ROOT_LEVEL:
3494 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
3495 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3496 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
3497 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3498 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3499 rsvd_bits(maxphyaddr, 51);
3500 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3501 rsvd_bits(maxphyaddr, 51);
3502 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
3503 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
3504 rsvd_bits(maxphyaddr, 51) |
3506 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3507 rsvd_bits(maxphyaddr, 51) |
3508 rsvd_bits(13, 20); /* large page */
3509 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3514 static void update_permission_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
3516 unsigned bit, byte, pfec;
3518 bool fault, x, w, u, wf, uf, ff, smep;
3520 smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3521 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
3524 wf = pfec & PFERR_WRITE_MASK;
3525 uf = pfec & PFERR_USER_MASK;
3526 ff = pfec & PFERR_FETCH_MASK;
3527 for (bit = 0; bit < 8; ++bit) {
3528 x = bit & ACC_EXEC_MASK;
3529 w = bit & ACC_WRITE_MASK;
3530 u = bit & ACC_USER_MASK;
3532 /* Not really needed: !nx will cause pte.nx to fault */
3534 /* Allow supervisor writes if !cr0.wp */
3535 w |= !is_write_protection(vcpu) && !uf;
3536 /* Disallow supervisor fetches of user code if cr4.smep */
3537 x &= !(smep && u && !uf);
3539 fault = (ff && !x) || (uf && !u) || (wf && !w);
3540 map |= fault << bit;
3542 mmu->permissions[byte] = map;
3546 static void update_last_pte_bitmap(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
3549 unsigned level, root_level = mmu->root_level;
3550 const unsigned ps_set_index = 1 << 2; /* bit 2 of index: ps */
3552 if (root_level == PT32E_ROOT_LEVEL)
3554 /* PT_PAGE_TABLE_LEVEL always terminates */
3555 map = 1 | (1 << ps_set_index);
3556 for (level = PT_DIRECTORY_LEVEL; level <= root_level; ++level) {
3557 if (level <= PT_PDPE_LEVEL
3558 && (mmu->root_level >= PT32E_ROOT_LEVEL || is_pse(vcpu)))
3559 map |= 1 << (ps_set_index | (level - 1));
3561 mmu->last_pte_bitmap = map;
3564 static int paging64_init_context_common(struct kvm_vcpu *vcpu,
3565 struct kvm_mmu *context,
3568 context->nx = is_nx(vcpu);
3569 context->root_level = level;
3571 reset_rsvds_bits_mask(vcpu, context);
3572 update_permission_bitmask(vcpu, context);
3573 update_last_pte_bitmap(vcpu, context);
3575 ASSERT(is_pae(vcpu));
3576 context->new_cr3 = paging_new_cr3;
3577 context->page_fault = paging64_page_fault;
3578 context->gva_to_gpa = paging64_gva_to_gpa;
3579 context->sync_page = paging64_sync_page;
3580 context->invlpg = paging64_invlpg;
3581 context->update_pte = paging64_update_pte;
3582 context->free = paging_free;
3583 context->shadow_root_level = level;
3584 context->root_hpa = INVALID_PAGE;
3585 context->direct_map = false;
3589 static int paging64_init_context(struct kvm_vcpu *vcpu,
3590 struct kvm_mmu *context)
3592 return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
3595 static int paging32_init_context(struct kvm_vcpu *vcpu,
3596 struct kvm_mmu *context)
3598 context->nx = false;
3599 context->root_level = PT32_ROOT_LEVEL;
3601 reset_rsvds_bits_mask(vcpu, context);
3602 update_permission_bitmask(vcpu, context);
3603 update_last_pte_bitmap(vcpu, context);
3605 context->new_cr3 = paging_new_cr3;
3606 context->page_fault = paging32_page_fault;
3607 context->gva_to_gpa = paging32_gva_to_gpa;
3608 context->free = paging_free;
3609 context->sync_page = paging32_sync_page;
3610 context->invlpg = paging32_invlpg;
3611 context->update_pte = paging32_update_pte;
3612 context->shadow_root_level = PT32E_ROOT_LEVEL;
3613 context->root_hpa = INVALID_PAGE;
3614 context->direct_map = false;
3618 static int paging32E_init_context(struct kvm_vcpu *vcpu,
3619 struct kvm_mmu *context)
3621 return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
3624 static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
3626 struct kvm_mmu *context = vcpu->arch.walk_mmu;
3628 context->base_role.word = 0;
3629 context->new_cr3 = nonpaging_new_cr3;
3630 context->page_fault = tdp_page_fault;
3631 context->free = nonpaging_free;
3632 context->sync_page = nonpaging_sync_page;
3633 context->invlpg = nonpaging_invlpg;
3634 context->update_pte = nonpaging_update_pte;
3635 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
3636 context->root_hpa = INVALID_PAGE;
3637 context->direct_map = true;
3638 context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
3639 context->get_cr3 = get_cr3;
3640 context->get_pdptr = kvm_pdptr_read;
3641 context->inject_page_fault = kvm_inject_page_fault;
3643 if (!is_paging(vcpu)) {
3644 context->nx = false;
3645 context->gva_to_gpa = nonpaging_gva_to_gpa;
3646 context->root_level = 0;
3647 } else if (is_long_mode(vcpu)) {
3648 context->nx = is_nx(vcpu);
3649 context->root_level = PT64_ROOT_LEVEL;
3650 reset_rsvds_bits_mask(vcpu, context);
3651 context->gva_to_gpa = paging64_gva_to_gpa;
3652 } else if (is_pae(vcpu)) {
3653 context->nx = is_nx(vcpu);
3654 context->root_level = PT32E_ROOT_LEVEL;
3655 reset_rsvds_bits_mask(vcpu, context);
3656 context->gva_to_gpa = paging64_gva_to_gpa;
3658 context->nx = false;
3659 context->root_level = PT32_ROOT_LEVEL;
3660 reset_rsvds_bits_mask(vcpu, context);
3661 context->gva_to_gpa = paging32_gva_to_gpa;
3664 update_permission_bitmask(vcpu, context);
3665 update_last_pte_bitmap(vcpu, context);
3670 int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
3673 bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3675 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3677 if (!is_paging(vcpu))
3678 r = nonpaging_init_context(vcpu, context);
3679 else if (is_long_mode(vcpu))
3680 r = paging64_init_context(vcpu, context);
3681 else if (is_pae(vcpu))
3682 r = paging32E_init_context(vcpu, context);
3684 r = paging32_init_context(vcpu, context);
3686 vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu);
3687 vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu);
3688 vcpu->arch.mmu.base_role.smep_andnot_wp
3689 = smep && !is_write_protection(vcpu);
3693 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
3695 static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
3697 int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu);
3699 vcpu->arch.walk_mmu->set_cr3 = kvm_x86_ops->set_cr3;
3700 vcpu->arch.walk_mmu->get_cr3 = get_cr3;
3701 vcpu->arch.walk_mmu->get_pdptr = kvm_pdptr_read;
3702 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
3707 static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
3709 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
3711 g_context->get_cr3 = get_cr3;
3712 g_context->get_pdptr = kvm_pdptr_read;
3713 g_context->inject_page_fault = kvm_inject_page_fault;
3716 * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The
3717 * translation of l2_gpa to l1_gpa addresses is done using the
3718 * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa
3719 * functions between mmu and nested_mmu are swapped.
3721 if (!is_paging(vcpu)) {
3722 g_context->nx = false;
3723 g_context->root_level = 0;
3724 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
3725 } else if (is_long_mode(vcpu)) {
3726 g_context->nx = is_nx(vcpu);
3727 g_context->root_level = PT64_ROOT_LEVEL;
3728 reset_rsvds_bits_mask(vcpu, g_context);
3729 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3730 } else if (is_pae(vcpu)) {
3731 g_context->nx = is_nx(vcpu);
3732 g_context->root_level = PT32E_ROOT_LEVEL;
3733 reset_rsvds_bits_mask(vcpu, g_context);
3734 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3736 g_context->nx = false;
3737 g_context->root_level = PT32_ROOT_LEVEL;
3738 reset_rsvds_bits_mask(vcpu, g_context);
3739 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
3742 update_permission_bitmask(vcpu, g_context);
3743 update_last_pte_bitmap(vcpu, g_context);
3748 static int init_kvm_mmu(struct kvm_vcpu *vcpu)
3750 if (mmu_is_nested(vcpu))
3751 return init_kvm_nested_mmu(vcpu);
3752 else if (tdp_enabled)
3753 return init_kvm_tdp_mmu(vcpu);
3755 return init_kvm_softmmu(vcpu);
3758 static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
3761 if (VALID_PAGE(vcpu->arch.mmu.root_hpa))
3762 /* mmu.free() should set root_hpa = INVALID_PAGE */
3763 vcpu->arch.mmu.free(vcpu);
3766 int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
3768 destroy_kvm_mmu(vcpu);
3769 return init_kvm_mmu(vcpu);
3771 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
3773 int kvm_mmu_load(struct kvm_vcpu *vcpu)
3777 r = mmu_topup_memory_caches(vcpu);
3780 r = mmu_alloc_roots(vcpu);
3781 spin_lock(&vcpu->kvm->mmu_lock);
3782 mmu_sync_roots(vcpu);
3783 spin_unlock(&vcpu->kvm->mmu_lock);
3786 /* set_cr3() should ensure TLB has been flushed */
3787 vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
3791 EXPORT_SYMBOL_GPL(kvm_mmu_load);
3793 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
3795 mmu_free_roots(vcpu);
3797 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
3799 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
3800 struct kvm_mmu_page *sp, u64 *spte,
3803 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
3804 ++vcpu->kvm->stat.mmu_pde_zapped;
3808 ++vcpu->kvm->stat.mmu_pte_updated;
3809 vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
3812 static bool need_remote_flush(u64 old, u64 new)
3814 if (!is_shadow_present_pte(old))
3816 if (!is_shadow_present_pte(new))
3818 if ((old ^ new) & PT64_BASE_ADDR_MASK)
3820 old ^= PT64_NX_MASK;
3821 new ^= PT64_NX_MASK;
3822 return (old & ~new & PT64_PERM_MASK) != 0;
3825 static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page,
3826 bool remote_flush, bool local_flush)
3832 kvm_flush_remote_tlbs(vcpu->kvm);
3833 else if (local_flush)
3834 kvm_mmu_flush_tlb(vcpu);
3837 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
3838 const u8 *new, int *bytes)
3844 * Assume that the pte write on a page table of the same type
3845 * as the current vcpu paging mode since we update the sptes only
3846 * when they have the same mode.
3848 if (is_pae(vcpu) && *bytes == 4) {
3849 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
3852 r = kvm_read_guest(vcpu->kvm, *gpa, &gentry, min(*bytes, 8));
3855 new = (const u8 *)&gentry;
3860 gentry = *(const u32 *)new;
3863 gentry = *(const u64 *)new;
3874 * If we're seeing too many writes to a page, it may no longer be a page table,
3875 * or we may be forking, in which case it is better to unmap the page.
3877 static bool detect_write_flooding(struct kvm_mmu_page *sp)
3880 * Skip write-flooding detected for the sp whose level is 1, because
3881 * it can become unsync, then the guest page is not write-protected.
3883 if (sp->role.level == PT_PAGE_TABLE_LEVEL)
3886 return ++sp->write_flooding_count >= 3;
3890 * Misaligned accesses are too much trouble to fix up; also, they usually
3891 * indicate a page is not used as a page table.
3893 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
3896 unsigned offset, pte_size, misaligned;
3898 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
3899 gpa, bytes, sp->role.word);
3901 offset = offset_in_page(gpa);
3902 pte_size = sp->role.cr4_pae ? 8 : 4;
3905 * Sometimes, the OS only writes the last one bytes to update status
3906 * bits, for example, in linux, andb instruction is used in clear_bit().
3908 if (!(offset & (pte_size - 1)) && bytes == 1)
3911 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
3912 misaligned |= bytes < 4;
3917 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
3919 unsigned page_offset, quadrant;
3923 page_offset = offset_in_page(gpa);
3924 level = sp->role.level;
3926 if (!sp->role.cr4_pae) {
3927 page_offset <<= 1; /* 32->64 */
3929 * A 32-bit pde maps 4MB while the shadow pdes map
3930 * only 2MB. So we need to double the offset again
3931 * and zap two pdes instead of one.
3933 if (level == PT32_ROOT_LEVEL) {
3934 page_offset &= ~7; /* kill rounding error */
3938 quadrant = page_offset >> PAGE_SHIFT;
3939 page_offset &= ~PAGE_MASK;
3940 if (quadrant != sp->role.quadrant)
3944 spte = &sp->spt[page_offset / sizeof(*spte)];
3948 void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
3949 const u8 *new, int bytes)
3951 gfn_t gfn = gpa >> PAGE_SHIFT;
3952 union kvm_mmu_page_role mask = { .word = 0 };
3953 struct kvm_mmu_page *sp;
3954 struct hlist_node *node;
3955 LIST_HEAD(invalid_list);
3956 u64 entry, gentry, *spte;
3958 bool remote_flush, local_flush, zap_page;
3961 * If we don't have indirect shadow pages, it means no page is
3962 * write-protected, so we can exit simply.
3964 if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
3967 zap_page = remote_flush = local_flush = false;
3969 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
3971 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes);
3974 * No need to care whether allocation memory is successful
3975 * or not since pte prefetch is skiped if it does not have
3976 * enough objects in the cache.
3978 mmu_topup_memory_caches(vcpu);
3980 spin_lock(&vcpu->kvm->mmu_lock);
3981 ++vcpu->kvm->stat.mmu_pte_write;
3982 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
3984 mask.cr0_wp = mask.cr4_pae = mask.nxe = 1;
3985 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) {
3986 if (detect_write_misaligned(sp, gpa, bytes) ||
3987 detect_write_flooding(sp)) {
3988 zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
3990 ++vcpu->kvm->stat.mmu_flooded;
3994 spte = get_written_sptes(sp, gpa, &npte);
4001 mmu_page_zap_pte(vcpu->kvm, sp, spte);
4003 !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
4004 & mask.word) && rmap_can_add(vcpu))
4005 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
4006 if (!remote_flush && need_remote_flush(entry, *spte))
4007 remote_flush = true;
4011 mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush);
4012 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
4013 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
4014 spin_unlock(&vcpu->kvm->mmu_lock);
4017 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
4022 if (vcpu->arch.mmu.direct_map)
4025 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
4027 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4031 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
4033 void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
4035 LIST_HEAD(invalid_list);
4037 while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES &&
4038 !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
4039 struct kvm_mmu_page *sp;
4041 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
4042 struct kvm_mmu_page, link);
4043 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
4044 ++vcpu->kvm->stat.mmu_recycled;
4046 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
4049 static bool is_mmio_page_fault(struct kvm_vcpu *vcpu, gva_t addr)
4051 if (vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu))
4052 return vcpu_match_mmio_gpa(vcpu, addr);
4054 return vcpu_match_mmio_gva(vcpu, addr);
4057 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code,
4058 void *insn, int insn_len)
4060 int r, emulation_type = EMULTYPE_RETRY;
4061 enum emulation_result er;
4063 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false);
4072 if (is_mmio_page_fault(vcpu, cr2))
4075 er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len);
4080 case EMULATE_DO_MMIO:
4081 ++vcpu->stat.mmio_exits;
4091 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
4093 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
4095 vcpu->arch.mmu.invlpg(vcpu, gva);
4096 kvm_mmu_flush_tlb(vcpu);
4097 ++vcpu->stat.invlpg;
4099 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
4101 void kvm_enable_tdp(void)
4105 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
4107 void kvm_disable_tdp(void)
4109 tdp_enabled = false;
4111 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
4113 static void free_mmu_pages(struct kvm_vcpu *vcpu)
4115 free_page((unsigned long)vcpu->arch.mmu.pae_root);
4116 if (vcpu->arch.mmu.lm_root != NULL)
4117 free_page((unsigned long)vcpu->arch.mmu.lm_root);
4120 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
4128 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
4129 * Therefore we need to allocate shadow page tables in the first
4130 * 4GB of memory, which happens to fit the DMA32 zone.
4132 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
4136 vcpu->arch.mmu.pae_root = page_address(page);
4137 for (i = 0; i < 4; ++i)
4138 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
4143 int kvm_mmu_create(struct kvm_vcpu *vcpu)
4147 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
4148 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
4149 vcpu->arch.mmu.translate_gpa = translate_gpa;
4150 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
4152 return alloc_mmu_pages(vcpu);
4155 int kvm_mmu_setup(struct kvm_vcpu *vcpu)
4158 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
4160 return init_kvm_mmu(vcpu);
4163 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
4165 struct kvm_memory_slot *memslot;
4169 memslot = id_to_memslot(kvm->memslots, slot);
4170 last_gfn = memslot->base_gfn + memslot->npages - 1;
4172 for (i = PT_PAGE_TABLE_LEVEL;
4173 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
4174 unsigned long *rmapp;
4175 unsigned long last_index, index;
4177 rmapp = memslot->arch.rmap[i - PT_PAGE_TABLE_LEVEL];
4178 last_index = gfn_to_index(last_gfn, memslot->base_gfn, i);
4180 for (index = 0; index <= last_index; ++index, ++rmapp) {
4182 __rmap_write_protect(kvm, rmapp, false);
4186 kvm_flush_remote_tlbs(kvm);
4189 void kvm_mmu_zap_all(struct kvm *kvm)
4191 struct kvm_mmu_page *sp, *node;
4192 LIST_HEAD(invalid_list);
4194 spin_lock(&kvm->mmu_lock);
4196 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
4197 if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list))
4200 kvm_mmu_commit_zap_page(kvm, &invalid_list);
4201 spin_unlock(&kvm->mmu_lock);
4204 static void kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm,
4205 struct list_head *invalid_list)
4207 struct kvm_mmu_page *page;
4209 if (list_empty(&kvm->arch.active_mmu_pages))
4212 page = container_of(kvm->arch.active_mmu_pages.prev,
4213 struct kvm_mmu_page, link);
4214 kvm_mmu_prepare_zap_page(kvm, page, invalid_list);
4217 static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc)
4220 int nr_to_scan = sc->nr_to_scan;
4222 if (nr_to_scan == 0)
4225 raw_spin_lock(&kvm_lock);
4227 list_for_each_entry(kvm, &vm_list, vm_list) {
4229 LIST_HEAD(invalid_list);
4232 * Never scan more than sc->nr_to_scan VM instances.
4233 * Will not hit this condition practically since we do not try
4234 * to shrink more than one VM and it is very unlikely to see
4235 * !n_used_mmu_pages so many times.
4240 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
4241 * here. We may skip a VM instance errorneosly, but we do not
4242 * want to shrink a VM that only started to populate its MMU
4245 if (!kvm->arch.n_used_mmu_pages)
4248 idx = srcu_read_lock(&kvm->srcu);
4249 spin_lock(&kvm->mmu_lock);
4251 kvm_mmu_remove_some_alloc_mmu_pages(kvm, &invalid_list);
4252 kvm_mmu_commit_zap_page(kvm, &invalid_list);
4254 spin_unlock(&kvm->mmu_lock);
4255 srcu_read_unlock(&kvm->srcu, idx);
4257 list_move_tail(&kvm->vm_list, &vm_list);
4261 raw_spin_unlock(&kvm_lock);
4264 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
4267 static struct shrinker mmu_shrinker = {
4268 .shrink = mmu_shrink,
4269 .seeks = DEFAULT_SEEKS * 10,
4272 static void mmu_destroy_caches(void)
4274 if (pte_list_desc_cache)
4275 kmem_cache_destroy(pte_list_desc_cache);
4276 if (mmu_page_header_cache)
4277 kmem_cache_destroy(mmu_page_header_cache);
4280 int kvm_mmu_module_init(void)
4282 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
4283 sizeof(struct pte_list_desc),
4285 if (!pte_list_desc_cache)
4288 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
4289 sizeof(struct kvm_mmu_page),
4291 if (!mmu_page_header_cache)
4294 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0))
4297 register_shrinker(&mmu_shrinker);
4302 mmu_destroy_caches();
4307 * Caculate mmu pages needed for kvm.
4309 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
4311 unsigned int nr_mmu_pages;
4312 unsigned int nr_pages = 0;
4313 struct kvm_memslots *slots;
4314 struct kvm_memory_slot *memslot;
4316 slots = kvm_memslots(kvm);
4318 kvm_for_each_memslot(memslot, slots)
4319 nr_pages += memslot->npages;
4321 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
4322 nr_mmu_pages = max(nr_mmu_pages,
4323 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
4325 return nr_mmu_pages;
4328 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
4330 struct kvm_shadow_walk_iterator iterator;
4334 walk_shadow_page_lockless_begin(vcpu);
4335 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
4336 sptes[iterator.level-1] = spte;
4338 if (!is_shadow_present_pte(spte))
4341 walk_shadow_page_lockless_end(vcpu);
4345 EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
4347 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
4351 destroy_kvm_mmu(vcpu);
4352 free_mmu_pages(vcpu);
4353 mmu_free_memory_caches(vcpu);
4356 void kvm_mmu_module_exit(void)
4358 mmu_destroy_caches();
4359 percpu_counter_destroy(&kvm_total_used_mmu_pages);
4360 unregister_shrinker(&mmu_shrinker);
4361 mmu_audit_disable();