2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
27 #include <linux/kvm_host.h>
28 #include <linux/types.h>
29 #include <linux/string.h>
31 #include <linux/highmem.h>
32 #include <linux/module.h>
33 #include <linux/swap.h>
34 #include <linux/hugetlb.h>
35 #include <linux/compiler.h>
36 #include <linux/srcu.h>
37 #include <linux/slab.h>
38 #include <linux/uaccess.h>
41 #include <asm/cmpxchg.h>
46 * When setting this variable to true it enables Two-Dimensional-Paging
47 * where the hardware walks 2 page tables:
48 * 1. the guest-virtual to guest-physical
49 * 2. while doing 1. it walks guest-physical to host-physical
50 * If the hardware supports that we don't need to do shadow paging.
52 bool tdp_enabled = false;
56 AUDIT_POST_PAGE_FAULT,
63 char *audit_point_name[] = {
76 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
77 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
81 #define pgprintk(x...) do { } while (0)
82 #define rmap_printk(x...) do { } while (0)
88 module_param(dbg, bool, 0644);
91 static int oos_shadow = 1;
92 module_param(oos_shadow, bool, 0644);
95 #define ASSERT(x) do { } while (0)
99 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
100 __FILE__, __LINE__, #x); \
104 #define PTE_PREFETCH_NUM 8
106 #define PT_FIRST_AVAIL_BITS_SHIFT 9
107 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
109 #define PT64_LEVEL_BITS 9
111 #define PT64_LEVEL_SHIFT(level) \
112 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
114 #define PT64_INDEX(address, level)\
115 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
118 #define PT32_LEVEL_BITS 10
120 #define PT32_LEVEL_SHIFT(level) \
121 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
123 #define PT32_LVL_OFFSET_MASK(level) \
124 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
125 * PT32_LEVEL_BITS))) - 1))
127 #define PT32_INDEX(address, level)\
128 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
131 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
132 #define PT64_DIR_BASE_ADDR_MASK \
133 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
134 #define PT64_LVL_ADDR_MASK(level) \
135 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
136 * PT64_LEVEL_BITS))) - 1))
137 #define PT64_LVL_OFFSET_MASK(level) \
138 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
139 * PT64_LEVEL_BITS))) - 1))
141 #define PT32_BASE_ADDR_MASK PAGE_MASK
142 #define PT32_DIR_BASE_ADDR_MASK \
143 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
144 #define PT32_LVL_ADDR_MASK(level) \
145 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
146 * PT32_LEVEL_BITS))) - 1))
148 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
151 #define PTE_LIST_EXT 4
153 #define ACC_EXEC_MASK 1
154 #define ACC_WRITE_MASK PT_WRITABLE_MASK
155 #define ACC_USER_MASK PT_USER_MASK
156 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
158 #include <trace/events/kvm.h>
160 #define CREATE_TRACE_POINTS
161 #include "mmutrace.h"
163 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
165 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
167 struct pte_list_desc {
168 u64 *sptes[PTE_LIST_EXT];
169 struct pte_list_desc *more;
172 struct kvm_shadow_walk_iterator {
180 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
181 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
182 shadow_walk_okay(&(_walker)); \
183 shadow_walk_next(&(_walker)))
185 static struct kmem_cache *pte_list_desc_cache;
186 static struct kmem_cache *mmu_page_header_cache;
187 static struct percpu_counter kvm_total_used_mmu_pages;
189 static u64 __read_mostly shadow_trap_nonpresent_pte;
190 static u64 __read_mostly shadow_notrap_nonpresent_pte;
191 static u64 __read_mostly shadow_nx_mask;
192 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
193 static u64 __read_mostly shadow_user_mask;
194 static u64 __read_mostly shadow_accessed_mask;
195 static u64 __read_mostly shadow_dirty_mask;
197 static inline u64 rsvd_bits(int s, int e)
199 return ((1ULL << (e - s + 1)) - 1) << s;
202 void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte)
204 shadow_trap_nonpresent_pte = trap_pte;
205 shadow_notrap_nonpresent_pte = notrap_pte;
207 EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes);
209 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
210 u64 dirty_mask, u64 nx_mask, u64 x_mask)
212 shadow_user_mask = user_mask;
213 shadow_accessed_mask = accessed_mask;
214 shadow_dirty_mask = dirty_mask;
215 shadow_nx_mask = nx_mask;
216 shadow_x_mask = x_mask;
218 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
220 static int is_cpuid_PSE36(void)
225 static int is_nx(struct kvm_vcpu *vcpu)
227 return vcpu->arch.efer & EFER_NX;
230 static int is_shadow_present_pte(u64 pte)
232 return pte != shadow_trap_nonpresent_pte
233 && pte != shadow_notrap_nonpresent_pte;
236 static int is_large_pte(u64 pte)
238 return pte & PT_PAGE_SIZE_MASK;
241 static int is_dirty_gpte(unsigned long pte)
243 return pte & PT_DIRTY_MASK;
246 static int is_rmap_spte(u64 pte)
248 return is_shadow_present_pte(pte);
251 static int is_last_spte(u64 pte, int level)
253 if (level == PT_PAGE_TABLE_LEVEL)
255 if (is_large_pte(pte))
260 static pfn_t spte_to_pfn(u64 pte)
262 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
265 static gfn_t pse36_gfn_delta(u32 gpte)
267 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
269 return (gpte & PT32_DIR_PSE36_MASK) << shift;
272 static void __set_spte(u64 *sptep, u64 spte)
274 set_64bit(sptep, spte);
277 static u64 __xchg_spte(u64 *sptep, u64 new_spte)
280 return xchg(sptep, new_spte);
286 } while (cmpxchg64(sptep, old_spte, new_spte) != old_spte);
292 static bool spte_has_volatile_bits(u64 spte)
294 if (!shadow_accessed_mask)
297 if (!is_shadow_present_pte(spte))
300 if ((spte & shadow_accessed_mask) &&
301 (!is_writable_pte(spte) || (spte & shadow_dirty_mask)))
307 static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask)
309 return (old_spte & bit_mask) && !(new_spte & bit_mask);
312 static void update_spte(u64 *sptep, u64 new_spte)
314 u64 mask, old_spte = *sptep;
316 WARN_ON(!is_rmap_spte(new_spte));
318 new_spte |= old_spte & shadow_dirty_mask;
320 mask = shadow_accessed_mask;
321 if (is_writable_pte(old_spte))
322 mask |= shadow_dirty_mask;
324 if (!spte_has_volatile_bits(old_spte) || (new_spte & mask) == mask)
325 __set_spte(sptep, new_spte);
327 old_spte = __xchg_spte(sptep, new_spte);
329 if (!shadow_accessed_mask)
332 if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask))
333 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
334 if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask))
335 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
338 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
339 struct kmem_cache *base_cache, int min)
343 if (cache->nobjs >= min)
345 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
346 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
349 cache->objects[cache->nobjs++] = obj;
354 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
355 struct kmem_cache *cache)
358 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
361 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
366 if (cache->nobjs >= min)
368 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
369 page = (void *)__get_free_page(GFP_KERNEL);
372 cache->objects[cache->nobjs++] = page;
377 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
380 free_page((unsigned long)mc->objects[--mc->nobjs]);
383 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
387 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
388 pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
391 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
394 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
395 mmu_page_header_cache, 4);
400 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
402 mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
403 pte_list_desc_cache);
404 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
405 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
406 mmu_page_header_cache);
409 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
415 p = mc->objects[--mc->nobjs];
419 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
421 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache,
422 sizeof(struct pte_list_desc));
425 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
427 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
430 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
432 if (!sp->role.direct)
433 return sp->gfns[index];
435 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
438 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
441 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
443 sp->gfns[index] = gfn;
447 * Return the pointer to the large page information for a given gfn,
448 * handling slots that are not large page aligned.
450 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
451 struct kvm_memory_slot *slot,
456 idx = (gfn >> KVM_HPAGE_GFN_SHIFT(level)) -
457 (slot->base_gfn >> KVM_HPAGE_GFN_SHIFT(level));
458 return &slot->lpage_info[level - 2][idx];
461 static void account_shadowed(struct kvm *kvm, gfn_t gfn)
463 struct kvm_memory_slot *slot;
464 struct kvm_lpage_info *linfo;
467 slot = gfn_to_memslot(kvm, gfn);
468 for (i = PT_DIRECTORY_LEVEL;
469 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
470 linfo = lpage_info_slot(gfn, slot, i);
471 linfo->write_count += 1;
473 kvm->arch.indirect_shadow_pages++;
476 static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
478 struct kvm_memory_slot *slot;
479 struct kvm_lpage_info *linfo;
482 slot = gfn_to_memslot(kvm, gfn);
483 for (i = PT_DIRECTORY_LEVEL;
484 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
485 linfo = lpage_info_slot(gfn, slot, i);
486 linfo->write_count -= 1;
487 WARN_ON(linfo->write_count < 0);
489 kvm->arch.indirect_shadow_pages--;
492 static int has_wrprotected_page(struct kvm *kvm,
496 struct kvm_memory_slot *slot;
497 struct kvm_lpage_info *linfo;
499 slot = gfn_to_memslot(kvm, gfn);
501 linfo = lpage_info_slot(gfn, slot, level);
502 return linfo->write_count;
508 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
510 unsigned long page_size;
513 page_size = kvm_host_page_size(kvm, gfn);
515 for (i = PT_PAGE_TABLE_LEVEL;
516 i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
517 if (page_size >= KVM_HPAGE_SIZE(i))
526 static struct kvm_memory_slot *
527 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
530 struct kvm_memory_slot *slot;
532 slot = gfn_to_memslot(vcpu->kvm, gfn);
533 if (!slot || slot->flags & KVM_MEMSLOT_INVALID ||
534 (no_dirty_log && slot->dirty_bitmap))
540 static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn)
542 return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true);
545 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
547 int host_level, level, max_level;
549 host_level = host_mapping_level(vcpu->kvm, large_gfn);
551 if (host_level == PT_PAGE_TABLE_LEVEL)
554 max_level = kvm_x86_ops->get_lpage_level() < host_level ?
555 kvm_x86_ops->get_lpage_level() : host_level;
557 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
558 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
565 * Pte mapping structures:
567 * If pte_list bit zero is zero, then pte_list point to the spte.
569 * If pte_list bit zero is one, (then pte_list & ~1) points to a struct
570 * pte_list_desc containing more mappings.
572 * Returns the number of pte entries before the spte was added or zero if
573 * the spte was not added.
576 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
577 unsigned long *pte_list)
579 struct pte_list_desc *desc;
583 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
584 *pte_list = (unsigned long)spte;
585 } else if (!(*pte_list & 1)) {
586 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
587 desc = mmu_alloc_pte_list_desc(vcpu);
588 desc->sptes[0] = (u64 *)*pte_list;
589 desc->sptes[1] = spte;
590 *pte_list = (unsigned long)desc | 1;
593 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
594 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
595 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
597 count += PTE_LIST_EXT;
599 if (desc->sptes[PTE_LIST_EXT-1]) {
600 desc->more = mmu_alloc_pte_list_desc(vcpu);
603 for (i = 0; desc->sptes[i]; ++i)
605 desc->sptes[i] = spte;
610 static u64 *pte_list_next(unsigned long *pte_list, u64 *spte)
612 struct pte_list_desc *desc;
618 else if (!(*pte_list & 1)) {
620 return (u64 *)*pte_list;
623 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
626 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
627 if (prev_spte == spte)
628 return desc->sptes[i];
629 prev_spte = desc->sptes[i];
637 pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc,
638 int i, struct pte_list_desc *prev_desc)
642 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
644 desc->sptes[i] = desc->sptes[j];
645 desc->sptes[j] = NULL;
648 if (!prev_desc && !desc->more)
649 *pte_list = (unsigned long)desc->sptes[0];
652 prev_desc->more = desc->more;
654 *pte_list = (unsigned long)desc->more | 1;
655 mmu_free_pte_list_desc(desc);
658 static void pte_list_remove(u64 *spte, unsigned long *pte_list)
660 struct pte_list_desc *desc;
661 struct pte_list_desc *prev_desc;
665 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
667 } else if (!(*pte_list & 1)) {
668 rmap_printk("pte_list_remove: %p 1->0\n", spte);
669 if ((u64 *)*pte_list != spte) {
670 printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte);
675 rmap_printk("pte_list_remove: %p many->many\n", spte);
676 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
679 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
680 if (desc->sptes[i] == spte) {
681 pte_list_desc_remove_entry(pte_list,
689 pr_err("pte_list_remove: %p many->many\n", spte);
694 typedef void (*pte_list_walk_fn) (u64 *spte);
695 static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn)
697 struct pte_list_desc *desc;
703 if (!(*pte_list & 1))
704 return fn((u64 *)*pte_list);
706 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
708 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
715 * Take gfn and return the reverse mapping to it.
717 static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
719 struct kvm_memory_slot *slot;
720 struct kvm_lpage_info *linfo;
722 slot = gfn_to_memslot(kvm, gfn);
723 if (likely(level == PT_PAGE_TABLE_LEVEL))
724 return &slot->rmap[gfn - slot->base_gfn];
726 linfo = lpage_info_slot(gfn, slot, level);
728 return &linfo->rmap_pde;
731 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
733 struct kvm_mmu_page *sp;
734 unsigned long *rmapp;
736 sp = page_header(__pa(spte));
737 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
738 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
739 return pte_list_add(vcpu, spte, rmapp);
742 static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte)
744 return pte_list_next(rmapp, spte);
747 static void rmap_remove(struct kvm *kvm, u64 *spte)
749 struct kvm_mmu_page *sp;
751 unsigned long *rmapp;
753 sp = page_header(__pa(spte));
754 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
755 rmapp = gfn_to_rmap(kvm, gfn, sp->role.level);
756 pte_list_remove(spte, rmapp);
759 static int set_spte_track_bits(u64 *sptep, u64 new_spte)
762 u64 old_spte = *sptep;
764 if (!spte_has_volatile_bits(old_spte))
765 __set_spte(sptep, new_spte);
767 old_spte = __xchg_spte(sptep, new_spte);
769 if (!is_rmap_spte(old_spte))
772 pfn = spte_to_pfn(old_spte);
773 if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
774 kvm_set_pfn_accessed(pfn);
775 if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask))
776 kvm_set_pfn_dirty(pfn);
780 static void drop_spte(struct kvm *kvm, u64 *sptep, u64 new_spte)
782 if (set_spte_track_bits(sptep, new_spte))
783 rmap_remove(kvm, sptep);
786 static int rmap_write_protect(struct kvm *kvm, u64 gfn)
788 unsigned long *rmapp;
790 int i, write_protected = 0;
792 rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL);
794 spte = rmap_next(kvm, rmapp, NULL);
797 BUG_ON(!(*spte & PT_PRESENT_MASK));
798 rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
799 if (is_writable_pte(*spte)) {
800 update_spte(spte, *spte & ~PT_WRITABLE_MASK);
803 spte = rmap_next(kvm, rmapp, spte);
806 /* check for huge page mappings */
807 for (i = PT_DIRECTORY_LEVEL;
808 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
809 rmapp = gfn_to_rmap(kvm, gfn, i);
810 spte = rmap_next(kvm, rmapp, NULL);
813 BUG_ON(!(*spte & PT_PRESENT_MASK));
814 BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK));
815 pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn);
816 if (is_writable_pte(*spte)) {
818 shadow_trap_nonpresent_pte);
823 spte = rmap_next(kvm, rmapp, spte);
827 return write_protected;
830 static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
834 int need_tlb_flush = 0;
836 while ((spte = rmap_next(kvm, rmapp, NULL))) {
837 BUG_ON(!(*spte & PT_PRESENT_MASK));
838 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte);
839 drop_spte(kvm, spte, shadow_trap_nonpresent_pte);
842 return need_tlb_flush;
845 static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
850 pte_t *ptep = (pte_t *)data;
853 WARN_ON(pte_huge(*ptep));
854 new_pfn = pte_pfn(*ptep);
855 spte = rmap_next(kvm, rmapp, NULL);
857 BUG_ON(!is_shadow_present_pte(*spte));
858 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte);
860 if (pte_write(*ptep)) {
861 drop_spte(kvm, spte, shadow_trap_nonpresent_pte);
862 spte = rmap_next(kvm, rmapp, NULL);
864 new_spte = *spte &~ (PT64_BASE_ADDR_MASK);
865 new_spte |= (u64)new_pfn << PAGE_SHIFT;
867 new_spte &= ~PT_WRITABLE_MASK;
868 new_spte &= ~SPTE_HOST_WRITEABLE;
869 new_spte &= ~shadow_accessed_mask;
870 set_spte_track_bits(spte, new_spte);
871 spte = rmap_next(kvm, rmapp, spte);
875 kvm_flush_remote_tlbs(kvm);
880 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
882 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
888 struct kvm_memslots *slots;
890 slots = kvm_memslots(kvm);
892 for (i = 0; i < slots->nmemslots; i++) {
893 struct kvm_memory_slot *memslot = &slots->memslots[i];
894 unsigned long start = memslot->userspace_addr;
897 end = start + (memslot->npages << PAGE_SHIFT);
898 if (hva >= start && hva < end) {
899 gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT;
900 gfn_t gfn = memslot->base_gfn + gfn_offset;
902 ret = handler(kvm, &memslot->rmap[gfn_offset], data);
904 for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) {
905 struct kvm_lpage_info *linfo;
907 linfo = lpage_info_slot(gfn, memslot,
908 PT_DIRECTORY_LEVEL + j);
909 ret |= handler(kvm, &linfo->rmap_pde, data);
911 trace_kvm_age_page(hva, memslot, ret);
919 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
921 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
924 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
926 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
929 static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
936 * Emulate the accessed bit for EPT, by checking if this page has
937 * an EPT mapping, and clearing it if it does. On the next access,
938 * a new EPT mapping will be established.
939 * This has some overhead, but not as much as the cost of swapping
940 * out actively used pages or breaking up actively used hugepages.
942 if (!shadow_accessed_mask)
943 return kvm_unmap_rmapp(kvm, rmapp, data);
945 spte = rmap_next(kvm, rmapp, NULL);
949 BUG_ON(!(_spte & PT_PRESENT_MASK));
950 _young = _spte & PT_ACCESSED_MASK;
953 clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
955 spte = rmap_next(kvm, rmapp, spte);
960 static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
967 * If there's no access bit in the secondary pte set by the
968 * hardware it's up to gup-fast/gup to set the access bit in
969 * the primary pte or in the page structure.
971 if (!shadow_accessed_mask)
974 spte = rmap_next(kvm, rmapp, NULL);
977 BUG_ON(!(_spte & PT_PRESENT_MASK));
978 young = _spte & PT_ACCESSED_MASK;
983 spte = rmap_next(kvm, rmapp, spte);
989 #define RMAP_RECYCLE_THRESHOLD 1000
991 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
993 unsigned long *rmapp;
994 struct kvm_mmu_page *sp;
996 sp = page_header(__pa(spte));
998 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1000 kvm_unmap_rmapp(vcpu->kvm, rmapp, 0);
1001 kvm_flush_remote_tlbs(vcpu->kvm);
1004 int kvm_age_hva(struct kvm *kvm, unsigned long hva)
1006 return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp);
1009 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1011 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1015 static int is_empty_shadow_page(u64 *spt)
1020 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1021 if (is_shadow_present_pte(*pos)) {
1022 printk(KERN_ERR "%s: %p %llx\n", __func__,
1031 * This value is the sum of all of the kvm instances's
1032 * kvm->arch.n_used_mmu_pages values. We need a global,
1033 * aggregate version in order to make the slab shrinker
1036 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1038 kvm->arch.n_used_mmu_pages += nr;
1039 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1042 static void kvm_mmu_free_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1044 ASSERT(is_empty_shadow_page(sp->spt));
1045 hlist_del(&sp->hash_link);
1046 list_del(&sp->link);
1047 free_page((unsigned long)sp->spt);
1048 if (!sp->role.direct)
1049 free_page((unsigned long)sp->gfns);
1050 kmem_cache_free(mmu_page_header_cache, sp);
1051 kvm_mod_used_mmu_pages(kvm, -1);
1054 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1056 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
1059 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1060 struct kvm_mmu_page *sp, u64 *parent_pte)
1065 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1068 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1071 pte_list_remove(parent_pte, &sp->parent_ptes);
1074 static void drop_parent_pte(struct kvm_mmu_page *sp,
1077 mmu_page_remove_parent_pte(sp, parent_pte);
1078 __set_spte(parent_pte, shadow_trap_nonpresent_pte);
1081 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
1082 u64 *parent_pte, int direct)
1084 struct kvm_mmu_page *sp;
1085 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache,
1087 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
1089 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache,
1091 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1092 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1093 bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS);
1094 sp->parent_ptes = 0;
1095 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1096 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1100 static void mark_unsync(u64 *spte);
1101 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1103 pte_list_walk(&sp->parent_ptes, mark_unsync);
1106 static void mark_unsync(u64 *spte)
1108 struct kvm_mmu_page *sp;
1111 sp = page_header(__pa(spte));
1112 index = spte - sp->spt;
1113 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1115 if (sp->unsync_children++)
1117 kvm_mmu_mark_parents_unsync(sp);
1120 static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu,
1121 struct kvm_mmu_page *sp)
1125 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1126 sp->spt[i] = shadow_trap_nonpresent_pte;
1129 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1130 struct kvm_mmu_page *sp)
1135 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1139 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1140 struct kvm_mmu_page *sp, u64 *spte,
1146 #define KVM_PAGE_ARRAY_NR 16
1148 struct kvm_mmu_pages {
1149 struct mmu_page_and_offset {
1150 struct kvm_mmu_page *sp;
1152 } page[KVM_PAGE_ARRAY_NR];
1156 #define for_each_unsync_children(bitmap, idx) \
1157 for (idx = find_first_bit(bitmap, 512); \
1159 idx = find_next_bit(bitmap, 512, idx+1))
1161 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1167 for (i=0; i < pvec->nr; i++)
1168 if (pvec->page[i].sp == sp)
1171 pvec->page[pvec->nr].sp = sp;
1172 pvec->page[pvec->nr].idx = idx;
1174 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1177 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1178 struct kvm_mmu_pages *pvec)
1180 int i, ret, nr_unsync_leaf = 0;
1182 for_each_unsync_children(sp->unsync_child_bitmap, i) {
1183 struct kvm_mmu_page *child;
1184 u64 ent = sp->spt[i];
1186 if (!is_shadow_present_pte(ent) || is_large_pte(ent))
1187 goto clear_child_bitmap;
1189 child = page_header(ent & PT64_BASE_ADDR_MASK);
1191 if (child->unsync_children) {
1192 if (mmu_pages_add(pvec, child, i))
1195 ret = __mmu_unsync_walk(child, pvec);
1197 goto clear_child_bitmap;
1199 nr_unsync_leaf += ret;
1202 } else if (child->unsync) {
1204 if (mmu_pages_add(pvec, child, i))
1207 goto clear_child_bitmap;
1212 __clear_bit(i, sp->unsync_child_bitmap);
1213 sp->unsync_children--;
1214 WARN_ON((int)sp->unsync_children < 0);
1218 return nr_unsync_leaf;
1221 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1222 struct kvm_mmu_pages *pvec)
1224 if (!sp->unsync_children)
1227 mmu_pages_add(pvec, sp, 0);
1228 return __mmu_unsync_walk(sp, pvec);
1231 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1233 WARN_ON(!sp->unsync);
1234 trace_kvm_mmu_sync_page(sp);
1236 --kvm->stat.mmu_unsync;
1239 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1240 struct list_head *invalid_list);
1241 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1242 struct list_head *invalid_list);
1244 #define for_each_gfn_sp(kvm, sp, gfn, pos) \
1245 hlist_for_each_entry(sp, pos, \
1246 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1247 if ((sp)->gfn != (gfn)) {} else
1249 #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos) \
1250 hlist_for_each_entry(sp, pos, \
1251 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1252 if ((sp)->gfn != (gfn) || (sp)->role.direct || \
1253 (sp)->role.invalid) {} else
1255 /* @sp->gfn should be write-protected at the call site */
1256 static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1257 struct list_head *invalid_list, bool clear_unsync)
1259 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
1260 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1265 kvm_unlink_unsync_page(vcpu->kvm, sp);
1267 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1268 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1272 kvm_mmu_flush_tlb(vcpu);
1276 static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
1277 struct kvm_mmu_page *sp)
1279 LIST_HEAD(invalid_list);
1282 ret = __kvm_sync_page(vcpu, sp, &invalid_list, false);
1284 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1289 static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1290 struct list_head *invalid_list)
1292 return __kvm_sync_page(vcpu, sp, invalid_list, true);
1295 /* @gfn should be write-protected at the call site */
1296 static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
1298 struct kvm_mmu_page *s;
1299 struct hlist_node *node;
1300 LIST_HEAD(invalid_list);
1303 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
1307 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1308 kvm_unlink_unsync_page(vcpu->kvm, s);
1309 if ((s->role.cr4_pae != !!is_pae(vcpu)) ||
1310 (vcpu->arch.mmu.sync_page(vcpu, s))) {
1311 kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list);
1317 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1319 kvm_mmu_flush_tlb(vcpu);
1322 struct mmu_page_path {
1323 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1324 unsigned int idx[PT64_ROOT_LEVEL-1];
1327 #define for_each_sp(pvec, sp, parents, i) \
1328 for (i = mmu_pages_next(&pvec, &parents, -1), \
1329 sp = pvec.page[i].sp; \
1330 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1331 i = mmu_pages_next(&pvec, &parents, i))
1333 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1334 struct mmu_page_path *parents,
1339 for (n = i+1; n < pvec->nr; n++) {
1340 struct kvm_mmu_page *sp = pvec->page[n].sp;
1342 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1343 parents->idx[0] = pvec->page[n].idx;
1347 parents->parent[sp->role.level-2] = sp;
1348 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1354 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1356 struct kvm_mmu_page *sp;
1357 unsigned int level = 0;
1360 unsigned int idx = parents->idx[level];
1362 sp = parents->parent[level];
1366 --sp->unsync_children;
1367 WARN_ON((int)sp->unsync_children < 0);
1368 __clear_bit(idx, sp->unsync_child_bitmap);
1370 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
1373 static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1374 struct mmu_page_path *parents,
1375 struct kvm_mmu_pages *pvec)
1377 parents->parent[parent->role.level-1] = NULL;
1381 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1382 struct kvm_mmu_page *parent)
1385 struct kvm_mmu_page *sp;
1386 struct mmu_page_path parents;
1387 struct kvm_mmu_pages pages;
1388 LIST_HEAD(invalid_list);
1390 kvm_mmu_pages_init(parent, &parents, &pages);
1391 while (mmu_unsync_walk(parent, &pages)) {
1394 for_each_sp(pages, sp, parents, i)
1395 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1398 kvm_flush_remote_tlbs(vcpu->kvm);
1400 for_each_sp(pages, sp, parents, i) {
1401 kvm_sync_page(vcpu, sp, &invalid_list);
1402 mmu_pages_clear_parents(&parents);
1404 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1405 cond_resched_lock(&vcpu->kvm->mmu_lock);
1406 kvm_mmu_pages_init(parent, &parents, &pages);
1410 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1418 union kvm_mmu_page_role role;
1420 struct kvm_mmu_page *sp;
1421 struct hlist_node *node;
1422 bool need_sync = false;
1424 role = vcpu->arch.mmu.base_role;
1426 role.direct = direct;
1429 role.access = access;
1430 if (!vcpu->arch.mmu.direct_map
1431 && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
1432 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1433 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1434 role.quadrant = quadrant;
1436 for_each_gfn_sp(vcpu->kvm, sp, gfn, node) {
1437 if (!need_sync && sp->unsync)
1440 if (sp->role.word != role.word)
1443 if (sp->unsync && kvm_sync_page_transient(vcpu, sp))
1446 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1447 if (sp->unsync_children) {
1448 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1449 kvm_mmu_mark_parents_unsync(sp);
1450 } else if (sp->unsync)
1451 kvm_mmu_mark_parents_unsync(sp);
1453 trace_kvm_mmu_get_page(sp, false);
1456 ++vcpu->kvm->stat.mmu_cache_miss;
1457 sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct);
1462 hlist_add_head(&sp->hash_link,
1463 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
1465 if (rmap_write_protect(vcpu->kvm, gfn))
1466 kvm_flush_remote_tlbs(vcpu->kvm);
1467 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
1468 kvm_sync_pages(vcpu, gfn);
1470 account_shadowed(vcpu->kvm, gfn);
1472 if (shadow_trap_nonpresent_pte != shadow_notrap_nonpresent_pte)
1473 vcpu->arch.mmu.prefetch_page(vcpu, sp);
1475 nonpaging_prefetch_page(vcpu, sp);
1476 trace_kvm_mmu_get_page(sp, true);
1480 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1481 struct kvm_vcpu *vcpu, u64 addr)
1483 iterator->addr = addr;
1484 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1485 iterator->level = vcpu->arch.mmu.shadow_root_level;
1487 if (iterator->level == PT64_ROOT_LEVEL &&
1488 vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
1489 !vcpu->arch.mmu.direct_map)
1492 if (iterator->level == PT32E_ROOT_LEVEL) {
1493 iterator->shadow_addr
1494 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1495 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1497 if (!iterator->shadow_addr)
1498 iterator->level = 0;
1502 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1504 if (iterator->level < PT_PAGE_TABLE_LEVEL)
1507 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1508 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1512 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1514 if (is_last_spte(*iterator->sptep, iterator->level)) {
1515 iterator->level = 0;
1519 iterator->shadow_addr = *iterator->sptep & PT64_BASE_ADDR_MASK;
1523 static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp)
1527 spte = __pa(sp->spt)
1528 | PT_PRESENT_MASK | PT_ACCESSED_MASK
1529 | PT_WRITABLE_MASK | PT_USER_MASK;
1530 __set_spte(sptep, spte);
1533 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1535 if (is_large_pte(*sptep)) {
1536 drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte);
1537 kvm_flush_remote_tlbs(vcpu->kvm);
1541 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1542 unsigned direct_access)
1544 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
1545 struct kvm_mmu_page *child;
1548 * For the direct sp, if the guest pte's dirty bit
1549 * changed form clean to dirty, it will corrupt the
1550 * sp's access: allow writable in the read-only sp,
1551 * so we should update the spte at this point to get
1552 * a new sp with the correct access.
1554 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
1555 if (child->role.access == direct_access)
1558 drop_parent_pte(child, sptep);
1559 kvm_flush_remote_tlbs(vcpu->kvm);
1563 static void mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
1567 struct kvm_mmu_page *child;
1570 if (is_shadow_present_pte(pte)) {
1571 if (is_last_spte(pte, sp->role.level))
1572 drop_spte(kvm, spte, shadow_trap_nonpresent_pte);
1574 child = page_header(pte & PT64_BASE_ADDR_MASK);
1575 drop_parent_pte(child, spte);
1578 __set_spte(spte, shadow_trap_nonpresent_pte);
1579 if (is_large_pte(pte))
1583 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
1584 struct kvm_mmu_page *sp)
1588 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1589 mmu_page_zap_pte(kvm, sp, sp->spt + i);
1592 static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
1594 mmu_page_remove_parent_pte(sp, parent_pte);
1597 static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm)
1600 struct kvm_vcpu *vcpu;
1602 kvm_for_each_vcpu(i, vcpu, kvm)
1603 vcpu->arch.last_pte_updated = NULL;
1606 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
1610 while ((parent_pte = pte_list_next(&sp->parent_ptes, NULL)))
1611 drop_parent_pte(sp, parent_pte);
1614 static int mmu_zap_unsync_children(struct kvm *kvm,
1615 struct kvm_mmu_page *parent,
1616 struct list_head *invalid_list)
1619 struct mmu_page_path parents;
1620 struct kvm_mmu_pages pages;
1622 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
1625 kvm_mmu_pages_init(parent, &parents, &pages);
1626 while (mmu_unsync_walk(parent, &pages)) {
1627 struct kvm_mmu_page *sp;
1629 for_each_sp(pages, sp, parents, i) {
1630 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
1631 mmu_pages_clear_parents(&parents);
1634 kvm_mmu_pages_init(parent, &parents, &pages);
1640 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1641 struct list_head *invalid_list)
1645 trace_kvm_mmu_prepare_zap_page(sp);
1646 ++kvm->stat.mmu_shadow_zapped;
1647 ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
1648 kvm_mmu_page_unlink_children(kvm, sp);
1649 kvm_mmu_unlink_parents(kvm, sp);
1650 if (!sp->role.invalid && !sp->role.direct)
1651 unaccount_shadowed(kvm, sp->gfn);
1653 kvm_unlink_unsync_page(kvm, sp);
1654 if (!sp->root_count) {
1657 list_move(&sp->link, invalid_list);
1659 list_move(&sp->link, &kvm->arch.active_mmu_pages);
1660 kvm_reload_remote_mmus(kvm);
1663 sp->role.invalid = 1;
1664 kvm_mmu_reset_last_pte_updated(kvm);
1668 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1669 struct list_head *invalid_list)
1671 struct kvm_mmu_page *sp;
1673 if (list_empty(invalid_list))
1676 kvm_flush_remote_tlbs(kvm);
1679 sp = list_first_entry(invalid_list, struct kvm_mmu_page, link);
1680 WARN_ON(!sp->role.invalid || sp->root_count);
1681 kvm_mmu_free_page(kvm, sp);
1682 } while (!list_empty(invalid_list));
1687 * Changing the number of mmu pages allocated to the vm
1688 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
1690 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
1692 LIST_HEAD(invalid_list);
1694 * If we set the number of mmu pages to be smaller be than the
1695 * number of actived pages , we must to free some mmu pages before we
1699 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
1700 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages &&
1701 !list_empty(&kvm->arch.active_mmu_pages)) {
1702 struct kvm_mmu_page *page;
1704 page = container_of(kvm->arch.active_mmu_pages.prev,
1705 struct kvm_mmu_page, link);
1706 kvm_mmu_prepare_zap_page(kvm, page, &invalid_list);
1707 kvm_mmu_commit_zap_page(kvm, &invalid_list);
1709 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
1712 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
1715 static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
1717 struct kvm_mmu_page *sp;
1718 struct hlist_node *node;
1719 LIST_HEAD(invalid_list);
1722 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
1725 for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
1726 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
1729 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
1731 kvm_mmu_commit_zap_page(kvm, &invalid_list);
1735 static void mmu_unshadow(struct kvm *kvm, gfn_t gfn)
1737 struct kvm_mmu_page *sp;
1738 struct hlist_node *node;
1739 LIST_HEAD(invalid_list);
1741 for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
1742 pgprintk("%s: zap %llx %x\n",
1743 __func__, gfn, sp->role.word);
1744 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
1746 kvm_mmu_commit_zap_page(kvm, &invalid_list);
1749 static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
1751 int slot = memslot_id(kvm, gfn);
1752 struct kvm_mmu_page *sp = page_header(__pa(pte));
1754 __set_bit(slot, sp->slot_bitmap);
1757 static void mmu_convert_notrap(struct kvm_mmu_page *sp)
1762 if (shadow_trap_nonpresent_pte == shadow_notrap_nonpresent_pte)
1765 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1766 if (pt[i] == shadow_notrap_nonpresent_pte)
1767 __set_spte(&pt[i], shadow_trap_nonpresent_pte);
1772 * The function is based on mtrr_type_lookup() in
1773 * arch/x86/kernel/cpu/mtrr/generic.c
1775 static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
1780 u8 prev_match, curr_match;
1781 int num_var_ranges = KVM_NR_VAR_MTRR;
1783 if (!mtrr_state->enabled)
1786 /* Make end inclusive end, instead of exclusive */
1789 /* Look in fixed ranges. Just return the type as per start */
1790 if (mtrr_state->have_fixed && (start < 0x100000)) {
1793 if (start < 0x80000) {
1795 idx += (start >> 16);
1796 return mtrr_state->fixed_ranges[idx];
1797 } else if (start < 0xC0000) {
1799 idx += ((start - 0x80000) >> 14);
1800 return mtrr_state->fixed_ranges[idx];
1801 } else if (start < 0x1000000) {
1803 idx += ((start - 0xC0000) >> 12);
1804 return mtrr_state->fixed_ranges[idx];
1809 * Look in variable ranges
1810 * Look of multiple ranges matching this address and pick type
1811 * as per MTRR precedence
1813 if (!(mtrr_state->enabled & 2))
1814 return mtrr_state->def_type;
1817 for (i = 0; i < num_var_ranges; ++i) {
1818 unsigned short start_state, end_state;
1820 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
1823 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
1824 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
1825 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
1826 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
1828 start_state = ((start & mask) == (base & mask));
1829 end_state = ((end & mask) == (base & mask));
1830 if (start_state != end_state)
1833 if ((start & mask) != (base & mask))
1836 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
1837 if (prev_match == 0xFF) {
1838 prev_match = curr_match;
1842 if (prev_match == MTRR_TYPE_UNCACHABLE ||
1843 curr_match == MTRR_TYPE_UNCACHABLE)
1844 return MTRR_TYPE_UNCACHABLE;
1846 if ((prev_match == MTRR_TYPE_WRBACK &&
1847 curr_match == MTRR_TYPE_WRTHROUGH) ||
1848 (prev_match == MTRR_TYPE_WRTHROUGH &&
1849 curr_match == MTRR_TYPE_WRBACK)) {
1850 prev_match = MTRR_TYPE_WRTHROUGH;
1851 curr_match = MTRR_TYPE_WRTHROUGH;
1854 if (prev_match != curr_match)
1855 return MTRR_TYPE_UNCACHABLE;
1858 if (prev_match != 0xFF)
1861 return mtrr_state->def_type;
1864 u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
1868 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
1869 (gfn << PAGE_SHIFT) + PAGE_SIZE);
1870 if (mtrr == 0xfe || mtrr == 0xff)
1871 mtrr = MTRR_TYPE_WRBACK;
1874 EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
1876 static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1878 trace_kvm_mmu_unsync_page(sp);
1879 ++vcpu->kvm->stat.mmu_unsync;
1882 kvm_mmu_mark_parents_unsync(sp);
1883 mmu_convert_notrap(sp);
1886 static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
1888 struct kvm_mmu_page *s;
1889 struct hlist_node *node;
1891 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
1894 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1895 __kvm_unsync_page(vcpu, s);
1899 static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
1902 struct kvm_mmu_page *s;
1903 struct hlist_node *node;
1904 bool need_unsync = false;
1906 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
1910 if (s->role.level != PT_PAGE_TABLE_LEVEL)
1913 if (!need_unsync && !s->unsync) {
1920 kvm_unsync_pages(vcpu, gfn);
1924 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1925 unsigned pte_access, int user_fault,
1926 int write_fault, int level,
1927 gfn_t gfn, pfn_t pfn, bool speculative,
1928 bool can_unsync, bool host_writable)
1930 u64 spte, entry = *sptep;
1934 * We don't set the accessed bit, since we sometimes want to see
1935 * whether the guest actually used the pte (in order to detect
1938 spte = PT_PRESENT_MASK;
1940 spte |= shadow_accessed_mask;
1942 if (pte_access & ACC_EXEC_MASK)
1943 spte |= shadow_x_mask;
1945 spte |= shadow_nx_mask;
1946 if (pte_access & ACC_USER_MASK)
1947 spte |= shadow_user_mask;
1948 if (level > PT_PAGE_TABLE_LEVEL)
1949 spte |= PT_PAGE_SIZE_MASK;
1951 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
1952 kvm_is_mmio_pfn(pfn));
1955 spte |= SPTE_HOST_WRITEABLE;
1957 pte_access &= ~ACC_WRITE_MASK;
1959 spte |= (u64)pfn << PAGE_SHIFT;
1961 if ((pte_access & ACC_WRITE_MASK)
1962 || (!vcpu->arch.mmu.direct_map && write_fault
1963 && !is_write_protection(vcpu) && !user_fault)) {
1965 if (level > PT_PAGE_TABLE_LEVEL &&
1966 has_wrprotected_page(vcpu->kvm, gfn, level)) {
1968 drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte);
1972 spte |= PT_WRITABLE_MASK;
1974 if (!vcpu->arch.mmu.direct_map
1975 && !(pte_access & ACC_WRITE_MASK)) {
1976 spte &= ~PT_USER_MASK;
1978 * If we converted a user page to a kernel page,
1979 * so that the kernel can write to it when cr0.wp=0,
1980 * then we should prevent the kernel from executing it
1981 * if SMEP is enabled.
1983 if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))
1984 spte |= PT64_NX_MASK;
1988 * Optimization: for pte sync, if spte was writable the hash
1989 * lookup is unnecessary (and expensive). Write protection
1990 * is responsibility of mmu_get_page / kvm_sync_page.
1991 * Same reasoning can be applied to dirty page accounting.
1993 if (!can_unsync && is_writable_pte(*sptep))
1996 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
1997 pgprintk("%s: found shadow page for %llx, marking ro\n",
2000 pte_access &= ~ACC_WRITE_MASK;
2001 if (is_writable_pte(spte))
2002 spte &= ~PT_WRITABLE_MASK;
2006 if (pte_access & ACC_WRITE_MASK)
2007 mark_page_dirty(vcpu->kvm, gfn);
2010 update_spte(sptep, spte);
2012 * If we overwrite a writable spte with a read-only one we
2013 * should flush remote TLBs. Otherwise rmap_write_protect
2014 * will find a read-only spte, even though the writable spte
2015 * might be cached on a CPU's TLB.
2017 if (is_writable_pte(entry) && !is_writable_pte(*sptep))
2018 kvm_flush_remote_tlbs(vcpu->kvm);
2023 static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2024 unsigned pt_access, unsigned pte_access,
2025 int user_fault, int write_fault,
2026 int *ptwrite, int level, gfn_t gfn,
2027 pfn_t pfn, bool speculative,
2030 int was_rmapped = 0;
2033 pgprintk("%s: spte %llx access %x write_fault %d"
2034 " user_fault %d gfn %llx\n",
2035 __func__, *sptep, pt_access,
2036 write_fault, user_fault, gfn);
2038 if (is_rmap_spte(*sptep)) {
2040 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2041 * the parent of the now unreachable PTE.
2043 if (level > PT_PAGE_TABLE_LEVEL &&
2044 !is_large_pte(*sptep)) {
2045 struct kvm_mmu_page *child;
2048 child = page_header(pte & PT64_BASE_ADDR_MASK);
2049 drop_parent_pte(child, sptep);
2050 kvm_flush_remote_tlbs(vcpu->kvm);
2051 } else if (pfn != spte_to_pfn(*sptep)) {
2052 pgprintk("hfn old %llx new %llx\n",
2053 spte_to_pfn(*sptep), pfn);
2054 drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte);
2055 kvm_flush_remote_tlbs(vcpu->kvm);
2060 if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault,
2061 level, gfn, pfn, speculative, true,
2065 kvm_mmu_flush_tlb(vcpu);
2068 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2069 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2070 is_large_pte(*sptep)? "2MB" : "4kB",
2071 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
2073 if (!was_rmapped && is_large_pte(*sptep))
2074 ++vcpu->kvm->stat.lpages;
2076 if (is_shadow_present_pte(*sptep)) {
2077 page_header_update_slot(vcpu->kvm, sptep, gfn);
2079 rmap_count = rmap_add(vcpu, sptep, gfn);
2080 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2081 rmap_recycle(vcpu, sptep, gfn);
2084 kvm_release_pfn_clean(pfn);
2086 vcpu->arch.last_pte_updated = sptep;
2087 vcpu->arch.last_pte_gfn = gfn;
2091 static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
2095 static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2098 struct kvm_memory_slot *slot;
2101 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2104 return page_to_pfn(bad_page);
2107 hva = gfn_to_hva_memslot(slot, gfn);
2109 return hva_to_pfn_atomic(vcpu->kvm, hva);
2112 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2113 struct kvm_mmu_page *sp,
2114 u64 *start, u64 *end)
2116 struct page *pages[PTE_PREFETCH_NUM];
2117 unsigned access = sp->role.access;
2121 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2122 if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK))
2125 ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start);
2129 for (i = 0; i < ret; i++, gfn++, start++)
2130 mmu_set_spte(vcpu, start, ACC_ALL,
2132 sp->role.level, gfn,
2133 page_to_pfn(pages[i]), true, true);
2138 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2139 struct kvm_mmu_page *sp, u64 *sptep)
2141 u64 *spte, *start = NULL;
2144 WARN_ON(!sp->role.direct);
2146 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2149 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2150 if (*spte != shadow_trap_nonpresent_pte || spte == sptep) {
2153 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2161 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2163 struct kvm_mmu_page *sp;
2166 * Since it's no accessed bit on EPT, it's no way to
2167 * distinguish between actually accessed translations
2168 * and prefetched, so disable pte prefetch if EPT is
2171 if (!shadow_accessed_mask)
2174 sp = page_header(__pa(sptep));
2175 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2178 __direct_pte_prefetch(vcpu, sp, sptep);
2181 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
2182 int map_writable, int level, gfn_t gfn, pfn_t pfn,
2185 struct kvm_shadow_walk_iterator iterator;
2186 struct kvm_mmu_page *sp;
2190 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2191 if (iterator.level == level) {
2192 unsigned pte_access = ACC_ALL;
2194 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, pte_access,
2195 0, write, &pt_write,
2196 level, gfn, pfn, prefault, map_writable);
2197 direct_pte_prefetch(vcpu, iterator.sptep);
2198 ++vcpu->stat.pf_fixed;
2202 if (*iterator.sptep == shadow_trap_nonpresent_pte) {
2203 u64 base_addr = iterator.addr;
2205 base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2206 pseudo_gfn = base_addr >> PAGE_SHIFT;
2207 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2209 1, ACC_ALL, iterator.sptep);
2211 pgprintk("nonpaging_map: ENOMEM\n");
2212 kvm_release_pfn_clean(pfn);
2216 __set_spte(iterator.sptep,
2218 | PT_PRESENT_MASK | PT_WRITABLE_MASK
2219 | shadow_user_mask | shadow_x_mask
2220 | shadow_accessed_mask);
2226 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2230 info.si_signo = SIGBUS;
2232 info.si_code = BUS_MCEERR_AR;
2233 info.si_addr = (void __user *)address;
2234 info.si_addr_lsb = PAGE_SHIFT;
2236 send_sig_info(SIGBUS, &info, tsk);
2239 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gva_t gva,
2240 unsigned access, gfn_t gfn, pfn_t pfn)
2242 kvm_release_pfn_clean(pfn);
2243 if (is_hwpoison_pfn(pfn)) {
2244 kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current);
2246 } else if (is_fault_pfn(pfn))
2249 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
2253 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
2254 gfn_t *gfnp, pfn_t *pfnp, int *levelp)
2258 int level = *levelp;
2261 * Check if it's a transparent hugepage. If this would be an
2262 * hugetlbfs page, level wouldn't be set to
2263 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2266 if (!is_error_pfn(pfn) && !kvm_is_mmio_pfn(pfn) &&
2267 level == PT_PAGE_TABLE_LEVEL &&
2268 PageTransCompound(pfn_to_page(pfn)) &&
2269 !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) {
2272 * mmu_notifier_retry was successful and we hold the
2273 * mmu_lock here, so the pmd can't become splitting
2274 * from under us, and in turn
2275 * __split_huge_page_refcount() can't run from under
2276 * us and we can safely transfer the refcount from
2277 * PG_tail to PG_head as we switch the pfn to tail to
2280 *levelp = level = PT_DIRECTORY_LEVEL;
2281 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2282 VM_BUG_ON((gfn & mask) != (pfn & mask));
2286 kvm_release_pfn_clean(pfn);
2288 if (!get_page_unless_zero(pfn_to_page(pfn)))
2295 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
2296 gva_t gva, pfn_t *pfn, bool write, bool *writable);
2298 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn,
2305 unsigned long mmu_seq;
2308 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
2309 if (likely(!force_pt_level)) {
2310 level = mapping_level(vcpu, gfn);
2312 * This path builds a PAE pagetable - so we can map
2313 * 2mb pages at maximum. Therefore check if the level
2314 * is larger than that.
2316 if (level > PT_DIRECTORY_LEVEL)
2317 level = PT_DIRECTORY_LEVEL;
2319 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2321 level = PT_PAGE_TABLE_LEVEL;
2323 mmu_seq = vcpu->kvm->mmu_notifier_seq;
2326 if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
2330 if (is_error_pfn(pfn))
2331 return kvm_handle_bad_page(vcpu, v, ACC_ALL, gfn, pfn);
2333 spin_lock(&vcpu->kvm->mmu_lock);
2334 if (mmu_notifier_retry(vcpu, mmu_seq))
2336 kvm_mmu_free_some_pages(vcpu);
2337 if (likely(!force_pt_level))
2338 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
2339 r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn,
2341 spin_unlock(&vcpu->kvm->mmu_lock);
2347 spin_unlock(&vcpu->kvm->mmu_lock);
2348 kvm_release_pfn_clean(pfn);
2353 static void mmu_free_roots(struct kvm_vcpu *vcpu)
2356 struct kvm_mmu_page *sp;
2357 LIST_HEAD(invalid_list);
2359 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2361 spin_lock(&vcpu->kvm->mmu_lock);
2362 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
2363 (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
2364 vcpu->arch.mmu.direct_map)) {
2365 hpa_t root = vcpu->arch.mmu.root_hpa;
2367 sp = page_header(root);
2369 if (!sp->root_count && sp->role.invalid) {
2370 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
2371 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2373 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2374 spin_unlock(&vcpu->kvm->mmu_lock);
2377 for (i = 0; i < 4; ++i) {
2378 hpa_t root = vcpu->arch.mmu.pae_root[i];
2381 root &= PT64_BASE_ADDR_MASK;
2382 sp = page_header(root);
2384 if (!sp->root_count && sp->role.invalid)
2385 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2388 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
2390 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2391 spin_unlock(&vcpu->kvm->mmu_lock);
2392 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2395 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2399 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
2400 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2407 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
2409 struct kvm_mmu_page *sp;
2412 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2413 spin_lock(&vcpu->kvm->mmu_lock);
2414 kvm_mmu_free_some_pages(vcpu);
2415 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL,
2418 spin_unlock(&vcpu->kvm->mmu_lock);
2419 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
2420 } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
2421 for (i = 0; i < 4; ++i) {
2422 hpa_t root = vcpu->arch.mmu.pae_root[i];
2424 ASSERT(!VALID_PAGE(root));
2425 spin_lock(&vcpu->kvm->mmu_lock);
2426 kvm_mmu_free_some_pages(vcpu);
2427 sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
2429 PT32_ROOT_LEVEL, 1, ACC_ALL,
2431 root = __pa(sp->spt);
2433 spin_unlock(&vcpu->kvm->mmu_lock);
2434 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
2436 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
2443 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
2445 struct kvm_mmu_page *sp;
2450 root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
2452 if (mmu_check_root(vcpu, root_gfn))
2456 * Do we shadow a long mode page table? If so we need to
2457 * write-protect the guests page table root.
2459 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
2460 hpa_t root = vcpu->arch.mmu.root_hpa;
2462 ASSERT(!VALID_PAGE(root));
2464 spin_lock(&vcpu->kvm->mmu_lock);
2465 kvm_mmu_free_some_pages(vcpu);
2466 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
2468 root = __pa(sp->spt);
2470 spin_unlock(&vcpu->kvm->mmu_lock);
2471 vcpu->arch.mmu.root_hpa = root;
2476 * We shadow a 32 bit page table. This may be a legacy 2-level
2477 * or a PAE 3-level page table. In either case we need to be aware that
2478 * the shadow page table may be a PAE or a long mode page table.
2480 pm_mask = PT_PRESENT_MASK;
2481 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
2482 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
2484 for (i = 0; i < 4; ++i) {
2485 hpa_t root = vcpu->arch.mmu.pae_root[i];
2487 ASSERT(!VALID_PAGE(root));
2488 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
2489 pdptr = kvm_pdptr_read_mmu(vcpu, &vcpu->arch.mmu, i);
2490 if (!is_present_gpte(pdptr)) {
2491 vcpu->arch.mmu.pae_root[i] = 0;
2494 root_gfn = pdptr >> PAGE_SHIFT;
2495 if (mmu_check_root(vcpu, root_gfn))
2498 spin_lock(&vcpu->kvm->mmu_lock);
2499 kvm_mmu_free_some_pages(vcpu);
2500 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
2503 root = __pa(sp->spt);
2505 spin_unlock(&vcpu->kvm->mmu_lock);
2507 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
2509 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
2512 * If we shadow a 32 bit page table with a long mode page
2513 * table we enter this path.
2515 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2516 if (vcpu->arch.mmu.lm_root == NULL) {
2518 * The additional page necessary for this is only
2519 * allocated on demand.
2524 lm_root = (void*)get_zeroed_page(GFP_KERNEL);
2525 if (lm_root == NULL)
2528 lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
2530 vcpu->arch.mmu.lm_root = lm_root;
2533 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
2539 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
2541 if (vcpu->arch.mmu.direct_map)
2542 return mmu_alloc_direct_roots(vcpu);
2544 return mmu_alloc_shadow_roots(vcpu);
2547 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
2550 struct kvm_mmu_page *sp;
2552 if (vcpu->arch.mmu.direct_map)
2555 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2558 vcpu_clear_mmio_info(vcpu, ~0ul);
2559 trace_kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
2560 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
2561 hpa_t root = vcpu->arch.mmu.root_hpa;
2562 sp = page_header(root);
2563 mmu_sync_children(vcpu, sp);
2564 trace_kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
2567 for (i = 0; i < 4; ++i) {
2568 hpa_t root = vcpu->arch.mmu.pae_root[i];
2570 if (root && VALID_PAGE(root)) {
2571 root &= PT64_BASE_ADDR_MASK;
2572 sp = page_header(root);
2573 mmu_sync_children(vcpu, sp);
2576 trace_kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
2579 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
2581 spin_lock(&vcpu->kvm->mmu_lock);
2582 mmu_sync_roots(vcpu);
2583 spin_unlock(&vcpu->kvm->mmu_lock);
2586 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
2587 u32 access, struct x86_exception *exception)
2590 exception->error_code = 0;
2594 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
2596 struct x86_exception *exception)
2599 exception->error_code = 0;
2600 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access);
2603 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
2604 u32 error_code, bool prefault)
2609 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
2610 r = mmu_topup_memory_caches(vcpu);
2615 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
2617 gfn = gva >> PAGE_SHIFT;
2619 return nonpaging_map(vcpu, gva & PAGE_MASK,
2620 error_code & PFERR_WRITE_MASK, gfn, prefault);
2623 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
2625 struct kvm_arch_async_pf arch;
2627 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
2629 arch.direct_map = vcpu->arch.mmu.direct_map;
2630 arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
2632 return kvm_setup_async_pf(vcpu, gva, gfn, &arch);
2635 static bool can_do_async_pf(struct kvm_vcpu *vcpu)
2637 if (unlikely(!irqchip_in_kernel(vcpu->kvm) ||
2638 kvm_event_needs_reinjection(vcpu)))
2641 return kvm_x86_ops->interrupt_allowed(vcpu);
2644 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
2645 gva_t gva, pfn_t *pfn, bool write, bool *writable)
2649 *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable);
2652 return false; /* *pfn has correct page already */
2654 put_page(pfn_to_page(*pfn));
2656 if (!prefault && can_do_async_pf(vcpu)) {
2657 trace_kvm_try_async_get_page(gva, gfn);
2658 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
2659 trace_kvm_async_pf_doublefault(gva, gfn);
2660 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
2662 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
2666 *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable);
2671 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
2678 gfn_t gfn = gpa >> PAGE_SHIFT;
2679 unsigned long mmu_seq;
2680 int write = error_code & PFERR_WRITE_MASK;
2684 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
2686 r = mmu_topup_memory_caches(vcpu);
2690 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
2691 if (likely(!force_pt_level)) {
2692 level = mapping_level(vcpu, gfn);
2693 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2695 level = PT_PAGE_TABLE_LEVEL;
2697 mmu_seq = vcpu->kvm->mmu_notifier_seq;
2700 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
2704 if (is_error_pfn(pfn))
2705 return kvm_handle_bad_page(vcpu, 0, 0, gfn, pfn);
2706 spin_lock(&vcpu->kvm->mmu_lock);
2707 if (mmu_notifier_retry(vcpu, mmu_seq))
2709 kvm_mmu_free_some_pages(vcpu);
2710 if (likely(!force_pt_level))
2711 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
2712 r = __direct_map(vcpu, gpa, write, map_writable,
2713 level, gfn, pfn, prefault);
2714 spin_unlock(&vcpu->kvm->mmu_lock);
2719 spin_unlock(&vcpu->kvm->mmu_lock);
2720 kvm_release_pfn_clean(pfn);
2724 static void nonpaging_free(struct kvm_vcpu *vcpu)
2726 mmu_free_roots(vcpu);
2729 static int nonpaging_init_context(struct kvm_vcpu *vcpu,
2730 struct kvm_mmu *context)
2732 context->new_cr3 = nonpaging_new_cr3;
2733 context->page_fault = nonpaging_page_fault;
2734 context->gva_to_gpa = nonpaging_gva_to_gpa;
2735 context->free = nonpaging_free;
2736 context->prefetch_page = nonpaging_prefetch_page;
2737 context->sync_page = nonpaging_sync_page;
2738 context->invlpg = nonpaging_invlpg;
2739 context->update_pte = nonpaging_update_pte;
2740 context->root_level = 0;
2741 context->shadow_root_level = PT32E_ROOT_LEVEL;
2742 context->root_hpa = INVALID_PAGE;
2743 context->direct_map = true;
2744 context->nx = false;
2748 void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
2750 ++vcpu->stat.tlb_flush;
2751 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2754 static void paging_new_cr3(struct kvm_vcpu *vcpu)
2756 pgprintk("%s: cr3 %lx\n", __func__, kvm_read_cr3(vcpu));
2757 mmu_free_roots(vcpu);
2760 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
2762 return kvm_read_cr3(vcpu);
2765 static void inject_page_fault(struct kvm_vcpu *vcpu,
2766 struct x86_exception *fault)
2768 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
2771 static void paging_free(struct kvm_vcpu *vcpu)
2773 nonpaging_free(vcpu);
2776 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
2780 bit7 = (gpte >> 7) & 1;
2781 return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0;
2785 #include "paging_tmpl.h"
2789 #include "paging_tmpl.h"
2792 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
2793 struct kvm_mmu *context,
2796 int maxphyaddr = cpuid_maxphyaddr(vcpu);
2797 u64 exb_bit_rsvd = 0;
2800 exb_bit_rsvd = rsvd_bits(63, 63);
2802 case PT32_ROOT_LEVEL:
2803 /* no rsvd bits for 2 level 4K page table entries */
2804 context->rsvd_bits_mask[0][1] = 0;
2805 context->rsvd_bits_mask[0][0] = 0;
2806 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
2808 if (!is_pse(vcpu)) {
2809 context->rsvd_bits_mask[1][1] = 0;
2813 if (is_cpuid_PSE36())
2814 /* 36bits PSE 4MB page */
2815 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
2817 /* 32 bits PSE 4MB page */
2818 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
2820 case PT32E_ROOT_LEVEL:
2821 context->rsvd_bits_mask[0][2] =
2822 rsvd_bits(maxphyaddr, 63) |
2823 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
2824 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
2825 rsvd_bits(maxphyaddr, 62); /* PDE */
2826 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2827 rsvd_bits(maxphyaddr, 62); /* PTE */
2828 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
2829 rsvd_bits(maxphyaddr, 62) |
2830 rsvd_bits(13, 20); /* large page */
2831 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
2833 case PT64_ROOT_LEVEL:
2834 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
2835 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2836 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
2837 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2838 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
2839 rsvd_bits(maxphyaddr, 51);
2840 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2841 rsvd_bits(maxphyaddr, 51);
2842 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
2843 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
2844 rsvd_bits(maxphyaddr, 51) |
2846 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
2847 rsvd_bits(maxphyaddr, 51) |
2848 rsvd_bits(13, 20); /* large page */
2849 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
2854 static int paging64_init_context_common(struct kvm_vcpu *vcpu,
2855 struct kvm_mmu *context,
2858 context->nx = is_nx(vcpu);
2860 reset_rsvds_bits_mask(vcpu, context, level);
2862 ASSERT(is_pae(vcpu));
2863 context->new_cr3 = paging_new_cr3;
2864 context->page_fault = paging64_page_fault;
2865 context->gva_to_gpa = paging64_gva_to_gpa;
2866 context->prefetch_page = paging64_prefetch_page;
2867 context->sync_page = paging64_sync_page;
2868 context->invlpg = paging64_invlpg;
2869 context->update_pte = paging64_update_pte;
2870 context->free = paging_free;
2871 context->root_level = level;
2872 context->shadow_root_level = level;
2873 context->root_hpa = INVALID_PAGE;
2874 context->direct_map = false;
2878 static int paging64_init_context(struct kvm_vcpu *vcpu,
2879 struct kvm_mmu *context)
2881 return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
2884 static int paging32_init_context(struct kvm_vcpu *vcpu,
2885 struct kvm_mmu *context)
2887 context->nx = false;
2889 reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL);
2891 context->new_cr3 = paging_new_cr3;
2892 context->page_fault = paging32_page_fault;
2893 context->gva_to_gpa = paging32_gva_to_gpa;
2894 context->free = paging_free;
2895 context->prefetch_page = paging32_prefetch_page;
2896 context->sync_page = paging32_sync_page;
2897 context->invlpg = paging32_invlpg;
2898 context->update_pte = paging32_update_pte;
2899 context->root_level = PT32_ROOT_LEVEL;
2900 context->shadow_root_level = PT32E_ROOT_LEVEL;
2901 context->root_hpa = INVALID_PAGE;
2902 context->direct_map = false;
2906 static int paging32E_init_context(struct kvm_vcpu *vcpu,
2907 struct kvm_mmu *context)
2909 return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
2912 static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
2914 struct kvm_mmu *context = vcpu->arch.walk_mmu;
2916 context->base_role.word = 0;
2917 context->new_cr3 = nonpaging_new_cr3;
2918 context->page_fault = tdp_page_fault;
2919 context->free = nonpaging_free;
2920 context->prefetch_page = nonpaging_prefetch_page;
2921 context->sync_page = nonpaging_sync_page;
2922 context->invlpg = nonpaging_invlpg;
2923 context->update_pte = nonpaging_update_pte;
2924 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
2925 context->root_hpa = INVALID_PAGE;
2926 context->direct_map = true;
2927 context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
2928 context->get_cr3 = get_cr3;
2929 context->inject_page_fault = kvm_inject_page_fault;
2930 context->nx = is_nx(vcpu);
2932 if (!is_paging(vcpu)) {
2933 context->nx = false;
2934 context->gva_to_gpa = nonpaging_gva_to_gpa;
2935 context->root_level = 0;
2936 } else if (is_long_mode(vcpu)) {
2937 context->nx = is_nx(vcpu);
2938 reset_rsvds_bits_mask(vcpu, context, PT64_ROOT_LEVEL);
2939 context->gva_to_gpa = paging64_gva_to_gpa;
2940 context->root_level = PT64_ROOT_LEVEL;
2941 } else if (is_pae(vcpu)) {
2942 context->nx = is_nx(vcpu);
2943 reset_rsvds_bits_mask(vcpu, context, PT32E_ROOT_LEVEL);
2944 context->gva_to_gpa = paging64_gva_to_gpa;
2945 context->root_level = PT32E_ROOT_LEVEL;
2947 context->nx = false;
2948 reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL);
2949 context->gva_to_gpa = paging32_gva_to_gpa;
2950 context->root_level = PT32_ROOT_LEVEL;
2956 int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
2959 bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
2961 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
2963 if (!is_paging(vcpu))
2964 r = nonpaging_init_context(vcpu, context);
2965 else if (is_long_mode(vcpu))
2966 r = paging64_init_context(vcpu, context);
2967 else if (is_pae(vcpu))
2968 r = paging32E_init_context(vcpu, context);
2970 r = paging32_init_context(vcpu, context);
2972 vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu);
2973 vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu);
2974 vcpu->arch.mmu.base_role.smep_andnot_wp
2975 = smep && !is_write_protection(vcpu);
2979 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
2981 static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
2983 int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu);
2985 vcpu->arch.walk_mmu->set_cr3 = kvm_x86_ops->set_cr3;
2986 vcpu->arch.walk_mmu->get_cr3 = get_cr3;
2987 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
2992 static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
2994 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
2996 g_context->get_cr3 = get_cr3;
2997 g_context->inject_page_fault = kvm_inject_page_fault;
3000 * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The
3001 * translation of l2_gpa to l1_gpa addresses is done using the
3002 * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa
3003 * functions between mmu and nested_mmu are swapped.
3005 if (!is_paging(vcpu)) {
3006 g_context->nx = false;
3007 g_context->root_level = 0;
3008 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
3009 } else if (is_long_mode(vcpu)) {
3010 g_context->nx = is_nx(vcpu);
3011 reset_rsvds_bits_mask(vcpu, g_context, PT64_ROOT_LEVEL);
3012 g_context->root_level = PT64_ROOT_LEVEL;
3013 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3014 } else if (is_pae(vcpu)) {
3015 g_context->nx = is_nx(vcpu);
3016 reset_rsvds_bits_mask(vcpu, g_context, PT32E_ROOT_LEVEL);
3017 g_context->root_level = PT32E_ROOT_LEVEL;
3018 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3020 g_context->nx = false;
3021 reset_rsvds_bits_mask(vcpu, g_context, PT32_ROOT_LEVEL);
3022 g_context->root_level = PT32_ROOT_LEVEL;
3023 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
3029 static int init_kvm_mmu(struct kvm_vcpu *vcpu)
3031 if (mmu_is_nested(vcpu))
3032 return init_kvm_nested_mmu(vcpu);
3033 else if (tdp_enabled)
3034 return init_kvm_tdp_mmu(vcpu);
3036 return init_kvm_softmmu(vcpu);
3039 static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
3042 if (VALID_PAGE(vcpu->arch.mmu.root_hpa))
3043 /* mmu.free() should set root_hpa = INVALID_PAGE */
3044 vcpu->arch.mmu.free(vcpu);
3047 int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
3049 destroy_kvm_mmu(vcpu);
3050 return init_kvm_mmu(vcpu);
3052 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
3054 int kvm_mmu_load(struct kvm_vcpu *vcpu)
3058 r = mmu_topup_memory_caches(vcpu);
3061 r = mmu_alloc_roots(vcpu);
3062 spin_lock(&vcpu->kvm->mmu_lock);
3063 mmu_sync_roots(vcpu);
3064 spin_unlock(&vcpu->kvm->mmu_lock);
3067 /* set_cr3() should ensure TLB has been flushed */
3068 vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
3072 EXPORT_SYMBOL_GPL(kvm_mmu_load);
3074 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
3076 mmu_free_roots(vcpu);
3078 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
3080 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
3081 struct kvm_mmu_page *sp, u64 *spte,
3084 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
3085 ++vcpu->kvm->stat.mmu_pde_zapped;
3089 ++vcpu->kvm->stat.mmu_pte_updated;
3090 vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
3093 static bool need_remote_flush(u64 old, u64 new)
3095 if (!is_shadow_present_pte(old))
3097 if (!is_shadow_present_pte(new))
3099 if ((old ^ new) & PT64_BASE_ADDR_MASK)
3101 old ^= PT64_NX_MASK;
3102 new ^= PT64_NX_MASK;
3103 return (old & ~new & PT64_PERM_MASK) != 0;
3106 static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page,
3107 bool remote_flush, bool local_flush)
3113 kvm_flush_remote_tlbs(vcpu->kvm);
3114 else if (local_flush)
3115 kvm_mmu_flush_tlb(vcpu);
3118 static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu)
3120 u64 *spte = vcpu->arch.last_pte_updated;
3122 return !!(spte && (*spte & shadow_accessed_mask));
3125 static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn)
3127 u64 *spte = vcpu->arch.last_pte_updated;
3130 && vcpu->arch.last_pte_gfn == gfn
3131 && shadow_accessed_mask
3132 && !(*spte & shadow_accessed_mask)
3133 && is_shadow_present_pte(*spte))
3134 set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
3137 void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
3138 const u8 *new, int bytes,
3139 bool guest_initiated)
3141 gfn_t gfn = gpa >> PAGE_SHIFT;
3142 union kvm_mmu_page_role mask = { .word = 0 };
3143 struct kvm_mmu_page *sp;
3144 struct hlist_node *node;
3145 LIST_HEAD(invalid_list);
3146 u64 entry, gentry, *spte;
3147 unsigned pte_size, page_offset, misaligned, quadrant, offset;
3148 int level, npte, invlpg_counter, r, flooded = 0;
3149 bool remote_flush, local_flush, zap_page;
3152 * If we don't have indirect shadow pages, it means no page is
3153 * write-protected, so we can exit simply.
3155 if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
3158 zap_page = remote_flush = local_flush = false;
3159 offset = offset_in_page(gpa);
3161 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
3163 invlpg_counter = atomic_read(&vcpu->kvm->arch.invlpg_counter);
3166 * Assume that the pte write on a page table of the same type
3167 * as the current vcpu paging mode since we update the sptes only
3168 * when they have the same mode.
3170 if ((is_pae(vcpu) && bytes == 4) || !new) {
3171 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
3176 r = kvm_read_guest(vcpu->kvm, gpa, &gentry, min(bytes, 8));
3179 new = (const u8 *)&gentry;
3184 gentry = *(const u32 *)new;
3187 gentry = *(const u64 *)new;
3194 spin_lock(&vcpu->kvm->mmu_lock);
3195 if (atomic_read(&vcpu->kvm->arch.invlpg_counter) != invlpg_counter)
3197 kvm_mmu_free_some_pages(vcpu);
3198 ++vcpu->kvm->stat.mmu_pte_write;
3199 trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
3200 if (guest_initiated) {
3201 kvm_mmu_access_page(vcpu, gfn);
3202 if (gfn == vcpu->arch.last_pt_write_gfn
3203 && !last_updated_pte_accessed(vcpu)) {
3204 ++vcpu->arch.last_pt_write_count;
3205 if (vcpu->arch.last_pt_write_count >= 3)
3208 vcpu->arch.last_pt_write_gfn = gfn;
3209 vcpu->arch.last_pt_write_count = 1;
3210 vcpu->arch.last_pte_updated = NULL;
3214 mask.cr0_wp = mask.cr4_pae = mask.nxe = 1;
3215 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) {
3216 pte_size = sp->role.cr4_pae ? 8 : 4;
3217 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
3218 misaligned |= bytes < 4;
3219 if (misaligned || flooded) {
3221 * Misaligned accesses are too much trouble to fix
3222 * up; also, they usually indicate a page is not used
3225 * If we're seeing too many writes to a page,
3226 * it may no longer be a page table, or we may be
3227 * forking, in which case it is better to unmap the
3230 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
3231 gpa, bytes, sp->role.word);
3232 zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
3234 ++vcpu->kvm->stat.mmu_flooded;
3237 page_offset = offset;
3238 level = sp->role.level;
3240 if (!sp->role.cr4_pae) {
3241 page_offset <<= 1; /* 32->64 */
3243 * A 32-bit pde maps 4MB while the shadow pdes map
3244 * only 2MB. So we need to double the offset again
3245 * and zap two pdes instead of one.
3247 if (level == PT32_ROOT_LEVEL) {
3248 page_offset &= ~7; /* kill rounding error */
3252 quadrant = page_offset >> PAGE_SHIFT;
3253 page_offset &= ~PAGE_MASK;
3254 if (quadrant != sp->role.quadrant)
3258 spte = &sp->spt[page_offset / sizeof(*spte)];
3261 mmu_page_zap_pte(vcpu->kvm, sp, spte);
3263 !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
3265 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
3266 if (!remote_flush && need_remote_flush(entry, *spte))
3267 remote_flush = true;
3271 mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush);
3272 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3273 trace_kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
3274 spin_unlock(&vcpu->kvm->mmu_lock);
3277 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
3282 if (vcpu->arch.mmu.direct_map)
3285 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
3287 spin_lock(&vcpu->kvm->mmu_lock);
3288 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
3289 spin_unlock(&vcpu->kvm->mmu_lock);
3292 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
3294 void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
3296 LIST_HEAD(invalid_list);
3298 while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES &&
3299 !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
3300 struct kvm_mmu_page *sp;
3302 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
3303 struct kvm_mmu_page, link);
3304 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
3305 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3306 ++vcpu->kvm->stat.mmu_recycled;
3310 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code,
3311 void *insn, int insn_len)
3314 enum emulation_result er;
3316 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false);
3325 r = mmu_topup_memory_caches(vcpu);
3329 er = x86_emulate_instruction(vcpu, cr2, 0, insn, insn_len);
3334 case EMULATE_DO_MMIO:
3335 ++vcpu->stat.mmio_exits;
3345 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
3347 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
3349 vcpu->arch.mmu.invlpg(vcpu, gva);
3350 kvm_mmu_flush_tlb(vcpu);
3351 ++vcpu->stat.invlpg;
3353 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
3355 void kvm_enable_tdp(void)
3359 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
3361 void kvm_disable_tdp(void)
3363 tdp_enabled = false;
3365 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
3367 static void free_mmu_pages(struct kvm_vcpu *vcpu)
3369 free_page((unsigned long)vcpu->arch.mmu.pae_root);
3370 if (vcpu->arch.mmu.lm_root != NULL)
3371 free_page((unsigned long)vcpu->arch.mmu.lm_root);
3374 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
3382 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
3383 * Therefore we need to allocate shadow page tables in the first
3384 * 4GB of memory, which happens to fit the DMA32 zone.
3386 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
3390 vcpu->arch.mmu.pae_root = page_address(page);
3391 for (i = 0; i < 4; ++i)
3392 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
3397 int kvm_mmu_create(struct kvm_vcpu *vcpu)
3400 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3402 return alloc_mmu_pages(vcpu);
3405 int kvm_mmu_setup(struct kvm_vcpu *vcpu)
3408 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3410 return init_kvm_mmu(vcpu);
3413 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
3415 struct kvm_mmu_page *sp;
3417 list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
3421 if (!test_bit(slot, sp->slot_bitmap))
3425 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3426 if (!is_shadow_present_pte(pt[i]) ||
3427 !is_last_spte(pt[i], sp->role.level))
3430 if (is_large_pte(pt[i])) {
3431 drop_spte(kvm, &pt[i],
3432 shadow_trap_nonpresent_pte);
3438 if (is_writable_pte(pt[i]))
3439 update_spte(&pt[i], pt[i] & ~PT_WRITABLE_MASK);
3442 kvm_flush_remote_tlbs(kvm);
3445 void kvm_mmu_zap_all(struct kvm *kvm)
3447 struct kvm_mmu_page *sp, *node;
3448 LIST_HEAD(invalid_list);
3450 spin_lock(&kvm->mmu_lock);
3452 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
3453 if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list))
3456 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3457 spin_unlock(&kvm->mmu_lock);
3460 static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm,
3461 struct list_head *invalid_list)
3463 struct kvm_mmu_page *page;
3465 page = container_of(kvm->arch.active_mmu_pages.prev,
3466 struct kvm_mmu_page, link);
3467 return kvm_mmu_prepare_zap_page(kvm, page, invalid_list);
3470 static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc)
3473 struct kvm *kvm_freed = NULL;
3474 int nr_to_scan = sc->nr_to_scan;
3476 if (nr_to_scan == 0)
3479 raw_spin_lock(&kvm_lock);
3481 list_for_each_entry(kvm, &vm_list, vm_list) {
3482 int idx, freed_pages;
3483 LIST_HEAD(invalid_list);
3485 idx = srcu_read_lock(&kvm->srcu);
3486 spin_lock(&kvm->mmu_lock);
3487 if (!kvm_freed && nr_to_scan > 0 &&
3488 kvm->arch.n_used_mmu_pages > 0) {
3489 freed_pages = kvm_mmu_remove_some_alloc_mmu_pages(kvm,
3495 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3496 spin_unlock(&kvm->mmu_lock);
3497 srcu_read_unlock(&kvm->srcu, idx);
3500 list_move_tail(&kvm_freed->vm_list, &vm_list);
3502 raw_spin_unlock(&kvm_lock);
3505 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
3508 static struct shrinker mmu_shrinker = {
3509 .shrink = mmu_shrink,
3510 .seeks = DEFAULT_SEEKS * 10,
3513 static void mmu_destroy_caches(void)
3515 if (pte_list_desc_cache)
3516 kmem_cache_destroy(pte_list_desc_cache);
3517 if (mmu_page_header_cache)
3518 kmem_cache_destroy(mmu_page_header_cache);
3521 int kvm_mmu_module_init(void)
3523 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
3524 sizeof(struct pte_list_desc),
3526 if (!pte_list_desc_cache)
3529 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
3530 sizeof(struct kvm_mmu_page),
3532 if (!mmu_page_header_cache)
3535 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0))
3538 register_shrinker(&mmu_shrinker);
3543 mmu_destroy_caches();
3548 * Caculate mmu pages needed for kvm.
3550 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
3553 unsigned int nr_mmu_pages;
3554 unsigned int nr_pages = 0;
3555 struct kvm_memslots *slots;
3557 slots = kvm_memslots(kvm);
3559 for (i = 0; i < slots->nmemslots; i++)
3560 nr_pages += slots->memslots[i].npages;
3562 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
3563 nr_mmu_pages = max(nr_mmu_pages,
3564 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
3566 return nr_mmu_pages;
3569 static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3572 if (len > buffer->len)
3577 static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3582 ret = pv_mmu_peek_buffer(buffer, len);
3587 buffer->processed += len;
3591 static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu,
3592 gpa_t addr, gpa_t value)
3597 if (!is_long_mode(vcpu) && !is_pae(vcpu))
3600 r = mmu_topup_memory_caches(vcpu);
3604 if (!emulator_write_phys(vcpu, addr, &value, bytes))
3610 static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3612 (void)kvm_set_cr3(vcpu, kvm_read_cr3(vcpu));
3616 static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr)
3618 spin_lock(&vcpu->kvm->mmu_lock);
3619 mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT);
3620 spin_unlock(&vcpu->kvm->mmu_lock);
3624 static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu,
3625 struct kvm_pv_mmu_op_buffer *buffer)
3627 struct kvm_mmu_op_header *header;
3629 header = pv_mmu_peek_buffer(buffer, sizeof *header);
3632 switch (header->op) {
3633 case KVM_MMU_OP_WRITE_PTE: {
3634 struct kvm_mmu_op_write_pte *wpte;
3636 wpte = pv_mmu_read_buffer(buffer, sizeof *wpte);
3639 return kvm_pv_mmu_write(vcpu, wpte->pte_phys,
3642 case KVM_MMU_OP_FLUSH_TLB: {
3643 struct kvm_mmu_op_flush_tlb *ftlb;
3645 ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb);
3648 return kvm_pv_mmu_flush_tlb(vcpu);
3650 case KVM_MMU_OP_RELEASE_PT: {
3651 struct kvm_mmu_op_release_pt *rpt;
3653 rpt = pv_mmu_read_buffer(buffer, sizeof *rpt);
3656 return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys);
3662 int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes,
3663 gpa_t addr, unsigned long *ret)
3666 struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer;
3668 buffer->ptr = buffer->buf;
3669 buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf);
3670 buffer->processed = 0;
3672 r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len);
3676 while (buffer->len) {
3677 r = kvm_pv_mmu_op_one(vcpu, buffer);
3686 *ret = buffer->processed;
3690 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
3692 struct kvm_shadow_walk_iterator iterator;
3695 spin_lock(&vcpu->kvm->mmu_lock);
3696 for_each_shadow_entry(vcpu, addr, iterator) {
3697 sptes[iterator.level-1] = *iterator.sptep;
3699 if (!is_shadow_present_pte(*iterator.sptep))
3702 spin_unlock(&vcpu->kvm->mmu_lock);
3706 EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
3708 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
3712 destroy_kvm_mmu(vcpu);
3713 free_mmu_pages(vcpu);
3714 mmu_free_memory_caches(vcpu);
3717 #ifdef CONFIG_KVM_MMU_AUDIT
3718 #include "mmu_audit.c"
3720 static void mmu_audit_disable(void) { }
3723 void kvm_mmu_module_exit(void)
3725 mmu_destroy_caches();
3726 percpu_counter_destroy(&kvm_total_used_mmu_pages);
3727 unregister_shrinker(&mmu_shrinker);
3728 mmu_audit_disable();