arch/x86/kvm/mmu.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * MMU support
   8  *
   9  * Copyright (C) 2006 Qumranet, Inc.
  10  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  11  *
  12  * Authors:
  13  *   Yaniv Kamay  <yaniv@qumranet.com>
  14  *   Avi Kivity   <avi@qumranet.com>
  15  *
  16  * This work is licensed under the terms of the GNU GPL, version 2.  See
  17  * the COPYING file in the top-level directory.
  18  *
  19  */
  20
  21 #include "irq.h"
  22 #include "mmu.h"
  23 #include "x86.h"
  24 #include "kvm_cache_regs.h"
  25
  26 #include <linux/kvm_host.h>
  27 #include <linux/types.h>
  28 #include <linux/string.h>
  29 #include <linux/mm.h>
  30 #include <linux/highmem.h>
  31 #include <linux/module.h>
  32 #include <linux/swap.h>
  33 #include <linux/hugetlb.h>
  34 #include <linux/compiler.h>
  35 #include <linux/srcu.h>
  36 #include <linux/slab.h>
  37 #include <linux/uaccess.h>
  38
  39 #include <asm/page.h>
  40 #include <asm/cmpxchg.h>
  41 #include <asm/io.h>
  42 #include <asm/vmx.h>
  43
  44 /*
  45  * When setting this variable to true it enables Two-Dimensional-Paging
  46  * where the hardware walks 2 page tables:
  47  * 1. the guest-virtual to guest-physical
  48  * 2. while doing 1. it walks guest-physical to host-physical
  49  * If the hardware supports that we don't need to do shadow paging.
  50  */
  51 bool tdp_enabled = false;
  52
  53 enum {
  54         AUDIT_PRE_PAGE_FAULT,
  55         AUDIT_POST_PAGE_FAULT,
  56         AUDIT_PRE_PTE_WRITE,
  57         AUDIT_POST_PTE_WRITE,
  58         AUDIT_PRE_SYNC,
  59         AUDIT_POST_SYNC
  60 };
  61
  62 char *audit_point_name[] = {
  63         "pre page fault",
  64         "post page fault",
  65         "pre pte write",
  66         "post pte write",
  67         "pre sync",
  68         "post sync"
  69 };
  70
  71 #undef MMU_DEBUG
  72
  73 #ifdef MMU_DEBUG
  74
  75 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
  76 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
  77
  78 #else
  79
  80 #define pgprintk(x...) do { } while (0)
  81 #define rmap_printk(x...) do { } while (0)
  82
  83 #endif
  84
  85 #ifdef MMU_DEBUG
  86 static int dbg = 0;
  87 module_param(dbg, bool, 0644);
  88 #endif
  89
  90 static int oos_shadow = 1;
  91 module_param(oos_shadow, bool, 0644);
  92
  93 #ifndef MMU_DEBUG
  94 #define ASSERT(x) do { } while (0)
  95 #else
  96 #define ASSERT(x)                                                       \
  97         if (!(x)) {                                                     \
  98                 printk(KERN_WARNING "assertion failed %s:%d: %s\n",     \
  99                        __FILE__, __LINE__, #x);                         \
 100         }
 101 #endif
 102
 103 #define PTE_PREFETCH_NUM                8
 104
 105 #define PT_FIRST_AVAIL_BITS_SHIFT 9
 106 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
 107
 108 #define PT64_LEVEL_BITS 9
 109
 110 #define PT64_LEVEL_SHIFT(level) \
 111                 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
 112
 113 #define PT64_INDEX(address, level)\
 114         (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
 115
 116
 117 #define PT32_LEVEL_BITS 10
 118
 119 #define PT32_LEVEL_SHIFT(level) \
 120                 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
 121
 122 #define PT32_LVL_OFFSET_MASK(level) \
 123         (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
 124                                                 * PT32_LEVEL_BITS))) - 1))
 125
 126 #define PT32_INDEX(address, level)\
 127         (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
 128
 129
 130 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
 131 #define PT64_DIR_BASE_ADDR_MASK \
 132         (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
 133 #define PT64_LVL_ADDR_MASK(level) \
 134         (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
 135                                                 * PT64_LEVEL_BITS))) - 1))
 136 #define PT64_LVL_OFFSET_MASK(level) \
 137         (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
 138                                                 * PT64_LEVEL_BITS))) - 1))
 139
 140 #define PT32_BASE_ADDR_MASK PAGE_MASK
 141 #define PT32_DIR_BASE_ADDR_MASK \
 142         (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
 143 #define PT32_LVL_ADDR_MASK(level) \
 144         (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
 145                                             * PT32_LEVEL_BITS))) - 1))
 146
 147 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
 148                         | PT64_NX_MASK)
 149
 150 #define PTE_LIST_EXT 4
 151
 152 #define ACC_EXEC_MASK    1
 153 #define ACC_WRITE_MASK   PT_WRITABLE_MASK
 154 #define ACC_USER_MASK    PT_USER_MASK
 155 #define ACC_ALL          (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
 156
 157 #include <trace/events/kvm.h>
 158
 159 #define CREATE_TRACE_POINTS
 160 #include "mmutrace.h"
 161
 162 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
 163
 164 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
 165
 166 struct pte_list_desc {
 167         u64 *sptes[PTE_LIST_EXT];
 168         struct pte_list_desc *more;
 169 };
 170
 171 struct kvm_shadow_walk_iterator {
 172         u64 addr;
 173         hpa_t shadow_addr;
 174         u64 *sptep;
 175         int level;
 176         unsigned index;
 177 };
 178
 179 #define for_each_shadow_entry(_vcpu, _addr, _walker)    \
 180         for (shadow_walk_init(&(_walker), _vcpu, _addr);        \
 181              shadow_walk_okay(&(_walker));                      \
 182              shadow_walk_next(&(_walker)))
 183
 184 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte)     \
 185         for (shadow_walk_init(&(_walker), _vcpu, _addr);                \
 186              shadow_walk_okay(&(_walker)) &&                            \
 187                 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; });  \
 188              __shadow_walk_next(&(_walker), spte))
 189
 190 static struct kmem_cache *pte_list_desc_cache;
 191 static struct kmem_cache *mmu_page_header_cache;
 192 static struct percpu_counter kvm_total_used_mmu_pages;
 193
 194 static u64 __read_mostly shadow_nx_mask;
 195 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
 196 static u64 __read_mostly shadow_user_mask;
 197 static u64 __read_mostly shadow_accessed_mask;
 198 static u64 __read_mostly shadow_dirty_mask;
 199 static u64 __read_mostly shadow_mmio_mask;
 200
 201 static void mmu_spte_set(u64 *sptep, u64 spte);
 202
 203 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask)
 204 {
 205         shadow_mmio_mask = mmio_mask;
 206 }
 207 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
 208
 209 static void mark_mmio_spte(u64 *sptep, u64 gfn, unsigned access)
 210 {
 211         access &= ACC_WRITE_MASK | ACC_USER_MASK;
 212
 213         trace_mark_mmio_spte(sptep, gfn, access);
 214         mmu_spte_set(sptep, shadow_mmio_mask | access | gfn << PAGE_SHIFT);
 215 }
 216
 217 static bool is_mmio_spte(u64 spte)
 218 {
 219         return (spte & shadow_mmio_mask) == shadow_mmio_mask;
 220 }
 221
 222 static gfn_t get_mmio_spte_gfn(u64 spte)
 223 {
 224         return (spte & ~shadow_mmio_mask) >> PAGE_SHIFT;
 225 }
 226
 227 static unsigned get_mmio_spte_access(u64 spte)
 228 {
 229         return (spte & ~shadow_mmio_mask) & ~PAGE_MASK;
 230 }
 231
 232 static bool set_mmio_spte(u64 *sptep, gfn_t gfn, pfn_t pfn, unsigned access)
 233 {
 234         if (unlikely(is_noslot_pfn(pfn))) {
 235                 mark_mmio_spte(sptep, gfn, access);
 236                 return true;
 237         }
 238
 239         return false;
 240 }
 241
 242 static inline u64 rsvd_bits(int s, int e)
 243 {
 244         return ((1ULL << (e - s + 1)) - 1) << s;
 245 }
 246
 247 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
 248                 u64 dirty_mask, u64 nx_mask, u64 x_mask)
 249 {
 250         shadow_user_mask = user_mask;
 251         shadow_accessed_mask = accessed_mask;
 252         shadow_dirty_mask = dirty_mask;
 253         shadow_nx_mask = nx_mask;
 254         shadow_x_mask = x_mask;
 255 }
 256 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
 257
 258 static int is_cpuid_PSE36(void)
 259 {
 260         return 1;
 261 }
 262
 263 static int is_nx(struct kvm_vcpu *vcpu)
 264 {
 265         return vcpu->arch.efer & EFER_NX;
 266 }
 267
 268 static int is_shadow_present_pte(u64 pte)
 269 {
 270         return pte & PT_PRESENT_MASK && !is_mmio_spte(pte);
 271 }
 272
 273 static int is_large_pte(u64 pte)
 274 {
 275         return pte & PT_PAGE_SIZE_MASK;
 276 }
 277
 278 static int is_dirty_gpte(unsigned long pte)
 279 {
 280         return pte & PT_DIRTY_MASK;
 281 }
 282
 283 static int is_rmap_spte(u64 pte)
 284 {
 285         return is_shadow_present_pte(pte);
 286 }
 287
 288 static int is_last_spte(u64 pte, int level)
 289 {
 290         if (level == PT_PAGE_TABLE_LEVEL)
 291                 return 1;
 292         if (is_large_pte(pte))
 293                 return 1;
 294         return 0;
 295 }
 296
 297 static pfn_t spte_to_pfn(u64 pte)
 298 {
 299         return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
 300 }
 301
 302 static gfn_t pse36_gfn_delta(u32 gpte)
 303 {
 304         int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
 305
 306         return (gpte & PT32_DIR_PSE36_MASK) << shift;
 307 }
 308
 309 #ifdef CONFIG_X86_64
 310 static void __set_spte(u64 *sptep, u64 spte)
 311 {
 312         *sptep = spte;
 313 }
 314
 315 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
 316 {
 317         *sptep = spte;
 318 }
 319
 320 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
 321 {
 322         return xchg(sptep, spte);
 323 }
 324
 325 static u64 __get_spte_lockless(u64 *sptep)
 326 {
 327         return ACCESS_ONCE(*sptep);
 328 }
 329
 330 static bool __check_direct_spte_mmio_pf(u64 spte)
 331 {
 332         /* It is valid if the spte is zapped. */
 333         return spte == 0ull;
 334 }
 335 #else
 336 union split_spte {
 337         struct {
 338                 u32 spte_low;
 339                 u32 spte_high;
 340         };
 341         u64 spte;
 342 };
 343
 344 static void count_spte_clear(u64 *sptep, u64 spte)
 345 {
 346         struct kvm_mmu_page *sp =  page_header(__pa(sptep));
 347
 348         if (is_shadow_present_pte(spte))
 349                 return;
 350
 351         /* Ensure the spte is completely set before we increase the count */
 352         smp_wmb();
 353         sp->clear_spte_count++;
 354 }
 355
 356 static void __set_spte(u64 *sptep, u64 spte)
 357 {
 358         union split_spte *ssptep, sspte;
 359
 360         ssptep = (union split_spte *)sptep;
 361         sspte = (union split_spte)spte;
 362
 363         ssptep->spte_high = sspte.spte_high;
 364
 365         /*
 366          * If we map the spte from nonpresent to present, We should store
 367          * the high bits firstly, then set present bit, so cpu can not
 368          * fetch this spte while we are setting the spte.
 369          */
 370         smp_wmb();
 371
 372         ssptep->spte_low = sspte.spte_low;
 373 }
 374
 375 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
 376 {
 377         union split_spte *ssptep, sspte;
 378
 379         ssptep = (union split_spte *)sptep;
 380         sspte = (union split_spte)spte;
 381
 382         ssptep->spte_low = sspte.spte_low;
 383
 384         /*
 385          * If we map the spte from present to nonpresent, we should clear
 386          * present bit firstly to avoid vcpu fetch the old high bits.
 387          */
 388         smp_wmb();
 389
 390         ssptep->spte_high = sspte.spte_high;
 391         count_spte_clear(sptep, spte);
 392 }
 393
 394 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
 395 {
 396         union split_spte *ssptep, sspte, orig;
 397
 398         ssptep = (union split_spte *)sptep;
 399         sspte = (union split_spte)spte;
 400
 401         /* xchg acts as a barrier before the setting of the high bits */
 402         orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
 403         orig.spte_high = ssptep->spte_high;
 404         ssptep->spte_high = sspte.spte_high;
 405         count_spte_clear(sptep, spte);
 406
 407         return orig.spte;
 408 }
 409
 410 /*
 411  * The idea using the light way get the spte on x86_32 guest is from
 412  * gup_get_pte(arch/x86/mm/gup.c).
 413  * The difference is we can not catch the spte tlb flush if we leave
 414  * guest mode, so we emulate it by increase clear_spte_count when spte
 415  * is cleared.
 416  */
 417 static u64 __get_spte_lockless(u64 *sptep)
 418 {
 419         struct kvm_mmu_page *sp =  page_header(__pa(sptep));
 420         union split_spte spte, *orig = (union split_spte *)sptep;
 421         int count;
 422
 423 retry:
 424         count = sp->clear_spte_count;
 425         smp_rmb();
 426
 427         spte.spte_low = orig->spte_low;
 428         smp_rmb();
 429
 430         spte.spte_high = orig->spte_high;
 431         smp_rmb();
 432
 433         if (unlikely(spte.spte_low != orig->spte_low ||
 434               count != sp->clear_spte_count))
 435                 goto retry;
 436
 437         return spte.spte;
 438 }
 439
 440 static bool __check_direct_spte_mmio_pf(u64 spte)
 441 {
 442         union split_spte sspte = (union split_spte)spte;
 443         u32 high_mmio_mask = shadow_mmio_mask >> 32;
 444
 445         /* It is valid if the spte is zapped. */
 446         if (spte == 0ull)
 447                 return true;
 448
 449         /* It is valid if the spte is being zapped. */
 450         if (sspte.spte_low == 0ull &&
 451             (sspte.spte_high & high_mmio_mask) == high_mmio_mask)
 452                 return true;
 453
 454         return false;
 455 }
 456 #endif
 457
 458 static bool spte_has_volatile_bits(u64 spte)
 459 {
 460         if (!shadow_accessed_mask)
 461                 return false;
 462
 463         if (!is_shadow_present_pte(spte))
 464                 return false;
 465
 466         if ((spte & shadow_accessed_mask) &&
 467               (!is_writable_pte(spte) || (spte & shadow_dirty_mask)))
 468                 return false;
 469
 470         return true;
 471 }
 472
 473 static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask)
 474 {
 475         return (old_spte & bit_mask) && !(new_spte & bit_mask);
 476 }
 477
 478 /* Rules for using mmu_spte_set:
 479  * Set the sptep from nonpresent to present.
 480  * Note: the sptep being assigned *must* be either not present
 481  * or in a state where the hardware will not attempt to update
 482  * the spte.
 483  */
 484 static void mmu_spte_set(u64 *sptep, u64 new_spte)
 485 {
 486         WARN_ON(is_shadow_present_pte(*sptep));
 487         __set_spte(sptep, new_spte);
 488 }
 489
 490 /* Rules for using mmu_spte_update:
 491  * Update the state bits, it means the mapped pfn is not changged.
 492  */
 493 static void mmu_spte_update(u64 *sptep, u64 new_spte)
 494 {
 495         u64 mask, old_spte = *sptep;
 496
 497         WARN_ON(!is_rmap_spte(new_spte));
 498
 499         if (!is_shadow_present_pte(old_spte))
 500                 return mmu_spte_set(sptep, new_spte);
 501
 502         new_spte |= old_spte & shadow_dirty_mask;
 503
 504         mask = shadow_accessed_mask;
 505         if (is_writable_pte(old_spte))
 506                 mask |= shadow_dirty_mask;
 507
 508         if (!spte_has_volatile_bits(old_spte) || (new_spte & mask) == mask)
 509                 __update_clear_spte_fast(sptep, new_spte);
 510         else
 511                 old_spte = __update_clear_spte_slow(sptep, new_spte);
 512
 513         if (!shadow_accessed_mask)
 514                 return;
 515
 516         if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask))
 517                 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
 518         if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask))
 519                 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
 520 }
 521
 522 /*
 523  * Rules for using mmu_spte_clear_track_bits:
 524  * It sets the sptep from present to nonpresent, and track the
 525  * state bits, it is used to clear the last level sptep.
 526  */
 527 static int mmu_spte_clear_track_bits(u64 *sptep)
 528 {
 529         pfn_t pfn;
 530         u64 old_spte = *sptep;
 531
 532         if (!spte_has_volatile_bits(old_spte))
 533                 __update_clear_spte_fast(sptep, 0ull);
 534         else
 535                 old_spte = __update_clear_spte_slow(sptep, 0ull);
 536
 537         if (!is_rmap_spte(old_spte))
 538                 return 0;
 539
 540         pfn = spte_to_pfn(old_spte);
 541         if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
 542                 kvm_set_pfn_accessed(pfn);
 543         if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask))
 544                 kvm_set_pfn_dirty(pfn);
 545         return 1;
 546 }
 547
 548 /*
 549  * Rules for using mmu_spte_clear_no_track:
 550  * Directly clear spte without caring the state bits of sptep,
 551  * it is used to set the upper level spte.
 552  */
 553 static void mmu_spte_clear_no_track(u64 *sptep)
 554 {
 555         __update_clear_spte_fast(sptep, 0ull);
 556 }
 557
 558 static u64 mmu_spte_get_lockless(u64 *sptep)
 559 {
 560         return __get_spte_lockless(sptep);
 561 }
 562
 563 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
 564 {
 565         rcu_read_lock();
 566         atomic_inc(&vcpu->kvm->arch.reader_counter);
 567
 568         /* Increase the counter before walking shadow page table */
 569         smp_mb__after_atomic_inc();
 570 }
 571
 572 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
 573 {
 574         /* Decrease the counter after walking shadow page table finished */
 575         smp_mb__before_atomic_dec();
 576         atomic_dec(&vcpu->kvm->arch.reader_counter);
 577         rcu_read_unlock();
 578 }
 579
 580 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
 581                                   struct kmem_cache *base_cache, int min)
 582 {
 583         void *obj;
 584
 585         if (cache->nobjs >= min)
 586                 return 0;
 587         while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
 588                 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
 589                 if (!obj)
 590                         return -ENOMEM;
 591                 cache->objects[cache->nobjs++] = obj;
 592         }
 593         return 0;
 594 }
 595
 596 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
 597 {
 598         return cache->nobjs;
 599 }
 600
 601 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
 602                                   struct kmem_cache *cache)
 603 {
 604         while (mc->nobjs)
 605                 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
 606 }
 607
 608 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
 609                                        int min)
 610 {
 611         void *page;
 612
 613         if (cache->nobjs >= min)
 614                 return 0;
 615         while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
 616                 page = (void *)__get_free_page(GFP_KERNEL);
 617                 if (!page)
 618                         return -ENOMEM;
 619                 cache->objects[cache->nobjs++] = page;
 620         }
 621         return 0;
 622 }
 623
 624 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
 625 {
 626         while (mc->nobjs)
 627                 free_page((unsigned long)mc->objects[--mc->nobjs]);
 628 }
 629
 630 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
 631 {
 632         int r;
 633
 634         r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
 635                                    pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
 636         if (r)
 637                 goto out;
 638         r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
 639         if (r)
 640                 goto out;
 641         r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
 642                                    mmu_page_header_cache, 4);
 643 out:
 644         return r;
 645 }
 646
 647 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
 648 {
 649         mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
 650                                 pte_list_desc_cache);
 651         mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
 652         mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
 653                                 mmu_page_header_cache);
 654 }
 655
 656 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
 657                                     size_t size)
 658 {
 659         void *p;
 660
 661         BUG_ON(!mc->nobjs);
 662         p = mc->objects[--mc->nobjs];
 663         return p;
 664 }
 665
 666 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
 667 {
 668         return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache,
 669                                       sizeof(struct pte_list_desc));
 670 }
 671
 672 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
 673 {
 674         kmem_cache_free(pte_list_desc_cache, pte_list_desc);
 675 }
 676
 677 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
 678 {
 679         if (!sp->role.direct)
 680                 return sp->gfns[index];
 681
 682         return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
 683 }
 684
 685 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
 686 {
 687         if (sp->role.direct)
 688                 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
 689         else
 690                 sp->gfns[index] = gfn;
 691 }
 692
 693 /*
 694  * Return the pointer to the large page information for a given gfn,
 695  * handling slots that are not large page aligned.
 696  */
 697 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
 698                                               struct kvm_memory_slot *slot,
 699                                               int level)
 700 {
 701         unsigned long idx;
 702
 703         idx = (gfn >> KVM_HPAGE_GFN_SHIFT(level)) -
 704               (slot->base_gfn >> KVM_HPAGE_GFN_SHIFT(level));
 705         return &slot->lpage_info[level - 2][idx];
 706 }
 707
 708 static void account_shadowed(struct kvm *kvm, gfn_t gfn)
 709 {
 710         struct kvm_memory_slot *slot;
 711         struct kvm_lpage_info *linfo;
 712         int i;
 713
 714         slot = gfn_to_memslot(kvm, gfn);
 715         for (i = PT_DIRECTORY_LEVEL;
 716              i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
 717                 linfo = lpage_info_slot(gfn, slot, i);
 718                 linfo->write_count += 1;
 719         }
 720         kvm->arch.indirect_shadow_pages++;
 721 }
 722
 723 static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
 724 {
 725         struct kvm_memory_slot *slot;
 726         struct kvm_lpage_info *linfo;
 727         int i;
 728
 729         slot = gfn_to_memslot(kvm, gfn);
 730         for (i = PT_DIRECTORY_LEVEL;
 731              i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
 732                 linfo = lpage_info_slot(gfn, slot, i);
 733                 linfo->write_count -= 1;
 734                 WARN_ON(linfo->write_count < 0);
 735         }
 736         kvm->arch.indirect_shadow_pages--;
 737 }
 738
 739 static int has_wrprotected_page(struct kvm *kvm,
 740                                 gfn_t gfn,
 741                                 int level)
 742 {
 743         struct kvm_memory_slot *slot;
 744         struct kvm_lpage_info *linfo;
 745
 746         slot = gfn_to_memslot(kvm, gfn);
 747         if (slot) {
 748                 linfo = lpage_info_slot(gfn, slot, level);
 749                 return linfo->write_count;
 750         }
 751
 752         return 1;
 753 }
 754
 755 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
 756 {
 757         unsigned long page_size;
 758         int i, ret = 0;
 759
 760         page_size = kvm_host_page_size(kvm, gfn);
 761
 762         for (i = PT_PAGE_TABLE_LEVEL;
 763              i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
 764                 if (page_size >= KVM_HPAGE_SIZE(i))
 765                         ret = i;
 766                 else
 767                         break;
 768         }
 769
 770         return ret;
 771 }
 772
 773 static struct kvm_memory_slot *
 774 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
 775                             bool no_dirty_log)
 776 {
 777         struct kvm_memory_slot *slot;
 778
 779         slot = gfn_to_memslot(vcpu->kvm, gfn);
 780         if (!slot || slot->flags & KVM_MEMSLOT_INVALID ||
 781               (no_dirty_log && slot->dirty_bitmap))
 782                 slot = NULL;
 783
 784         return slot;
 785 }
 786
 787 static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn)
 788 {
 789         return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true);
 790 }
 791
 792 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
 793 {
 794         int host_level, level, max_level;
 795
 796         host_level = host_mapping_level(vcpu->kvm, large_gfn);
 797
 798         if (host_level == PT_PAGE_TABLE_LEVEL)
 799                 return host_level;
 800
 801         max_level = kvm_x86_ops->get_lpage_level() < host_level ?
 802                 kvm_x86_ops->get_lpage_level() : host_level;
 803
 804         for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
 805                 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
 806                         break;
 807
 808         return level - 1;
 809 }
 810
 811 /*
 812  * Pte mapping structures:
 813  *
 814  * If pte_list bit zero is zero, then pte_list point to the spte.
 815  *
 816  * If pte_list bit zero is one, (then pte_list & ~1) points to a struct
 817  * pte_list_desc containing more mappings.
 818  *
 819  * Returns the number of pte entries before the spte was added or zero if
 820  * the spte was not added.
 821  *
 822  */
 823 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
 824                         unsigned long *pte_list)
 825 {
 826         struct pte_list_desc *desc;
 827         int i, count = 0;
 828
 829         if (!*pte_list) {
 830                 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
 831                 *pte_list = (unsigned long)spte;
 832         } else if (!(*pte_list & 1)) {
 833                 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
 834                 desc = mmu_alloc_pte_list_desc(vcpu);
 835                 desc->sptes[0] = (u64 *)*pte_list;
 836                 desc->sptes[1] = spte;
 837                 *pte_list = (unsigned long)desc | 1;
 838                 ++count;
 839         } else {
 840                 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
 841                 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
 842                 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
 843                         desc = desc->more;
 844                         count += PTE_LIST_EXT;
 845                 }
 846                 if (desc->sptes[PTE_LIST_EXT-1]) {
 847                         desc->more = mmu_alloc_pte_list_desc(vcpu);
 848                         desc = desc->more;
 849                 }
 850                 for (i = 0; desc->sptes[i]; ++i)
 851                         ++count;
 852                 desc->sptes[i] = spte;
 853         }
 854         return count;
 855 }
 856
 857 static u64 *pte_list_next(unsigned long *pte_list, u64 *spte)
 858 {
 859         struct pte_list_desc *desc;
 860         u64 *prev_spte;
 861         int i;
 862
 863         if (!*pte_list)
 864                 return NULL;
 865         else if (!(*pte_list & 1)) {
 866                 if (!spte)
 867                         return (u64 *)*pte_list;
 868                 return NULL;
 869         }
 870         desc = (struct pte_list_desc *)(*pte_list & ~1ul);
 871         prev_spte = NULL;
 872         while (desc) {
 873                 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
 874                         if (prev_spte == spte)
 875                                 return desc->sptes[i];
 876                         prev_spte = desc->sptes[i];
 877                 }
 878                 desc = desc->more;
 879         }
 880         return NULL;
 881 }
 882
 883 static void
 884 pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc,
 885                            int i, struct pte_list_desc *prev_desc)
 886 {
 887         int j;
 888
 889         for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
 890                 ;
 891         desc->sptes[i] = desc->sptes[j];
 892         desc->sptes[j] = NULL;
 893         if (j != 0)
 894                 return;
 895         if (!prev_desc && !desc->more)
 896                 *pte_list = (unsigned long)desc->sptes[0];
 897         else
 898                 if (prev_desc)
 899                         prev_desc->more = desc->more;
 900                 else
 901                         *pte_list = (unsigned long)desc->more | 1;
 902         mmu_free_pte_list_desc(desc);
 903 }
 904
 905 static void pte_list_remove(u64 *spte, unsigned long *pte_list)
 906 {
 907         struct pte_list_desc *desc;
 908         struct pte_list_desc *prev_desc;
 909         int i;
 910
 911         if (!*pte_list) {
 912                 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
 913                 BUG();
 914         } else if (!(*pte_list & 1)) {
 915                 rmap_printk("pte_list_remove:  %p 1->0\n", spte);
 916                 if ((u64 *)*pte_list != spte) {
 917                         printk(KERN_ERR "pte_list_remove:  %p 1->BUG\n", spte);
 918                         BUG();
 919                 }
 920                 *pte_list = 0;
 921         } else {
 922                 rmap_printk("pte_list_remove:  %p many->many\n", spte);
 923                 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
 924                 prev_desc = NULL;
 925                 while (desc) {
 926                         for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
 927                                 if (desc->sptes[i] == spte) {
 928                                         pte_list_desc_remove_entry(pte_list,
 929                                                                desc, i,
 930                                                                prev_desc);
 931                                         return;
 932                                 }
 933                         prev_desc = desc;
 934                         desc = desc->more;
 935                 }
 936                 pr_err("pte_list_remove: %p many->many\n", spte);
 937                 BUG();
 938         }
 939 }
 940
 941 typedef void (*pte_list_walk_fn) (u64 *spte);
 942 static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn)
 943 {
 944         struct pte_list_desc *desc;
 945         int i;
 946
 947         if (!*pte_list)
 948                 return;
 949
 950         if (!(*pte_list & 1))
 951                 return fn((u64 *)*pte_list);
 952
 953         desc = (struct pte_list_desc *)(*pte_list & ~1ul);
 954         while (desc) {
 955                 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
 956                         fn(desc->sptes[i]);
 957                 desc = desc->more;
 958         }
 959 }
 960
 961 static unsigned long *__gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level,
 962                                     struct kvm_memory_slot *slot)
 963 {
 964         struct kvm_lpage_info *linfo;
 965
 966         if (likely(level == PT_PAGE_TABLE_LEVEL))
 967                 return &slot->rmap[gfn - slot->base_gfn];
 968
 969         linfo = lpage_info_slot(gfn, slot, level);
 970         return &linfo->rmap_pde;
 971 }
 972
 973 /*
 974  * Take gfn and return the reverse mapping to it.
 975  */
 976 static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
 977 {
 978         struct kvm_memory_slot *slot;
 979
 980         slot = gfn_to_memslot(kvm, gfn);
 981         return __gfn_to_rmap(kvm, gfn, level, slot);
 982 }
 983
 984 static bool rmap_can_add(struct kvm_vcpu *vcpu)
 985 {
 986         struct kvm_mmu_memory_cache *cache;
 987
 988         cache = &vcpu->arch.mmu_pte_list_desc_cache;
 989         return mmu_memory_cache_free_objects(cache);
 990 }
 991
 992 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
 993 {
 994         struct kvm_mmu_page *sp;
 995         unsigned long *rmapp;
 996
 997         sp = page_header(__pa(spte));
 998         kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
 999         rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1000         return pte_list_add(vcpu, spte, rmapp);
1001 }
1002
1003 static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte)
1004 {
1005         return pte_list_next(rmapp, spte);
1006 }
1007
1008 static void rmap_remove(struct kvm *kvm, u64 *spte)
1009 {
1010         struct kvm_mmu_page *sp;
1011         gfn_t gfn;
1012         unsigned long *rmapp;
1013
1014         sp = page_header(__pa(spte));
1015         gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1016         rmapp = gfn_to_rmap(kvm, gfn, sp->role.level);
1017         pte_list_remove(spte, rmapp);
1018 }
1019
1020 static void drop_spte(struct kvm *kvm, u64 *sptep)
1021 {
1022         if (mmu_spte_clear_track_bits(sptep))
1023                 rmap_remove(kvm, sptep);
1024 }
1025
1026 int kvm_mmu_rmap_write_protect(struct kvm *kvm, u64 gfn,
1027                                struct kvm_memory_slot *slot)
1028 {
1029         unsigned long *rmapp;
1030         u64 *spte;
1031         int i, write_protected = 0;
1032
1033         rmapp = __gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL, slot);
1034         spte = rmap_next(kvm, rmapp, NULL);
1035         while (spte) {
1036                 BUG_ON(!(*spte & PT_PRESENT_MASK));
1037                 rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
1038                 if (is_writable_pte(*spte)) {
1039                         mmu_spte_update(spte, *spte & ~PT_WRITABLE_MASK);
1040                         write_protected = 1;
1041                 }
1042                 spte = rmap_next(kvm, rmapp, spte);
1043         }
1044
1045         /* check for huge page mappings */
1046         for (i = PT_DIRECTORY_LEVEL;
1047              i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
1048                 rmapp = __gfn_to_rmap(kvm, gfn, i, slot);
1049                 spte = rmap_next(kvm, rmapp, NULL);
1050                 while (spte) {
1051                         BUG_ON(!(*spte & PT_PRESENT_MASK));
1052                         BUG_ON(!is_large_pte(*spte));
1053                         pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn);
1054                         if (is_writable_pte(*spte)) {
1055                                 drop_spte(kvm, spte);
1056                                 --kvm->stat.lpages;
1057                                 spte = NULL;
1058                                 write_protected = 1;
1059                         }
1060                         spte = rmap_next(kvm, rmapp, spte);
1061                 }
1062         }
1063
1064         return write_protected;
1065 }
1066
1067 static int rmap_write_protect(struct kvm *kvm, u64 gfn)
1068 {
1069         struct kvm_memory_slot *slot;
1070
1071         slot = gfn_to_memslot(kvm, gfn);
1072         return kvm_mmu_rmap_write_protect(kvm, gfn, slot);
1073 }
1074
1075 static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
1076                            unsigned long data)
1077 {
1078         u64 *spte;
1079         int need_tlb_flush = 0;
1080
1081         while ((spte = rmap_next(kvm, rmapp, NULL))) {
1082                 BUG_ON(!(*spte & PT_PRESENT_MASK));
1083                 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte);
1084                 drop_spte(kvm, spte);
1085                 need_tlb_flush = 1;
1086         }
1087         return need_tlb_flush;
1088 }
1089
1090 static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
1091                              unsigned long data)
1092 {
1093         int need_flush = 0;
1094         u64 *spte, new_spte;
1095         pte_t *ptep = (pte_t *)data;
1096         pfn_t new_pfn;
1097
1098         WARN_ON(pte_huge(*ptep));
1099         new_pfn = pte_pfn(*ptep);
1100         spte = rmap_next(kvm, rmapp, NULL);
1101         while (spte) {
1102                 BUG_ON(!is_shadow_present_pte(*spte));
1103                 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte);
1104                 need_flush = 1;
1105                 if (pte_write(*ptep)) {
1106                         drop_spte(kvm, spte);
1107                         spte = rmap_next(kvm, rmapp, NULL);
1108                 } else {
1109                         new_spte = *spte &~ (PT64_BASE_ADDR_MASK);
1110                         new_spte |= (u64)new_pfn << PAGE_SHIFT;
1111
1112                         new_spte &= ~PT_WRITABLE_MASK;
1113                         new_spte &= ~SPTE_HOST_WRITEABLE;
1114                         new_spte &= ~shadow_accessed_mask;
1115                         mmu_spte_clear_track_bits(spte);
1116                         mmu_spte_set(spte, new_spte);
1117                         spte = rmap_next(kvm, rmapp, spte);
1118                 }
1119         }
1120         if (need_flush)
1121                 kvm_flush_remote_tlbs(kvm);
1122
1123         return 0;
1124 }
1125
1126 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1127                           unsigned long data,
1128                           int (*handler)(struct kvm *kvm, unsigned long *rmapp,
1129                                          unsigned long data))
1130 {
1131         int i, j;
1132         int ret;
1133         int retval = 0;
1134         struct kvm_memslots *slots;
1135
1136         slots = kvm_memslots(kvm);
1137
1138         for (i = 0; i < slots->nmemslots; i++) {
1139                 struct kvm_memory_slot *memslot = &slots->memslots[i];
1140                 unsigned long start = memslot->userspace_addr;
1141                 unsigned long end;
1142
1143                 end = start + (memslot->npages << PAGE_SHIFT);
1144                 if (hva >= start && hva < end) {
1145                         gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT;
1146                         gfn_t gfn = memslot->base_gfn + gfn_offset;
1147
1148                         ret = handler(kvm, &memslot->rmap[gfn_offset], data);
1149
1150                         for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) {
1151                                 struct kvm_lpage_info *linfo;
1152
1153                                 linfo = lpage_info_slot(gfn, memslot,
1154                                                         PT_DIRECTORY_LEVEL + j);
1155                                 ret |= handler(kvm, &linfo->rmap_pde, data);
1156                         }
1157                         trace_kvm_age_page(hva, memslot, ret);
1158                         retval |= ret;
1159                 }
1160         }
1161
1162         return retval;
1163 }
1164
1165 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
1166 {
1167         return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
1168 }
1169
1170 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1171 {
1172         kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1173 }
1174
1175 static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1176                          unsigned long data)
1177 {
1178         u64 *spte;
1179         int young = 0;
1180
1181         /*
1182          * Emulate the accessed bit for EPT, by checking if this page has
1183          * an EPT mapping, and clearing it if it does. On the next access,
1184          * a new EPT mapping will be established.
1185          * This has some overhead, but not as much as the cost of swapping
1186          * out actively used pages or breaking up actively used hugepages.
1187          */
1188         if (!shadow_accessed_mask)
1189                 return kvm_unmap_rmapp(kvm, rmapp, data);
1190
1191         spte = rmap_next(kvm, rmapp, NULL);
1192         while (spte) {
1193                 int _young;
1194                 u64 _spte = *spte;
1195                 BUG_ON(!(_spte & PT_PRESENT_MASK));
1196                 _young = _spte & PT_ACCESSED_MASK;
1197                 if (_young) {
1198                         young = 1;
1199                         clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
1200                 }
1201                 spte = rmap_next(kvm, rmapp, spte);
1202         }
1203         return young;
1204 }
1205
1206 static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1207                               unsigned long data)
1208 {
1209         u64 *spte;
1210         int young = 0;
1211
1212         /*
1213          * If there's no access bit in the secondary pte set by the
1214          * hardware it's up to gup-fast/gup to set the access bit in
1215          * the primary pte or in the page structure.
1216          */
1217         if (!shadow_accessed_mask)
1218                 goto out;
1219
1220         spte = rmap_next(kvm, rmapp, NULL);
1221         while (spte) {
1222                 u64 _spte = *spte;
1223                 BUG_ON(!(_spte & PT_PRESENT_MASK));
1224                 young = _spte & PT_ACCESSED_MASK;
1225                 if (young) {
1226                         young = 1;
1227                         break;
1228                 }
1229                 spte = rmap_next(kvm, rmapp, spte);
1230         }
1231 out:
1232         return young;
1233 }
1234
1235 #define RMAP_RECYCLE_THRESHOLD 1000
1236
1237 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1238 {
1239         unsigned long *rmapp;
1240         struct kvm_mmu_page *sp;
1241
1242         sp = page_header(__pa(spte));
1243
1244         rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1245
1246         kvm_unmap_rmapp(vcpu->kvm, rmapp, 0);
1247         kvm_flush_remote_tlbs(vcpu->kvm);
1248 }
1249
1250 int kvm_age_hva(struct kvm *kvm, unsigned long hva)
1251 {
1252         return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp);
1253 }
1254
1255 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1256 {
1257         return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1258 }
1259
1260 #ifdef MMU_DEBUG
1261 static int is_empty_shadow_page(u64 *spt)
1262 {
1263         u64 *pos;
1264         u64 *end;
1265
1266         for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1267                 if (is_shadow_present_pte(*pos)) {
1268                         printk(KERN_ERR "%s: %p %llx\n", __func__,
1269                                pos, *pos);
1270                         return 0;
1271                 }
1272         return 1;
1273 }
1274 #endif
1275
1276 /*
1277  * This value is the sum of all of the kvm instances's
1278  * kvm->arch.n_used_mmu_pages values.  We need a global,
1279  * aggregate version in order to make the slab shrinker
1280  * faster
1281  */
1282 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1283 {
1284         kvm->arch.n_used_mmu_pages += nr;
1285         percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1286 }
1287
1288 /*
1289  * Remove the sp from shadow page cache, after call it,
1290  * we can not find this sp from the cache, and the shadow
1291  * page table is still valid.
1292  * It should be under the protection of mmu lock.
1293  */
1294 static void kvm_mmu_isolate_page(struct kvm_mmu_page *sp)
1295 {
1296         ASSERT(is_empty_shadow_page(sp->spt));
1297         hlist_del(&sp->hash_link);
1298         if (!sp->role.direct)
1299                 free_page((unsigned long)sp->gfns);
1300 }
1301
1302 /*
1303  * Free the shadow page table and the sp, we can do it
1304  * out of the protection of mmu lock.
1305  */
1306 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1307 {
1308         list_del(&sp->link);
1309         free_page((unsigned long)sp->spt);
1310         kmem_cache_free(mmu_page_header_cache, sp);
1311 }
1312
1313 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1314 {
1315         return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
1316 }
1317
1318 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1319                                     struct kvm_mmu_page *sp, u64 *parent_pte)
1320 {
1321         if (!parent_pte)
1322                 return;
1323
1324         pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1325 }
1326
1327 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1328                                        u64 *parent_pte)
1329 {
1330         pte_list_remove(parent_pte, &sp->parent_ptes);
1331 }
1332
1333 static void drop_parent_pte(struct kvm_mmu_page *sp,
1334                             u64 *parent_pte)
1335 {
1336         mmu_page_remove_parent_pte(sp, parent_pte);
1337         mmu_spte_clear_no_track(parent_pte);
1338 }
1339
1340 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
1341                                                u64 *parent_pte, int direct)
1342 {
1343         struct kvm_mmu_page *sp;
1344         sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache,
1345                                         sizeof *sp);
1346         sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
1347         if (!direct)
1348                 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache,
1349                                                   PAGE_SIZE);
1350         set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1351         list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1352         bitmap_zero(sp->slot_bitmap, KVM_MEM_SLOTS_NUM);
1353         sp->parent_ptes = 0;
1354         mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1355         kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1356         return sp;
1357 }
1358
1359 static void mark_unsync(u64 *spte);
1360 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1361 {
1362         pte_list_walk(&sp->parent_ptes, mark_unsync);
1363 }
1364
1365 static void mark_unsync(u64 *spte)
1366 {
1367         struct kvm_mmu_page *sp;
1368         unsigned int index;
1369
1370         sp = page_header(__pa(spte));
1371         index = spte - sp->spt;
1372         if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1373                 return;
1374         if (sp->unsync_children++)
1375                 return;
1376         kvm_mmu_mark_parents_unsync(sp);
1377 }
1378
1379 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1380                                struct kvm_mmu_page *sp)
1381 {
1382         return 1;
1383 }
1384
1385 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1386 {
1387 }
1388
1389 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1390                                  struct kvm_mmu_page *sp, u64 *spte,
1391                                  const void *pte)
1392 {
1393         WARN_ON(1);
1394 }
1395
1396 #define KVM_PAGE_ARRAY_NR 16
1397
1398 struct kvm_mmu_pages {
1399         struct mmu_page_and_offset {
1400                 struct kvm_mmu_page *sp;
1401                 unsigned int idx;
1402         } page[KVM_PAGE_ARRAY_NR];
1403         unsigned int nr;
1404 };
1405
1406 #define for_each_unsync_children(bitmap, idx)           \
1407         for (idx = find_first_bit(bitmap, 512);         \
1408              idx < 512;                                 \
1409              idx = find_next_bit(bitmap, 512, idx+1))
1410
1411 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1412                          int idx)
1413 {
1414         int i;
1415
1416         if (sp->unsync)
1417                 for (i=0; i < pvec->nr; i++)
1418                         if (pvec->page[i].sp == sp)
1419                                 return 0;
1420
1421         pvec->page[pvec->nr].sp = sp;
1422         pvec->page[pvec->nr].idx = idx;
1423         pvec->nr++;
1424         return (pvec->nr == KVM_PAGE_ARRAY_NR);
1425 }
1426
1427 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1428                            struct kvm_mmu_pages *pvec)
1429 {
1430         int i, ret, nr_unsync_leaf = 0;
1431
1432         for_each_unsync_children(sp->unsync_child_bitmap, i) {
1433                 struct kvm_mmu_page *child;
1434                 u64 ent = sp->spt[i];
1435
1436                 if (!is_shadow_present_pte(ent) || is_large_pte(ent))
1437                         goto clear_child_bitmap;
1438
1439                 child = page_header(ent & PT64_BASE_ADDR_MASK);
1440
1441                 if (child->unsync_children) {
1442                         if (mmu_pages_add(pvec, child, i))
1443                                 return -ENOSPC;
1444
1445                         ret = __mmu_unsync_walk(child, pvec);
1446                         if (!ret)
1447                                 goto clear_child_bitmap;
1448                         else if (ret > 0)
1449                                 nr_unsync_leaf += ret;
1450                         else
1451                                 return ret;
1452                 } else if (child->unsync) {
1453                         nr_unsync_leaf++;
1454                         if (mmu_pages_add(pvec, child, i))
1455                                 return -ENOSPC;
1456                 } else
1457                          goto clear_child_bitmap;
1458
1459                 continue;
1460
1461 clear_child_bitmap:
1462                 __clear_bit(i, sp->unsync_child_bitmap);
1463                 sp->unsync_children--;
1464                 WARN_ON((int)sp->unsync_children < 0);
1465         }
1466
1467
1468         return nr_unsync_leaf;
1469 }
1470
1471 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1472                            struct kvm_mmu_pages *pvec)
1473 {
1474         if (!sp->unsync_children)
1475                 return 0;
1476
1477         mmu_pages_add(pvec, sp, 0);
1478         return __mmu_unsync_walk(sp, pvec);
1479 }
1480
1481 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1482 {
1483         WARN_ON(!sp->unsync);
1484         trace_kvm_mmu_sync_page(sp);
1485         sp->unsync = 0;
1486         --kvm->stat.mmu_unsync;
1487 }
1488
1489 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1490                                     struct list_head *invalid_list);
1491 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1492                                     struct list_head *invalid_list);
1493
1494 #define for_each_gfn_sp(kvm, sp, gfn, pos)                              \
1495   hlist_for_each_entry(sp, pos,                                         \
1496    &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link)   \
1497         if ((sp)->gfn != (gfn)) {} else
1498
1499 #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos)               \
1500   hlist_for_each_entry(sp, pos,                                         \
1501    &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link)   \
1502                 if ((sp)->gfn != (gfn) || (sp)->role.direct ||          \
1503                         (sp)->role.invalid) {} else
1504
1505 /* @sp->gfn should be write-protected at the call site */
1506 static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1507                            struct list_head *invalid_list, bool clear_unsync)
1508 {
1509         if (sp->role.cr4_pae != !!is_pae(vcpu)) {
1510                 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1511                 return 1;
1512         }
1513
1514         if (clear_unsync)
1515                 kvm_unlink_unsync_page(vcpu->kvm, sp);
1516
1517         if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1518                 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1519                 return 1;
1520         }
1521
1522         kvm_mmu_flush_tlb(vcpu);
1523         return 0;
1524 }
1525
1526 static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
1527                                    struct kvm_mmu_page *sp)
1528 {
1529         LIST_HEAD(invalid_list);
1530         int ret;
1531
1532         ret = __kvm_sync_page(vcpu, sp, &invalid_list, false);
1533         if (ret)
1534                 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1535
1536         return ret;
1537 }
1538
1539 static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1540                          struct list_head *invalid_list)
1541 {
1542         return __kvm_sync_page(vcpu, sp, invalid_list, true);
1543 }
1544
1545 /* @gfn should be write-protected at the call site */
1546 static void kvm_sync_pages(struct kvm_vcpu *vcpu,  gfn_t gfn)
1547 {
1548         struct kvm_mmu_page *s;
1549         struct hlist_node *node;
1550         LIST_HEAD(invalid_list);
1551         bool flush = false;
1552
1553         for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
1554                 if (!s->unsync)
1555                         continue;
1556
1557                 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1558                 kvm_unlink_unsync_page(vcpu->kvm, s);
1559                 if ((s->role.cr4_pae != !!is_pae(vcpu)) ||
1560                         (vcpu->arch.mmu.sync_page(vcpu, s))) {
1561                         kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list);
1562                         continue;
1563                 }
1564                 flush = true;
1565         }
1566
1567         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1568         if (flush)
1569                 kvm_mmu_flush_tlb(vcpu);
1570 }
1571
1572 struct mmu_page_path {
1573         struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1574         unsigned int idx[PT64_ROOT_LEVEL-1];
1575 };
1576
1577 #define for_each_sp(pvec, sp, parents, i)                       \
1578                 for (i = mmu_pages_next(&pvec, &parents, -1),   \
1579                         sp = pvec.page[i].sp;                   \
1580                         i < pvec.nr && ({ sp = pvec.page[i].sp; 1;});   \
1581                         i = mmu_pages_next(&pvec, &parents, i))
1582
1583 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1584                           struct mmu_page_path *parents,
1585                           int i)
1586 {
1587         int n;
1588
1589         for (n = i+1; n < pvec->nr; n++) {
1590                 struct kvm_mmu_page *sp = pvec->page[n].sp;
1591
1592                 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1593                         parents->idx[0] = pvec->page[n].idx;
1594                         return n;
1595                 }
1596
1597                 parents->parent[sp->role.level-2] = sp;
1598                 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1599         }
1600
1601         return n;
1602 }
1603
1604 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1605 {
1606         struct kvm_mmu_page *sp;
1607         unsigned int level = 0;
1608
1609         do {
1610                 unsigned int idx = parents->idx[level];
1611
1612                 sp = parents->parent[level];
1613                 if (!sp)
1614                         return;
1615
1616                 --sp->unsync_children;
1617                 WARN_ON((int)sp->unsync_children < 0);
1618                 __clear_bit(idx, sp->unsync_child_bitmap);
1619                 level++;
1620         } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
1621 }
1622
1623 static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1624                                struct mmu_page_path *parents,
1625                                struct kvm_mmu_pages *pvec)
1626 {
1627         parents->parent[parent->role.level-1] = NULL;
1628         pvec->nr = 0;
1629 }
1630
1631 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1632                               struct kvm_mmu_page *parent)
1633 {
1634         int i;
1635         struct kvm_mmu_page *sp;
1636         struct mmu_page_path parents;
1637         struct kvm_mmu_pages pages;
1638         LIST_HEAD(invalid_list);
1639
1640         kvm_mmu_pages_init(parent, &parents, &pages);
1641         while (mmu_unsync_walk(parent, &pages)) {
1642                 int protected = 0;
1643
1644                 for_each_sp(pages, sp, parents, i)
1645                         protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1646
1647                 if (protected)
1648                         kvm_flush_remote_tlbs(vcpu->kvm);
1649
1650                 for_each_sp(pages, sp, parents, i) {
1651                         kvm_sync_page(vcpu, sp, &invalid_list);
1652                         mmu_pages_clear_parents(&parents);
1653                 }
1654                 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1655                 cond_resched_lock(&vcpu->kvm->mmu_lock);
1656                 kvm_mmu_pages_init(parent, &parents, &pages);
1657         }
1658 }
1659
1660 static void init_shadow_page_table(struct kvm_mmu_page *sp)
1661 {
1662         int i;
1663
1664         for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1665                 sp->spt[i] = 0ull;
1666 }
1667
1668 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
1669 {
1670         sp->write_flooding_count = 0;
1671 }
1672
1673 static void clear_sp_write_flooding_count(u64 *spte)
1674 {
1675         struct kvm_mmu_page *sp =  page_header(__pa(spte));
1676
1677         __clear_sp_write_flooding_count(sp);
1678 }
1679
1680 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1681                                              gfn_t gfn,
1682                                              gva_t gaddr,
1683                                              unsigned level,
1684                                              int direct,
1685                                              unsigned access,
1686                                              u64 *parent_pte)
1687 {
1688         union kvm_mmu_page_role role;
1689         unsigned quadrant;
1690         struct kvm_mmu_page *sp;
1691         struct hlist_node *node;
1692         bool need_sync = false;
1693
1694         role = vcpu->arch.mmu.base_role;
1695         role.level = level;
1696         role.direct = direct;
1697         if (role.direct)
1698                 role.cr4_pae = 0;
1699         role.access = access;
1700         if (!vcpu->arch.mmu.direct_map
1701             && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
1702                 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1703                 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1704                 role.quadrant = quadrant;
1705         }
1706         for_each_gfn_sp(vcpu->kvm, sp, gfn, node) {
1707                 if (!need_sync && sp->unsync)
1708                         need_sync = true;
1709
1710                 if (sp->role.word != role.word)
1711                         continue;
1712
1713                 if (sp->unsync && kvm_sync_page_transient(vcpu, sp))
1714                         break;
1715
1716                 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1717                 if (sp->unsync_children) {
1718                         kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1719                         kvm_mmu_mark_parents_unsync(sp);
1720                 } else if (sp->unsync)
1721                         kvm_mmu_mark_parents_unsync(sp);
1722
1723                 __clear_sp_write_flooding_count(sp);
1724                 trace_kvm_mmu_get_page(sp, false);
1725                 return sp;
1726         }
1727         ++vcpu->kvm->stat.mmu_cache_miss;
1728         sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct);
1729         if (!sp)
1730                 return sp;
1731         sp->gfn = gfn;
1732         sp->role = role;
1733         hlist_add_head(&sp->hash_link,
1734                 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
1735         if (!direct) {
1736                 if (rmap_write_protect(vcpu->kvm, gfn))
1737                         kvm_flush_remote_tlbs(vcpu->kvm);
1738                 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
1739                         kvm_sync_pages(vcpu, gfn);
1740
1741                 account_shadowed(vcpu->kvm, gfn);
1742         }
1743         init_shadow_page_table(sp);
1744         trace_kvm_mmu_get_page(sp, true);
1745         return sp;
1746 }
1747
1748 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1749                              struct kvm_vcpu *vcpu, u64 addr)
1750 {
1751         iterator->addr = addr;
1752         iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1753         iterator->level = vcpu->arch.mmu.shadow_root_level;
1754
1755         if (iterator->level == PT64_ROOT_LEVEL &&
1756             vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
1757             !vcpu->arch.mmu.direct_map)
1758                 --iterator->level;
1759
1760         if (iterator->level == PT32E_ROOT_LEVEL) {
1761                 iterator->shadow_addr
1762                         = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1763                 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1764                 --iterator->level;
1765                 if (!iterator->shadow_addr)
1766                         iterator->level = 0;
1767         }
1768 }
1769
1770 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1771 {
1772         if (iterator->level < PT_PAGE_TABLE_LEVEL)
1773                 return false;
1774
1775         iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1776         iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1777         return true;
1778 }
1779
1780 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
1781                                u64 spte)
1782 {
1783         if (is_last_spte(spte, iterator->level)) {
1784                 iterator->level = 0;
1785                 return;
1786         }
1787
1788         iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
1789         --iterator->level;
1790 }
1791
1792 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1793 {
1794         return __shadow_walk_next(iterator, *iterator->sptep);
1795 }
1796
1797 static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp)
1798 {
1799         u64 spte;
1800
1801         spte = __pa(sp->spt)
1802                 | PT_PRESENT_MASK | PT_ACCESSED_MASK
1803                 | PT_WRITABLE_MASK | PT_USER_MASK;
1804         mmu_spte_set(sptep, spte);
1805 }
1806
1807 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1808 {
1809         if (is_large_pte(*sptep)) {
1810                 drop_spte(vcpu->kvm, sptep);
1811                 kvm_flush_remote_tlbs(vcpu->kvm);
1812         }
1813 }
1814
1815 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1816                                    unsigned direct_access)
1817 {
1818         if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
1819                 struct kvm_mmu_page *child;
1820
1821                 /*
1822                  * For the direct sp, if the guest pte's dirty bit
1823                  * changed form clean to dirty, it will corrupt the
1824                  * sp's access: allow writable in the read-only sp,
1825                  * so we should update the spte at this point to get
1826                  * a new sp with the correct access.
1827                  */
1828                 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
1829                 if (child->role.access == direct_access)
1830                         return;
1831
1832                 drop_parent_pte(child, sptep);
1833                 kvm_flush_remote_tlbs(vcpu->kvm);
1834         }
1835 }
1836
1837 static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
1838                              u64 *spte)
1839 {
1840         u64 pte;
1841         struct kvm_mmu_page *child;
1842
1843         pte = *spte;
1844         if (is_shadow_present_pte(pte)) {
1845                 if (is_last_spte(pte, sp->role.level)) {
1846                         drop_spte(kvm, spte);
1847                         if (is_large_pte(pte))
1848                                 --kvm->stat.lpages;
1849                 } else {
1850                         child = page_header(pte & PT64_BASE_ADDR_MASK);
1851                         drop_parent_pte(child, spte);
1852                 }
1853                 return true;
1854         }
1855
1856         if (is_mmio_spte(pte))
1857                 mmu_spte_clear_no_track(spte);
1858
1859         return false;
1860 }
1861
1862 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
1863                                          struct kvm_mmu_page *sp)
1864 {
1865         unsigned i;
1866
1867         for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1868                 mmu_page_zap_pte(kvm, sp, sp->spt + i);
1869 }
1870
1871 static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
1872 {
1873         mmu_page_remove_parent_pte(sp, parent_pte);
1874 }
1875
1876 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
1877 {
1878         u64 *parent_pte;
1879
1880         while ((parent_pte = pte_list_next(&sp->parent_ptes, NULL)))
1881                 drop_parent_pte(sp, parent_pte);
1882 }
1883
1884 static int mmu_zap_unsync_children(struct kvm *kvm,
1885                                    struct kvm_mmu_page *parent,
1886                                    struct list_head *invalid_list)
1887 {
1888         int i, zapped = 0;
1889         struct mmu_page_path parents;
1890         struct kvm_mmu_pages pages;
1891
1892         if (parent->role.level == PT_PAGE_TABLE_LEVEL)
1893                 return 0;
1894
1895         kvm_mmu_pages_init(parent, &parents, &pages);
1896         while (mmu_unsync_walk(parent, &pages)) {
1897                 struct kvm_mmu_page *sp;
1898
1899                 for_each_sp(pages, sp, parents, i) {
1900                         kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
1901                         mmu_pages_clear_parents(&parents);
1902                         zapped++;
1903                 }
1904                 kvm_mmu_pages_init(parent, &parents, &pages);
1905         }
1906
1907         return zapped;
1908 }
1909
1910 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1911                                     struct list_head *invalid_list)
1912 {
1913         int ret;
1914
1915         trace_kvm_mmu_prepare_zap_page(sp);
1916         ++kvm->stat.mmu_shadow_zapped;
1917         ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
1918         kvm_mmu_page_unlink_children(kvm, sp);
1919         kvm_mmu_unlink_parents(kvm, sp);
1920         if (!sp->role.invalid && !sp->role.direct)
1921                 unaccount_shadowed(kvm, sp->gfn);
1922         if (sp->unsync)
1923                 kvm_unlink_unsync_page(kvm, sp);
1924         if (!sp->root_count) {
1925                 /* Count self */
1926                 ret++;
1927                 list_move(&sp->link, invalid_list);
1928                 kvm_mod_used_mmu_pages(kvm, -1);
1929         } else {
1930                 list_move(&sp->link, &kvm->arch.active_mmu_pages);
1931                 kvm_reload_remote_mmus(kvm);
1932         }
1933
1934         sp->role.invalid = 1;
1935         return ret;
1936 }
1937
1938 static void kvm_mmu_isolate_pages(struct list_head *invalid_list)
1939 {
1940         struct kvm_mmu_page *sp;
1941
1942         list_for_each_entry(sp, invalid_list, link)
1943                 kvm_mmu_isolate_page(sp);
1944 }
1945
1946 static void free_pages_rcu(struct rcu_head *head)
1947 {
1948         struct kvm_mmu_page *next, *sp;
1949
1950         sp = container_of(head, struct kvm_mmu_page, rcu);
1951         while (sp) {
1952                 if (!list_empty(&sp->link))
1953                         next = list_first_entry(&sp->link,
1954                                       struct kvm_mmu_page, link);
1955                 else
1956                         next = NULL;
1957                 kvm_mmu_free_page(sp);
1958                 sp = next;
1959         }
1960 }
1961
1962 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1963                                     struct list_head *invalid_list)
1964 {
1965         struct kvm_mmu_page *sp;
1966
1967         if (list_empty(invalid_list))
1968                 return;
1969
1970         kvm_flush_remote_tlbs(kvm);
1971
1972         if (atomic_read(&kvm->arch.reader_counter)) {
1973                 kvm_mmu_isolate_pages(invalid_list);
1974                 sp = list_first_entry(invalid_list, struct kvm_mmu_page, link);
1975                 list_del_init(invalid_list);
1976
1977                 trace_kvm_mmu_delay_free_pages(sp);
1978                 call_rcu(&sp->rcu, free_pages_rcu);
1979                 return;
1980         }
1981
1982         do {
1983                 sp = list_first_entry(invalid_list, struct kvm_mmu_page, link);
1984                 WARN_ON(!sp->role.invalid || sp->root_count);
1985                 kvm_mmu_isolate_page(sp);
1986                 kvm_mmu_free_page(sp);
1987         } while (!list_empty(invalid_list));
1988
1989 }
1990
1991 /*
1992  * Changing the number of mmu pages allocated to the vm
1993  * Note: if goal_nr_mmu_pages is too small, you will get dead lock
1994  */
1995 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
1996 {
1997         LIST_HEAD(invalid_list);
1998         /*
1999          * If we set the number of mmu pages to be smaller be than the
2000          * number of actived pages , we must to free some mmu pages before we
2001          * change the value
2002          */
2003
2004         if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2005                 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages &&
2006                         !list_empty(&kvm->arch.active_mmu_pages)) {
2007                         struct kvm_mmu_page *page;
2008
2009                         page = container_of(kvm->arch.active_mmu_pages.prev,
2010                                             struct kvm_mmu_page, link);
2011                         kvm_mmu_prepare_zap_page(kvm, page, &invalid_list);
2012                 }
2013                 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2014                 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2015         }
2016
2017         kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2018 }
2019
2020 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2021 {
2022         struct kvm_mmu_page *sp;
2023         struct hlist_node *node;
2024         LIST_HEAD(invalid_list);
2025         int r;
2026
2027         pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2028         r = 0;
2029         spin_lock(&kvm->mmu_lock);
2030         for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
2031                 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2032                          sp->role.word);
2033                 r = 1;
2034                 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2035         }
2036         kvm_mmu_commit_zap_page(kvm, &invalid_list);
2037         spin_unlock(&kvm->mmu_lock);
2038
2039         return r;
2040 }
2041 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2042
2043 static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
2044 {
2045         int slot = memslot_id(kvm, gfn);
2046         struct kvm_mmu_page *sp = page_header(__pa(pte));
2047
2048         __set_bit(slot, sp->slot_bitmap);
2049 }
2050
2051 /*
2052  * The function is based on mtrr_type_lookup() in
2053  * arch/x86/kernel/cpu/mtrr/generic.c
2054  */
2055 static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
2056                          u64 start, u64 end)
2057 {
2058         int i;
2059         u64 base, mask;
2060         u8 prev_match, curr_match;
2061         int num_var_ranges = KVM_NR_VAR_MTRR;
2062
2063         if (!mtrr_state->enabled)
2064                 return 0xFF;
2065
2066         /* Make end inclusive end, instead of exclusive */
2067         end--;
2068
2069         /* Look in fixed ranges. Just return the type as per start */
2070         if (mtrr_state->have_fixed && (start < 0x100000)) {
2071                 int idx;
2072
2073                 if (start < 0x80000) {
2074                         idx = 0;
2075                         idx += (start >> 16);
2076                         return mtrr_state->fixed_ranges[idx];
2077                 } else if (start < 0xC0000) {
2078                         idx = 1 * 8;
2079                         idx += ((start - 0x80000) >> 14);
2080                         return mtrr_state->fixed_ranges[idx];
2081                 } else if (start < 0x1000000) {
2082                         idx = 3 * 8;
2083                         idx += ((start - 0xC0000) >> 12);
2084                         return mtrr_state->fixed_ranges[idx];
2085                 }
2086         }
2087
2088         /*
2089          * Look in variable ranges
2090          * Look of multiple ranges matching this address and pick type
2091          * as per MTRR precedence
2092          */
2093         if (!(mtrr_state->enabled & 2))
2094                 return mtrr_state->def_type;
2095
2096         prev_match = 0xFF;
2097         for (i = 0; i < num_var_ranges; ++i) {
2098                 unsigned short start_state, end_state;
2099
2100                 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
2101                         continue;
2102
2103                 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
2104                        (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
2105                 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
2106                        (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
2107
2108                 start_state = ((start & mask) == (base & mask));
2109                 end_state = ((end & mask) == (base & mask));
2110                 if (start_state != end_state)
2111                         return 0xFE;
2112
2113                 if ((start & mask) != (base & mask))
2114                         continue;
2115
2116                 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
2117                 if (prev_match == 0xFF) {
2118                         prev_match = curr_match;
2119                         continue;
2120                 }
2121
2122                 if (prev_match == MTRR_TYPE_UNCACHABLE ||
2123                     curr_match == MTRR_TYPE_UNCACHABLE)
2124                         return MTRR_TYPE_UNCACHABLE;
2125
2126                 if ((prev_match == MTRR_TYPE_WRBACK &&
2127                      curr_match == MTRR_TYPE_WRTHROUGH) ||
2128                     (prev_match == MTRR_TYPE_WRTHROUGH &&
2129                      curr_match == MTRR_TYPE_WRBACK)) {
2130                         prev_match = MTRR_TYPE_WRTHROUGH;
2131                         curr_match = MTRR_TYPE_WRTHROUGH;
2132                 }
2133
2134                 if (prev_match != curr_match)
2135                         return MTRR_TYPE_UNCACHABLE;
2136         }
2137
2138         if (prev_match != 0xFF)
2139                 return prev_match;
2140
2141         return mtrr_state->def_type;
2142 }
2143
2144 u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
2145 {
2146         u8 mtrr;
2147
2148         mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
2149                              (gfn << PAGE_SHIFT) + PAGE_SIZE);
2150         if (mtrr == 0xfe || mtrr == 0xff)
2151                 mtrr = MTRR_TYPE_WRBACK;
2152         return mtrr;
2153 }
2154 EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
2155
2156 static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2157 {
2158         trace_kvm_mmu_unsync_page(sp);
2159         ++vcpu->kvm->stat.mmu_unsync;
2160         sp->unsync = 1;
2161
2162         kvm_mmu_mark_parents_unsync(sp);
2163 }
2164
2165 static void kvm_unsync_pages(struct kvm_vcpu *vcpu,  gfn_t gfn)
2166 {
2167         struct kvm_mmu_page *s;
2168         struct hlist_node *node;
2169
2170         for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
2171                 if (s->unsync)
2172                         continue;
2173                 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
2174                 __kvm_unsync_page(vcpu, s);
2175         }
2176 }
2177
2178 static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2179                                   bool can_unsync)
2180 {
2181         struct kvm_mmu_page *s;
2182         struct hlist_node *node;
2183         bool need_unsync = false;
2184
2185         for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
2186                 if (!can_unsync)
2187                         return 1;
2188
2189                 if (s->role.level != PT_PAGE_TABLE_LEVEL)
2190                         return 1;
2191
2192                 if (!need_unsync && !s->unsync) {
2193                         if (!oos_shadow)
2194                                 return 1;
2195                         need_unsync = true;
2196                 }
2197         }
2198         if (need_unsync)
2199                 kvm_unsync_pages(vcpu, gfn);
2200         return 0;
2201 }
2202
2203 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2204                     unsigned pte_access, int user_fault,
2205                     int write_fault, int level,
2206                     gfn_t gfn, pfn_t pfn, bool speculative,
2207                     bool can_unsync, bool host_writable)
2208 {
2209         u64 spte, entry = *sptep;
2210         int ret = 0;
2211
2212         if (set_mmio_spte(sptep, gfn, pfn, pte_access))
2213                 return 0;
2214
2215         spte = PT_PRESENT_MASK;
2216         if (!speculative)
2217                 spte |= shadow_accessed_mask;
2218
2219         if (pte_access & ACC_EXEC_MASK)
2220                 spte |= shadow_x_mask;
2221         else
2222                 spte |= shadow_nx_mask;
2223         if (pte_access & ACC_USER_MASK)
2224                 spte |= shadow_user_mask;
2225         if (level > PT_PAGE_TABLE_LEVEL)
2226                 spte |= PT_PAGE_SIZE_MASK;
2227         if (tdp_enabled)
2228                 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2229                         kvm_is_mmio_pfn(pfn));
2230
2231         if (host_writable)
2232                 spte |= SPTE_HOST_WRITEABLE;
2233         else
2234                 pte_access &= ~ACC_WRITE_MASK;
2235
2236         spte |= (u64)pfn << PAGE_SHIFT;
2237
2238         if ((pte_access & ACC_WRITE_MASK)
2239             || (!vcpu->arch.mmu.direct_map && write_fault
2240                 && !is_write_protection(vcpu) && !user_fault)) {
2241
2242                 if (level > PT_PAGE_TABLE_LEVEL &&
2243                     has_wrprotected_page(vcpu->kvm, gfn, level)) {
2244                         ret = 1;
2245                         drop_spte(vcpu->kvm, sptep);
2246                         goto done;
2247                 }
2248
2249                 spte |= PT_WRITABLE_MASK;
2250
2251                 if (!vcpu->arch.mmu.direct_map
2252                     && !(pte_access & ACC_WRITE_MASK)) {
2253                         spte &= ~PT_USER_MASK;
2254                         /*
2255                          * If we converted a user page to a kernel page,
2256                          * so that the kernel can write to it when cr0.wp=0,
2257                          * then we should prevent the kernel from executing it
2258                          * if SMEP is enabled.
2259                          */
2260                         if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))
2261                                 spte |= PT64_NX_MASK;
2262                 }
2263
2264                 /*
2265                  * Optimization: for pte sync, if spte was writable the hash
2266                  * lookup is unnecessary (and expensive). Write protection
2267                  * is responsibility of mmu_get_page / kvm_sync_page.
2268                  * Same reasoning can be applied to dirty page accounting.
2269                  */
2270                 if (!can_unsync && is_writable_pte(*sptep))
2271                         goto set_pte;
2272
2273                 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2274                         pgprintk("%s: found shadow page for %llx, marking ro\n",
2275                                  __func__, gfn);
2276                         ret = 1;
2277                         pte_access &= ~ACC_WRITE_MASK;
2278                         if (is_writable_pte(spte))
2279                                 spte &= ~PT_WRITABLE_MASK;
2280                 }
2281         }
2282
2283         if (pte_access & ACC_WRITE_MASK)
2284                 mark_page_dirty(vcpu->kvm, gfn);
2285
2286 set_pte:
2287         mmu_spte_update(sptep, spte);
2288         /*
2289          * If we overwrite a writable spte with a read-only one we
2290          * should flush remote TLBs. Otherwise rmap_write_protect
2291          * will find a read-only spte, even though the writable spte
2292          * might be cached on a CPU's TLB.
2293          */
2294         if (is_writable_pte(entry) && !is_writable_pte(*sptep))
2295                 kvm_flush_remote_tlbs(vcpu->kvm);
2296 done:
2297         return ret;
2298 }
2299
2300 static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2301                          unsigned pt_access, unsigned pte_access,
2302                          int user_fault, int write_fault,
2303                          int *emulate, int level, gfn_t gfn,
2304                          pfn_t pfn, bool speculative,
2305                          bool host_writable)
2306 {
2307         int was_rmapped = 0;
2308         int rmap_count;
2309
2310         pgprintk("%s: spte %llx access %x write_fault %d"
2311                  " user_fault %d gfn %llx\n",
2312                  __func__, *sptep, pt_access,
2313                  write_fault, user_fault, gfn);
2314
2315         if (is_rmap_spte(*sptep)) {
2316                 /*
2317                  * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2318                  * the parent of the now unreachable PTE.
2319                  */
2320                 if (level > PT_PAGE_TABLE_LEVEL &&
2321                     !is_large_pte(*sptep)) {
2322                         struct kvm_mmu_page *child;
2323                         u64 pte = *sptep;
2324
2325                         child = page_header(pte & PT64_BASE_ADDR_MASK);
2326                         drop_parent_pte(child, sptep);
2327                         kvm_flush_remote_tlbs(vcpu->kvm);
2328                 } else if (pfn != spte_to_pfn(*sptep)) {
2329                         pgprintk("hfn old %llx new %llx\n",
2330                                  spte_to_pfn(*sptep), pfn);
2331                         drop_spte(vcpu->kvm, sptep);
2332                         kvm_flush_remote_tlbs(vcpu->kvm);
2333                 } else
2334                         was_rmapped = 1;
2335         }
2336
2337         if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault,
2338                       level, gfn, pfn, speculative, true,
2339                       host_writable)) {
2340                 if (write_fault)
2341                         *emulate = 1;
2342                 kvm_mmu_flush_tlb(vcpu);
2343         }
2344
2345         if (unlikely(is_mmio_spte(*sptep) && emulate))
2346                 *emulate = 1;
2347
2348         pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2349         pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2350                  is_large_pte(*sptep)? "2MB" : "4kB",
2351                  *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
2352                  *sptep, sptep);
2353         if (!was_rmapped && is_large_pte(*sptep))
2354                 ++vcpu->kvm->stat.lpages;
2355
2356         if (is_shadow_present_pte(*sptep)) {
2357                 page_header_update_slot(vcpu->kvm, sptep, gfn);
2358                 if (!was_rmapped) {
2359                         rmap_count = rmap_add(vcpu, sptep, gfn);
2360                         if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2361                                 rmap_recycle(vcpu, sptep, gfn);
2362                 }
2363         }
2364         kvm_release_pfn_clean(pfn);
2365 }
2366
2367 static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
2368 {
2369 }
2370
2371 static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2372                                      bool no_dirty_log)
2373 {
2374         struct kvm_memory_slot *slot;
2375         unsigned long hva;
2376
2377         slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2378         if (!slot) {
2379                 get_page(fault_page);
2380                 return page_to_pfn(fault_page);
2381         }
2382
2383         hva = gfn_to_hva_memslot(slot, gfn);
2384
2385         return hva_to_pfn_atomic(vcpu->kvm, hva);
2386 }
2387
2388 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2389                                     struct kvm_mmu_page *sp,
2390                                     u64 *start, u64 *end)
2391 {
2392         struct page *pages[PTE_PREFETCH_NUM];
2393         unsigned access = sp->role.access;
2394         int i, ret;
2395         gfn_t gfn;
2396
2397         gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2398         if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK))
2399                 return -1;
2400
2401         ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start);
2402         if (ret <= 0)
2403                 return -1;
2404
2405         for (i = 0; i < ret; i++, gfn++, start++)
2406                 mmu_set_spte(vcpu, start, ACC_ALL,
2407                              access, 0, 0, NULL,
2408                              sp->role.level, gfn,
2409                              page_to_pfn(pages[i]), true, true);
2410
2411         return 0;
2412 }
2413
2414 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2415                                   struct kvm_mmu_page *sp, u64 *sptep)
2416 {
2417         u64 *spte, *start = NULL;
2418         int i;
2419
2420         WARN_ON(!sp->role.direct);
2421
2422         i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2423         spte = sp->spt + i;
2424
2425         for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2426                 if (is_shadow_present_pte(*spte) || spte == sptep) {
2427                         if (!start)
2428                                 continue;
2429                         if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2430                                 break;
2431                         start = NULL;
2432                 } else if (!start)
2433                         start = spte;
2434         }
2435 }
2436
2437 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2438 {
2439         struct kvm_mmu_page *sp;
2440
2441         /*
2442          * Since it's no accessed bit on EPT, it's no way to
2443          * distinguish between actually accessed translations
2444          * and prefetched, so disable pte prefetch if EPT is
2445          * enabled.
2446          */
2447         if (!shadow_accessed_mask)
2448                 return;
2449
2450         sp = page_header(__pa(sptep));
2451         if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2452                 return;
2453
2454         __direct_pte_prefetch(vcpu, sp, sptep);
2455 }
2456
2457 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
2458                         int map_writable, int level, gfn_t gfn, pfn_t pfn,
2459                         bool prefault)
2460 {
2461         struct kvm_shadow_walk_iterator iterator;
2462         struct kvm_mmu_page *sp;
2463         int emulate = 0;
2464         gfn_t pseudo_gfn;
2465
2466         for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2467                 if (iterator.level == level) {
2468                         unsigned pte_access = ACC_ALL;
2469
2470                         mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, pte_access,
2471                                      0, write, &emulate,
2472                                      level, gfn, pfn, prefault, map_writable);
2473                         direct_pte_prefetch(vcpu, iterator.sptep);
2474                         ++vcpu->stat.pf_fixed;
2475                         break;
2476                 }
2477
2478                 if (!is_shadow_present_pte(*iterator.sptep)) {
2479                         u64 base_addr = iterator.addr;
2480
2481                         base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2482                         pseudo_gfn = base_addr >> PAGE_SHIFT;
2483                         sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2484                                               iterator.level - 1,
2485                                               1, ACC_ALL, iterator.sptep);
2486                         if (!sp) {
2487                                 pgprintk("nonpaging_map: ENOMEM\n");
2488                                 kvm_release_pfn_clean(pfn);
2489                                 return -ENOMEM;
2490                         }
2491
2492                         mmu_spte_set(iterator.sptep,
2493                                      __pa(sp->spt)
2494                                      | PT_PRESENT_MASK | PT_WRITABLE_MASK
2495                                      | shadow_user_mask | shadow_x_mask
2496                                      | shadow_accessed_mask);
2497                 }
2498         }
2499         return emulate;
2500 }
2501
2502 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2503 {
2504         siginfo_t info;
2505
2506         info.si_signo   = SIGBUS;
2507         info.si_errno   = 0;
2508         info.si_code    = BUS_MCEERR_AR;
2509         info.si_addr    = (void __user *)address;
2510         info.si_addr_lsb = PAGE_SHIFT;
2511
2512         send_sig_info(SIGBUS, &info, tsk);
2513 }
2514
2515 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, pfn_t pfn)
2516 {
2517         kvm_release_pfn_clean(pfn);
2518         if (is_hwpoison_pfn(pfn)) {
2519                 kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current);
2520                 return 0;
2521         }
2522
2523         return -EFAULT;
2524 }
2525
2526 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
2527                                         gfn_t *gfnp, pfn_t *pfnp, int *levelp)
2528 {
2529         pfn_t pfn = *pfnp;
2530         gfn_t gfn = *gfnp;
2531         int level = *levelp;
2532
2533         /*
2534          * Check if it's a transparent hugepage. If this would be an
2535          * hugetlbfs page, level wouldn't be set to
2536          * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2537          * here.
2538          */
2539         if (!is_error_pfn(pfn) && !kvm_is_mmio_pfn(pfn) &&
2540             level == PT_PAGE_TABLE_LEVEL &&
2541             PageTransCompound(pfn_to_page(pfn)) &&
2542             !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) {
2543                 unsigned long mask;
2544                 /*
2545                  * mmu_notifier_retry was successful and we hold the
2546                  * mmu_lock here, so the pmd can't become splitting
2547                  * from under us, and in turn
2548                  * __split_huge_page_refcount() can't run from under
2549                  * us and we can safely transfer the refcount from
2550                  * PG_tail to PG_head as we switch the pfn to tail to
2551                  * head.
2552                  */
2553                 *levelp = level = PT_DIRECTORY_LEVEL;
2554                 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2555                 VM_BUG_ON((gfn & mask) != (pfn & mask));
2556                 if (pfn & mask) {
2557                         gfn &= ~mask;
2558                         *gfnp = gfn;
2559                         kvm_release_pfn_clean(pfn);
2560                         pfn &= ~mask;
2561                         if (!get_page_unless_zero(pfn_to_page(pfn)))
2562                                 BUG();
2563                         *pfnp = pfn;
2564                 }
2565         }
2566 }
2567
2568 static bool mmu_invalid_pfn(pfn_t pfn)
2569 {
2570         return unlikely(is_invalid_pfn(pfn));
2571 }
2572
2573 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2574                                 pfn_t pfn, unsigned access, int *ret_val)
2575 {
2576         bool ret = true;
2577
2578         /* The pfn is invalid, report the error! */
2579         if (unlikely(is_invalid_pfn(pfn))) {
2580                 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2581                 goto exit;
2582         }
2583
2584         if (unlikely(is_noslot_pfn(pfn)))
2585                 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
2586
2587         ret = false;
2588 exit:
2589         return ret;
2590 }
2591
2592 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
2593                          gva_t gva, pfn_t *pfn, bool write, bool *writable);
2594
2595 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn,
2596                          bool prefault)
2597 {
2598         int r;
2599         int level;
2600         int force_pt_level;
2601         pfn_t pfn;
2602         unsigned long mmu_seq;
2603         bool map_writable;
2604
2605         force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
2606         if (likely(!force_pt_level)) {
2607                 level = mapping_level(vcpu, gfn);
2608                 /*
2609                  * This path builds a PAE pagetable - so we can map
2610                  * 2mb pages at maximum. Therefore check if the level
2611                  * is larger than that.
2612                  */
2613                 if (level > PT_DIRECTORY_LEVEL)
2614                         level = PT_DIRECTORY_LEVEL;
2615
2616                 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2617         } else
2618                 level = PT_PAGE_TABLE_LEVEL;
2619
2620         mmu_seq = vcpu->kvm->mmu_notifier_seq;
2621         smp_rmb();
2622
2623         if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
2624                 return 0;
2625
2626         if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
2627                 return r;
2628
2629         spin_lock(&vcpu->kvm->mmu_lock);
2630         if (mmu_notifier_retry(vcpu, mmu_seq))
2631                 goto out_unlock;
2632         kvm_mmu_free_some_pages(vcpu);
2633         if (likely(!force_pt_level))
2634                 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
2635         r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn,
2636                          prefault);
2637         spin_unlock(&vcpu->kvm->mmu_lock);
2638
2639
2640         return r;
2641
2642 out_unlock:
2643         spin_unlock(&vcpu->kvm->mmu_lock);
2644         kvm_release_pfn_clean(pfn);
2645         return 0;
2646 }
2647
2648
2649 static void mmu_free_roots(struct kvm_vcpu *vcpu)
2650 {
2651         int i;
2652         struct kvm_mmu_page *sp;
2653         LIST_HEAD(invalid_list);
2654
2655         if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2656                 return;
2657         spin_lock(&vcpu->kvm->mmu_lock);
2658         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
2659             (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
2660              vcpu->arch.mmu.direct_map)) {
2661                 hpa_t root = vcpu->arch.mmu.root_hpa;
2662
2663                 sp = page_header(root);
2664                 --sp->root_count;
2665                 if (!sp->root_count && sp->role.invalid) {
2666                         kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
2667                         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2668                 }
2669                 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2670                 spin_unlock(&vcpu->kvm->mmu_lock);
2671                 return;
2672         }
2673         for (i = 0; i < 4; ++i) {
2674                 hpa_t root = vcpu->arch.mmu.pae_root[i];
2675
2676                 if (root) {
2677                         root &= PT64_BASE_ADDR_MASK;
2678                         sp = page_header(root);
2679                         --sp->root_count;
2680                         if (!sp->root_count && sp->role.invalid)
2681                                 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2682                                                          &invalid_list);
2683                 }
2684                 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
2685         }
2686         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2687         spin_unlock(&vcpu->kvm->mmu_lock);
2688         vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2689 }
2690
2691 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2692 {
2693         int ret = 0;
2694
2695         if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
2696                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2697                 ret = 1;
2698         }
2699
2700         return ret;
2701 }
2702
2703 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
2704 {
2705         struct kvm_mmu_page *sp;
2706         unsigned i;
2707
2708         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2709                 spin_lock(&vcpu->kvm->mmu_lock);
2710                 kvm_mmu_free_some_pages(vcpu);
2711                 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL,
2712                                       1, ACC_ALL, NULL);
2713                 ++sp->root_count;
2714                 spin_unlock(&vcpu->kvm->mmu_lock);
2715                 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
2716         } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
2717                 for (i = 0; i < 4; ++i) {
2718                         hpa_t root = vcpu->arch.mmu.pae_root[i];
2719
2720                         ASSERT(!VALID_PAGE(root));
2721                         spin_lock(&vcpu->kvm->mmu_lock);
2722                         kvm_mmu_free_some_pages(vcpu);
2723                         sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
2724                                               i << 30,
2725                                               PT32_ROOT_LEVEL, 1, ACC_ALL,
2726                                               NULL);
2727                         root = __pa(sp->spt);
2728                         ++sp->root_count;
2729                         spin_unlock(&vcpu->kvm->mmu_lock);
2730                         vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
2731                 }
2732                 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
2733         } else
2734                 BUG();
2735
2736         return 0;
2737 }
2738
2739 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
2740 {
2741         struct kvm_mmu_page *sp;
2742         u64 pdptr, pm_mask;
2743         gfn_t root_gfn;
2744         int i;
2745
2746         root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
2747
2748         if (mmu_check_root(vcpu, root_gfn))
2749                 return 1;
2750
2751         /*
2752          * Do we shadow a long mode page table? If so we need to
2753          * write-protect the guests page table root.
2754          */
2755         if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
2756                 hpa_t root = vcpu->arch.mmu.root_hpa;
2757
2758                 ASSERT(!VALID_PAGE(root));
2759
2760                 spin_lock(&vcpu->kvm->mmu_lock);
2761                 kvm_mmu_free_some_pages(vcpu);
2762                 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
2763                                       0, ACC_ALL, NULL);
2764                 root = __pa(sp->spt);
2765                 ++sp->root_count;
2766                 spin_unlock(&vcpu->kvm->mmu_lock);
2767                 vcpu->arch.mmu.root_hpa = root;
2768                 return 0;
2769         }
2770
2771         /*
2772          * We shadow a 32 bit page table. This may be a legacy 2-level
2773          * or a PAE 3-level page table. In either case we need to be aware that
2774          * the shadow page table may be a PAE or a long mode page table.
2775          */
2776         pm_mask = PT_PRESENT_MASK;
2777         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
2778                 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
2779
2780         for (i = 0; i < 4; ++i) {
2781                 hpa_t root = vcpu->arch.mmu.pae_root[i];
2782
2783                 ASSERT(!VALID_PAGE(root));
2784                 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
2785                         pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i);
2786                         if (!is_present_gpte(pdptr)) {
2787                                 vcpu->arch.mmu.pae_root[i] = 0;
2788                                 continue;
2789                         }
2790                         root_gfn = pdptr >> PAGE_SHIFT;
2791                         if (mmu_check_root(vcpu, root_gfn))
2792                                 return 1;
2793                 }
2794                 spin_lock(&vcpu->kvm->mmu_lock);
2795                 kvm_mmu_free_some_pages(vcpu);
2796                 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
2797                                       PT32_ROOT_LEVEL, 0,
2798                                       ACC_ALL, NULL);
2799                 root = __pa(sp->spt);
2800                 ++sp->root_count;
2801                 spin_unlock(&vcpu->kvm->mmu_lock);
2802
2803                 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
2804         }
2805         vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
2806
2807         /*
2808          * If we shadow a 32 bit page table with a long mode page
2809          * table we enter this path.
2810          */
2811         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2812                 if (vcpu->arch.mmu.lm_root == NULL) {
2813                         /*
2814                          * The additional page necessary for this is only
2815                          * allocated on demand.
2816                          */
2817
2818                         u64 *lm_root;
2819
2820                         lm_root = (void*)get_zeroed_page(GFP_KERNEL);
2821                         if (lm_root == NULL)
2822                                 return 1;
2823
2824                         lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
2825
2826                         vcpu->arch.mmu.lm_root = lm_root;
2827                 }
2828
2829                 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
2830         }
2831
2832         return 0;
2833 }
2834
2835 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
2836 {
2837         if (vcpu->arch.mmu.direct_map)
2838                 return mmu_alloc_direct_roots(vcpu);
2839         else
2840                 return mmu_alloc_shadow_roots(vcpu);
2841 }
2842
2843 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
2844 {
2845         int i;
2846         struct kvm_mmu_page *sp;
2847
2848         if (vcpu->arch.mmu.direct_map)
2849                 return;
2850
2851         if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2852                 return;
2853
2854         vcpu_clear_mmio_info(vcpu, ~0ul);
2855         trace_kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
2856         if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
2857                 hpa_t root = vcpu->arch.mmu.root_hpa;
2858                 sp = page_header(root);
2859                 mmu_sync_children(vcpu, sp);
2860                 trace_kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
2861                 return;
2862         }
2863         for (i = 0; i < 4; ++i) {
2864                 hpa_t root = vcpu->arch.mmu.pae_root[i];
2865
2866                 if (root && VALID_PAGE(root)) {
2867                         root &= PT64_BASE_ADDR_MASK;
2868                         sp = page_header(root);
2869                         mmu_sync_children(vcpu, sp);
2870                 }
2871         }
2872         trace_kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
2873 }
2874
2875 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
2876 {
2877         spin_lock(&vcpu->kvm->mmu_lock);
2878         mmu_sync_roots(vcpu);
2879         spin_unlock(&vcpu->kvm->mmu_lock);
2880 }
2881
2882 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
2883                                   u32 access, struct x86_exception *exception)
2884 {
2885         if (exception)
2886                 exception->error_code = 0;
2887         return vaddr;
2888 }
2889
2890 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
2891                                          u32 access,
2892                                          struct x86_exception *exception)
2893 {
2894         if (exception)
2895                 exception->error_code = 0;
2896         return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access);
2897 }
2898
2899 static bool quickly_check_mmio_pf(struct kvm_vcpu *vcpu, u64 addr, bool direct)
2900 {
2901         if (direct)
2902                 return vcpu_match_mmio_gpa(vcpu, addr);
2903
2904         return vcpu_match_mmio_gva(vcpu, addr);
2905 }
2906
2907
2908 /*
2909  * On direct hosts, the last spte is only allows two states
2910  * for mmio page fault:
2911  *   - It is the mmio spte
2912  *   - It is zapped or it is being zapped.
2913  *
2914  * This function completely checks the spte when the last spte
2915  * is not the mmio spte.
2916  */
2917 static bool check_direct_spte_mmio_pf(u64 spte)
2918 {
2919         return __check_direct_spte_mmio_pf(spte);
2920 }
2921
2922 static u64 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr)
2923 {
2924         struct kvm_shadow_walk_iterator iterator;
2925         u64 spte = 0ull;
2926
2927         walk_shadow_page_lockless_begin(vcpu);
2928         for_each_shadow_entry_lockless(vcpu, addr, iterator, spte)
2929                 if (!is_shadow_present_pte(spte))
2930                         break;
2931         walk_shadow_page_lockless_end(vcpu);
2932
2933         return spte;
2934 }
2935
2936 /*
2937  * If it is a real mmio page fault, return 1 and emulat the instruction
2938  * directly, return 0 to let CPU fault again on the address, -1 is
2939  * returned if bug is detected.
2940  */
2941 int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct)
2942 {
2943         u64 spte;
2944
2945         if (quickly_check_mmio_pf(vcpu, addr, direct))
2946                 return 1;
2947
2948         spte = walk_shadow_page_get_mmio_spte(vcpu, addr);
2949
2950         if (is_mmio_spte(spte)) {
2951                 gfn_t gfn = get_mmio_spte_gfn(spte);
2952                 unsigned access = get_mmio_spte_access(spte);
2953
2954                 if (direct)
2955                         addr = 0;
2956
2957                 trace_handle_mmio_page_fault(addr, gfn, access);
2958                 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
2959                 return 1;
2960         }
2961
2962         /*
2963          * It's ok if the gva is remapped by other cpus on shadow guest,
2964          * it's a BUG if the gfn is not a mmio page.
2965          */
2966         if (direct && !check_direct_spte_mmio_pf(spte))
2967                 return -1;
2968
2969         /*
2970          * If the page table is zapped by other cpus, let CPU fault again on
2971          * the address.
2972          */
2973         return 0;
2974 }
2975 EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common);
2976
2977 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr,
2978                                   u32 error_code, bool direct)
2979 {
2980         int ret;
2981
2982         ret = handle_mmio_page_fault_common(vcpu, addr, direct);
2983         WARN_ON(ret < 0);
2984         return ret;
2985 }
2986
2987 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
2988                                 u32 error_code, bool prefault)
2989 {
2990         gfn_t gfn;
2991         int r;
2992
2993         pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
2994
2995         if (unlikely(error_code & PFERR_RSVD_MASK))
2996                 return handle_mmio_page_fault(vcpu, gva, error_code, true);
2997
2998         r = mmu_topup_memory_caches(vcpu);
2999         if (r)
3000                 return r;
3001
3002         ASSERT(vcpu);
3003         ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3004
3005         gfn = gva >> PAGE_SHIFT;
3006
3007         return nonpaging_map(vcpu, gva & PAGE_MASK,
3008                              error_code & PFERR_WRITE_MASK, gfn, prefault);
3009 }
3010
3011 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
3012 {
3013         struct kvm_arch_async_pf arch;
3014
3015         arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3016         arch.gfn = gfn;
3017         arch.direct_map = vcpu->arch.mmu.direct_map;
3018         arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
3019
3020         return kvm_setup_async_pf(vcpu, gva, gfn, &arch);
3021 }
3022
3023 static bool can_do_async_pf(struct kvm_vcpu *vcpu)
3024 {
3025         if (unlikely(!irqchip_in_kernel(vcpu->kvm) ||
3026                      kvm_event_needs_reinjection(vcpu)))
3027                 return false;
3028
3029         return kvm_x86_ops->interrupt_allowed(vcpu);
3030 }
3031
3032 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3033                          gva_t gva, pfn_t *pfn, bool write, bool *writable)
3034 {
3035         bool async;
3036
3037         *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable);
3038
3039         if (!async)
3040                 return false; /* *pfn has correct page already */
3041
3042         put_page(pfn_to_page(*pfn));
3043
3044         if (!prefault && can_do_async_pf(vcpu)) {
3045                 trace_kvm_try_async_get_page(gva, gfn);
3046                 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3047                         trace_kvm_async_pf_doublefault(gva, gfn);
3048                         kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3049                         return true;
3050                 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
3051                         return true;
3052         }
3053
3054         *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable);
3055
3056         return false;
3057 }
3058
3059 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
3060                           bool prefault)
3061 {
3062         pfn_t pfn;
3063         int r;
3064         int level;
3065         int force_pt_level;
3066         gfn_t gfn = gpa >> PAGE_SHIFT;
3067         unsigned long mmu_seq;
3068         int write = error_code & PFERR_WRITE_MASK;
3069         bool map_writable;
3070
3071         ASSERT(vcpu);
3072         ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3073
3074         if (unlikely(error_code & PFERR_RSVD_MASK))
3075                 return handle_mmio_page_fault(vcpu, gpa, error_code, true);
3076
3077         r = mmu_topup_memory_caches(vcpu);
3078         if (r)
3079                 return r;
3080
3081         force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
3082         if (likely(!force_pt_level)) {
3083                 level = mapping_level(vcpu, gfn);
3084                 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3085         } else
3086                 level = PT_PAGE_TABLE_LEVEL;
3087
3088         mmu_seq = vcpu->kvm->mmu_notifier_seq;
3089         smp_rmb();
3090
3091         if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3092                 return 0;
3093
3094         if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
3095                 return r;
3096
3097         spin_lock(&vcpu->kvm->mmu_lock);
3098         if (mmu_notifier_retry(vcpu, mmu_seq))
3099                 goto out_unlock;
3100         kvm_mmu_free_some_pages(vcpu);
3101         if (likely(!force_pt_level))
3102                 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3103         r = __direct_map(vcpu, gpa, write, map_writable,
3104                          level, gfn, pfn, prefault);
3105         spin_unlock(&vcpu->kvm->mmu_lock);
3106
3107         return r;
3108
3109 out_unlock:
3110         spin_unlock(&vcpu->kvm->mmu_lock);
3111         kvm_release_pfn_clean(pfn);
3112         return 0;
3113 }
3114
3115 static void nonpaging_free(struct kvm_vcpu *vcpu)
3116 {
3117         mmu_free_roots(vcpu);
3118 }
3119
3120 static int nonpaging_init_context(struct kvm_vcpu *vcpu,
3121                                   struct kvm_mmu *context)
3122 {
3123         context->new_cr3 = nonpaging_new_cr3;
3124         context->page_fault = nonpaging_page_fault;
3125         context->gva_to_gpa = nonpaging_gva_to_gpa;
3126         context->free = nonpaging_free;
3127         context->sync_page = nonpaging_sync_page;
3128         context->invlpg = nonpaging_invlpg;
3129         context->update_pte = nonpaging_update_pte;
3130         context->root_level = 0;
3131         context->shadow_root_level = PT32E_ROOT_LEVEL;
3132         context->root_hpa = INVALID_PAGE;
3133         context->direct_map = true;
3134         context->nx = false;
3135         return 0;
3136 }
3137
3138 void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3139 {
3140         ++vcpu->stat.tlb_flush;
3141         kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
3142 }
3143
3144 static void paging_new_cr3(struct kvm_vcpu *vcpu)
3145 {
3146         pgprintk("%s: cr3 %lx\n", __func__, kvm_read_cr3(vcpu));
3147         mmu_free_roots(vcpu);
3148 }
3149
3150 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3151 {
3152         return kvm_read_cr3(vcpu);
3153 }
3154
3155 static void inject_page_fault(struct kvm_vcpu *vcpu,
3156                               struct x86_exception *fault)
3157 {
3158         vcpu->arch.mmu.inject_page_fault(vcpu, fault);
3159 }
3160
3161 static void paging_free(struct kvm_vcpu *vcpu)
3162 {
3163         nonpaging_free(vcpu);
3164 }
3165
3166 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
3167 {
3168         int bit7;
3169
3170         bit7 = (gpte >> 7) & 1;
3171         return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0;
3172 }
3173
3174 static bool sync_mmio_spte(u64 *sptep, gfn_t gfn, unsigned access,
3175                            int *nr_present)
3176 {
3177         if (unlikely(is_mmio_spte(*sptep))) {
3178                 if (gfn != get_mmio_spte_gfn(*sptep)) {
3179                         mmu_spte_clear_no_track(sptep);
3180                         return true;
3181                 }
3182
3183                 (*nr_present)++;
3184                 mark_mmio_spte(sptep, gfn, access);
3185                 return true;
3186         }
3187
3188         return false;
3189 }
3190
3191 #define PTTYPE 64
3192 #include "paging_tmpl.h"
3193 #undef PTTYPE
3194
3195 #define PTTYPE 32
3196 #include "paging_tmpl.h"
3197 #undef PTTYPE
3198
3199 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3200                                   struct kvm_mmu *context,
3201                                   int level)
3202 {
3203         int maxphyaddr = cpuid_maxphyaddr(vcpu);
3204         u64 exb_bit_rsvd = 0;
3205
3206         if (!context->nx)
3207                 exb_bit_rsvd = rsvd_bits(63, 63);
3208         switch (level) {
3209         case PT32_ROOT_LEVEL:
3210                 /* no rsvd bits for 2 level 4K page table entries */
3211                 context->rsvd_bits_mask[0][1] = 0;
3212                 context->rsvd_bits_mask[0][0] = 0;
3213                 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3214
3215                 if (!is_pse(vcpu)) {
3216                         context->rsvd_bits_mask[1][1] = 0;
3217                         break;
3218                 }
3219
3220                 if (is_cpuid_PSE36())
3221                         /* 36bits PSE 4MB page */
3222                         context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
3223                 else
3224                         /* 32 bits PSE 4MB page */
3225                         context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
3226                 break;
3227         case PT32E_ROOT_LEVEL:
3228                 context->rsvd_bits_mask[0][2] =
3229                         rsvd_bits(maxphyaddr, 63) |
3230                         rsvd_bits(7, 8) | rsvd_bits(1, 2);      /* PDPTE */
3231                 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3232                         rsvd_bits(maxphyaddr, 62);      /* PDE */
3233                 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3234                         rsvd_bits(maxphyaddr, 62);      /* PTE */
3235                 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3236                         rsvd_bits(maxphyaddr, 62) |
3237                         rsvd_bits(13, 20);              /* large page */
3238                 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3239                 break;
3240         case PT64_ROOT_LEVEL:
3241                 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
3242                         rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3243                 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
3244                         rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3245                 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3246                         rsvd_bits(maxphyaddr, 51);
3247                 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3248                         rsvd_bits(maxphyaddr, 51);
3249                 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
3250                 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
3251                         rsvd_bits(maxphyaddr, 51) |
3252                         rsvd_bits(13, 29);
3253                 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3254                         rsvd_bits(maxphyaddr, 51) |
3255                         rsvd_bits(13, 20);              /* large page */
3256                 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3257                 break;
3258         }
3259 }
3260
3261 static int paging64_init_context_common(struct kvm_vcpu *vcpu,
3262                                         struct kvm_mmu *context,
3263                                         int level)
3264 {
3265         context->nx = is_nx(vcpu);
3266
3267         reset_rsvds_bits_mask(vcpu, context, level);
3268
3269         ASSERT(is_pae(vcpu));
3270         context->new_cr3 = paging_new_cr3;
3271         context->page_fault = paging64_page_fault;
3272         context->gva_to_gpa = paging64_gva_to_gpa;
3273         context->sync_page = paging64_sync_page;
3274         context->invlpg = paging64_invlpg;
3275         context->update_pte = paging64_update_pte;
3276         context->free = paging_free;
3277         context->root_level = level;
3278         context->shadow_root_level = level;
3279         context->root_hpa = INVALID_PAGE;
3280         context->direct_map = false;
3281         return 0;
3282 }
3283
3284 static int paging64_init_context(struct kvm_vcpu *vcpu,
3285                                  struct kvm_mmu *context)
3286 {
3287         return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
3288 }
3289
3290 static int paging32_init_context(struct kvm_vcpu *vcpu,
3291                                  struct kvm_mmu *context)
3292 {
3293         context->nx = false;
3294
3295         reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL);
3296
3297         context->new_cr3 = paging_new_cr3;
3298         context->page_fault = paging32_page_fault;
3299         context->gva_to_gpa = paging32_gva_to_gpa;
3300         context->free = paging_free;
3301         context->sync_page = paging32_sync_page;
3302         context->invlpg = paging32_invlpg;
3303         context->update_pte = paging32_update_pte;
3304         context->root_level = PT32_ROOT_LEVEL;
3305         context->shadow_root_level = PT32E_ROOT_LEVEL;
3306         context->root_hpa = INVALID_PAGE;
3307         context->direct_map = false;
3308         return 0;
3309 }
3310
3311 static int paging32E_init_context(struct kvm_vcpu *vcpu,
3312                                   struct kvm_mmu *context)
3313 {
3314         return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
3315 }
3316
3317 static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
3318 {
3319         struct kvm_mmu *context = vcpu->arch.walk_mmu;
3320
3321         context->base_role.word = 0;
3322         context->new_cr3 = nonpaging_new_cr3;
3323         context->page_fault = tdp_page_fault;
3324         context->free = nonpaging_free;
3325         context->sync_page = nonpaging_sync_page;
3326         context->invlpg = nonpaging_invlpg;
3327         context->update_pte = nonpaging_update_pte;
3328         context->shadow_root_level = kvm_x86_ops->get_tdp_level();
3329         context->root_hpa = INVALID_PAGE;
3330         context->direct_map = true;
3331         context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
3332         context->get_cr3 = get_cr3;
3333         context->get_pdptr = kvm_pdptr_read;
3334         context->inject_page_fault = kvm_inject_page_fault;
3335         context->nx = is_nx(vcpu);
3336
3337         if (!is_paging(vcpu)) {
3338                 context->nx = false;
3339                 context->gva_to_gpa = nonpaging_gva_to_gpa;
3340                 context->root_level = 0;
3341         } else if (is_long_mode(vcpu)) {
3342                 context->nx = is_nx(vcpu);
3343                 reset_rsvds_bits_mask(vcpu, context, PT64_ROOT_LEVEL);
3344                 context->gva_to_gpa = paging64_gva_to_gpa;
3345                 context->root_level = PT64_ROOT_LEVEL;
3346         } else if (is_pae(vcpu)) {
3347                 context->nx = is_nx(vcpu);
3348                 reset_rsvds_bits_mask(vcpu, context, PT32E_ROOT_LEVEL);
3349                 context->gva_to_gpa = paging64_gva_to_gpa;
3350                 context->root_level = PT32E_ROOT_LEVEL;
3351         } else {
3352                 context->nx = false;
3353                 reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL);
3354                 context->gva_to_gpa = paging32_gva_to_gpa;
3355                 context->root_level = PT32_ROOT_LEVEL;
3356         }
3357
3358         return 0;
3359 }
3360
3361 int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
3362 {
3363         int r;
3364         bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3365         ASSERT(vcpu);
3366         ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3367
3368         if (!is_paging(vcpu))
3369                 r = nonpaging_init_context(vcpu, context);
3370         else if (is_long_mode(vcpu))
3371                 r = paging64_init_context(vcpu, context);
3372         else if (is_pae(vcpu))
3373                 r = paging32E_init_context(vcpu, context);
3374         else
3375                 r = paging32_init_context(vcpu, context);
3376
3377         vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu);
3378         vcpu->arch.mmu.base_role.cr0_wp  = is_write_protection(vcpu);
3379         vcpu->arch.mmu.base_role.smep_andnot_wp
3380                 = smep && !is_write_protection(vcpu);
3381
3382         return r;
3383 }
3384 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
3385
3386 static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
3387 {
3388         int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu);
3389
3390         vcpu->arch.walk_mmu->set_cr3           = kvm_x86_ops->set_cr3;
3391         vcpu->arch.walk_mmu->get_cr3           = get_cr3;
3392         vcpu->arch.walk_mmu->get_pdptr         = kvm_pdptr_read;
3393         vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
3394
3395         return r;
3396 }
3397
3398 static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
3399 {
3400         struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
3401
3402         g_context->get_cr3           = get_cr3;
3403         g_context->get_pdptr         = kvm_pdptr_read;
3404         g_context->inject_page_fault = kvm_inject_page_fault;
3405
3406         /*
3407          * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The
3408          * translation of l2_gpa to l1_gpa addresses is done using the
3409          * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa
3410          * functions between mmu and nested_mmu are swapped.
3411          */
3412         if (!is_paging(vcpu)) {
3413                 g_context->nx = false;
3414                 g_context->root_level = 0;
3415                 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
3416         } else if (is_long_mode(vcpu)) {
3417                 g_context->nx = is_nx(vcpu);
3418                 reset_rsvds_bits_mask(vcpu, g_context, PT64_ROOT_LEVEL);
3419                 g_context->root_level = PT64_ROOT_LEVEL;
3420                 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3421         } else if (is_pae(vcpu)) {
3422                 g_context->nx = is_nx(vcpu);
3423                 reset_rsvds_bits_mask(vcpu, g_context, PT32E_ROOT_LEVEL);
3424                 g_context->root_level = PT32E_ROOT_LEVEL;
3425                 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3426         } else {
3427                 g_context->nx = false;
3428                 reset_rsvds_bits_mask(vcpu, g_context, PT32_ROOT_LEVEL);
3429                 g_context->root_level = PT32_ROOT_LEVEL;
3430                 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
3431         }
3432
3433         return 0;
3434 }
3435
3436 static int init_kvm_mmu(struct kvm_vcpu *vcpu)
3437 {
3438         if (mmu_is_nested(vcpu))
3439                 return init_kvm_nested_mmu(vcpu);
3440         else if (tdp_enabled)
3441                 return init_kvm_tdp_mmu(vcpu);
3442         else
3443                 return init_kvm_softmmu(vcpu);
3444 }
3445
3446 static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
3447 {
3448         ASSERT(vcpu);
3449         if (VALID_PAGE(vcpu->arch.mmu.root_hpa))
3450                 /* mmu.free() should set root_hpa = INVALID_PAGE */
3451                 vcpu->arch.mmu.free(vcpu);
3452 }
3453
3454 int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
3455 {
3456         destroy_kvm_mmu(vcpu);
3457         return init_kvm_mmu(vcpu);
3458 }
3459 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
3460
3461 int kvm_mmu_load(struct kvm_vcpu *vcpu)
3462 {
3463         int r;
3464
3465         r = mmu_topup_memory_caches(vcpu);
3466         if (r)
3467                 goto out;
3468         r = mmu_alloc_roots(vcpu);
3469         spin_lock(&vcpu->kvm->mmu_lock);
3470         mmu_sync_roots(vcpu);
3471         spin_unlock(&vcpu->kvm->mmu_lock);
3472         if (r)
3473                 goto out;
3474         /* set_cr3() should ensure TLB has been flushed */
3475         vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
3476 out:
3477         return r;
3478 }
3479 EXPORT_SYMBOL_GPL(kvm_mmu_load);
3480
3481 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
3482 {
3483         mmu_free_roots(vcpu);
3484 }
3485 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
3486
3487 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
3488                                   struct kvm_mmu_page *sp, u64 *spte,
3489                                   const void *new)
3490 {
3491         if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
3492                 ++vcpu->kvm->stat.mmu_pde_zapped;
3493                 return;
3494         }
3495
3496         ++vcpu->kvm->stat.mmu_pte_updated;
3497         vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
3498 }
3499
3500 static bool need_remote_flush(u64 old, u64 new)
3501 {
3502         if (!is_shadow_present_pte(old))
3503                 return false;
3504         if (!is_shadow_present_pte(new))
3505                 return true;
3506         if ((old ^ new) & PT64_BASE_ADDR_MASK)
3507                 return true;
3508         old ^= PT64_NX_MASK;
3509         new ^= PT64_NX_MASK;
3510         return (old & ~new & PT64_PERM_MASK) != 0;
3511 }
3512
3513 static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page,
3514                                     bool remote_flush, bool local_flush)
3515 {
3516         if (zap_page)
3517                 return;
3518
3519         if (remote_flush)
3520                 kvm_flush_remote_tlbs(vcpu->kvm);
3521         else if (local_flush)
3522                 kvm_mmu_flush_tlb(vcpu);
3523 }
3524
3525 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
3526                                     const u8 *new, int *bytes)
3527 {
3528         u64 gentry;
3529         int r;
3530
3531         /*
3532          * Assume that the pte write on a page table of the same type
3533          * as the current vcpu paging mode since we update the sptes only
3534          * when they have the same mode.
3535          */
3536         if (is_pae(vcpu) && *bytes == 4) {
3537                 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
3538                 *gpa &= ~(gpa_t)7;
3539                 *bytes = 8;
3540                 r = kvm_read_guest(vcpu->kvm, *gpa, &gentry, min(*bytes, 8));
3541                 if (r)
3542                         gentry = 0;
3543                 new = (const u8 *)&gentry;
3544         }
3545
3546         switch (*bytes) {
3547         case 4:
3548                 gentry = *(const u32 *)new;
3549                 break;
3550         case 8:
3551                 gentry = *(const u64 *)new;
3552                 break;
3553         default:
3554                 gentry = 0;
3555                 break;
3556         }
3557
3558         return gentry;
3559 }
3560
3561 /*
3562  * If we're seeing too many writes to a page, it may no longer be a page table,
3563  * or we may be forking, in which case it is better to unmap the page.
3564  */
3565 static bool detect_write_flooding(struct kvm_mmu_page *sp, u64 *spte)
3566 {
3567         /*
3568          * Skip write-flooding detected for the sp whose level is 1, because
3569          * it can become unsync, then the guest page is not write-protected.
3570          */
3571         if (sp->role.level == 1)
3572                 return false;
3573
3574         return ++sp->write_flooding_count >= 3;
3575 }
3576
3577 /*
3578  * Misaligned accesses are too much trouble to fix up; also, they usually
3579  * indicate a page is not used as a page table.
3580  */
3581 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
3582                                     int bytes)
3583 {
3584         unsigned offset, pte_size, misaligned;
3585
3586         pgprintk("misaligned: gpa %llx bytes %d role %x\n",
3587                  gpa, bytes, sp->role.word);
3588
3589         offset = offset_in_page(gpa);
3590         pte_size = sp->role.cr4_pae ? 8 : 4;
3591
3592         /*
3593          * Sometimes, the OS only writes the last one bytes to update status
3594          * bits, for example, in linux, andb instruction is used in clear_bit().
3595          */
3596         if (!(offset & (pte_size - 1)) && bytes == 1)
3597                 return false;
3598
3599         misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
3600         misaligned |= bytes < 4;
3601
3602         return misaligned;
3603 }
3604
3605 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
3606 {
3607         unsigned page_offset, quadrant;
3608         u64 *spte;
3609         int level;
3610
3611         page_offset = offset_in_page(gpa);
3612         level = sp->role.level;
3613         *nspte = 1;
3614         if (!sp->role.cr4_pae) {
3615                 page_offset <<= 1;      /* 32->64 */
3616                 /*
3617                  * A 32-bit pde maps 4MB while the shadow pdes map
3618                  * only 2MB.  So we need to double the offset again
3619                  * and zap two pdes instead of one.
3620                  */
3621                 if (level == PT32_ROOT_LEVEL) {
3622                         page_offset &= ~7; /* kill rounding error */
3623                         page_offset <<= 1;
3624                         *nspte = 2;
3625                 }
3626                 quadrant = page_offset >> PAGE_SHIFT;
3627                 page_offset &= ~PAGE_MASK;
3628                 if (quadrant != sp->role.quadrant)
3629                         return NULL;
3630         }
3631
3632         spte = &sp->spt[page_offset / sizeof(*spte)];
3633         return spte;
3634 }
3635
3636 void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
3637                        const u8 *new, int bytes)
3638 {
3639         gfn_t gfn = gpa >> PAGE_SHIFT;
3640         union kvm_mmu_page_role mask = { .word = 0 };
3641         struct kvm_mmu_page *sp;
3642         struct hlist_node *node;
3643         LIST_HEAD(invalid_list);
3644         u64 entry, gentry, *spte;
3645         int npte;
3646         bool remote_flush, local_flush, zap_page;
3647
3648         /*
3649          * If we don't have indirect shadow pages, it means no page is
3650          * write-protected, so we can exit simply.
3651          */
3652         if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
3653                 return;
3654
3655         zap_page = remote_flush = local_flush = false;
3656
3657         pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
3658
3659         gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes);
3660
3661         /*
3662          * No need to care whether allocation memory is successful
3663          * or not since pte prefetch is skiped if it does not have
3664          * enough objects in the cache.
3665          */
3666         mmu_topup_memory_caches(vcpu);
3667
3668         spin_lock(&vcpu->kvm->mmu_lock);
3669         ++vcpu->kvm->stat.mmu_pte_write;
3670         trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
3671
3672         mask.cr0_wp = mask.cr4_pae = mask.nxe = 1;
3673         for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) {
3674                 spte = get_written_sptes(sp, gpa, &npte);
3675
3676                 if (detect_write_misaligned(sp, gpa, bytes) ||
3677                       detect_write_flooding(sp, spte)) {
3678                         zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
3679                                                      &invalid_list);
3680                         ++vcpu->kvm->stat.mmu_flooded;
3681                         continue;
3682                 }
3683
3684                 spte = get_written_sptes(sp, gpa, &npte);
3685                 if (!spte)
3686                         continue;
3687
3688                 local_flush = true;
3689                 while (npte--) {
3690                         entry = *spte;
3691                         mmu_page_zap_pte(vcpu->kvm, sp, spte);
3692                         if (gentry &&
3693                               !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
3694                               & mask.word) && rmap_can_add(vcpu))
3695                                 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
3696                         if (!remote_flush && need_remote_flush(entry, *spte))
3697                                 remote_flush = true;
3698                         ++spte;
3699                 }
3700         }
3701         mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush);
3702         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3703         trace_kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
3704         spin_unlock(&vcpu->kvm->mmu_lock);
3705 }
3706
3707 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
3708 {
3709         gpa_t gpa;
3710         int r;
3711
3712         if (vcpu->arch.mmu.direct_map)
3713                 return 0;
3714
3715         gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
3716
3717         r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
3718
3719         return r;
3720 }
3721 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
3722
3723 void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
3724 {
3725         LIST_HEAD(invalid_list);
3726
3727         while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES &&
3728                !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
3729                 struct kvm_mmu_page *sp;
3730
3731                 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
3732                                   struct kvm_mmu_page, link);
3733                 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
3734                 ++vcpu->kvm->stat.mmu_recycled;
3735         }
3736         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3737 }
3738
3739 static bool is_mmio_page_fault(struct kvm_vcpu *vcpu, gva_t addr)
3740 {
3741         if (vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu))
3742                 return vcpu_match_mmio_gpa(vcpu, addr);
3743
3744         return vcpu_match_mmio_gva(vcpu, addr);
3745 }
3746
3747 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code,
3748                        void *insn, int insn_len)
3749 {
3750         int r, emulation_type = EMULTYPE_RETRY;
3751         enum emulation_result er;
3752
3753         r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false);
3754         if (r < 0)
3755                 goto out;
3756
3757         if (!r) {
3758                 r = 1;
3759                 goto out;
3760         }
3761
3762         if (is_mmio_page_fault(vcpu, cr2))
3763                 emulation_type = 0;
3764
3765         er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len);
3766
3767         switch (er) {
3768         case EMULATE_DONE:
3769                 return 1;
3770         case EMULATE_DO_MMIO:
3771                 ++vcpu->stat.mmio_exits;
3772                 /* fall through */
3773         case EMULATE_FAIL:
3774                 return 0;
3775         default:
3776                 BUG();
3777         }
3778 out:
3779         return r;
3780 }
3781 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
3782
3783 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
3784 {
3785         vcpu->arch.mmu.invlpg(vcpu, gva);
3786         kvm_mmu_flush_tlb(vcpu);
3787         ++vcpu->stat.invlpg;
3788 }
3789 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
3790
3791 void kvm_enable_tdp(void)
3792 {
3793         tdp_enabled = true;
3794 }
3795 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
3796
3797 void kvm_disable_tdp(void)
3798 {
3799         tdp_enabled = false;
3800 }
3801 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
3802
3803 static void free_mmu_pages(struct kvm_vcpu *vcpu)
3804 {
3805         free_page((unsigned long)vcpu->arch.mmu.pae_root);
3806         if (vcpu->arch.mmu.lm_root != NULL)
3807                 free_page((unsigned long)vcpu->arch.mmu.lm_root);
3808 }
3809
3810 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
3811 {
3812         struct page *page;
3813         int i;
3814
3815         ASSERT(vcpu);
3816
3817         /*
3818          * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
3819          * Therefore we need to allocate shadow page tables in the first
3820          * 4GB of memory, which happens to fit the DMA32 zone.
3821          */
3822         page = alloc_page(GFP_KERNEL | __GFP_DMA32);
3823         if (!page)
3824                 return -ENOMEM;
3825
3826         vcpu->arch.mmu.pae_root = page_address(page);
3827         for (i = 0; i < 4; ++i)
3828                 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
3829
3830         return 0;
3831 }
3832
3833 int kvm_mmu_create(struct kvm_vcpu *vcpu)
3834 {
3835         ASSERT(vcpu);
3836         ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3837
3838         return alloc_mmu_pages(vcpu);
3839 }
3840
3841 int kvm_mmu_setup(struct kvm_vcpu *vcpu)
3842 {
3843         ASSERT(vcpu);
3844         ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3845
3846         return init_kvm_mmu(vcpu);
3847 }
3848
3849 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
3850 {
3851         struct kvm_mmu_page *sp;
3852
3853         list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
3854                 int i;
3855                 u64 *pt;
3856
3857                 if (!test_bit(slot, sp->slot_bitmap))
3858                         continue;
3859
3860                 pt = sp->spt;
3861                 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3862                         if (!is_shadow_present_pte(pt[i]) ||
3863                               !is_last_spte(pt[i], sp->role.level))
3864                                 continue;
3865
3866                         if (is_large_pte(pt[i])) {
3867                                 drop_spte(kvm, &pt[i]);
3868                                 --kvm->stat.lpages;
3869                                 continue;
3870                         }
3871
3872                         /* avoid RMW */
3873                         if (is_writable_pte(pt[i]))
3874                                 mmu_spte_update(&pt[i],
3875                                                 pt[i] & ~PT_WRITABLE_MASK);
3876                 }
3877         }
3878         kvm_flush_remote_tlbs(kvm);
3879 }
3880
3881 void kvm_mmu_zap_all(struct kvm *kvm)
3882 {
3883         struct kvm_mmu_page *sp, *node;
3884         LIST_HEAD(invalid_list);
3885
3886         spin_lock(&kvm->mmu_lock);
3887 restart:
3888         list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
3889                 if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list))
3890                         goto restart;
3891
3892         kvm_mmu_commit_zap_page(kvm, &invalid_list);
3893         spin_unlock(&kvm->mmu_lock);
3894 }
3895
3896 static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm,
3897                                                struct list_head *invalid_list)
3898 {
3899         struct kvm_mmu_page *page;
3900
3901         page = container_of(kvm->arch.active_mmu_pages.prev,
3902                             struct kvm_mmu_page, link);
3903         return kvm_mmu_prepare_zap_page(kvm, page, invalid_list);
3904 }
3905
3906 static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc)
3907 {
3908         struct kvm *kvm;
3909         struct kvm *kvm_freed = NULL;
3910         int nr_to_scan = sc->nr_to_scan;
3911
3912         if (nr_to_scan == 0)
3913                 goto out;
3914
3915         raw_spin_lock(&kvm_lock);
3916
3917         list_for_each_entry(kvm, &vm_list, vm_list) {
3918                 int idx, freed_pages;
3919                 LIST_HEAD(invalid_list);
3920
3921                 idx = srcu_read_lock(&kvm->srcu);
3922                 spin_lock(&kvm->mmu_lock);
3923                 if (!kvm_freed && nr_to_scan > 0 &&
3924                     kvm->arch.n_used_mmu_pages > 0) {
3925                         freed_pages = kvm_mmu_remove_some_alloc_mmu_pages(kvm,
3926                                                           &invalid_list);
3927                         kvm_freed = kvm;
3928                 }
3929                 nr_to_scan--;
3930
3931                 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3932                 spin_unlock(&kvm->mmu_lock);
3933                 srcu_read_unlock(&kvm->srcu, idx);
3934         }
3935         if (kvm_freed)
3936                 list_move_tail(&kvm_freed->vm_list, &vm_list);
3937
3938         raw_spin_unlock(&kvm_lock);
3939
3940 out:
3941         return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
3942 }
3943
3944 static struct shrinker mmu_shrinker = {
3945         .shrink = mmu_shrink,
3946         .seeks = DEFAULT_SEEKS * 10,
3947 };
3948
3949 static void mmu_destroy_caches(void)
3950 {
3951         if (pte_list_desc_cache)
3952                 kmem_cache_destroy(pte_list_desc_cache);
3953         if (mmu_page_header_cache)
3954                 kmem_cache_destroy(mmu_page_header_cache);
3955 }
3956
3957 int kvm_mmu_module_init(void)
3958 {
3959         pte_list_desc_cache = kmem_cache_create("pte_list_desc",
3960                                             sizeof(struct pte_list_desc),
3961                                             0, 0, NULL);
3962         if (!pte_list_desc_cache)
3963                 goto nomem;
3964
3965         mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
3966                                                   sizeof(struct kvm_mmu_page),
3967                                                   0, 0, NULL);
3968         if (!mmu_page_header_cache)
3969                 goto nomem;
3970
3971         if (percpu_counter_init(&kvm_total_used_mmu_pages, 0))
3972                 goto nomem;
3973
3974         register_shrinker(&mmu_shrinker);
3975
3976         return 0;
3977
3978 nomem:
3979         mmu_destroy_caches();
3980         return -ENOMEM;
3981 }
3982
3983 /*
3984  * Caculate mmu pages needed for kvm.
3985  */
3986 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
3987 {
3988         int i;
3989         unsigned int nr_mmu_pages;
3990         unsigned int  nr_pages = 0;
3991         struct kvm_memslots *slots;
3992
3993         slots = kvm_memslots(kvm);
3994
3995         for (i = 0; i < slots->nmemslots; i++)
3996                 nr_pages += slots->memslots[i].npages;
3997
3998         nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
3999         nr_mmu_pages = max(nr_mmu_pages,
4000                         (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
4001
4002         return nr_mmu_pages;
4003 }
4004
4005 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
4006 {
4007         struct kvm_shadow_walk_iterator iterator;
4008         u64 spte;
4009         int nr_sptes = 0;
4010
4011         walk_shadow_page_lockless_begin(vcpu);
4012         for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
4013                 sptes[iterator.level-1] = spte;
4014                 nr_sptes++;
4015                 if (!is_shadow_present_pte(spte))
4016                         break;
4017         }
4018         walk_shadow_page_lockless_end(vcpu);
4019
4020         return nr_sptes;
4021 }
4022 EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
4023
4024 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
4025 {
4026         ASSERT(vcpu);
4027
4028         destroy_kvm_mmu(vcpu);
4029         free_mmu_pages(vcpu);
4030         mmu_free_memory_caches(vcpu);
4031 }
4032
4033 #ifdef CONFIG_KVM_MMU_AUDIT
4034 #include "mmu_audit.c"
4035 #else
4036 static void mmu_audit_disable(void) { }
4037 #endif
4038
4039 void kvm_mmu_module_exit(void)
4040 {
4041         mmu_destroy_caches();
4042         percpu_counter_destroy(&kvm_total_used_mmu_pages);
4043         unregister_shrinker(&mmu_shrinker);
4044         mmu_audit_disable();
4045 }