2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
26 #include <linux/kvm_host.h>
27 #include <linux/types.h>
28 #include <linux/string.h>
30 #include <linux/highmem.h>
31 #include <linux/module.h>
32 #include <linux/swap.h>
33 #include <linux/hugetlb.h>
34 #include <linux/compiler.h>
35 #include <linux/srcu.h>
36 #include <linux/slab.h>
37 #include <linux/uaccess.h>
40 #include <asm/cmpxchg.h>
45 * When setting this variable to true it enables Two-Dimensional-Paging
46 * where the hardware walks 2 page tables:
47 * 1. the guest-virtual to guest-physical
48 * 2. while doing 1. it walks guest-physical to host-physical
49 * If the hardware supports that we don't need to do shadow paging.
51 bool tdp_enabled = false;
55 AUDIT_POST_PAGE_FAULT,
66 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
67 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
71 #define pgprintk(x...) do { } while (0)
72 #define rmap_printk(x...) do { } while (0)
78 module_param(dbg, bool, 0644);
82 #define ASSERT(x) do { } while (0)
86 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
87 __FILE__, __LINE__, #x); \
91 #define PTE_PREFETCH_NUM 8
93 #define PT_FIRST_AVAIL_BITS_SHIFT 9
94 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
96 #define PT64_LEVEL_BITS 9
98 #define PT64_LEVEL_SHIFT(level) \
99 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
101 #define PT64_INDEX(address, level)\
102 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
105 #define PT32_LEVEL_BITS 10
107 #define PT32_LEVEL_SHIFT(level) \
108 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
110 #define PT32_LVL_OFFSET_MASK(level) \
111 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
112 * PT32_LEVEL_BITS))) - 1))
114 #define PT32_INDEX(address, level)\
115 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
118 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
119 #define PT64_DIR_BASE_ADDR_MASK \
120 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
121 #define PT64_LVL_ADDR_MASK(level) \
122 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
123 * PT64_LEVEL_BITS))) - 1))
124 #define PT64_LVL_OFFSET_MASK(level) \
125 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
126 * PT64_LEVEL_BITS))) - 1))
128 #define PT32_BASE_ADDR_MASK PAGE_MASK
129 #define PT32_DIR_BASE_ADDR_MASK \
130 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
131 #define PT32_LVL_ADDR_MASK(level) \
132 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
133 * PT32_LEVEL_BITS))) - 1))
135 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
138 #define ACC_EXEC_MASK 1
139 #define ACC_WRITE_MASK PT_WRITABLE_MASK
140 #define ACC_USER_MASK PT_USER_MASK
141 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
143 #include <trace/events/kvm.h>
145 #define CREATE_TRACE_POINTS
146 #include "mmutrace.h"
148 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
150 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
152 /* make pte_list_desc fit well in cache line */
153 #define PTE_LIST_EXT 3
155 struct pte_list_desc {
156 u64 *sptes[PTE_LIST_EXT];
157 struct pte_list_desc *more;
160 struct kvm_shadow_walk_iterator {
168 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
169 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
170 shadow_walk_okay(&(_walker)); \
171 shadow_walk_next(&(_walker)))
173 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
174 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
175 shadow_walk_okay(&(_walker)) && \
176 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
177 __shadow_walk_next(&(_walker), spte))
179 static struct kmem_cache *pte_list_desc_cache;
180 static struct kmem_cache *mmu_page_header_cache;
181 static struct percpu_counter kvm_total_used_mmu_pages;
183 static u64 __read_mostly shadow_nx_mask;
184 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
185 static u64 __read_mostly shadow_user_mask;
186 static u64 __read_mostly shadow_accessed_mask;
187 static u64 __read_mostly shadow_dirty_mask;
188 static u64 __read_mostly shadow_mmio_mask;
190 static void mmu_spte_set(u64 *sptep, u64 spte);
192 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask)
194 shadow_mmio_mask = mmio_mask;
196 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
198 static void mark_mmio_spte(u64 *sptep, u64 gfn, unsigned access)
200 access &= ACC_WRITE_MASK | ACC_USER_MASK;
202 trace_mark_mmio_spte(sptep, gfn, access);
203 mmu_spte_set(sptep, shadow_mmio_mask | access | gfn << PAGE_SHIFT);
206 static bool is_mmio_spte(u64 spte)
208 return (spte & shadow_mmio_mask) == shadow_mmio_mask;
211 static gfn_t get_mmio_spte_gfn(u64 spte)
213 return (spte & ~shadow_mmio_mask) >> PAGE_SHIFT;
216 static unsigned get_mmio_spte_access(u64 spte)
218 return (spte & ~shadow_mmio_mask) & ~PAGE_MASK;
221 static bool set_mmio_spte(u64 *sptep, gfn_t gfn, pfn_t pfn, unsigned access)
223 if (unlikely(is_noslot_pfn(pfn))) {
224 mark_mmio_spte(sptep, gfn, access);
231 static inline u64 rsvd_bits(int s, int e)
233 return ((1ULL << (e - s + 1)) - 1) << s;
236 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
237 u64 dirty_mask, u64 nx_mask, u64 x_mask)
239 shadow_user_mask = user_mask;
240 shadow_accessed_mask = accessed_mask;
241 shadow_dirty_mask = dirty_mask;
242 shadow_nx_mask = nx_mask;
243 shadow_x_mask = x_mask;
245 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
247 static int is_cpuid_PSE36(void)
252 static int is_nx(struct kvm_vcpu *vcpu)
254 return vcpu->arch.efer & EFER_NX;
257 static int is_shadow_present_pte(u64 pte)
259 return pte & PT_PRESENT_MASK && !is_mmio_spte(pte);
262 static int is_large_pte(u64 pte)
264 return pte & PT_PAGE_SIZE_MASK;
267 static int is_dirty_gpte(unsigned long pte)
269 return pte & PT_DIRTY_MASK;
272 static int is_rmap_spte(u64 pte)
274 return is_shadow_present_pte(pte);
277 static int is_last_spte(u64 pte, int level)
279 if (level == PT_PAGE_TABLE_LEVEL)
281 if (is_large_pte(pte))
286 static pfn_t spte_to_pfn(u64 pte)
288 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
291 static gfn_t pse36_gfn_delta(u32 gpte)
293 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
295 return (gpte & PT32_DIR_PSE36_MASK) << shift;
299 static void __set_spte(u64 *sptep, u64 spte)
304 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
309 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
311 return xchg(sptep, spte);
314 static u64 __get_spte_lockless(u64 *sptep)
316 return ACCESS_ONCE(*sptep);
319 static bool __check_direct_spte_mmio_pf(u64 spte)
321 /* It is valid if the spte is zapped. */
333 static void count_spte_clear(u64 *sptep, u64 spte)
335 struct kvm_mmu_page *sp = page_header(__pa(sptep));
337 if (is_shadow_present_pte(spte))
340 /* Ensure the spte is completely set before we increase the count */
342 sp->clear_spte_count++;
345 static void __set_spte(u64 *sptep, u64 spte)
347 union split_spte *ssptep, sspte;
349 ssptep = (union split_spte *)sptep;
350 sspte = (union split_spte)spte;
352 ssptep->spte_high = sspte.spte_high;
355 * If we map the spte from nonpresent to present, We should store
356 * the high bits firstly, then set present bit, so cpu can not
357 * fetch this spte while we are setting the spte.
361 ssptep->spte_low = sspte.spte_low;
364 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
366 union split_spte *ssptep, sspte;
368 ssptep = (union split_spte *)sptep;
369 sspte = (union split_spte)spte;
371 ssptep->spte_low = sspte.spte_low;
374 * If we map the spte from present to nonpresent, we should clear
375 * present bit firstly to avoid vcpu fetch the old high bits.
379 ssptep->spte_high = sspte.spte_high;
380 count_spte_clear(sptep, spte);
383 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
385 union split_spte *ssptep, sspte, orig;
387 ssptep = (union split_spte *)sptep;
388 sspte = (union split_spte)spte;
390 /* xchg acts as a barrier before the setting of the high bits */
391 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
392 orig.spte_high = ssptep->spte_high;
393 ssptep->spte_high = sspte.spte_high;
394 count_spte_clear(sptep, spte);
400 * The idea using the light way get the spte on x86_32 guest is from
401 * gup_get_pte(arch/x86/mm/gup.c).
402 * The difference is we can not catch the spte tlb flush if we leave
403 * guest mode, so we emulate it by increase clear_spte_count when spte
406 static u64 __get_spte_lockless(u64 *sptep)
408 struct kvm_mmu_page *sp = page_header(__pa(sptep));
409 union split_spte spte, *orig = (union split_spte *)sptep;
413 count = sp->clear_spte_count;
416 spte.spte_low = orig->spte_low;
419 spte.spte_high = orig->spte_high;
422 if (unlikely(spte.spte_low != orig->spte_low ||
423 count != sp->clear_spte_count))
429 static bool __check_direct_spte_mmio_pf(u64 spte)
431 union split_spte sspte = (union split_spte)spte;
432 u32 high_mmio_mask = shadow_mmio_mask >> 32;
434 /* It is valid if the spte is zapped. */
438 /* It is valid if the spte is being zapped. */
439 if (sspte.spte_low == 0ull &&
440 (sspte.spte_high & high_mmio_mask) == high_mmio_mask)
447 static bool spte_has_volatile_bits(u64 spte)
449 if (!shadow_accessed_mask)
452 if (!is_shadow_present_pte(spte))
455 if ((spte & shadow_accessed_mask) &&
456 (!is_writable_pte(spte) || (spte & shadow_dirty_mask)))
462 static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask)
464 return (old_spte & bit_mask) && !(new_spte & bit_mask);
467 /* Rules for using mmu_spte_set:
468 * Set the sptep from nonpresent to present.
469 * Note: the sptep being assigned *must* be either not present
470 * or in a state where the hardware will not attempt to update
473 static void mmu_spte_set(u64 *sptep, u64 new_spte)
475 WARN_ON(is_shadow_present_pte(*sptep));
476 __set_spte(sptep, new_spte);
479 /* Rules for using mmu_spte_update:
480 * Update the state bits, it means the mapped pfn is not changged.
482 static void mmu_spte_update(u64 *sptep, u64 new_spte)
484 u64 mask, old_spte = *sptep;
486 WARN_ON(!is_rmap_spte(new_spte));
488 if (!is_shadow_present_pte(old_spte))
489 return mmu_spte_set(sptep, new_spte);
491 new_spte |= old_spte & shadow_dirty_mask;
493 mask = shadow_accessed_mask;
494 if (is_writable_pte(old_spte))
495 mask |= shadow_dirty_mask;
497 if (!spte_has_volatile_bits(old_spte) || (new_spte & mask) == mask)
498 __update_clear_spte_fast(sptep, new_spte);
500 old_spte = __update_clear_spte_slow(sptep, new_spte);
502 if (!shadow_accessed_mask)
505 if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask))
506 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
507 if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask))
508 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
512 * Rules for using mmu_spte_clear_track_bits:
513 * It sets the sptep from present to nonpresent, and track the
514 * state bits, it is used to clear the last level sptep.
516 static int mmu_spte_clear_track_bits(u64 *sptep)
519 u64 old_spte = *sptep;
521 if (!spte_has_volatile_bits(old_spte))
522 __update_clear_spte_fast(sptep, 0ull);
524 old_spte = __update_clear_spte_slow(sptep, 0ull);
526 if (!is_rmap_spte(old_spte))
529 pfn = spte_to_pfn(old_spte);
530 if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
531 kvm_set_pfn_accessed(pfn);
532 if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask))
533 kvm_set_pfn_dirty(pfn);
538 * Rules for using mmu_spte_clear_no_track:
539 * Directly clear spte without caring the state bits of sptep,
540 * it is used to set the upper level spte.
542 static void mmu_spte_clear_no_track(u64 *sptep)
544 __update_clear_spte_fast(sptep, 0ull);
547 static u64 mmu_spte_get_lockless(u64 *sptep)
549 return __get_spte_lockless(sptep);
552 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
555 * Prevent page table teardown by making any free-er wait during
556 * kvm_flush_remote_tlbs() IPI to all active vcpus.
559 vcpu->mode = READING_SHADOW_PAGE_TABLES;
561 * Make sure a following spte read is not reordered ahead of the write
567 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
570 * Make sure the write to vcpu->mode is not reordered in front of
571 * reads to sptes. If it does, kvm_commit_zap_page() can see us
572 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
575 vcpu->mode = OUTSIDE_GUEST_MODE;
579 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
580 struct kmem_cache *base_cache, int min)
584 if (cache->nobjs >= min)
586 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
587 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
590 cache->objects[cache->nobjs++] = obj;
595 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
600 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
601 struct kmem_cache *cache)
604 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
607 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
612 if (cache->nobjs >= min)
614 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
615 page = (void *)__get_free_page(GFP_KERNEL);
618 cache->objects[cache->nobjs++] = page;
623 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
626 free_page((unsigned long)mc->objects[--mc->nobjs]);
629 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
633 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
634 pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
637 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
640 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
641 mmu_page_header_cache, 4);
646 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
648 mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
649 pte_list_desc_cache);
650 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
651 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
652 mmu_page_header_cache);
655 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
661 p = mc->objects[--mc->nobjs];
665 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
667 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache,
668 sizeof(struct pte_list_desc));
671 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
673 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
676 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
678 if (!sp->role.direct)
679 return sp->gfns[index];
681 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
684 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
687 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
689 sp->gfns[index] = gfn;
693 * Return the pointer to the large page information for a given gfn,
694 * handling slots that are not large page aligned.
696 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
697 struct kvm_memory_slot *slot,
702 idx = gfn_to_index(gfn, slot->base_gfn, level);
703 return &slot->arch.lpage_info[level - 2][idx];
706 static void account_shadowed(struct kvm *kvm, gfn_t gfn)
708 struct kvm_memory_slot *slot;
709 struct kvm_lpage_info *linfo;
712 slot = gfn_to_memslot(kvm, gfn);
713 for (i = PT_DIRECTORY_LEVEL;
714 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
715 linfo = lpage_info_slot(gfn, slot, i);
716 linfo->write_count += 1;
718 kvm->arch.indirect_shadow_pages++;
721 static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
723 struct kvm_memory_slot *slot;
724 struct kvm_lpage_info *linfo;
727 slot = gfn_to_memslot(kvm, gfn);
728 for (i = PT_DIRECTORY_LEVEL;
729 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
730 linfo = lpage_info_slot(gfn, slot, i);
731 linfo->write_count -= 1;
732 WARN_ON(linfo->write_count < 0);
734 kvm->arch.indirect_shadow_pages--;
737 static int has_wrprotected_page(struct kvm *kvm,
741 struct kvm_memory_slot *slot;
742 struct kvm_lpage_info *linfo;
744 slot = gfn_to_memslot(kvm, gfn);
746 linfo = lpage_info_slot(gfn, slot, level);
747 return linfo->write_count;
753 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
755 unsigned long page_size;
758 page_size = kvm_host_page_size(kvm, gfn);
760 for (i = PT_PAGE_TABLE_LEVEL;
761 i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
762 if (page_size >= KVM_HPAGE_SIZE(i))
771 static struct kvm_memory_slot *
772 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
775 struct kvm_memory_slot *slot;
777 slot = gfn_to_memslot(vcpu->kvm, gfn);
778 if (!slot || slot->flags & KVM_MEMSLOT_INVALID ||
779 (no_dirty_log && slot->dirty_bitmap))
785 static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn)
787 return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true);
790 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
792 int host_level, level, max_level;
794 host_level = host_mapping_level(vcpu->kvm, large_gfn);
796 if (host_level == PT_PAGE_TABLE_LEVEL)
799 max_level = kvm_x86_ops->get_lpage_level() < host_level ?
800 kvm_x86_ops->get_lpage_level() : host_level;
802 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
803 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
810 * Pte mapping structures:
812 * If pte_list bit zero is zero, then pte_list point to the spte.
814 * If pte_list bit zero is one, (then pte_list & ~1) points to a struct
815 * pte_list_desc containing more mappings.
817 * Returns the number of pte entries before the spte was added or zero if
818 * the spte was not added.
821 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
822 unsigned long *pte_list)
824 struct pte_list_desc *desc;
828 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
829 *pte_list = (unsigned long)spte;
830 } else if (!(*pte_list & 1)) {
831 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
832 desc = mmu_alloc_pte_list_desc(vcpu);
833 desc->sptes[0] = (u64 *)*pte_list;
834 desc->sptes[1] = spte;
835 *pte_list = (unsigned long)desc | 1;
838 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
839 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
840 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
842 count += PTE_LIST_EXT;
844 if (desc->sptes[PTE_LIST_EXT-1]) {
845 desc->more = mmu_alloc_pte_list_desc(vcpu);
848 for (i = 0; desc->sptes[i]; ++i)
850 desc->sptes[i] = spte;
856 pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc,
857 int i, struct pte_list_desc *prev_desc)
861 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
863 desc->sptes[i] = desc->sptes[j];
864 desc->sptes[j] = NULL;
867 if (!prev_desc && !desc->more)
868 *pte_list = (unsigned long)desc->sptes[0];
871 prev_desc->more = desc->more;
873 *pte_list = (unsigned long)desc->more | 1;
874 mmu_free_pte_list_desc(desc);
877 static void pte_list_remove(u64 *spte, unsigned long *pte_list)
879 struct pte_list_desc *desc;
880 struct pte_list_desc *prev_desc;
884 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
886 } else if (!(*pte_list & 1)) {
887 rmap_printk("pte_list_remove: %p 1->0\n", spte);
888 if ((u64 *)*pte_list != spte) {
889 printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte);
894 rmap_printk("pte_list_remove: %p many->many\n", spte);
895 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
898 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
899 if (desc->sptes[i] == spte) {
900 pte_list_desc_remove_entry(pte_list,
908 pr_err("pte_list_remove: %p many->many\n", spte);
913 typedef void (*pte_list_walk_fn) (u64 *spte);
914 static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn)
916 struct pte_list_desc *desc;
922 if (!(*pte_list & 1))
923 return fn((u64 *)*pte_list);
925 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
927 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
933 static unsigned long *__gfn_to_rmap(gfn_t gfn, int level,
934 struct kvm_memory_slot *slot)
936 struct kvm_lpage_info *linfo;
938 if (likely(level == PT_PAGE_TABLE_LEVEL))
939 return &slot->rmap[gfn - slot->base_gfn];
941 linfo = lpage_info_slot(gfn, slot, level);
942 return &linfo->rmap_pde;
946 * Take gfn and return the reverse mapping to it.
948 static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
950 struct kvm_memory_slot *slot;
952 slot = gfn_to_memslot(kvm, gfn);
953 return __gfn_to_rmap(gfn, level, slot);
956 static bool rmap_can_add(struct kvm_vcpu *vcpu)
958 struct kvm_mmu_memory_cache *cache;
960 cache = &vcpu->arch.mmu_pte_list_desc_cache;
961 return mmu_memory_cache_free_objects(cache);
964 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
966 struct kvm_mmu_page *sp;
967 unsigned long *rmapp;
969 sp = page_header(__pa(spte));
970 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
971 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
972 return pte_list_add(vcpu, spte, rmapp);
975 static void rmap_remove(struct kvm *kvm, u64 *spte)
977 struct kvm_mmu_page *sp;
979 unsigned long *rmapp;
981 sp = page_header(__pa(spte));
982 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
983 rmapp = gfn_to_rmap(kvm, gfn, sp->role.level);
984 pte_list_remove(spte, rmapp);
988 * Used by the following functions to iterate through the sptes linked by a
989 * rmap. All fields are private and not assumed to be used outside.
991 struct rmap_iterator {
993 struct pte_list_desc *desc; /* holds the sptep if not NULL */
994 int pos; /* index of the sptep */
998 * Iteration must be started by this function. This should also be used after
999 * removing/dropping sptes from the rmap link because in such cases the
1000 * information in the itererator may not be valid.
1002 * Returns sptep if found, NULL otherwise.
1004 static u64 *rmap_get_first(unsigned long rmap, struct rmap_iterator *iter)
1014 iter->desc = (struct pte_list_desc *)(rmap & ~1ul);
1016 return iter->desc->sptes[iter->pos];
1020 * Must be used with a valid iterator: e.g. after rmap_get_first().
1022 * Returns sptep if found, NULL otherwise.
1024 static u64 *rmap_get_next(struct rmap_iterator *iter)
1027 if (iter->pos < PTE_LIST_EXT - 1) {
1031 sptep = iter->desc->sptes[iter->pos];
1036 iter->desc = iter->desc->more;
1040 /* desc->sptes[0] cannot be NULL */
1041 return iter->desc->sptes[iter->pos];
1048 static void drop_spte(struct kvm *kvm, u64 *sptep)
1050 if (mmu_spte_clear_track_bits(sptep))
1051 rmap_remove(kvm, sptep);
1054 static int __rmap_write_protect(struct kvm *kvm, unsigned long *rmapp, int level)
1057 struct rmap_iterator iter;
1058 int write_protected = 0;
1060 for (sptep = rmap_get_first(*rmapp, &iter); sptep;) {
1061 BUG_ON(!(*sptep & PT_PRESENT_MASK));
1062 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1064 if (!is_writable_pte(*sptep)) {
1065 sptep = rmap_get_next(&iter);
1069 if (level == PT_PAGE_TABLE_LEVEL) {
1070 mmu_spte_update(sptep, *sptep & ~PT_WRITABLE_MASK);
1071 sptep = rmap_get_next(&iter);
1073 BUG_ON(!is_large_pte(*sptep));
1074 drop_spte(kvm, sptep);
1076 sptep = rmap_get_first(*rmapp, &iter);
1079 write_protected = 1;
1082 return write_protected;
1086 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1087 * @kvm: kvm instance
1088 * @slot: slot to protect
1089 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1090 * @mask: indicates which pages we should protect
1092 * Used when we do not need to care about huge page mappings: e.g. during dirty
1093 * logging we do not have any such mappings.
1095 void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1096 struct kvm_memory_slot *slot,
1097 gfn_t gfn_offset, unsigned long mask)
1099 unsigned long *rmapp;
1102 rmapp = &slot->rmap[gfn_offset + __ffs(mask)];
1103 __rmap_write_protect(kvm, rmapp, PT_PAGE_TABLE_LEVEL);
1105 /* clear the first set bit */
1110 static int rmap_write_protect(struct kvm *kvm, u64 gfn)
1112 struct kvm_memory_slot *slot;
1113 unsigned long *rmapp;
1115 int write_protected = 0;
1117 slot = gfn_to_memslot(kvm, gfn);
1119 for (i = PT_PAGE_TABLE_LEVEL;
1120 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
1121 rmapp = __gfn_to_rmap(gfn, i, slot);
1122 write_protected |= __rmap_write_protect(kvm, rmapp, i);
1125 return write_protected;
1128 static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
1132 struct rmap_iterator iter;
1133 int need_tlb_flush = 0;
1135 while ((sptep = rmap_get_first(*rmapp, &iter))) {
1136 BUG_ON(!(*sptep & PT_PRESENT_MASK));
1137 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", sptep, *sptep);
1139 drop_spte(kvm, sptep);
1143 return need_tlb_flush;
1146 static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
1150 struct rmap_iterator iter;
1153 pte_t *ptep = (pte_t *)data;
1156 WARN_ON(pte_huge(*ptep));
1157 new_pfn = pte_pfn(*ptep);
1159 for (sptep = rmap_get_first(*rmapp, &iter); sptep;) {
1160 BUG_ON(!is_shadow_present_pte(*sptep));
1161 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", sptep, *sptep);
1165 if (pte_write(*ptep)) {
1166 drop_spte(kvm, sptep);
1167 sptep = rmap_get_first(*rmapp, &iter);
1169 new_spte = *sptep & ~PT64_BASE_ADDR_MASK;
1170 new_spte |= (u64)new_pfn << PAGE_SHIFT;
1172 new_spte &= ~PT_WRITABLE_MASK;
1173 new_spte &= ~SPTE_HOST_WRITEABLE;
1174 new_spte &= ~shadow_accessed_mask;
1176 mmu_spte_clear_track_bits(sptep);
1177 mmu_spte_set(sptep, new_spte);
1178 sptep = rmap_get_next(&iter);
1183 kvm_flush_remote_tlbs(kvm);
1188 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1190 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
1191 unsigned long data))
1196 struct kvm_memslots *slots;
1197 struct kvm_memory_slot *memslot;
1199 slots = kvm_memslots(kvm);
1201 kvm_for_each_memslot(memslot, slots) {
1202 unsigned long start = memslot->userspace_addr;
1205 end = start + (memslot->npages << PAGE_SHIFT);
1206 if (hva >= start && hva < end) {
1207 gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT;
1208 gfn_t gfn = memslot->base_gfn + gfn_offset;
1210 ret = handler(kvm, &memslot->rmap[gfn_offset], data);
1212 for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) {
1213 struct kvm_lpage_info *linfo;
1215 linfo = lpage_info_slot(gfn, memslot,
1216 PT_DIRECTORY_LEVEL + j);
1217 ret |= handler(kvm, &linfo->rmap_pde, data);
1219 trace_kvm_age_page(hva, memslot, ret);
1227 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
1229 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
1232 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1234 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1237 static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1241 struct rmap_iterator uninitialized_var(iter);
1245 * In case of absence of EPT Access and Dirty Bits supports,
1246 * emulate the accessed bit for EPT, by checking if this page has
1247 * an EPT mapping, and clearing it if it does. On the next access,
1248 * a new EPT mapping will be established.
1249 * This has some overhead, but not as much as the cost of swapping
1250 * out actively used pages or breaking up actively used hugepages.
1252 if (!shadow_accessed_mask)
1253 return kvm_unmap_rmapp(kvm, rmapp, data);
1255 for (sptep = rmap_get_first(*rmapp, &iter); sptep;
1256 sptep = rmap_get_next(&iter)) {
1257 BUG_ON(!is_shadow_present_pte(*sptep));
1259 if (*sptep & shadow_accessed_mask) {
1261 clear_bit((ffs(shadow_accessed_mask) - 1),
1262 (unsigned long *)sptep);
1269 static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1273 struct rmap_iterator iter;
1277 * If there's no access bit in the secondary pte set by the
1278 * hardware it's up to gup-fast/gup to set the access bit in
1279 * the primary pte or in the page structure.
1281 if (!shadow_accessed_mask)
1284 for (sptep = rmap_get_first(*rmapp, &iter); sptep;
1285 sptep = rmap_get_next(&iter)) {
1286 BUG_ON(!is_shadow_present_pte(*sptep));
1288 if (*sptep & shadow_accessed_mask) {
1297 #define RMAP_RECYCLE_THRESHOLD 1000
1299 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1301 unsigned long *rmapp;
1302 struct kvm_mmu_page *sp;
1304 sp = page_header(__pa(spte));
1306 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1308 kvm_unmap_rmapp(vcpu->kvm, rmapp, 0);
1309 kvm_flush_remote_tlbs(vcpu->kvm);
1312 int kvm_age_hva(struct kvm *kvm, unsigned long hva)
1314 return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp);
1317 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1319 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1323 static int is_empty_shadow_page(u64 *spt)
1328 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1329 if (is_shadow_present_pte(*pos)) {
1330 printk(KERN_ERR "%s: %p %llx\n", __func__,
1339 * This value is the sum of all of the kvm instances's
1340 * kvm->arch.n_used_mmu_pages values. We need a global,
1341 * aggregate version in order to make the slab shrinker
1344 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1346 kvm->arch.n_used_mmu_pages += nr;
1347 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1351 * Remove the sp from shadow page cache, after call it,
1352 * we can not find this sp from the cache, and the shadow
1353 * page table is still valid.
1354 * It should be under the protection of mmu lock.
1356 static void kvm_mmu_isolate_page(struct kvm_mmu_page *sp)
1358 ASSERT(is_empty_shadow_page(sp->spt));
1359 hlist_del(&sp->hash_link);
1360 if (!sp->role.direct)
1361 free_page((unsigned long)sp->gfns);
1365 * Free the shadow page table and the sp, we can do it
1366 * out of the protection of mmu lock.
1368 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1370 list_del(&sp->link);
1371 free_page((unsigned long)sp->spt);
1372 kmem_cache_free(mmu_page_header_cache, sp);
1375 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1377 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
1380 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1381 struct kvm_mmu_page *sp, u64 *parent_pte)
1386 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1389 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1392 pte_list_remove(parent_pte, &sp->parent_ptes);
1395 static void drop_parent_pte(struct kvm_mmu_page *sp,
1398 mmu_page_remove_parent_pte(sp, parent_pte);
1399 mmu_spte_clear_no_track(parent_pte);
1402 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
1403 u64 *parent_pte, int direct)
1405 struct kvm_mmu_page *sp;
1406 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache,
1408 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
1410 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache,
1412 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1413 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1414 bitmap_zero(sp->slot_bitmap, KVM_MEM_SLOTS_NUM);
1415 sp->parent_ptes = 0;
1416 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1417 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1421 static void mark_unsync(u64 *spte);
1422 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1424 pte_list_walk(&sp->parent_ptes, mark_unsync);
1427 static void mark_unsync(u64 *spte)
1429 struct kvm_mmu_page *sp;
1432 sp = page_header(__pa(spte));
1433 index = spte - sp->spt;
1434 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1436 if (sp->unsync_children++)
1438 kvm_mmu_mark_parents_unsync(sp);
1441 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1442 struct kvm_mmu_page *sp)
1447 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1451 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1452 struct kvm_mmu_page *sp, u64 *spte,
1458 #define KVM_PAGE_ARRAY_NR 16
1460 struct kvm_mmu_pages {
1461 struct mmu_page_and_offset {
1462 struct kvm_mmu_page *sp;
1464 } page[KVM_PAGE_ARRAY_NR];
1468 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1474 for (i=0; i < pvec->nr; i++)
1475 if (pvec->page[i].sp == sp)
1478 pvec->page[pvec->nr].sp = sp;
1479 pvec->page[pvec->nr].idx = idx;
1481 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1484 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1485 struct kvm_mmu_pages *pvec)
1487 int i, ret, nr_unsync_leaf = 0;
1489 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1490 struct kvm_mmu_page *child;
1491 u64 ent = sp->spt[i];
1493 if (!is_shadow_present_pte(ent) || is_large_pte(ent))
1494 goto clear_child_bitmap;
1496 child = page_header(ent & PT64_BASE_ADDR_MASK);
1498 if (child->unsync_children) {
1499 if (mmu_pages_add(pvec, child, i))
1502 ret = __mmu_unsync_walk(child, pvec);
1504 goto clear_child_bitmap;
1506 nr_unsync_leaf += ret;
1509 } else if (child->unsync) {
1511 if (mmu_pages_add(pvec, child, i))
1514 goto clear_child_bitmap;
1519 __clear_bit(i, sp->unsync_child_bitmap);
1520 sp->unsync_children--;
1521 WARN_ON((int)sp->unsync_children < 0);
1525 return nr_unsync_leaf;
1528 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1529 struct kvm_mmu_pages *pvec)
1531 if (!sp->unsync_children)
1534 mmu_pages_add(pvec, sp, 0);
1535 return __mmu_unsync_walk(sp, pvec);
1538 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1540 WARN_ON(!sp->unsync);
1541 trace_kvm_mmu_sync_page(sp);
1543 --kvm->stat.mmu_unsync;
1546 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1547 struct list_head *invalid_list);
1548 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1549 struct list_head *invalid_list);
1551 #define for_each_gfn_sp(kvm, sp, gfn, pos) \
1552 hlist_for_each_entry(sp, pos, \
1553 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1554 if ((sp)->gfn != (gfn)) {} else
1556 #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos) \
1557 hlist_for_each_entry(sp, pos, \
1558 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1559 if ((sp)->gfn != (gfn) || (sp)->role.direct || \
1560 (sp)->role.invalid) {} else
1562 /* @sp->gfn should be write-protected at the call site */
1563 static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1564 struct list_head *invalid_list, bool clear_unsync)
1566 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
1567 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1572 kvm_unlink_unsync_page(vcpu->kvm, sp);
1574 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1575 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1579 kvm_mmu_flush_tlb(vcpu);
1583 static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
1584 struct kvm_mmu_page *sp)
1586 LIST_HEAD(invalid_list);
1589 ret = __kvm_sync_page(vcpu, sp, &invalid_list, false);
1591 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1596 #ifdef CONFIG_KVM_MMU_AUDIT
1597 #include "mmu_audit.c"
1599 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1600 static void mmu_audit_disable(void) { }
1603 static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1604 struct list_head *invalid_list)
1606 return __kvm_sync_page(vcpu, sp, invalid_list, true);
1609 /* @gfn should be write-protected at the call site */
1610 static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
1612 struct kvm_mmu_page *s;
1613 struct hlist_node *node;
1614 LIST_HEAD(invalid_list);
1617 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
1621 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1622 kvm_unlink_unsync_page(vcpu->kvm, s);
1623 if ((s->role.cr4_pae != !!is_pae(vcpu)) ||
1624 (vcpu->arch.mmu.sync_page(vcpu, s))) {
1625 kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list);
1631 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1633 kvm_mmu_flush_tlb(vcpu);
1636 struct mmu_page_path {
1637 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1638 unsigned int idx[PT64_ROOT_LEVEL-1];
1641 #define for_each_sp(pvec, sp, parents, i) \
1642 for (i = mmu_pages_next(&pvec, &parents, -1), \
1643 sp = pvec.page[i].sp; \
1644 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1645 i = mmu_pages_next(&pvec, &parents, i))
1647 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1648 struct mmu_page_path *parents,
1653 for (n = i+1; n < pvec->nr; n++) {
1654 struct kvm_mmu_page *sp = pvec->page[n].sp;
1656 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1657 parents->idx[0] = pvec->page[n].idx;
1661 parents->parent[sp->role.level-2] = sp;
1662 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1668 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1670 struct kvm_mmu_page *sp;
1671 unsigned int level = 0;
1674 unsigned int idx = parents->idx[level];
1676 sp = parents->parent[level];
1680 --sp->unsync_children;
1681 WARN_ON((int)sp->unsync_children < 0);
1682 __clear_bit(idx, sp->unsync_child_bitmap);
1684 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
1687 static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1688 struct mmu_page_path *parents,
1689 struct kvm_mmu_pages *pvec)
1691 parents->parent[parent->role.level-1] = NULL;
1695 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1696 struct kvm_mmu_page *parent)
1699 struct kvm_mmu_page *sp;
1700 struct mmu_page_path parents;
1701 struct kvm_mmu_pages pages;
1702 LIST_HEAD(invalid_list);
1704 kvm_mmu_pages_init(parent, &parents, &pages);
1705 while (mmu_unsync_walk(parent, &pages)) {
1708 for_each_sp(pages, sp, parents, i)
1709 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1712 kvm_flush_remote_tlbs(vcpu->kvm);
1714 for_each_sp(pages, sp, parents, i) {
1715 kvm_sync_page(vcpu, sp, &invalid_list);
1716 mmu_pages_clear_parents(&parents);
1718 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1719 cond_resched_lock(&vcpu->kvm->mmu_lock);
1720 kvm_mmu_pages_init(parent, &parents, &pages);
1724 static void init_shadow_page_table(struct kvm_mmu_page *sp)
1728 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1732 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
1734 sp->write_flooding_count = 0;
1737 static void clear_sp_write_flooding_count(u64 *spte)
1739 struct kvm_mmu_page *sp = page_header(__pa(spte));
1741 __clear_sp_write_flooding_count(sp);
1744 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1752 union kvm_mmu_page_role role;
1754 struct kvm_mmu_page *sp;
1755 struct hlist_node *node;
1756 bool need_sync = false;
1758 role = vcpu->arch.mmu.base_role;
1760 role.direct = direct;
1763 role.access = access;
1764 if (!vcpu->arch.mmu.direct_map
1765 && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
1766 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1767 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1768 role.quadrant = quadrant;
1770 for_each_gfn_sp(vcpu->kvm, sp, gfn, node) {
1771 if (!need_sync && sp->unsync)
1774 if (sp->role.word != role.word)
1777 if (sp->unsync && kvm_sync_page_transient(vcpu, sp))
1780 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1781 if (sp->unsync_children) {
1782 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1783 kvm_mmu_mark_parents_unsync(sp);
1784 } else if (sp->unsync)
1785 kvm_mmu_mark_parents_unsync(sp);
1787 __clear_sp_write_flooding_count(sp);
1788 trace_kvm_mmu_get_page(sp, false);
1791 ++vcpu->kvm->stat.mmu_cache_miss;
1792 sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct);
1797 hlist_add_head(&sp->hash_link,
1798 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
1800 if (rmap_write_protect(vcpu->kvm, gfn))
1801 kvm_flush_remote_tlbs(vcpu->kvm);
1802 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
1803 kvm_sync_pages(vcpu, gfn);
1805 account_shadowed(vcpu->kvm, gfn);
1807 init_shadow_page_table(sp);
1808 trace_kvm_mmu_get_page(sp, true);
1812 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1813 struct kvm_vcpu *vcpu, u64 addr)
1815 iterator->addr = addr;
1816 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1817 iterator->level = vcpu->arch.mmu.shadow_root_level;
1819 if (iterator->level == PT64_ROOT_LEVEL &&
1820 vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
1821 !vcpu->arch.mmu.direct_map)
1824 if (iterator->level == PT32E_ROOT_LEVEL) {
1825 iterator->shadow_addr
1826 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1827 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1829 if (!iterator->shadow_addr)
1830 iterator->level = 0;
1834 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1836 if (iterator->level < PT_PAGE_TABLE_LEVEL)
1839 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1840 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1844 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
1847 if (is_last_spte(spte, iterator->level)) {
1848 iterator->level = 0;
1852 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
1856 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1858 return __shadow_walk_next(iterator, *iterator->sptep);
1861 static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp)
1865 spte = __pa(sp->spt)
1866 | PT_PRESENT_MASK | PT_ACCESSED_MASK
1867 | PT_WRITABLE_MASK | PT_USER_MASK;
1868 mmu_spte_set(sptep, spte);
1871 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1873 if (is_large_pte(*sptep)) {
1874 drop_spte(vcpu->kvm, sptep);
1875 --vcpu->kvm->stat.lpages;
1876 kvm_flush_remote_tlbs(vcpu->kvm);
1880 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1881 unsigned direct_access)
1883 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
1884 struct kvm_mmu_page *child;
1887 * For the direct sp, if the guest pte's dirty bit
1888 * changed form clean to dirty, it will corrupt the
1889 * sp's access: allow writable in the read-only sp,
1890 * so we should update the spte at this point to get
1891 * a new sp with the correct access.
1893 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
1894 if (child->role.access == direct_access)
1897 drop_parent_pte(child, sptep);
1898 kvm_flush_remote_tlbs(vcpu->kvm);
1902 static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
1906 struct kvm_mmu_page *child;
1909 if (is_shadow_present_pte(pte)) {
1910 if (is_last_spte(pte, sp->role.level)) {
1911 drop_spte(kvm, spte);
1912 if (is_large_pte(pte))
1915 child = page_header(pte & PT64_BASE_ADDR_MASK);
1916 drop_parent_pte(child, spte);
1921 if (is_mmio_spte(pte))
1922 mmu_spte_clear_no_track(spte);
1927 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
1928 struct kvm_mmu_page *sp)
1932 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1933 mmu_page_zap_pte(kvm, sp, sp->spt + i);
1936 static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
1938 mmu_page_remove_parent_pte(sp, parent_pte);
1941 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
1944 struct rmap_iterator iter;
1946 while ((sptep = rmap_get_first(sp->parent_ptes, &iter)))
1947 drop_parent_pte(sp, sptep);
1950 static int mmu_zap_unsync_children(struct kvm *kvm,
1951 struct kvm_mmu_page *parent,
1952 struct list_head *invalid_list)
1955 struct mmu_page_path parents;
1956 struct kvm_mmu_pages pages;
1958 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
1961 kvm_mmu_pages_init(parent, &parents, &pages);
1962 while (mmu_unsync_walk(parent, &pages)) {
1963 struct kvm_mmu_page *sp;
1965 for_each_sp(pages, sp, parents, i) {
1966 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
1967 mmu_pages_clear_parents(&parents);
1970 kvm_mmu_pages_init(parent, &parents, &pages);
1976 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1977 struct list_head *invalid_list)
1981 trace_kvm_mmu_prepare_zap_page(sp);
1982 ++kvm->stat.mmu_shadow_zapped;
1983 ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
1984 kvm_mmu_page_unlink_children(kvm, sp);
1985 kvm_mmu_unlink_parents(kvm, sp);
1986 if (!sp->role.invalid && !sp->role.direct)
1987 unaccount_shadowed(kvm, sp->gfn);
1989 kvm_unlink_unsync_page(kvm, sp);
1990 if (!sp->root_count) {
1993 list_move(&sp->link, invalid_list);
1994 kvm_mod_used_mmu_pages(kvm, -1);
1996 list_move(&sp->link, &kvm->arch.active_mmu_pages);
1997 kvm_reload_remote_mmus(kvm);
2000 sp->role.invalid = 1;
2004 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2005 struct list_head *invalid_list)
2007 struct kvm_mmu_page *sp;
2009 if (list_empty(invalid_list))
2013 * wmb: make sure everyone sees our modifications to the page tables
2014 * rmb: make sure we see changes to vcpu->mode
2019 * Wait for all vcpus to exit guest mode and/or lockless shadow
2022 kvm_flush_remote_tlbs(kvm);
2025 sp = list_first_entry(invalid_list, struct kvm_mmu_page, link);
2026 WARN_ON(!sp->role.invalid || sp->root_count);
2027 kvm_mmu_isolate_page(sp);
2028 kvm_mmu_free_page(sp);
2029 } while (!list_empty(invalid_list));
2033 * Changing the number of mmu pages allocated to the vm
2034 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2036 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
2038 LIST_HEAD(invalid_list);
2040 * If we set the number of mmu pages to be smaller be than the
2041 * number of actived pages , we must to free some mmu pages before we
2045 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2046 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages &&
2047 !list_empty(&kvm->arch.active_mmu_pages)) {
2048 struct kvm_mmu_page *page;
2050 page = container_of(kvm->arch.active_mmu_pages.prev,
2051 struct kvm_mmu_page, link);
2052 kvm_mmu_prepare_zap_page(kvm, page, &invalid_list);
2054 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2055 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2058 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2061 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2063 struct kvm_mmu_page *sp;
2064 struct hlist_node *node;
2065 LIST_HEAD(invalid_list);
2068 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2070 spin_lock(&kvm->mmu_lock);
2071 for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
2072 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2075 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2077 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2078 spin_unlock(&kvm->mmu_lock);
2082 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2084 static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
2086 int slot = memslot_id(kvm, gfn);
2087 struct kvm_mmu_page *sp = page_header(__pa(pte));
2089 __set_bit(slot, sp->slot_bitmap);
2093 * The function is based on mtrr_type_lookup() in
2094 * arch/x86/kernel/cpu/mtrr/generic.c
2096 static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
2101 u8 prev_match, curr_match;
2102 int num_var_ranges = KVM_NR_VAR_MTRR;
2104 if (!mtrr_state->enabled)
2107 /* Make end inclusive end, instead of exclusive */
2110 /* Look in fixed ranges. Just return the type as per start */
2111 if (mtrr_state->have_fixed && (start < 0x100000)) {
2114 if (start < 0x80000) {
2116 idx += (start >> 16);
2117 return mtrr_state->fixed_ranges[idx];
2118 } else if (start < 0xC0000) {
2120 idx += ((start - 0x80000) >> 14);
2121 return mtrr_state->fixed_ranges[idx];
2122 } else if (start < 0x1000000) {
2124 idx += ((start - 0xC0000) >> 12);
2125 return mtrr_state->fixed_ranges[idx];
2130 * Look in variable ranges
2131 * Look of multiple ranges matching this address and pick type
2132 * as per MTRR precedence
2134 if (!(mtrr_state->enabled & 2))
2135 return mtrr_state->def_type;
2138 for (i = 0; i < num_var_ranges; ++i) {
2139 unsigned short start_state, end_state;
2141 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
2144 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
2145 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
2146 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
2147 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
2149 start_state = ((start & mask) == (base & mask));
2150 end_state = ((end & mask) == (base & mask));
2151 if (start_state != end_state)
2154 if ((start & mask) != (base & mask))
2157 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
2158 if (prev_match == 0xFF) {
2159 prev_match = curr_match;
2163 if (prev_match == MTRR_TYPE_UNCACHABLE ||
2164 curr_match == MTRR_TYPE_UNCACHABLE)
2165 return MTRR_TYPE_UNCACHABLE;
2167 if ((prev_match == MTRR_TYPE_WRBACK &&
2168 curr_match == MTRR_TYPE_WRTHROUGH) ||
2169 (prev_match == MTRR_TYPE_WRTHROUGH &&
2170 curr_match == MTRR_TYPE_WRBACK)) {
2171 prev_match = MTRR_TYPE_WRTHROUGH;
2172 curr_match = MTRR_TYPE_WRTHROUGH;
2175 if (prev_match != curr_match)
2176 return MTRR_TYPE_UNCACHABLE;
2179 if (prev_match != 0xFF)
2182 return mtrr_state->def_type;
2185 u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
2189 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
2190 (gfn << PAGE_SHIFT) + PAGE_SIZE);
2191 if (mtrr == 0xfe || mtrr == 0xff)
2192 mtrr = MTRR_TYPE_WRBACK;
2195 EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
2197 static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2199 trace_kvm_mmu_unsync_page(sp);
2200 ++vcpu->kvm->stat.mmu_unsync;
2203 kvm_mmu_mark_parents_unsync(sp);
2206 static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
2208 struct kvm_mmu_page *s;
2209 struct hlist_node *node;
2211 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
2214 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
2215 __kvm_unsync_page(vcpu, s);
2219 static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2222 struct kvm_mmu_page *s;
2223 struct hlist_node *node;
2224 bool need_unsync = false;
2226 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
2230 if (s->role.level != PT_PAGE_TABLE_LEVEL)
2233 if (!need_unsync && !s->unsync) {
2238 kvm_unsync_pages(vcpu, gfn);
2242 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2243 unsigned pte_access, int user_fault,
2244 int write_fault, int level,
2245 gfn_t gfn, pfn_t pfn, bool speculative,
2246 bool can_unsync, bool host_writable)
2248 u64 spte, entry = *sptep;
2251 if (set_mmio_spte(sptep, gfn, pfn, pte_access))
2254 spte = PT_PRESENT_MASK;
2256 spte |= shadow_accessed_mask;
2258 if (pte_access & ACC_EXEC_MASK)
2259 spte |= shadow_x_mask;
2261 spte |= shadow_nx_mask;
2262 if (pte_access & ACC_USER_MASK)
2263 spte |= shadow_user_mask;
2264 if (level > PT_PAGE_TABLE_LEVEL)
2265 spte |= PT_PAGE_SIZE_MASK;
2267 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2268 kvm_is_mmio_pfn(pfn));
2271 spte |= SPTE_HOST_WRITEABLE;
2273 pte_access &= ~ACC_WRITE_MASK;
2275 spte |= (u64)pfn << PAGE_SHIFT;
2277 if ((pte_access & ACC_WRITE_MASK)
2278 || (!vcpu->arch.mmu.direct_map && write_fault
2279 && !is_write_protection(vcpu) && !user_fault)) {
2281 if (level > PT_PAGE_TABLE_LEVEL &&
2282 has_wrprotected_page(vcpu->kvm, gfn, level)) {
2284 drop_spte(vcpu->kvm, sptep);
2288 spte |= PT_WRITABLE_MASK;
2290 if (!vcpu->arch.mmu.direct_map
2291 && !(pte_access & ACC_WRITE_MASK)) {
2292 spte &= ~PT_USER_MASK;
2294 * If we converted a user page to a kernel page,
2295 * so that the kernel can write to it when cr0.wp=0,
2296 * then we should prevent the kernel from executing it
2297 * if SMEP is enabled.
2299 if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))
2300 spte |= PT64_NX_MASK;
2304 * Optimization: for pte sync, if spte was writable the hash
2305 * lookup is unnecessary (and expensive). Write protection
2306 * is responsibility of mmu_get_page / kvm_sync_page.
2307 * Same reasoning can be applied to dirty page accounting.
2309 if (!can_unsync && is_writable_pte(*sptep))
2312 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2313 pgprintk("%s: found shadow page for %llx, marking ro\n",
2316 pte_access &= ~ACC_WRITE_MASK;
2317 if (is_writable_pte(spte))
2318 spte &= ~PT_WRITABLE_MASK;
2322 if (pte_access & ACC_WRITE_MASK)
2323 mark_page_dirty(vcpu->kvm, gfn);
2326 mmu_spte_update(sptep, spte);
2328 * If we overwrite a writable spte with a read-only one we
2329 * should flush remote TLBs. Otherwise rmap_write_protect
2330 * will find a read-only spte, even though the writable spte
2331 * might be cached on a CPU's TLB.
2333 if (is_writable_pte(entry) && !is_writable_pte(*sptep))
2334 kvm_flush_remote_tlbs(vcpu->kvm);
2339 static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2340 unsigned pt_access, unsigned pte_access,
2341 int user_fault, int write_fault,
2342 int *emulate, int level, gfn_t gfn,
2343 pfn_t pfn, bool speculative,
2346 int was_rmapped = 0;
2349 pgprintk("%s: spte %llx access %x write_fault %d"
2350 " user_fault %d gfn %llx\n",
2351 __func__, *sptep, pt_access,
2352 write_fault, user_fault, gfn);
2354 if (is_rmap_spte(*sptep)) {
2356 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2357 * the parent of the now unreachable PTE.
2359 if (level > PT_PAGE_TABLE_LEVEL &&
2360 !is_large_pte(*sptep)) {
2361 struct kvm_mmu_page *child;
2364 child = page_header(pte & PT64_BASE_ADDR_MASK);
2365 drop_parent_pte(child, sptep);
2366 kvm_flush_remote_tlbs(vcpu->kvm);
2367 } else if (pfn != spte_to_pfn(*sptep)) {
2368 pgprintk("hfn old %llx new %llx\n",
2369 spte_to_pfn(*sptep), pfn);
2370 drop_spte(vcpu->kvm, sptep);
2371 kvm_flush_remote_tlbs(vcpu->kvm);
2376 if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault,
2377 level, gfn, pfn, speculative, true,
2381 kvm_mmu_flush_tlb(vcpu);
2384 if (unlikely(is_mmio_spte(*sptep) && emulate))
2387 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2388 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2389 is_large_pte(*sptep)? "2MB" : "4kB",
2390 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
2392 if (!was_rmapped && is_large_pte(*sptep))
2393 ++vcpu->kvm->stat.lpages;
2395 if (is_shadow_present_pte(*sptep)) {
2396 page_header_update_slot(vcpu->kvm, sptep, gfn);
2398 rmap_count = rmap_add(vcpu, sptep, gfn);
2399 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2400 rmap_recycle(vcpu, sptep, gfn);
2403 kvm_release_pfn_clean(pfn);
2406 static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
2410 static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2413 struct kvm_memory_slot *slot;
2416 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2418 get_page(fault_page);
2419 return page_to_pfn(fault_page);
2422 hva = gfn_to_hva_memslot(slot, gfn);
2424 return hva_to_pfn_atomic(vcpu->kvm, hva);
2427 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2428 struct kvm_mmu_page *sp,
2429 u64 *start, u64 *end)
2431 struct page *pages[PTE_PREFETCH_NUM];
2432 unsigned access = sp->role.access;
2436 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2437 if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK))
2440 ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start);
2444 for (i = 0; i < ret; i++, gfn++, start++)
2445 mmu_set_spte(vcpu, start, ACC_ALL,
2447 sp->role.level, gfn,
2448 page_to_pfn(pages[i]), true, true);
2453 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2454 struct kvm_mmu_page *sp, u64 *sptep)
2456 u64 *spte, *start = NULL;
2459 WARN_ON(!sp->role.direct);
2461 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2464 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2465 if (is_shadow_present_pte(*spte) || spte == sptep) {
2468 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2476 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2478 struct kvm_mmu_page *sp;
2481 * Since it's no accessed bit on EPT, it's no way to
2482 * distinguish between actually accessed translations
2483 * and prefetched, so disable pte prefetch if EPT is
2486 if (!shadow_accessed_mask)
2489 sp = page_header(__pa(sptep));
2490 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2493 __direct_pte_prefetch(vcpu, sp, sptep);
2496 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
2497 int map_writable, int level, gfn_t gfn, pfn_t pfn,
2500 struct kvm_shadow_walk_iterator iterator;
2501 struct kvm_mmu_page *sp;
2505 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2506 if (iterator.level == level) {
2507 unsigned pte_access = ACC_ALL;
2509 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, pte_access,
2511 level, gfn, pfn, prefault, map_writable);
2512 direct_pte_prefetch(vcpu, iterator.sptep);
2513 ++vcpu->stat.pf_fixed;
2517 if (!is_shadow_present_pte(*iterator.sptep)) {
2518 u64 base_addr = iterator.addr;
2520 base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2521 pseudo_gfn = base_addr >> PAGE_SHIFT;
2522 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2524 1, ACC_ALL, iterator.sptep);
2526 pgprintk("nonpaging_map: ENOMEM\n");
2527 kvm_release_pfn_clean(pfn);
2531 mmu_spte_set(iterator.sptep,
2533 | PT_PRESENT_MASK | PT_WRITABLE_MASK
2534 | shadow_user_mask | shadow_x_mask
2535 | shadow_accessed_mask);
2541 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2545 info.si_signo = SIGBUS;
2547 info.si_code = BUS_MCEERR_AR;
2548 info.si_addr = (void __user *)address;
2549 info.si_addr_lsb = PAGE_SHIFT;
2551 send_sig_info(SIGBUS, &info, tsk);
2554 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, pfn_t pfn)
2556 kvm_release_pfn_clean(pfn);
2557 if (is_hwpoison_pfn(pfn)) {
2558 kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current);
2565 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
2566 gfn_t *gfnp, pfn_t *pfnp, int *levelp)
2570 int level = *levelp;
2573 * Check if it's a transparent hugepage. If this would be an
2574 * hugetlbfs page, level wouldn't be set to
2575 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2578 if (!is_error_pfn(pfn) && !kvm_is_mmio_pfn(pfn) &&
2579 level == PT_PAGE_TABLE_LEVEL &&
2580 PageTransCompound(pfn_to_page(pfn)) &&
2581 !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) {
2584 * mmu_notifier_retry was successful and we hold the
2585 * mmu_lock here, so the pmd can't become splitting
2586 * from under us, and in turn
2587 * __split_huge_page_refcount() can't run from under
2588 * us and we can safely transfer the refcount from
2589 * PG_tail to PG_head as we switch the pfn to tail to
2592 *levelp = level = PT_DIRECTORY_LEVEL;
2593 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2594 VM_BUG_ON((gfn & mask) != (pfn & mask));
2598 kvm_release_pfn_clean(pfn);
2606 static bool mmu_invalid_pfn(pfn_t pfn)
2608 return unlikely(is_invalid_pfn(pfn));
2611 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2612 pfn_t pfn, unsigned access, int *ret_val)
2616 /* The pfn is invalid, report the error! */
2617 if (unlikely(is_invalid_pfn(pfn))) {
2618 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2622 if (unlikely(is_noslot_pfn(pfn)))
2623 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
2630 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
2631 gva_t gva, pfn_t *pfn, bool write, bool *writable);
2633 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn,
2640 unsigned long mmu_seq;
2643 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
2644 if (likely(!force_pt_level)) {
2645 level = mapping_level(vcpu, gfn);
2647 * This path builds a PAE pagetable - so we can map
2648 * 2mb pages at maximum. Therefore check if the level
2649 * is larger than that.
2651 if (level > PT_DIRECTORY_LEVEL)
2652 level = PT_DIRECTORY_LEVEL;
2654 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2656 level = PT_PAGE_TABLE_LEVEL;
2658 mmu_seq = vcpu->kvm->mmu_notifier_seq;
2661 if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
2664 if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
2667 spin_lock(&vcpu->kvm->mmu_lock);
2668 if (mmu_notifier_retry(vcpu, mmu_seq))
2670 kvm_mmu_free_some_pages(vcpu);
2671 if (likely(!force_pt_level))
2672 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
2673 r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn,
2675 spin_unlock(&vcpu->kvm->mmu_lock);
2681 spin_unlock(&vcpu->kvm->mmu_lock);
2682 kvm_release_pfn_clean(pfn);
2687 static void mmu_free_roots(struct kvm_vcpu *vcpu)
2690 struct kvm_mmu_page *sp;
2691 LIST_HEAD(invalid_list);
2693 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2695 spin_lock(&vcpu->kvm->mmu_lock);
2696 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
2697 (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
2698 vcpu->arch.mmu.direct_map)) {
2699 hpa_t root = vcpu->arch.mmu.root_hpa;
2701 sp = page_header(root);
2703 if (!sp->root_count && sp->role.invalid) {
2704 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
2705 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2707 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2708 spin_unlock(&vcpu->kvm->mmu_lock);
2711 for (i = 0; i < 4; ++i) {
2712 hpa_t root = vcpu->arch.mmu.pae_root[i];
2715 root &= PT64_BASE_ADDR_MASK;
2716 sp = page_header(root);
2718 if (!sp->root_count && sp->role.invalid)
2719 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2722 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
2724 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2725 spin_unlock(&vcpu->kvm->mmu_lock);
2726 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2729 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2733 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
2734 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2741 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
2743 struct kvm_mmu_page *sp;
2746 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2747 spin_lock(&vcpu->kvm->mmu_lock);
2748 kvm_mmu_free_some_pages(vcpu);
2749 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL,
2752 spin_unlock(&vcpu->kvm->mmu_lock);
2753 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
2754 } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
2755 for (i = 0; i < 4; ++i) {
2756 hpa_t root = vcpu->arch.mmu.pae_root[i];
2758 ASSERT(!VALID_PAGE(root));
2759 spin_lock(&vcpu->kvm->mmu_lock);
2760 kvm_mmu_free_some_pages(vcpu);
2761 sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
2763 PT32_ROOT_LEVEL, 1, ACC_ALL,
2765 root = __pa(sp->spt);
2767 spin_unlock(&vcpu->kvm->mmu_lock);
2768 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
2770 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
2777 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
2779 struct kvm_mmu_page *sp;
2784 root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
2786 if (mmu_check_root(vcpu, root_gfn))
2790 * Do we shadow a long mode page table? If so we need to
2791 * write-protect the guests page table root.
2793 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
2794 hpa_t root = vcpu->arch.mmu.root_hpa;
2796 ASSERT(!VALID_PAGE(root));
2798 spin_lock(&vcpu->kvm->mmu_lock);
2799 kvm_mmu_free_some_pages(vcpu);
2800 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
2802 root = __pa(sp->spt);
2804 spin_unlock(&vcpu->kvm->mmu_lock);
2805 vcpu->arch.mmu.root_hpa = root;
2810 * We shadow a 32 bit page table. This may be a legacy 2-level
2811 * or a PAE 3-level page table. In either case we need to be aware that
2812 * the shadow page table may be a PAE or a long mode page table.
2814 pm_mask = PT_PRESENT_MASK;
2815 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
2816 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
2818 for (i = 0; i < 4; ++i) {
2819 hpa_t root = vcpu->arch.mmu.pae_root[i];
2821 ASSERT(!VALID_PAGE(root));
2822 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
2823 pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i);
2824 if (!is_present_gpte(pdptr)) {
2825 vcpu->arch.mmu.pae_root[i] = 0;
2828 root_gfn = pdptr >> PAGE_SHIFT;
2829 if (mmu_check_root(vcpu, root_gfn))
2832 spin_lock(&vcpu->kvm->mmu_lock);
2833 kvm_mmu_free_some_pages(vcpu);
2834 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
2837 root = __pa(sp->spt);
2839 spin_unlock(&vcpu->kvm->mmu_lock);
2841 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
2843 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
2846 * If we shadow a 32 bit page table with a long mode page
2847 * table we enter this path.
2849 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2850 if (vcpu->arch.mmu.lm_root == NULL) {
2852 * The additional page necessary for this is only
2853 * allocated on demand.
2858 lm_root = (void*)get_zeroed_page(GFP_KERNEL);
2859 if (lm_root == NULL)
2862 lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
2864 vcpu->arch.mmu.lm_root = lm_root;
2867 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
2873 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
2875 if (vcpu->arch.mmu.direct_map)
2876 return mmu_alloc_direct_roots(vcpu);
2878 return mmu_alloc_shadow_roots(vcpu);
2881 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
2884 struct kvm_mmu_page *sp;
2886 if (vcpu->arch.mmu.direct_map)
2889 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2892 vcpu_clear_mmio_info(vcpu, ~0ul);
2893 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
2894 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
2895 hpa_t root = vcpu->arch.mmu.root_hpa;
2896 sp = page_header(root);
2897 mmu_sync_children(vcpu, sp);
2898 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
2901 for (i = 0; i < 4; ++i) {
2902 hpa_t root = vcpu->arch.mmu.pae_root[i];
2904 if (root && VALID_PAGE(root)) {
2905 root &= PT64_BASE_ADDR_MASK;
2906 sp = page_header(root);
2907 mmu_sync_children(vcpu, sp);
2910 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
2913 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
2915 spin_lock(&vcpu->kvm->mmu_lock);
2916 mmu_sync_roots(vcpu);
2917 spin_unlock(&vcpu->kvm->mmu_lock);
2920 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
2921 u32 access, struct x86_exception *exception)
2924 exception->error_code = 0;
2928 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
2930 struct x86_exception *exception)
2933 exception->error_code = 0;
2934 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access);
2937 static bool quickly_check_mmio_pf(struct kvm_vcpu *vcpu, u64 addr, bool direct)
2940 return vcpu_match_mmio_gpa(vcpu, addr);
2942 return vcpu_match_mmio_gva(vcpu, addr);
2947 * On direct hosts, the last spte is only allows two states
2948 * for mmio page fault:
2949 * - It is the mmio spte
2950 * - It is zapped or it is being zapped.
2952 * This function completely checks the spte when the last spte
2953 * is not the mmio spte.
2955 static bool check_direct_spte_mmio_pf(u64 spte)
2957 return __check_direct_spte_mmio_pf(spte);
2960 static u64 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr)
2962 struct kvm_shadow_walk_iterator iterator;
2965 walk_shadow_page_lockless_begin(vcpu);
2966 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte)
2967 if (!is_shadow_present_pte(spte))
2969 walk_shadow_page_lockless_end(vcpu);
2975 * If it is a real mmio page fault, return 1 and emulat the instruction
2976 * directly, return 0 to let CPU fault again on the address, -1 is
2977 * returned if bug is detected.
2979 int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct)
2983 if (quickly_check_mmio_pf(vcpu, addr, direct))
2986 spte = walk_shadow_page_get_mmio_spte(vcpu, addr);
2988 if (is_mmio_spte(spte)) {
2989 gfn_t gfn = get_mmio_spte_gfn(spte);
2990 unsigned access = get_mmio_spte_access(spte);
2995 trace_handle_mmio_page_fault(addr, gfn, access);
2996 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3001 * It's ok if the gva is remapped by other cpus on shadow guest,
3002 * it's a BUG if the gfn is not a mmio page.
3004 if (direct && !check_direct_spte_mmio_pf(spte))
3008 * If the page table is zapped by other cpus, let CPU fault again on
3013 EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common);
3015 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr,
3016 u32 error_code, bool direct)
3020 ret = handle_mmio_page_fault_common(vcpu, addr, direct);
3025 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3026 u32 error_code, bool prefault)
3031 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
3033 if (unlikely(error_code & PFERR_RSVD_MASK))
3034 return handle_mmio_page_fault(vcpu, gva, error_code, true);
3036 r = mmu_topup_memory_caches(vcpu);
3041 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3043 gfn = gva >> PAGE_SHIFT;
3045 return nonpaging_map(vcpu, gva & PAGE_MASK,
3046 error_code & PFERR_WRITE_MASK, gfn, prefault);
3049 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
3051 struct kvm_arch_async_pf arch;
3053 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3055 arch.direct_map = vcpu->arch.mmu.direct_map;
3056 arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
3058 return kvm_setup_async_pf(vcpu, gva, gfn, &arch);
3061 static bool can_do_async_pf(struct kvm_vcpu *vcpu)
3063 if (unlikely(!irqchip_in_kernel(vcpu->kvm) ||
3064 kvm_event_needs_reinjection(vcpu)))
3067 return kvm_x86_ops->interrupt_allowed(vcpu);
3070 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3071 gva_t gva, pfn_t *pfn, bool write, bool *writable)
3075 *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable);
3078 return false; /* *pfn has correct page already */
3080 put_page(pfn_to_page(*pfn));
3082 if (!prefault && can_do_async_pf(vcpu)) {
3083 trace_kvm_try_async_get_page(gva, gfn);
3084 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3085 trace_kvm_async_pf_doublefault(gva, gfn);
3086 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3088 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
3092 *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable);
3097 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
3104 gfn_t gfn = gpa >> PAGE_SHIFT;
3105 unsigned long mmu_seq;
3106 int write = error_code & PFERR_WRITE_MASK;
3110 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3112 if (unlikely(error_code & PFERR_RSVD_MASK))
3113 return handle_mmio_page_fault(vcpu, gpa, error_code, true);
3115 r = mmu_topup_memory_caches(vcpu);
3119 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
3120 if (likely(!force_pt_level)) {
3121 level = mapping_level(vcpu, gfn);
3122 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3124 level = PT_PAGE_TABLE_LEVEL;
3126 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3129 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3132 if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
3135 spin_lock(&vcpu->kvm->mmu_lock);
3136 if (mmu_notifier_retry(vcpu, mmu_seq))
3138 kvm_mmu_free_some_pages(vcpu);
3139 if (likely(!force_pt_level))
3140 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3141 r = __direct_map(vcpu, gpa, write, map_writable,
3142 level, gfn, pfn, prefault);
3143 spin_unlock(&vcpu->kvm->mmu_lock);
3148 spin_unlock(&vcpu->kvm->mmu_lock);
3149 kvm_release_pfn_clean(pfn);
3153 static void nonpaging_free(struct kvm_vcpu *vcpu)
3155 mmu_free_roots(vcpu);
3158 static int nonpaging_init_context(struct kvm_vcpu *vcpu,
3159 struct kvm_mmu *context)
3161 context->new_cr3 = nonpaging_new_cr3;
3162 context->page_fault = nonpaging_page_fault;
3163 context->gva_to_gpa = nonpaging_gva_to_gpa;
3164 context->free = nonpaging_free;
3165 context->sync_page = nonpaging_sync_page;
3166 context->invlpg = nonpaging_invlpg;
3167 context->update_pte = nonpaging_update_pte;
3168 context->root_level = 0;
3169 context->shadow_root_level = PT32E_ROOT_LEVEL;
3170 context->root_hpa = INVALID_PAGE;
3171 context->direct_map = true;
3172 context->nx = false;
3176 void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3178 ++vcpu->stat.tlb_flush;
3179 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
3182 static void paging_new_cr3(struct kvm_vcpu *vcpu)
3184 pgprintk("%s: cr3 %lx\n", __func__, kvm_read_cr3(vcpu));
3185 mmu_free_roots(vcpu);
3188 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3190 return kvm_read_cr3(vcpu);
3193 static void inject_page_fault(struct kvm_vcpu *vcpu,
3194 struct x86_exception *fault)
3196 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
3199 static void paging_free(struct kvm_vcpu *vcpu)
3201 nonpaging_free(vcpu);
3204 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
3208 bit7 = (gpte >> 7) & 1;
3209 return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0;
3212 static bool sync_mmio_spte(u64 *sptep, gfn_t gfn, unsigned access,
3215 if (unlikely(is_mmio_spte(*sptep))) {
3216 if (gfn != get_mmio_spte_gfn(*sptep)) {
3217 mmu_spte_clear_no_track(sptep);
3222 mark_mmio_spte(sptep, gfn, access);
3230 #include "paging_tmpl.h"
3234 #include "paging_tmpl.h"
3237 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3238 struct kvm_mmu *context)
3240 int maxphyaddr = cpuid_maxphyaddr(vcpu);
3241 u64 exb_bit_rsvd = 0;
3244 exb_bit_rsvd = rsvd_bits(63, 63);
3245 switch (context->root_level) {
3246 case PT32_ROOT_LEVEL:
3247 /* no rsvd bits for 2 level 4K page table entries */
3248 context->rsvd_bits_mask[0][1] = 0;
3249 context->rsvd_bits_mask[0][0] = 0;
3250 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3252 if (!is_pse(vcpu)) {
3253 context->rsvd_bits_mask[1][1] = 0;
3257 if (is_cpuid_PSE36())
3258 /* 36bits PSE 4MB page */
3259 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
3261 /* 32 bits PSE 4MB page */
3262 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
3264 case PT32E_ROOT_LEVEL:
3265 context->rsvd_bits_mask[0][2] =
3266 rsvd_bits(maxphyaddr, 63) |
3267 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
3268 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3269 rsvd_bits(maxphyaddr, 62); /* PDE */
3270 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3271 rsvd_bits(maxphyaddr, 62); /* PTE */
3272 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3273 rsvd_bits(maxphyaddr, 62) |
3274 rsvd_bits(13, 20); /* large page */
3275 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3277 case PT64_ROOT_LEVEL:
3278 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
3279 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3280 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
3281 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3282 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3283 rsvd_bits(maxphyaddr, 51);
3284 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3285 rsvd_bits(maxphyaddr, 51);
3286 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
3287 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
3288 rsvd_bits(maxphyaddr, 51) |
3290 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3291 rsvd_bits(maxphyaddr, 51) |
3292 rsvd_bits(13, 20); /* large page */
3293 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3298 static int paging64_init_context_common(struct kvm_vcpu *vcpu,
3299 struct kvm_mmu *context,
3302 context->nx = is_nx(vcpu);
3303 context->root_level = level;
3305 reset_rsvds_bits_mask(vcpu, context);
3307 ASSERT(is_pae(vcpu));
3308 context->new_cr3 = paging_new_cr3;
3309 context->page_fault = paging64_page_fault;
3310 context->gva_to_gpa = paging64_gva_to_gpa;
3311 context->sync_page = paging64_sync_page;
3312 context->invlpg = paging64_invlpg;
3313 context->update_pte = paging64_update_pte;
3314 context->free = paging_free;
3315 context->shadow_root_level = level;
3316 context->root_hpa = INVALID_PAGE;
3317 context->direct_map = false;
3321 static int paging64_init_context(struct kvm_vcpu *vcpu,
3322 struct kvm_mmu *context)
3324 return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
3327 static int paging32_init_context(struct kvm_vcpu *vcpu,
3328 struct kvm_mmu *context)
3330 context->nx = false;
3331 context->root_level = PT32_ROOT_LEVEL;
3333 reset_rsvds_bits_mask(vcpu, context);
3335 context->new_cr3 = paging_new_cr3;
3336 context->page_fault = paging32_page_fault;
3337 context->gva_to_gpa = paging32_gva_to_gpa;
3338 context->free = paging_free;
3339 context->sync_page = paging32_sync_page;
3340 context->invlpg = paging32_invlpg;
3341 context->update_pte = paging32_update_pte;
3342 context->shadow_root_level = PT32E_ROOT_LEVEL;
3343 context->root_hpa = INVALID_PAGE;
3344 context->direct_map = false;
3348 static int paging32E_init_context(struct kvm_vcpu *vcpu,
3349 struct kvm_mmu *context)
3351 return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
3354 static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
3356 struct kvm_mmu *context = vcpu->arch.walk_mmu;
3358 context->base_role.word = 0;
3359 context->new_cr3 = nonpaging_new_cr3;
3360 context->page_fault = tdp_page_fault;
3361 context->free = nonpaging_free;
3362 context->sync_page = nonpaging_sync_page;
3363 context->invlpg = nonpaging_invlpg;
3364 context->update_pte = nonpaging_update_pte;
3365 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
3366 context->root_hpa = INVALID_PAGE;
3367 context->direct_map = true;
3368 context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
3369 context->get_cr3 = get_cr3;
3370 context->get_pdptr = kvm_pdptr_read;
3371 context->inject_page_fault = kvm_inject_page_fault;
3373 if (!is_paging(vcpu)) {
3374 context->nx = false;
3375 context->gva_to_gpa = nonpaging_gva_to_gpa;
3376 context->root_level = 0;
3377 } else if (is_long_mode(vcpu)) {
3378 context->nx = is_nx(vcpu);
3379 context->root_level = PT64_ROOT_LEVEL;
3380 reset_rsvds_bits_mask(vcpu, context);
3381 context->gva_to_gpa = paging64_gva_to_gpa;
3382 } else if (is_pae(vcpu)) {
3383 context->nx = is_nx(vcpu);
3384 context->root_level = PT32E_ROOT_LEVEL;
3385 reset_rsvds_bits_mask(vcpu, context);
3386 context->gva_to_gpa = paging64_gva_to_gpa;
3388 context->nx = false;
3389 context->root_level = PT32_ROOT_LEVEL;
3390 reset_rsvds_bits_mask(vcpu, context);
3391 context->gva_to_gpa = paging32_gva_to_gpa;
3397 int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
3400 bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3402 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3404 if (!is_paging(vcpu))
3405 r = nonpaging_init_context(vcpu, context);
3406 else if (is_long_mode(vcpu))
3407 r = paging64_init_context(vcpu, context);
3408 else if (is_pae(vcpu))
3409 r = paging32E_init_context(vcpu, context);
3411 r = paging32_init_context(vcpu, context);
3413 vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu);
3414 vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu);
3415 vcpu->arch.mmu.base_role.smep_andnot_wp
3416 = smep && !is_write_protection(vcpu);
3420 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
3422 static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
3424 int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu);
3426 vcpu->arch.walk_mmu->set_cr3 = kvm_x86_ops->set_cr3;
3427 vcpu->arch.walk_mmu->get_cr3 = get_cr3;
3428 vcpu->arch.walk_mmu->get_pdptr = kvm_pdptr_read;
3429 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
3434 static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
3436 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
3438 g_context->get_cr3 = get_cr3;
3439 g_context->get_pdptr = kvm_pdptr_read;
3440 g_context->inject_page_fault = kvm_inject_page_fault;
3443 * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The
3444 * translation of l2_gpa to l1_gpa addresses is done using the
3445 * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa
3446 * functions between mmu and nested_mmu are swapped.
3448 if (!is_paging(vcpu)) {
3449 g_context->nx = false;
3450 g_context->root_level = 0;
3451 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
3452 } else if (is_long_mode(vcpu)) {
3453 g_context->nx = is_nx(vcpu);
3454 g_context->root_level = PT64_ROOT_LEVEL;
3455 reset_rsvds_bits_mask(vcpu, g_context);
3456 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3457 } else if (is_pae(vcpu)) {
3458 g_context->nx = is_nx(vcpu);
3459 g_context->root_level = PT32E_ROOT_LEVEL;
3460 reset_rsvds_bits_mask(vcpu, g_context);
3461 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3463 g_context->nx = false;
3464 g_context->root_level = PT32_ROOT_LEVEL;
3465 reset_rsvds_bits_mask(vcpu, g_context);
3466 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
3472 static int init_kvm_mmu(struct kvm_vcpu *vcpu)
3474 if (mmu_is_nested(vcpu))
3475 return init_kvm_nested_mmu(vcpu);
3476 else if (tdp_enabled)
3477 return init_kvm_tdp_mmu(vcpu);
3479 return init_kvm_softmmu(vcpu);
3482 static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
3485 if (VALID_PAGE(vcpu->arch.mmu.root_hpa))
3486 /* mmu.free() should set root_hpa = INVALID_PAGE */
3487 vcpu->arch.mmu.free(vcpu);
3490 int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
3492 destroy_kvm_mmu(vcpu);
3493 return init_kvm_mmu(vcpu);
3495 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
3497 int kvm_mmu_load(struct kvm_vcpu *vcpu)
3501 r = mmu_topup_memory_caches(vcpu);
3504 r = mmu_alloc_roots(vcpu);
3505 spin_lock(&vcpu->kvm->mmu_lock);
3506 mmu_sync_roots(vcpu);
3507 spin_unlock(&vcpu->kvm->mmu_lock);
3510 /* set_cr3() should ensure TLB has been flushed */
3511 vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
3515 EXPORT_SYMBOL_GPL(kvm_mmu_load);
3517 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
3519 mmu_free_roots(vcpu);
3521 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
3523 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
3524 struct kvm_mmu_page *sp, u64 *spte,
3527 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
3528 ++vcpu->kvm->stat.mmu_pde_zapped;
3532 ++vcpu->kvm->stat.mmu_pte_updated;
3533 vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
3536 static bool need_remote_flush(u64 old, u64 new)
3538 if (!is_shadow_present_pte(old))
3540 if (!is_shadow_present_pte(new))
3542 if ((old ^ new) & PT64_BASE_ADDR_MASK)
3544 old ^= PT64_NX_MASK;
3545 new ^= PT64_NX_MASK;
3546 return (old & ~new & PT64_PERM_MASK) != 0;
3549 static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page,
3550 bool remote_flush, bool local_flush)
3556 kvm_flush_remote_tlbs(vcpu->kvm);
3557 else if (local_flush)
3558 kvm_mmu_flush_tlb(vcpu);
3561 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
3562 const u8 *new, int *bytes)
3568 * Assume that the pte write on a page table of the same type
3569 * as the current vcpu paging mode since we update the sptes only
3570 * when they have the same mode.
3572 if (is_pae(vcpu) && *bytes == 4) {
3573 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
3576 r = kvm_read_guest(vcpu->kvm, *gpa, &gentry, min(*bytes, 8));
3579 new = (const u8 *)&gentry;
3584 gentry = *(const u32 *)new;
3587 gentry = *(const u64 *)new;
3598 * If we're seeing too many writes to a page, it may no longer be a page table,
3599 * or we may be forking, in which case it is better to unmap the page.
3601 static bool detect_write_flooding(struct kvm_mmu_page *sp)
3604 * Skip write-flooding detected for the sp whose level is 1, because
3605 * it can become unsync, then the guest page is not write-protected.
3607 if (sp->role.level == PT_PAGE_TABLE_LEVEL)
3610 return ++sp->write_flooding_count >= 3;
3614 * Misaligned accesses are too much trouble to fix up; also, they usually
3615 * indicate a page is not used as a page table.
3617 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
3620 unsigned offset, pte_size, misaligned;
3622 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
3623 gpa, bytes, sp->role.word);
3625 offset = offset_in_page(gpa);
3626 pte_size = sp->role.cr4_pae ? 8 : 4;
3629 * Sometimes, the OS only writes the last one bytes to update status
3630 * bits, for example, in linux, andb instruction is used in clear_bit().
3632 if (!(offset & (pte_size - 1)) && bytes == 1)
3635 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
3636 misaligned |= bytes < 4;
3641 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
3643 unsigned page_offset, quadrant;
3647 page_offset = offset_in_page(gpa);
3648 level = sp->role.level;
3650 if (!sp->role.cr4_pae) {
3651 page_offset <<= 1; /* 32->64 */
3653 * A 32-bit pde maps 4MB while the shadow pdes map
3654 * only 2MB. So we need to double the offset again
3655 * and zap two pdes instead of one.
3657 if (level == PT32_ROOT_LEVEL) {
3658 page_offset &= ~7; /* kill rounding error */
3662 quadrant = page_offset >> PAGE_SHIFT;
3663 page_offset &= ~PAGE_MASK;
3664 if (quadrant != sp->role.quadrant)
3668 spte = &sp->spt[page_offset / sizeof(*spte)];
3672 void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
3673 const u8 *new, int bytes)
3675 gfn_t gfn = gpa >> PAGE_SHIFT;
3676 union kvm_mmu_page_role mask = { .word = 0 };
3677 struct kvm_mmu_page *sp;
3678 struct hlist_node *node;
3679 LIST_HEAD(invalid_list);
3680 u64 entry, gentry, *spte;
3682 bool remote_flush, local_flush, zap_page;
3685 * If we don't have indirect shadow pages, it means no page is
3686 * write-protected, so we can exit simply.
3688 if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
3691 zap_page = remote_flush = local_flush = false;
3693 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
3695 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes);
3698 * No need to care whether allocation memory is successful
3699 * or not since pte prefetch is skiped if it does not have
3700 * enough objects in the cache.
3702 mmu_topup_memory_caches(vcpu);
3704 spin_lock(&vcpu->kvm->mmu_lock);
3705 ++vcpu->kvm->stat.mmu_pte_write;
3706 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
3708 mask.cr0_wp = mask.cr4_pae = mask.nxe = 1;
3709 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) {
3710 if (detect_write_misaligned(sp, gpa, bytes) ||
3711 detect_write_flooding(sp)) {
3712 zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
3714 ++vcpu->kvm->stat.mmu_flooded;
3718 spte = get_written_sptes(sp, gpa, &npte);
3725 mmu_page_zap_pte(vcpu->kvm, sp, spte);
3727 !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
3728 & mask.word) && rmap_can_add(vcpu))
3729 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
3730 if (!remote_flush && need_remote_flush(entry, *spte))
3731 remote_flush = true;
3735 mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush);
3736 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3737 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
3738 spin_unlock(&vcpu->kvm->mmu_lock);
3741 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
3746 if (vcpu->arch.mmu.direct_map)
3749 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
3751 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
3755 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
3757 void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
3759 LIST_HEAD(invalid_list);
3761 while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES &&
3762 !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
3763 struct kvm_mmu_page *sp;
3765 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
3766 struct kvm_mmu_page, link);
3767 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
3768 ++vcpu->kvm->stat.mmu_recycled;
3770 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3773 static bool is_mmio_page_fault(struct kvm_vcpu *vcpu, gva_t addr)
3775 if (vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu))
3776 return vcpu_match_mmio_gpa(vcpu, addr);
3778 return vcpu_match_mmio_gva(vcpu, addr);
3781 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code,
3782 void *insn, int insn_len)
3784 int r, emulation_type = EMULTYPE_RETRY;
3785 enum emulation_result er;
3787 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false);
3796 if (is_mmio_page_fault(vcpu, cr2))
3799 er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len);
3804 case EMULATE_DO_MMIO:
3805 ++vcpu->stat.mmio_exits;
3815 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
3817 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
3819 vcpu->arch.mmu.invlpg(vcpu, gva);
3820 kvm_mmu_flush_tlb(vcpu);
3821 ++vcpu->stat.invlpg;
3823 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
3825 void kvm_enable_tdp(void)
3829 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
3831 void kvm_disable_tdp(void)
3833 tdp_enabled = false;
3835 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
3837 static void free_mmu_pages(struct kvm_vcpu *vcpu)
3839 free_page((unsigned long)vcpu->arch.mmu.pae_root);
3840 if (vcpu->arch.mmu.lm_root != NULL)
3841 free_page((unsigned long)vcpu->arch.mmu.lm_root);
3844 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
3852 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
3853 * Therefore we need to allocate shadow page tables in the first
3854 * 4GB of memory, which happens to fit the DMA32 zone.
3856 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
3860 vcpu->arch.mmu.pae_root = page_address(page);
3861 for (i = 0; i < 4; ++i)
3862 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
3867 int kvm_mmu_create(struct kvm_vcpu *vcpu)
3871 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
3872 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
3873 vcpu->arch.mmu.translate_gpa = translate_gpa;
3874 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
3876 return alloc_mmu_pages(vcpu);
3879 int kvm_mmu_setup(struct kvm_vcpu *vcpu)
3882 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3884 return init_kvm_mmu(vcpu);
3887 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
3889 struct kvm_mmu_page *sp;
3891 list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
3895 if (!test_bit(slot, sp->slot_bitmap))
3899 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3900 if (!is_shadow_present_pte(pt[i]) ||
3901 !is_last_spte(pt[i], sp->role.level))
3904 if (is_large_pte(pt[i])) {
3905 drop_spte(kvm, &pt[i]);
3911 if (is_writable_pte(pt[i]))
3912 mmu_spte_update(&pt[i],
3913 pt[i] & ~PT_WRITABLE_MASK);
3916 kvm_flush_remote_tlbs(kvm);
3919 void kvm_mmu_zap_all(struct kvm *kvm)
3921 struct kvm_mmu_page *sp, *node;
3922 LIST_HEAD(invalid_list);
3924 spin_lock(&kvm->mmu_lock);
3926 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
3927 if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list))
3930 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3931 spin_unlock(&kvm->mmu_lock);
3934 static void kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm,
3935 struct list_head *invalid_list)
3937 struct kvm_mmu_page *page;
3939 page = container_of(kvm->arch.active_mmu_pages.prev,
3940 struct kvm_mmu_page, link);
3941 kvm_mmu_prepare_zap_page(kvm, page, invalid_list);
3944 static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc)
3947 int nr_to_scan = sc->nr_to_scan;
3949 if (nr_to_scan == 0)
3952 raw_spin_lock(&kvm_lock);
3954 list_for_each_entry(kvm, &vm_list, vm_list) {
3956 LIST_HEAD(invalid_list);
3959 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
3960 * here. We may skip a VM instance errorneosly, but we do not
3961 * want to shrink a VM that only started to populate its MMU
3964 if (kvm->arch.n_used_mmu_pages > 0) {
3970 idx = srcu_read_lock(&kvm->srcu);
3971 spin_lock(&kvm->mmu_lock);
3973 kvm_mmu_remove_some_alloc_mmu_pages(kvm, &invalid_list);
3974 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3976 spin_unlock(&kvm->mmu_lock);
3977 srcu_read_unlock(&kvm->srcu, idx);
3979 list_move_tail(&kvm->vm_list, &vm_list);
3983 raw_spin_unlock(&kvm_lock);
3986 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
3989 static struct shrinker mmu_shrinker = {
3990 .shrink = mmu_shrink,
3991 .seeks = DEFAULT_SEEKS * 10,
3994 static void mmu_destroy_caches(void)
3996 if (pte_list_desc_cache)
3997 kmem_cache_destroy(pte_list_desc_cache);
3998 if (mmu_page_header_cache)
3999 kmem_cache_destroy(mmu_page_header_cache);
4002 int kvm_mmu_module_init(void)
4004 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
4005 sizeof(struct pte_list_desc),
4007 if (!pte_list_desc_cache)
4010 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
4011 sizeof(struct kvm_mmu_page),
4013 if (!mmu_page_header_cache)
4016 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0))
4019 register_shrinker(&mmu_shrinker);
4024 mmu_destroy_caches();
4029 * Caculate mmu pages needed for kvm.
4031 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
4033 unsigned int nr_mmu_pages;
4034 unsigned int nr_pages = 0;
4035 struct kvm_memslots *slots;
4036 struct kvm_memory_slot *memslot;
4038 slots = kvm_memslots(kvm);
4040 kvm_for_each_memslot(memslot, slots)
4041 nr_pages += memslot->npages;
4043 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
4044 nr_mmu_pages = max(nr_mmu_pages,
4045 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
4047 return nr_mmu_pages;
4050 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
4052 struct kvm_shadow_walk_iterator iterator;
4056 walk_shadow_page_lockless_begin(vcpu);
4057 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
4058 sptes[iterator.level-1] = spte;
4060 if (!is_shadow_present_pte(spte))
4063 walk_shadow_page_lockless_end(vcpu);
4067 EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
4069 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
4073 destroy_kvm_mmu(vcpu);
4074 free_mmu_pages(vcpu);
4075 mmu_free_memory_caches(vcpu);
4078 void kvm_mmu_module_exit(void)
4080 mmu_destroy_caches();
4081 percpu_counter_destroy(&kvm_total_used_mmu_pages);
4082 unregister_shrinker(&mmu_shrinker);
4083 mmu_audit_disable();