3 * Local APIC virtualization
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
21 #include <linux/kvm_host.h>
22 #include <linux/kvm.h>
24 #include <linux/highmem.h>
25 #include <linux/smp.h>
26 #include <linux/hrtimer.h>
28 #include <linux/module.h>
29 #include <linux/math64.h>
30 #include <linux/slab.h>
31 #include <asm/processor.h>
34 #include <asm/current.h>
35 #include <asm/apicdef.h>
36 #include <linux/atomic.h>
37 #include "kvm_cache_regs.h"
44 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
46 #define mod_64(x, y) ((x) % (y))
54 #define APIC_BUS_CYCLE_NS 1
56 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
57 #define apic_debug(fmt, arg...)
59 #define APIC_LVT_NUM 6
60 /* 14 is the version for Xeon and Pentium 8.4.8*/
61 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
62 #define LAPIC_MMIO_LENGTH (1 << 12)
63 /* followed define is not in apicdef.h */
64 #define APIC_SHORT_MASK 0xc0000
65 #define APIC_DEST_NOSHORT 0x0
66 #define APIC_DEST_MASK 0x800
67 #define MAX_APIC_VECTOR 256
69 #define VEC_POS(v) ((v) & (32 - 1))
70 #define REG_POS(v) (((v) >> 5) << 4)
72 static unsigned int min_timer_period_us = 500;
73 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
75 static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
77 return *((u32 *) (apic->regs + reg_off));
80 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
82 *((u32 *) (apic->regs + reg_off)) = val;
85 static inline int apic_test_and_set_vector(int vec, void *bitmap)
87 return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
90 static inline int apic_test_and_clear_vector(int vec, void *bitmap)
92 return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
95 static inline int apic_test_vector(int vec, void *bitmap)
97 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
100 static inline void apic_set_vector(int vec, void *bitmap)
102 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
105 static inline void apic_clear_vector(int vec, void *bitmap)
107 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
110 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
112 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
115 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
117 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
120 static inline int apic_hw_enabled(struct kvm_lapic *apic)
122 return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
125 static inline int apic_sw_enabled(struct kvm_lapic *apic)
127 return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
130 static inline int apic_enabled(struct kvm_lapic *apic)
132 return apic_sw_enabled(apic) && apic_hw_enabled(apic);
136 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
139 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
140 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
142 static inline int kvm_apic_id(struct kvm_lapic *apic)
144 return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
147 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
149 return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
152 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
154 return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
157 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
159 return ((apic_get_reg(apic, APIC_LVTT) &
160 apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_ONESHOT);
163 static inline int apic_lvtt_period(struct kvm_lapic *apic)
165 return ((apic_get_reg(apic, APIC_LVTT) &
166 apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_PERIODIC);
169 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
171 return ((apic_get_reg(apic, APIC_LVTT) &
172 apic->lapic_timer.timer_mode_mask) ==
173 APIC_LVT_TIMER_TSCDEADLINE);
176 static inline int apic_lvt_nmi_mode(u32 lvt_val)
178 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
181 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
183 struct kvm_lapic *apic = vcpu->arch.apic;
184 struct kvm_cpuid_entry2 *feat;
185 u32 v = APIC_VERSION;
187 if (!irqchip_in_kernel(vcpu->kvm))
190 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
191 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
192 v |= APIC_LVR_DIRECTED_EOI;
193 apic_set_reg(apic, APIC_LVR, v);
196 static inline int apic_x2apic_mode(struct kvm_lapic *apic)
198 return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
201 static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
202 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
203 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
204 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
205 LINT_MASK, LINT_MASK, /* LVT0-1 */
206 LVT_MASK /* LVTERR */
209 static int find_highest_vector(void *bitmap)
212 int word_offset = MAX_APIC_VECTOR >> 5;
214 while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
217 if (likely(!word_offset && !word[0]))
220 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
223 static u8 count_vectors(void *bitmap)
228 for (word_offset = 0; word_offset < MAX_APIC_VECTOR >> 5; ++word_offset)
229 count += hweight32(word[word_offset << 2]);
233 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
235 apic->irr_pending = true;
236 return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
239 static inline int apic_search_irr(struct kvm_lapic *apic)
241 return find_highest_vector(apic->regs + APIC_IRR);
244 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
248 if (!apic->irr_pending)
251 result = apic_search_irr(apic);
252 ASSERT(result == -1 || result >= 16);
257 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
259 apic->irr_pending = false;
260 apic_clear_vector(vec, apic->regs + APIC_IRR);
261 if (apic_search_irr(apic) != -1)
262 apic->irr_pending = true;
265 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
267 if (!__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
269 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
271 * ISR (in service register) bit is set when injecting an interrupt.
272 * The highest vector is injected. Thus the latest bit set matches
273 * the highest bit in ISR.
275 apic->highest_isr_cache = vec;
278 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
280 if (__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
282 BUG_ON(apic->isr_count < 0);
283 apic->highest_isr_cache = -1;
286 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
288 struct kvm_lapic *apic = vcpu->arch.apic;
291 /* This may race with setting of irr in __apic_accept_irq() and
292 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
293 * will cause vmexit immediately and the value will be recalculated
294 * on the next vmentry.
298 highest_irr = apic_find_highest_irr(apic);
303 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
304 int vector, int level, int trig_mode);
306 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq)
308 struct kvm_lapic *apic = vcpu->arch.apic;
310 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
311 irq->level, irq->trig_mode);
314 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
317 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
321 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
324 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
328 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
330 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
333 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
336 if (pv_eoi_get_user(vcpu, &val) < 0)
337 apic_debug("Can't read EOI MSR value: 0x%llx\n",
338 (unsigned long long)vcpi->arch.pv_eoi.msr_val);
342 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
344 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
345 apic_debug("Can't set EOI MSR value: 0x%llx\n",
346 (unsigned long long)vcpi->arch.pv_eoi.msr_val);
349 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
352 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
354 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
355 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
356 (unsigned long long)vcpi->arch.pv_eoi.msr_val);
359 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
362 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
365 if (!apic->isr_count)
367 if (likely(apic->highest_isr_cache != -1))
368 return apic->highest_isr_cache;
370 result = find_highest_vector(apic->regs + APIC_ISR);
371 ASSERT(result == -1 || result >= 16);
376 static void apic_update_ppr(struct kvm_lapic *apic)
378 u32 tpr, isrv, ppr, old_ppr;
381 old_ppr = apic_get_reg(apic, APIC_PROCPRI);
382 tpr = apic_get_reg(apic, APIC_TASKPRI);
383 isr = apic_find_highest_isr(apic);
384 isrv = (isr != -1) ? isr : 0;
386 if ((tpr & 0xf0) >= (isrv & 0xf0))
391 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
392 apic, ppr, isr, isrv);
394 if (old_ppr != ppr) {
395 apic_set_reg(apic, APIC_PROCPRI, ppr);
397 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
401 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
403 apic_set_reg(apic, APIC_TASKPRI, tpr);
404 apic_update_ppr(apic);
407 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
409 return dest == 0xff || kvm_apic_id(apic) == dest;
412 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
417 if (apic_x2apic_mode(apic)) {
418 logical_id = apic_get_reg(apic, APIC_LDR);
419 return logical_id & mda;
422 logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
424 switch (apic_get_reg(apic, APIC_DFR)) {
426 if (logical_id & mda)
429 case APIC_DFR_CLUSTER:
430 if (((logical_id >> 4) == (mda >> 0x4))
431 && (logical_id & mda & 0xf))
435 apic_debug("Bad DFR vcpu %d: %08x\n",
436 apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
443 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
444 int short_hand, int dest, int dest_mode)
447 struct kvm_lapic *target = vcpu->arch.apic;
449 apic_debug("target %p, source %p, dest 0x%x, "
450 "dest_mode 0x%x, short_hand 0x%x\n",
451 target, source, dest, dest_mode, short_hand);
454 switch (short_hand) {
455 case APIC_DEST_NOSHORT:
458 result = kvm_apic_match_physical_addr(target, dest);
461 result = kvm_apic_match_logical_addr(target, dest);
464 result = (target == source);
466 case APIC_DEST_ALLINC:
469 case APIC_DEST_ALLBUT:
470 result = (target != source);
473 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
482 * Add a pending IRQ into lapic.
483 * Return 1 if successfully added and 0 if discarded.
485 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
486 int vector, int level, int trig_mode)
489 struct kvm_vcpu *vcpu = apic->vcpu;
491 switch (delivery_mode) {
493 vcpu->arch.apic_arb_prio++;
495 /* FIXME add logic for vcpu on reset */
496 if (unlikely(!apic_enabled(apic)))
500 apic_debug("level trig mode for vector %d", vector);
501 apic_set_vector(vector, apic->regs + APIC_TMR);
503 apic_clear_vector(vector, apic->regs + APIC_TMR);
505 result = !apic_test_and_set_irr(vector, apic);
506 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
507 trig_mode, vector, !result);
510 apic_debug("level trig mode repeatedly for "
511 "vector %d", vector);
515 kvm_make_request(KVM_REQ_EVENT, vcpu);
520 apic_debug("Ignoring delivery mode 3\n");
524 apic_debug("Ignoring guest SMI\n");
529 kvm_inject_nmi(vcpu);
534 if (!trig_mode || level) {
536 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
537 kvm_make_request(KVM_REQ_EVENT, vcpu);
540 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
545 case APIC_DM_STARTUP:
546 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
547 vcpu->vcpu_id, vector);
548 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
550 vcpu->arch.sipi_vector = vector;
551 vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
552 kvm_make_request(KVM_REQ_EVENT, vcpu);
559 * Should only be called by kvm_apic_local_deliver() with LVT0,
560 * before NMI watchdog was enabled. Already handled by
561 * kvm_apic_accept_pic_intr().
566 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
573 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
575 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
578 static int apic_set_eoi(struct kvm_lapic *apic)
580 int vector = apic_find_highest_isr(apic);
582 trace_kvm_eoi(apic, vector);
585 * Not every write EOI will has corresponding ISR,
586 * one example is when Kernel check timer on setup_IO_APIC
591 apic_clear_isr(vector, apic);
592 apic_update_ppr(apic);
594 if (!(apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) &&
595 kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
597 if (apic_test_vector(vector, apic->regs + APIC_TMR))
598 trigger_mode = IOAPIC_LEVEL_TRIG;
600 trigger_mode = IOAPIC_EDGE_TRIG;
601 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
603 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
607 static void apic_send_ipi(struct kvm_lapic *apic)
609 u32 icr_low = apic_get_reg(apic, APIC_ICR);
610 u32 icr_high = apic_get_reg(apic, APIC_ICR2);
611 struct kvm_lapic_irq irq;
613 irq.vector = icr_low & APIC_VECTOR_MASK;
614 irq.delivery_mode = icr_low & APIC_MODE_MASK;
615 irq.dest_mode = icr_low & APIC_DEST_MASK;
616 irq.level = icr_low & APIC_INT_ASSERT;
617 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
618 irq.shorthand = icr_low & APIC_SHORT_MASK;
619 if (apic_x2apic_mode(apic))
620 irq.dest_id = icr_high;
622 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
624 trace_kvm_apic_ipi(icr_low, irq.dest_id);
626 apic_debug("icr_high 0x%x, icr_low 0x%x, "
627 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
628 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
629 icr_high, icr_low, irq.shorthand, irq.dest_id,
630 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
633 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq);
636 static u32 apic_get_tmcct(struct kvm_lapic *apic)
642 ASSERT(apic != NULL);
644 /* if initial count is 0, current count should also be 0 */
645 if (apic_get_reg(apic, APIC_TMICT) == 0)
648 remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
649 if (ktime_to_ns(remaining) < 0)
650 remaining = ktime_set(0, 0);
652 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
653 tmcct = div64_u64(ns,
654 (APIC_BUS_CYCLE_NS * apic->divide_count));
659 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
661 struct kvm_vcpu *vcpu = apic->vcpu;
662 struct kvm_run *run = vcpu->run;
664 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
665 run->tpr_access.rip = kvm_rip_read(vcpu);
666 run->tpr_access.is_write = write;
669 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
671 if (apic->vcpu->arch.tpr_access_reporting)
672 __report_tpr_access(apic, write);
675 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
679 if (offset >= LAPIC_MMIO_LENGTH)
684 if (apic_x2apic_mode(apic))
685 val = kvm_apic_id(apic);
687 val = kvm_apic_id(apic) << 24;
690 apic_debug("Access APIC ARBPRI register which is for P6\n");
693 case APIC_TMCCT: /* Timer CCR */
694 if (apic_lvtt_tscdeadline(apic))
697 val = apic_get_tmcct(apic);
700 apic_update_ppr(apic);
701 val = apic_get_reg(apic, offset);
704 report_tpr_access(apic, false);
707 val = apic_get_reg(apic, offset);
714 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
716 return container_of(dev, struct kvm_lapic, dev);
719 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
722 unsigned char alignment = offset & 0xf;
724 /* this bitmask has a bit cleared for each reserved register */
725 static const u64 rmask = 0x43ff01ffffffe70cULL;
727 if ((alignment + len) > 4) {
728 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
733 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
734 apic_debug("KVM_APIC_READ: read reserved register %x\n",
739 result = __apic_read(apic, offset & ~0xf);
741 trace_kvm_apic_read(offset, result);
747 memcpy(data, (char *)&result + alignment, len);
750 printk(KERN_ERR "Local APIC read with len = %x, "
751 "should be 1,2, or 4 instead\n", len);
757 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
759 return apic_hw_enabled(apic) &&
760 addr >= apic->base_address &&
761 addr < apic->base_address + LAPIC_MMIO_LENGTH;
764 static int apic_mmio_read(struct kvm_io_device *this,
765 gpa_t address, int len, void *data)
767 struct kvm_lapic *apic = to_lapic(this);
768 u32 offset = address - apic->base_address;
770 if (!apic_mmio_in_range(apic, address))
773 apic_reg_read(apic, offset, len, data);
778 static void update_divide_count(struct kvm_lapic *apic)
780 u32 tmp1, tmp2, tdcr;
782 tdcr = apic_get_reg(apic, APIC_TDCR);
784 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
785 apic->divide_count = 0x1 << (tmp2 & 0x7);
787 apic_debug("timer divide count is 0x%x\n",
791 static void start_apic_timer(struct kvm_lapic *apic)
794 atomic_set(&apic->lapic_timer.pending, 0);
796 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
797 /* lapic timer in oneshot or periodic mode */
798 now = apic->lapic_timer.timer.base->get_time();
799 apic->lapic_timer.period = (u64)apic_get_reg(apic, APIC_TMICT)
800 * APIC_BUS_CYCLE_NS * apic->divide_count;
802 if (!apic->lapic_timer.period)
805 * Do not allow the guest to program periodic timers with small
806 * interval, since the hrtimers are not throttled by the host
809 if (apic_lvtt_period(apic)) {
810 s64 min_period = min_timer_period_us * 1000LL;
812 if (apic->lapic_timer.period < min_period) {
814 "kvm: vcpu %i: requested %lld ns "
815 "lapic timer period limited to %lld ns\n",
817 apic->lapic_timer.period, min_period);
818 apic->lapic_timer.period = min_period;
822 hrtimer_start(&apic->lapic_timer.timer,
823 ktime_add_ns(now, apic->lapic_timer.period),
826 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
828 "timer initial count 0x%x, period %lldns, "
829 "expire @ 0x%016" PRIx64 ".\n", __func__,
830 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
831 apic_get_reg(apic, APIC_TMICT),
832 apic->lapic_timer.period,
833 ktime_to_ns(ktime_add_ns(now,
834 apic->lapic_timer.period)));
835 } else if (apic_lvtt_tscdeadline(apic)) {
836 /* lapic timer in tsc deadline mode */
837 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
839 struct kvm_vcpu *vcpu = apic->vcpu;
840 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
843 if (unlikely(!tscdeadline || !this_tsc_khz))
846 local_irq_save(flags);
848 now = apic->lapic_timer.timer.base->get_time();
849 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
850 if (likely(tscdeadline > guest_tsc)) {
851 ns = (tscdeadline - guest_tsc) * 1000000ULL;
852 do_div(ns, this_tsc_khz);
854 hrtimer_start(&apic->lapic_timer.timer,
855 ktime_add_ns(now, ns), HRTIMER_MODE_ABS);
857 local_irq_restore(flags);
861 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
863 int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0));
865 if (apic_lvt_nmi_mode(lvt0_val)) {
866 if (!nmi_wd_enabled) {
867 apic_debug("Receive NMI setting on APIC_LVT0 "
868 "for cpu %d\n", apic->vcpu->vcpu_id);
869 apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
871 } else if (nmi_wd_enabled)
872 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
875 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
879 trace_kvm_apic_write(reg, val);
882 case APIC_ID: /* Local APIC ID */
883 if (!apic_x2apic_mode(apic))
884 apic_set_reg(apic, APIC_ID, val);
890 report_tpr_access(apic, true);
891 apic_set_tpr(apic, val & 0xff);
899 if (!apic_x2apic_mode(apic))
900 apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
906 if (!apic_x2apic_mode(apic))
907 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
914 if (apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
915 mask |= APIC_SPIV_DIRECTED_EOI;
916 apic_set_reg(apic, APIC_SPIV, val & mask);
917 if (!(val & APIC_SPIV_APIC_ENABLED)) {
921 for (i = 0; i < APIC_LVT_NUM; i++) {
922 lvt_val = apic_get_reg(apic,
923 APIC_LVTT + 0x10 * i);
924 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
925 lvt_val | APIC_LVT_MASKED);
927 atomic_set(&apic->lapic_timer.pending, 0);
933 /* No delay here, so we always clear the pending bit */
934 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
939 if (!apic_x2apic_mode(apic))
941 apic_set_reg(apic, APIC_ICR2, val);
945 apic_manage_nmi_watchdog(apic, val);
950 /* TODO: Check vector */
951 if (!apic_sw_enabled(apic))
952 val |= APIC_LVT_MASKED;
954 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
955 apic_set_reg(apic, reg, val);
960 if ((apic_get_reg(apic, APIC_LVTT) &
961 apic->lapic_timer.timer_mode_mask) !=
962 (val & apic->lapic_timer.timer_mode_mask))
963 hrtimer_cancel(&apic->lapic_timer.timer);
965 if (!apic_sw_enabled(apic))
966 val |= APIC_LVT_MASKED;
967 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
968 apic_set_reg(apic, APIC_LVTT, val);
972 if (apic_lvtt_tscdeadline(apic))
975 hrtimer_cancel(&apic->lapic_timer.timer);
976 apic_set_reg(apic, APIC_TMICT, val);
977 start_apic_timer(apic);
982 apic_debug("KVM_WRITE:TDCR %x\n", val);
983 apic_set_reg(apic, APIC_TDCR, val);
984 update_divide_count(apic);
988 if (apic_x2apic_mode(apic) && val != 0) {
989 apic_debug("KVM_WRITE:ESR not zero %x\n", val);
995 if (apic_x2apic_mode(apic)) {
996 apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1005 apic_debug("Local APIC Write to read-only register %x\n", reg);
1009 static int apic_mmio_write(struct kvm_io_device *this,
1010 gpa_t address, int len, const void *data)
1012 struct kvm_lapic *apic = to_lapic(this);
1013 unsigned int offset = address - apic->base_address;
1016 if (!apic_mmio_in_range(apic, address))
1020 * APIC register must be aligned on 128-bits boundary.
1021 * 32/64/128 bits registers must be accessed thru 32 bits.
1024 if (len != 4 || (offset & 0xf)) {
1025 /* Don't shout loud, $infamous_os would cause only noise. */
1026 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1032 /* too common printing */
1033 if (offset != APIC_EOI)
1034 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1035 "0x%x\n", __func__, offset, len, val);
1037 apic_reg_write(apic, offset & 0xff0, val);
1042 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1044 struct kvm_lapic *apic = vcpu->arch.apic;
1047 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1049 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1051 void kvm_free_lapic(struct kvm_vcpu *vcpu)
1053 if (!vcpu->arch.apic)
1056 hrtimer_cancel(&vcpu->arch.apic->lapic_timer.timer);
1058 if (vcpu->arch.apic->regs)
1059 free_page((unsigned long)vcpu->arch.apic->regs);
1061 kfree(vcpu->arch.apic);
1065 *----------------------------------------------------------------------
1067 *----------------------------------------------------------------------
1070 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1072 struct kvm_lapic *apic = vcpu->arch.apic;
1076 if (apic_lvtt_oneshot(apic) || apic_lvtt_period(apic))
1079 return apic->lapic_timer.tscdeadline;
1082 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1084 struct kvm_lapic *apic = vcpu->arch.apic;
1088 if (apic_lvtt_oneshot(apic) || apic_lvtt_period(apic))
1091 hrtimer_cancel(&apic->lapic_timer.timer);
1092 apic->lapic_timer.tscdeadline = data;
1093 start_apic_timer(apic);
1096 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1098 struct kvm_lapic *apic = vcpu->arch.apic;
1102 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1103 | (apic_get_reg(apic, APIC_TASKPRI) & 4));
1106 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1108 struct kvm_lapic *apic = vcpu->arch.apic;
1113 tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
1115 return (tpr & 0xf0) >> 4;
1118 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1120 struct kvm_lapic *apic = vcpu->arch.apic;
1123 value |= MSR_IA32_APICBASE_BSP;
1124 vcpu->arch.apic_base = value;
1128 if (!kvm_vcpu_is_bsp(apic->vcpu))
1129 value &= ~MSR_IA32_APICBASE_BSP;
1131 vcpu->arch.apic_base = value;
1132 if (apic_x2apic_mode(apic)) {
1133 u32 id = kvm_apic_id(apic);
1134 u32 ldr = ((id & ~0xf) << 16) | (1 << (id & 0xf));
1135 apic_set_reg(apic, APIC_LDR, ldr);
1137 apic->base_address = apic->vcpu->arch.apic_base &
1138 MSR_IA32_APICBASE_BASE;
1140 /* with FSB delivery interrupt, we can restart APIC functionality */
1141 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1142 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1146 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
1148 struct kvm_lapic *apic;
1151 apic_debug("%s\n", __func__);
1154 apic = vcpu->arch.apic;
1155 ASSERT(apic != NULL);
1157 /* Stop the timer in case it's a reset to an active apic */
1158 hrtimer_cancel(&apic->lapic_timer.timer);
1160 apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
1161 kvm_apic_set_version(apic->vcpu);
1163 for (i = 0; i < APIC_LVT_NUM; i++)
1164 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1165 apic_set_reg(apic, APIC_LVT0,
1166 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1168 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
1169 apic_set_reg(apic, APIC_SPIV, 0xff);
1170 apic_set_reg(apic, APIC_TASKPRI, 0);
1171 apic_set_reg(apic, APIC_LDR, 0);
1172 apic_set_reg(apic, APIC_ESR, 0);
1173 apic_set_reg(apic, APIC_ICR, 0);
1174 apic_set_reg(apic, APIC_ICR2, 0);
1175 apic_set_reg(apic, APIC_TDCR, 0);
1176 apic_set_reg(apic, APIC_TMICT, 0);
1177 for (i = 0; i < 8; i++) {
1178 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1179 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1180 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1182 apic->irr_pending = false;
1183 apic->isr_count = 0;
1184 apic->highest_isr_cache = -1;
1185 update_divide_count(apic);
1186 atomic_set(&apic->lapic_timer.pending, 0);
1187 if (kvm_vcpu_is_bsp(vcpu))
1188 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
1189 vcpu->arch.pv_eoi.msr_val = 0;
1190 apic_update_ppr(apic);
1192 vcpu->arch.apic_arb_prio = 0;
1193 vcpu->arch.apic_attention = 0;
1195 apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
1196 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1197 vcpu, kvm_apic_id(apic),
1198 vcpu->arch.apic_base, apic->base_address);
1201 bool kvm_apic_present(struct kvm_vcpu *vcpu)
1203 return vcpu->arch.apic && apic_hw_enabled(vcpu->arch.apic);
1206 int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
1208 return kvm_apic_present(vcpu) && apic_sw_enabled(vcpu->arch.apic);
1212 *----------------------------------------------------------------------
1214 *----------------------------------------------------------------------
1217 static bool lapic_is_periodic(struct kvm_lapic *apic)
1219 return apic_lvtt_period(apic);
1222 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1224 struct kvm_lapic *lapic = vcpu->arch.apic;
1226 if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
1227 return atomic_read(&lapic->lapic_timer.pending);
1232 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1234 u32 reg = apic_get_reg(apic, lvt_type);
1235 int vector, mode, trig_mode;
1237 if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1238 vector = reg & APIC_VECTOR_MASK;
1239 mode = reg & APIC_MODE_MASK;
1240 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1241 return __apic_accept_irq(apic, mode, vector, 1, trig_mode);
1246 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1248 struct kvm_lapic *apic = vcpu->arch.apic;
1251 kvm_apic_local_deliver(apic, APIC_LVT0);
1254 static const struct kvm_io_device_ops apic_mmio_ops = {
1255 .read = apic_mmio_read,
1256 .write = apic_mmio_write,
1259 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1261 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
1262 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
1263 struct kvm_vcpu *vcpu = apic->vcpu;
1264 wait_queue_head_t *q = &vcpu->wq;
1267 * There is a race window between reading and incrementing, but we do
1268 * not care about potentially losing timer events in the !reinject
1269 * case anyway. Note: KVM_REQ_PENDING_TIMER is implicitly checked
1270 * in vcpu_enter_guest.
1272 if (!atomic_read(&ktimer->pending)) {
1273 atomic_inc(&ktimer->pending);
1274 /* FIXME: this code should not know anything about vcpus */
1275 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1278 if (waitqueue_active(q))
1279 wake_up_interruptible(q);
1281 if (lapic_is_periodic(apic)) {
1282 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1283 return HRTIMER_RESTART;
1285 return HRTIMER_NORESTART;
1288 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1290 struct kvm_lapic *apic;
1292 ASSERT(vcpu != NULL);
1293 apic_debug("apic_init %d\n", vcpu->vcpu_id);
1295 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1299 vcpu->arch.apic = apic;
1301 apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1303 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1305 goto nomem_free_apic;
1309 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1311 apic->lapic_timer.timer.function = apic_timer_fn;
1313 apic->base_address = APIC_DEFAULT_PHYS_BASE;
1314 vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
1316 kvm_lapic_reset(vcpu);
1317 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1326 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1328 struct kvm_lapic *apic = vcpu->arch.apic;
1331 if (!apic || !apic_enabled(apic))
1334 apic_update_ppr(apic);
1335 highest_irr = apic_find_highest_irr(apic);
1336 if ((highest_irr == -1) ||
1337 ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
1342 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1344 u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1347 if (!apic_hw_enabled(vcpu->arch.apic))
1349 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1350 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1355 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1357 struct kvm_lapic *apic = vcpu->arch.apic;
1359 if (apic && atomic_read(&apic->lapic_timer.pending) > 0) {
1360 if (kvm_apic_local_deliver(apic, APIC_LVTT))
1361 atomic_dec(&apic->lapic_timer.pending);
1365 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1367 int vector = kvm_apic_has_interrupt(vcpu);
1368 struct kvm_lapic *apic = vcpu->arch.apic;
1373 apic_set_isr(vector, apic);
1374 apic_update_ppr(apic);
1375 apic_clear_irr(vector, apic);
1379 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1381 struct kvm_lapic *apic = vcpu->arch.apic;
1383 apic->base_address = vcpu->arch.apic_base &
1384 MSR_IA32_APICBASE_BASE;
1385 kvm_apic_set_version(vcpu);
1387 apic_update_ppr(apic);
1388 hrtimer_cancel(&apic->lapic_timer.timer);
1389 update_divide_count(apic);
1390 start_apic_timer(apic);
1391 apic->irr_pending = true;
1392 apic->isr_count = count_vectors(apic->regs + APIC_ISR);
1393 apic->highest_isr_cache = -1;
1394 kvm_make_request(KVM_REQ_EVENT, vcpu);
1397 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1399 struct kvm_lapic *apic = vcpu->arch.apic;
1400 struct hrtimer *timer;
1405 timer = &apic->lapic_timer.timer;
1406 if (hrtimer_cancel(timer))
1407 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1411 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1413 * Detect whether guest triggered PV EOI since the
1414 * last entry. If yes, set EOI on guests's behalf.
1415 * Clear PV EOI in guest memory in any case.
1417 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1418 struct kvm_lapic *apic)
1423 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1424 * and KVM_PV_EOI_ENABLED in guest memory as follows:
1426 * KVM_APIC_PV_EOI_PENDING is unset:
1427 * -> host disabled PV EOI.
1428 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1429 * -> host enabled PV EOI, guest did not execute EOI yet.
1430 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1431 * -> host enabled PV EOI, guest executed EOI.
1433 BUG_ON(!pv_eoi_enabled(vcpu));
1434 pending = pv_eoi_get_pending(vcpu);
1436 * Clear pending bit in any case: it will be set again on vmentry.
1437 * While this might not be ideal from performance point of view,
1438 * this makes sure pv eoi is only enabled when we know it's safe.
1440 pv_eoi_clr_pending(vcpu);
1443 vector = apic_set_eoi(apic);
1444 trace_kvm_pv_eoi(apic, vector);
1447 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1452 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1453 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1455 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1458 vapic = kmap_atomic(vcpu->arch.apic->vapic_page);
1459 data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1460 kunmap_atomic(vapic);
1462 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1466 * apic_sync_pv_eoi_to_guest - called before vmentry
1468 * Detect whether it's safe to enable PV EOI and
1471 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
1472 struct kvm_lapic *apic)
1474 if (!pv_eoi_enabled(vcpu) ||
1475 /* IRR set or many bits in ISR: could be nested. */
1476 apic->irr_pending ||
1477 /* Cache not set: could be safe but we don't bother. */
1478 apic->highest_isr_cache == -1 ||
1479 /* Need EOI to update ioapic. */
1480 kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) {
1482 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1483 * so we need not do anything here.
1488 pv_eoi_set_pending(apic->vcpu);
1491 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1494 int max_irr, max_isr;
1495 struct kvm_lapic *apic = vcpu->arch.apic;
1498 apic_sync_pv_eoi_to_guest(vcpu, apic);
1500 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1503 tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1504 max_irr = apic_find_highest_irr(apic);
1507 max_isr = apic_find_highest_isr(apic);
1510 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1512 vapic = kmap_atomic(vcpu->arch.apic->vapic_page);
1513 *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1514 kunmap_atomic(vapic);
1517 void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1519 vcpu->arch.apic->vapic_addr = vapic_addr;
1521 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1523 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1526 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1528 struct kvm_lapic *apic = vcpu->arch.apic;
1529 u32 reg = (msr - APIC_BASE_MSR) << 4;
1531 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1534 /* if this is ICR write vector before command */
1536 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1537 return apic_reg_write(apic, reg, (u32)data);
1540 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1542 struct kvm_lapic *apic = vcpu->arch.apic;
1543 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1545 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1548 if (apic_reg_read(apic, reg, 4, &low))
1551 apic_reg_read(apic, APIC_ICR2, 4, &high);
1553 *data = (((u64)high) << 32) | low;
1558 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1560 struct kvm_lapic *apic = vcpu->arch.apic;
1562 if (!irqchip_in_kernel(vcpu->kvm))
1565 /* if this is ICR write vector before command */
1566 if (reg == APIC_ICR)
1567 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1568 return apic_reg_write(apic, reg, (u32)data);
1571 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
1573 struct kvm_lapic *apic = vcpu->arch.apic;
1576 if (!irqchip_in_kernel(vcpu->kvm))
1579 if (apic_reg_read(apic, reg, 4, &low))
1581 if (reg == APIC_ICR)
1582 apic_reg_read(apic, APIC_ICR2, 4, &high);
1584 *data = (((u64)high) << 32) | low;
1589 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
1591 u64 addr = data & ~KVM_MSR_ENABLED;
1592 if (!IS_ALIGNED(addr, 4))
1595 vcpu->arch.pv_eoi.msr_val = data;
1596 if (!pv_eoi_enabled(vcpu))
1598 return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,