arch/x86/kvm/lapic.c

   1
   2 /*
   3  * Local APIC virtualization
   4  *
   5  * Copyright (C) 2006 Qumranet, Inc.
   6  * Copyright (C) 2007 Novell
   7  * Copyright (C) 2007 Intel
   8  * Copyright 2009 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Dor Laor <dor.laor@qumranet.com>
  12  *   Gregory Haskins <ghaskins@novell.com>
  13  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
  14  *
  15  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  16  *
  17  * This work is licensed under the terms of the GNU GPL, version 2.  See
  18  * the COPYING file in the top-level directory.
  19  */
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/kvm.h>
  23 #include <linux/mm.h>
  24 #include <linux/highmem.h>
  25 #include <linux/smp.h>
  26 #include <linux/hrtimer.h>
  27 #include <linux/io.h>
  28 #include <linux/module.h>
  29 #include <linux/math64.h>
  30 #include <linux/slab.h>
  31 #include <asm/processor.h>
  32 #include <asm/msr.h>
  33 #include <asm/page.h>
  34 #include <asm/current.h>
  35 #include <asm/apicdef.h>
  36 #include <linux/atomic.h>
  37 #include <linux/jump_label.h>
  38 #include "kvm_cache_regs.h"
  39 #include "irq.h"
  40 #include "trace.h"
  41 #include "x86.h"
  42 #include "cpuid.h"
  43
  44 #ifndef CONFIG_X86_64
  45 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
  46 #else
  47 #define mod_64(x, y) ((x) % (y))
  48 #endif
  49
  50 #define PRId64 "d"
  51 #define PRIx64 "llx"
  52 #define PRIu64 "u"
  53 #define PRIo64 "o"
  54
  55 #define APIC_BUS_CYCLE_NS 1
  56
  57 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  58 #define apic_debug(fmt, arg...)
  59
  60 #define APIC_LVT_NUM                    6
  61 /* 14 is the version for Xeon and Pentium 8.4.8*/
  62 #define APIC_VERSION                    (0x14UL | ((APIC_LVT_NUM - 1) << 16))
  63 #define LAPIC_MMIO_LENGTH               (1 << 12)
  64 /* followed define is not in apicdef.h */
  65 #define APIC_SHORT_MASK                 0xc0000
  66 #define APIC_DEST_NOSHORT               0x0
  67 #define APIC_DEST_MASK                  0x800
  68 #define MAX_APIC_VECTOR                 256
  69
  70 #define VEC_POS(v) ((v) & (32 - 1))
  71 #define REG_POS(v) (((v) >> 5) << 4)
  72
  73 static unsigned int min_timer_period_us = 500;
  74 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
  75
  76 static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
  77 {
  78         return *((u32 *) (apic->regs + reg_off));
  79 }
  80
  81 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
  82 {
  83         *((u32 *) (apic->regs + reg_off)) = val;
  84 }
  85
  86 static inline int apic_test_and_set_vector(int vec, void *bitmap)
  87 {
  88         return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  89 }
  90
  91 static inline int apic_test_and_clear_vector(int vec, void *bitmap)
  92 {
  93         return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  94 }
  95
  96 static inline int apic_test_vector(int vec, void *bitmap)
  97 {
  98         return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  99 }
 100
 101 static inline void apic_set_vector(int vec, void *bitmap)
 102 {
 103         set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 104 }
 105
 106 static inline void apic_clear_vector(int vec, void *bitmap)
 107 {
 108         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 109 }
 110
 111 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
 112 {
 113         return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 114 }
 115
 116 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
 117 {
 118         return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 119 }
 120
 121 struct static_key_deferred apic_hw_disabled __read_mostly;
 122
 123 static inline int apic_hw_enabled(struct kvm_lapic *apic)
 124 {
 125         if (static_key_false(&apic_hw_disabled.key))
 126                 return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
 127         return MSR_IA32_APICBASE_ENABLE;
 128 }
 129
 130 struct static_key_deferred apic_sw_disabled __read_mostly;
 131
 132 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
 133 {
 134         if ((apic_get_reg(apic, APIC_SPIV) ^ val) & APIC_SPIV_APIC_ENABLED) {
 135                 if (val & APIC_SPIV_APIC_ENABLED)
 136                         static_key_slow_dec_deferred(&apic_sw_disabled);
 137                 else
 138                         static_key_slow_inc(&apic_sw_disabled.key);
 139         }
 140         apic_set_reg(apic, APIC_SPIV, val);
 141 }
 142
 143 static inline int apic_sw_enabled(struct kvm_lapic *apic)
 144 {
 145         if (static_key_false(&apic_sw_disabled.key))
 146                 return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
 147         return APIC_SPIV_APIC_ENABLED;
 148 }
 149
 150 static inline int apic_enabled(struct kvm_lapic *apic)
 151 {
 152         return apic_sw_enabled(apic) && apic_hw_enabled(apic);
 153 }
 154
 155 #define LVT_MASK        \
 156         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 157
 158 #define LINT_MASK       \
 159         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 160          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 161
 162 static inline int kvm_apic_id(struct kvm_lapic *apic)
 163 {
 164         return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
 165 }
 166
 167 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 168 {
 169         return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 170 }
 171
 172 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 173 {
 174         return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 175 }
 176
 177 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
 178 {
 179         return ((apic_get_reg(apic, APIC_LVTT) &
 180                 apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_ONESHOT);
 181 }
 182
 183 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 184 {
 185         return ((apic_get_reg(apic, APIC_LVTT) &
 186                 apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_PERIODIC);
 187 }
 188
 189 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
 190 {
 191         return ((apic_get_reg(apic, APIC_LVTT) &
 192                 apic->lapic_timer.timer_mode_mask) ==
 193                         APIC_LVT_TIMER_TSCDEADLINE);
 194 }
 195
 196 static inline int apic_lvt_nmi_mode(u32 lvt_val)
 197 {
 198         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
 199 }
 200
 201 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
 202 {
 203         struct kvm_lapic *apic = vcpu->arch.apic;
 204         struct kvm_cpuid_entry2 *feat;
 205         u32 v = APIC_VERSION;
 206
 207         if (!irqchip_in_kernel(vcpu->kvm))
 208                 return;
 209
 210         feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
 211         if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
 212                 v |= APIC_LVR_DIRECTED_EOI;
 213         apic_set_reg(apic, APIC_LVR, v);
 214 }
 215
 216 static inline int apic_x2apic_mode(struct kvm_lapic *apic)
 217 {
 218         return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
 219 }
 220
 221 static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
 222         LVT_MASK ,      /* part LVTT mask, timer mode mask added at runtime */
 223         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 224         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 225         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 226         LVT_MASK                /* LVTERR */
 227 };
 228
 229 static int find_highest_vector(void *bitmap)
 230 {
 231         u32 *word = bitmap;
 232         int word_offset = MAX_APIC_VECTOR >> 5;
 233
 234         while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
 235                 continue;
 236
 237         if (likely(!word_offset && !word[0]))
 238                 return -1;
 239         else
 240                 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
 241 }
 242
 243 static u8 count_vectors(void *bitmap)
 244 {
 245         u32 *word = bitmap;
 246         int word_offset;
 247         u8 count = 0;
 248         for (word_offset = 0; word_offset < MAX_APIC_VECTOR >> 5; ++word_offset)
 249                 count += hweight32(word[word_offset << 2]);
 250         return count;
 251 }
 252
 253 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
 254 {
 255         apic->irr_pending = true;
 256         return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
 257 }
 258
 259 static inline int apic_search_irr(struct kvm_lapic *apic)
 260 {
 261         return find_highest_vector(apic->regs + APIC_IRR);
 262 }
 263
 264 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 265 {
 266         int result;
 267
 268         if (!apic->irr_pending)
 269                 return -1;
 270
 271         result = apic_search_irr(apic);
 272         ASSERT(result == -1 || result >= 16);
 273
 274         return result;
 275 }
 276
 277 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 278 {
 279         apic->irr_pending = false;
 280         apic_clear_vector(vec, apic->regs + APIC_IRR);
 281         if (apic_search_irr(apic) != -1)
 282                 apic->irr_pending = true;
 283 }
 284
 285 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
 286 {
 287         if (!__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
 288                 ++apic->isr_count;
 289         BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
 290         /*
 291          * ISR (in service register) bit is set when injecting an interrupt.
 292          * The highest vector is injected. Thus the latest bit set matches
 293          * the highest bit in ISR.
 294          */
 295         apic->highest_isr_cache = vec;
 296 }
 297
 298 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
 299 {
 300         if (__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
 301                 --apic->isr_count;
 302         BUG_ON(apic->isr_count < 0);
 303         apic->highest_isr_cache = -1;
 304 }
 305
 306 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 307 {
 308         struct kvm_lapic *apic = vcpu->arch.apic;
 309         int highest_irr;
 310
 311         /* This may race with setting of irr in __apic_accept_irq() and
 312          * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
 313          * will cause vmexit immediately and the value will be recalculated
 314          * on the next vmentry.
 315          */
 316         if (!apic)
 317                 return 0;
 318         highest_irr = apic_find_highest_irr(apic);
 319
 320         return highest_irr;
 321 }
 322
 323 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 324                              int vector, int level, int trig_mode);
 325
 326 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq)
 327 {
 328         struct kvm_lapic *apic = vcpu->arch.apic;
 329
 330         return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
 331                         irq->level, irq->trig_mode);
 332 }
 333
 334 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
 335 {
 336
 337         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
 338                                       sizeof(val));
 339 }
 340
 341 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
 342 {
 343
 344         return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
 345                                       sizeof(*val));
 346 }
 347
 348 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
 349 {
 350         return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
 351 }
 352
 353 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
 354 {
 355         u8 val;
 356         if (pv_eoi_get_user(vcpu, &val) < 0)
 357                 apic_debug("Can't read EOI MSR value: 0x%llx\n",
 358                            (unsigned long long)vcpi->arch.pv_eoi.msr_val);
 359         return val & 0x1;
 360 }
 361
 362 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
 363 {
 364         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
 365                 apic_debug("Can't set EOI MSR value: 0x%llx\n",
 366                            (unsigned long long)vcpi->arch.pv_eoi.msr_val);
 367                 return;
 368         }
 369         __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 370 }
 371
 372 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
 373 {
 374         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
 375                 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
 376                            (unsigned long long)vcpi->arch.pv_eoi.msr_val);
 377                 return;
 378         }
 379         __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 380 }
 381
 382 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 383 {
 384         int result;
 385         if (!apic->isr_count)
 386                 return -1;
 387         if (likely(apic->highest_isr_cache != -1))
 388                 return apic->highest_isr_cache;
 389
 390         result = find_highest_vector(apic->regs + APIC_ISR);
 391         ASSERT(result == -1 || result >= 16);
 392
 393         return result;
 394 }
 395
 396 static void apic_update_ppr(struct kvm_lapic *apic)
 397 {
 398         u32 tpr, isrv, ppr, old_ppr;
 399         int isr;
 400
 401         old_ppr = apic_get_reg(apic, APIC_PROCPRI);
 402         tpr = apic_get_reg(apic, APIC_TASKPRI);
 403         isr = apic_find_highest_isr(apic);
 404         isrv = (isr != -1) ? isr : 0;
 405
 406         if ((tpr & 0xf0) >= (isrv & 0xf0))
 407                 ppr = tpr & 0xff;
 408         else
 409                 ppr = isrv & 0xf0;
 410
 411         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
 412                    apic, ppr, isr, isrv);
 413
 414         if (old_ppr != ppr) {
 415                 apic_set_reg(apic, APIC_PROCPRI, ppr);
 416                 if (ppr < old_ppr)
 417                         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 418         }
 419 }
 420
 421 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 422 {
 423         apic_set_reg(apic, APIC_TASKPRI, tpr);
 424         apic_update_ppr(apic);
 425 }
 426
 427 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
 428 {
 429         return dest == 0xff || kvm_apic_id(apic) == dest;
 430 }
 431
 432 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
 433 {
 434         int result = 0;
 435         u32 logical_id;
 436
 437         if (apic_x2apic_mode(apic)) {
 438                 logical_id = apic_get_reg(apic, APIC_LDR);
 439                 return logical_id & mda;
 440         }
 441
 442         logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
 443
 444         switch (apic_get_reg(apic, APIC_DFR)) {
 445         case APIC_DFR_FLAT:
 446                 if (logical_id & mda)
 447                         result = 1;
 448                 break;
 449         case APIC_DFR_CLUSTER:
 450                 if (((logical_id >> 4) == (mda >> 0x4))
 451                     && (logical_id & mda & 0xf))
 452                         result = 1;
 453                 break;
 454         default:
 455                 apic_debug("Bad DFR vcpu %d: %08x\n",
 456                            apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
 457                 break;
 458         }
 459
 460         return result;
 461 }
 462
 463 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 464                            int short_hand, int dest, int dest_mode)
 465 {
 466         int result = 0;
 467         struct kvm_lapic *target = vcpu->arch.apic;
 468
 469         apic_debug("target %p, source %p, dest 0x%x, "
 470                    "dest_mode 0x%x, short_hand 0x%x\n",
 471                    target, source, dest, dest_mode, short_hand);
 472
 473         ASSERT(target);
 474         switch (short_hand) {
 475         case APIC_DEST_NOSHORT:
 476                 if (dest_mode == 0)
 477                         /* Physical mode. */
 478                         result = kvm_apic_match_physical_addr(target, dest);
 479                 else
 480                         /* Logical mode. */
 481                         result = kvm_apic_match_logical_addr(target, dest);
 482                 break;
 483         case APIC_DEST_SELF:
 484                 result = (target == source);
 485                 break;
 486         case APIC_DEST_ALLINC:
 487                 result = 1;
 488                 break;
 489         case APIC_DEST_ALLBUT:
 490                 result = (target != source);
 491                 break;
 492         default:
 493                 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
 494                            short_hand);
 495                 break;
 496         }
 497
 498         return result;
 499 }
 500
 501 /*
 502  * Add a pending IRQ into lapic.
 503  * Return 1 if successfully added and 0 if discarded.
 504  */
 505 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 506                              int vector, int level, int trig_mode)
 507 {
 508         int result = 0;
 509         struct kvm_vcpu *vcpu = apic->vcpu;
 510
 511         switch (delivery_mode) {
 512         case APIC_DM_LOWEST:
 513                 vcpu->arch.apic_arb_prio++;
 514         case APIC_DM_FIXED:
 515                 /* FIXME add logic for vcpu on reset */
 516                 if (unlikely(!apic_enabled(apic)))
 517                         break;
 518
 519                 if (trig_mode) {
 520                         apic_debug("level trig mode for vector %d", vector);
 521                         apic_set_vector(vector, apic->regs + APIC_TMR);
 522                 } else
 523                         apic_clear_vector(vector, apic->regs + APIC_TMR);
 524
 525                 result = !apic_test_and_set_irr(vector, apic);
 526                 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
 527                                           trig_mode, vector, !result);
 528                 if (!result) {
 529                         if (trig_mode)
 530                                 apic_debug("level trig mode repeatedly for "
 531                                                 "vector %d", vector);
 532                         break;
 533                 }
 534
 535                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 536                 kvm_vcpu_kick(vcpu);
 537                 break;
 538
 539         case APIC_DM_REMRD:
 540                 apic_debug("Ignoring delivery mode 3\n");
 541                 break;
 542
 543         case APIC_DM_SMI:
 544                 apic_debug("Ignoring guest SMI\n");
 545                 break;
 546
 547         case APIC_DM_NMI:
 548                 result = 1;
 549                 kvm_inject_nmi(vcpu);
 550                 kvm_vcpu_kick(vcpu);
 551                 break;
 552
 553         case APIC_DM_INIT:
 554                 if (!trig_mode || level) {
 555                         result = 1;
 556                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
 557                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 558                         kvm_vcpu_kick(vcpu);
 559                 } else {
 560                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
 561                                    vcpu->vcpu_id);
 562                 }
 563                 break;
 564
 565         case APIC_DM_STARTUP:
 566                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
 567                            vcpu->vcpu_id, vector);
 568                 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
 569                         result = 1;
 570                         vcpu->arch.sipi_vector = vector;
 571                         vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
 572                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 573                         kvm_vcpu_kick(vcpu);
 574                 }
 575                 break;
 576
 577         case APIC_DM_EXTINT:
 578                 /*
 579                  * Should only be called by kvm_apic_local_deliver() with LVT0,
 580                  * before NMI watchdog was enabled. Already handled by
 581                  * kvm_apic_accept_pic_intr().
 582                  */
 583                 break;
 584
 585         default:
 586                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
 587                        delivery_mode);
 588                 break;
 589         }
 590         return result;
 591 }
 592
 593 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
 594 {
 595         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
 596 }
 597
 598 static int apic_set_eoi(struct kvm_lapic *apic)
 599 {
 600         int vector = apic_find_highest_isr(apic);
 601
 602         trace_kvm_eoi(apic, vector);
 603
 604         /*
 605          * Not every write EOI will has corresponding ISR,
 606          * one example is when Kernel check timer on setup_IO_APIC
 607          */
 608         if (vector == -1)
 609                 return vector;
 610
 611         apic_clear_isr(vector, apic);
 612         apic_update_ppr(apic);
 613
 614         if (!(apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) &&
 615             kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
 616                 int trigger_mode;
 617                 if (apic_test_vector(vector, apic->regs + APIC_TMR))
 618                         trigger_mode = IOAPIC_LEVEL_TRIG;
 619                 else
 620                         trigger_mode = IOAPIC_EDGE_TRIG;
 621                 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
 622         }
 623         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 624         return vector;
 625 }
 626
 627 static void apic_send_ipi(struct kvm_lapic *apic)
 628 {
 629         u32 icr_low = apic_get_reg(apic, APIC_ICR);
 630         u32 icr_high = apic_get_reg(apic, APIC_ICR2);
 631         struct kvm_lapic_irq irq;
 632
 633         irq.vector = icr_low & APIC_VECTOR_MASK;
 634         irq.delivery_mode = icr_low & APIC_MODE_MASK;
 635         irq.dest_mode = icr_low & APIC_DEST_MASK;
 636         irq.level = icr_low & APIC_INT_ASSERT;
 637         irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
 638         irq.shorthand = icr_low & APIC_SHORT_MASK;
 639         if (apic_x2apic_mode(apic))
 640                 irq.dest_id = icr_high;
 641         else
 642                 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
 643
 644         trace_kvm_apic_ipi(icr_low, irq.dest_id);
 645
 646         apic_debug("icr_high 0x%x, icr_low 0x%x, "
 647                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
 648                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
 649                    icr_high, icr_low, irq.shorthand, irq.dest_id,
 650                    irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
 651                    irq.vector);
 652
 653         kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq);
 654 }
 655
 656 static u32 apic_get_tmcct(struct kvm_lapic *apic)
 657 {
 658         ktime_t remaining;
 659         s64 ns;
 660         u32 tmcct;
 661
 662         ASSERT(apic != NULL);
 663
 664         /* if initial count is 0, current count should also be 0 */
 665         if (apic_get_reg(apic, APIC_TMICT) == 0)
 666                 return 0;
 667
 668         remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
 669         if (ktime_to_ns(remaining) < 0)
 670                 remaining = ktime_set(0, 0);
 671
 672         ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
 673         tmcct = div64_u64(ns,
 674                          (APIC_BUS_CYCLE_NS * apic->divide_count));
 675
 676         return tmcct;
 677 }
 678
 679 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
 680 {
 681         struct kvm_vcpu *vcpu = apic->vcpu;
 682         struct kvm_run *run = vcpu->run;
 683
 684         kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
 685         run->tpr_access.rip = kvm_rip_read(vcpu);
 686         run->tpr_access.is_write = write;
 687 }
 688
 689 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
 690 {
 691         if (apic->vcpu->arch.tpr_access_reporting)
 692                 __report_tpr_access(apic, write);
 693 }
 694
 695 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
 696 {
 697         u32 val = 0;
 698
 699         if (offset >= LAPIC_MMIO_LENGTH)
 700                 return 0;
 701
 702         switch (offset) {
 703         case APIC_ID:
 704                 if (apic_x2apic_mode(apic))
 705                         val = kvm_apic_id(apic);
 706                 else
 707                         val = kvm_apic_id(apic) << 24;
 708                 break;
 709         case APIC_ARBPRI:
 710                 apic_debug("Access APIC ARBPRI register which is for P6\n");
 711                 break;
 712
 713         case APIC_TMCCT:        /* Timer CCR */
 714                 if (apic_lvtt_tscdeadline(apic))
 715                         return 0;
 716
 717                 val = apic_get_tmcct(apic);
 718                 break;
 719         case APIC_PROCPRI:
 720                 apic_update_ppr(apic);
 721                 val = apic_get_reg(apic, offset);
 722                 break;
 723         case APIC_TASKPRI:
 724                 report_tpr_access(apic, false);
 725                 /* fall thru */
 726         default:
 727                 val = apic_get_reg(apic, offset);
 728                 break;
 729         }
 730
 731         return val;
 732 }
 733
 734 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
 735 {
 736         return container_of(dev, struct kvm_lapic, dev);
 737 }
 738
 739 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
 740                 void *data)
 741 {
 742         unsigned char alignment = offset & 0xf;
 743         u32 result;
 744         /* this bitmask has a bit cleared for each reserved register */
 745         static const u64 rmask = 0x43ff01ffffffe70cULL;
 746
 747         if ((alignment + len) > 4) {
 748                 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
 749                            offset, len);
 750                 return 1;
 751         }
 752
 753         if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
 754                 apic_debug("KVM_APIC_READ: read reserved register %x\n",
 755                            offset);
 756                 return 1;
 757         }
 758
 759         result = __apic_read(apic, offset & ~0xf);
 760
 761         trace_kvm_apic_read(offset, result);
 762
 763         switch (len) {
 764         case 1:
 765         case 2:
 766         case 4:
 767                 memcpy(data, (char *)&result + alignment, len);
 768                 break;
 769         default:
 770                 printk(KERN_ERR "Local APIC read with len = %x, "
 771                        "should be 1,2, or 4 instead\n", len);
 772                 break;
 773         }
 774         return 0;
 775 }
 776
 777 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
 778 {
 779         return apic_hw_enabled(apic) &&
 780             addr >= apic->base_address &&
 781             addr < apic->base_address + LAPIC_MMIO_LENGTH;
 782 }
 783
 784 static int apic_mmio_read(struct kvm_io_device *this,
 785                            gpa_t address, int len, void *data)
 786 {
 787         struct kvm_lapic *apic = to_lapic(this);
 788         u32 offset = address - apic->base_address;
 789
 790         if (!apic_mmio_in_range(apic, address))
 791                 return -EOPNOTSUPP;
 792
 793         apic_reg_read(apic, offset, len, data);
 794
 795         return 0;
 796 }
 797
 798 static void update_divide_count(struct kvm_lapic *apic)
 799 {
 800         u32 tmp1, tmp2, tdcr;
 801
 802         tdcr = apic_get_reg(apic, APIC_TDCR);
 803         tmp1 = tdcr & 0xf;
 804         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
 805         apic->divide_count = 0x1 << (tmp2 & 0x7);
 806
 807         apic_debug("timer divide count is 0x%x\n",
 808                                    apic->divide_count);
 809 }
 810
 811 static void start_apic_timer(struct kvm_lapic *apic)
 812 {
 813         ktime_t now;
 814         atomic_set(&apic->lapic_timer.pending, 0);
 815
 816         if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
 817                 /* lapic timer in oneshot or periodic mode */
 818                 now = apic->lapic_timer.timer.base->get_time();
 819                 apic->lapic_timer.period = (u64)apic_get_reg(apic, APIC_TMICT)
 820                             * APIC_BUS_CYCLE_NS * apic->divide_count;
 821
 822                 if (!apic->lapic_timer.period)
 823                         return;
 824                 /*
 825                  * Do not allow the guest to program periodic timers with small
 826                  * interval, since the hrtimers are not throttled by the host
 827                  * scheduler.
 828                  */
 829                 if (apic_lvtt_period(apic)) {
 830                         s64 min_period = min_timer_period_us * 1000LL;
 831
 832                         if (apic->lapic_timer.period < min_period) {
 833                                 pr_info_ratelimited(
 834                                     "kvm: vcpu %i: requested %lld ns "
 835                                     "lapic timer period limited to %lld ns\n",
 836                                     apic->vcpu->vcpu_id,
 837                                     apic->lapic_timer.period, min_period);
 838                                 apic->lapic_timer.period = min_period;
 839                         }
 840                 }
 841
 842                 hrtimer_start(&apic->lapic_timer.timer,
 843                               ktime_add_ns(now, apic->lapic_timer.period),
 844                               HRTIMER_MODE_ABS);
 845
 846                 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
 847                            PRIx64 ", "
 848                            "timer initial count 0x%x, period %lldns, "
 849                            "expire @ 0x%016" PRIx64 ".\n", __func__,
 850                            APIC_BUS_CYCLE_NS, ktime_to_ns(now),
 851                            apic_get_reg(apic, APIC_TMICT),
 852                            apic->lapic_timer.period,
 853                            ktime_to_ns(ktime_add_ns(now,
 854                                         apic->lapic_timer.period)));
 855         } else if (apic_lvtt_tscdeadline(apic)) {
 856                 /* lapic timer in tsc deadline mode */
 857                 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
 858                 u64 ns = 0;
 859                 struct kvm_vcpu *vcpu = apic->vcpu;
 860                 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
 861                 unsigned long flags;
 862
 863                 if (unlikely(!tscdeadline || !this_tsc_khz))
 864                         return;
 865
 866                 local_irq_save(flags);
 867
 868                 now = apic->lapic_timer.timer.base->get_time();
 869                 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
 870                 if (likely(tscdeadline > guest_tsc)) {
 871                         ns = (tscdeadline - guest_tsc) * 1000000ULL;
 872                         do_div(ns, this_tsc_khz);
 873                 }
 874                 hrtimer_start(&apic->lapic_timer.timer,
 875                         ktime_add_ns(now, ns), HRTIMER_MODE_ABS);
 876
 877                 local_irq_restore(flags);
 878         }
 879 }
 880
 881 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
 882 {
 883         int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0));
 884
 885         if (apic_lvt_nmi_mode(lvt0_val)) {
 886                 if (!nmi_wd_enabled) {
 887                         apic_debug("Receive NMI setting on APIC_LVT0 "
 888                                    "for cpu %d\n", apic->vcpu->vcpu_id);
 889                         apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
 890                 }
 891         } else if (nmi_wd_enabled)
 892                 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
 893 }
 894
 895 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
 896 {
 897         int ret = 0;
 898
 899         trace_kvm_apic_write(reg, val);
 900
 901         switch (reg) {
 902         case APIC_ID:           /* Local APIC ID */
 903                 if (!apic_x2apic_mode(apic))
 904                         apic_set_reg(apic, APIC_ID, val);
 905                 else
 906                         ret = 1;
 907                 break;
 908
 909         case APIC_TASKPRI:
 910                 report_tpr_access(apic, true);
 911                 apic_set_tpr(apic, val & 0xff);
 912                 break;
 913
 914         case APIC_EOI:
 915                 apic_set_eoi(apic);
 916                 break;
 917
 918         case APIC_LDR:
 919                 if (!apic_x2apic_mode(apic))
 920                         apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
 921                 else
 922                         ret = 1;
 923                 break;
 924
 925         case APIC_DFR:
 926                 if (!apic_x2apic_mode(apic))
 927                         apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
 928                 else
 929                         ret = 1;
 930                 break;
 931
 932         case APIC_SPIV: {
 933                 u32 mask = 0x3ff;
 934                 if (apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
 935                         mask |= APIC_SPIV_DIRECTED_EOI;
 936                 apic_set_spiv(apic, val & mask);
 937                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
 938                         int i;
 939                         u32 lvt_val;
 940
 941                         for (i = 0; i < APIC_LVT_NUM; i++) {
 942                                 lvt_val = apic_get_reg(apic,
 943                                                        APIC_LVTT + 0x10 * i);
 944                                 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
 945                                              lvt_val | APIC_LVT_MASKED);
 946                         }
 947                         atomic_set(&apic->lapic_timer.pending, 0);
 948
 949                 }
 950                 break;
 951         }
 952         case APIC_ICR:
 953                 /* No delay here, so we always clear the pending bit */
 954                 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
 955                 apic_send_ipi(apic);
 956                 break;
 957
 958         case APIC_ICR2:
 959                 if (!apic_x2apic_mode(apic))
 960                         val &= 0xff000000;
 961                 apic_set_reg(apic, APIC_ICR2, val);
 962                 break;
 963
 964         case APIC_LVT0:
 965                 apic_manage_nmi_watchdog(apic, val);
 966         case APIC_LVTTHMR:
 967         case APIC_LVTPC:
 968         case APIC_LVT1:
 969         case APIC_LVTERR:
 970                 /* TODO: Check vector */
 971                 if (!apic_sw_enabled(apic))
 972                         val |= APIC_LVT_MASKED;
 973
 974                 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
 975                 apic_set_reg(apic, reg, val);
 976
 977                 break;
 978
 979         case APIC_LVTT:
 980                 if ((apic_get_reg(apic, APIC_LVTT) &
 981                     apic->lapic_timer.timer_mode_mask) !=
 982                    (val & apic->lapic_timer.timer_mode_mask))
 983                         hrtimer_cancel(&apic->lapic_timer.timer);
 984
 985                 if (!apic_sw_enabled(apic))
 986                         val |= APIC_LVT_MASKED;
 987                 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
 988                 apic_set_reg(apic, APIC_LVTT, val);
 989                 break;
 990
 991         case APIC_TMICT:
 992                 if (apic_lvtt_tscdeadline(apic))
 993                         break;
 994
 995                 hrtimer_cancel(&apic->lapic_timer.timer);
 996                 apic_set_reg(apic, APIC_TMICT, val);
 997                 start_apic_timer(apic);
 998                 break;
 999
1000         case APIC_TDCR:
1001                 if (val & 4)
1002                         apic_debug("KVM_WRITE:TDCR %x\n", val);
1003                 apic_set_reg(apic, APIC_TDCR, val);
1004                 update_divide_count(apic);
1005                 break;
1006
1007         case APIC_ESR:
1008                 if (apic_x2apic_mode(apic) && val != 0) {
1009                         apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1010                         ret = 1;
1011                 }
1012                 break;
1013
1014         case APIC_SELF_IPI:
1015                 if (apic_x2apic_mode(apic)) {
1016                         apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1017                 } else
1018                         ret = 1;
1019                 break;
1020         default:
1021                 ret = 1;
1022                 break;
1023         }
1024         if (ret)
1025                 apic_debug("Local APIC Write to read-only register %x\n", reg);
1026         return ret;
1027 }
1028
1029 static int apic_mmio_write(struct kvm_io_device *this,
1030                             gpa_t address, int len, const void *data)
1031 {
1032         struct kvm_lapic *apic = to_lapic(this);
1033         unsigned int offset = address - apic->base_address;
1034         u32 val;
1035
1036         if (!apic_mmio_in_range(apic, address))
1037                 return -EOPNOTSUPP;
1038
1039         /*
1040          * APIC register must be aligned on 128-bits boundary.
1041          * 32/64/128 bits registers must be accessed thru 32 bits.
1042          * Refer SDM 8.4.1
1043          */
1044         if (len != 4 || (offset & 0xf)) {
1045                 /* Don't shout loud, $infamous_os would cause only noise. */
1046                 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1047                 return 0;
1048         }
1049
1050         val = *(u32*)data;
1051
1052         /* too common printing */
1053         if (offset != APIC_EOI)
1054                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1055                            "0x%x\n", __func__, offset, len, val);
1056
1057         apic_reg_write(apic, offset & 0xff0, val);
1058
1059         return 0;
1060 }
1061
1062 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1063 {
1064         struct kvm_lapic *apic = vcpu->arch.apic;
1065
1066         if (apic)
1067                 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1068 }
1069 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1070
1071 void kvm_free_lapic(struct kvm_vcpu *vcpu)
1072 {
1073         struct kvm_lapic *apic = vcpu->arch.apic;
1074
1075         if (!vcpu->arch.apic)
1076                 return;
1077
1078         hrtimer_cancel(&apic->lapic_timer.timer);
1079
1080         if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1081                 static_key_slow_dec_deferred(&apic_hw_disabled);
1082
1083         if (!(apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED))
1084                 static_key_slow_dec_deferred(&apic_sw_disabled);
1085
1086         if (apic->regs)
1087                 free_page((unsigned long)apic->regs);
1088
1089         kfree(apic);
1090 }
1091
1092 /*
1093  *----------------------------------------------------------------------
1094  * LAPIC interface
1095  *----------------------------------------------------------------------
1096  */
1097
1098 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1099 {
1100         struct kvm_lapic *apic = vcpu->arch.apic;
1101         if (!apic)
1102                 return 0;
1103
1104         if (apic_lvtt_oneshot(apic) || apic_lvtt_period(apic))
1105                 return 0;
1106
1107         return apic->lapic_timer.tscdeadline;
1108 }
1109
1110 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1111 {
1112         struct kvm_lapic *apic = vcpu->arch.apic;
1113         if (!apic)
1114                 return;
1115
1116         if (apic_lvtt_oneshot(apic) || apic_lvtt_period(apic))
1117                 return;
1118
1119         hrtimer_cancel(&apic->lapic_timer.timer);
1120         apic->lapic_timer.tscdeadline = data;
1121         start_apic_timer(apic);
1122 }
1123
1124 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1125 {
1126         struct kvm_lapic *apic = vcpu->arch.apic;
1127
1128         if (!apic)
1129                 return;
1130         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1131                      | (apic_get_reg(apic, APIC_TASKPRI) & 4));
1132 }
1133
1134 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1135 {
1136         struct kvm_lapic *apic = vcpu->arch.apic;
1137         u64 tpr;
1138
1139         if (!apic)
1140                 return 0;
1141         tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
1142
1143         return (tpr & 0xf0) >> 4;
1144 }
1145
1146 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1147 {
1148         struct kvm_lapic *apic = vcpu->arch.apic;
1149
1150         if (!apic) {
1151                 value |= MSR_IA32_APICBASE_BSP;
1152                 vcpu->arch.apic_base = value;
1153                 return;
1154         }
1155
1156         /* update jump label if enable bit changes */
1157         if ((vcpu->arch.apic_base ^ value) & MSR_IA32_APICBASE_ENABLE) {
1158                 if (value & MSR_IA32_APICBASE_ENABLE)
1159                         static_key_slow_dec_deferred(&apic_hw_disabled);
1160                 else
1161                         static_key_slow_inc(&apic_hw_disabled.key);
1162         }
1163
1164         if (!kvm_vcpu_is_bsp(apic->vcpu))
1165                 value &= ~MSR_IA32_APICBASE_BSP;
1166
1167         vcpu->arch.apic_base = value;
1168         if (apic_x2apic_mode(apic)) {
1169                 u32 id = kvm_apic_id(apic);
1170                 u32 ldr = ((id & ~0xf) << 16) | (1 << (id & 0xf));
1171                 apic_set_reg(apic, APIC_LDR, ldr);
1172         }
1173         apic->base_address = apic->vcpu->arch.apic_base &
1174                              MSR_IA32_APICBASE_BASE;
1175
1176         /* with FSB delivery interrupt, we can restart APIC functionality */
1177         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1178                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1179
1180 }
1181
1182 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
1183 {
1184         struct kvm_lapic *apic;
1185         int i;
1186
1187         apic_debug("%s\n", __func__);
1188
1189         ASSERT(vcpu);
1190         apic = vcpu->arch.apic;
1191         ASSERT(apic != NULL);
1192
1193         /* Stop the timer in case it's a reset to an active apic */
1194         hrtimer_cancel(&apic->lapic_timer.timer);
1195
1196         apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
1197         kvm_apic_set_version(apic->vcpu);
1198
1199         for (i = 0; i < APIC_LVT_NUM; i++)
1200                 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1201         apic_set_reg(apic, APIC_LVT0,
1202                      SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1203
1204         apic_set_reg(apic, APIC_DFR, 0xffffffffU);
1205         apic_set_spiv(apic, 0xff);
1206         apic_set_reg(apic, APIC_TASKPRI, 0);
1207         apic_set_reg(apic, APIC_LDR, 0);
1208         apic_set_reg(apic, APIC_ESR, 0);
1209         apic_set_reg(apic, APIC_ICR, 0);
1210         apic_set_reg(apic, APIC_ICR2, 0);
1211         apic_set_reg(apic, APIC_TDCR, 0);
1212         apic_set_reg(apic, APIC_TMICT, 0);
1213         for (i = 0; i < 8; i++) {
1214                 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1215                 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1216                 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1217         }
1218         apic->irr_pending = false;
1219         apic->isr_count = 0;
1220         apic->highest_isr_cache = -1;
1221         update_divide_count(apic);
1222         atomic_set(&apic->lapic_timer.pending, 0);
1223         if (kvm_vcpu_is_bsp(vcpu))
1224                 kvm_lapic_set_base(vcpu,
1225                                 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
1226         vcpu->arch.pv_eoi.msr_val = 0;
1227         apic_update_ppr(apic);
1228
1229         vcpu->arch.apic_arb_prio = 0;
1230         vcpu->arch.apic_attention = 0;
1231
1232         apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
1233                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1234                    vcpu, kvm_apic_id(apic),
1235                    vcpu->arch.apic_base, apic->base_address);
1236 }
1237
1238 bool kvm_apic_present(struct kvm_vcpu *vcpu)
1239 {
1240         return vcpu->arch.apic && apic_hw_enabled(vcpu->arch.apic);
1241 }
1242
1243 int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
1244 {
1245         return kvm_apic_present(vcpu) && apic_sw_enabled(vcpu->arch.apic);
1246 }
1247
1248 /*
1249  *----------------------------------------------------------------------
1250  * timer interface
1251  *----------------------------------------------------------------------
1252  */
1253
1254 static bool lapic_is_periodic(struct kvm_lapic *apic)
1255 {
1256         return apic_lvtt_period(apic);
1257 }
1258
1259 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1260 {
1261         struct kvm_lapic *lapic = vcpu->arch.apic;
1262
1263         if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
1264                 return atomic_read(&lapic->lapic_timer.pending);
1265
1266         return 0;
1267 }
1268
1269 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1270 {
1271         u32 reg = apic_get_reg(apic, lvt_type);
1272         int vector, mode, trig_mode;
1273
1274         if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1275                 vector = reg & APIC_VECTOR_MASK;
1276                 mode = reg & APIC_MODE_MASK;
1277                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1278                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode);
1279         }
1280         return 0;
1281 }
1282
1283 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1284 {
1285         struct kvm_lapic *apic = vcpu->arch.apic;
1286
1287         if (apic)
1288                 kvm_apic_local_deliver(apic, APIC_LVT0);
1289 }
1290
1291 static const struct kvm_io_device_ops apic_mmio_ops = {
1292         .read     = apic_mmio_read,
1293         .write    = apic_mmio_write,
1294 };
1295
1296 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1297 {
1298         struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
1299         struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
1300         struct kvm_vcpu *vcpu = apic->vcpu;
1301         wait_queue_head_t *q = &vcpu->wq;
1302
1303         /*
1304          * There is a race window between reading and incrementing, but we do
1305          * not care about potentially losing timer events in the !reinject
1306          * case anyway. Note: KVM_REQ_PENDING_TIMER is implicitly checked
1307          * in vcpu_enter_guest.
1308          */
1309         if (!atomic_read(&ktimer->pending)) {
1310                 atomic_inc(&ktimer->pending);
1311                 /* FIXME: this code should not know anything about vcpus */
1312                 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1313         }
1314
1315         if (waitqueue_active(q))
1316                 wake_up_interruptible(q);
1317
1318         if (lapic_is_periodic(apic)) {
1319                 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1320                 return HRTIMER_RESTART;
1321         } else
1322                 return HRTIMER_NORESTART;
1323 }
1324
1325 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1326 {
1327         struct kvm_lapic *apic;
1328
1329         ASSERT(vcpu != NULL);
1330         apic_debug("apic_init %d\n", vcpu->vcpu_id);
1331
1332         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1333         if (!apic)
1334                 goto nomem;
1335
1336         vcpu->arch.apic = apic;
1337
1338         apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1339         if (!apic->regs) {
1340                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1341                        vcpu->vcpu_id);
1342                 goto nomem_free_apic;
1343         }
1344         apic->vcpu = vcpu;
1345
1346         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1347                      HRTIMER_MODE_ABS);
1348         apic->lapic_timer.timer.function = apic_timer_fn;
1349
1350         /*
1351          * APIC is created enabled. This will prevent kvm_lapic_set_base from
1352          * thinking that APIC satet has changed.
1353          */
1354         vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
1355         kvm_lapic_set_base(vcpu,
1356                         APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
1357
1358         static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
1359         kvm_lapic_reset(vcpu);
1360         kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1361
1362         return 0;
1363 nomem_free_apic:
1364         kfree(apic);
1365 nomem:
1366         return -ENOMEM;
1367 }
1368
1369 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1370 {
1371         struct kvm_lapic *apic = vcpu->arch.apic;
1372         int highest_irr;
1373
1374         if (!apic || !apic_enabled(apic))
1375                 return -1;
1376
1377         apic_update_ppr(apic);
1378         highest_irr = apic_find_highest_irr(apic);
1379         if ((highest_irr == -1) ||
1380             ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
1381                 return -1;
1382         return highest_irr;
1383 }
1384
1385 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1386 {
1387         u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1388         int r = 0;
1389
1390         if (!apic_hw_enabled(vcpu->arch.apic))
1391                 r = 1;
1392         if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1393             GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1394                 r = 1;
1395         return r;
1396 }
1397
1398 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1399 {
1400         struct kvm_lapic *apic = vcpu->arch.apic;
1401
1402         if (apic && atomic_read(&apic->lapic_timer.pending) > 0) {
1403                 if (kvm_apic_local_deliver(apic, APIC_LVTT))
1404                         atomic_dec(&apic->lapic_timer.pending);
1405         }
1406 }
1407
1408 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1409 {
1410         int vector = kvm_apic_has_interrupt(vcpu);
1411         struct kvm_lapic *apic = vcpu->arch.apic;
1412
1413         if (vector == -1)
1414                 return -1;
1415
1416         apic_set_isr(vector, apic);
1417         apic_update_ppr(apic);
1418         apic_clear_irr(vector, apic);
1419         return vector;
1420 }
1421
1422 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1423 {
1424         struct kvm_lapic *apic = vcpu->arch.apic;
1425
1426         kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
1427         kvm_apic_set_version(vcpu);
1428         apic_set_spiv(apic, apic_get_reg(apic, APIC_SPIV));
1429
1430         apic_update_ppr(apic);
1431         hrtimer_cancel(&apic->lapic_timer.timer);
1432         update_divide_count(apic);
1433         start_apic_timer(apic);
1434         apic->irr_pending = true;
1435         apic->isr_count = count_vectors(apic->regs + APIC_ISR);
1436         apic->highest_isr_cache = -1;
1437         kvm_make_request(KVM_REQ_EVENT, vcpu);
1438 }
1439
1440 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1441 {
1442         struct kvm_lapic *apic = vcpu->arch.apic;
1443         struct hrtimer *timer;
1444
1445         if (!apic)
1446                 return;
1447
1448         timer = &apic->lapic_timer.timer;
1449         if (hrtimer_cancel(timer))
1450                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1451 }
1452
1453 /*
1454  * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1455  *
1456  * Detect whether guest triggered PV EOI since the
1457  * last entry. If yes, set EOI on guests's behalf.
1458  * Clear PV EOI in guest memory in any case.
1459  */
1460 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1461                                         struct kvm_lapic *apic)
1462 {
1463         bool pending;
1464         int vector;
1465         /*
1466          * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1467          * and KVM_PV_EOI_ENABLED in guest memory as follows:
1468          *
1469          * KVM_APIC_PV_EOI_PENDING is unset:
1470          *      -> host disabled PV EOI.
1471          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1472          *      -> host enabled PV EOI, guest did not execute EOI yet.
1473          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1474          *      -> host enabled PV EOI, guest executed EOI.
1475          */
1476         BUG_ON(!pv_eoi_enabled(vcpu));
1477         pending = pv_eoi_get_pending(vcpu);
1478         /*
1479          * Clear pending bit in any case: it will be set again on vmentry.
1480          * While this might not be ideal from performance point of view,
1481          * this makes sure pv eoi is only enabled when we know it's safe.
1482          */
1483         pv_eoi_clr_pending(vcpu);
1484         if (pending)
1485                 return;
1486         vector = apic_set_eoi(apic);
1487         trace_kvm_pv_eoi(apic, vector);
1488 }
1489
1490 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1491 {
1492         u32 data;
1493         void *vapic;
1494
1495         if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1496                 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1497
1498         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1499                 return;
1500
1501         vapic = kmap_atomic(vcpu->arch.apic->vapic_page);
1502         data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1503         kunmap_atomic(vapic);
1504
1505         apic_set_tpr(vcpu->arch.apic, data & 0xff);
1506 }
1507
1508 /*
1509  * apic_sync_pv_eoi_to_guest - called before vmentry
1510  *
1511  * Detect whether it's safe to enable PV EOI and
1512  * if yes do so.
1513  */
1514 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
1515                                         struct kvm_lapic *apic)
1516 {
1517         if (!pv_eoi_enabled(vcpu) ||
1518             /* IRR set or many bits in ISR: could be nested. */
1519             apic->irr_pending ||
1520             /* Cache not set: could be safe but we don't bother. */
1521             apic->highest_isr_cache == -1 ||
1522             /* Need EOI to update ioapic. */
1523             kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) {
1524                 /*
1525                  * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1526                  * so we need not do anything here.
1527                  */
1528                 return;
1529         }
1530
1531         pv_eoi_set_pending(apic->vcpu);
1532 }
1533
1534 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1535 {
1536         u32 data, tpr;
1537         int max_irr, max_isr;
1538         struct kvm_lapic *apic = vcpu->arch.apic;
1539         void *vapic;
1540
1541         apic_sync_pv_eoi_to_guest(vcpu, apic);
1542
1543         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1544                 return;
1545
1546         tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1547         max_irr = apic_find_highest_irr(apic);
1548         if (max_irr < 0)
1549                 max_irr = 0;
1550         max_isr = apic_find_highest_isr(apic);
1551         if (max_isr < 0)
1552                 max_isr = 0;
1553         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1554
1555         vapic = kmap_atomic(vcpu->arch.apic->vapic_page);
1556         *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1557         kunmap_atomic(vapic);
1558 }
1559
1560 void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1561 {
1562         vcpu->arch.apic->vapic_addr = vapic_addr;
1563         if (vapic_addr)
1564                 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1565         else
1566                 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1567 }
1568
1569 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1570 {
1571         struct kvm_lapic *apic = vcpu->arch.apic;
1572         u32 reg = (msr - APIC_BASE_MSR) << 4;
1573
1574         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1575                 return 1;
1576
1577         /* if this is ICR write vector before command */
1578         if (msr == 0x830)
1579                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1580         return apic_reg_write(apic, reg, (u32)data);
1581 }
1582
1583 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1584 {
1585         struct kvm_lapic *apic = vcpu->arch.apic;
1586         u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1587
1588         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1589                 return 1;
1590
1591         if (apic_reg_read(apic, reg, 4, &low))
1592                 return 1;
1593         if (msr == 0x830)
1594                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1595
1596         *data = (((u64)high) << 32) | low;
1597
1598         return 0;
1599 }
1600
1601 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1602 {
1603         struct kvm_lapic *apic = vcpu->arch.apic;
1604
1605         if (!irqchip_in_kernel(vcpu->kvm))
1606                 return 1;
1607
1608         /* if this is ICR write vector before command */
1609         if (reg == APIC_ICR)
1610                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1611         return apic_reg_write(apic, reg, (u32)data);
1612 }
1613
1614 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
1615 {
1616         struct kvm_lapic *apic = vcpu->arch.apic;
1617         u32 low, high = 0;
1618
1619         if (!irqchip_in_kernel(vcpu->kvm))
1620                 return 1;
1621
1622         if (apic_reg_read(apic, reg, 4, &low))
1623                 return 1;
1624         if (reg == APIC_ICR)
1625                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1626
1627         *data = (((u64)high) << 32) | low;
1628
1629         return 0;
1630 }
1631
1632 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
1633 {
1634         u64 addr = data & ~KVM_MSR_ENABLED;
1635         if (!IS_ALIGNED(addr, 4))
1636                 return 1;
1637
1638         vcpu->arch.pv_eoi.msr_val = data;
1639         if (!pv_eoi_enabled(vcpu))
1640                 return 0;
1641         return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
1642                                          addr);
1643 }
1644
1645 void kvm_lapic_init(void)
1646 {
1647         /* do not patch jump label more than once per second */
1648         jump_label_rate_limit(&apic_hw_disabled, HZ);
1649         jump_label_rate_limit(&apic_sw_disabled, HZ);
1650 }