1 // SPDX-License-Identifier: GPL-2.0-only
4 * Local APIC virtualization
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2007 Novell
8 * Copyright (C) 2007 Intel
9 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
12 * Dor Laor <dor.laor@qumranet.com>
13 * Gregory Haskins <ghaskins@novell.com>
14 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
16 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
19 #include <linux/kvm_host.h>
20 #include <linux/kvm.h>
22 #include <linux/highmem.h>
23 #include <linux/smp.h>
24 #include <linux/hrtimer.h>
26 #include <linux/export.h>
27 #include <linux/math64.h>
28 #include <linux/slab.h>
29 #include <asm/processor.h>
32 #include <asm/current.h>
33 #include <asm/apicdef.h>
34 #include <asm/delay.h>
35 #include <linux/atomic.h>
36 #include <linux/jump_label.h>
37 #include "kvm_cache_regs.h"
45 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
47 #define mod_64(x, y) ((x) % (y))
55 /* 14 is the version for Xeon and Pentium 8.4.8*/
56 #define APIC_VERSION (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16))
57 #define LAPIC_MMIO_LENGTH (1 << 12)
58 /* followed define is not in apicdef.h */
59 #define MAX_APIC_VECTOR 256
60 #define APIC_VECTORS_PER_REG 32
62 #define APIC_BROADCAST 0xFF
63 #define X2APIC_BROADCAST 0xFFFFFFFFul
65 static bool lapic_timer_advance_dynamic __read_mostly;
66 #define LAPIC_TIMER_ADVANCE_ADJUST_MIN 100 /* clock cycles */
67 #define LAPIC_TIMER_ADVANCE_ADJUST_MAX 10000 /* clock cycles */
68 #define LAPIC_TIMER_ADVANCE_NS_INIT 1000
69 #define LAPIC_TIMER_ADVANCE_NS_MAX 5000
70 /* step-by-step approximation to mitigate fluctuation */
71 #define LAPIC_TIMER_ADVANCE_ADJUST_STEP 8
73 static inline int apic_test_vector(int vec, void *bitmap)
75 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
78 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
80 struct kvm_lapic *apic = vcpu->arch.apic;
82 return apic_test_vector(vector, apic->regs + APIC_ISR) ||
83 apic_test_vector(vector, apic->regs + APIC_IRR);
86 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
88 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
91 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
93 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
96 struct static_key_deferred apic_hw_disabled __read_mostly;
97 struct static_key_deferred apic_sw_disabled __read_mostly;
99 static inline int apic_enabled(struct kvm_lapic *apic)
101 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
105 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
108 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
109 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
111 static inline u32 kvm_x2apic_id(struct kvm_lapic *apic)
113 return apic->vcpu->vcpu_id;
116 bool kvm_can_post_timer_interrupt(struct kvm_vcpu *vcpu)
118 return pi_inject_timer && kvm_vcpu_apicv_active(vcpu);
120 EXPORT_SYMBOL_GPL(kvm_can_post_timer_interrupt);
122 static bool kvm_use_posted_timer_interrupt(struct kvm_vcpu *vcpu)
124 return kvm_can_post_timer_interrupt(vcpu) && vcpu->mode == IN_GUEST_MODE;
127 static inline bool kvm_apic_map_get_logical_dest(struct kvm_apic_map *map,
128 u32 dest_id, struct kvm_lapic ***cluster, u16 *mask) {
130 case KVM_APIC_MODE_X2APIC: {
131 u32 offset = (dest_id >> 16) * 16;
132 u32 max_apic_id = map->max_apic_id;
134 if (offset <= max_apic_id) {
135 u8 cluster_size = min(max_apic_id - offset + 1, 16U);
137 offset = array_index_nospec(offset, map->max_apic_id + 1);
138 *cluster = &map->phys_map[offset];
139 *mask = dest_id & (0xffff >> (16 - cluster_size));
146 case KVM_APIC_MODE_XAPIC_FLAT:
147 *cluster = map->xapic_flat_map;
148 *mask = dest_id & 0xff;
150 case KVM_APIC_MODE_XAPIC_CLUSTER:
151 *cluster = map->xapic_cluster_map[(dest_id >> 4) & 0xf];
152 *mask = dest_id & 0xf;
160 static void kvm_apic_map_free(struct rcu_head *rcu)
162 struct kvm_apic_map *map = container_of(rcu, struct kvm_apic_map, rcu);
167 static void recalculate_apic_map(struct kvm *kvm)
169 struct kvm_apic_map *new, *old = NULL;
170 struct kvm_vcpu *vcpu;
172 u32 max_id = 255; /* enough space for any xAPIC ID */
174 mutex_lock(&kvm->arch.apic_map_lock);
176 kvm_for_each_vcpu(i, vcpu, kvm)
177 if (kvm_apic_present(vcpu))
178 max_id = max(max_id, kvm_x2apic_id(vcpu->arch.apic));
180 new = kvzalloc(sizeof(struct kvm_apic_map) +
181 sizeof(struct kvm_lapic *) * ((u64)max_id + 1),
187 new->max_apic_id = max_id;
189 kvm_for_each_vcpu(i, vcpu, kvm) {
190 struct kvm_lapic *apic = vcpu->arch.apic;
191 struct kvm_lapic **cluster;
197 if (!kvm_apic_present(vcpu))
200 xapic_id = kvm_xapic_id(apic);
201 x2apic_id = kvm_x2apic_id(apic);
203 /* Hotplug hack: see kvm_apic_match_physical_addr(), ... */
204 if ((apic_x2apic_mode(apic) || x2apic_id > 0xff) &&
205 x2apic_id <= new->max_apic_id)
206 new->phys_map[x2apic_id] = apic;
208 * ... xAPIC ID of VCPUs with APIC ID > 0xff will wrap-around,
209 * prevent them from masking VCPUs with APIC ID <= 0xff.
211 if (!apic_x2apic_mode(apic) && !new->phys_map[xapic_id])
212 new->phys_map[xapic_id] = apic;
214 if (!kvm_apic_sw_enabled(apic))
217 ldr = kvm_lapic_get_reg(apic, APIC_LDR);
219 if (apic_x2apic_mode(apic)) {
220 new->mode |= KVM_APIC_MODE_X2APIC;
222 ldr = GET_APIC_LOGICAL_ID(ldr);
223 if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
224 new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
226 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
229 if (!kvm_apic_map_get_logical_dest(new, ldr, &cluster, &mask))
233 cluster[ffs(mask) - 1] = apic;
236 old = rcu_dereference_protected(kvm->arch.apic_map,
237 lockdep_is_held(&kvm->arch.apic_map_lock));
238 rcu_assign_pointer(kvm->arch.apic_map, new);
239 mutex_unlock(&kvm->arch.apic_map_lock);
242 call_rcu(&old->rcu, kvm_apic_map_free);
244 kvm_make_scan_ioapic_request(kvm);
247 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
249 bool enabled = val & APIC_SPIV_APIC_ENABLED;
251 kvm_lapic_set_reg(apic, APIC_SPIV, val);
253 if (enabled != apic->sw_enabled) {
254 apic->sw_enabled = enabled;
256 static_key_slow_dec_deferred(&apic_sw_disabled);
258 static_key_slow_inc(&apic_sw_disabled.key);
260 recalculate_apic_map(apic->vcpu->kvm);
264 static inline void kvm_apic_set_xapic_id(struct kvm_lapic *apic, u8 id)
266 kvm_lapic_set_reg(apic, APIC_ID, id << 24);
267 recalculate_apic_map(apic->vcpu->kvm);
270 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
272 kvm_lapic_set_reg(apic, APIC_LDR, id);
273 recalculate_apic_map(apic->vcpu->kvm);
276 static inline u32 kvm_apic_calc_x2apic_ldr(u32 id)
278 return ((id >> 4) << 16) | (1 << (id & 0xf));
281 static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u32 id)
283 u32 ldr = kvm_apic_calc_x2apic_ldr(id);
285 WARN_ON_ONCE(id != apic->vcpu->vcpu_id);
287 kvm_lapic_set_reg(apic, APIC_ID, id);
288 kvm_lapic_set_reg(apic, APIC_LDR, ldr);
289 recalculate_apic_map(apic->vcpu->kvm);
292 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
294 return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
297 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
299 return kvm_lapic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
302 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
304 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
307 static inline int apic_lvtt_period(struct kvm_lapic *apic)
309 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
312 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
314 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
317 static inline int apic_lvt_nmi_mode(u32 lvt_val)
319 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
322 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
324 struct kvm_lapic *apic = vcpu->arch.apic;
325 struct kvm_cpuid_entry2 *feat;
326 u32 v = APIC_VERSION;
328 if (!lapic_in_kernel(vcpu))
332 * KVM emulates 82093AA datasheet (with in-kernel IOAPIC implementation)
333 * which doesn't have EOI register; Some buggy OSes (e.g. Windows with
334 * Hyper-V role) disable EOI broadcast in lapic not checking for IOAPIC
335 * version first and level-triggered interrupts never get EOIed in
338 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
339 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))) &&
340 !ioapic_in_kernel(vcpu->kvm))
341 v |= APIC_LVR_DIRECTED_EOI;
342 kvm_lapic_set_reg(apic, APIC_LVR, v);
345 static const unsigned int apic_lvt_mask[KVM_APIC_LVT_NUM] = {
346 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
347 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
348 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
349 LINT_MASK, LINT_MASK, /* LVT0-1 */
350 LVT_MASK /* LVTERR */
353 static int find_highest_vector(void *bitmap)
358 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
359 vec >= 0; vec -= APIC_VECTORS_PER_REG) {
360 reg = bitmap + REG_POS(vec);
362 return __fls(*reg) + vec;
368 static u8 count_vectors(void *bitmap)
374 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
375 reg = bitmap + REG_POS(vec);
376 count += hweight32(*reg);
382 bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr)
385 u32 pir_val, irr_val, prev_irr_val;
388 max_updated_irr = -1;
391 for (i = vec = 0; i <= 7; i++, vec += 32) {
392 pir_val = READ_ONCE(pir[i]);
393 irr_val = *((u32 *)(regs + APIC_IRR + i * 0x10));
395 prev_irr_val = irr_val;
396 irr_val |= xchg(&pir[i], 0);
397 *((u32 *)(regs + APIC_IRR + i * 0x10)) = irr_val;
398 if (prev_irr_val != irr_val) {
400 __fls(irr_val ^ prev_irr_val) + vec;
404 *max_irr = __fls(irr_val) + vec;
407 return ((max_updated_irr != -1) &&
408 (max_updated_irr == *max_irr));
410 EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
412 bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr)
414 struct kvm_lapic *apic = vcpu->arch.apic;
416 return __kvm_apic_update_irr(pir, apic->regs, max_irr);
418 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
420 static inline int apic_search_irr(struct kvm_lapic *apic)
422 return find_highest_vector(apic->regs + APIC_IRR);
425 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
430 * Note that irr_pending is just a hint. It will be always
431 * true with virtual interrupt delivery enabled.
433 if (!apic->irr_pending)
436 result = apic_search_irr(apic);
437 ASSERT(result == -1 || result >= 16);
442 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
444 struct kvm_vcpu *vcpu;
448 if (unlikely(vcpu->arch.apicv_active)) {
449 /* need to update RVI */
450 kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR);
451 kvm_x86_ops->hwapic_irr_update(vcpu,
452 apic_find_highest_irr(apic));
454 apic->irr_pending = false;
455 kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR);
456 if (apic_search_irr(apic) != -1)
457 apic->irr_pending = true;
461 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
463 struct kvm_vcpu *vcpu;
465 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
471 * With APIC virtualization enabled, all caching is disabled
472 * because the processor can modify ISR under the hood. Instead
475 if (unlikely(vcpu->arch.apicv_active))
476 kvm_x86_ops->hwapic_isr_update(vcpu, vec);
479 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
481 * ISR (in service register) bit is set when injecting an interrupt.
482 * The highest vector is injected. Thus the latest bit set matches
483 * the highest bit in ISR.
485 apic->highest_isr_cache = vec;
489 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
494 * Note that isr_count is always 1, and highest_isr_cache
495 * is always -1, with APIC virtualization enabled.
497 if (!apic->isr_count)
499 if (likely(apic->highest_isr_cache != -1))
500 return apic->highest_isr_cache;
502 result = find_highest_vector(apic->regs + APIC_ISR);
503 ASSERT(result == -1 || result >= 16);
508 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
510 struct kvm_vcpu *vcpu;
511 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
517 * We do get here for APIC virtualization enabled if the guest
518 * uses the Hyper-V APIC enlightenment. In this case we may need
519 * to trigger a new interrupt delivery by writing the SVI field;
520 * on the other hand isr_count and highest_isr_cache are unused
521 * and must be left alone.
523 if (unlikely(vcpu->arch.apicv_active))
524 kvm_x86_ops->hwapic_isr_update(vcpu,
525 apic_find_highest_isr(apic));
528 BUG_ON(apic->isr_count < 0);
529 apic->highest_isr_cache = -1;
533 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
535 /* This may race with setting of irr in __apic_accept_irq() and
536 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
537 * will cause vmexit immediately and the value will be recalculated
538 * on the next vmentry.
540 return apic_find_highest_irr(vcpu->arch.apic);
542 EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
544 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
545 int vector, int level, int trig_mode,
546 struct dest_map *dest_map);
548 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
549 struct dest_map *dest_map)
551 struct kvm_lapic *apic = vcpu->arch.apic;
553 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
554 irq->level, irq->trig_mode, dest_map);
557 static int __pv_send_ipi(unsigned long *ipi_bitmap, struct kvm_apic_map *map,
558 struct kvm_lapic_irq *irq, u32 min)
561 struct kvm_vcpu *vcpu;
563 if (min > map->max_apic_id)
566 for_each_set_bit(i, ipi_bitmap,
567 min((u32)BITS_PER_LONG, (map->max_apic_id - min + 1))) {
568 if (map->phys_map[min + i]) {
569 vcpu = map->phys_map[min + i]->vcpu;
570 count += kvm_apic_set_irq(vcpu, irq, NULL);
577 int kvm_pv_send_ipi(struct kvm *kvm, unsigned long ipi_bitmap_low,
578 unsigned long ipi_bitmap_high, u32 min,
579 unsigned long icr, int op_64_bit)
581 struct kvm_apic_map *map;
582 struct kvm_lapic_irq irq = {0};
583 int cluster_size = op_64_bit ? 64 : 32;
586 if (icr & (APIC_DEST_MASK | APIC_SHORT_MASK))
589 irq.vector = icr & APIC_VECTOR_MASK;
590 irq.delivery_mode = icr & APIC_MODE_MASK;
591 irq.level = (icr & APIC_INT_ASSERT) != 0;
592 irq.trig_mode = icr & APIC_INT_LEVELTRIG;
595 map = rcu_dereference(kvm->arch.apic_map);
599 count = __pv_send_ipi(&ipi_bitmap_low, map, &irq, min);
601 count += __pv_send_ipi(&ipi_bitmap_high, map, &irq, min);
608 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
611 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
615 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
618 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
622 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
624 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
627 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
630 if (pv_eoi_get_user(vcpu, &val) < 0)
631 printk(KERN_WARNING "Can't read EOI MSR value: 0x%llx\n",
632 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
636 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
638 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
639 printk(KERN_WARNING "Can't set EOI MSR value: 0x%llx\n",
640 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
643 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
646 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
648 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
649 printk(KERN_WARNING "Can't clear EOI MSR value: 0x%llx\n",
650 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
653 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
656 static int apic_has_interrupt_for_ppr(struct kvm_lapic *apic, u32 ppr)
659 if (apic->vcpu->arch.apicv_active)
660 highest_irr = kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
662 highest_irr = apic_find_highest_irr(apic);
663 if (highest_irr == -1 || (highest_irr & 0xF0) <= ppr)
668 static bool __apic_update_ppr(struct kvm_lapic *apic, u32 *new_ppr)
670 u32 tpr, isrv, ppr, old_ppr;
673 old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI);
674 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI);
675 isr = apic_find_highest_isr(apic);
676 isrv = (isr != -1) ? isr : 0;
678 if ((tpr & 0xf0) >= (isrv & 0xf0))
685 kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr);
687 return ppr < old_ppr;
690 static void apic_update_ppr(struct kvm_lapic *apic)
694 if (__apic_update_ppr(apic, &ppr) &&
695 apic_has_interrupt_for_ppr(apic, ppr) != -1)
696 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
699 void kvm_apic_update_ppr(struct kvm_vcpu *vcpu)
701 apic_update_ppr(vcpu->arch.apic);
703 EXPORT_SYMBOL_GPL(kvm_apic_update_ppr);
705 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
707 kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr);
708 apic_update_ppr(apic);
711 static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
713 return mda == (apic_x2apic_mode(apic) ?
714 X2APIC_BROADCAST : APIC_BROADCAST);
717 static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
719 if (kvm_apic_broadcast(apic, mda))
722 if (apic_x2apic_mode(apic))
723 return mda == kvm_x2apic_id(apic);
726 * Hotplug hack: Make LAPIC in xAPIC mode also accept interrupts as if
727 * it were in x2APIC mode. Hotplugged VCPUs start in xAPIC mode and
728 * this allows unique addressing of VCPUs with APIC ID over 0xff.
729 * The 0xff condition is needed because writeable xAPIC ID.
731 if (kvm_x2apic_id(apic) > 0xff && mda == kvm_x2apic_id(apic))
734 return mda == kvm_xapic_id(apic);
737 static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
741 if (kvm_apic_broadcast(apic, mda))
744 logical_id = kvm_lapic_get_reg(apic, APIC_LDR);
746 if (apic_x2apic_mode(apic))
747 return ((logical_id >> 16) == (mda >> 16))
748 && (logical_id & mda & 0xffff) != 0;
750 logical_id = GET_APIC_LOGICAL_ID(logical_id);
752 switch (kvm_lapic_get_reg(apic, APIC_DFR)) {
754 return (logical_id & mda) != 0;
755 case APIC_DFR_CLUSTER:
756 return ((logical_id >> 4) == (mda >> 4))
757 && (logical_id & mda & 0xf) != 0;
763 /* The KVM local APIC implementation has two quirks:
765 * - Real hardware delivers interrupts destined to x2APIC ID > 0xff to LAPICs
766 * in xAPIC mode if the "destination & 0xff" matches its xAPIC ID.
767 * KVM doesn't do that aliasing.
769 * - in-kernel IOAPIC messages have to be delivered directly to
770 * x2APIC, because the kernel does not support interrupt remapping.
771 * In order to support broadcast without interrupt remapping, x2APIC
772 * rewrites the destination of non-IPI messages from APIC_BROADCAST
773 * to X2APIC_BROADCAST.
775 * The broadcast quirk can be disabled with KVM_CAP_X2APIC_API. This is
776 * important when userspace wants to use x2APIC-format MSIs, because
777 * APIC_BROADCAST (0xff) is a legal route for "cluster 0, CPUs 0-7".
779 static u32 kvm_apic_mda(struct kvm_vcpu *vcpu, unsigned int dest_id,
780 struct kvm_lapic *source, struct kvm_lapic *target)
782 bool ipi = source != NULL;
784 if (!vcpu->kvm->arch.x2apic_broadcast_quirk_disabled &&
785 !ipi && dest_id == APIC_BROADCAST && apic_x2apic_mode(target))
786 return X2APIC_BROADCAST;
791 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
792 int shorthand, unsigned int dest, int dest_mode)
794 struct kvm_lapic *target = vcpu->arch.apic;
795 u32 mda = kvm_apic_mda(vcpu, dest, source, target);
799 case APIC_DEST_NOSHORT:
800 if (dest_mode == APIC_DEST_PHYSICAL)
801 return kvm_apic_match_physical_addr(target, mda);
803 return kvm_apic_match_logical_addr(target, mda);
805 return target == source;
806 case APIC_DEST_ALLINC:
808 case APIC_DEST_ALLBUT:
809 return target != source;
814 EXPORT_SYMBOL_GPL(kvm_apic_match_dest);
816 int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
817 const unsigned long *bitmap, u32 bitmap_size)
822 mod = vector % dest_vcpus;
824 for (i = 0; i <= mod; i++) {
825 idx = find_next_bit(bitmap, bitmap_size, idx + 1);
826 BUG_ON(idx == bitmap_size);
832 static void kvm_apic_disabled_lapic_found(struct kvm *kvm)
834 if (!kvm->arch.disabled_lapic_found) {
835 kvm->arch.disabled_lapic_found = true;
837 "Disabled LAPIC found during irq injection\n");
841 static bool kvm_apic_is_broadcast_dest(struct kvm *kvm, struct kvm_lapic **src,
842 struct kvm_lapic_irq *irq, struct kvm_apic_map *map)
844 if (kvm->arch.x2apic_broadcast_quirk_disabled) {
845 if ((irq->dest_id == APIC_BROADCAST &&
846 map->mode != KVM_APIC_MODE_X2APIC))
848 if (irq->dest_id == X2APIC_BROADCAST)
851 bool x2apic_ipi = src && *src && apic_x2apic_mode(*src);
852 if (irq->dest_id == (x2apic_ipi ?
853 X2APIC_BROADCAST : APIC_BROADCAST))
860 /* Return true if the interrupt can be handled by using *bitmap as index mask
861 * for valid destinations in *dst array.
862 * Return false if kvm_apic_map_get_dest_lapic did nothing useful.
863 * Note: we may have zero kvm_lapic destinations when we return true, which
864 * means that the interrupt should be dropped. In this case, *bitmap would be
865 * zero and *dst undefined.
867 static inline bool kvm_apic_map_get_dest_lapic(struct kvm *kvm,
868 struct kvm_lapic **src, struct kvm_lapic_irq *irq,
869 struct kvm_apic_map *map, struct kvm_lapic ***dst,
870 unsigned long *bitmap)
874 if (irq->shorthand == APIC_DEST_SELF && src) {
878 } else if (irq->shorthand)
881 if (!map || kvm_apic_is_broadcast_dest(kvm, src, irq, map))
884 if (irq->dest_mode == APIC_DEST_PHYSICAL) {
885 if (irq->dest_id > map->max_apic_id) {
888 u32 dest_id = array_index_nospec(irq->dest_id, map->max_apic_id + 1);
889 *dst = &map->phys_map[dest_id];
896 if (!kvm_apic_map_get_logical_dest(map, irq->dest_id, dst,
900 if (!kvm_lowest_prio_delivery(irq))
903 if (!kvm_vector_hashing_enabled()) {
905 for_each_set_bit(i, bitmap, 16) {
910 else if (kvm_apic_compare_prio((*dst)[i]->vcpu,
911 (*dst)[lowest]->vcpu) < 0)
918 lowest = kvm_vector_to_index(irq->vector, hweight16(*bitmap),
921 if (!(*dst)[lowest]) {
922 kvm_apic_disabled_lapic_found(kvm);
928 *bitmap = (lowest >= 0) ? 1 << lowest : 0;
933 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
934 struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map)
936 struct kvm_apic_map *map;
937 unsigned long bitmap;
938 struct kvm_lapic **dst = NULL;
944 if (irq->shorthand == APIC_DEST_SELF) {
945 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
950 map = rcu_dereference(kvm->arch.apic_map);
952 ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dst, &bitmap);
955 for_each_set_bit(i, &bitmap, 16) {
958 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
967 * This routine tries to handler interrupts in posted mode, here is how
968 * it deals with different cases:
969 * - For single-destination interrupts, handle it in posted mode
970 * - Else if vector hashing is enabled and it is a lowest-priority
971 * interrupt, handle it in posted mode and use the following mechanism
972 * to find the destinaiton vCPU.
973 * 1. For lowest-priority interrupts, store all the possible
974 * destination vCPUs in an array.
975 * 2. Use "guest vector % max number of destination vCPUs" to find
976 * the right destination vCPU in the array for the lowest-priority
978 * - Otherwise, use remapped mode to inject the interrupt.
980 bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
981 struct kvm_vcpu **dest_vcpu)
983 struct kvm_apic_map *map;
984 unsigned long bitmap;
985 struct kvm_lapic **dst = NULL;
992 map = rcu_dereference(kvm->arch.apic_map);
994 if (kvm_apic_map_get_dest_lapic(kvm, NULL, irq, map, &dst, &bitmap) &&
995 hweight16(bitmap) == 1) {
996 unsigned long i = find_first_bit(&bitmap, 16);
999 *dest_vcpu = dst[i]->vcpu;
1009 * Add a pending IRQ into lapic.
1010 * Return 1 if successfully added and 0 if discarded.
1012 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
1013 int vector, int level, int trig_mode,
1014 struct dest_map *dest_map)
1017 struct kvm_vcpu *vcpu = apic->vcpu;
1019 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
1021 switch (delivery_mode) {
1022 case APIC_DM_LOWEST:
1023 vcpu->arch.apic_arb_prio++;
1026 if (unlikely(trig_mode && !level))
1029 /* FIXME add logic for vcpu on reset */
1030 if (unlikely(!apic_enabled(apic)))
1036 __set_bit(vcpu->vcpu_id, dest_map->map);
1037 dest_map->vectors[vcpu->vcpu_id] = vector;
1040 if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) {
1042 kvm_lapic_set_vector(vector,
1043 apic->regs + APIC_TMR);
1045 kvm_lapic_clear_vector(vector,
1046 apic->regs + APIC_TMR);
1049 if (vcpu->arch.apicv_active)
1050 kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
1052 kvm_lapic_set_irr(vector, apic);
1054 kvm_make_request(KVM_REQ_EVENT, vcpu);
1055 kvm_vcpu_kick(vcpu);
1061 vcpu->arch.pv.pv_unhalted = 1;
1062 kvm_make_request(KVM_REQ_EVENT, vcpu);
1063 kvm_vcpu_kick(vcpu);
1068 kvm_make_request(KVM_REQ_SMI, vcpu);
1069 kvm_vcpu_kick(vcpu);
1074 kvm_inject_nmi(vcpu);
1075 kvm_vcpu_kick(vcpu);
1079 if (!trig_mode || level) {
1081 /* assumes that there are only KVM_APIC_INIT/SIPI */
1082 apic->pending_events = (1UL << KVM_APIC_INIT);
1083 /* make sure pending_events is visible before sending
1086 kvm_make_request(KVM_REQ_EVENT, vcpu);
1087 kvm_vcpu_kick(vcpu);
1091 case APIC_DM_STARTUP:
1093 apic->sipi_vector = vector;
1094 /* make sure sipi_vector is visible for the receiver */
1096 set_bit(KVM_APIC_SIPI, &apic->pending_events);
1097 kvm_make_request(KVM_REQ_EVENT, vcpu);
1098 kvm_vcpu_kick(vcpu);
1101 case APIC_DM_EXTINT:
1103 * Should only be called by kvm_apic_local_deliver() with LVT0,
1104 * before NMI watchdog was enabled. Already handled by
1105 * kvm_apic_accept_pic_intr().
1110 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
1118 * This routine identifies the destination vcpus mask meant to receive the
1119 * IOAPIC interrupts. It either uses kvm_apic_map_get_dest_lapic() to find
1120 * out the destination vcpus array and set the bitmap or it traverses to
1121 * each available vcpu to identify the same.
1123 void kvm_bitmap_or_dest_vcpus(struct kvm *kvm, struct kvm_lapic_irq *irq,
1124 unsigned long *vcpu_bitmap)
1126 struct kvm_lapic **dest_vcpu = NULL;
1127 struct kvm_lapic *src = NULL;
1128 struct kvm_apic_map *map;
1129 struct kvm_vcpu *vcpu;
1130 unsigned long bitmap;
1135 map = rcu_dereference(kvm->arch.apic_map);
1137 ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dest_vcpu,
1140 for_each_set_bit(i, &bitmap, 16) {
1143 vcpu_idx = dest_vcpu[i]->vcpu->vcpu_idx;
1144 __set_bit(vcpu_idx, vcpu_bitmap);
1147 kvm_for_each_vcpu(i, vcpu, kvm) {
1148 if (!kvm_apic_present(vcpu))
1150 if (!kvm_apic_match_dest(vcpu, NULL,
1155 __set_bit(i, vcpu_bitmap);
1161 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
1163 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
1166 static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector)
1168 return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors);
1171 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
1175 /* Eoi the ioapic only if the ioapic doesn't own the vector. */
1176 if (!kvm_ioapic_handles_vector(apic, vector))
1179 /* Request a KVM exit to inform the userspace IOAPIC. */
1180 if (irqchip_split(apic->vcpu->kvm)) {
1181 apic->vcpu->arch.pending_ioapic_eoi = vector;
1182 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu);
1186 if (apic_test_vector(vector, apic->regs + APIC_TMR))
1187 trigger_mode = IOAPIC_LEVEL_TRIG;
1189 trigger_mode = IOAPIC_EDGE_TRIG;
1191 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
1194 static int apic_set_eoi(struct kvm_lapic *apic)
1196 int vector = apic_find_highest_isr(apic);
1198 trace_kvm_eoi(apic, vector);
1201 * Not every write EOI will has corresponding ISR,
1202 * one example is when Kernel check timer on setup_IO_APIC
1207 apic_clear_isr(vector, apic);
1208 apic_update_ppr(apic);
1210 if (test_bit(vector, vcpu_to_synic(apic->vcpu)->vec_bitmap))
1211 kvm_hv_synic_send_eoi(apic->vcpu, vector);
1213 kvm_ioapic_send_eoi(apic, vector);
1214 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1219 * this interface assumes a trap-like exit, which has already finished
1220 * desired side effect including vISR and vPPR update.
1222 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
1224 struct kvm_lapic *apic = vcpu->arch.apic;
1226 trace_kvm_eoi(apic, vector);
1228 kvm_ioapic_send_eoi(apic, vector);
1229 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1231 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
1233 static void apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high)
1235 struct kvm_lapic_irq irq;
1237 irq.vector = icr_low & APIC_VECTOR_MASK;
1238 irq.delivery_mode = icr_low & APIC_MODE_MASK;
1239 irq.dest_mode = icr_low & APIC_DEST_MASK;
1240 irq.level = (icr_low & APIC_INT_ASSERT) != 0;
1241 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
1242 irq.shorthand = icr_low & APIC_SHORT_MASK;
1243 irq.msi_redir_hint = false;
1244 if (apic_x2apic_mode(apic))
1245 irq.dest_id = icr_high;
1247 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
1249 trace_kvm_apic_ipi(icr_low, irq.dest_id);
1251 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
1254 static u32 apic_get_tmcct(struct kvm_lapic *apic)
1256 ktime_t remaining, now;
1260 ASSERT(apic != NULL);
1262 /* if initial count is 0, current count should also be 0 */
1263 if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 ||
1264 apic->lapic_timer.period == 0)
1268 remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
1269 if (ktime_to_ns(remaining) < 0)
1272 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
1273 tmcct = div64_u64(ns,
1274 (APIC_BUS_CYCLE_NS * apic->divide_count));
1279 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
1281 struct kvm_vcpu *vcpu = apic->vcpu;
1282 struct kvm_run *run = vcpu->run;
1284 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
1285 run->tpr_access.rip = kvm_rip_read(vcpu);
1286 run->tpr_access.is_write = write;
1289 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
1291 if (apic->vcpu->arch.tpr_access_reporting)
1292 __report_tpr_access(apic, write);
1295 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
1299 if (offset >= LAPIC_MMIO_LENGTH)
1306 case APIC_TMCCT: /* Timer CCR */
1307 if (apic_lvtt_tscdeadline(apic))
1310 val = apic_get_tmcct(apic);
1313 apic_update_ppr(apic);
1314 val = kvm_lapic_get_reg(apic, offset);
1317 report_tpr_access(apic, false);
1320 val = kvm_lapic_get_reg(apic, offset);
1327 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1329 return container_of(dev, struct kvm_lapic, dev);
1332 #define APIC_REG_MASK(reg) (1ull << ((reg) >> 4))
1333 #define APIC_REGS_MASK(first, count) \
1334 (APIC_REG_MASK(first) * ((1ull << (count)) - 1))
1336 int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1339 unsigned char alignment = offset & 0xf;
1341 /* this bitmask has a bit cleared for each reserved register */
1342 u64 valid_reg_mask =
1343 APIC_REG_MASK(APIC_ID) |
1344 APIC_REG_MASK(APIC_LVR) |
1345 APIC_REG_MASK(APIC_TASKPRI) |
1346 APIC_REG_MASK(APIC_PROCPRI) |
1347 APIC_REG_MASK(APIC_LDR) |
1348 APIC_REG_MASK(APIC_DFR) |
1349 APIC_REG_MASK(APIC_SPIV) |
1350 APIC_REGS_MASK(APIC_ISR, APIC_ISR_NR) |
1351 APIC_REGS_MASK(APIC_TMR, APIC_ISR_NR) |
1352 APIC_REGS_MASK(APIC_IRR, APIC_ISR_NR) |
1353 APIC_REG_MASK(APIC_ESR) |
1354 APIC_REG_MASK(APIC_ICR) |
1355 APIC_REG_MASK(APIC_ICR2) |
1356 APIC_REG_MASK(APIC_LVTT) |
1357 APIC_REG_MASK(APIC_LVTTHMR) |
1358 APIC_REG_MASK(APIC_LVTPC) |
1359 APIC_REG_MASK(APIC_LVT0) |
1360 APIC_REG_MASK(APIC_LVT1) |
1361 APIC_REG_MASK(APIC_LVTERR) |
1362 APIC_REG_MASK(APIC_TMICT) |
1363 APIC_REG_MASK(APIC_TMCCT) |
1364 APIC_REG_MASK(APIC_TDCR);
1366 /* ARBPRI is not valid on x2APIC */
1367 if (!apic_x2apic_mode(apic))
1368 valid_reg_mask |= APIC_REG_MASK(APIC_ARBPRI);
1370 if (offset > 0x3f0 || !(valid_reg_mask & APIC_REG_MASK(offset)))
1373 result = __apic_read(apic, offset & ~0xf);
1375 trace_kvm_apic_read(offset, result);
1381 memcpy(data, (char *)&result + alignment, len);
1384 printk(KERN_ERR "Local APIC read with len = %x, "
1385 "should be 1,2, or 4 instead\n", len);
1390 EXPORT_SYMBOL_GPL(kvm_lapic_reg_read);
1392 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1394 return addr >= apic->base_address &&
1395 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1398 static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1399 gpa_t address, int len, void *data)
1401 struct kvm_lapic *apic = to_lapic(this);
1402 u32 offset = address - apic->base_address;
1404 if (!apic_mmio_in_range(apic, address))
1407 if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) {
1408 if (!kvm_check_has_quirk(vcpu->kvm,
1409 KVM_X86_QUIRK_LAPIC_MMIO_HOLE))
1412 memset(data, 0xff, len);
1416 kvm_lapic_reg_read(apic, offset, len, data);
1421 static void update_divide_count(struct kvm_lapic *apic)
1423 u32 tmp1, tmp2, tdcr;
1425 tdcr = kvm_lapic_get_reg(apic, APIC_TDCR);
1427 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1428 apic->divide_count = 0x1 << (tmp2 & 0x7);
1431 static void limit_periodic_timer_frequency(struct kvm_lapic *apic)
1434 * Do not allow the guest to program periodic timers with small
1435 * interval, since the hrtimers are not throttled by the host
1438 if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1439 s64 min_period = min_timer_period_us * 1000LL;
1441 if (apic->lapic_timer.period < min_period) {
1442 pr_info_ratelimited(
1443 "kvm: vcpu %i: requested %lld ns "
1444 "lapic timer period limited to %lld ns\n",
1445 apic->vcpu->vcpu_id,
1446 apic->lapic_timer.period, min_period);
1447 apic->lapic_timer.period = min_period;
1452 static void apic_update_lvtt(struct kvm_lapic *apic)
1454 u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) &
1455 apic->lapic_timer.timer_mode_mask;
1457 if (apic->lapic_timer.timer_mode != timer_mode) {
1458 if (apic_lvtt_tscdeadline(apic) != (timer_mode ==
1459 APIC_LVT_TIMER_TSCDEADLINE)) {
1460 hrtimer_cancel(&apic->lapic_timer.timer);
1461 kvm_lapic_set_reg(apic, APIC_TMICT, 0);
1462 apic->lapic_timer.period = 0;
1463 apic->lapic_timer.tscdeadline = 0;
1465 apic->lapic_timer.timer_mode = timer_mode;
1466 limit_periodic_timer_frequency(apic);
1471 * On APICv, this test will cause a busy wait
1472 * during a higher-priority task.
1475 static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1477 struct kvm_lapic *apic = vcpu->arch.apic;
1478 u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT);
1480 if (kvm_apic_hw_enabled(apic)) {
1481 int vec = reg & APIC_VECTOR_MASK;
1482 void *bitmap = apic->regs + APIC_ISR;
1484 if (vcpu->arch.apicv_active)
1485 bitmap = apic->regs + APIC_IRR;
1487 if (apic_test_vector(vec, bitmap))
1493 static inline void __wait_lapic_expire(struct kvm_vcpu *vcpu, u64 guest_cycles)
1495 u64 timer_advance_ns = vcpu->arch.apic->lapic_timer.timer_advance_ns;
1498 * If the guest TSC is running at a different ratio than the host, then
1499 * convert the delay to nanoseconds to achieve an accurate delay. Note
1500 * that __delay() uses delay_tsc whenever the hardware has TSC, thus
1501 * always for VMX enabled hardware.
1503 if (vcpu->arch.tsc_scaling_ratio == kvm_default_tsc_scaling_ratio) {
1504 __delay(min(guest_cycles,
1505 nsec_to_cycles(vcpu, timer_advance_ns)));
1507 u64 delay_ns = guest_cycles * 1000000ULL;
1508 do_div(delay_ns, vcpu->arch.virtual_tsc_khz);
1509 ndelay(min_t(u32, delay_ns, timer_advance_ns));
1513 static inline void adjust_lapic_timer_advance(struct kvm_vcpu *vcpu,
1514 s64 advance_expire_delta)
1516 struct kvm_lapic *apic = vcpu->arch.apic;
1517 u32 timer_advance_ns = apic->lapic_timer.timer_advance_ns;
1520 /* Do not adjust for tiny fluctuations or large random spikes. */
1521 if (abs(advance_expire_delta) > LAPIC_TIMER_ADVANCE_ADJUST_MAX ||
1522 abs(advance_expire_delta) < LAPIC_TIMER_ADVANCE_ADJUST_MIN)
1526 if (advance_expire_delta < 0) {
1527 ns = -advance_expire_delta * 1000000ULL;
1528 do_div(ns, vcpu->arch.virtual_tsc_khz);
1529 timer_advance_ns -= ns/LAPIC_TIMER_ADVANCE_ADJUST_STEP;
1532 ns = advance_expire_delta * 1000000ULL;
1533 do_div(ns, vcpu->arch.virtual_tsc_khz);
1534 timer_advance_ns += ns/LAPIC_TIMER_ADVANCE_ADJUST_STEP;
1537 if (unlikely(timer_advance_ns > LAPIC_TIMER_ADVANCE_NS_MAX))
1538 timer_advance_ns = LAPIC_TIMER_ADVANCE_NS_INIT;
1539 apic->lapic_timer.timer_advance_ns = timer_advance_ns;
1542 static void __kvm_wait_lapic_expire(struct kvm_vcpu *vcpu)
1544 struct kvm_lapic *apic = vcpu->arch.apic;
1545 u64 guest_tsc, tsc_deadline;
1547 if (apic->lapic_timer.expired_tscdeadline == 0)
1550 tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1551 apic->lapic_timer.expired_tscdeadline = 0;
1552 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1553 apic->lapic_timer.advance_expire_delta = guest_tsc - tsc_deadline;
1555 if (guest_tsc < tsc_deadline)
1556 __wait_lapic_expire(vcpu, tsc_deadline - guest_tsc);
1558 if (lapic_timer_advance_dynamic)
1559 adjust_lapic_timer_advance(vcpu, apic->lapic_timer.advance_expire_delta);
1562 void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu)
1564 if (lapic_timer_int_injected(vcpu))
1565 __kvm_wait_lapic_expire(vcpu);
1567 EXPORT_SYMBOL_GPL(kvm_wait_lapic_expire);
1569 static void kvm_apic_inject_pending_timer_irqs(struct kvm_lapic *apic)
1571 struct kvm_timer *ktimer = &apic->lapic_timer;
1573 kvm_apic_local_deliver(apic, APIC_LVTT);
1574 if (apic_lvtt_tscdeadline(apic))
1575 ktimer->tscdeadline = 0;
1576 if (apic_lvtt_oneshot(apic)) {
1577 ktimer->tscdeadline = 0;
1578 ktimer->target_expiration = 0;
1582 static void apic_timer_expired(struct kvm_lapic *apic)
1584 struct kvm_vcpu *vcpu = apic->vcpu;
1585 struct kvm_timer *ktimer = &apic->lapic_timer;
1587 if (atomic_read(&apic->lapic_timer.pending))
1590 if (apic_lvtt_tscdeadline(apic) || ktimer->hv_timer_in_use)
1591 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1593 if (kvm_use_posted_timer_interrupt(apic->vcpu)) {
1594 if (apic->lapic_timer.timer_advance_ns)
1595 __kvm_wait_lapic_expire(vcpu);
1596 kvm_apic_inject_pending_timer_irqs(apic);
1600 atomic_inc(&apic->lapic_timer.pending);
1601 kvm_set_pending_timer(vcpu);
1604 static void start_sw_tscdeadline(struct kvm_lapic *apic)
1606 struct kvm_timer *ktimer = &apic->lapic_timer;
1607 u64 guest_tsc, tscdeadline = ktimer->tscdeadline;
1610 struct kvm_vcpu *vcpu = apic->vcpu;
1611 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1612 unsigned long flags;
1615 if (unlikely(!tscdeadline || !this_tsc_khz))
1618 local_irq_save(flags);
1621 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1623 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1624 do_div(ns, this_tsc_khz);
1626 if (likely(tscdeadline > guest_tsc) &&
1627 likely(ns > apic->lapic_timer.timer_advance_ns)) {
1628 expire = ktime_add_ns(now, ns);
1629 expire = ktime_sub_ns(expire, ktimer->timer_advance_ns);
1630 hrtimer_start(&ktimer->timer, expire, HRTIMER_MODE_ABS_HARD);
1632 apic_timer_expired(apic);
1634 local_irq_restore(flags);
1637 static void update_target_expiration(struct kvm_lapic *apic, uint32_t old_divisor)
1639 ktime_t now, remaining;
1640 u64 ns_remaining_old, ns_remaining_new;
1642 apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT)
1643 * APIC_BUS_CYCLE_NS * apic->divide_count;
1644 limit_periodic_timer_frequency(apic);
1647 remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
1648 if (ktime_to_ns(remaining) < 0)
1651 ns_remaining_old = ktime_to_ns(remaining);
1652 ns_remaining_new = mul_u64_u32_div(ns_remaining_old,
1653 apic->divide_count, old_divisor);
1655 apic->lapic_timer.tscdeadline +=
1656 nsec_to_cycles(apic->vcpu, ns_remaining_new) -
1657 nsec_to_cycles(apic->vcpu, ns_remaining_old);
1658 apic->lapic_timer.target_expiration = ktime_add_ns(now, ns_remaining_new);
1661 static bool set_target_expiration(struct kvm_lapic *apic)
1667 apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT)
1668 * APIC_BUS_CYCLE_NS * apic->divide_count;
1670 if (!apic->lapic_timer.period) {
1671 apic->lapic_timer.tscdeadline = 0;
1675 limit_periodic_timer_frequency(apic);
1677 apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
1678 nsec_to_cycles(apic->vcpu, apic->lapic_timer.period);
1679 apic->lapic_timer.target_expiration = ktime_add_ns(now, apic->lapic_timer.period);
1684 static void advance_periodic_target_expiration(struct kvm_lapic *apic)
1686 ktime_t now = ktime_get();
1691 * Synchronize both deadlines to the same time source or
1692 * differences in the periods (caused by differences in the
1693 * underlying clocks or numerical approximation errors) will
1694 * cause the two to drift apart over time as the errors
1697 apic->lapic_timer.target_expiration =
1698 ktime_add_ns(apic->lapic_timer.target_expiration,
1699 apic->lapic_timer.period);
1700 delta = ktime_sub(apic->lapic_timer.target_expiration, now);
1701 apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
1702 nsec_to_cycles(apic->vcpu, delta);
1705 static void start_sw_period(struct kvm_lapic *apic)
1707 if (!apic->lapic_timer.period)
1710 if (ktime_after(ktime_get(),
1711 apic->lapic_timer.target_expiration)) {
1712 apic_timer_expired(apic);
1714 if (apic_lvtt_oneshot(apic))
1717 advance_periodic_target_expiration(apic);
1720 hrtimer_start(&apic->lapic_timer.timer,
1721 apic->lapic_timer.target_expiration,
1725 bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu)
1727 if (!lapic_in_kernel(vcpu))
1730 return vcpu->arch.apic->lapic_timer.hv_timer_in_use;
1732 EXPORT_SYMBOL_GPL(kvm_lapic_hv_timer_in_use);
1734 static void cancel_hv_timer(struct kvm_lapic *apic)
1736 WARN_ON(preemptible());
1737 WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1738 kvm_x86_ops->cancel_hv_timer(apic->vcpu);
1739 apic->lapic_timer.hv_timer_in_use = false;
1742 static bool start_hv_timer(struct kvm_lapic *apic)
1744 struct kvm_timer *ktimer = &apic->lapic_timer;
1745 struct kvm_vcpu *vcpu = apic->vcpu;
1748 WARN_ON(preemptible());
1749 if (!kvm_x86_ops->set_hv_timer)
1752 if (!ktimer->tscdeadline)
1755 if (kvm_x86_ops->set_hv_timer(vcpu, ktimer->tscdeadline, &expired))
1758 ktimer->hv_timer_in_use = true;
1759 hrtimer_cancel(&ktimer->timer);
1762 * To simplify handling the periodic timer, leave the hv timer running
1763 * even if the deadline timer has expired, i.e. rely on the resulting
1764 * VM-Exit to recompute the periodic timer's target expiration.
1766 if (!apic_lvtt_period(apic)) {
1768 * Cancel the hv timer if the sw timer fired while the hv timer
1769 * was being programmed, or if the hv timer itself expired.
1771 if (atomic_read(&ktimer->pending)) {
1772 cancel_hv_timer(apic);
1773 } else if (expired) {
1774 apic_timer_expired(apic);
1775 cancel_hv_timer(apic);
1779 trace_kvm_hv_timer_state(vcpu->vcpu_id, ktimer->hv_timer_in_use);
1784 static void start_sw_timer(struct kvm_lapic *apic)
1786 struct kvm_timer *ktimer = &apic->lapic_timer;
1788 WARN_ON(preemptible());
1789 if (apic->lapic_timer.hv_timer_in_use)
1790 cancel_hv_timer(apic);
1791 if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending))
1794 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1795 start_sw_period(apic);
1796 else if (apic_lvtt_tscdeadline(apic))
1797 start_sw_tscdeadline(apic);
1798 trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, false);
1801 static void restart_apic_timer(struct kvm_lapic *apic)
1805 if (!apic_lvtt_period(apic) && atomic_read(&apic->lapic_timer.pending))
1808 if (!start_hv_timer(apic))
1809 start_sw_timer(apic);
1814 void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu)
1816 struct kvm_lapic *apic = vcpu->arch.apic;
1819 /* If the preempt notifier has already run, it also called apic_timer_expired */
1820 if (!apic->lapic_timer.hv_timer_in_use)
1822 WARN_ON(swait_active(&vcpu->wq));
1823 cancel_hv_timer(apic);
1824 apic_timer_expired(apic);
1826 if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1827 advance_periodic_target_expiration(apic);
1828 restart_apic_timer(apic);
1833 EXPORT_SYMBOL_GPL(kvm_lapic_expired_hv_timer);
1835 void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu)
1837 restart_apic_timer(vcpu->arch.apic);
1839 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_hv_timer);
1841 void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu)
1843 struct kvm_lapic *apic = vcpu->arch.apic;
1846 /* Possibly the TSC deadline timer is not enabled yet */
1847 if (apic->lapic_timer.hv_timer_in_use)
1848 start_sw_timer(apic);
1851 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_sw_timer);
1853 void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu)
1855 struct kvm_lapic *apic = vcpu->arch.apic;
1857 WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1858 restart_apic_timer(apic);
1861 static void start_apic_timer(struct kvm_lapic *apic)
1863 atomic_set(&apic->lapic_timer.pending, 0);
1865 if ((apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1866 && !set_target_expiration(apic))
1869 restart_apic_timer(apic);
1872 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1874 bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val);
1876 if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) {
1877 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode;
1878 if (lvt0_in_nmi_mode) {
1879 atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1881 atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1885 int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1889 trace_kvm_apic_write(reg, val);
1892 case APIC_ID: /* Local APIC ID */
1893 if (!apic_x2apic_mode(apic))
1894 kvm_apic_set_xapic_id(apic, val >> 24);
1900 report_tpr_access(apic, true);
1901 apic_set_tpr(apic, val & 0xff);
1909 if (!apic_x2apic_mode(apic))
1910 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1916 if (!apic_x2apic_mode(apic)) {
1917 kvm_lapic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1918 recalculate_apic_map(apic->vcpu->kvm);
1925 if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1926 mask |= APIC_SPIV_DIRECTED_EOI;
1927 apic_set_spiv(apic, val & mask);
1928 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1932 for (i = 0; i < KVM_APIC_LVT_NUM; i++) {
1933 lvt_val = kvm_lapic_get_reg(apic,
1934 APIC_LVTT + 0x10 * i);
1935 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i,
1936 lvt_val | APIC_LVT_MASKED);
1938 apic_update_lvtt(apic);
1939 atomic_set(&apic->lapic_timer.pending, 0);
1945 /* No delay here, so we always clear the pending bit */
1947 apic_send_ipi(apic, val, kvm_lapic_get_reg(apic, APIC_ICR2));
1948 kvm_lapic_set_reg(apic, APIC_ICR, val);
1952 if (!apic_x2apic_mode(apic))
1954 kvm_lapic_set_reg(apic, APIC_ICR2, val);
1958 apic_manage_nmi_watchdog(apic, val);
1964 /* TODO: Check vector */
1965 if (!kvm_apic_sw_enabled(apic))
1966 val |= APIC_LVT_MASKED;
1968 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1969 kvm_lapic_set_reg(apic, reg, val);
1974 if (!kvm_apic_sw_enabled(apic))
1975 val |= APIC_LVT_MASKED;
1976 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1977 kvm_lapic_set_reg(apic, APIC_LVTT, val);
1978 apic_update_lvtt(apic);
1982 if (apic_lvtt_tscdeadline(apic))
1985 hrtimer_cancel(&apic->lapic_timer.timer);
1986 kvm_lapic_set_reg(apic, APIC_TMICT, val);
1987 start_apic_timer(apic);
1991 uint32_t old_divisor = apic->divide_count;
1993 kvm_lapic_set_reg(apic, APIC_TDCR, val);
1994 update_divide_count(apic);
1995 if (apic->divide_count != old_divisor &&
1996 apic->lapic_timer.period) {
1997 hrtimer_cancel(&apic->lapic_timer.timer);
1998 update_target_expiration(apic, old_divisor);
1999 restart_apic_timer(apic);
2004 if (apic_x2apic_mode(apic) && val != 0)
2009 if (apic_x2apic_mode(apic)) {
2010 kvm_lapic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
2021 EXPORT_SYMBOL_GPL(kvm_lapic_reg_write);
2023 static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
2024 gpa_t address, int len, const void *data)
2026 struct kvm_lapic *apic = to_lapic(this);
2027 unsigned int offset = address - apic->base_address;
2030 if (!apic_mmio_in_range(apic, address))
2033 if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) {
2034 if (!kvm_check_has_quirk(vcpu->kvm,
2035 KVM_X86_QUIRK_LAPIC_MMIO_HOLE))
2042 * APIC register must be aligned on 128-bits boundary.
2043 * 32/64/128 bits registers must be accessed thru 32 bits.
2046 if (len != 4 || (offset & 0xf))
2051 kvm_lapic_reg_write(apic, offset & 0xff0, val);
2056 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
2058 kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
2060 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
2062 /* emulate APIC access in a trap manner */
2063 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
2067 /* hw has done the conditional check and inst decode */
2070 kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val);
2072 /* TODO: optimize to just emulate side effect w/o one more write */
2073 kvm_lapic_reg_write(vcpu->arch.apic, offset, val);
2075 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
2077 void kvm_free_lapic(struct kvm_vcpu *vcpu)
2079 struct kvm_lapic *apic = vcpu->arch.apic;
2081 if (!vcpu->arch.apic)
2084 hrtimer_cancel(&apic->lapic_timer.timer);
2086 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
2087 static_key_slow_dec_deferred(&apic_hw_disabled);
2089 if (!apic->sw_enabled)
2090 static_key_slow_dec_deferred(&apic_sw_disabled);
2093 free_page((unsigned long)apic->regs);
2099 *----------------------------------------------------------------------
2101 *----------------------------------------------------------------------
2103 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
2105 struct kvm_lapic *apic = vcpu->arch.apic;
2107 if (!lapic_in_kernel(vcpu) ||
2108 !apic_lvtt_tscdeadline(apic))
2111 return apic->lapic_timer.tscdeadline;
2114 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
2116 struct kvm_lapic *apic = vcpu->arch.apic;
2118 if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) ||
2119 apic_lvtt_period(apic))
2122 hrtimer_cancel(&apic->lapic_timer.timer);
2123 apic->lapic_timer.tscdeadline = data;
2124 start_apic_timer(apic);
2127 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
2129 struct kvm_lapic *apic = vcpu->arch.apic;
2131 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
2132 | (kvm_lapic_get_reg(apic, APIC_TASKPRI) & 4));
2135 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
2139 tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
2141 return (tpr & 0xf0) >> 4;
2144 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
2146 u64 old_value = vcpu->arch.apic_base;
2147 struct kvm_lapic *apic = vcpu->arch.apic;
2150 value |= MSR_IA32_APICBASE_BSP;
2152 vcpu->arch.apic_base = value;
2154 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE)
2155 kvm_update_cpuid(vcpu);
2160 /* update jump label if enable bit changes */
2161 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
2162 if (value & MSR_IA32_APICBASE_ENABLE) {
2163 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
2164 static_key_slow_dec_deferred(&apic_hw_disabled);
2166 static_key_slow_inc(&apic_hw_disabled.key);
2167 recalculate_apic_map(vcpu->kvm);
2171 if (((old_value ^ value) & X2APIC_ENABLE) && (value & X2APIC_ENABLE))
2172 kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);
2174 if ((old_value ^ value) & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE))
2175 kvm_x86_ops->set_virtual_apic_mode(vcpu);
2177 apic->base_address = apic->vcpu->arch.apic_base &
2178 MSR_IA32_APICBASE_BASE;
2180 if ((value & MSR_IA32_APICBASE_ENABLE) &&
2181 apic->base_address != APIC_DEFAULT_PHYS_BASE)
2182 pr_warn_once("APIC base relocation is unsupported by KVM");
2185 void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
2187 struct kvm_lapic *apic = vcpu->arch.apic;
2193 /* Stop the timer in case it's a reset to an active apic */
2194 hrtimer_cancel(&apic->lapic_timer.timer);
2197 kvm_lapic_set_base(vcpu, APIC_DEFAULT_PHYS_BASE |
2198 MSR_IA32_APICBASE_ENABLE);
2199 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
2201 kvm_apic_set_version(apic->vcpu);
2203 for (i = 0; i < KVM_APIC_LVT_NUM; i++)
2204 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
2205 apic_update_lvtt(apic);
2206 if (kvm_vcpu_is_reset_bsp(vcpu) &&
2207 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
2208 kvm_lapic_set_reg(apic, APIC_LVT0,
2209 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
2210 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
2212 kvm_lapic_set_reg(apic, APIC_DFR, 0xffffffffU);
2213 apic_set_spiv(apic, 0xff);
2214 kvm_lapic_set_reg(apic, APIC_TASKPRI, 0);
2215 if (!apic_x2apic_mode(apic))
2216 kvm_apic_set_ldr(apic, 0);
2217 kvm_lapic_set_reg(apic, APIC_ESR, 0);
2218 kvm_lapic_set_reg(apic, APIC_ICR, 0);
2219 kvm_lapic_set_reg(apic, APIC_ICR2, 0);
2220 kvm_lapic_set_reg(apic, APIC_TDCR, 0);
2221 kvm_lapic_set_reg(apic, APIC_TMICT, 0);
2222 for (i = 0; i < 8; i++) {
2223 kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
2224 kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
2225 kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
2227 apic->irr_pending = vcpu->arch.apicv_active;
2228 apic->isr_count = vcpu->arch.apicv_active ? 1 : 0;
2229 apic->highest_isr_cache = -1;
2230 update_divide_count(apic);
2231 atomic_set(&apic->lapic_timer.pending, 0);
2232 if (kvm_vcpu_is_bsp(vcpu))
2233 kvm_lapic_set_base(vcpu,
2234 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
2235 vcpu->arch.pv_eoi.msr_val = 0;
2236 apic_update_ppr(apic);
2237 if (vcpu->arch.apicv_active) {
2238 kvm_x86_ops->apicv_post_state_restore(vcpu);
2239 kvm_x86_ops->hwapic_irr_update(vcpu, -1);
2240 kvm_x86_ops->hwapic_isr_update(vcpu, -1);
2243 vcpu->arch.apic_arb_prio = 0;
2244 vcpu->arch.apic_attention = 0;
2248 *----------------------------------------------------------------------
2250 *----------------------------------------------------------------------
2253 static bool lapic_is_periodic(struct kvm_lapic *apic)
2255 return apic_lvtt_period(apic);
2258 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
2260 struct kvm_lapic *apic = vcpu->arch.apic;
2262 if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT))
2263 return atomic_read(&apic->lapic_timer.pending);
2268 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
2270 u32 reg = kvm_lapic_get_reg(apic, lvt_type);
2271 int vector, mode, trig_mode;
2273 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
2274 vector = reg & APIC_VECTOR_MASK;
2275 mode = reg & APIC_MODE_MASK;
2276 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
2277 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
2283 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
2285 struct kvm_lapic *apic = vcpu->arch.apic;
2288 kvm_apic_local_deliver(apic, APIC_LVT0);
2291 static const struct kvm_io_device_ops apic_mmio_ops = {
2292 .read = apic_mmio_read,
2293 .write = apic_mmio_write,
2296 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
2298 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
2299 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
2301 apic_timer_expired(apic);
2303 if (lapic_is_periodic(apic)) {
2304 advance_periodic_target_expiration(apic);
2305 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
2306 return HRTIMER_RESTART;
2308 return HRTIMER_NORESTART;
2311 int kvm_create_lapic(struct kvm_vcpu *vcpu, int timer_advance_ns)
2313 struct kvm_lapic *apic;
2315 ASSERT(vcpu != NULL);
2317 apic = kzalloc(sizeof(*apic), GFP_KERNEL_ACCOUNT);
2321 vcpu->arch.apic = apic;
2323 apic->regs = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
2325 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
2327 goto nomem_free_apic;
2331 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
2332 HRTIMER_MODE_ABS_HARD);
2333 apic->lapic_timer.timer.function = apic_timer_fn;
2334 if (timer_advance_ns == -1) {
2335 apic->lapic_timer.timer_advance_ns = LAPIC_TIMER_ADVANCE_NS_INIT;
2336 lapic_timer_advance_dynamic = true;
2338 apic->lapic_timer.timer_advance_ns = timer_advance_ns;
2339 lapic_timer_advance_dynamic = false;
2343 * APIC is created enabled. This will prevent kvm_lapic_set_base from
2344 * thinking that APIC state has changed.
2346 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
2347 static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
2348 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
2353 vcpu->arch.apic = NULL;
2358 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
2360 struct kvm_lapic *apic = vcpu->arch.apic;
2363 if (!kvm_apic_hw_enabled(apic))
2366 __apic_update_ppr(apic, &ppr);
2367 return apic_has_interrupt_for_ppr(apic, ppr);
2370 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
2372 u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0);
2375 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
2377 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
2378 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
2383 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
2385 struct kvm_lapic *apic = vcpu->arch.apic;
2387 if (atomic_read(&apic->lapic_timer.pending) > 0) {
2388 kvm_apic_inject_pending_timer_irqs(apic);
2389 atomic_set(&apic->lapic_timer.pending, 0);
2393 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
2395 int vector = kvm_apic_has_interrupt(vcpu);
2396 struct kvm_lapic *apic = vcpu->arch.apic;
2403 * We get here even with APIC virtualization enabled, if doing
2404 * nested virtualization and L1 runs with the "acknowledge interrupt
2405 * on exit" mode. Then we cannot inject the interrupt via RVI,
2406 * because the process would deliver it through the IDT.
2409 apic_clear_irr(vector, apic);
2410 if (test_bit(vector, vcpu_to_synic(vcpu)->auto_eoi_bitmap)) {
2412 * For auto-EOI interrupts, there might be another pending
2413 * interrupt above PPR, so check whether to raise another
2416 apic_update_ppr(apic);
2419 * For normal interrupts, PPR has been raised and there cannot
2420 * be a higher-priority pending interrupt---except if there was
2421 * a concurrent interrupt injection, but that would have
2422 * triggered KVM_REQ_EVENT already.
2424 apic_set_isr(vector, apic);
2425 __apic_update_ppr(apic, &ppr);
2431 static int kvm_apic_state_fixup(struct kvm_vcpu *vcpu,
2432 struct kvm_lapic_state *s, bool set)
2434 if (apic_x2apic_mode(vcpu->arch.apic)) {
2435 u32 *id = (u32 *)(s->regs + APIC_ID);
2436 u32 *ldr = (u32 *)(s->regs + APIC_LDR);
2438 if (vcpu->kvm->arch.x2apic_format) {
2439 if (*id != vcpu->vcpu_id)
2448 /* In x2APIC mode, the LDR is fixed and based on the id */
2450 *ldr = kvm_apic_calc_x2apic_ldr(*id);
2456 int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2458 memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s));
2459 return kvm_apic_state_fixup(vcpu, s, false);
2462 int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2464 struct kvm_lapic *apic = vcpu->arch.apic;
2468 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
2469 /* set SPIV separately to get count of SW disabled APICs right */
2470 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
2472 r = kvm_apic_state_fixup(vcpu, s, true);
2475 memcpy(vcpu->arch.apic->regs, s->regs, sizeof(*s));
2477 recalculate_apic_map(vcpu->kvm);
2478 kvm_apic_set_version(vcpu);
2480 apic_update_ppr(apic);
2481 hrtimer_cancel(&apic->lapic_timer.timer);
2482 apic_update_lvtt(apic);
2483 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
2484 update_divide_count(apic);
2485 start_apic_timer(apic);
2486 apic->irr_pending = true;
2487 apic->isr_count = vcpu->arch.apicv_active ?
2488 1 : count_vectors(apic->regs + APIC_ISR);
2489 apic->highest_isr_cache = -1;
2490 if (vcpu->arch.apicv_active) {
2491 kvm_x86_ops->apicv_post_state_restore(vcpu);
2492 kvm_x86_ops->hwapic_irr_update(vcpu,
2493 apic_find_highest_irr(apic));
2494 kvm_x86_ops->hwapic_isr_update(vcpu,
2495 apic_find_highest_isr(apic));
2497 kvm_make_request(KVM_REQ_EVENT, vcpu);
2498 if (ioapic_in_kernel(vcpu->kvm))
2499 kvm_rtc_eoi_tracking_restore_one(vcpu);
2501 vcpu->arch.apic_arb_prio = 0;
2506 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
2508 struct hrtimer *timer;
2510 if (!lapic_in_kernel(vcpu) ||
2511 kvm_can_post_timer_interrupt(vcpu))
2514 timer = &vcpu->arch.apic->lapic_timer.timer;
2515 if (hrtimer_cancel(timer))
2516 hrtimer_start_expires(timer, HRTIMER_MODE_ABS_HARD);
2520 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
2522 * Detect whether guest triggered PV EOI since the
2523 * last entry. If yes, set EOI on guests's behalf.
2524 * Clear PV EOI in guest memory in any case.
2526 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
2527 struct kvm_lapic *apic)
2532 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
2533 * and KVM_PV_EOI_ENABLED in guest memory as follows:
2535 * KVM_APIC_PV_EOI_PENDING is unset:
2536 * -> host disabled PV EOI.
2537 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
2538 * -> host enabled PV EOI, guest did not execute EOI yet.
2539 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
2540 * -> host enabled PV EOI, guest executed EOI.
2542 BUG_ON(!pv_eoi_enabled(vcpu));
2543 pending = pv_eoi_get_pending(vcpu);
2545 * Clear pending bit in any case: it will be set again on vmentry.
2546 * While this might not be ideal from performance point of view,
2547 * this makes sure pv eoi is only enabled when we know it's safe.
2549 pv_eoi_clr_pending(vcpu);
2552 vector = apic_set_eoi(apic);
2553 trace_kvm_pv_eoi(apic, vector);
2556 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
2560 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
2561 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
2563 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2566 if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2570 apic_set_tpr(vcpu->arch.apic, data & 0xff);
2574 * apic_sync_pv_eoi_to_guest - called before vmentry
2576 * Detect whether it's safe to enable PV EOI and
2579 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
2580 struct kvm_lapic *apic)
2582 if (!pv_eoi_enabled(vcpu) ||
2583 /* IRR set or many bits in ISR: could be nested. */
2584 apic->irr_pending ||
2585 /* Cache not set: could be safe but we don't bother. */
2586 apic->highest_isr_cache == -1 ||
2587 /* Need EOI to update ioapic. */
2588 kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) {
2590 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
2591 * so we need not do anything here.
2596 pv_eoi_set_pending(apic->vcpu);
2599 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
2602 int max_irr, max_isr;
2603 struct kvm_lapic *apic = vcpu->arch.apic;
2605 apic_sync_pv_eoi_to_guest(vcpu, apic);
2607 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2610 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff;
2611 max_irr = apic_find_highest_irr(apic);
2614 max_isr = apic_find_highest_isr(apic);
2617 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
2619 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2623 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
2626 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2627 &vcpu->arch.apic->vapic_cache,
2628 vapic_addr, sizeof(u32)))
2630 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2632 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2635 vcpu->arch.apic->vapic_addr = vapic_addr;
2639 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2641 struct kvm_lapic *apic = vcpu->arch.apic;
2642 u32 reg = (msr - APIC_BASE_MSR) << 4;
2644 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2647 if (reg == APIC_ICR2)
2650 /* if this is ICR write vector before command */
2651 if (reg == APIC_ICR)
2652 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2653 return kvm_lapic_reg_write(apic, reg, (u32)data);
2656 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
2658 struct kvm_lapic *apic = vcpu->arch.apic;
2659 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
2661 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2664 if (reg == APIC_DFR || reg == APIC_ICR2)
2667 if (kvm_lapic_reg_read(apic, reg, 4, &low))
2669 if (reg == APIC_ICR)
2670 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2672 *data = (((u64)high) << 32) | low;
2677 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
2679 struct kvm_lapic *apic = vcpu->arch.apic;
2681 if (!lapic_in_kernel(vcpu))
2684 /* if this is ICR write vector before command */
2685 if (reg == APIC_ICR)
2686 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2687 return kvm_lapic_reg_write(apic, reg, (u32)data);
2690 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2692 struct kvm_lapic *apic = vcpu->arch.apic;
2695 if (!lapic_in_kernel(vcpu))
2698 if (kvm_lapic_reg_read(apic, reg, 4, &low))
2700 if (reg == APIC_ICR)
2701 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2703 *data = (((u64)high) << 32) | low;
2708 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len)
2710 u64 addr = data & ~KVM_MSR_ENABLED;
2711 struct gfn_to_hva_cache *ghc = &vcpu->arch.pv_eoi.data;
2712 unsigned long new_len;
2714 if (!IS_ALIGNED(addr, 4))
2717 vcpu->arch.pv_eoi.msr_val = data;
2718 if (!pv_eoi_enabled(vcpu))
2721 if (addr == ghc->gpa && len <= ghc->len)
2726 return kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, addr, new_len);
2729 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2731 struct kvm_lapic *apic = vcpu->arch.apic;
2735 if (!lapic_in_kernel(vcpu) || !apic->pending_events)
2739 * INITs are latched while CPU is in specific states
2740 * (SMM, VMX non-root mode, SVM with GIF=0).
2741 * Because a CPU cannot be in these states immediately
2742 * after it has processed an INIT signal (and thus in
2743 * KVM_MP_STATE_INIT_RECEIVED state), just eat SIPIs
2744 * and leave the INIT pending.
2746 if (kvm_vcpu_latch_init(vcpu)) {
2747 WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED);
2748 if (test_bit(KVM_APIC_SIPI, &apic->pending_events))
2749 clear_bit(KVM_APIC_SIPI, &apic->pending_events);
2753 pe = xchg(&apic->pending_events, 0);
2754 if (test_bit(KVM_APIC_INIT, &pe)) {
2755 kvm_vcpu_reset(vcpu, true);
2756 if (kvm_vcpu_is_bsp(apic->vcpu))
2757 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2759 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2761 if (test_bit(KVM_APIC_SIPI, &pe) &&
2762 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2763 /* evaluate pending_events before reading the vector */
2765 sipi_vector = apic->sipi_vector;
2766 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2767 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2771 void kvm_lapic_init(void)
2773 /* do not patch jump label more than once per second */
2774 jump_label_rate_limit(&apic_hw_disabled, HZ);
2775 jump_label_rate_limit(&apic_sw_disabled, HZ);
2778 void kvm_lapic_exit(void)
2780 static_key_deferred_flush(&apic_hw_disabled);
2781 static_key_deferred_flush(&apic_sw_disabled);