arch/x86/kvm/lapic.c

   1
   2 /*
   3  * Local APIC virtualization
   4  *
   5  * Copyright (C) 2006 Qumranet, Inc.
   6  * Copyright (C) 2007 Novell
   7  * Copyright (C) 2007 Intel
   8  * Copyright 2009 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Dor Laor <dor.laor@qumranet.com>
  12  *   Gregory Haskins <ghaskins@novell.com>
  13  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
  14  *
  15  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  16  *
  17  * This work is licensed under the terms of the GNU GPL, version 2.  See
  18  * the COPYING file in the top-level directory.
  19  */
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/kvm.h>
  23 #include <linux/mm.h>
  24 #include <linux/highmem.h>
  25 #include <linux/smp.h>
  26 #include <linux/hrtimer.h>
  27 #include <linux/io.h>
  28 #include <linux/module.h>
  29 #include <linux/math64.h>
  30 #include <linux/slab.h>
  31 #include <asm/processor.h>
  32 #include <asm/msr.h>
  33 #include <asm/page.h>
  34 #include <asm/current.h>
  35 #include <asm/apicdef.h>
  36 #include <linux/atomic.h>
  37 #include <linux/jump_label.h>
  38 #include "kvm_cache_regs.h"
  39 #include "irq.h"
  40 #include "trace.h"
  41 #include "x86.h"
  42 #include "cpuid.h"
  43
  44 #ifndef CONFIG_X86_64
  45 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
  46 #else
  47 #define mod_64(x, y) ((x) % (y))
  48 #endif
  49
  50 #define PRId64 "d"
  51 #define PRIx64 "llx"
  52 #define PRIu64 "u"
  53 #define PRIo64 "o"
  54
  55 #define APIC_BUS_CYCLE_NS 1
  56
  57 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  58 #define apic_debug(fmt, arg...)
  59
  60 #define APIC_LVT_NUM                    6
  61 /* 14 is the version for Xeon and Pentium 8.4.8*/
  62 #define APIC_VERSION                    (0x14UL | ((APIC_LVT_NUM - 1) << 16))
  63 #define LAPIC_MMIO_LENGTH               (1 << 12)
  64 /* followed define is not in apicdef.h */
  65 #define APIC_SHORT_MASK                 0xc0000
  66 #define APIC_DEST_NOSHORT               0x0
  67 #define APIC_DEST_MASK                  0x800
  68 #define MAX_APIC_VECTOR                 256
  69
  70 #define VEC_POS(v) ((v) & (32 - 1))
  71 #define REG_POS(v) (((v) >> 5) << 4)
  72
  73 static unsigned int min_timer_period_us = 500;
  74 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
  75
  76 static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
  77 {
  78         return *((u32 *) (apic->regs + reg_off));
  79 }
  80
  81 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
  82 {
  83         *((u32 *) (apic->regs + reg_off)) = val;
  84 }
  85
  86 static inline int apic_test_and_set_vector(int vec, void *bitmap)
  87 {
  88         return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  89 }
  90
  91 static inline int apic_test_and_clear_vector(int vec, void *bitmap)
  92 {
  93         return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  94 }
  95
  96 static inline int apic_test_vector(int vec, void *bitmap)
  97 {
  98         return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  99 }
 100
 101 static inline void apic_set_vector(int vec, void *bitmap)
 102 {
 103         set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 104 }
 105
 106 static inline void apic_clear_vector(int vec, void *bitmap)
 107 {
 108         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 109 }
 110
 111 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
 112 {
 113         return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 114 }
 115
 116 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
 117 {
 118         return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 119 }
 120
 121 struct static_key_deferred apic_hw_disabled __read_mostly;
 122
 123 static inline int apic_hw_enabled(struct kvm_lapic *apic)
 124 {
 125         if (static_key_false(&apic_hw_disabled.key))
 126                 return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
 127         return MSR_IA32_APICBASE_ENABLE;
 128 }
 129
 130 struct static_key_deferred apic_sw_disabled __read_mostly;
 131
 132 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
 133 {
 134         if ((apic_get_reg(apic, APIC_SPIV) ^ val) & APIC_SPIV_APIC_ENABLED) {
 135                 if (val & APIC_SPIV_APIC_ENABLED)
 136                         static_key_slow_dec_deferred(&apic_sw_disabled);
 137                 else
 138                         static_key_slow_inc(&apic_sw_disabled.key);
 139         }
 140         apic_set_reg(apic, APIC_SPIV, val);
 141 }
 142
 143 static inline int apic_sw_enabled(struct kvm_lapic *apic)
 144 {
 145         if (static_key_false(&apic_sw_disabled.key))
 146                 return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
 147         return APIC_SPIV_APIC_ENABLED;
 148 }
 149
 150 static inline int apic_enabled(struct kvm_lapic *apic)
 151 {
 152         return apic_sw_enabled(apic) && apic_hw_enabled(apic);
 153 }
 154
 155 static inline bool vcpu_has_lapic(struct kvm_vcpu *vcpu)
 156 {
 157         if (static_key_false(&kvm_no_apic_vcpu))
 158                 return vcpu->arch.apic;
 159         return true;
 160 }
 161
 162 #define LVT_MASK        \
 163         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 164
 165 #define LINT_MASK       \
 166         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 167          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 168
 169 static inline int kvm_apic_id(struct kvm_lapic *apic)
 170 {
 171         return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
 172 }
 173
 174 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 175 {
 176         return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 177 }
 178
 179 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 180 {
 181         return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 182 }
 183
 184 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
 185 {
 186         return ((apic_get_reg(apic, APIC_LVTT) &
 187                 apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_ONESHOT);
 188 }
 189
 190 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 191 {
 192         return ((apic_get_reg(apic, APIC_LVTT) &
 193                 apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_PERIODIC);
 194 }
 195
 196 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
 197 {
 198         return ((apic_get_reg(apic, APIC_LVTT) &
 199                 apic->lapic_timer.timer_mode_mask) ==
 200                         APIC_LVT_TIMER_TSCDEADLINE);
 201 }
 202
 203 static inline int apic_lvt_nmi_mode(u32 lvt_val)
 204 {
 205         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
 206 }
 207
 208 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
 209 {
 210         struct kvm_lapic *apic = vcpu->arch.apic;
 211         struct kvm_cpuid_entry2 *feat;
 212         u32 v = APIC_VERSION;
 213
 214         if (!vcpu_has_lapic(vcpu))
 215                 return;
 216
 217         feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
 218         if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
 219                 v |= APIC_LVR_DIRECTED_EOI;
 220         apic_set_reg(apic, APIC_LVR, v);
 221 }
 222
 223 static inline int apic_x2apic_mode(struct kvm_lapic *apic)
 224 {
 225         return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
 226 }
 227
 228 static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
 229         LVT_MASK ,      /* part LVTT mask, timer mode mask added at runtime */
 230         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 231         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 232         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 233         LVT_MASK                /* LVTERR */
 234 };
 235
 236 static int find_highest_vector(void *bitmap)
 237 {
 238         u32 *word = bitmap;
 239         int word_offset = MAX_APIC_VECTOR >> 5;
 240
 241         while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
 242                 continue;
 243
 244         if (likely(!word_offset && !word[0]))
 245                 return -1;
 246         else
 247                 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
 248 }
 249
 250 static u8 count_vectors(void *bitmap)
 251 {
 252         u32 *word = bitmap;
 253         int word_offset;
 254         u8 count = 0;
 255         for (word_offset = 0; word_offset < MAX_APIC_VECTOR >> 5; ++word_offset)
 256                 count += hweight32(word[word_offset << 2]);
 257         return count;
 258 }
 259
 260 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
 261 {
 262         apic->irr_pending = true;
 263         return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
 264 }
 265
 266 static inline int apic_search_irr(struct kvm_lapic *apic)
 267 {
 268         return find_highest_vector(apic->regs + APIC_IRR);
 269 }
 270
 271 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 272 {
 273         int result;
 274
 275         if (!apic->irr_pending)
 276                 return -1;
 277
 278         result = apic_search_irr(apic);
 279         ASSERT(result == -1 || result >= 16);
 280
 281         return result;
 282 }
 283
 284 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 285 {
 286         apic->irr_pending = false;
 287         apic_clear_vector(vec, apic->regs + APIC_IRR);
 288         if (apic_search_irr(apic) != -1)
 289                 apic->irr_pending = true;
 290 }
 291
 292 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
 293 {
 294         if (!__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
 295                 ++apic->isr_count;
 296         BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
 297         /*
 298          * ISR (in service register) bit is set when injecting an interrupt.
 299          * The highest vector is injected. Thus the latest bit set matches
 300          * the highest bit in ISR.
 301          */
 302         apic->highest_isr_cache = vec;
 303 }
 304
 305 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
 306 {
 307         if (__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
 308                 --apic->isr_count;
 309         BUG_ON(apic->isr_count < 0);
 310         apic->highest_isr_cache = -1;
 311 }
 312
 313 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 314 {
 315         int highest_irr;
 316
 317         /* This may race with setting of irr in __apic_accept_irq() and
 318          * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
 319          * will cause vmexit immediately and the value will be recalculated
 320          * on the next vmentry.
 321          */
 322         if (!vcpu_has_lapic(vcpu))
 323                 return 0;
 324         highest_irr = apic_find_highest_irr(vcpu->arch.apic);
 325
 326         return highest_irr;
 327 }
 328
 329 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 330                              int vector, int level, int trig_mode);
 331
 332 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq)
 333 {
 334         struct kvm_lapic *apic = vcpu->arch.apic;
 335
 336         return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
 337                         irq->level, irq->trig_mode);
 338 }
 339
 340 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
 341 {
 342
 343         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
 344                                       sizeof(val));
 345 }
 346
 347 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
 348 {
 349
 350         return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
 351                                       sizeof(*val));
 352 }
 353
 354 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
 355 {
 356         return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
 357 }
 358
 359 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
 360 {
 361         u8 val;
 362         if (pv_eoi_get_user(vcpu, &val) < 0)
 363                 apic_debug("Can't read EOI MSR value: 0x%llx\n",
 364                            (unsigned long long)vcpi->arch.pv_eoi.msr_val);
 365         return val & 0x1;
 366 }
 367
 368 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
 369 {
 370         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
 371                 apic_debug("Can't set EOI MSR value: 0x%llx\n",
 372                            (unsigned long long)vcpi->arch.pv_eoi.msr_val);
 373                 return;
 374         }
 375         __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 376 }
 377
 378 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
 379 {
 380         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
 381                 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
 382                            (unsigned long long)vcpi->arch.pv_eoi.msr_val);
 383                 return;
 384         }
 385         __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 386 }
 387
 388 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 389 {
 390         int result;
 391         if (!apic->isr_count)
 392                 return -1;
 393         if (likely(apic->highest_isr_cache != -1))
 394                 return apic->highest_isr_cache;
 395
 396         result = find_highest_vector(apic->regs + APIC_ISR);
 397         ASSERT(result == -1 || result >= 16);
 398
 399         return result;
 400 }
 401
 402 static void apic_update_ppr(struct kvm_lapic *apic)
 403 {
 404         u32 tpr, isrv, ppr, old_ppr;
 405         int isr;
 406
 407         old_ppr = apic_get_reg(apic, APIC_PROCPRI);
 408         tpr = apic_get_reg(apic, APIC_TASKPRI);
 409         isr = apic_find_highest_isr(apic);
 410         isrv = (isr != -1) ? isr : 0;
 411
 412         if ((tpr & 0xf0) >= (isrv & 0xf0))
 413                 ppr = tpr & 0xff;
 414         else
 415                 ppr = isrv & 0xf0;
 416
 417         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
 418                    apic, ppr, isr, isrv);
 419
 420         if (old_ppr != ppr) {
 421                 apic_set_reg(apic, APIC_PROCPRI, ppr);
 422                 if (ppr < old_ppr)
 423                         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 424         }
 425 }
 426
 427 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 428 {
 429         apic_set_reg(apic, APIC_TASKPRI, tpr);
 430         apic_update_ppr(apic);
 431 }
 432
 433 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
 434 {
 435         return dest == 0xff || kvm_apic_id(apic) == dest;
 436 }
 437
 438 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
 439 {
 440         int result = 0;
 441         u32 logical_id;
 442
 443         if (apic_x2apic_mode(apic)) {
 444                 logical_id = apic_get_reg(apic, APIC_LDR);
 445                 return logical_id & mda;
 446         }
 447
 448         logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
 449
 450         switch (apic_get_reg(apic, APIC_DFR)) {
 451         case APIC_DFR_FLAT:
 452                 if (logical_id & mda)
 453                         result = 1;
 454                 break;
 455         case APIC_DFR_CLUSTER:
 456                 if (((logical_id >> 4) == (mda >> 0x4))
 457                     && (logical_id & mda & 0xf))
 458                         result = 1;
 459                 break;
 460         default:
 461                 apic_debug("Bad DFR vcpu %d: %08x\n",
 462                            apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
 463                 break;
 464         }
 465
 466         return result;
 467 }
 468
 469 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 470                            int short_hand, int dest, int dest_mode)
 471 {
 472         int result = 0;
 473         struct kvm_lapic *target = vcpu->arch.apic;
 474
 475         apic_debug("target %p, source %p, dest 0x%x, "
 476                    "dest_mode 0x%x, short_hand 0x%x\n",
 477                    target, source, dest, dest_mode, short_hand);
 478
 479         ASSERT(target);
 480         switch (short_hand) {
 481         case APIC_DEST_NOSHORT:
 482                 if (dest_mode == 0)
 483                         /* Physical mode. */
 484                         result = kvm_apic_match_physical_addr(target, dest);
 485                 else
 486                         /* Logical mode. */
 487                         result = kvm_apic_match_logical_addr(target, dest);
 488                 break;
 489         case APIC_DEST_SELF:
 490                 result = (target == source);
 491                 break;
 492         case APIC_DEST_ALLINC:
 493                 result = 1;
 494                 break;
 495         case APIC_DEST_ALLBUT:
 496                 result = (target != source);
 497                 break;
 498         default:
 499                 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
 500                            short_hand);
 501                 break;
 502         }
 503
 504         return result;
 505 }
 506
 507 /*
 508  * Add a pending IRQ into lapic.
 509  * Return 1 if successfully added and 0 if discarded.
 510  */
 511 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 512                              int vector, int level, int trig_mode)
 513 {
 514         int result = 0;
 515         struct kvm_vcpu *vcpu = apic->vcpu;
 516
 517         switch (delivery_mode) {
 518         case APIC_DM_LOWEST:
 519                 vcpu->arch.apic_arb_prio++;
 520         case APIC_DM_FIXED:
 521                 /* FIXME add logic for vcpu on reset */
 522                 if (unlikely(!apic_enabled(apic)))
 523                         break;
 524
 525                 if (trig_mode) {
 526                         apic_debug("level trig mode for vector %d", vector);
 527                         apic_set_vector(vector, apic->regs + APIC_TMR);
 528                 } else
 529                         apic_clear_vector(vector, apic->regs + APIC_TMR);
 530
 531                 result = !apic_test_and_set_irr(vector, apic);
 532                 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
 533                                           trig_mode, vector, !result);
 534                 if (!result) {
 535                         if (trig_mode)
 536                                 apic_debug("level trig mode repeatedly for "
 537                                                 "vector %d", vector);
 538                         break;
 539                 }
 540
 541                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 542                 kvm_vcpu_kick(vcpu);
 543                 break;
 544
 545         case APIC_DM_REMRD:
 546                 apic_debug("Ignoring delivery mode 3\n");
 547                 break;
 548
 549         case APIC_DM_SMI:
 550                 apic_debug("Ignoring guest SMI\n");
 551                 break;
 552
 553         case APIC_DM_NMI:
 554                 result = 1;
 555                 kvm_inject_nmi(vcpu);
 556                 kvm_vcpu_kick(vcpu);
 557                 break;
 558
 559         case APIC_DM_INIT:
 560                 if (!trig_mode || level) {
 561                         result = 1;
 562                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
 563                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 564                         kvm_vcpu_kick(vcpu);
 565                 } else {
 566                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
 567                                    vcpu->vcpu_id);
 568                 }
 569                 break;
 570
 571         case APIC_DM_STARTUP:
 572                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
 573                            vcpu->vcpu_id, vector);
 574                 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
 575                         result = 1;
 576                         vcpu->arch.sipi_vector = vector;
 577                         vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
 578                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 579                         kvm_vcpu_kick(vcpu);
 580                 }
 581                 break;
 582
 583         case APIC_DM_EXTINT:
 584                 /*
 585                  * Should only be called by kvm_apic_local_deliver() with LVT0,
 586                  * before NMI watchdog was enabled. Already handled by
 587                  * kvm_apic_accept_pic_intr().
 588                  */
 589                 break;
 590
 591         default:
 592                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
 593                        delivery_mode);
 594                 break;
 595         }
 596         return result;
 597 }
 598
 599 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
 600 {
 601         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
 602 }
 603
 604 static int apic_set_eoi(struct kvm_lapic *apic)
 605 {
 606         int vector = apic_find_highest_isr(apic);
 607
 608         trace_kvm_eoi(apic, vector);
 609
 610         /*
 611          * Not every write EOI will has corresponding ISR,
 612          * one example is when Kernel check timer on setup_IO_APIC
 613          */
 614         if (vector == -1)
 615                 return vector;
 616
 617         apic_clear_isr(vector, apic);
 618         apic_update_ppr(apic);
 619
 620         if (!(apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) &&
 621             kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
 622                 int trigger_mode;
 623                 if (apic_test_vector(vector, apic->regs + APIC_TMR))
 624                         trigger_mode = IOAPIC_LEVEL_TRIG;
 625                 else
 626                         trigger_mode = IOAPIC_EDGE_TRIG;
 627                 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
 628         }
 629         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 630         return vector;
 631 }
 632
 633 static void apic_send_ipi(struct kvm_lapic *apic)
 634 {
 635         u32 icr_low = apic_get_reg(apic, APIC_ICR);
 636         u32 icr_high = apic_get_reg(apic, APIC_ICR2);
 637         struct kvm_lapic_irq irq;
 638
 639         irq.vector = icr_low & APIC_VECTOR_MASK;
 640         irq.delivery_mode = icr_low & APIC_MODE_MASK;
 641         irq.dest_mode = icr_low & APIC_DEST_MASK;
 642         irq.level = icr_low & APIC_INT_ASSERT;
 643         irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
 644         irq.shorthand = icr_low & APIC_SHORT_MASK;
 645         if (apic_x2apic_mode(apic))
 646                 irq.dest_id = icr_high;
 647         else
 648                 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
 649
 650         trace_kvm_apic_ipi(icr_low, irq.dest_id);
 651
 652         apic_debug("icr_high 0x%x, icr_low 0x%x, "
 653                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
 654                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
 655                    icr_high, icr_low, irq.shorthand, irq.dest_id,
 656                    irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
 657                    irq.vector);
 658
 659         kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq);
 660 }
 661
 662 static u32 apic_get_tmcct(struct kvm_lapic *apic)
 663 {
 664         ktime_t remaining;
 665         s64 ns;
 666         u32 tmcct;
 667
 668         ASSERT(apic != NULL);
 669
 670         /* if initial count is 0, current count should also be 0 */
 671         if (apic_get_reg(apic, APIC_TMICT) == 0)
 672                 return 0;
 673
 674         remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
 675         if (ktime_to_ns(remaining) < 0)
 676                 remaining = ktime_set(0, 0);
 677
 678         ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
 679         tmcct = div64_u64(ns,
 680                          (APIC_BUS_CYCLE_NS * apic->divide_count));
 681
 682         return tmcct;
 683 }
 684
 685 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
 686 {
 687         struct kvm_vcpu *vcpu = apic->vcpu;
 688         struct kvm_run *run = vcpu->run;
 689
 690         kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
 691         run->tpr_access.rip = kvm_rip_read(vcpu);
 692         run->tpr_access.is_write = write;
 693 }
 694
 695 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
 696 {
 697         if (apic->vcpu->arch.tpr_access_reporting)
 698                 __report_tpr_access(apic, write);
 699 }
 700
 701 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
 702 {
 703         u32 val = 0;
 704
 705         if (offset >= LAPIC_MMIO_LENGTH)
 706                 return 0;
 707
 708         switch (offset) {
 709         case APIC_ID:
 710                 if (apic_x2apic_mode(apic))
 711                         val = kvm_apic_id(apic);
 712                 else
 713                         val = kvm_apic_id(apic) << 24;
 714                 break;
 715         case APIC_ARBPRI:
 716                 apic_debug("Access APIC ARBPRI register which is for P6\n");
 717                 break;
 718
 719         case APIC_TMCCT:        /* Timer CCR */
 720                 if (apic_lvtt_tscdeadline(apic))
 721                         return 0;
 722
 723                 val = apic_get_tmcct(apic);
 724                 break;
 725         case APIC_PROCPRI:
 726                 apic_update_ppr(apic);
 727                 val = apic_get_reg(apic, offset);
 728                 break;
 729         case APIC_TASKPRI:
 730                 report_tpr_access(apic, false);
 731                 /* fall thru */
 732         default:
 733                 val = apic_get_reg(apic, offset);
 734                 break;
 735         }
 736
 737         return val;
 738 }
 739
 740 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
 741 {
 742         return container_of(dev, struct kvm_lapic, dev);
 743 }
 744
 745 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
 746                 void *data)
 747 {
 748         unsigned char alignment = offset & 0xf;
 749         u32 result;
 750         /* this bitmask has a bit cleared for each reserved register */
 751         static const u64 rmask = 0x43ff01ffffffe70cULL;
 752
 753         if ((alignment + len) > 4) {
 754                 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
 755                            offset, len);
 756                 return 1;
 757         }
 758
 759         if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
 760                 apic_debug("KVM_APIC_READ: read reserved register %x\n",
 761                            offset);
 762                 return 1;
 763         }
 764
 765         result = __apic_read(apic, offset & ~0xf);
 766
 767         trace_kvm_apic_read(offset, result);
 768
 769         switch (len) {
 770         case 1:
 771         case 2:
 772         case 4:
 773                 memcpy(data, (char *)&result + alignment, len);
 774                 break;
 775         default:
 776                 printk(KERN_ERR "Local APIC read with len = %x, "
 777                        "should be 1,2, or 4 instead\n", len);
 778                 break;
 779         }
 780         return 0;
 781 }
 782
 783 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
 784 {
 785         return apic_hw_enabled(apic) &&
 786             addr >= apic->base_address &&
 787             addr < apic->base_address + LAPIC_MMIO_LENGTH;
 788 }
 789
 790 static int apic_mmio_read(struct kvm_io_device *this,
 791                            gpa_t address, int len, void *data)
 792 {
 793         struct kvm_lapic *apic = to_lapic(this);
 794         u32 offset = address - apic->base_address;
 795
 796         if (!apic_mmio_in_range(apic, address))
 797                 return -EOPNOTSUPP;
 798
 799         apic_reg_read(apic, offset, len, data);
 800
 801         return 0;
 802 }
 803
 804 static void update_divide_count(struct kvm_lapic *apic)
 805 {
 806         u32 tmp1, tmp2, tdcr;
 807
 808         tdcr = apic_get_reg(apic, APIC_TDCR);
 809         tmp1 = tdcr & 0xf;
 810         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
 811         apic->divide_count = 0x1 << (tmp2 & 0x7);
 812
 813         apic_debug("timer divide count is 0x%x\n",
 814                                    apic->divide_count);
 815 }
 816
 817 static void start_apic_timer(struct kvm_lapic *apic)
 818 {
 819         ktime_t now;
 820         atomic_set(&apic->lapic_timer.pending, 0);
 821
 822         if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
 823                 /* lapic timer in oneshot or periodic mode */
 824                 now = apic->lapic_timer.timer.base->get_time();
 825                 apic->lapic_timer.period = (u64)apic_get_reg(apic, APIC_TMICT)
 826                             * APIC_BUS_CYCLE_NS * apic->divide_count;
 827
 828                 if (!apic->lapic_timer.period)
 829                         return;
 830                 /*
 831                  * Do not allow the guest to program periodic timers with small
 832                  * interval, since the hrtimers are not throttled by the host
 833                  * scheduler.
 834                  */
 835                 if (apic_lvtt_period(apic)) {
 836                         s64 min_period = min_timer_period_us * 1000LL;
 837
 838                         if (apic->lapic_timer.period < min_period) {
 839                                 pr_info_ratelimited(
 840                                     "kvm: vcpu %i: requested %lld ns "
 841                                     "lapic timer period limited to %lld ns\n",
 842                                     apic->vcpu->vcpu_id,
 843                                     apic->lapic_timer.period, min_period);
 844                                 apic->lapic_timer.period = min_period;
 845                         }
 846                 }
 847
 848                 hrtimer_start(&apic->lapic_timer.timer,
 849                               ktime_add_ns(now, apic->lapic_timer.period),
 850                               HRTIMER_MODE_ABS);
 851
 852                 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
 853                            PRIx64 ", "
 854                            "timer initial count 0x%x, period %lldns, "
 855                            "expire @ 0x%016" PRIx64 ".\n", __func__,
 856                            APIC_BUS_CYCLE_NS, ktime_to_ns(now),
 857                            apic_get_reg(apic, APIC_TMICT),
 858                            apic->lapic_timer.period,
 859                            ktime_to_ns(ktime_add_ns(now,
 860                                         apic->lapic_timer.period)));
 861         } else if (apic_lvtt_tscdeadline(apic)) {
 862                 /* lapic timer in tsc deadline mode */
 863                 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
 864                 u64 ns = 0;
 865                 struct kvm_vcpu *vcpu = apic->vcpu;
 866                 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
 867                 unsigned long flags;
 868
 869                 if (unlikely(!tscdeadline || !this_tsc_khz))
 870                         return;
 871
 872                 local_irq_save(flags);
 873
 874                 now = apic->lapic_timer.timer.base->get_time();
 875                 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
 876                 if (likely(tscdeadline > guest_tsc)) {
 877                         ns = (tscdeadline - guest_tsc) * 1000000ULL;
 878                         do_div(ns, this_tsc_khz);
 879                 }
 880                 hrtimer_start(&apic->lapic_timer.timer,
 881                         ktime_add_ns(now, ns), HRTIMER_MODE_ABS);
 882
 883                 local_irq_restore(flags);
 884         }
 885 }
 886
 887 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
 888 {
 889         int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0));
 890
 891         if (apic_lvt_nmi_mode(lvt0_val)) {
 892                 if (!nmi_wd_enabled) {
 893                         apic_debug("Receive NMI setting on APIC_LVT0 "
 894                                    "for cpu %d\n", apic->vcpu->vcpu_id);
 895                         apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
 896                 }
 897         } else if (nmi_wd_enabled)
 898                 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
 899 }
 900
 901 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
 902 {
 903         int ret = 0;
 904
 905         trace_kvm_apic_write(reg, val);
 906
 907         switch (reg) {
 908         case APIC_ID:           /* Local APIC ID */
 909                 if (!apic_x2apic_mode(apic))
 910                         apic_set_reg(apic, APIC_ID, val);
 911                 else
 912                         ret = 1;
 913                 break;
 914
 915         case APIC_TASKPRI:
 916                 report_tpr_access(apic, true);
 917                 apic_set_tpr(apic, val & 0xff);
 918                 break;
 919
 920         case APIC_EOI:
 921                 apic_set_eoi(apic);
 922                 break;
 923
 924         case APIC_LDR:
 925                 if (!apic_x2apic_mode(apic))
 926                         apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
 927                 else
 928                         ret = 1;
 929                 break;
 930
 931         case APIC_DFR:
 932                 if (!apic_x2apic_mode(apic))
 933                         apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
 934                 else
 935                         ret = 1;
 936                 break;
 937
 938         case APIC_SPIV: {
 939                 u32 mask = 0x3ff;
 940                 if (apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
 941                         mask |= APIC_SPIV_DIRECTED_EOI;
 942                 apic_set_spiv(apic, val & mask);
 943                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
 944                         int i;
 945                         u32 lvt_val;
 946
 947                         for (i = 0; i < APIC_LVT_NUM; i++) {
 948                                 lvt_val = apic_get_reg(apic,
 949                                                        APIC_LVTT + 0x10 * i);
 950                                 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
 951                                              lvt_val | APIC_LVT_MASKED);
 952                         }
 953                         atomic_set(&apic->lapic_timer.pending, 0);
 954
 955                 }
 956                 break;
 957         }
 958         case APIC_ICR:
 959                 /* No delay here, so we always clear the pending bit */
 960                 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
 961                 apic_send_ipi(apic);
 962                 break;
 963
 964         case APIC_ICR2:
 965                 if (!apic_x2apic_mode(apic))
 966                         val &= 0xff000000;
 967                 apic_set_reg(apic, APIC_ICR2, val);
 968                 break;
 969
 970         case APIC_LVT0:
 971                 apic_manage_nmi_watchdog(apic, val);
 972         case APIC_LVTTHMR:
 973         case APIC_LVTPC:
 974         case APIC_LVT1:
 975         case APIC_LVTERR:
 976                 /* TODO: Check vector */
 977                 if (!apic_sw_enabled(apic))
 978                         val |= APIC_LVT_MASKED;
 979
 980                 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
 981                 apic_set_reg(apic, reg, val);
 982
 983                 break;
 984
 985         case APIC_LVTT:
 986                 if ((apic_get_reg(apic, APIC_LVTT) &
 987                     apic->lapic_timer.timer_mode_mask) !=
 988                    (val & apic->lapic_timer.timer_mode_mask))
 989                         hrtimer_cancel(&apic->lapic_timer.timer);
 990
 991                 if (!apic_sw_enabled(apic))
 992                         val |= APIC_LVT_MASKED;
 993                 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
 994                 apic_set_reg(apic, APIC_LVTT, val);
 995                 break;
 996
 997         case APIC_TMICT:
 998                 if (apic_lvtt_tscdeadline(apic))
 999                         break;
1000
1001                 hrtimer_cancel(&apic->lapic_timer.timer);
1002                 apic_set_reg(apic, APIC_TMICT, val);
1003                 start_apic_timer(apic);
1004                 break;
1005
1006         case APIC_TDCR:
1007                 if (val & 4)
1008                         apic_debug("KVM_WRITE:TDCR %x\n", val);
1009                 apic_set_reg(apic, APIC_TDCR, val);
1010                 update_divide_count(apic);
1011                 break;
1012
1013         case APIC_ESR:
1014                 if (apic_x2apic_mode(apic) && val != 0) {
1015                         apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1016                         ret = 1;
1017                 }
1018                 break;
1019
1020         case APIC_SELF_IPI:
1021                 if (apic_x2apic_mode(apic)) {
1022                         apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1023                 } else
1024                         ret = 1;
1025                 break;
1026         default:
1027                 ret = 1;
1028                 break;
1029         }
1030         if (ret)
1031                 apic_debug("Local APIC Write to read-only register %x\n", reg);
1032         return ret;
1033 }
1034
1035 static int apic_mmio_write(struct kvm_io_device *this,
1036                             gpa_t address, int len, const void *data)
1037 {
1038         struct kvm_lapic *apic = to_lapic(this);
1039         unsigned int offset = address - apic->base_address;
1040         u32 val;
1041
1042         if (!apic_mmio_in_range(apic, address))
1043                 return -EOPNOTSUPP;
1044
1045         /*
1046          * APIC register must be aligned on 128-bits boundary.
1047          * 32/64/128 bits registers must be accessed thru 32 bits.
1048          * Refer SDM 8.4.1
1049          */
1050         if (len != 4 || (offset & 0xf)) {
1051                 /* Don't shout loud, $infamous_os would cause only noise. */
1052                 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1053                 return 0;
1054         }
1055
1056         val = *(u32*)data;
1057
1058         /* too common printing */
1059         if (offset != APIC_EOI)
1060                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1061                            "0x%x\n", __func__, offset, len, val);
1062
1063         apic_reg_write(apic, offset & 0xff0, val);
1064
1065         return 0;
1066 }
1067
1068 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1069 {
1070         if (vcpu_has_lapic(vcpu))
1071                 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1072 }
1073 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1074
1075 void kvm_free_lapic(struct kvm_vcpu *vcpu)
1076 {
1077         struct kvm_lapic *apic = vcpu->arch.apic;
1078
1079         if (!vcpu->arch.apic)
1080                 return;
1081
1082         hrtimer_cancel(&apic->lapic_timer.timer);
1083
1084         if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1085                 static_key_slow_dec_deferred(&apic_hw_disabled);
1086
1087         if (!(apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED))
1088                 static_key_slow_dec_deferred(&apic_sw_disabled);
1089
1090         if (apic->regs)
1091                 free_page((unsigned long)apic->regs);
1092
1093         kfree(apic);
1094 }
1095
1096 /*
1097  *----------------------------------------------------------------------
1098  * LAPIC interface
1099  *----------------------------------------------------------------------
1100  */
1101
1102 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1103 {
1104         struct kvm_lapic *apic = vcpu->arch.apic;
1105
1106         if (!vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1107                         apic_lvtt_period(apic))
1108                 return 0;
1109
1110         return apic->lapic_timer.tscdeadline;
1111 }
1112
1113 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1114 {
1115         struct kvm_lapic *apic = vcpu->arch.apic;
1116
1117         if (!vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1118                         apic_lvtt_period(apic))
1119                 return;
1120
1121         hrtimer_cancel(&apic->lapic_timer.timer);
1122         apic->lapic_timer.tscdeadline = data;
1123         start_apic_timer(apic);
1124 }
1125
1126 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1127 {
1128         struct kvm_lapic *apic = vcpu->arch.apic;
1129
1130         if (!vcpu_has_lapic(vcpu))
1131                 return;
1132
1133         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1134                      | (apic_get_reg(apic, APIC_TASKPRI) & 4));
1135 }
1136
1137 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1138 {
1139         u64 tpr;
1140
1141         if (!vcpu_has_lapic(vcpu))
1142                 return 0;
1143
1144         tpr = (u64) apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
1145
1146         return (tpr & 0xf0) >> 4;
1147 }
1148
1149 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1150 {
1151         struct kvm_lapic *apic = vcpu->arch.apic;
1152
1153         if (!apic) {
1154                 value |= MSR_IA32_APICBASE_BSP;
1155                 vcpu->arch.apic_base = value;
1156                 return;
1157         }
1158
1159         /* update jump label if enable bit changes */
1160         if ((vcpu->arch.apic_base ^ value) & MSR_IA32_APICBASE_ENABLE) {
1161                 if (value & MSR_IA32_APICBASE_ENABLE)
1162                         static_key_slow_dec_deferred(&apic_hw_disabled);
1163                 else
1164                         static_key_slow_inc(&apic_hw_disabled.key);
1165         }
1166
1167         if (!kvm_vcpu_is_bsp(apic->vcpu))
1168                 value &= ~MSR_IA32_APICBASE_BSP;
1169
1170         vcpu->arch.apic_base = value;
1171         if (apic_x2apic_mode(apic)) {
1172                 u32 id = kvm_apic_id(apic);
1173                 u32 ldr = ((id & ~0xf) << 16) | (1 << (id & 0xf));
1174                 apic_set_reg(apic, APIC_LDR, ldr);
1175         }
1176         apic->base_address = apic->vcpu->arch.apic_base &
1177                              MSR_IA32_APICBASE_BASE;
1178
1179         /* with FSB delivery interrupt, we can restart APIC functionality */
1180         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1181                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1182
1183 }
1184
1185 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
1186 {
1187         struct kvm_lapic *apic;
1188         int i;
1189
1190         apic_debug("%s\n", __func__);
1191
1192         ASSERT(vcpu);
1193         apic = vcpu->arch.apic;
1194         ASSERT(apic != NULL);
1195
1196         /* Stop the timer in case it's a reset to an active apic */
1197         hrtimer_cancel(&apic->lapic_timer.timer);
1198
1199         apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
1200         kvm_apic_set_version(apic->vcpu);
1201
1202         for (i = 0; i < APIC_LVT_NUM; i++)
1203                 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1204         apic_set_reg(apic, APIC_LVT0,
1205                      SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1206
1207         apic_set_reg(apic, APIC_DFR, 0xffffffffU);
1208         apic_set_spiv(apic, 0xff);
1209         apic_set_reg(apic, APIC_TASKPRI, 0);
1210         apic_set_reg(apic, APIC_LDR, 0);
1211         apic_set_reg(apic, APIC_ESR, 0);
1212         apic_set_reg(apic, APIC_ICR, 0);
1213         apic_set_reg(apic, APIC_ICR2, 0);
1214         apic_set_reg(apic, APIC_TDCR, 0);
1215         apic_set_reg(apic, APIC_TMICT, 0);
1216         for (i = 0; i < 8; i++) {
1217                 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1218                 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1219                 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1220         }
1221         apic->irr_pending = false;
1222         apic->isr_count = 0;
1223         apic->highest_isr_cache = -1;
1224         update_divide_count(apic);
1225         atomic_set(&apic->lapic_timer.pending, 0);
1226         if (kvm_vcpu_is_bsp(vcpu))
1227                 kvm_lapic_set_base(vcpu,
1228                                 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
1229         vcpu->arch.pv_eoi.msr_val = 0;
1230         apic_update_ppr(apic);
1231
1232         vcpu->arch.apic_arb_prio = 0;
1233         vcpu->arch.apic_attention = 0;
1234
1235         apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
1236                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1237                    vcpu, kvm_apic_id(apic),
1238                    vcpu->arch.apic_base, apic->base_address);
1239 }
1240
1241 bool kvm_apic_present(struct kvm_vcpu *vcpu)
1242 {
1243         return vcpu_has_lapic(vcpu) && apic_hw_enabled(vcpu->arch.apic);
1244 }
1245
1246 int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
1247 {
1248         return kvm_apic_present(vcpu) && apic_sw_enabled(vcpu->arch.apic);
1249 }
1250
1251 /*
1252  *----------------------------------------------------------------------
1253  * timer interface
1254  *----------------------------------------------------------------------
1255  */
1256
1257 static bool lapic_is_periodic(struct kvm_lapic *apic)
1258 {
1259         return apic_lvtt_period(apic);
1260 }
1261
1262 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1263 {
1264         struct kvm_lapic *apic = vcpu->arch.apic;
1265
1266         if (vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
1267                         apic_lvt_enabled(apic, APIC_LVTT))
1268                 return atomic_read(&apic->lapic_timer.pending);
1269
1270         return 0;
1271 }
1272
1273 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1274 {
1275         u32 reg = apic_get_reg(apic, lvt_type);
1276         int vector, mode, trig_mode;
1277
1278         if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1279                 vector = reg & APIC_VECTOR_MASK;
1280                 mode = reg & APIC_MODE_MASK;
1281                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1282                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode);
1283         }
1284         return 0;
1285 }
1286
1287 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1288 {
1289         struct kvm_lapic *apic = vcpu->arch.apic;
1290
1291         if (apic)
1292                 kvm_apic_local_deliver(apic, APIC_LVT0);
1293 }
1294
1295 static const struct kvm_io_device_ops apic_mmio_ops = {
1296         .read     = apic_mmio_read,
1297         .write    = apic_mmio_write,
1298 };
1299
1300 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1301 {
1302         struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
1303         struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
1304         struct kvm_vcpu *vcpu = apic->vcpu;
1305         wait_queue_head_t *q = &vcpu->wq;
1306
1307         /*
1308          * There is a race window between reading and incrementing, but we do
1309          * not care about potentially losing timer events in the !reinject
1310          * case anyway. Note: KVM_REQ_PENDING_TIMER is implicitly checked
1311          * in vcpu_enter_guest.
1312          */
1313         if (!atomic_read(&ktimer->pending)) {
1314                 atomic_inc(&ktimer->pending);
1315                 /* FIXME: this code should not know anything about vcpus */
1316                 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1317         }
1318
1319         if (waitqueue_active(q))
1320                 wake_up_interruptible(q);
1321
1322         if (lapic_is_periodic(apic)) {
1323                 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1324                 return HRTIMER_RESTART;
1325         } else
1326                 return HRTIMER_NORESTART;
1327 }
1328
1329 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1330 {
1331         struct kvm_lapic *apic;
1332
1333         ASSERT(vcpu != NULL);
1334         apic_debug("apic_init %d\n", vcpu->vcpu_id);
1335
1336         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1337         if (!apic)
1338                 goto nomem;
1339
1340         vcpu->arch.apic = apic;
1341
1342         apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1343         if (!apic->regs) {
1344                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1345                        vcpu->vcpu_id);
1346                 goto nomem_free_apic;
1347         }
1348         apic->vcpu = vcpu;
1349
1350         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1351                      HRTIMER_MODE_ABS);
1352         apic->lapic_timer.timer.function = apic_timer_fn;
1353
1354         /*
1355          * APIC is created enabled. This will prevent kvm_lapic_set_base from
1356          * thinking that APIC satet has changed.
1357          */
1358         vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
1359         kvm_lapic_set_base(vcpu,
1360                         APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
1361
1362         static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
1363         kvm_lapic_reset(vcpu);
1364         kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1365
1366         return 0;
1367 nomem_free_apic:
1368         kfree(apic);
1369 nomem:
1370         return -ENOMEM;
1371 }
1372
1373 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1374 {
1375         struct kvm_lapic *apic = vcpu->arch.apic;
1376         int highest_irr;
1377
1378         if (!vcpu_has_lapic(vcpu) || !apic_enabled(apic))
1379                 return -1;
1380
1381         apic_update_ppr(apic);
1382         highest_irr = apic_find_highest_irr(apic);
1383         if ((highest_irr == -1) ||
1384             ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
1385                 return -1;
1386         return highest_irr;
1387 }
1388
1389 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1390 {
1391         u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1392         int r = 0;
1393
1394         if (!apic_hw_enabled(vcpu->arch.apic))
1395                 r = 1;
1396         if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1397             GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1398                 r = 1;
1399         return r;
1400 }
1401
1402 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1403 {
1404         struct kvm_lapic *apic = vcpu->arch.apic;
1405
1406         if (!vcpu_has_lapic(vcpu))
1407                 return;
1408
1409         if (atomic_read(&apic->lapic_timer.pending) > 0) {
1410                 if (kvm_apic_local_deliver(apic, APIC_LVTT))
1411                         atomic_dec(&apic->lapic_timer.pending);
1412         }
1413 }
1414
1415 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1416 {
1417         int vector = kvm_apic_has_interrupt(vcpu);
1418         struct kvm_lapic *apic = vcpu->arch.apic;
1419
1420         if (vector == -1)
1421                 return -1;
1422
1423         apic_set_isr(vector, apic);
1424         apic_update_ppr(apic);
1425         apic_clear_irr(vector, apic);
1426         return vector;
1427 }
1428
1429 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1430 {
1431         struct kvm_lapic *apic = vcpu->arch.apic;
1432
1433         kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
1434         kvm_apic_set_version(vcpu);
1435         apic_set_spiv(apic, apic_get_reg(apic, APIC_SPIV));
1436
1437         apic_update_ppr(apic);
1438         hrtimer_cancel(&apic->lapic_timer.timer);
1439         update_divide_count(apic);
1440         start_apic_timer(apic);
1441         apic->irr_pending = true;
1442         apic->isr_count = count_vectors(apic->regs + APIC_ISR);
1443         apic->highest_isr_cache = -1;
1444         kvm_make_request(KVM_REQ_EVENT, vcpu);
1445 }
1446
1447 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1448 {
1449         struct hrtimer *timer;
1450
1451         if (!vcpu_has_lapic(vcpu))
1452                 return;
1453
1454         timer = &vcpu->arch.apic->lapic_timer.timer;
1455         if (hrtimer_cancel(timer))
1456                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1457 }
1458
1459 /*
1460  * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1461  *
1462  * Detect whether guest triggered PV EOI since the
1463  * last entry. If yes, set EOI on guests's behalf.
1464  * Clear PV EOI in guest memory in any case.
1465  */
1466 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1467                                         struct kvm_lapic *apic)
1468 {
1469         bool pending;
1470         int vector;
1471         /*
1472          * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1473          * and KVM_PV_EOI_ENABLED in guest memory as follows:
1474          *
1475          * KVM_APIC_PV_EOI_PENDING is unset:
1476          *      -> host disabled PV EOI.
1477          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1478          *      -> host enabled PV EOI, guest did not execute EOI yet.
1479          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1480          *      -> host enabled PV EOI, guest executed EOI.
1481          */
1482         BUG_ON(!pv_eoi_enabled(vcpu));
1483         pending = pv_eoi_get_pending(vcpu);
1484         /*
1485          * Clear pending bit in any case: it will be set again on vmentry.
1486          * While this might not be ideal from performance point of view,
1487          * this makes sure pv eoi is only enabled when we know it's safe.
1488          */
1489         pv_eoi_clr_pending(vcpu);
1490         if (pending)
1491                 return;
1492         vector = apic_set_eoi(apic);
1493         trace_kvm_pv_eoi(apic, vector);
1494 }
1495
1496 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1497 {
1498         u32 data;
1499         void *vapic;
1500
1501         if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1502                 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1503
1504         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1505                 return;
1506
1507         vapic = kmap_atomic(vcpu->arch.apic->vapic_page);
1508         data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1509         kunmap_atomic(vapic);
1510
1511         apic_set_tpr(vcpu->arch.apic, data & 0xff);
1512 }
1513
1514 /*
1515  * apic_sync_pv_eoi_to_guest - called before vmentry
1516  *
1517  * Detect whether it's safe to enable PV EOI and
1518  * if yes do so.
1519  */
1520 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
1521                                         struct kvm_lapic *apic)
1522 {
1523         if (!pv_eoi_enabled(vcpu) ||
1524             /* IRR set or many bits in ISR: could be nested. */
1525             apic->irr_pending ||
1526             /* Cache not set: could be safe but we don't bother. */
1527             apic->highest_isr_cache == -1 ||
1528             /* Need EOI to update ioapic. */
1529             kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) {
1530                 /*
1531                  * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1532                  * so we need not do anything here.
1533                  */
1534                 return;
1535         }
1536
1537         pv_eoi_set_pending(apic->vcpu);
1538 }
1539
1540 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1541 {
1542         u32 data, tpr;
1543         int max_irr, max_isr;
1544         struct kvm_lapic *apic = vcpu->arch.apic;
1545         void *vapic;
1546
1547         apic_sync_pv_eoi_to_guest(vcpu, apic);
1548
1549         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1550                 return;
1551
1552         tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1553         max_irr = apic_find_highest_irr(apic);
1554         if (max_irr < 0)
1555                 max_irr = 0;
1556         max_isr = apic_find_highest_isr(apic);
1557         if (max_isr < 0)
1558                 max_isr = 0;
1559         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1560
1561         vapic = kmap_atomic(vcpu->arch.apic->vapic_page);
1562         *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1563         kunmap_atomic(vapic);
1564 }
1565
1566 void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1567 {
1568         vcpu->arch.apic->vapic_addr = vapic_addr;
1569         if (vapic_addr)
1570                 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1571         else
1572                 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1573 }
1574
1575 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1576 {
1577         struct kvm_lapic *apic = vcpu->arch.apic;
1578         u32 reg = (msr - APIC_BASE_MSR) << 4;
1579
1580         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1581                 return 1;
1582
1583         /* if this is ICR write vector before command */
1584         if (msr == 0x830)
1585                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1586         return apic_reg_write(apic, reg, (u32)data);
1587 }
1588
1589 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1590 {
1591         struct kvm_lapic *apic = vcpu->arch.apic;
1592         u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1593
1594         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1595                 return 1;
1596
1597         if (apic_reg_read(apic, reg, 4, &low))
1598                 return 1;
1599         if (msr == 0x830)
1600                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1601
1602         *data = (((u64)high) << 32) | low;
1603
1604         return 0;
1605 }
1606
1607 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1608 {
1609         struct kvm_lapic *apic = vcpu->arch.apic;
1610
1611         if (!vcpu_has_lapic(vcpu))
1612                 return 1;
1613
1614         /* if this is ICR write vector before command */
1615         if (reg == APIC_ICR)
1616                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1617         return apic_reg_write(apic, reg, (u32)data);
1618 }
1619
1620 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
1621 {
1622         struct kvm_lapic *apic = vcpu->arch.apic;
1623         u32 low, high = 0;
1624
1625         if (!vcpu_has_lapic(vcpu))
1626                 return 1;
1627
1628         if (apic_reg_read(apic, reg, 4, &low))
1629                 return 1;
1630         if (reg == APIC_ICR)
1631                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1632
1633         *data = (((u64)high) << 32) | low;
1634
1635         return 0;
1636 }
1637
1638 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
1639 {
1640         u64 addr = data & ~KVM_MSR_ENABLED;
1641         if (!IS_ALIGNED(addr, 4))
1642                 return 1;
1643
1644         vcpu->arch.pv_eoi.msr_val = data;
1645         if (!pv_eoi_enabled(vcpu))
1646                 return 0;
1647         return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
1648                                          addr);
1649 }
1650
1651 void kvm_lapic_init(void)
1652 {
1653         /* do not patch jump label more than once per second */
1654         jump_label_rate_limit(&apic_hw_disabled, HZ);
1655         jump_label_rate_limit(&apic_sw_disabled, HZ);
1656 }