arch/x86/kvm/lapic.c

   1
   2 /*
   3  * Local APIC virtualization
   4  *
   5  * Copyright (C) 2006 Qumranet, Inc.
   6  * Copyright (C) 2007 Novell
   7  * Copyright (C) 2007 Intel
   8  * Copyright 2009 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Dor Laor <dor.laor@qumranet.com>
  12  *   Gregory Haskins <ghaskins@novell.com>
  13  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
  14  *
  15  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  16  *
  17  * This work is licensed under the terms of the GNU GPL, version 2.  See
  18  * the COPYING file in the top-level directory.
  19  */
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/kvm.h>
  23 #include <linux/mm.h>
  24 #include <linux/highmem.h>
  25 #include <linux/smp.h>
  26 #include <linux/hrtimer.h>
  27 #include <linux/io.h>
  28 #include <linux/module.h>
  29 #include <linux/math64.h>
  30 #include <linux/slab.h>
  31 #include <asm/processor.h>
  32 #include <asm/msr.h>
  33 #include <asm/page.h>
  34 #include <asm/current.h>
  35 #include <asm/apicdef.h>
  36 #include <linux/atomic.h>
  37 #include <linux/jump_label.h>
  38 #include "kvm_cache_regs.h"
  39 #include "irq.h"
  40 #include "trace.h"
  41 #include "x86.h"
  42 #include "cpuid.h"
  43
  44 #ifndef CONFIG_X86_64
  45 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
  46 #else
  47 #define mod_64(x, y) ((x) % (y))
  48 #endif
  49
  50 #define PRId64 "d"
  51 #define PRIx64 "llx"
  52 #define PRIu64 "u"
  53 #define PRIo64 "o"
  54
  55 #define APIC_BUS_CYCLE_NS 1
  56
  57 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  58 #define apic_debug(fmt, arg...)
  59
  60 #define APIC_LVT_NUM                    6
  61 /* 14 is the version for Xeon and Pentium 8.4.8*/
  62 #define APIC_VERSION                    (0x14UL | ((APIC_LVT_NUM - 1) << 16))
  63 #define LAPIC_MMIO_LENGTH               (1 << 12)
  64 /* followed define is not in apicdef.h */
  65 #define APIC_SHORT_MASK                 0xc0000
  66 #define APIC_DEST_NOSHORT               0x0
  67 #define APIC_DEST_MASK                  0x800
  68 #define MAX_APIC_VECTOR                 256
  69
  70 #define VEC_POS(v) ((v) & (32 - 1))
  71 #define REG_POS(v) (((v) >> 5) << 4)
  72
  73 static unsigned int min_timer_period_us = 500;
  74 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
  75
  76 static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
  77 {
  78         return *((u32 *) (apic->regs + reg_off));
  79 }
  80
  81 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
  82 {
  83         *((u32 *) (apic->regs + reg_off)) = val;
  84 }
  85
  86 static inline int apic_test_and_set_vector(int vec, void *bitmap)
  87 {
  88         return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  89 }
  90
  91 static inline int apic_test_and_clear_vector(int vec, void *bitmap)
  92 {
  93         return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  94 }
  95
  96 static inline int apic_test_vector(int vec, void *bitmap)
  97 {
  98         return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  99 }
 100
 101 static inline void apic_set_vector(int vec, void *bitmap)
 102 {
 103         set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 104 }
 105
 106 static inline void apic_clear_vector(int vec, void *bitmap)
 107 {
 108         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 109 }
 110
 111 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
 112 {
 113         return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 114 }
 115
 116 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
 117 {
 118         return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 119 }
 120
 121 struct static_key_deferred apic_hw_disabled __read_mostly;
 122
 123 static inline int apic_hw_enabled(struct kvm_lapic *apic)
 124 {
 125         if (static_key_false(&apic_hw_disabled.key))
 126                 return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
 127         return MSR_IA32_APICBASE_ENABLE;
 128 }
 129
 130 static inline int  apic_sw_enabled(struct kvm_lapic *apic)
 131 {
 132         return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
 133 }
 134
 135 static inline int apic_enabled(struct kvm_lapic *apic)
 136 {
 137         return apic_sw_enabled(apic) && apic_hw_enabled(apic);
 138 }
 139
 140 #define LVT_MASK        \
 141         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 142
 143 #define LINT_MASK       \
 144         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 145          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 146
 147 static inline int kvm_apic_id(struct kvm_lapic *apic)
 148 {
 149         return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
 150 }
 151
 152 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 153 {
 154         return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 155 }
 156
 157 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 158 {
 159         return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 160 }
 161
 162 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
 163 {
 164         return ((apic_get_reg(apic, APIC_LVTT) &
 165                 apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_ONESHOT);
 166 }
 167
 168 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 169 {
 170         return ((apic_get_reg(apic, APIC_LVTT) &
 171                 apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_PERIODIC);
 172 }
 173
 174 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
 175 {
 176         return ((apic_get_reg(apic, APIC_LVTT) &
 177                 apic->lapic_timer.timer_mode_mask) ==
 178                         APIC_LVT_TIMER_TSCDEADLINE);
 179 }
 180
 181 static inline int apic_lvt_nmi_mode(u32 lvt_val)
 182 {
 183         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
 184 }
 185
 186 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
 187 {
 188         struct kvm_lapic *apic = vcpu->arch.apic;
 189         struct kvm_cpuid_entry2 *feat;
 190         u32 v = APIC_VERSION;
 191
 192         if (!irqchip_in_kernel(vcpu->kvm))
 193                 return;
 194
 195         feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
 196         if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
 197                 v |= APIC_LVR_DIRECTED_EOI;
 198         apic_set_reg(apic, APIC_LVR, v);
 199 }
 200
 201 static inline int apic_x2apic_mode(struct kvm_lapic *apic)
 202 {
 203         return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
 204 }
 205
 206 static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
 207         LVT_MASK ,      /* part LVTT mask, timer mode mask added at runtime */
 208         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 209         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 210         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 211         LVT_MASK                /* LVTERR */
 212 };
 213
 214 static int find_highest_vector(void *bitmap)
 215 {
 216         u32 *word = bitmap;
 217         int word_offset = MAX_APIC_VECTOR >> 5;
 218
 219         while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
 220                 continue;
 221
 222         if (likely(!word_offset && !word[0]))
 223                 return -1;
 224         else
 225                 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
 226 }
 227
 228 static u8 count_vectors(void *bitmap)
 229 {
 230         u32 *word = bitmap;
 231         int word_offset;
 232         u8 count = 0;
 233         for (word_offset = 0; word_offset < MAX_APIC_VECTOR >> 5; ++word_offset)
 234                 count += hweight32(word[word_offset << 2]);
 235         return count;
 236 }
 237
 238 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
 239 {
 240         apic->irr_pending = true;
 241         return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
 242 }
 243
 244 static inline int apic_search_irr(struct kvm_lapic *apic)
 245 {
 246         return find_highest_vector(apic->regs + APIC_IRR);
 247 }
 248
 249 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 250 {
 251         int result;
 252
 253         if (!apic->irr_pending)
 254                 return -1;
 255
 256         result = apic_search_irr(apic);
 257         ASSERT(result == -1 || result >= 16);
 258
 259         return result;
 260 }
 261
 262 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 263 {
 264         apic->irr_pending = false;
 265         apic_clear_vector(vec, apic->regs + APIC_IRR);
 266         if (apic_search_irr(apic) != -1)
 267                 apic->irr_pending = true;
 268 }
 269
 270 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
 271 {
 272         if (!__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
 273                 ++apic->isr_count;
 274         BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
 275         /*
 276          * ISR (in service register) bit is set when injecting an interrupt.
 277          * The highest vector is injected. Thus the latest bit set matches
 278          * the highest bit in ISR.
 279          */
 280         apic->highest_isr_cache = vec;
 281 }
 282
 283 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
 284 {
 285         if (__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
 286                 --apic->isr_count;
 287         BUG_ON(apic->isr_count < 0);
 288         apic->highest_isr_cache = -1;
 289 }
 290
 291 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 292 {
 293         struct kvm_lapic *apic = vcpu->arch.apic;
 294         int highest_irr;
 295
 296         /* This may race with setting of irr in __apic_accept_irq() and
 297          * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
 298          * will cause vmexit immediately and the value will be recalculated
 299          * on the next vmentry.
 300          */
 301         if (!apic)
 302                 return 0;
 303         highest_irr = apic_find_highest_irr(apic);
 304
 305         return highest_irr;
 306 }
 307
 308 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 309                              int vector, int level, int trig_mode);
 310
 311 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq)
 312 {
 313         struct kvm_lapic *apic = vcpu->arch.apic;
 314
 315         return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
 316                         irq->level, irq->trig_mode);
 317 }
 318
 319 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
 320 {
 321
 322         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
 323                                       sizeof(val));
 324 }
 325
 326 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
 327 {
 328
 329         return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
 330                                       sizeof(*val));
 331 }
 332
 333 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
 334 {
 335         return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
 336 }
 337
 338 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
 339 {
 340         u8 val;
 341         if (pv_eoi_get_user(vcpu, &val) < 0)
 342                 apic_debug("Can't read EOI MSR value: 0x%llx\n",
 343                            (unsigned long long)vcpi->arch.pv_eoi.msr_val);
 344         return val & 0x1;
 345 }
 346
 347 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
 348 {
 349         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
 350                 apic_debug("Can't set EOI MSR value: 0x%llx\n",
 351                            (unsigned long long)vcpi->arch.pv_eoi.msr_val);
 352                 return;
 353         }
 354         __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 355 }
 356
 357 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
 358 {
 359         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
 360                 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
 361                            (unsigned long long)vcpi->arch.pv_eoi.msr_val);
 362                 return;
 363         }
 364         __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 365 }
 366
 367 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 368 {
 369         int result;
 370         if (!apic->isr_count)
 371                 return -1;
 372         if (likely(apic->highest_isr_cache != -1))
 373                 return apic->highest_isr_cache;
 374
 375         result = find_highest_vector(apic->regs + APIC_ISR);
 376         ASSERT(result == -1 || result >= 16);
 377
 378         return result;
 379 }
 380
 381 static void apic_update_ppr(struct kvm_lapic *apic)
 382 {
 383         u32 tpr, isrv, ppr, old_ppr;
 384         int isr;
 385
 386         old_ppr = apic_get_reg(apic, APIC_PROCPRI);
 387         tpr = apic_get_reg(apic, APIC_TASKPRI);
 388         isr = apic_find_highest_isr(apic);
 389         isrv = (isr != -1) ? isr : 0;
 390
 391         if ((tpr & 0xf0) >= (isrv & 0xf0))
 392                 ppr = tpr & 0xff;
 393         else
 394                 ppr = isrv & 0xf0;
 395
 396         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
 397                    apic, ppr, isr, isrv);
 398
 399         if (old_ppr != ppr) {
 400                 apic_set_reg(apic, APIC_PROCPRI, ppr);
 401                 if (ppr < old_ppr)
 402                         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 403         }
 404 }
 405
 406 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 407 {
 408         apic_set_reg(apic, APIC_TASKPRI, tpr);
 409         apic_update_ppr(apic);
 410 }
 411
 412 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
 413 {
 414         return dest == 0xff || kvm_apic_id(apic) == dest;
 415 }
 416
 417 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
 418 {
 419         int result = 0;
 420         u32 logical_id;
 421
 422         if (apic_x2apic_mode(apic)) {
 423                 logical_id = apic_get_reg(apic, APIC_LDR);
 424                 return logical_id & mda;
 425         }
 426
 427         logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
 428
 429         switch (apic_get_reg(apic, APIC_DFR)) {
 430         case APIC_DFR_FLAT:
 431                 if (logical_id & mda)
 432                         result = 1;
 433                 break;
 434         case APIC_DFR_CLUSTER:
 435                 if (((logical_id >> 4) == (mda >> 0x4))
 436                     && (logical_id & mda & 0xf))
 437                         result = 1;
 438                 break;
 439         default:
 440                 apic_debug("Bad DFR vcpu %d: %08x\n",
 441                            apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
 442                 break;
 443         }
 444
 445         return result;
 446 }
 447
 448 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 449                            int short_hand, int dest, int dest_mode)
 450 {
 451         int result = 0;
 452         struct kvm_lapic *target = vcpu->arch.apic;
 453
 454         apic_debug("target %p, source %p, dest 0x%x, "
 455                    "dest_mode 0x%x, short_hand 0x%x\n",
 456                    target, source, dest, dest_mode, short_hand);
 457
 458         ASSERT(target);
 459         switch (short_hand) {
 460         case APIC_DEST_NOSHORT:
 461                 if (dest_mode == 0)
 462                         /* Physical mode. */
 463                         result = kvm_apic_match_physical_addr(target, dest);
 464                 else
 465                         /* Logical mode. */
 466                         result = kvm_apic_match_logical_addr(target, dest);
 467                 break;
 468         case APIC_DEST_SELF:
 469                 result = (target == source);
 470                 break;
 471         case APIC_DEST_ALLINC:
 472                 result = 1;
 473                 break;
 474         case APIC_DEST_ALLBUT:
 475                 result = (target != source);
 476                 break;
 477         default:
 478                 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
 479                            short_hand);
 480                 break;
 481         }
 482
 483         return result;
 484 }
 485
 486 /*
 487  * Add a pending IRQ into lapic.
 488  * Return 1 if successfully added and 0 if discarded.
 489  */
 490 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 491                              int vector, int level, int trig_mode)
 492 {
 493         int result = 0;
 494         struct kvm_vcpu *vcpu = apic->vcpu;
 495
 496         switch (delivery_mode) {
 497         case APIC_DM_LOWEST:
 498                 vcpu->arch.apic_arb_prio++;
 499         case APIC_DM_FIXED:
 500                 /* FIXME add logic for vcpu on reset */
 501                 if (unlikely(!apic_enabled(apic)))
 502                         break;
 503
 504                 if (trig_mode) {
 505                         apic_debug("level trig mode for vector %d", vector);
 506                         apic_set_vector(vector, apic->regs + APIC_TMR);
 507                 } else
 508                         apic_clear_vector(vector, apic->regs + APIC_TMR);
 509
 510                 result = !apic_test_and_set_irr(vector, apic);
 511                 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
 512                                           trig_mode, vector, !result);
 513                 if (!result) {
 514                         if (trig_mode)
 515                                 apic_debug("level trig mode repeatedly for "
 516                                                 "vector %d", vector);
 517                         break;
 518                 }
 519
 520                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 521                 kvm_vcpu_kick(vcpu);
 522                 break;
 523
 524         case APIC_DM_REMRD:
 525                 apic_debug("Ignoring delivery mode 3\n");
 526                 break;
 527
 528         case APIC_DM_SMI:
 529                 apic_debug("Ignoring guest SMI\n");
 530                 break;
 531
 532         case APIC_DM_NMI:
 533                 result = 1;
 534                 kvm_inject_nmi(vcpu);
 535                 kvm_vcpu_kick(vcpu);
 536                 break;
 537
 538         case APIC_DM_INIT:
 539                 if (!trig_mode || level) {
 540                         result = 1;
 541                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
 542                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 543                         kvm_vcpu_kick(vcpu);
 544                 } else {
 545                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
 546                                    vcpu->vcpu_id);
 547                 }
 548                 break;
 549
 550         case APIC_DM_STARTUP:
 551                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
 552                            vcpu->vcpu_id, vector);
 553                 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
 554                         result = 1;
 555                         vcpu->arch.sipi_vector = vector;
 556                         vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
 557                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 558                         kvm_vcpu_kick(vcpu);
 559                 }
 560                 break;
 561
 562         case APIC_DM_EXTINT:
 563                 /*
 564                  * Should only be called by kvm_apic_local_deliver() with LVT0,
 565                  * before NMI watchdog was enabled. Already handled by
 566                  * kvm_apic_accept_pic_intr().
 567                  */
 568                 break;
 569
 570         default:
 571                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
 572                        delivery_mode);
 573                 break;
 574         }
 575         return result;
 576 }
 577
 578 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
 579 {
 580         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
 581 }
 582
 583 static int apic_set_eoi(struct kvm_lapic *apic)
 584 {
 585         int vector = apic_find_highest_isr(apic);
 586
 587         trace_kvm_eoi(apic, vector);
 588
 589         /*
 590          * Not every write EOI will has corresponding ISR,
 591          * one example is when Kernel check timer on setup_IO_APIC
 592          */
 593         if (vector == -1)
 594                 return vector;
 595
 596         apic_clear_isr(vector, apic);
 597         apic_update_ppr(apic);
 598
 599         if (!(apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) &&
 600             kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
 601                 int trigger_mode;
 602                 if (apic_test_vector(vector, apic->regs + APIC_TMR))
 603                         trigger_mode = IOAPIC_LEVEL_TRIG;
 604                 else
 605                         trigger_mode = IOAPIC_EDGE_TRIG;
 606                 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
 607         }
 608         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 609         return vector;
 610 }
 611
 612 static void apic_send_ipi(struct kvm_lapic *apic)
 613 {
 614         u32 icr_low = apic_get_reg(apic, APIC_ICR);
 615         u32 icr_high = apic_get_reg(apic, APIC_ICR2);
 616         struct kvm_lapic_irq irq;
 617
 618         irq.vector = icr_low & APIC_VECTOR_MASK;
 619         irq.delivery_mode = icr_low & APIC_MODE_MASK;
 620         irq.dest_mode = icr_low & APIC_DEST_MASK;
 621         irq.level = icr_low & APIC_INT_ASSERT;
 622         irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
 623         irq.shorthand = icr_low & APIC_SHORT_MASK;
 624         if (apic_x2apic_mode(apic))
 625                 irq.dest_id = icr_high;
 626         else
 627                 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
 628
 629         trace_kvm_apic_ipi(icr_low, irq.dest_id);
 630
 631         apic_debug("icr_high 0x%x, icr_low 0x%x, "
 632                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
 633                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
 634                    icr_high, icr_low, irq.shorthand, irq.dest_id,
 635                    irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
 636                    irq.vector);
 637
 638         kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq);
 639 }
 640
 641 static u32 apic_get_tmcct(struct kvm_lapic *apic)
 642 {
 643         ktime_t remaining;
 644         s64 ns;
 645         u32 tmcct;
 646
 647         ASSERT(apic != NULL);
 648
 649         /* if initial count is 0, current count should also be 0 */
 650         if (apic_get_reg(apic, APIC_TMICT) == 0)
 651                 return 0;
 652
 653         remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
 654         if (ktime_to_ns(remaining) < 0)
 655                 remaining = ktime_set(0, 0);
 656
 657         ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
 658         tmcct = div64_u64(ns,
 659                          (APIC_BUS_CYCLE_NS * apic->divide_count));
 660
 661         return tmcct;
 662 }
 663
 664 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
 665 {
 666         struct kvm_vcpu *vcpu = apic->vcpu;
 667         struct kvm_run *run = vcpu->run;
 668
 669         kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
 670         run->tpr_access.rip = kvm_rip_read(vcpu);
 671         run->tpr_access.is_write = write;
 672 }
 673
 674 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
 675 {
 676         if (apic->vcpu->arch.tpr_access_reporting)
 677                 __report_tpr_access(apic, write);
 678 }
 679
 680 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
 681 {
 682         u32 val = 0;
 683
 684         if (offset >= LAPIC_MMIO_LENGTH)
 685                 return 0;
 686
 687         switch (offset) {
 688         case APIC_ID:
 689                 if (apic_x2apic_mode(apic))
 690                         val = kvm_apic_id(apic);
 691                 else
 692                         val = kvm_apic_id(apic) << 24;
 693                 break;
 694         case APIC_ARBPRI:
 695                 apic_debug("Access APIC ARBPRI register which is for P6\n");
 696                 break;
 697
 698         case APIC_TMCCT:        /* Timer CCR */
 699                 if (apic_lvtt_tscdeadline(apic))
 700                         return 0;
 701
 702                 val = apic_get_tmcct(apic);
 703                 break;
 704         case APIC_PROCPRI:
 705                 apic_update_ppr(apic);
 706                 val = apic_get_reg(apic, offset);
 707                 break;
 708         case APIC_TASKPRI:
 709                 report_tpr_access(apic, false);
 710                 /* fall thru */
 711         default:
 712                 val = apic_get_reg(apic, offset);
 713                 break;
 714         }
 715
 716         return val;
 717 }
 718
 719 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
 720 {
 721         return container_of(dev, struct kvm_lapic, dev);
 722 }
 723
 724 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
 725                 void *data)
 726 {
 727         unsigned char alignment = offset & 0xf;
 728         u32 result;
 729         /* this bitmask has a bit cleared for each reserved register */
 730         static const u64 rmask = 0x43ff01ffffffe70cULL;
 731
 732         if ((alignment + len) > 4) {
 733                 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
 734                            offset, len);
 735                 return 1;
 736         }
 737
 738         if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
 739                 apic_debug("KVM_APIC_READ: read reserved register %x\n",
 740                            offset);
 741                 return 1;
 742         }
 743
 744         result = __apic_read(apic, offset & ~0xf);
 745
 746         trace_kvm_apic_read(offset, result);
 747
 748         switch (len) {
 749         case 1:
 750         case 2:
 751         case 4:
 752                 memcpy(data, (char *)&result + alignment, len);
 753                 break;
 754         default:
 755                 printk(KERN_ERR "Local APIC read with len = %x, "
 756                        "should be 1,2, or 4 instead\n", len);
 757                 break;
 758         }
 759         return 0;
 760 }
 761
 762 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
 763 {
 764         return apic_hw_enabled(apic) &&
 765             addr >= apic->base_address &&
 766             addr < apic->base_address + LAPIC_MMIO_LENGTH;
 767 }
 768
 769 static int apic_mmio_read(struct kvm_io_device *this,
 770                            gpa_t address, int len, void *data)
 771 {
 772         struct kvm_lapic *apic = to_lapic(this);
 773         u32 offset = address - apic->base_address;
 774
 775         if (!apic_mmio_in_range(apic, address))
 776                 return -EOPNOTSUPP;
 777
 778         apic_reg_read(apic, offset, len, data);
 779
 780         return 0;
 781 }
 782
 783 static void update_divide_count(struct kvm_lapic *apic)
 784 {
 785         u32 tmp1, tmp2, tdcr;
 786
 787         tdcr = apic_get_reg(apic, APIC_TDCR);
 788         tmp1 = tdcr & 0xf;
 789         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
 790         apic->divide_count = 0x1 << (tmp2 & 0x7);
 791
 792         apic_debug("timer divide count is 0x%x\n",
 793                                    apic->divide_count);
 794 }
 795
 796 static void start_apic_timer(struct kvm_lapic *apic)
 797 {
 798         ktime_t now;
 799         atomic_set(&apic->lapic_timer.pending, 0);
 800
 801         if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
 802                 /* lapic timer in oneshot or periodic mode */
 803                 now = apic->lapic_timer.timer.base->get_time();
 804                 apic->lapic_timer.period = (u64)apic_get_reg(apic, APIC_TMICT)
 805                             * APIC_BUS_CYCLE_NS * apic->divide_count;
 806
 807                 if (!apic->lapic_timer.period)
 808                         return;
 809                 /*
 810                  * Do not allow the guest to program periodic timers with small
 811                  * interval, since the hrtimers are not throttled by the host
 812                  * scheduler.
 813                  */
 814                 if (apic_lvtt_period(apic)) {
 815                         s64 min_period = min_timer_period_us * 1000LL;
 816
 817                         if (apic->lapic_timer.period < min_period) {
 818                                 pr_info_ratelimited(
 819                                     "kvm: vcpu %i: requested %lld ns "
 820                                     "lapic timer period limited to %lld ns\n",
 821                                     apic->vcpu->vcpu_id,
 822                                     apic->lapic_timer.period, min_period);
 823                                 apic->lapic_timer.period = min_period;
 824                         }
 825                 }
 826
 827                 hrtimer_start(&apic->lapic_timer.timer,
 828                               ktime_add_ns(now, apic->lapic_timer.period),
 829                               HRTIMER_MODE_ABS);
 830
 831                 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
 832                            PRIx64 ", "
 833                            "timer initial count 0x%x, period %lldns, "
 834                            "expire @ 0x%016" PRIx64 ".\n", __func__,
 835                            APIC_BUS_CYCLE_NS, ktime_to_ns(now),
 836                            apic_get_reg(apic, APIC_TMICT),
 837                            apic->lapic_timer.period,
 838                            ktime_to_ns(ktime_add_ns(now,
 839                                         apic->lapic_timer.period)));
 840         } else if (apic_lvtt_tscdeadline(apic)) {
 841                 /* lapic timer in tsc deadline mode */
 842                 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
 843                 u64 ns = 0;
 844                 struct kvm_vcpu *vcpu = apic->vcpu;
 845                 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
 846                 unsigned long flags;
 847
 848                 if (unlikely(!tscdeadline || !this_tsc_khz))
 849                         return;
 850
 851                 local_irq_save(flags);
 852
 853                 now = apic->lapic_timer.timer.base->get_time();
 854                 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
 855                 if (likely(tscdeadline > guest_tsc)) {
 856                         ns = (tscdeadline - guest_tsc) * 1000000ULL;
 857                         do_div(ns, this_tsc_khz);
 858                 }
 859                 hrtimer_start(&apic->lapic_timer.timer,
 860                         ktime_add_ns(now, ns), HRTIMER_MODE_ABS);
 861
 862                 local_irq_restore(flags);
 863         }
 864 }
 865
 866 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
 867 {
 868         int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0));
 869
 870         if (apic_lvt_nmi_mode(lvt0_val)) {
 871                 if (!nmi_wd_enabled) {
 872                         apic_debug("Receive NMI setting on APIC_LVT0 "
 873                                    "for cpu %d\n", apic->vcpu->vcpu_id);
 874                         apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
 875                 }
 876         } else if (nmi_wd_enabled)
 877                 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
 878 }
 879
 880 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
 881 {
 882         int ret = 0;
 883
 884         trace_kvm_apic_write(reg, val);
 885
 886         switch (reg) {
 887         case APIC_ID:           /* Local APIC ID */
 888                 if (!apic_x2apic_mode(apic))
 889                         apic_set_reg(apic, APIC_ID, val);
 890                 else
 891                         ret = 1;
 892                 break;
 893
 894         case APIC_TASKPRI:
 895                 report_tpr_access(apic, true);
 896                 apic_set_tpr(apic, val & 0xff);
 897                 break;
 898
 899         case APIC_EOI:
 900                 apic_set_eoi(apic);
 901                 break;
 902
 903         case APIC_LDR:
 904                 if (!apic_x2apic_mode(apic))
 905                         apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
 906                 else
 907                         ret = 1;
 908                 break;
 909
 910         case APIC_DFR:
 911                 if (!apic_x2apic_mode(apic))
 912                         apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
 913                 else
 914                         ret = 1;
 915                 break;
 916
 917         case APIC_SPIV: {
 918                 u32 mask = 0x3ff;
 919                 if (apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
 920                         mask |= APIC_SPIV_DIRECTED_EOI;
 921                 apic_set_reg(apic, APIC_SPIV, val & mask);
 922                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
 923                         int i;
 924                         u32 lvt_val;
 925
 926                         for (i = 0; i < APIC_LVT_NUM; i++) {
 927                                 lvt_val = apic_get_reg(apic,
 928                                                        APIC_LVTT + 0x10 * i);
 929                                 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
 930                                              lvt_val | APIC_LVT_MASKED);
 931                         }
 932                         atomic_set(&apic->lapic_timer.pending, 0);
 933
 934                 }
 935                 break;
 936         }
 937         case APIC_ICR:
 938                 /* No delay here, so we always clear the pending bit */
 939                 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
 940                 apic_send_ipi(apic);
 941                 break;
 942
 943         case APIC_ICR2:
 944                 if (!apic_x2apic_mode(apic))
 945                         val &= 0xff000000;
 946                 apic_set_reg(apic, APIC_ICR2, val);
 947                 break;
 948
 949         case APIC_LVT0:
 950                 apic_manage_nmi_watchdog(apic, val);
 951         case APIC_LVTTHMR:
 952         case APIC_LVTPC:
 953         case APIC_LVT1:
 954         case APIC_LVTERR:
 955                 /* TODO: Check vector */
 956                 if (!apic_sw_enabled(apic))
 957                         val |= APIC_LVT_MASKED;
 958
 959                 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
 960                 apic_set_reg(apic, reg, val);
 961
 962                 break;
 963
 964         case APIC_LVTT:
 965                 if ((apic_get_reg(apic, APIC_LVTT) &
 966                     apic->lapic_timer.timer_mode_mask) !=
 967                    (val & apic->lapic_timer.timer_mode_mask))
 968                         hrtimer_cancel(&apic->lapic_timer.timer);
 969
 970                 if (!apic_sw_enabled(apic))
 971                         val |= APIC_LVT_MASKED;
 972                 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
 973                 apic_set_reg(apic, APIC_LVTT, val);
 974                 break;
 975
 976         case APIC_TMICT:
 977                 if (apic_lvtt_tscdeadline(apic))
 978                         break;
 979
 980                 hrtimer_cancel(&apic->lapic_timer.timer);
 981                 apic_set_reg(apic, APIC_TMICT, val);
 982                 start_apic_timer(apic);
 983                 break;
 984
 985         case APIC_TDCR:
 986                 if (val & 4)
 987                         apic_debug("KVM_WRITE:TDCR %x\n", val);
 988                 apic_set_reg(apic, APIC_TDCR, val);
 989                 update_divide_count(apic);
 990                 break;
 991
 992         case APIC_ESR:
 993                 if (apic_x2apic_mode(apic) && val != 0) {
 994                         apic_debug("KVM_WRITE:ESR not zero %x\n", val);
 995                         ret = 1;
 996                 }
 997                 break;
 998
 999         case APIC_SELF_IPI:
1000                 if (apic_x2apic_mode(apic)) {
1001                         apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1002                 } else
1003                         ret = 1;
1004                 break;
1005         default:
1006                 ret = 1;
1007                 break;
1008         }
1009         if (ret)
1010                 apic_debug("Local APIC Write to read-only register %x\n", reg);
1011         return ret;
1012 }
1013
1014 static int apic_mmio_write(struct kvm_io_device *this,
1015                             gpa_t address, int len, const void *data)
1016 {
1017         struct kvm_lapic *apic = to_lapic(this);
1018         unsigned int offset = address - apic->base_address;
1019         u32 val;
1020
1021         if (!apic_mmio_in_range(apic, address))
1022                 return -EOPNOTSUPP;
1023
1024         /*
1025          * APIC register must be aligned on 128-bits boundary.
1026          * 32/64/128 bits registers must be accessed thru 32 bits.
1027          * Refer SDM 8.4.1
1028          */
1029         if (len != 4 || (offset & 0xf)) {
1030                 /* Don't shout loud, $infamous_os would cause only noise. */
1031                 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1032                 return 0;
1033         }
1034
1035         val = *(u32*)data;
1036
1037         /* too common printing */
1038         if (offset != APIC_EOI)
1039                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1040                            "0x%x\n", __func__, offset, len, val);
1041
1042         apic_reg_write(apic, offset & 0xff0, val);
1043
1044         return 0;
1045 }
1046
1047 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1048 {
1049         struct kvm_lapic *apic = vcpu->arch.apic;
1050
1051         if (apic)
1052                 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1053 }
1054 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1055
1056 void kvm_free_lapic(struct kvm_vcpu *vcpu)
1057 {
1058         if (!vcpu->arch.apic)
1059                 return;
1060
1061         hrtimer_cancel(&vcpu->arch.apic->lapic_timer.timer);
1062
1063         if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1064                 static_key_slow_dec_deferred(&apic_hw_disabled);
1065
1066         if (vcpu->arch.apic->regs)
1067                 free_page((unsigned long)vcpu->arch.apic->regs);
1068
1069         kfree(vcpu->arch.apic);
1070 }
1071
1072 /*
1073  *----------------------------------------------------------------------
1074  * LAPIC interface
1075  *----------------------------------------------------------------------
1076  */
1077
1078 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1079 {
1080         struct kvm_lapic *apic = vcpu->arch.apic;
1081         if (!apic)
1082                 return 0;
1083
1084         if (apic_lvtt_oneshot(apic) || apic_lvtt_period(apic))
1085                 return 0;
1086
1087         return apic->lapic_timer.tscdeadline;
1088 }
1089
1090 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1091 {
1092         struct kvm_lapic *apic = vcpu->arch.apic;
1093         if (!apic)
1094                 return;
1095
1096         if (apic_lvtt_oneshot(apic) || apic_lvtt_period(apic))
1097                 return;
1098
1099         hrtimer_cancel(&apic->lapic_timer.timer);
1100         apic->lapic_timer.tscdeadline = data;
1101         start_apic_timer(apic);
1102 }
1103
1104 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1105 {
1106         struct kvm_lapic *apic = vcpu->arch.apic;
1107
1108         if (!apic)
1109                 return;
1110         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1111                      | (apic_get_reg(apic, APIC_TASKPRI) & 4));
1112 }
1113
1114 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1115 {
1116         struct kvm_lapic *apic = vcpu->arch.apic;
1117         u64 tpr;
1118
1119         if (!apic)
1120                 return 0;
1121         tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
1122
1123         return (tpr & 0xf0) >> 4;
1124 }
1125
1126 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1127 {
1128         struct kvm_lapic *apic = vcpu->arch.apic;
1129
1130         if (!apic) {
1131                 value |= MSR_IA32_APICBASE_BSP;
1132                 vcpu->arch.apic_base = value;
1133                 return;
1134         }
1135
1136         /* update jump label if enable bit changes */
1137         if ((vcpu->arch.apic_base ^ value) & MSR_IA32_APICBASE_ENABLE) {
1138                 if (value & MSR_IA32_APICBASE_ENABLE)
1139                         static_key_slow_dec_deferred(&apic_hw_disabled);
1140                 else
1141                         static_key_slow_inc(&apic_hw_disabled.key);
1142         }
1143
1144         if (!kvm_vcpu_is_bsp(apic->vcpu))
1145                 value &= ~MSR_IA32_APICBASE_BSP;
1146
1147         vcpu->arch.apic_base = value;
1148         if (apic_x2apic_mode(apic)) {
1149                 u32 id = kvm_apic_id(apic);
1150                 u32 ldr = ((id & ~0xf) << 16) | (1 << (id & 0xf));
1151                 apic_set_reg(apic, APIC_LDR, ldr);
1152         }
1153         apic->base_address = apic->vcpu->arch.apic_base &
1154                              MSR_IA32_APICBASE_BASE;
1155
1156         /* with FSB delivery interrupt, we can restart APIC functionality */
1157         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1158                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1159
1160 }
1161
1162 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
1163 {
1164         struct kvm_lapic *apic;
1165         int i;
1166
1167         apic_debug("%s\n", __func__);
1168
1169         ASSERT(vcpu);
1170         apic = vcpu->arch.apic;
1171         ASSERT(apic != NULL);
1172
1173         /* Stop the timer in case it's a reset to an active apic */
1174         hrtimer_cancel(&apic->lapic_timer.timer);
1175
1176         apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
1177         kvm_apic_set_version(apic->vcpu);
1178
1179         for (i = 0; i < APIC_LVT_NUM; i++)
1180                 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1181         apic_set_reg(apic, APIC_LVT0,
1182                      SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1183
1184         apic_set_reg(apic, APIC_DFR, 0xffffffffU);
1185         apic_set_reg(apic, APIC_SPIV, 0xff);
1186         apic_set_reg(apic, APIC_TASKPRI, 0);
1187         apic_set_reg(apic, APIC_LDR, 0);
1188         apic_set_reg(apic, APIC_ESR, 0);
1189         apic_set_reg(apic, APIC_ICR, 0);
1190         apic_set_reg(apic, APIC_ICR2, 0);
1191         apic_set_reg(apic, APIC_TDCR, 0);
1192         apic_set_reg(apic, APIC_TMICT, 0);
1193         for (i = 0; i < 8; i++) {
1194                 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1195                 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1196                 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1197         }
1198         apic->irr_pending = false;
1199         apic->isr_count = 0;
1200         apic->highest_isr_cache = -1;
1201         update_divide_count(apic);
1202         atomic_set(&apic->lapic_timer.pending, 0);
1203         if (kvm_vcpu_is_bsp(vcpu))
1204                 kvm_lapic_set_base(vcpu,
1205                                 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
1206         vcpu->arch.pv_eoi.msr_val = 0;
1207         apic_update_ppr(apic);
1208
1209         vcpu->arch.apic_arb_prio = 0;
1210         vcpu->arch.apic_attention = 0;
1211
1212         apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
1213                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1214                    vcpu, kvm_apic_id(apic),
1215                    vcpu->arch.apic_base, apic->base_address);
1216 }
1217
1218 bool kvm_apic_present(struct kvm_vcpu *vcpu)
1219 {
1220         return vcpu->arch.apic && apic_hw_enabled(vcpu->arch.apic);
1221 }
1222
1223 int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
1224 {
1225         return kvm_apic_present(vcpu) && apic_sw_enabled(vcpu->arch.apic);
1226 }
1227
1228 /*
1229  *----------------------------------------------------------------------
1230  * timer interface
1231  *----------------------------------------------------------------------
1232  */
1233
1234 static bool lapic_is_periodic(struct kvm_lapic *apic)
1235 {
1236         return apic_lvtt_period(apic);
1237 }
1238
1239 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1240 {
1241         struct kvm_lapic *lapic = vcpu->arch.apic;
1242
1243         if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
1244                 return atomic_read(&lapic->lapic_timer.pending);
1245
1246         return 0;
1247 }
1248
1249 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1250 {
1251         u32 reg = apic_get_reg(apic, lvt_type);
1252         int vector, mode, trig_mode;
1253
1254         if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1255                 vector = reg & APIC_VECTOR_MASK;
1256                 mode = reg & APIC_MODE_MASK;
1257                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1258                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode);
1259         }
1260         return 0;
1261 }
1262
1263 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1264 {
1265         struct kvm_lapic *apic = vcpu->arch.apic;
1266
1267         if (apic)
1268                 kvm_apic_local_deliver(apic, APIC_LVT0);
1269 }
1270
1271 static const struct kvm_io_device_ops apic_mmio_ops = {
1272         .read     = apic_mmio_read,
1273         .write    = apic_mmio_write,
1274 };
1275
1276 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1277 {
1278         struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
1279         struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
1280         struct kvm_vcpu *vcpu = apic->vcpu;
1281         wait_queue_head_t *q = &vcpu->wq;
1282
1283         /*
1284          * There is a race window between reading and incrementing, but we do
1285          * not care about potentially losing timer events in the !reinject
1286          * case anyway. Note: KVM_REQ_PENDING_TIMER is implicitly checked
1287          * in vcpu_enter_guest.
1288          */
1289         if (!atomic_read(&ktimer->pending)) {
1290                 atomic_inc(&ktimer->pending);
1291                 /* FIXME: this code should not know anything about vcpus */
1292                 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1293         }
1294
1295         if (waitqueue_active(q))
1296                 wake_up_interruptible(q);
1297
1298         if (lapic_is_periodic(apic)) {
1299                 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1300                 return HRTIMER_RESTART;
1301         } else
1302                 return HRTIMER_NORESTART;
1303 }
1304
1305 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1306 {
1307         struct kvm_lapic *apic;
1308
1309         ASSERT(vcpu != NULL);
1310         apic_debug("apic_init %d\n", vcpu->vcpu_id);
1311
1312         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1313         if (!apic)
1314                 goto nomem;
1315
1316         vcpu->arch.apic = apic;
1317
1318         apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1319         if (!apic->regs) {
1320                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1321                        vcpu->vcpu_id);
1322                 goto nomem_free_apic;
1323         }
1324         apic->vcpu = vcpu;
1325
1326         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1327                      HRTIMER_MODE_ABS);
1328         apic->lapic_timer.timer.function = apic_timer_fn;
1329
1330         /*
1331          * APIC is created enabled. This will prevent kvm_lapic_set_base from
1332          * thinking that APIC satet has changed.
1333          */
1334         vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
1335         kvm_lapic_set_base(vcpu,
1336                         APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
1337
1338         kvm_lapic_reset(vcpu);
1339         kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1340
1341         return 0;
1342 nomem_free_apic:
1343         kfree(apic);
1344 nomem:
1345         return -ENOMEM;
1346 }
1347
1348 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1349 {
1350         struct kvm_lapic *apic = vcpu->arch.apic;
1351         int highest_irr;
1352
1353         if (!apic || !apic_enabled(apic))
1354                 return -1;
1355
1356         apic_update_ppr(apic);
1357         highest_irr = apic_find_highest_irr(apic);
1358         if ((highest_irr == -1) ||
1359             ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
1360                 return -1;
1361         return highest_irr;
1362 }
1363
1364 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1365 {
1366         u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1367         int r = 0;
1368
1369         if (!apic_hw_enabled(vcpu->arch.apic))
1370                 r = 1;
1371         if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1372             GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1373                 r = 1;
1374         return r;
1375 }
1376
1377 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1378 {
1379         struct kvm_lapic *apic = vcpu->arch.apic;
1380
1381         if (apic && atomic_read(&apic->lapic_timer.pending) > 0) {
1382                 if (kvm_apic_local_deliver(apic, APIC_LVTT))
1383                         atomic_dec(&apic->lapic_timer.pending);
1384         }
1385 }
1386
1387 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1388 {
1389         int vector = kvm_apic_has_interrupt(vcpu);
1390         struct kvm_lapic *apic = vcpu->arch.apic;
1391
1392         if (vector == -1)
1393                 return -1;
1394
1395         apic_set_isr(vector, apic);
1396         apic_update_ppr(apic);
1397         apic_clear_irr(vector, apic);
1398         return vector;
1399 }
1400
1401 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1402 {
1403         struct kvm_lapic *apic = vcpu->arch.apic;
1404
1405         kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
1406         kvm_apic_set_version(vcpu);
1407
1408         apic_update_ppr(apic);
1409         hrtimer_cancel(&apic->lapic_timer.timer);
1410         update_divide_count(apic);
1411         start_apic_timer(apic);
1412         apic->irr_pending = true;
1413         apic->isr_count = count_vectors(apic->regs + APIC_ISR);
1414         apic->highest_isr_cache = -1;
1415         kvm_make_request(KVM_REQ_EVENT, vcpu);
1416 }
1417
1418 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1419 {
1420         struct kvm_lapic *apic = vcpu->arch.apic;
1421         struct hrtimer *timer;
1422
1423         if (!apic)
1424                 return;
1425
1426         timer = &apic->lapic_timer.timer;
1427         if (hrtimer_cancel(timer))
1428                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1429 }
1430
1431 /*
1432  * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1433  *
1434  * Detect whether guest triggered PV EOI since the
1435  * last entry. If yes, set EOI on guests's behalf.
1436  * Clear PV EOI in guest memory in any case.
1437  */
1438 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1439                                         struct kvm_lapic *apic)
1440 {
1441         bool pending;
1442         int vector;
1443         /*
1444          * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1445          * and KVM_PV_EOI_ENABLED in guest memory as follows:
1446          *
1447          * KVM_APIC_PV_EOI_PENDING is unset:
1448          *      -> host disabled PV EOI.
1449          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1450          *      -> host enabled PV EOI, guest did not execute EOI yet.
1451          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1452          *      -> host enabled PV EOI, guest executed EOI.
1453          */
1454         BUG_ON(!pv_eoi_enabled(vcpu));
1455         pending = pv_eoi_get_pending(vcpu);
1456         /*
1457          * Clear pending bit in any case: it will be set again on vmentry.
1458          * While this might not be ideal from performance point of view,
1459          * this makes sure pv eoi is only enabled when we know it's safe.
1460          */
1461         pv_eoi_clr_pending(vcpu);
1462         if (pending)
1463                 return;
1464         vector = apic_set_eoi(apic);
1465         trace_kvm_pv_eoi(apic, vector);
1466 }
1467
1468 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1469 {
1470         u32 data;
1471         void *vapic;
1472
1473         if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1474                 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1475
1476         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1477                 return;
1478
1479         vapic = kmap_atomic(vcpu->arch.apic->vapic_page);
1480         data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1481         kunmap_atomic(vapic);
1482
1483         apic_set_tpr(vcpu->arch.apic, data & 0xff);
1484 }
1485
1486 /*
1487  * apic_sync_pv_eoi_to_guest - called before vmentry
1488  *
1489  * Detect whether it's safe to enable PV EOI and
1490  * if yes do so.
1491  */
1492 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
1493                                         struct kvm_lapic *apic)
1494 {
1495         if (!pv_eoi_enabled(vcpu) ||
1496             /* IRR set or many bits in ISR: could be nested. */
1497             apic->irr_pending ||
1498             /* Cache not set: could be safe but we don't bother. */
1499             apic->highest_isr_cache == -1 ||
1500             /* Need EOI to update ioapic. */
1501             kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) {
1502                 /*
1503                  * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1504                  * so we need not do anything here.
1505                  */
1506                 return;
1507         }
1508
1509         pv_eoi_set_pending(apic->vcpu);
1510 }
1511
1512 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1513 {
1514         u32 data, tpr;
1515         int max_irr, max_isr;
1516         struct kvm_lapic *apic = vcpu->arch.apic;
1517         void *vapic;
1518
1519         apic_sync_pv_eoi_to_guest(vcpu, apic);
1520
1521         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1522                 return;
1523
1524         tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1525         max_irr = apic_find_highest_irr(apic);
1526         if (max_irr < 0)
1527                 max_irr = 0;
1528         max_isr = apic_find_highest_isr(apic);
1529         if (max_isr < 0)
1530                 max_isr = 0;
1531         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1532
1533         vapic = kmap_atomic(vcpu->arch.apic->vapic_page);
1534         *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1535         kunmap_atomic(vapic);
1536 }
1537
1538 void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1539 {
1540         vcpu->arch.apic->vapic_addr = vapic_addr;
1541         if (vapic_addr)
1542                 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1543         else
1544                 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1545 }
1546
1547 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1548 {
1549         struct kvm_lapic *apic = vcpu->arch.apic;
1550         u32 reg = (msr - APIC_BASE_MSR) << 4;
1551
1552         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1553                 return 1;
1554
1555         /* if this is ICR write vector before command */
1556         if (msr == 0x830)
1557                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1558         return apic_reg_write(apic, reg, (u32)data);
1559 }
1560
1561 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1562 {
1563         struct kvm_lapic *apic = vcpu->arch.apic;
1564         u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1565
1566         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1567                 return 1;
1568
1569         if (apic_reg_read(apic, reg, 4, &low))
1570                 return 1;
1571         if (msr == 0x830)
1572                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1573
1574         *data = (((u64)high) << 32) | low;
1575
1576         return 0;
1577 }
1578
1579 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1580 {
1581         struct kvm_lapic *apic = vcpu->arch.apic;
1582
1583         if (!irqchip_in_kernel(vcpu->kvm))
1584                 return 1;
1585
1586         /* if this is ICR write vector before command */
1587         if (reg == APIC_ICR)
1588                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1589         return apic_reg_write(apic, reg, (u32)data);
1590 }
1591
1592 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
1593 {
1594         struct kvm_lapic *apic = vcpu->arch.apic;
1595         u32 low, high = 0;
1596
1597         if (!irqchip_in_kernel(vcpu->kvm))
1598                 return 1;
1599
1600         if (apic_reg_read(apic, reg, 4, &low))
1601                 return 1;
1602         if (reg == APIC_ICR)
1603                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1604
1605         *data = (((u64)high) << 32) | low;
1606
1607         return 0;
1608 }
1609
1610 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
1611 {
1612         u64 addr = data & ~KVM_MSR_ENABLED;
1613         if (!IS_ALIGNED(addr, 4))
1614                 return 1;
1615
1616         vcpu->arch.pv_eoi.msr_val = data;
1617         if (!pv_eoi_enabled(vcpu))
1618                 return 0;
1619         return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
1620                                          addr);
1621 }
1622
1623 void kvm_lapic_init(void)
1624 {
1625         /* do not patch jump label more than once per second */
1626         jump_label_rate_limit(&apic_hw_disabled, HZ);
1627 }