1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
4 * cpuid support routines
6 * derived from arch/x86/kvm/x86.c
8 * Copyright 2011 Red Hat, Inc. and/or its affiliates.
9 * Copyright IBM Corporation, 2008
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13 #include <linux/kvm_host.h>
14 #include "linux/lockdep.h"
15 #include <linux/export.h>
16 #include <linux/vmalloc.h>
17 #include <linux/uaccess.h>
18 #include <linux/sched/stat.h>
20 #include <asm/processor.h>
22 #include <asm/fpu/xstate.h>
24 #include <asm/cpuid.h>
33 * Unlike "struct cpuinfo_x86.x86_capability", kvm_cpu_caps doesn't need to be
34 * aligned to sizeof(unsigned long) because it's not accessed via bitops.
36 u32 kvm_cpu_caps[NR_KVM_CPU_CAPS] __read_mostly;
37 EXPORT_SYMBOL_GPL(kvm_cpu_caps);
39 u32 xstate_required_size(u64 xstate_bv, bool compacted)
42 u32 ret = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
44 xstate_bv &= XFEATURE_MASK_EXTEND;
46 if (xstate_bv & 0x1) {
47 u32 eax, ebx, ecx, edx, offset;
48 cpuid_count(0xD, feature_bit, &eax, &ebx, &ecx, &edx);
49 /* ECX[1]: 64B alignment in compacted form */
51 offset = (ecx & 0x2) ? ALIGN(ret, 64) : ret;
54 ret = max(ret, offset + eax);
66 /* Scattered Flag - For features that are scattered by cpufeatures.h. */
69 BUILD_BUG_ON(X86_FEATURE_##name >= MAX_CPU_FEATURES); \
70 (boot_cpu_has(X86_FEATURE_##name) ? F(name) : 0); \
74 * Magic value used by KVM when querying userspace-provided CPUID entries and
75 * doesn't care about the CPIUD index because the index of the function in
76 * question is not significant. Note, this magic value must have at least one
77 * bit set in bits[63:32] and must be consumed as a u64 by cpuid_entry2_find()
78 * to avoid false positives when processing guest CPUID input.
80 #define KVM_CPUID_INDEX_NOT_SIGNIFICANT -1ull
82 static inline struct kvm_cpuid_entry2 *cpuid_entry2_find(
83 struct kvm_cpuid_entry2 *entries, int nent, u32 function, u64 index)
85 struct kvm_cpuid_entry2 *e;
89 * KVM has a semi-arbitrary rule that querying the guest's CPUID model
90 * with IRQs disabled is disallowed. The CPUID model can legitimately
91 * have over one hundred entries, i.e. the lookup is slow, and IRQs are
92 * typically disabled in KVM only when KVM is in a performance critical
93 * path, e.g. the core VM-Enter/VM-Exit run loop. Nothing will break
94 * if this rule is violated, this assertion is purely to flag potential
95 * performance issues. If this fires, consider moving the lookup out
96 * of the hotpath, e.g. by caching information during CPUID updates.
98 lockdep_assert_irqs_enabled();
100 for (i = 0; i < nent; i++) {
103 if (e->function != function)
107 * If the index isn't significant, use the first entry with a
108 * matching function. It's userspace's responsibilty to not
109 * provide "duplicate" entries in all cases.
111 if (!(e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) || e->index == index)
116 * Similarly, use the first matching entry if KVM is doing a
117 * lookup (as opposed to emulating CPUID) for a function that's
118 * architecturally defined as not having a significant index.
120 if (index == KVM_CPUID_INDEX_NOT_SIGNIFICANT) {
122 * Direct lookups from KVM should not diverge from what
123 * KVM defines internally (the architectural behavior).
125 WARN_ON_ONCE(cpuid_function_is_indexed(function));
133 static int kvm_check_cpuid(struct kvm_vcpu *vcpu,
134 struct kvm_cpuid_entry2 *entries,
137 struct kvm_cpuid_entry2 *best;
141 * The existing code assumes virtual address is 48-bit or 57-bit in the
142 * canonical address checks; exit if it is ever changed.
144 best = cpuid_entry2_find(entries, nent, 0x80000008,
145 KVM_CPUID_INDEX_NOT_SIGNIFICANT);
147 int vaddr_bits = (best->eax & 0xff00) >> 8;
149 if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0)
154 * Exposing dynamic xfeatures to the guest requires additional
155 * enabling in the FPU, e.g. to expand the guest XSAVE state size.
157 best = cpuid_entry2_find(entries, nent, 0xd, 0);
161 xfeatures = best->eax | ((u64)best->edx << 32);
162 xfeatures &= XFEATURE_MASK_USER_DYNAMIC;
166 return fpu_enable_guest_xfd_features(&vcpu->arch.guest_fpu, xfeatures);
169 /* Check whether the supplied CPUID data is equal to what is already set for the vCPU. */
170 static int kvm_cpuid_check_equal(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2,
173 struct kvm_cpuid_entry2 *orig;
176 if (nent != vcpu->arch.cpuid_nent)
179 for (i = 0; i < nent; i++) {
180 orig = &vcpu->arch.cpuid_entries[i];
181 if (e2[i].function != orig->function ||
182 e2[i].index != orig->index ||
183 e2[i].flags != orig->flags ||
184 e2[i].eax != orig->eax || e2[i].ebx != orig->ebx ||
185 e2[i].ecx != orig->ecx || e2[i].edx != orig->edx)
192 static struct kvm_hypervisor_cpuid kvm_get_hypervisor_cpuid(struct kvm_vcpu *vcpu,
195 struct kvm_hypervisor_cpuid cpuid = {};
196 struct kvm_cpuid_entry2 *entry;
199 for_each_possible_hypervisor_cpuid_base(base) {
200 entry = kvm_find_cpuid_entry(vcpu, base);
205 signature[0] = entry->ebx;
206 signature[1] = entry->ecx;
207 signature[2] = entry->edx;
209 if (!memcmp(signature, sig, sizeof(signature))) {
211 cpuid.limit = entry->eax;
220 static struct kvm_cpuid_entry2 *__kvm_find_kvm_cpuid_features(struct kvm_vcpu *vcpu,
221 struct kvm_cpuid_entry2 *entries, int nent)
223 u32 base = vcpu->arch.kvm_cpuid.base;
228 return cpuid_entry2_find(entries, nent, base | KVM_CPUID_FEATURES,
229 KVM_CPUID_INDEX_NOT_SIGNIFICANT);
232 static struct kvm_cpuid_entry2 *kvm_find_kvm_cpuid_features(struct kvm_vcpu *vcpu)
234 return __kvm_find_kvm_cpuid_features(vcpu, vcpu->arch.cpuid_entries,
235 vcpu->arch.cpuid_nent);
238 void kvm_update_pv_runtime(struct kvm_vcpu *vcpu)
240 struct kvm_cpuid_entry2 *best = kvm_find_kvm_cpuid_features(vcpu);
243 * save the feature bitmap to avoid cpuid lookup for every PV
247 vcpu->arch.pv_cpuid.features = best->eax;
251 * Calculate guest's supported XCR0 taking into account guest CPUID data and
252 * KVM's supported XCR0 (comprised of host's XCR0 and KVM_SUPPORTED_XCR0).
254 static u64 cpuid_get_supported_xcr0(struct kvm_cpuid_entry2 *entries, int nent)
256 struct kvm_cpuid_entry2 *best;
258 best = cpuid_entry2_find(entries, nent, 0xd, 0);
262 return (best->eax | ((u64)best->edx << 32)) & kvm_caps.supported_xcr0;
265 static void __kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *entries,
268 struct kvm_cpuid_entry2 *best;
270 best = cpuid_entry2_find(entries, nent, 1, KVM_CPUID_INDEX_NOT_SIGNIFICANT);
272 /* Update OSXSAVE bit */
273 if (boot_cpu_has(X86_FEATURE_XSAVE))
274 cpuid_entry_change(best, X86_FEATURE_OSXSAVE,
275 kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE));
277 cpuid_entry_change(best, X86_FEATURE_APIC,
278 vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE);
281 best = cpuid_entry2_find(entries, nent, 7, 0);
282 if (best && boot_cpu_has(X86_FEATURE_PKU) && best->function == 0x7)
283 cpuid_entry_change(best, X86_FEATURE_OSPKE,
284 kvm_is_cr4_bit_set(vcpu, X86_CR4_PKE));
286 best = cpuid_entry2_find(entries, nent, 0xD, 0);
288 best->ebx = xstate_required_size(vcpu->arch.xcr0, false);
290 best = cpuid_entry2_find(entries, nent, 0xD, 1);
291 if (best && (cpuid_entry_has(best, X86_FEATURE_XSAVES) ||
292 cpuid_entry_has(best, X86_FEATURE_XSAVEC)))
293 best->ebx = xstate_required_size(vcpu->arch.xcr0, true);
295 best = __kvm_find_kvm_cpuid_features(vcpu, entries, nent);
296 if (kvm_hlt_in_guest(vcpu->kvm) && best &&
297 (best->eax & (1 << KVM_FEATURE_PV_UNHALT)))
298 best->eax &= ~(1 << KVM_FEATURE_PV_UNHALT);
300 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT)) {
301 best = cpuid_entry2_find(entries, nent, 0x1, KVM_CPUID_INDEX_NOT_SIGNIFICANT);
303 cpuid_entry_change(best, X86_FEATURE_MWAIT,
304 vcpu->arch.ia32_misc_enable_msr &
305 MSR_IA32_MISC_ENABLE_MWAIT);
309 void kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu)
311 __kvm_update_cpuid_runtime(vcpu, vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent);
313 EXPORT_SYMBOL_GPL(kvm_update_cpuid_runtime);
315 static bool kvm_cpuid_has_hyperv(struct kvm_cpuid_entry2 *entries, int nent)
317 struct kvm_cpuid_entry2 *entry;
319 entry = cpuid_entry2_find(entries, nent, HYPERV_CPUID_INTERFACE,
320 KVM_CPUID_INDEX_NOT_SIGNIFICANT);
321 return entry && entry->eax == HYPERV_CPUID_SIGNATURE_EAX;
324 static void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
326 struct kvm_lapic *apic = vcpu->arch.apic;
327 struct kvm_cpuid_entry2 *best;
330 BUILD_BUG_ON(KVM_NR_GOVERNED_FEATURES > KVM_MAX_NR_GOVERNED_FEATURES);
331 bitmap_zero(vcpu->arch.governed_features.enabled,
332 KVM_MAX_NR_GOVERNED_FEATURES);
335 * If TDP is enabled, let the guest use GBPAGES if they're supported in
336 * hardware. The hardware page walker doesn't let KVM disable GBPAGES,
337 * i.e. won't treat them as reserved, and KVM doesn't redo the GVA->GPA
338 * walk for performance and complexity reasons. Not to mention KVM
339 * _can't_ solve the problem because GVA->GPA walks aren't visible to
340 * KVM once a TDP translation is installed. Mimic hardware behavior so
341 * that KVM's is at least consistent, i.e. doesn't randomly inject #PF.
342 * If TDP is disabled, honor *only* guest CPUID as KVM has full control
343 * and can install smaller shadow pages if the host lacks 1GiB support.
345 allow_gbpages = tdp_enabled ? boot_cpu_has(X86_FEATURE_GBPAGES) :
346 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES);
348 kvm_governed_feature_set(vcpu, X86_FEATURE_GBPAGES);
350 best = kvm_find_cpuid_entry(vcpu, 1);
352 if (cpuid_entry_has(best, X86_FEATURE_TSC_DEADLINE_TIMER))
353 apic->lapic_timer.timer_mode_mask = 3 << 17;
355 apic->lapic_timer.timer_mode_mask = 1 << 17;
357 kvm_apic_set_version(vcpu);
360 vcpu->arch.guest_supported_xcr0 =
361 cpuid_get_supported_xcr0(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent);
363 kvm_update_pv_runtime(vcpu);
365 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
366 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu);
368 kvm_pmu_refresh(vcpu);
369 vcpu->arch.cr4_guest_rsvd_bits =
370 __cr4_reserved_bits(guest_cpuid_has, vcpu);
372 kvm_hv_set_cpuid(vcpu, kvm_cpuid_has_hyperv(vcpu->arch.cpuid_entries,
373 vcpu->arch.cpuid_nent));
375 /* Invoke the vendor callback only after the above state is updated. */
376 static_call(kvm_x86_vcpu_after_set_cpuid)(vcpu);
379 * Except for the MMU, which needs to do its thing any vendor specific
380 * adjustments to the reserved GPA bits.
382 kvm_mmu_after_set_cpuid(vcpu);
385 int cpuid_query_maxphyaddr(struct kvm_vcpu *vcpu)
387 struct kvm_cpuid_entry2 *best;
389 best = kvm_find_cpuid_entry(vcpu, 0x80000000);
390 if (!best || best->eax < 0x80000008)
392 best = kvm_find_cpuid_entry(vcpu, 0x80000008);
394 return best->eax & 0xff;
400 * This "raw" version returns the reserved GPA bits without any adjustments for
401 * encryption technologies that usurp bits. The raw mask should be used if and
402 * only if hardware does _not_ strip the usurped bits, e.g. in virtual MTRRs.
404 u64 kvm_vcpu_reserved_gpa_bits_raw(struct kvm_vcpu *vcpu)
406 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63);
409 static int kvm_set_cpuid(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2,
414 __kvm_update_cpuid_runtime(vcpu, e2, nent);
417 * KVM does not correctly handle changing guest CPUID after KVM_RUN, as
418 * MAXPHYADDR, GBPAGES support, AMD reserved bit behavior, etc.. aren't
419 * tracked in kvm_mmu_page_role. As a result, KVM may miss guest page
420 * faults due to reusing SPs/SPTEs. In practice no sane VMM mucks with
421 * the core vCPU model on the fly. It would've been better to forbid any
422 * KVM_SET_CPUID{,2} calls after KVM_RUN altogether but unfortunately
423 * some VMMs (e.g. QEMU) reuse vCPU fds for CPU hotplug/unplug and do
424 * KVM_SET_CPUID{,2} again. To support this legacy behavior, check
425 * whether the supplied CPUID data is equal to what's already set.
427 if (kvm_vcpu_has_run(vcpu)) {
428 r = kvm_cpuid_check_equal(vcpu, e2, nent);
436 if (kvm_cpuid_has_hyperv(e2, nent)) {
437 r = kvm_hv_vcpu_init(vcpu);
442 r = kvm_check_cpuid(vcpu, e2, nent);
446 kvfree(vcpu->arch.cpuid_entries);
447 vcpu->arch.cpuid_entries = e2;
448 vcpu->arch.cpuid_nent = nent;
450 vcpu->arch.kvm_cpuid = kvm_get_hypervisor_cpuid(vcpu, KVM_SIGNATURE);
451 vcpu->arch.xen.cpuid = kvm_get_hypervisor_cpuid(vcpu, XEN_SIGNATURE);
452 kvm_vcpu_after_set_cpuid(vcpu);
457 /* when an old userspace process fills a new kernel module */
458 int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
459 struct kvm_cpuid *cpuid,
460 struct kvm_cpuid_entry __user *entries)
463 struct kvm_cpuid_entry *e = NULL;
464 struct kvm_cpuid_entry2 *e2 = NULL;
466 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
470 e = vmemdup_user(entries, array_size(sizeof(*e), cpuid->nent));
474 e2 = kvmalloc_array(cpuid->nent, sizeof(*e2), GFP_KERNEL_ACCOUNT);
480 for (i = 0; i < cpuid->nent; i++) {
481 e2[i].function = e[i].function;
482 e2[i].eax = e[i].eax;
483 e2[i].ebx = e[i].ebx;
484 e2[i].ecx = e[i].ecx;
485 e2[i].edx = e[i].edx;
488 e2[i].padding[0] = 0;
489 e2[i].padding[1] = 0;
490 e2[i].padding[2] = 0;
493 r = kvm_set_cpuid(vcpu, e2, cpuid->nent);
503 int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
504 struct kvm_cpuid2 *cpuid,
505 struct kvm_cpuid_entry2 __user *entries)
507 struct kvm_cpuid_entry2 *e2 = NULL;
510 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
514 e2 = vmemdup_user(entries, array_size(sizeof(*e2), cpuid->nent));
519 r = kvm_set_cpuid(vcpu, e2, cpuid->nent);
526 int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
527 struct kvm_cpuid2 *cpuid,
528 struct kvm_cpuid_entry2 __user *entries)
530 if (cpuid->nent < vcpu->arch.cpuid_nent)
533 if (copy_to_user(entries, vcpu->arch.cpuid_entries,
534 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
537 cpuid->nent = vcpu->arch.cpuid_nent;
541 /* Mask kvm_cpu_caps for @leaf with the raw CPUID capabilities of this CPU. */
542 static __always_inline void __kvm_cpu_cap_mask(unsigned int leaf)
544 const struct cpuid_reg cpuid = x86_feature_cpuid(leaf * 32);
545 struct kvm_cpuid_entry2 entry;
547 reverse_cpuid_check(leaf);
549 cpuid_count(cpuid.function, cpuid.index,
550 &entry.eax, &entry.ebx, &entry.ecx, &entry.edx);
552 kvm_cpu_caps[leaf] &= *__cpuid_entry_get_reg(&entry, cpuid.reg);
555 static __always_inline
556 void kvm_cpu_cap_init_kvm_defined(enum kvm_only_cpuid_leafs leaf, u32 mask)
558 /* Use kvm_cpu_cap_mask for leafs that aren't KVM-only. */
559 BUILD_BUG_ON(leaf < NCAPINTS);
561 kvm_cpu_caps[leaf] = mask;
563 __kvm_cpu_cap_mask(leaf);
566 static __always_inline void kvm_cpu_cap_mask(enum cpuid_leafs leaf, u32 mask)
568 /* Use kvm_cpu_cap_init_kvm_defined for KVM-only leafs. */
569 BUILD_BUG_ON(leaf >= NCAPINTS);
571 kvm_cpu_caps[leaf] &= mask;
573 __kvm_cpu_cap_mask(leaf);
576 void kvm_set_cpu_caps(void)
579 unsigned int f_gbpages = F(GBPAGES);
580 unsigned int f_lm = F(LM);
581 unsigned int f_xfd = F(XFD);
583 unsigned int f_gbpages = 0;
584 unsigned int f_lm = 0;
585 unsigned int f_xfd = 0;
587 memset(kvm_cpu_caps, 0, sizeof(kvm_cpu_caps));
589 BUILD_BUG_ON(sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps)) >
590 sizeof(boot_cpu_data.x86_capability));
592 memcpy(&kvm_cpu_caps, &boot_cpu_data.x86_capability,
593 sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps)));
595 kvm_cpu_cap_mask(CPUID_1_ECX,
597 * NOTE: MONITOR (and MWAIT) are emulated as NOP, but *not*
598 * advertised to guests via CPUID!
600 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
601 0 /* DS-CPL, VMX, SMX, EST */ |
602 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
603 F(FMA) | F(CX16) | 0 /* xTPR Update */ | F(PDCM) |
604 F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) |
605 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
606 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
609 /* KVM emulates x2apic in software irrespective of host support. */
610 kvm_cpu_cap_set(X86_FEATURE_X2APIC);
612 kvm_cpu_cap_mask(CPUID_1_EDX,
613 F(FPU) | F(VME) | F(DE) | F(PSE) |
614 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
615 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
616 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
617 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLUSH) |
618 0 /* Reserved, DS, ACPI */ | F(MMX) |
619 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
620 0 /* HTT, TM, Reserved, PBE */
623 kvm_cpu_cap_mask(CPUID_7_0_EBX,
624 F(FSGSBASE) | F(SGX) | F(BMI1) | F(HLE) | F(AVX2) |
625 F(FDP_EXCPTN_ONLY) | F(SMEP) | F(BMI2) | F(ERMS) | F(INVPCID) |
626 F(RTM) | F(ZERO_FCS_FDS) | 0 /*MPX*/ | F(AVX512F) |
627 F(AVX512DQ) | F(RDSEED) | F(ADX) | F(SMAP) | F(AVX512IFMA) |
628 F(CLFLUSHOPT) | F(CLWB) | 0 /*INTEL_PT*/ | F(AVX512PF) |
629 F(AVX512ER) | F(AVX512CD) | F(SHA_NI) | F(AVX512BW) |
632 kvm_cpu_cap_mask(CPUID_7_ECX,
633 F(AVX512VBMI) | F(LA57) | F(PKU) | 0 /*OSPKE*/ | F(RDPID) |
634 F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) |
635 F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) |
636 F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/ |
637 F(SGX_LC) | F(BUS_LOCK_DETECT)
639 /* Set LA57 based on hardware capability. */
640 if (cpuid_ecx(7) & F(LA57))
641 kvm_cpu_cap_set(X86_FEATURE_LA57);
644 * PKU not yet implemented for shadow paging and requires OSPKE
645 * to be set on the host. Clear it if that is not the case
647 if (!tdp_enabled || !boot_cpu_has(X86_FEATURE_OSPKE))
648 kvm_cpu_cap_clear(X86_FEATURE_PKU);
650 kvm_cpu_cap_mask(CPUID_7_EDX,
651 F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) |
652 F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) |
653 F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) |
654 F(SERIALIZE) | F(TSXLDTRK) | F(AVX512_FP16) |
655 F(AMX_TILE) | F(AMX_INT8) | F(AMX_BF16) | F(FLUSH_L1D)
658 /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */
659 kvm_cpu_cap_set(X86_FEATURE_TSC_ADJUST);
660 kvm_cpu_cap_set(X86_FEATURE_ARCH_CAPABILITIES);
662 if (boot_cpu_has(X86_FEATURE_IBPB) && boot_cpu_has(X86_FEATURE_IBRS))
663 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL);
664 if (boot_cpu_has(X86_FEATURE_STIBP))
665 kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP);
666 if (boot_cpu_has(X86_FEATURE_AMD_SSBD))
667 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD);
669 kvm_cpu_cap_mask(CPUID_7_1_EAX,
670 F(AVX_VNNI) | F(AVX512_BF16) | F(CMPCCXADD) |
671 F(FZRM) | F(FSRS) | F(FSRC) |
672 F(AMX_FP16) | F(AVX_IFMA)
675 kvm_cpu_cap_init_kvm_defined(CPUID_7_1_EDX,
676 F(AVX_VNNI_INT8) | F(AVX_NE_CONVERT) | F(PREFETCHITI) |
680 kvm_cpu_cap_mask(CPUID_D_1_EAX,
681 F(XSAVEOPT) | F(XSAVEC) | F(XGETBV1) | F(XSAVES) | f_xfd
684 kvm_cpu_cap_init_kvm_defined(CPUID_12_EAX,
685 SF(SGX1) | SF(SGX2) | SF(SGX_EDECCSSA)
688 kvm_cpu_cap_mask(CPUID_8000_0001_ECX,
689 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
690 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
691 F(3DNOWPREFETCH) | F(OSVW) | 0 /* IBS */ | F(XOP) |
692 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM) |
693 F(TOPOEXT) | 0 /* PERFCTR_CORE */
696 kvm_cpu_cap_mask(CPUID_8000_0001_EDX,
697 F(FPU) | F(VME) | F(DE) | F(PSE) |
698 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
699 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
700 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
701 F(PAT) | F(PSE36) | 0 /* Reserved */ |
702 F(NX) | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
703 F(FXSR) | F(FXSR_OPT) | f_gbpages | F(RDTSCP) |
704 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW)
707 if (!tdp_enabled && IS_ENABLED(CONFIG_X86_64))
708 kvm_cpu_cap_set(X86_FEATURE_GBPAGES);
710 kvm_cpu_cap_init_kvm_defined(CPUID_8000_0007_EDX,
714 kvm_cpu_cap_mask(CPUID_8000_0008_EBX,
715 F(CLZERO) | F(XSAVEERPTR) |
716 F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) |
717 F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) |
722 * AMD has separate bits for each SPEC_CTRL bit.
723 * arch/x86/kernel/cpu/bugs.c is kind enough to
724 * record that in cpufeatures so use them.
726 if (boot_cpu_has(X86_FEATURE_IBPB))
727 kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB);
728 if (boot_cpu_has(X86_FEATURE_IBRS))
729 kvm_cpu_cap_set(X86_FEATURE_AMD_IBRS);
730 if (boot_cpu_has(X86_FEATURE_STIBP))
731 kvm_cpu_cap_set(X86_FEATURE_AMD_STIBP);
732 if (boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD))
733 kvm_cpu_cap_set(X86_FEATURE_AMD_SSBD);
734 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
735 kvm_cpu_cap_set(X86_FEATURE_AMD_SSB_NO);
737 * The preference is to use SPEC CTRL MSR instead of the
740 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
741 !boot_cpu_has(X86_FEATURE_AMD_SSBD))
742 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
745 * Hide all SVM features by default, SVM will set the cap bits for
746 * features it emulates and/or exposes for L1.
748 kvm_cpu_cap_mask(CPUID_8000_000A_EDX, 0);
750 kvm_cpu_cap_mask(CPUID_8000_001F_EAX,
751 0 /* SME */ | F(SEV) | 0 /* VM_PAGE_FLUSH */ | F(SEV_ES) |
754 kvm_cpu_cap_mask(CPUID_8000_0021_EAX,
755 F(NO_NESTED_DATA_BP) | F(LFENCE_RDTSC) | 0 /* SmmPgCfgLock */ |
756 F(NULL_SEL_CLR_BASE) | F(AUTOIBRS) | 0 /* PrefetchCtlMsr */
759 if (cpu_feature_enabled(X86_FEATURE_SRSO_NO))
760 kvm_cpu_cap_set(X86_FEATURE_SRSO_NO);
762 kvm_cpu_cap_init_kvm_defined(CPUID_8000_0022_EAX,
767 * Synthesize "LFENCE is serializing" into the AMD-defined entry in
768 * KVM's supported CPUID if the feature is reported as supported by the
769 * kernel. LFENCE_RDTSC was a Linux-defined synthetic feature long
770 * before AMD joined the bandwagon, e.g. LFENCE is serializing on most
771 * CPUs that support SSE2. On CPUs that don't support AMD's leaf,
772 * kvm_cpu_cap_mask() will unfortunately drop the flag due to ANDing
773 * the mask with the raw host CPUID, and reporting support in AMD's
774 * leaf can make it easier for userspace to detect the feature.
776 if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC))
777 kvm_cpu_cap_set(X86_FEATURE_LFENCE_RDTSC);
778 if (!static_cpu_has_bug(X86_BUG_NULL_SEG))
779 kvm_cpu_cap_set(X86_FEATURE_NULL_SEL_CLR_BASE);
780 kvm_cpu_cap_set(X86_FEATURE_NO_SMM_CTL_MSR);
782 kvm_cpu_cap_mask(CPUID_C000_0001_EDX,
783 F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) |
784 F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) |
789 * Hide RDTSCP and RDPID if either feature is reported as supported but
790 * probing MSR_TSC_AUX failed. This is purely a sanity check and
791 * should never happen, but the guest will likely crash if RDTSCP or
792 * RDPID is misreported, and KVM has botched MSR_TSC_AUX emulation in
793 * the past. For example, the sanity check may fire if this instance of
794 * KVM is running as L1 on top of an older, broken KVM.
796 if (WARN_ON((kvm_cpu_cap_has(X86_FEATURE_RDTSCP) ||
797 kvm_cpu_cap_has(X86_FEATURE_RDPID)) &&
798 !kvm_is_supported_user_return_msr(MSR_TSC_AUX))) {
799 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP);
800 kvm_cpu_cap_clear(X86_FEATURE_RDPID);
803 EXPORT_SYMBOL_GPL(kvm_set_cpu_caps);
805 struct kvm_cpuid_array {
806 struct kvm_cpuid_entry2 *entries;
811 static struct kvm_cpuid_entry2 *get_next_cpuid(struct kvm_cpuid_array *array)
813 if (array->nent >= array->maxnent)
816 return &array->entries[array->nent++];
819 static struct kvm_cpuid_entry2 *do_host_cpuid(struct kvm_cpuid_array *array,
820 u32 function, u32 index)
822 struct kvm_cpuid_entry2 *entry = get_next_cpuid(array);
827 memset(entry, 0, sizeof(*entry));
828 entry->function = function;
829 entry->index = index;
830 switch (function & 0xC0000000) {
832 /* Hypervisor leaves are always synthesized by __do_cpuid_func. */
837 * 0x80000021 is sometimes synthesized by __do_cpuid_func, which
838 * would result in out-of-bounds calls to do_host_cpuid.
841 static int max_cpuid_80000000;
842 if (!READ_ONCE(max_cpuid_80000000))
843 WRITE_ONCE(max_cpuid_80000000, cpuid_eax(0x80000000));
844 if (function > READ_ONCE(max_cpuid_80000000))
853 cpuid_count(entry->function, entry->index,
854 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
856 if (cpuid_function_is_indexed(function))
857 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
862 static int __do_cpuid_func_emulated(struct kvm_cpuid_array *array, u32 func)
864 struct kvm_cpuid_entry2 *entry;
866 if (array->nent >= array->maxnent)
869 entry = &array->entries[array->nent];
870 entry->function = func;
880 entry->ecx = F(MOVBE);
884 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
886 if (kvm_cpu_cap_has(X86_FEATURE_RDTSCP))
887 entry->ecx = F(RDPID);
897 static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
899 struct kvm_cpuid_entry2 *entry;
902 /* all calls to cpuid_count() should be made on the same cpu */
907 entry = do_host_cpuid(array, function, 0);
913 /* Limited to the highest leaf implemented in KVM. */
914 entry->eax = min(entry->eax, 0x1fU);
917 cpuid_entry_override(entry, CPUID_1_EDX);
918 cpuid_entry_override(entry, CPUID_1_ECX);
922 * On ancient CPUs, function 2 entries are STATEFUL. That is,
923 * CPUID(function=2, index=0) may return different results each
924 * time, with the least-significant byte in EAX enumerating the
925 * number of times software should do CPUID(2, 0).
927 * Modern CPUs, i.e. every CPU KVM has *ever* run on are less
928 * idiotic. Intel's SDM states that EAX & 0xff "will always
929 * return 01H. Software should ignore this value and not
930 * interpret it as an informational descriptor", while AMD's
931 * APM states that CPUID(2) is reserved.
933 * WARN if a frankenstein CPU that supports virtualization and
934 * a stateful CPUID.0x2 is encountered.
936 WARN_ON_ONCE((entry->eax & 0xff) > 1);
938 /* functions 4 and 0x8000001d have additional index. */
942 * Read entries until the cache type in the previous entry is
943 * zero, i.e. indicates an invalid entry.
945 for (i = 1; entry->eax & 0x1f; ++i) {
946 entry = do_host_cpuid(array, function, i);
951 case 6: /* Thermal management */
952 entry->eax = 0x4; /* allow ARAT */
957 /* function 7 has additional index. */
959 entry->eax = min(entry->eax, 1u);
960 cpuid_entry_override(entry, CPUID_7_0_EBX);
961 cpuid_entry_override(entry, CPUID_7_ECX);
962 cpuid_entry_override(entry, CPUID_7_EDX);
964 /* KVM only supports 0x7.0 and 0x7.1, capped above via min(). */
965 if (entry->eax == 1) {
966 entry = do_host_cpuid(array, function, 1);
970 cpuid_entry_override(entry, CPUID_7_1_EAX);
971 cpuid_entry_override(entry, CPUID_7_1_EDX);
976 case 0xa: { /* Architectural Performance Monitoring */
977 union cpuid10_eax eax;
978 union cpuid10_edx edx;
980 if (!enable_pmu || !static_cpu_has(X86_FEATURE_ARCH_PERFMON)) {
981 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
985 eax.split.version_id = kvm_pmu_cap.version;
986 eax.split.num_counters = kvm_pmu_cap.num_counters_gp;
987 eax.split.bit_width = kvm_pmu_cap.bit_width_gp;
988 eax.split.mask_length = kvm_pmu_cap.events_mask_len;
989 edx.split.num_counters_fixed = kvm_pmu_cap.num_counters_fixed;
990 edx.split.bit_width_fixed = kvm_pmu_cap.bit_width_fixed;
992 if (kvm_pmu_cap.version)
993 edx.split.anythread_deprecated = 1;
994 edx.split.reserved1 = 0;
995 edx.split.reserved2 = 0;
997 entry->eax = eax.full;
998 entry->ebx = kvm_pmu_cap.events_mask;
1000 entry->edx = edx.full;
1006 * No topology; a valid topology is indicated by the presence
1009 entry->eax = entry->ebx = entry->ecx = 0;
1012 u64 permitted_xcr0 = kvm_get_filtered_xcr0();
1013 u64 permitted_xss = kvm_caps.supported_xss;
1015 entry->eax &= permitted_xcr0;
1016 entry->ebx = xstate_required_size(permitted_xcr0, false);
1017 entry->ecx = entry->ebx;
1018 entry->edx &= permitted_xcr0 >> 32;
1019 if (!permitted_xcr0)
1022 entry = do_host_cpuid(array, function, 1);
1026 cpuid_entry_override(entry, CPUID_D_1_EAX);
1027 if (entry->eax & (F(XSAVES)|F(XSAVEC)))
1028 entry->ebx = xstate_required_size(permitted_xcr0 | permitted_xss,
1031 WARN_ON_ONCE(permitted_xss != 0);
1034 entry->ecx &= permitted_xss;
1035 entry->edx &= permitted_xss >> 32;
1037 for (i = 2; i < 64; ++i) {
1039 if (permitted_xcr0 & BIT_ULL(i))
1041 else if (permitted_xss & BIT_ULL(i))
1046 entry = do_host_cpuid(array, function, i);
1051 * The supported check above should have filtered out
1052 * invalid sub-leafs. Only valid sub-leafs should
1053 * reach this point, and they should have a non-zero
1054 * save state size. Furthermore, check whether the
1055 * processor agrees with permitted_xcr0/permitted_xss
1056 * on whether this is an XCR0- or IA32_XSS-managed area.
1058 if (WARN_ON_ONCE(!entry->eax || (entry->ecx & 0x1) != s_state)) {
1063 if (!kvm_cpu_cap_has(X86_FEATURE_XFD))
1064 entry->ecx &= ~BIT_ULL(2);
1071 if (!kvm_cpu_cap_has(X86_FEATURE_SGX)) {
1072 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1077 * Index 0: Sub-features, MISCSELECT (a.k.a extended features)
1078 * and max enclave sizes. The SGX sub-features and MISCSELECT
1079 * are restricted by kernel and KVM capabilities (like most
1080 * feature flags), while enclave size is unrestricted.
1082 cpuid_entry_override(entry, CPUID_12_EAX);
1083 entry->ebx &= SGX_MISC_EXINFO;
1085 entry = do_host_cpuid(array, function, 1);
1090 * Index 1: SECS.ATTRIBUTES. ATTRIBUTES are restricted a la
1091 * feature flags. Advertise all supported flags, including
1092 * privileged attributes that require explicit opt-in from
1093 * userspace. ATTRIBUTES.XFRM is not adjusted as userspace is
1094 * expected to derive it from supported XCR0.
1096 entry->eax &= SGX_ATTR_PRIV_MASK | SGX_ATTR_UNPRIV_MASK;
1101 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) {
1102 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1106 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) {
1107 if (!do_host_cpuid(array, function, i))
1111 /* Intel AMX TILE */
1113 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) {
1114 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1118 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) {
1119 if (!do_host_cpuid(array, function, i))
1123 case 0x1e: /* TMUL information */
1124 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) {
1125 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1129 case KVM_CPUID_SIGNATURE: {
1130 const u32 *sigptr = (const u32 *)KVM_SIGNATURE;
1131 entry->eax = KVM_CPUID_FEATURES;
1132 entry->ebx = sigptr[0];
1133 entry->ecx = sigptr[1];
1134 entry->edx = sigptr[2];
1137 case KVM_CPUID_FEATURES:
1138 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
1139 (1 << KVM_FEATURE_NOP_IO_DELAY) |
1140 (1 << KVM_FEATURE_CLOCKSOURCE2) |
1141 (1 << KVM_FEATURE_ASYNC_PF) |
1142 (1 << KVM_FEATURE_PV_EOI) |
1143 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT) |
1144 (1 << KVM_FEATURE_PV_UNHALT) |
1145 (1 << KVM_FEATURE_PV_TLB_FLUSH) |
1146 (1 << KVM_FEATURE_ASYNC_PF_VMEXIT) |
1147 (1 << KVM_FEATURE_PV_SEND_IPI) |
1148 (1 << KVM_FEATURE_POLL_CONTROL) |
1149 (1 << KVM_FEATURE_PV_SCHED_YIELD) |
1150 (1 << KVM_FEATURE_ASYNC_PF_INT);
1152 if (sched_info_on())
1153 entry->eax |= (1 << KVM_FEATURE_STEAL_TIME);
1160 entry->eax = min(entry->eax, 0x80000022);
1162 * Serializing LFENCE is reported in a multitude of ways, and
1163 * NullSegClearsBase is not reported in CPUID on Zen2; help
1164 * userspace by providing the CPUID leaf ourselves.
1166 * However, only do it if the host has CPUID leaf 0x8000001d.
1167 * QEMU thinks that it can query the host blindly for that
1168 * CPUID leaf if KVM reports that it supports 0x8000001d or
1169 * above. The processor merrily returns values from the
1170 * highest Intel leaf which QEMU tries to use as the guest's
1171 * 0x8000001d. Even worse, this can result in an infinite
1172 * loop if said highest leaf has no subleaves indexed by ECX.
1174 if (entry->eax >= 0x8000001d &&
1175 (static_cpu_has(X86_FEATURE_LFENCE_RDTSC)
1176 || !static_cpu_has_bug(X86_BUG_NULL_SEG)))
1177 entry->eax = max(entry->eax, 0x80000021);
1180 entry->ebx &= ~GENMASK(27, 16);
1181 cpuid_entry_override(entry, CPUID_8000_0001_EDX);
1182 cpuid_entry_override(entry, CPUID_8000_0001_ECX);
1185 /* Pass host L1 cache and TLB info. */
1188 /* Drop reserved bits, pass host L2 cache and TLB info. */
1189 entry->edx &= ~GENMASK(17, 16);
1191 case 0x80000007: /* Advanced power management */
1192 cpuid_entry_override(entry, CPUID_8000_0007_EDX);
1194 /* mask against host */
1195 entry->edx &= boot_cpu_data.x86_power;
1196 entry->eax = entry->ebx = entry->ecx = 0;
1199 unsigned g_phys_as = (entry->eax >> 16) & 0xff;
1200 unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U);
1201 unsigned phys_as = entry->eax & 0xff;
1204 * If TDP (NPT) is disabled use the adjusted host MAXPHYADDR as
1205 * the guest operates in the same PA space as the host, i.e.
1206 * reductions in MAXPHYADDR for memory encryption affect shadow
1209 * If TDP is enabled but an explicit guest MAXPHYADDR is not
1210 * provided, use the raw bare metal MAXPHYADDR as reductions to
1211 * the HPAs do not affect GPAs.
1214 g_phys_as = boot_cpu_data.x86_phys_bits;
1215 else if (!g_phys_as)
1216 g_phys_as = phys_as;
1218 entry->eax = g_phys_as | (virt_as << 8);
1219 entry->ecx &= ~(GENMASK(31, 16) | GENMASK(11, 8));
1221 cpuid_entry_override(entry, CPUID_8000_0008_EBX);
1225 if (!kvm_cpu_cap_has(X86_FEATURE_SVM)) {
1226 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1229 entry->eax = 1; /* SVM revision 1 */
1230 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
1231 ASID emulation to nested SVM */
1232 entry->ecx = 0; /* Reserved */
1233 cpuid_entry_override(entry, CPUID_8000_000A_EDX);
1236 entry->ecx = entry->edx = 0;
1239 entry->eax &= GENMASK(2, 0);
1240 entry->ebx = entry->ecx = entry->edx = 0;
1243 /* Do not return host topology information. */
1244 entry->eax = entry->ebx = entry->ecx = 0;
1245 entry->edx = 0; /* reserved */
1248 if (!kvm_cpu_cap_has(X86_FEATURE_SEV)) {
1249 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1251 cpuid_entry_override(entry, CPUID_8000_001F_EAX);
1252 /* Clear NumVMPL since KVM does not support VMPL. */
1253 entry->ebx &= ~GENMASK(31, 12);
1255 * Enumerate '0' for "PA bits reduction", the adjusted
1256 * MAXPHYADDR is enumerated directly (see 0x80000008).
1258 entry->ebx &= ~GENMASK(11, 6);
1262 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1265 entry->ebx = entry->ecx = entry->edx = 0;
1266 cpuid_entry_override(entry, CPUID_8000_0021_EAX);
1268 /* AMD Extended Performance Monitoring and Debug */
1270 union cpuid_0x80000022_ebx ebx;
1272 entry->ecx = entry->edx = 0;
1273 if (!enable_pmu || !kvm_cpu_cap_has(X86_FEATURE_PERFMON_V2)) {
1274 entry->eax = entry->ebx;
1278 cpuid_entry_override(entry, CPUID_8000_0022_EAX);
1280 if (kvm_cpu_cap_has(X86_FEATURE_PERFMON_V2))
1281 ebx.split.num_core_pmc = kvm_pmu_cap.num_counters_gp;
1282 else if (kvm_cpu_cap_has(X86_FEATURE_PERFCTR_CORE))
1283 ebx.split.num_core_pmc = AMD64_NUM_COUNTERS_CORE;
1285 ebx.split.num_core_pmc = AMD64_NUM_COUNTERS;
1287 entry->ebx = ebx.full;
1290 /*Add support for Centaur's CPUID instruction*/
1292 /*Just support up to 0xC0000004 now*/
1293 entry->eax = min(entry->eax, 0xC0000004);
1296 cpuid_entry_override(entry, CPUID_C000_0001_EDX);
1298 case 3: /* Processor serial number */
1299 case 5: /* MONITOR/MWAIT */
1304 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1316 static int do_cpuid_func(struct kvm_cpuid_array *array, u32 func,
1319 if (type == KVM_GET_EMULATED_CPUID)
1320 return __do_cpuid_func_emulated(array, func);
1322 return __do_cpuid_func(array, func);
1325 #define CENTAUR_CPUID_SIGNATURE 0xC0000000
1327 static int get_cpuid_func(struct kvm_cpuid_array *array, u32 func,
1333 if (func == CENTAUR_CPUID_SIGNATURE &&
1334 boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR)
1337 r = do_cpuid_func(array, func, type);
1341 limit = array->entries[array->nent - 1].eax;
1342 for (func = func + 1; func <= limit; ++func) {
1343 r = do_cpuid_func(array, func, type);
1351 static bool sanity_check_entries(struct kvm_cpuid_entry2 __user *entries,
1352 __u32 num_entries, unsigned int ioctl_type)
1357 if (ioctl_type != KVM_GET_EMULATED_CPUID)
1361 * We want to make sure that ->padding is being passed clean from
1362 * userspace in case we want to use it for something in the future.
1364 * Sadly, this wasn't enforced for KVM_GET_SUPPORTED_CPUID and so we
1365 * have to give ourselves satisfied only with the emulated side. /me
1368 for (i = 0; i < num_entries; i++) {
1369 if (copy_from_user(pad, entries[i].padding, sizeof(pad)))
1372 if (pad[0] || pad[1] || pad[2])
1378 int kvm_dev_ioctl_get_cpuid(struct kvm_cpuid2 *cpuid,
1379 struct kvm_cpuid_entry2 __user *entries,
1382 static const u32 funcs[] = {
1383 0, 0x80000000, CENTAUR_CPUID_SIGNATURE, KVM_CPUID_SIGNATURE,
1386 struct kvm_cpuid_array array = {
1391 if (cpuid->nent < 1)
1393 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1394 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
1396 if (sanity_check_entries(entries, cpuid->nent, type))
1399 array.entries = kvcalloc(cpuid->nent, sizeof(struct kvm_cpuid_entry2), GFP_KERNEL);
1403 array.maxnent = cpuid->nent;
1405 for (i = 0; i < ARRAY_SIZE(funcs); i++) {
1406 r = get_cpuid_func(&array, funcs[i], type);
1410 cpuid->nent = array.nent;
1412 if (copy_to_user(entries, array.entries,
1413 array.nent * sizeof(struct kvm_cpuid_entry2)))
1417 kvfree(array.entries);
1421 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry_index(struct kvm_vcpu *vcpu,
1422 u32 function, u32 index)
1424 return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent,
1427 EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry_index);
1429 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
1432 return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent,
1433 function, KVM_CPUID_INDEX_NOT_SIGNIFICANT);
1435 EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
1438 * Intel CPUID semantics treats any query for an out-of-range leaf as if the
1439 * highest basic leaf (i.e. CPUID.0H:EAX) were requested. AMD CPUID semantics
1440 * returns all zeroes for any undefined leaf, whether or not the leaf is in
1441 * range. Centaur/VIA follows Intel semantics.
1443 * A leaf is considered out-of-range if its function is higher than the maximum
1444 * supported leaf of its associated class or if its associated class does not
1447 * There are three primary classes to be considered, with their respective
1448 * ranges described as "<base> - <top>[,<base2> - <top2>] inclusive. A primary
1449 * class exists if a guest CPUID entry for its <base> leaf exists. For a given
1450 * class, CPUID.<base>.EAX contains the max supported leaf for the class.
1452 * - Basic: 0x00000000 - 0x3fffffff, 0x50000000 - 0x7fffffff
1453 * - Hypervisor: 0x40000000 - 0x4fffffff
1454 * - Extended: 0x80000000 - 0xbfffffff
1455 * - Centaur: 0xc0000000 - 0xcfffffff
1457 * The Hypervisor class is further subdivided into sub-classes that each act as
1458 * their own independent class associated with a 0x100 byte range. E.g. if Qemu
1459 * is advertising support for both HyperV and KVM, the resulting Hypervisor
1460 * CPUID sub-classes are:
1462 * - HyperV: 0x40000000 - 0x400000ff
1463 * - KVM: 0x40000100 - 0x400001ff
1465 static struct kvm_cpuid_entry2 *
1466 get_out_of_range_cpuid_entry(struct kvm_vcpu *vcpu, u32 *fn_ptr, u32 index)
1468 struct kvm_cpuid_entry2 *basic, *class;
1469 u32 function = *fn_ptr;
1471 basic = kvm_find_cpuid_entry(vcpu, 0);
1475 if (is_guest_vendor_amd(basic->ebx, basic->ecx, basic->edx) ||
1476 is_guest_vendor_hygon(basic->ebx, basic->ecx, basic->edx))
1479 if (function >= 0x40000000 && function <= 0x4fffffff)
1480 class = kvm_find_cpuid_entry(vcpu, function & 0xffffff00);
1481 else if (function >= 0xc0000000)
1482 class = kvm_find_cpuid_entry(vcpu, 0xc0000000);
1484 class = kvm_find_cpuid_entry(vcpu, function & 0x80000000);
1486 if (class && function <= class->eax)
1490 * Leaf specific adjustments are also applied when redirecting to the
1491 * max basic entry, e.g. if the max basic leaf is 0xb but there is no
1492 * entry for CPUID.0xb.index (see below), then the output value for EDX
1493 * needs to be pulled from CPUID.0xb.1.
1495 *fn_ptr = basic->eax;
1498 * The class does not exist or the requested function is out of range;
1499 * the effective CPUID entry is the max basic leaf. Note, the index of
1500 * the original requested leaf is observed!
1502 return kvm_find_cpuid_entry_index(vcpu, basic->eax, index);
1505 bool kvm_cpuid(struct kvm_vcpu *vcpu, u32 *eax, u32 *ebx,
1506 u32 *ecx, u32 *edx, bool exact_only)
1508 u32 orig_function = *eax, function = *eax, index = *ecx;
1509 struct kvm_cpuid_entry2 *entry;
1510 bool exact, used_max_basic = false;
1512 entry = kvm_find_cpuid_entry_index(vcpu, function, index);
1515 if (!entry && !exact_only) {
1516 entry = get_out_of_range_cpuid_entry(vcpu, &function, index);
1517 used_max_basic = !!entry;
1525 if (function == 7 && index == 0) {
1527 if (!__kvm_get_msr(vcpu, MSR_IA32_TSX_CTRL, &data, true) &&
1528 (data & TSX_CTRL_CPUID_CLEAR))
1529 *ebx &= ~(F(RTM) | F(HLE));
1530 } else if (function == 0x80000007) {
1531 if (kvm_hv_invtsc_suppressed(vcpu))
1532 *edx &= ~SF(CONSTANT_TSC);
1535 *eax = *ebx = *ecx = *edx = 0;
1537 * When leaf 0BH or 1FH is defined, CL is pass-through
1538 * and EDX is always the x2APIC ID, even for undefined
1539 * subleaves. Index 1 will exist iff the leaf is
1540 * implemented, so we pass through CL iff leaf 1
1541 * exists. EDX can be copied from any existing index.
1543 if (function == 0xb || function == 0x1f) {
1544 entry = kvm_find_cpuid_entry_index(vcpu, function, 1);
1546 *ecx = index & 0xff;
1551 trace_kvm_cpuid(orig_function, index, *eax, *ebx, *ecx, *edx, exact,
1555 EXPORT_SYMBOL_GPL(kvm_cpuid);
1557 int kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
1559 u32 eax, ebx, ecx, edx;
1561 if (cpuid_fault_enabled(vcpu) && !kvm_require_cpl(vcpu, 0))
1564 eax = kvm_rax_read(vcpu);
1565 ecx = kvm_rcx_read(vcpu);
1566 kvm_cpuid(vcpu, &eax, &ebx, &ecx, &edx, false);
1567 kvm_rax_write(vcpu, eax);
1568 kvm_rbx_write(vcpu, ebx);
1569 kvm_rcx_write(vcpu, ecx);
1570 kvm_rdx_write(vcpu, edx);
1571 return kvm_skip_emulated_instruction(vcpu);
1573 EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);