1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * x86 SMP booting functions
5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Copyright 2001 Andi Kleen, SuSE Labs.
9 * Much of the core SMP work is based on previous work by Thomas Radke, to
10 * whom a great many thanks are extended.
12 * Thanks to Intel for making available several different Pentium,
13 * Pentium Pro and Pentium-II/Xeon MP machines.
14 * Original development of Linux SMP code supported by Caldera.
17 * Felix Koop : NR_CPUS used properly
18 * Jose Renau : Handle single CPU case.
19 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
20 * Greg Wright : Fix for kernel stacks panic.
21 * Erich Boleyn : MP v1.4 and additional changes.
22 * Matthias Sattler : Changes for 2.1 kernel map.
23 * Michel Lespinasse : Changes for 2.1 kernel map.
24 * Michael Chastain : Change trampoline.S to gnu as.
25 * Alan Cox : Dumb bug: 'B' step PPro's are fine
26 * Ingo Molnar : Added APIC timers, based on code
28 * Ingo Molnar : various cleanups and rewrites
29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
31 * Andi Kleen : Changed for SMP boot into long mode.
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
35 * Andi Kleen : Converted to new state machine.
36 * Ashok Raj : CPU hotplug support
37 * Glauber Costa : i386 and x86_64 integration
40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
42 #include <linux/init.h>
43 #include <linux/smp.h>
44 #include <linux/export.h>
45 #include <linux/sched.h>
46 #include <linux/sched/topology.h>
47 #include <linux/sched/hotplug.h>
48 #include <linux/sched/task_stack.h>
49 #include <linux/percpu.h>
50 #include <linux/memblock.h>
51 #include <linux/err.h>
52 #include <linux/nmi.h>
53 #include <linux/tboot.h>
54 #include <linux/gfp.h>
55 #include <linux/cpuidle.h>
56 #include <linux/numa.h>
57 #include <linux/pgtable.h>
58 #include <linux/overflow.h>
59 #include <linux/syscore_ops.h>
65 #include <asm/realmode.h>
68 #include <asm/tlbflush.h>
70 #include <asm/mwait.h>
72 #include <asm/io_apic.h>
73 #include <asm/fpu/api.h>
74 #include <asm/setup.h>
75 #include <asm/uv/uv.h>
76 #include <linux/mc146818rtc.h>
77 #include <asm/i8259.h>
79 #include <asm/qspinlock.h>
80 #include <asm/intel-family.h>
81 #include <asm/cpu_device_id.h>
82 #include <asm/spec-ctrl.h>
83 #include <asm/hw_irq.h>
84 #include <asm/stackprotector.h>
86 /* representing HT siblings of each logical CPU */
87 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
88 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
90 /* representing HT and core siblings of each logical CPU */
91 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
92 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
94 /* representing HT, core, and die siblings of each logical CPU */
95 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map);
96 EXPORT_PER_CPU_SYMBOL(cpu_die_map);
98 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
100 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_l2c_shared_map);
102 /* Per CPU bogomips and other parameters */
103 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
104 EXPORT_PER_CPU_SYMBOL(cpu_info);
106 /* Logical package management. We might want to allocate that dynamically */
107 unsigned int __max_logical_packages __read_mostly;
108 EXPORT_SYMBOL(__max_logical_packages);
109 static unsigned int logical_packages __read_mostly;
110 static unsigned int logical_die __read_mostly;
112 /* Maximum number of SMT threads on any online core */
113 int __read_mostly __max_smt_threads = 1;
115 /* Flag to indicate if a complete sched domain rebuild is required */
116 bool x86_topology_update;
118 int arch_update_cpu_topology(void)
120 int retval = x86_topology_update;
122 x86_topology_update = false;
126 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
130 spin_lock_irqsave(&rtc_lock, flags);
131 CMOS_WRITE(0xa, 0xf);
132 spin_unlock_irqrestore(&rtc_lock, flags);
133 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
135 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
139 static inline void smpboot_restore_warm_reset_vector(void)
144 * Paranoid: Set warm reset code and vector here back
147 spin_lock_irqsave(&rtc_lock, flags);
149 spin_unlock_irqrestore(&rtc_lock, flags);
151 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
155 * Report back to the Boot Processor during boot time or to the caller processor
158 static void smp_callin(void)
163 * If waken up by an INIT in an 82489DX configuration
164 * cpu_callout_mask guarantees we don't get here before
165 * an INIT_deassert IPI reaches our local APIC, so it is
166 * now safe to touch our local APIC.
168 cpuid = smp_processor_id();
171 * the boot CPU has finished the init stage and is spinning
172 * on callin_map until we finish. We are free to set up this
173 * CPU, first the APIC. (this is probably redundant on most
179 * Save our processor parameters. Note: this information
180 * is needed for clock calibration.
182 smp_store_cpu_info(cpuid);
185 * The topology information must be up to date before
186 * calibrate_delay() and notify_cpu_starting().
188 set_cpu_sibling_map(raw_smp_processor_id());
190 init_freq_invariance(true, false);
194 * Update loops_per_jiffy in cpu_data. Previous call to
195 * smp_store_cpu_info() stored a value that is close but not as
196 * accurate as the value just calculated.
199 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
200 pr_debug("Stack at about %p\n", &cpuid);
204 notify_cpu_starting(cpuid);
207 * Allow the master to continue.
209 cpumask_set_cpu(cpuid, cpu_callin_mask);
212 static int cpu0_logical_apicid;
213 static int enable_start_cpu0;
215 * Activate a secondary processor.
217 static void notrace start_secondary(void *unused)
220 * Don't put *anything* except direct CPU state initialization
221 * before cpu_init(), SMP booting is too fragile that we want to
222 * limit the things done here to the most necessary things.
227 /* switch away from the initial page table */
228 load_cr3(swapper_pg_dir);
231 cpu_init_secondary();
232 rcu_cpu_starting(raw_smp_processor_id());
233 x86_cpuinit.early_percpu_clock_init();
236 enable_start_cpu0 = 0;
238 /* otherwise gcc will move up smp_processor_id before the cpu_init */
241 * Check TSC synchronization with the boot CPU:
243 check_tsc_sync_target();
245 speculative_store_bypass_ht_init();
248 * Lock vector_lock, set CPU online and bring the vector
249 * allocator online. Online must be set with vector_lock held
250 * to prevent a concurrent irq setup/teardown from seeing a
251 * half valid vector space.
254 set_cpu_online(smp_processor_id(), true);
256 unlock_vector_lock();
257 cpu_set_state_online(smp_processor_id());
258 x86_platform.nmi_init();
260 /* enable local interrupts */
263 x86_cpuinit.setup_percpu_clockev();
266 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
270 * topology_is_primary_thread - Check whether CPU is the primary SMT thread
273 bool topology_is_primary_thread(unsigned int cpu)
275 return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid, cpu));
279 * topology_smt_supported - Check whether SMT is supported by the CPUs
281 bool topology_smt_supported(void)
283 return smp_num_siblings > 1;
287 * topology_phys_to_logical_pkg - Map a physical package id to a logical
289 * Returns logical package id or -1 if not found
291 int topology_phys_to_logical_pkg(unsigned int phys_pkg)
295 for_each_possible_cpu(cpu) {
296 struct cpuinfo_x86 *c = &cpu_data(cpu);
298 if (c->initialized && c->phys_proc_id == phys_pkg)
299 return c->logical_proc_id;
303 EXPORT_SYMBOL(topology_phys_to_logical_pkg);
305 * topology_phys_to_logical_die - Map a physical die id to logical
307 * Returns logical die id or -1 if not found
309 int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu)
312 int proc_id = cpu_data(cur_cpu).phys_proc_id;
314 for_each_possible_cpu(cpu) {
315 struct cpuinfo_x86 *c = &cpu_data(cpu);
317 if (c->initialized && c->cpu_die_id == die_id &&
318 c->phys_proc_id == proc_id)
319 return c->logical_die_id;
323 EXPORT_SYMBOL(topology_phys_to_logical_die);
326 * topology_update_package_map - Update the physical to logical package map
327 * @pkg: The physical package id as retrieved via CPUID
328 * @cpu: The cpu for which this is updated
330 int topology_update_package_map(unsigned int pkg, unsigned int cpu)
334 /* Already available somewhere? */
335 new = topology_phys_to_logical_pkg(pkg);
339 new = logical_packages++;
341 pr_info("CPU %u Converting physical %u to logical package %u\n",
345 cpu_data(cpu).logical_proc_id = new;
349 * topology_update_die_map - Update the physical to logical die map
350 * @die: The die id as retrieved via CPUID
351 * @cpu: The cpu for which this is updated
353 int topology_update_die_map(unsigned int die, unsigned int cpu)
357 /* Already available somewhere? */
358 new = topology_phys_to_logical_die(die, cpu);
364 pr_info("CPU %u Converting physical %u to logical die %u\n",
368 cpu_data(cpu).logical_die_id = new;
372 void __init smp_store_boot_cpu_info(void)
374 int id = 0; /* CPU 0 */
375 struct cpuinfo_x86 *c = &cpu_data(id);
379 topology_update_package_map(c->phys_proc_id, id);
380 topology_update_die_map(c->cpu_die_id, id);
381 c->initialized = true;
385 * The bootstrap kernel entry code has set these up. Save them for
388 void smp_store_cpu_info(int id)
390 struct cpuinfo_x86 *c = &cpu_data(id);
392 /* Copy boot_cpu_data only on the first bringup */
397 * During boot time, CPU0 has this setup already. Save the info when
398 * bringing up AP or offlined CPU0.
400 identify_secondary_cpu(c);
401 c->initialized = true;
405 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
407 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
409 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
413 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
415 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
417 return !WARN_ONCE(!topology_same_node(c, o),
418 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
419 "[node: %d != %d]. Ignoring dependency.\n",
420 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
423 #define link_mask(mfunc, c1, c2) \
425 cpumask_set_cpu((c1), mfunc(c2)); \
426 cpumask_set_cpu((c2), mfunc(c1)); \
429 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
431 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
432 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
434 if (c->phys_proc_id == o->phys_proc_id &&
435 c->cpu_die_id == o->cpu_die_id &&
436 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) {
437 if (c->cpu_core_id == o->cpu_core_id)
438 return topology_sane(c, o, "smt");
440 if ((c->cu_id != 0xff) &&
441 (o->cu_id != 0xff) &&
442 (c->cu_id == o->cu_id))
443 return topology_sane(c, o, "smt");
446 } else if (c->phys_proc_id == o->phys_proc_id &&
447 c->cpu_die_id == o->cpu_die_id &&
448 c->cpu_core_id == o->cpu_core_id) {
449 return topology_sane(c, o, "smt");
455 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
457 if (c->phys_proc_id == o->phys_proc_id &&
458 c->cpu_die_id == o->cpu_die_id)
463 static bool match_l2c(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
465 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
467 /* If the arch didn't set up l2c_id, fall back to SMT */
468 if (per_cpu(cpu_l2c_id, cpu1) == BAD_APICID)
469 return match_smt(c, o);
471 /* Do not match if L2 cache id does not match: */
472 if (per_cpu(cpu_l2c_id, cpu1) != per_cpu(cpu_l2c_id, cpu2))
475 return topology_sane(c, o, "l2c");
479 * Unlike the other levels, we do not enforce keeping a
480 * multicore group inside a NUMA node. If this happens, we will
481 * discard the MC level of the topology later.
483 static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
485 if (c->phys_proc_id == o->phys_proc_id)
491 * Define intel_cod_cpu[] for Intel COD (Cluster-on-Die) CPUs.
493 * Any Intel CPU that has multiple nodes per package and does not
494 * match intel_cod_cpu[] has the SNC (Sub-NUMA Cluster) topology.
496 * When in SNC mode, these CPUs enumerate an LLC that is shared
497 * by multiple NUMA nodes. The LLC is shared for off-package data
498 * access but private to the NUMA node (half of the package) for
499 * on-package access. CPUID (the source of the information about
500 * the LLC) can only enumerate the cache as shared or unshared,
501 * but not this particular configuration.
504 static const struct x86_cpu_id intel_cod_cpu[] = {
505 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, 0), /* COD */
506 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, 0), /* COD */
507 X86_MATCH_INTEL_FAM6_MODEL(ANY, 1), /* SNC */
511 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
513 const struct x86_cpu_id *id = x86_match_cpu(intel_cod_cpu);
514 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
515 bool intel_snc = id && id->driver_data;
517 /* Do not match if we do not have a valid APICID for cpu: */
518 if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID)
521 /* Do not match if LLC id does not match: */
522 if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2))
526 * Allow the SNC topology without warning. Return of false
527 * means 'c' does not share the LLC of 'o'. This will be
528 * reflected to userspace.
530 if (match_pkg(c, o) && !topology_same_node(c, o) && intel_snc)
533 return topology_sane(c, o, "llc");
537 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_CLUSTER) || defined(CONFIG_SCHED_MC)
538 static inline int x86_sched_itmt_flags(void)
540 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
543 #ifdef CONFIG_SCHED_MC
544 static int x86_core_flags(void)
546 return cpu_core_flags() | x86_sched_itmt_flags();
549 #ifdef CONFIG_SCHED_SMT
550 static int x86_smt_flags(void)
552 return cpu_smt_flags() | x86_sched_itmt_flags();
555 #ifdef CONFIG_SCHED_CLUSTER
556 static int x86_cluster_flags(void)
558 return cpu_cluster_flags() | x86_sched_itmt_flags();
563 static struct sched_domain_topology_level x86_numa_in_package_topology[] = {
564 #ifdef CONFIG_SCHED_SMT
565 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
567 #ifdef CONFIG_SCHED_CLUSTER
568 { cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS) },
570 #ifdef CONFIG_SCHED_MC
571 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
576 static struct sched_domain_topology_level x86_hybrid_topology[] = {
577 #ifdef CONFIG_SCHED_SMT
578 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
580 #ifdef CONFIG_SCHED_MC
581 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
583 { cpu_cpu_mask, SD_INIT_NAME(DIE) },
587 static struct sched_domain_topology_level x86_topology[] = {
588 #ifdef CONFIG_SCHED_SMT
589 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
591 #ifdef CONFIG_SCHED_CLUSTER
592 { cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS) },
594 #ifdef CONFIG_SCHED_MC
595 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
597 { cpu_cpu_mask, SD_INIT_NAME(DIE) },
602 * Set if a package/die has multiple NUMA nodes inside.
603 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel
604 * Sub-NUMA Clustering have this.
606 static bool x86_has_numa_in_package;
608 void set_cpu_sibling_map(int cpu)
610 bool has_smt = smp_num_siblings > 1;
611 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
612 struct cpuinfo_x86 *c = &cpu_data(cpu);
613 struct cpuinfo_x86 *o;
616 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
619 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
620 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
621 cpumask_set_cpu(cpu, cpu_l2c_shared_mask(cpu));
622 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
623 cpumask_set_cpu(cpu, topology_die_cpumask(cpu));
628 for_each_cpu(i, cpu_sibling_setup_mask) {
631 if (match_pkg(c, o) && !topology_same_node(c, o))
632 x86_has_numa_in_package = true;
634 if ((i == cpu) || (has_smt && match_smt(c, o)))
635 link_mask(topology_sibling_cpumask, cpu, i);
637 if ((i == cpu) || (has_mp && match_llc(c, o)))
638 link_mask(cpu_llc_shared_mask, cpu, i);
640 if ((i == cpu) || (has_mp && match_l2c(c, o)))
641 link_mask(cpu_l2c_shared_mask, cpu, i);
643 if ((i == cpu) || (has_mp && match_die(c, o)))
644 link_mask(topology_die_cpumask, cpu, i);
647 threads = cpumask_weight(topology_sibling_cpumask(cpu));
648 if (threads > __max_smt_threads)
649 __max_smt_threads = threads;
651 for_each_cpu(i, topology_sibling_cpumask(cpu))
652 cpu_data(i).smt_active = threads > 1;
655 * This needs a separate iteration over the cpus because we rely on all
656 * topology_sibling_cpumask links to be set-up.
658 for_each_cpu(i, cpu_sibling_setup_mask) {
661 if ((i == cpu) || (has_mp && match_pkg(c, o))) {
662 link_mask(topology_core_cpumask, cpu, i);
665 * Does this new cpu bringup a new core?
669 * for each core in package, increment
670 * the booted_cores for this new cpu
673 topology_sibling_cpumask(i)) == i)
676 * increment the core count for all
677 * the other cpus in this package
680 cpu_data(i).booted_cores++;
681 } else if (i != cpu && !c->booted_cores)
682 c->booted_cores = cpu_data(i).booted_cores;
687 /* maps the cpu to the sched domain representing multi-core */
688 const struct cpumask *cpu_coregroup_mask(int cpu)
690 return cpu_llc_shared_mask(cpu);
693 const struct cpumask *cpu_clustergroup_mask(int cpu)
695 return cpu_l2c_shared_mask(cpu);
698 static void impress_friends(void)
701 unsigned long bogosum = 0;
703 * Allow the user to impress friends.
705 pr_debug("Before bogomips\n");
706 for_each_possible_cpu(cpu)
707 if (cpumask_test_cpu(cpu, cpu_callout_mask))
708 bogosum += cpu_data(cpu).loops_per_jiffy;
709 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
712 (bogosum/(5000/HZ))%100);
714 pr_debug("Before bogocount - setting activated=1\n");
717 void __inquire_remote_apic(int apicid)
719 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
720 const char * const names[] = { "ID", "VERSION", "SPIV" };
724 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
726 for (i = 0; i < ARRAY_SIZE(regs); i++) {
727 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
732 status = safe_apic_wait_icr_idle();
734 pr_cont("a previous APIC delivery may have failed\n");
736 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
741 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
742 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
745 case APIC_ICR_RR_VALID:
746 status = apic_read(APIC_RRR);
747 pr_cont("%08x\n", status);
756 * The Multiprocessor Specification 1.4 (1997) example code suggests
757 * that there should be a 10ms delay between the BSP asserting INIT
758 * and de-asserting INIT, when starting a remote processor.
759 * But that slows boot and resume on modern processors, which include
760 * many cores and don't require that delay.
762 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
763 * Modern processor families are quirked to remove the delay entirely.
765 #define UDELAY_10MS_DEFAULT 10000
767 static unsigned int init_udelay = UINT_MAX;
769 static int __init cpu_init_udelay(char *str)
771 get_option(&str, &init_udelay);
775 early_param("cpu_init_udelay", cpu_init_udelay);
777 static void __init smp_quirk_init_udelay(void)
779 /* if cmdline changed it from default, leave it alone */
780 if (init_udelay != UINT_MAX)
783 /* if modern processor, use no delay */
784 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
785 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) ||
786 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
790 /* else, use legacy delay */
791 init_udelay = UDELAY_10MS_DEFAULT;
795 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
796 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
797 * won't ... remember to clear down the APIC, etc later.
800 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
802 u32 dm = apic->dest_mode_logical ? APIC_DEST_LOGICAL : APIC_DEST_PHYSICAL;
803 unsigned long send_status, accept_status = 0;
807 /* Boot on the stack */
808 /* Kick the second */
809 apic_icr_write(APIC_DM_NMI | dm, apicid);
811 pr_debug("Waiting for send to finish...\n");
812 send_status = safe_apic_wait_icr_idle();
815 * Give the other CPU some time to accept the IPI.
818 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
819 maxlvt = lapic_get_maxlvt();
820 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
821 apic_write(APIC_ESR, 0);
822 accept_status = (apic_read(APIC_ESR) & 0xEF);
824 pr_debug("NMI sent\n");
827 pr_err("APIC never delivered???\n");
829 pr_err("APIC delivery error (%lx)\n", accept_status);
831 return (send_status | accept_status);
835 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
837 unsigned long send_status = 0, accept_status = 0;
838 int maxlvt, num_starts, j;
840 maxlvt = lapic_get_maxlvt();
843 * Be paranoid about clearing APIC errors.
845 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
846 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
847 apic_write(APIC_ESR, 0);
851 pr_debug("Asserting INIT\n");
854 * Turn INIT on target chip
859 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
862 pr_debug("Waiting for send to finish...\n");
863 send_status = safe_apic_wait_icr_idle();
867 pr_debug("Deasserting INIT\n");
871 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
873 pr_debug("Waiting for send to finish...\n");
874 send_status = safe_apic_wait_icr_idle();
879 * Should we send STARTUP IPIs ?
881 * Determine this based on the APIC version.
882 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
884 if (APIC_INTEGRATED(boot_cpu_apic_version))
890 * Run STARTUP IPI loop.
892 pr_debug("#startup loops: %d\n", num_starts);
894 for (j = 1; j <= num_starts; j++) {
895 pr_debug("Sending STARTUP #%d\n", j);
896 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
897 apic_write(APIC_ESR, 0);
899 pr_debug("After apic_write\n");
906 /* Boot on the stack */
907 /* Kick the second */
908 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
912 * Give the other CPU some time to accept the IPI.
914 if (init_udelay == 0)
919 pr_debug("Startup point 1\n");
921 pr_debug("Waiting for send to finish...\n");
922 send_status = safe_apic_wait_icr_idle();
925 * Give the other CPU some time to accept the IPI.
927 if (init_udelay == 0)
932 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
933 apic_write(APIC_ESR, 0);
934 accept_status = (apic_read(APIC_ESR) & 0xEF);
935 if (send_status || accept_status)
938 pr_debug("After Startup\n");
941 pr_err("APIC never delivered???\n");
943 pr_err("APIC delivery error (%lx)\n", accept_status);
945 return (send_status | accept_status);
948 /* reduce the number of lines printed when booting a large cpu count system */
949 static void announce_cpu(int cpu, int apicid)
951 static int current_node = NUMA_NO_NODE;
952 int node = early_cpu_to_node(cpu);
953 static int width, node_width;
956 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
959 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
962 printk(KERN_INFO "x86: Booting SMP configuration:\n");
964 if (system_state < SYSTEM_RUNNING) {
965 if (node != current_node) {
966 if (current_node > (-1))
970 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
971 node_width - num_digits(node), " ", node);
974 /* Add padding for the BSP */
976 pr_cont("%*s", width + 1, " ");
978 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
981 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
985 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
989 cpu = smp_processor_id();
990 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
997 * Wake up AP by INIT, INIT, STARTUP sequence.
999 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
1000 * boot-strap code which is not a desired behavior for waking up BSP. To
1001 * void the boot-strap code, wake up CPU0 by NMI instead.
1003 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
1004 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
1005 * We'll change this code in the future to wake up hard offlined CPU0 if
1006 * real platform and request are available.
1009 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
1010 int *cpu0_nmi_registered)
1018 * Wake up AP by INIT, INIT, STARTUP sequence.
1021 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
1026 * Wake up BSP by nmi.
1028 * Register a NMI handler to help wake up CPU0.
1030 boot_error = register_nmi_handler(NMI_LOCAL,
1031 wakeup_cpu0_nmi, 0, "wake_cpu0");
1034 enable_start_cpu0 = 1;
1035 *cpu0_nmi_registered = 1;
1036 id = apic->dest_mode_logical ? cpu0_logical_apicid : apicid;
1037 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
1046 int common_cpu_up(unsigned int cpu, struct task_struct *idle)
1050 /* Just in case we booted with a single CPU. */
1051 alternatives_enable_smp();
1053 per_cpu(current_task, cpu) = idle;
1054 cpu_init_stack_canary(cpu, idle);
1056 /* Initialize the interrupt stack(s) */
1057 ret = irq_init_percpu_irqstack(cpu);
1061 #ifdef CONFIG_X86_32
1062 /* Stack for startup_32 can be just as for start_secondary onwards */
1063 per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle);
1065 initial_gs = per_cpu_offset(cpu);
1071 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
1072 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
1073 * Returns zero if CPU booted OK, else error code from
1074 * ->wakeup_secondary_cpu.
1076 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle,
1077 int *cpu0_nmi_registered)
1079 /* start_ip had better be page-aligned! */
1080 unsigned long start_ip = real_mode_header->trampoline_start;
1082 unsigned long boot_error = 0;
1083 unsigned long timeout;
1085 idle->thread.sp = (unsigned long)task_pt_regs(idle);
1086 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu);
1087 initial_code = (unsigned long)start_secondary;
1088 initial_stack = idle->thread.sp;
1090 /* Enable the espfix hack for this CPU */
1091 init_espfix_ap(cpu);
1093 /* So we see what's up */
1094 announce_cpu(cpu, apicid);
1097 * This grunge runs the startup process for
1098 * the targeted processor.
1101 if (x86_platform.legacy.warm_reset) {
1103 pr_debug("Setting warm reset code and vector.\n");
1105 smpboot_setup_warm_reset_vector(start_ip);
1107 * Be paranoid about clearing APIC errors.
1109 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
1110 apic_write(APIC_ESR, 0);
1111 apic_read(APIC_ESR);
1116 * AP might wait on cpu_callout_mask in cpu_init() with
1117 * cpu_initialized_mask set if previous attempt to online
1118 * it timed-out. Clear cpu_initialized_mask so that after
1119 * INIT/SIPI it could start with a clean state.
1121 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1125 * Wake up a CPU in difference cases:
1126 * - Use the method in the APIC driver if it's defined
1128 * - Use an INIT boot APIC message for APs or NMI for BSP.
1130 if (apic->wakeup_secondary_cpu)
1131 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
1133 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
1134 cpu0_nmi_registered);
1138 * Wait 10s total for first sign of life from AP
1141 timeout = jiffies + 10*HZ;
1142 while (time_before(jiffies, timeout)) {
1143 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
1145 * Tell AP to proceed with initialization
1147 cpumask_set_cpu(cpu, cpu_callout_mask);
1157 * Wait till AP completes initial initialization
1159 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
1161 * Allow other tasks to run while we wait for the
1162 * AP to come online. This also gives a chance
1163 * for the MTRR work(triggered by the AP coming online)
1164 * to be completed in the stop machine context.
1170 if (x86_platform.legacy.warm_reset) {
1172 * Cleanup possible dangling ends...
1174 smpboot_restore_warm_reset_vector();
1180 int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
1182 int apicid = apic->cpu_present_to_apicid(cpu);
1183 int cpu0_nmi_registered = 0;
1184 unsigned long flags;
1187 lockdep_assert_irqs_enabled();
1189 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
1191 if (apicid == BAD_APICID ||
1192 !physid_isset(apicid, phys_cpu_present_map) ||
1193 !apic->apic_id_valid(apicid)) {
1194 pr_err("%s: bad cpu %d\n", __func__, cpu);
1199 * Already booted CPU?
1201 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
1202 pr_debug("do_boot_cpu %d Already started\n", cpu);
1207 * Save current MTRR state in case it was changed since early boot
1208 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1212 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1213 err = cpu_check_up_prepare(cpu);
1214 if (err && err != -EBUSY)
1217 /* the FPU context is blank, nobody can own it */
1218 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
1220 err = common_cpu_up(cpu, tidle);
1224 err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered);
1226 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1232 * Check TSC synchronization with the AP (keep irqs disabled
1235 local_irq_save(flags);
1236 check_tsc_sync_source(cpu);
1237 local_irq_restore(flags);
1239 while (!cpu_online(cpu)) {
1241 touch_nmi_watchdog();
1246 * Clean up the nmi handler. Do this after the callin and callout sync
1247 * to avoid impact of possible long unregister time.
1249 if (cpu0_nmi_registered)
1250 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
1256 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1258 void arch_disable_smp_support(void)
1260 disable_ioapic_support();
1264 * Fall back to non SMP mode after errors.
1266 * RED-PEN audit/test this more. I bet there is more state messed up here.
1268 static __init void disable_smp(void)
1270 pr_info("SMP disabled\n");
1272 disable_ioapic_support();
1274 init_cpu_present(cpumask_of(0));
1275 init_cpu_possible(cpumask_of(0));
1277 if (smp_found_config)
1278 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1280 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1281 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1282 cpumask_set_cpu(0, topology_core_cpumask(0));
1283 cpumask_set_cpu(0, topology_die_cpumask(0));
1287 * Various sanity checks.
1289 static void __init smp_sanity_check(void)
1293 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1294 if (def_to_bigsmp && nr_cpu_ids > 8) {
1298 pr_warn("More than 8 CPUs detected - skipping them\n"
1299 "Use CONFIG_X86_BIGSMP\n");
1302 for_each_present_cpu(cpu) {
1304 set_cpu_present(cpu, false);
1309 for_each_possible_cpu(cpu) {
1311 set_cpu_possible(cpu, false);
1319 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1320 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1321 hard_smp_processor_id());
1323 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1327 * Should not be necessary because the MP table should list the boot
1328 * CPU too, but we do it for the sake of robustness anyway.
1330 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1331 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1332 boot_cpu_physical_apicid);
1333 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1338 static void __init smp_cpu_index_default(void)
1341 struct cpuinfo_x86 *c;
1343 for_each_possible_cpu(i) {
1345 /* mark all to hotplug */
1346 c->cpu_index = nr_cpu_ids;
1350 static void __init smp_get_logical_apicid(void)
1353 cpu0_logical_apicid = apic_read(APIC_LDR);
1355 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1358 void __init smp_prepare_cpus_common(void)
1362 smp_cpu_index_default();
1365 * Setup boot CPU information
1367 smp_store_boot_cpu_info(); /* Final full version of the data */
1368 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1371 for_each_possible_cpu(i) {
1372 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1373 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1374 zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL);
1375 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1376 zalloc_cpumask_var(&per_cpu(cpu_l2c_shared_map, i), GFP_KERNEL);
1380 * Set 'default' x86 topology, this matches default_topology() in that
1381 * it has NUMA nodes as a topology level. See also
1382 * native_smp_cpus_done().
1384 * Must be done before set_cpus_sibling_map() is ran.
1386 set_sched_topology(x86_topology);
1388 set_cpu_sibling_map(0);
1392 * Prepare for SMP bootup.
1393 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter
1394 * for common interface support.
1396 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1398 smp_prepare_cpus_common();
1400 init_freq_invariance(false, false);
1403 switch (apic_intr_mode) {
1405 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1408 case APIC_SYMMETRIC_IO_NO_ROUTING:
1410 /* Setup local timer */
1411 x86_init.timers.setup_percpu_clockev();
1413 case APIC_VIRTUAL_WIRE:
1414 case APIC_SYMMETRIC_IO:
1418 /* Setup local timer */
1419 x86_init.timers.setup_percpu_clockev();
1421 smp_get_logical_apicid();
1424 print_cpu_info(&cpu_data(0));
1428 set_mtrr_aps_delayed_init();
1430 smp_quirk_init_udelay();
1432 speculative_store_bypass_ht_init();
1435 void arch_thaw_secondary_cpus_begin(void)
1437 set_mtrr_aps_delayed_init();
1440 void arch_thaw_secondary_cpus_end(void)
1446 * Early setup to make printk work.
1448 void __init native_smp_prepare_boot_cpu(void)
1450 int me = smp_processor_id();
1451 switch_to_new_gdt(me);
1452 /* already set me in cpu_online_mask in boot_cpu_init() */
1453 cpumask_set_cpu(me, cpu_callout_mask);
1454 cpu_set_state_online(me);
1455 native_pv_lock_init();
1458 void __init calculate_max_logical_packages(void)
1463 * Today neither Intel nor AMD support heterogeneous systems so
1464 * extrapolate the boot cpu's data to all packages.
1466 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads();
1467 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus);
1468 pr_info("Max logical packages: %u\n", __max_logical_packages);
1471 void __init native_smp_cpus_done(unsigned int max_cpus)
1473 pr_debug("Boot done\n");
1475 calculate_max_logical_packages();
1477 /* XXX for now assume numa-in-package and hybrid don't overlap */
1478 if (x86_has_numa_in_package)
1479 set_sched_topology(x86_numa_in_package_topology);
1480 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU))
1481 set_sched_topology(x86_hybrid_topology);
1488 static int __initdata setup_possible_cpus = -1;
1489 static int __init _setup_possible_cpus(char *str)
1491 get_option(&str, &setup_possible_cpus);
1494 early_param("possible_cpus", _setup_possible_cpus);
1498 * cpu_possible_mask should be static, it cannot change as cpu's
1499 * are onlined, or offlined. The reason is per-cpu data-structures
1500 * are allocated by some modules at init time, and don't expect to
1501 * do this dynamically on cpu arrival/departure.
1502 * cpu_present_mask on the other hand can change dynamically.
1503 * In case when cpu_hotplug is not compiled, then we resort to current
1504 * behaviour, which is cpu_possible == cpu_present.
1507 * Three ways to find out the number of additional hotplug CPUs:
1508 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1509 * - The user can overwrite it with possible_cpus=NUM
1510 * - Otherwise don't reserve additional CPUs.
1511 * We do this because additional CPUs waste a lot of memory.
1514 __init void prefill_possible_map(void)
1518 /* No boot processor was found in mptable or ACPI MADT */
1519 if (!num_processors) {
1520 if (boot_cpu_has(X86_FEATURE_APIC)) {
1521 int apicid = boot_cpu_physical_apicid;
1522 int cpu = hard_smp_processor_id();
1524 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu);
1526 /* Make sure boot cpu is enumerated */
1527 if (apic->cpu_present_to_apicid(0) == BAD_APICID &&
1528 apic->apic_id_valid(apicid))
1529 generic_processor_info(apicid, boot_cpu_apic_version);
1532 if (!num_processors)
1536 i = setup_max_cpus ?: 1;
1537 if (setup_possible_cpus == -1) {
1538 possible = num_processors;
1539 #ifdef CONFIG_HOTPLUG_CPU
1541 possible += disabled_cpus;
1547 possible = setup_possible_cpus;
1549 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1551 /* nr_cpu_ids could be reduced via nr_cpus= */
1552 if (possible > nr_cpu_ids) {
1553 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n",
1554 possible, nr_cpu_ids);
1555 possible = nr_cpu_ids;
1558 #ifdef CONFIG_HOTPLUG_CPU
1559 if (!setup_max_cpus)
1562 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1563 possible, setup_max_cpus);
1567 nr_cpu_ids = possible;
1569 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1570 possible, max_t(int, possible - num_processors, 0));
1572 reset_cpu_possible_mask();
1574 for (i = 0; i < possible; i++)
1575 set_cpu_possible(i, true);
1578 #ifdef CONFIG_HOTPLUG_CPU
1580 /* Recompute SMT state for all CPUs on offline */
1581 static void recompute_smt_state(void)
1583 int max_threads, cpu;
1586 for_each_online_cpu (cpu) {
1587 int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1589 if (threads > max_threads)
1590 max_threads = threads;
1592 __max_smt_threads = max_threads;
1595 static void remove_siblinginfo(int cpu)
1598 struct cpuinfo_x86 *c = &cpu_data(cpu);
1600 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1601 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1603 * last thread sibling in this cpu core going down
1605 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1606 cpu_data(sibling).booted_cores--;
1609 for_each_cpu(sibling, topology_die_cpumask(cpu))
1610 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling));
1612 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) {
1613 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1614 if (cpumask_weight(topology_sibling_cpumask(sibling)) == 1)
1615 cpu_data(sibling).smt_active = false;
1618 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1619 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1620 for_each_cpu(sibling, cpu_l2c_shared_mask(cpu))
1621 cpumask_clear_cpu(cpu, cpu_l2c_shared_mask(sibling));
1622 cpumask_clear(cpu_llc_shared_mask(cpu));
1623 cpumask_clear(cpu_l2c_shared_mask(cpu));
1624 cpumask_clear(topology_sibling_cpumask(cpu));
1625 cpumask_clear(topology_core_cpumask(cpu));
1626 cpumask_clear(topology_die_cpumask(cpu));
1628 c->booted_cores = 0;
1629 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1630 recompute_smt_state();
1633 static void remove_cpu_from_maps(int cpu)
1635 set_cpu_online(cpu, false);
1636 cpumask_clear_cpu(cpu, cpu_callout_mask);
1637 cpumask_clear_cpu(cpu, cpu_callin_mask);
1638 /* was set by cpu_init() */
1639 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1640 numa_remove_cpu(cpu);
1643 void cpu_disable_common(void)
1645 int cpu = smp_processor_id();
1647 remove_siblinginfo(cpu);
1649 /* It's now safe to remove this processor from the online map */
1651 remove_cpu_from_maps(cpu);
1652 unlock_vector_lock();
1657 int native_cpu_disable(void)
1661 ret = lapic_can_unplug_cpu();
1665 cpu_disable_common();
1668 * Disable the local APIC. Otherwise IPI broadcasts will reach
1669 * it. It still responds normally to INIT, NMI, SMI, and SIPI
1672 * Disabling the APIC must happen after cpu_disable_common()
1673 * which invokes fixup_irqs().
1675 * Disabling the APIC preserves already set bits in IRR, but
1676 * an interrupt arriving after disabling the local APIC does not
1677 * set the corresponding IRR bit.
1679 * fixup_irqs() scans IRR for set bits so it can raise a not
1680 * yet handled interrupt on the new destination CPU via an IPI
1681 * but obviously it can't do so for IRR bits which are not set.
1682 * IOW, interrupts arriving after disabling the local APIC will
1685 apic_soft_disable();
1690 int common_cpu_die(unsigned int cpu)
1694 /* We don't do anything here: idle task is faking death itself. */
1696 /* They ack this in play_dead() by setting CPU_DEAD */
1697 if (cpu_wait_death(cpu, 5)) {
1698 if (system_state == SYSTEM_RUNNING)
1699 pr_info("CPU %u is now offline\n", cpu);
1701 pr_err("CPU %u didn't die...\n", cpu);
1708 void native_cpu_die(unsigned int cpu)
1710 common_cpu_die(cpu);
1713 void play_dead_common(void)
1718 (void)cpu_report_death();
1721 * With physical CPU hotplug, we should halt the cpu
1723 local_irq_disable();
1727 * cond_wakeup_cpu0 - Wake up CPU0 if needed.
1729 * If NMI wants to wake up CPU0, start CPU0.
1731 void cond_wakeup_cpu0(void)
1733 if (smp_processor_id() == 0 && enable_start_cpu0)
1736 EXPORT_SYMBOL_GPL(cond_wakeup_cpu0);
1739 * We need to flush the caches before going to sleep, lest we have
1740 * dirty data in our caches when we come back up.
1742 static inline void mwait_play_dead(void)
1744 unsigned int eax, ebx, ecx, edx;
1745 unsigned int highest_cstate = 0;
1746 unsigned int highest_subcstate = 0;
1750 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
1751 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
1753 if (!this_cpu_has(X86_FEATURE_MWAIT))
1755 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1757 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1760 eax = CPUID_MWAIT_LEAF;
1762 native_cpuid(&eax, &ebx, &ecx, &edx);
1765 * eax will be 0 if EDX enumeration is not valid.
1766 * Initialized below to cstate, sub_cstate value when EDX is valid.
1768 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1771 edx >>= MWAIT_SUBSTATE_SIZE;
1772 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1773 if (edx & MWAIT_SUBSTATE_MASK) {
1775 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1778 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1779 (highest_subcstate - 1);
1783 * This should be a memory location in a cache line which is
1784 * unlikely to be touched by other processors. The actual
1785 * content is immaterial as it is not actually modified in any way.
1787 mwait_ptr = ¤t_thread_info()->flags;
1793 * The CLFLUSH is a workaround for erratum AAI65 for
1794 * the Xeon 7400 series. It's not clear it is actually
1795 * needed, but it should be harmless in either case.
1796 * The WBINVD is insufficient due to the spurious-wakeup
1797 * case where we return around the loop.
1802 __monitor(mwait_ptr, 0, 0);
1810 void hlt_play_dead(void)
1812 if (__this_cpu_read(cpu_info.x86) >= 4)
1822 void native_play_dead(void)
1825 tboot_shutdown(TB_SHUTDOWN_WFS);
1827 mwait_play_dead(); /* Only returns on failure */
1828 if (cpuidle_play_dead())
1832 #else /* ... !CONFIG_HOTPLUG_CPU */
1833 int native_cpu_disable(void)
1838 void native_cpu_die(unsigned int cpu)
1840 /* We said "no" in __cpu_disable */
1844 void native_play_dead(void)
1851 #ifdef CONFIG_X86_64
1853 * APERF/MPERF frequency ratio computation.
1855 * The scheduler wants to do frequency invariant accounting and needs a <1
1856 * ratio to account for the 'current' frequency, corresponding to
1857 * freq_curr / freq_max.
1859 * Since the frequency freq_curr on x86 is controlled by micro-controller and
1860 * our P-state setting is little more than a request/hint, we need to observe
1861 * the effective frequency 'BusyMHz', i.e. the average frequency over a time
1862 * interval after discarding idle time. This is given by:
1864 * BusyMHz = delta_APERF / delta_MPERF * freq_base
1866 * where freq_base is the max non-turbo P-state.
1868 * The freq_max term has to be set to a somewhat arbitrary value, because we
1869 * can't know which turbo states will be available at a given point in time:
1870 * it all depends on the thermal headroom of the entire package. We set it to
1871 * the turbo level with 4 cores active.
1873 * Benchmarks show that's a good compromise between the 1C turbo ratio
1874 * (freq_curr/freq_max would rarely reach 1) and something close to freq_base,
1875 * which would ignore the entire turbo range (a conspicuous part, making
1876 * freq_curr/freq_max always maxed out).
1878 * An exception to the heuristic above is the Atom uarch, where we choose the
1879 * highest turbo level for freq_max since Atom's are generally oriented towards
1882 * Setting freq_max to anything less than the 1C turbo ratio makes the ratio
1883 * freq_curr / freq_max to eventually grow >1, in which case we clip it to 1.
1886 DEFINE_STATIC_KEY_FALSE(arch_scale_freq_key);
1888 static DEFINE_PER_CPU(u64, arch_prev_aperf);
1889 static DEFINE_PER_CPU(u64, arch_prev_mperf);
1890 static u64 arch_turbo_freq_ratio = SCHED_CAPACITY_SCALE;
1891 static u64 arch_max_freq_ratio = SCHED_CAPACITY_SCALE;
1893 void arch_set_max_freq_ratio(bool turbo_disabled)
1895 arch_max_freq_ratio = turbo_disabled ? SCHED_CAPACITY_SCALE :
1896 arch_turbo_freq_ratio;
1898 EXPORT_SYMBOL_GPL(arch_set_max_freq_ratio);
1900 static bool turbo_disabled(void)
1905 err = rdmsrl_safe(MSR_IA32_MISC_ENABLE, &misc_en);
1909 return (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE);
1912 static bool slv_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq)
1916 err = rdmsrl_safe(MSR_ATOM_CORE_RATIOS, base_freq);
1920 err = rdmsrl_safe(MSR_ATOM_CORE_TURBO_RATIOS, turbo_freq);
1924 *base_freq = (*base_freq >> 16) & 0x3F; /* max P state */
1925 *turbo_freq = *turbo_freq & 0x3F; /* 1C turbo */
1930 #define X86_MATCH(model) \
1931 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, \
1932 INTEL_FAM6_##model, X86_FEATURE_APERFMPERF, NULL)
1934 static const struct x86_cpu_id has_knl_turbo_ratio_limits[] = {
1935 X86_MATCH(XEON_PHI_KNL),
1936 X86_MATCH(XEON_PHI_KNM),
1940 static const struct x86_cpu_id has_skx_turbo_ratio_limits[] = {
1941 X86_MATCH(SKYLAKE_X),
1945 static const struct x86_cpu_id has_glm_turbo_ratio_limits[] = {
1946 X86_MATCH(ATOM_GOLDMONT),
1947 X86_MATCH(ATOM_GOLDMONT_D),
1948 X86_MATCH(ATOM_GOLDMONT_PLUS),
1952 static bool knl_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq,
1953 int num_delta_fratio)
1955 int fratio, delta_fratio, found;
1959 err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq);
1963 *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */
1965 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &msr);
1969 fratio = (msr >> 8) & 0xFF;
1973 if (found >= num_delta_fratio) {
1974 *turbo_freq = fratio;
1978 delta_fratio = (msr >> (i + 5)) & 0x7;
1982 fratio -= delta_fratio;
1991 static bool skx_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq, int size)
1997 err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq);
2001 *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */
2003 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &ratios);
2007 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT1, &counts);
2011 for (i = 0; i < 64; i += 8) {
2012 group_size = (counts >> i) & 0xFF;
2013 if (group_size >= size) {
2014 *turbo_freq = (ratios >> i) & 0xFF;
2022 static bool core_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq)
2027 err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq);
2031 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &msr);
2035 *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */
2036 *turbo_freq = (msr >> 24) & 0xFF; /* 4C turbo */
2038 /* The CPU may have less than 4 cores */
2040 *turbo_freq = msr & 0xFF; /* 1C turbo */
2045 static bool intel_set_max_freq_ratio(void)
2047 u64 base_freq, turbo_freq;
2050 if (slv_set_max_freq_ratio(&base_freq, &turbo_freq))
2053 if (x86_match_cpu(has_glm_turbo_ratio_limits) &&
2054 skx_set_max_freq_ratio(&base_freq, &turbo_freq, 1))
2057 if (x86_match_cpu(has_knl_turbo_ratio_limits) &&
2058 knl_set_max_freq_ratio(&base_freq, &turbo_freq, 1))
2061 if (x86_match_cpu(has_skx_turbo_ratio_limits) &&
2062 skx_set_max_freq_ratio(&base_freq, &turbo_freq, 4))
2065 if (core_set_max_freq_ratio(&base_freq, &turbo_freq))
2072 * Some hypervisors advertise X86_FEATURE_APERFMPERF
2073 * but then fill all MSR's with zeroes.
2074 * Some CPUs have turbo boost but don't declare any turbo ratio
2075 * in MSR_TURBO_RATIO_LIMIT.
2077 if (!base_freq || !turbo_freq) {
2078 pr_debug("Couldn't determine cpu base or turbo frequency, necessary for scale-invariant accounting.\n");
2082 turbo_ratio = div_u64(turbo_freq * SCHED_CAPACITY_SCALE, base_freq);
2084 pr_debug("Non-zero turbo and base frequencies led to a 0 ratio.\n");
2088 arch_turbo_freq_ratio = turbo_ratio;
2089 arch_set_max_freq_ratio(turbo_disabled());
2094 static void init_counter_refs(void)
2098 rdmsrl(MSR_IA32_APERF, aperf);
2099 rdmsrl(MSR_IA32_MPERF, mperf);
2101 this_cpu_write(arch_prev_aperf, aperf);
2102 this_cpu_write(arch_prev_mperf, mperf);
2105 #ifdef CONFIG_PM_SLEEP
2106 static struct syscore_ops freq_invariance_syscore_ops = {
2107 .resume = init_counter_refs,
2110 static void register_freq_invariance_syscore_ops(void)
2112 /* Bail out if registered already. */
2113 if (freq_invariance_syscore_ops.node.prev)
2116 register_syscore_ops(&freq_invariance_syscore_ops);
2119 static inline void register_freq_invariance_syscore_ops(void) {}
2122 void init_freq_invariance(bool secondary, bool cppc_ready)
2126 if (!boot_cpu_has(X86_FEATURE_APERFMPERF))
2130 if (static_branch_likely(&arch_scale_freq_key)) {
2131 init_counter_refs();
2136 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2137 ret = intel_set_max_freq_ratio();
2138 else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
2142 ret = amd_set_max_freq_ratio(&arch_turbo_freq_ratio);
2146 init_counter_refs();
2147 static_branch_enable(&arch_scale_freq_key);
2148 register_freq_invariance_syscore_ops();
2149 pr_info("Estimated ratio of average max frequency by base frequency (times 1024): %llu\n", arch_max_freq_ratio);
2151 pr_debug("Couldn't determine max cpu frequency, necessary for scale-invariant accounting.\n");
2155 static void disable_freq_invariance_workfn(struct work_struct *work)
2157 static_branch_disable(&arch_scale_freq_key);
2160 static DECLARE_WORK(disable_freq_invariance_work,
2161 disable_freq_invariance_workfn);
2163 DEFINE_PER_CPU(unsigned long, arch_freq_scale) = SCHED_CAPACITY_SCALE;
2165 void arch_scale_freq_tick(void)
2171 if (!arch_scale_freq_invariant())
2174 rdmsrl(MSR_IA32_APERF, aperf);
2175 rdmsrl(MSR_IA32_MPERF, mperf);
2177 acnt = aperf - this_cpu_read(arch_prev_aperf);
2178 mcnt = mperf - this_cpu_read(arch_prev_mperf);
2180 this_cpu_write(arch_prev_aperf, aperf);
2181 this_cpu_write(arch_prev_mperf, mperf);
2183 if (check_shl_overflow(acnt, 2*SCHED_CAPACITY_SHIFT, &acnt))
2186 if (check_mul_overflow(mcnt, arch_max_freq_ratio, &mcnt) || !mcnt)
2189 freq_scale = div64_u64(acnt, mcnt);
2193 if (freq_scale > SCHED_CAPACITY_SCALE)
2194 freq_scale = SCHED_CAPACITY_SCALE;
2196 this_cpu_write(arch_freq_scale, freq_scale);
2200 pr_warn("Scheduler frequency invariance went wobbly, disabling!\n");
2201 schedule_work(&disable_freq_invariance_work);
2203 #endif /* CONFIG_X86_64 */