1 // SPDX-License-Identifier: GPL-2.0
3 * AMD Encrypted Register State Support
5 * Author: Joerg Roedel <jroedel@suse.de>
7 * This file is not compiled stand-alone. It contains code shared
8 * between the pre-decompression boot code and the running Linux kernel
9 * and is included directly into both code-bases.
12 #ifndef __BOOT_COMPRESSED
13 #define error(v) pr_err(v)
14 #define has_cpuflag(f) boot_cpu_has(f)
17 #define WARN(condition, format...) (!!(condition))
20 /* I/O parameters for CPUID-related helpers */
31 * Individual entries of the SNP CPUID table, as defined by the SNP
32 * Firmware ABI, Revision 0.9, Section 7.1, Table 14.
47 * SNP CPUID table, as defined by the SNP Firmware ABI, Revision 0.9,
48 * Section 8.14.2.6. Also noted there is the SNP firmware-enforced limit
49 * of 64 entries per CPUID table.
51 #define SNP_CPUID_COUNT_MAX 64
53 struct snp_cpuid_table {
57 struct snp_cpuid_fn fn[SNP_CPUID_COUNT_MAX];
61 * Since feature negotiation related variables are set early in the boot
62 * process they must reside in the .data section so as not to be zeroed
63 * out when the .bss section is later cleared.
65 * GHCB protocol version negotiated with the hypervisor.
67 static u16 ghcb_version __ro_after_init;
69 /* Copy of the SNP firmware's CPUID page. */
70 static struct snp_cpuid_table cpuid_table_copy __ro_after_init;
73 * These will be initialized based on CPUID table so that non-present
74 * all-zero leaves (for sparse tables) can be differentiated from
75 * invalid/out-of-range leaves. This is needed since all-zero leaves
76 * still need to be post-processed.
78 static u32 cpuid_std_range_max __ro_after_init;
79 static u32 cpuid_hyp_range_max __ro_after_init;
80 static u32 cpuid_ext_range_max __ro_after_init;
82 static bool __init sev_es_check_cpu_features(void)
84 if (!has_cpuflag(X86_FEATURE_RDRAND)) {
85 error("RDRAND instruction not supported - no trusted source of randomness available\n");
92 static void __noreturn sev_es_terminate(unsigned int set, unsigned int reason)
94 u64 val = GHCB_MSR_TERM_REQ;
96 /* Tell the hypervisor what went wrong. */
97 val |= GHCB_SEV_TERM_REASON(set, reason);
99 /* Request Guest Termination from Hypvervisor */
100 sev_es_wr_ghcb_msr(val);
104 asm volatile("hlt\n" : : : "memory");
108 * The hypervisor features are available from GHCB version 2 onward.
110 static u64 get_hv_features(void)
114 if (ghcb_version < 2)
117 sev_es_wr_ghcb_msr(GHCB_MSR_HV_FT_REQ);
120 val = sev_es_rd_ghcb_msr();
121 if (GHCB_RESP_CODE(val) != GHCB_MSR_HV_FT_RESP)
124 return GHCB_MSR_HV_FT_RESP_VAL(val);
127 static void snp_register_ghcb_early(unsigned long paddr)
129 unsigned long pfn = paddr >> PAGE_SHIFT;
132 sev_es_wr_ghcb_msr(GHCB_MSR_REG_GPA_REQ_VAL(pfn));
135 val = sev_es_rd_ghcb_msr();
137 /* If the response GPA is not ours then abort the guest */
138 if ((GHCB_RESP_CODE(val) != GHCB_MSR_REG_GPA_RESP) ||
139 (GHCB_MSR_REG_GPA_RESP_VAL(val) != pfn))
140 sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_REGISTER);
143 static bool sev_es_negotiate_protocol(void)
147 /* Do the GHCB protocol version negotiation */
148 sev_es_wr_ghcb_msr(GHCB_MSR_SEV_INFO_REQ);
150 val = sev_es_rd_ghcb_msr();
152 if (GHCB_MSR_INFO(val) != GHCB_MSR_SEV_INFO_RESP)
155 if (GHCB_MSR_PROTO_MAX(val) < GHCB_PROTOCOL_MIN ||
156 GHCB_MSR_PROTO_MIN(val) > GHCB_PROTOCOL_MAX)
159 ghcb_version = min_t(size_t, GHCB_MSR_PROTO_MAX(val), GHCB_PROTOCOL_MAX);
164 static __always_inline void vc_ghcb_invalidate(struct ghcb *ghcb)
166 ghcb->save.sw_exit_code = 0;
167 __builtin_memset(ghcb->save.valid_bitmap, 0, sizeof(ghcb->save.valid_bitmap));
170 static bool vc_decoding_needed(unsigned long exit_code)
172 /* Exceptions don't require to decode the instruction */
173 return !(exit_code >= SVM_EXIT_EXCP_BASE &&
174 exit_code <= SVM_EXIT_LAST_EXCP);
177 static enum es_result vc_init_em_ctxt(struct es_em_ctxt *ctxt,
178 struct pt_regs *regs,
179 unsigned long exit_code)
181 enum es_result ret = ES_OK;
183 memset(ctxt, 0, sizeof(*ctxt));
186 if (vc_decoding_needed(exit_code))
187 ret = vc_decode_insn(ctxt);
192 static void vc_finish_insn(struct es_em_ctxt *ctxt)
194 ctxt->regs->ip += ctxt->insn.length;
197 static enum es_result verify_exception_info(struct ghcb *ghcb, struct es_em_ctxt *ctxt)
201 ret = ghcb->save.sw_exit_info_1 & GENMASK_ULL(31, 0);
206 u64 info = ghcb->save.sw_exit_info_2;
207 unsigned long v = info & SVM_EVTINJ_VEC_MASK;
209 /* Check if exception information from hypervisor is sane. */
210 if ((info & SVM_EVTINJ_VALID) &&
211 ((v == X86_TRAP_GP) || (v == X86_TRAP_UD)) &&
212 ((info & SVM_EVTINJ_TYPE_MASK) == SVM_EVTINJ_TYPE_EXEPT)) {
215 if (info & SVM_EVTINJ_VALID_ERR)
216 ctxt->fi.error_code = info >> 32;
225 static enum es_result sev_es_ghcb_hv_call(struct ghcb *ghcb,
226 struct es_em_ctxt *ctxt,
227 u64 exit_code, u64 exit_info_1,
230 /* Fill in protocol and format specifiers */
231 ghcb->protocol_version = ghcb_version;
232 ghcb->ghcb_usage = GHCB_DEFAULT_USAGE;
234 ghcb_set_sw_exit_code(ghcb, exit_code);
235 ghcb_set_sw_exit_info_1(ghcb, exit_info_1);
236 ghcb_set_sw_exit_info_2(ghcb, exit_info_2);
238 sev_es_wr_ghcb_msr(__pa(ghcb));
241 return verify_exception_info(ghcb, ctxt);
244 static int __sev_cpuid_hv(u32 fn, int reg_idx, u32 *reg)
248 sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(fn, reg_idx));
250 val = sev_es_rd_ghcb_msr();
251 if (GHCB_RESP_CODE(val) != GHCB_MSR_CPUID_RESP)
259 static int __sev_cpuid_hv_msr(struct cpuid_leaf *leaf)
264 * MSR protocol does not support fetching non-zero subfunctions, but is
265 * sufficient to handle current early-boot cases. Should that change,
266 * make sure to report an error rather than ignoring the index and
267 * grabbing random values. If this issue arises in the future, handling
268 * can be added here to use GHCB-page protocol for cases that occur late
269 * enough in boot that GHCB page is available.
271 if (cpuid_function_is_indexed(leaf->fn) && leaf->subfn)
274 ret = __sev_cpuid_hv(leaf->fn, GHCB_CPUID_REQ_EAX, &leaf->eax);
275 ret = ret ? : __sev_cpuid_hv(leaf->fn, GHCB_CPUID_REQ_EBX, &leaf->ebx);
276 ret = ret ? : __sev_cpuid_hv(leaf->fn, GHCB_CPUID_REQ_ECX, &leaf->ecx);
277 ret = ret ? : __sev_cpuid_hv(leaf->fn, GHCB_CPUID_REQ_EDX, &leaf->edx);
282 static int __sev_cpuid_hv_ghcb(struct ghcb *ghcb, struct es_em_ctxt *ctxt, struct cpuid_leaf *leaf)
284 u32 cr4 = native_read_cr4();
287 ghcb_set_rax(ghcb, leaf->fn);
288 ghcb_set_rcx(ghcb, leaf->subfn);
290 if (cr4 & X86_CR4_OSXSAVE)
291 /* Safe to read xcr0 */
292 ghcb_set_xcr0(ghcb, xgetbv(XCR_XFEATURE_ENABLED_MASK));
294 /* xgetbv will cause #UD - use reset value for xcr0 */
295 ghcb_set_xcr0(ghcb, 1);
297 ret = sev_es_ghcb_hv_call(ghcb, ctxt, SVM_EXIT_CPUID, 0, 0);
301 if (!(ghcb_rax_is_valid(ghcb) &&
302 ghcb_rbx_is_valid(ghcb) &&
303 ghcb_rcx_is_valid(ghcb) &&
304 ghcb_rdx_is_valid(ghcb)))
307 leaf->eax = ghcb->save.rax;
308 leaf->ebx = ghcb->save.rbx;
309 leaf->ecx = ghcb->save.rcx;
310 leaf->edx = ghcb->save.rdx;
315 static int sev_cpuid_hv(struct ghcb *ghcb, struct es_em_ctxt *ctxt, struct cpuid_leaf *leaf)
317 return ghcb ? __sev_cpuid_hv_ghcb(ghcb, ctxt, leaf)
318 : __sev_cpuid_hv_msr(leaf);
322 * This may be called early while still running on the initial identity
323 * mapping. Use RIP-relative addressing to obtain the correct address
324 * while running with the initial identity mapping as well as the
325 * switch-over to kernel virtual addresses later.
327 static const struct snp_cpuid_table *snp_cpuid_get_table(void)
331 asm ("lea cpuid_table_copy(%%rip), %0"
333 : "p" (&cpuid_table_copy));
339 * The SNP Firmware ABI, Revision 0.9, Section 7.1, details the use of
340 * XCR0_IN and XSS_IN to encode multiple versions of 0xD subfunctions 0
341 * and 1 based on the corresponding features enabled by a particular
342 * combination of XCR0 and XSS registers so that a guest can look up the
343 * version corresponding to the features currently enabled in its XCR0/XSS
344 * registers. The only values that differ between these versions/table
345 * entries is the enabled XSAVE area size advertised via EBX.
347 * While hypervisors may choose to make use of this support, it is more
348 * robust/secure for a guest to simply find the entry corresponding to the
349 * base/legacy XSAVE area size (XCR0=1 or XCR0=3), and then calculate the
350 * XSAVE area size using subfunctions 2 through 64, as documented in APM
351 * Volume 3, Rev 3.31, Appendix E.3.8, which is what is done here.
353 * Since base/legacy XSAVE area size is documented as 0x240, use that value
354 * directly rather than relying on the base size in the CPUID table.
356 * Return: XSAVE area size on success, 0 otherwise.
358 static u32 snp_cpuid_calc_xsave_size(u64 xfeatures_en, bool compacted)
360 const struct snp_cpuid_table *cpuid_table = snp_cpuid_get_table();
361 u64 xfeatures_found = 0;
362 u32 xsave_size = 0x240;
365 for (i = 0; i < cpuid_table->count; i++) {
366 const struct snp_cpuid_fn *e = &cpuid_table->fn[i];
368 if (!(e->eax_in == 0xD && e->ecx_in > 1 && e->ecx_in < 64))
370 if (!(xfeatures_en & (BIT_ULL(e->ecx_in))))
372 if (xfeatures_found & (BIT_ULL(e->ecx_in)))
375 xfeatures_found |= (BIT_ULL(e->ecx_in));
378 xsave_size += e->eax;
380 xsave_size = max(xsave_size, e->eax + e->ebx);
384 * Either the guest set unsupported XCR0/XSS bits, or the corresponding
385 * entries in the CPUID table were not present. This is not a valid
388 if (xfeatures_found != (xfeatures_en & GENMASK_ULL(63, 2)))
395 snp_cpuid_get_validated_func(struct cpuid_leaf *leaf)
397 const struct snp_cpuid_table *cpuid_table = snp_cpuid_get_table();
400 for (i = 0; i < cpuid_table->count; i++) {
401 const struct snp_cpuid_fn *e = &cpuid_table->fn[i];
403 if (e->eax_in != leaf->fn)
406 if (cpuid_function_is_indexed(leaf->fn) && e->ecx_in != leaf->subfn)
410 * For 0xD subfunctions 0 and 1, only use the entry corresponding
411 * to the base/legacy XSAVE area size (XCR0=1 or XCR0=3, XSS=0).
412 * See the comments above snp_cpuid_calc_xsave_size() for more
415 if (e->eax_in == 0xD && (e->ecx_in == 0 || e->ecx_in == 1))
416 if (!(e->xcr0_in == 1 || e->xcr0_in == 3) || e->xss_in)
430 static void snp_cpuid_hv(struct ghcb *ghcb, struct es_em_ctxt *ctxt, struct cpuid_leaf *leaf)
432 if (sev_cpuid_hv(ghcb, ctxt, leaf))
433 sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_CPUID_HV);
436 static int snp_cpuid_postprocess(struct ghcb *ghcb, struct es_em_ctxt *ctxt,
437 struct cpuid_leaf *leaf)
439 struct cpuid_leaf leaf_hv = *leaf;
443 snp_cpuid_hv(ghcb, ctxt, &leaf_hv);
445 /* initial APIC ID */
446 leaf->ebx = (leaf_hv.ebx & GENMASK(31, 24)) | (leaf->ebx & GENMASK(23, 0));
447 /* APIC enabled bit */
448 leaf->edx = (leaf_hv.edx & BIT(9)) | (leaf->edx & ~BIT(9));
450 /* OSXSAVE enabled bit */
451 if (native_read_cr4() & X86_CR4_OSXSAVE)
452 leaf->ecx |= BIT(27);
455 /* OSPKE enabled bit */
456 leaf->ecx &= ~BIT(4);
457 if (native_read_cr4() & X86_CR4_PKE)
462 snp_cpuid_hv(ghcb, ctxt, &leaf_hv);
464 /* extended APIC ID */
465 leaf->edx = leaf_hv.edx;
468 bool compacted = false;
469 u64 xcr0 = 1, xss = 0;
472 if (leaf->subfn != 0 && leaf->subfn != 1)
475 if (native_read_cr4() & X86_CR4_OSXSAVE)
476 xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
477 if (leaf->subfn == 1) {
478 /* Get XSS value if XSAVES is enabled. */
479 if (leaf->eax & BIT(3)) {
480 unsigned long lo, hi;
482 asm volatile("rdmsr" : "=a" (lo), "=d" (hi)
483 : "c" (MSR_IA32_XSS));
484 xss = (hi << 32) | lo;
488 * The PPR and APM aren't clear on what size should be
489 * encoded in 0xD:0x1:EBX when compaction is not enabled
490 * by either XSAVEC (feature bit 1) or XSAVES (feature
491 * bit 3) since SNP-capable hardware has these feature
492 * bits fixed as 1. KVM sets it to 0 in this case, but
493 * to avoid this becoming an issue it's safer to simply
494 * treat this as unsupported for SNP guests.
496 if (!(leaf->eax & (BIT(1) | BIT(3))))
502 xsave_size = snp_cpuid_calc_xsave_size(xcr0 | xss, compacted);
506 leaf->ebx = xsave_size;
510 snp_cpuid_hv(ghcb, ctxt, &leaf_hv);
512 /* extended APIC ID */
513 leaf->eax = leaf_hv.eax;
515 leaf->ebx = (leaf->ebx & GENMASK(31, 8)) | (leaf_hv.ebx & GENMASK(7, 0));
517 leaf->ecx = (leaf->ecx & GENMASK(31, 8)) | (leaf_hv.ecx & GENMASK(7, 0));
520 /* No fix-ups needed, use values as-is. */
528 * Returns -EOPNOTSUPP if feature not enabled. Any other non-zero return value
529 * should be treated as fatal by caller.
531 static int snp_cpuid(struct ghcb *ghcb, struct es_em_ctxt *ctxt, struct cpuid_leaf *leaf)
533 const struct snp_cpuid_table *cpuid_table = snp_cpuid_get_table();
535 if (!cpuid_table->count)
538 if (!snp_cpuid_get_validated_func(leaf)) {
540 * Some hypervisors will avoid keeping track of CPUID entries
541 * where all values are zero, since they can be handled the
542 * same as out-of-range values (all-zero). This is useful here
543 * as well as it allows virtually all guest configurations to
544 * work using a single SNP CPUID table.
546 * To allow for this, there is a need to distinguish between
547 * out-of-range entries and in-range zero entries, since the
548 * CPUID table entries are only a template that may need to be
549 * augmented with additional values for things like
550 * CPU-specific information during post-processing. So if it's
551 * not in the table, set the values to zero. Then, if they are
552 * within a valid CPUID range, proceed with post-processing
553 * using zeros as the initial values. Otherwise, skip
554 * post-processing and just return zeros immediately.
556 leaf->eax = leaf->ebx = leaf->ecx = leaf->edx = 0;
558 /* Skip post-processing for out-of-range zero leafs. */
559 if (!(leaf->fn <= cpuid_std_range_max ||
560 (leaf->fn >= 0x40000000 && leaf->fn <= cpuid_hyp_range_max) ||
561 (leaf->fn >= 0x80000000 && leaf->fn <= cpuid_ext_range_max)))
565 return snp_cpuid_postprocess(ghcb, ctxt, leaf);
569 * Boot VC Handler - This is the first VC handler during boot, there is no GHCB
570 * page yet, so it only supports the MSR based communication with the
571 * hypervisor and only the CPUID exit-code.
573 void __init do_vc_no_ghcb(struct pt_regs *regs, unsigned long exit_code)
575 unsigned int subfn = lower_bits(regs->cx, 32);
576 unsigned int fn = lower_bits(regs->ax, 32);
577 struct cpuid_leaf leaf;
580 /* Only CPUID is supported via MSR protocol */
581 if (exit_code != SVM_EXIT_CPUID)
587 ret = snp_cpuid(NULL, NULL, &leaf);
591 if (ret != -EOPNOTSUPP)
594 if (__sev_cpuid_hv_msr(&leaf))
604 * This is a VC handler and the #VC is only raised when SEV-ES is
605 * active, which means SEV must be active too. Do sanity checks on the
606 * CPUID results to make sure the hypervisor does not trick the kernel
607 * into the no-sev path. This could map sensitive data unencrypted and
608 * make it accessible to the hypervisor.
610 * In particular, check for:
611 * - Availability of CPUID leaf 0x8000001f
614 * The hypervisor might still report the wrong C-bit position, but this
615 * can't be checked here.
618 if (fn == 0x80000000 && (regs->ax < 0x8000001f))
621 else if ((fn == 0x8000001f && !(regs->ax & BIT(1))))
625 /* Skip over the CPUID two-byte opcode */
631 /* Terminate the guest */
632 sev_es_terminate(SEV_TERM_SET_GEN, GHCB_SEV_ES_GEN_REQ);
635 static enum es_result vc_insn_string_read(struct es_em_ctxt *ctxt,
636 void *src, char *buf,
637 unsigned int data_size,
641 int i, b = backwards ? -1 : 1;
642 enum es_result ret = ES_OK;
644 for (i = 0; i < count; i++) {
645 void *s = src + (i * data_size * b);
646 char *d = buf + (i * data_size);
648 ret = vc_read_mem(ctxt, s, d, data_size);
656 static enum es_result vc_insn_string_write(struct es_em_ctxt *ctxt,
657 void *dst, char *buf,
658 unsigned int data_size,
662 int i, s = backwards ? -1 : 1;
663 enum es_result ret = ES_OK;
665 for (i = 0; i < count; i++) {
666 void *d = dst + (i * data_size * s);
667 char *b = buf + (i * data_size);
669 ret = vc_write_mem(ctxt, d, b, data_size);
677 #define IOIO_TYPE_STR BIT(2)
678 #define IOIO_TYPE_IN 1
679 #define IOIO_TYPE_INS (IOIO_TYPE_IN | IOIO_TYPE_STR)
680 #define IOIO_TYPE_OUT 0
681 #define IOIO_TYPE_OUTS (IOIO_TYPE_OUT | IOIO_TYPE_STR)
683 #define IOIO_REP BIT(3)
685 #define IOIO_ADDR_64 BIT(9)
686 #define IOIO_ADDR_32 BIT(8)
687 #define IOIO_ADDR_16 BIT(7)
689 #define IOIO_DATA_32 BIT(6)
690 #define IOIO_DATA_16 BIT(5)
691 #define IOIO_DATA_8 BIT(4)
693 #define IOIO_SEG_ES (0 << 10)
694 #define IOIO_SEG_DS (3 << 10)
696 static enum es_result vc_ioio_exitinfo(struct es_em_ctxt *ctxt, u64 *exitinfo)
698 struct insn *insn = &ctxt->insn;
701 switch (insn->opcode.bytes[0]) {
705 *exitinfo |= IOIO_TYPE_INS;
706 *exitinfo |= IOIO_SEG_ES;
707 *exitinfo |= (ctxt->regs->dx & 0xffff) << 16;
713 *exitinfo |= IOIO_TYPE_OUTS;
714 *exitinfo |= IOIO_SEG_DS;
715 *exitinfo |= (ctxt->regs->dx & 0xffff) << 16;
718 /* IN immediate opcodes */
721 *exitinfo |= IOIO_TYPE_IN;
722 *exitinfo |= (u8)insn->immediate.value << 16;
725 /* OUT immediate opcodes */
728 *exitinfo |= IOIO_TYPE_OUT;
729 *exitinfo |= (u8)insn->immediate.value << 16;
732 /* IN register opcodes */
735 *exitinfo |= IOIO_TYPE_IN;
736 *exitinfo |= (ctxt->regs->dx & 0xffff) << 16;
739 /* OUT register opcodes */
742 *exitinfo |= IOIO_TYPE_OUT;
743 *exitinfo |= (ctxt->regs->dx & 0xffff) << 16;
747 return ES_DECODE_FAILED;
750 switch (insn->opcode.bytes[0]) {
757 /* Single byte opcodes */
758 *exitinfo |= IOIO_DATA_8;
761 /* Length determined by instruction parsing */
762 *exitinfo |= (insn->opnd_bytes == 2) ? IOIO_DATA_16
765 switch (insn->addr_bytes) {
767 *exitinfo |= IOIO_ADDR_16;
770 *exitinfo |= IOIO_ADDR_32;
773 *exitinfo |= IOIO_ADDR_64;
777 if (insn_has_rep_prefix(insn))
778 *exitinfo |= IOIO_REP;
783 static enum es_result vc_handle_ioio(struct ghcb *ghcb, struct es_em_ctxt *ctxt)
785 struct pt_regs *regs = ctxt->regs;
786 u64 exit_info_1, exit_info_2;
789 ret = vc_ioio_exitinfo(ctxt, &exit_info_1);
793 if (exit_info_1 & IOIO_TYPE_STR) {
797 bool df = ((regs->flags & X86_EFLAGS_DF) == X86_EFLAGS_DF);
798 unsigned int io_bytes, exit_bytes;
799 unsigned int ghcb_count, op_count;
800 unsigned long es_base;
804 * For the string variants with rep prefix the amount of in/out
805 * operations per #VC exception is limited so that the kernel
806 * has a chance to take interrupts and re-schedule while the
807 * instruction is emulated.
809 io_bytes = (exit_info_1 >> 4) & 0x7;
810 ghcb_count = sizeof(ghcb->shared_buffer) / io_bytes;
812 op_count = (exit_info_1 & IOIO_REP) ? regs->cx : 1;
813 exit_info_2 = min(op_count, ghcb_count);
814 exit_bytes = exit_info_2 * io_bytes;
816 es_base = insn_get_seg_base(ctxt->regs, INAT_SEG_REG_ES);
818 /* Read bytes of OUTS into the shared buffer */
819 if (!(exit_info_1 & IOIO_TYPE_IN)) {
820 ret = vc_insn_string_read(ctxt,
821 (void *)(es_base + regs->si),
822 ghcb->shared_buffer, io_bytes,
829 * Issue an VMGEXIT to the HV to consume the bytes from the
830 * shared buffer or to have it write them into the shared buffer
831 * depending on the instruction: OUTS or INS.
833 sw_scratch = __pa(ghcb) + offsetof(struct ghcb, shared_buffer);
834 ghcb_set_sw_scratch(ghcb, sw_scratch);
835 ret = sev_es_ghcb_hv_call(ghcb, ctxt, SVM_EXIT_IOIO,
836 exit_info_1, exit_info_2);
840 /* Read bytes from shared buffer into the guest's destination. */
841 if (exit_info_1 & IOIO_TYPE_IN) {
842 ret = vc_insn_string_write(ctxt,
843 (void *)(es_base + regs->di),
844 ghcb->shared_buffer, io_bytes,
850 regs->di -= exit_bytes;
852 regs->di += exit_bytes;
855 regs->si -= exit_bytes;
857 regs->si += exit_bytes;
860 if (exit_info_1 & IOIO_REP)
861 regs->cx -= exit_info_2;
863 ret = regs->cx ? ES_RETRY : ES_OK;
867 /* IN/OUT into/from rAX */
869 int bits = (exit_info_1 & 0x70) >> 1;
872 if (!(exit_info_1 & IOIO_TYPE_IN))
873 rax = lower_bits(regs->ax, bits);
875 ghcb_set_rax(ghcb, rax);
877 ret = sev_es_ghcb_hv_call(ghcb, ctxt, SVM_EXIT_IOIO, exit_info_1, 0);
881 if (exit_info_1 & IOIO_TYPE_IN) {
882 if (!ghcb_rax_is_valid(ghcb))
884 regs->ax = lower_bits(ghcb->save.rax, bits);
891 static int vc_handle_cpuid_snp(struct ghcb *ghcb, struct es_em_ctxt *ctxt)
893 struct pt_regs *regs = ctxt->regs;
894 struct cpuid_leaf leaf;
898 leaf.subfn = regs->cx;
899 ret = snp_cpuid(ghcb, ctxt, &leaf);
910 static enum es_result vc_handle_cpuid(struct ghcb *ghcb,
911 struct es_em_ctxt *ctxt)
913 struct pt_regs *regs = ctxt->regs;
914 u32 cr4 = native_read_cr4();
918 snp_cpuid_ret = vc_handle_cpuid_snp(ghcb, ctxt);
921 if (snp_cpuid_ret != -EOPNOTSUPP)
924 ghcb_set_rax(ghcb, regs->ax);
925 ghcb_set_rcx(ghcb, regs->cx);
927 if (cr4 & X86_CR4_OSXSAVE)
928 /* Safe to read xcr0 */
929 ghcb_set_xcr0(ghcb, xgetbv(XCR_XFEATURE_ENABLED_MASK));
931 /* xgetbv will cause #GP - use reset value for xcr0 */
932 ghcb_set_xcr0(ghcb, 1);
934 ret = sev_es_ghcb_hv_call(ghcb, ctxt, SVM_EXIT_CPUID, 0, 0);
938 if (!(ghcb_rax_is_valid(ghcb) &&
939 ghcb_rbx_is_valid(ghcb) &&
940 ghcb_rcx_is_valid(ghcb) &&
941 ghcb_rdx_is_valid(ghcb)))
944 regs->ax = ghcb->save.rax;
945 regs->bx = ghcb->save.rbx;
946 regs->cx = ghcb->save.rcx;
947 regs->dx = ghcb->save.rdx;
952 static enum es_result vc_handle_rdtsc(struct ghcb *ghcb,
953 struct es_em_ctxt *ctxt,
954 unsigned long exit_code)
956 bool rdtscp = (exit_code == SVM_EXIT_RDTSCP);
959 ret = sev_es_ghcb_hv_call(ghcb, ctxt, exit_code, 0, 0);
963 if (!(ghcb_rax_is_valid(ghcb) && ghcb_rdx_is_valid(ghcb) &&
964 (!rdtscp || ghcb_rcx_is_valid(ghcb))))
967 ctxt->regs->ax = ghcb->save.rax;
968 ctxt->regs->dx = ghcb->save.rdx;
970 ctxt->regs->cx = ghcb->save.rcx;
975 struct cc_setup_data {
976 struct setup_data header;
981 * Search for a Confidential Computing blob passed in as a setup_data entry
982 * via the Linux Boot Protocol.
984 static struct cc_blob_sev_info *find_cc_blob_setup_data(struct boot_params *bp)
986 struct cc_setup_data *sd = NULL;
987 struct setup_data *hdr;
989 hdr = (struct setup_data *)bp->hdr.setup_data;
992 if (hdr->type == SETUP_CC_BLOB) {
993 sd = (struct cc_setup_data *)hdr;
994 return (struct cc_blob_sev_info *)(unsigned long)sd->cc_blob_address;
996 hdr = (struct setup_data *)hdr->next;
1003 * Initialize the kernel's copy of the SNP CPUID table, and set up the
1004 * pointer that will be used to access it.
1006 * Maintaining a direct mapping of the SNP CPUID table used by firmware would
1007 * be possible as an alternative, but the approach is brittle since the
1008 * mapping needs to be updated in sync with all the changes to virtual memory
1009 * layout and related mapping facilities throughout the boot process.
1011 static void __init setup_cpuid_table(const struct cc_blob_sev_info *cc_info)
1013 const struct snp_cpuid_table *cpuid_table_fw, *cpuid_table;
1016 if (!cc_info || !cc_info->cpuid_phys || cc_info->cpuid_len < PAGE_SIZE)
1017 sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_CPUID);
1019 cpuid_table_fw = (const struct snp_cpuid_table *)cc_info->cpuid_phys;
1020 if (!cpuid_table_fw->count || cpuid_table_fw->count > SNP_CPUID_COUNT_MAX)
1021 sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_CPUID);
1023 cpuid_table = snp_cpuid_get_table();
1024 memcpy((void *)cpuid_table, cpuid_table_fw, sizeof(*cpuid_table));
1026 /* Initialize CPUID ranges for range-checking. */
1027 for (i = 0; i < cpuid_table->count; i++) {
1028 const struct snp_cpuid_fn *fn = &cpuid_table->fn[i];
1030 if (fn->eax_in == 0x0)
1031 cpuid_std_range_max = fn->eax;
1032 else if (fn->eax_in == 0x40000000)
1033 cpuid_hyp_range_max = fn->eax;
1034 else if (fn->eax_in == 0x80000000)
1035 cpuid_ext_range_max = fn->eax;
1039 static void pvalidate_pages(struct snp_psc_desc *desc)
1041 struct psc_entry *e;
1042 unsigned long vaddr;
1048 for (i = 0; i <= desc->hdr.end_entry; i++) {
1049 e = &desc->entries[i];
1051 vaddr = (unsigned long)pfn_to_kaddr(e->gfn);
1052 size = e->pagesize ? RMP_PG_SIZE_2M : RMP_PG_SIZE_4K;
1053 validate = e->operation == SNP_PAGE_STATE_PRIVATE;
1055 rc = pvalidate(vaddr, size, validate);
1056 if (rc == PVALIDATE_FAIL_SIZEMISMATCH && size == RMP_PG_SIZE_2M) {
1057 unsigned long vaddr_end = vaddr + PMD_SIZE;
1059 for (; vaddr < vaddr_end; vaddr += PAGE_SIZE) {
1060 rc = pvalidate(vaddr, RMP_PG_SIZE_4K, validate);
1067 WARN(1, "Failed to validate address 0x%lx ret %d", vaddr, rc);
1068 sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_PVALIDATE);
1073 static int vmgexit_psc(struct ghcb *ghcb, struct snp_psc_desc *desc)
1075 int cur_entry, end_entry, ret = 0;
1076 struct snp_psc_desc *data;
1077 struct es_em_ctxt ctxt;
1079 vc_ghcb_invalidate(ghcb);
1081 /* Copy the input desc into GHCB shared buffer */
1082 data = (struct snp_psc_desc *)ghcb->shared_buffer;
1083 memcpy(ghcb->shared_buffer, desc, min_t(int, GHCB_SHARED_BUF_SIZE, sizeof(*desc)));
1086 * As per the GHCB specification, the hypervisor can resume the guest
1087 * before processing all the entries. Check whether all the entries
1088 * are processed. If not, then keep retrying. Note, the hypervisor
1089 * will update the data memory directly to indicate the status, so
1090 * reference the data->hdr everywhere.
1092 * The strategy here is to wait for the hypervisor to change the page
1093 * state in the RMP table before guest accesses the memory pages. If the
1094 * page state change was not successful, then later memory access will
1095 * result in a crash.
1097 cur_entry = data->hdr.cur_entry;
1098 end_entry = data->hdr.end_entry;
1100 while (data->hdr.cur_entry <= data->hdr.end_entry) {
1101 ghcb_set_sw_scratch(ghcb, (u64)__pa(data));
1103 /* This will advance the shared buffer data points to. */
1104 ret = sev_es_ghcb_hv_call(ghcb, &ctxt, SVM_VMGEXIT_PSC, 0, 0);
1107 * Page State Change VMGEXIT can pass error code through
1110 if (WARN(ret || ghcb->save.sw_exit_info_2,
1111 "SNP: PSC failed ret=%d exit_info_2=%llx\n",
1112 ret, ghcb->save.sw_exit_info_2)) {
1117 /* Verify that reserved bit is not set */
1118 if (WARN(data->hdr.reserved, "Reserved bit is set in the PSC header\n")) {
1124 * Sanity check that entry processing is not going backwards.
1125 * This will happen only if hypervisor is tricking us.
1127 if (WARN(data->hdr.end_entry > end_entry || cur_entry > data->hdr.cur_entry,
1128 "SNP: PSC processing going backward, end_entry %d (got %d) cur_entry %d (got %d)\n",
1129 end_entry, data->hdr.end_entry, cur_entry, data->hdr.cur_entry)) {