2 * Copyright (C) 1995 Linus Torvalds
4 * Pentium III FXSR, SSE support
5 * Gareth Hughes <gareth@valinux.com>, May 2000
10 * CPU hotplug support - ashok.raj@intel.com
14 * This file handles the architecture-dependent parts of process handling..
17 #include <linux/cpu.h>
18 #include <linux/errno.h>
19 #include <linux/sched.h>
20 #include <linux/sched/task.h>
21 #include <linux/sched/task_stack.h>
23 #include <linux/kernel.h>
25 #include <linux/elfcore.h>
26 #include <linux/smp.h>
27 #include <linux/slab.h>
28 #include <linux/user.h>
29 #include <linux/interrupt.h>
30 #include <linux/delay.h>
31 #include <linux/export.h>
32 #include <linux/ptrace.h>
33 #include <linux/notifier.h>
34 #include <linux/kprobes.h>
35 #include <linux/kdebug.h>
36 #include <linux/prctl.h>
37 #include <linux/uaccess.h>
39 #include <linux/ftrace.h>
40 #include <linux/syscalls.h>
42 #include <asm/pgtable.h>
43 #include <asm/processor.h>
44 #include <asm/fpu/internal.h>
45 #include <asm/mmu_context.h>
46 #include <asm/prctl.h>
48 #include <asm/proto.h>
50 #include <asm/syscalls.h>
51 #include <asm/debugreg.h>
52 #include <asm/switch_to.h>
53 #include <asm/xen/hypervisor.h>
55 #include <asm/intel_rdt_sched.h>
56 #include <asm/unistd.h>
57 #ifdef CONFIG_IA32_EMULATION
58 /* Not included via unistd.h */
59 #include <asm/unistd_32_ia32.h>
62 __visible DEFINE_PER_CPU(unsigned long, rsp_scratch);
64 /* Prints also some state that isn't saved in the pt_regs */
65 void __show_regs(struct pt_regs *regs, int all)
67 unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L, fs, gs, shadowgs;
68 unsigned long d0, d1, d2, d3, d6, d7;
69 unsigned int fsindex, gsindex;
70 unsigned int ds, cs, es;
72 printk(KERN_DEFAULT "RIP: %04lx:%pS\n", regs->cs, (void *)regs->ip);
73 printk(KERN_DEFAULT "RSP: %04lx:%016lx EFLAGS: %08lx", regs->ss,
74 regs->sp, regs->flags);
75 if (regs->orig_ax != -1)
76 pr_cont(" ORIG_RAX: %016lx\n", regs->orig_ax);
80 printk(KERN_DEFAULT "RAX: %016lx RBX: %016lx RCX: %016lx\n",
81 regs->ax, regs->bx, regs->cx);
82 printk(KERN_DEFAULT "RDX: %016lx RSI: %016lx RDI: %016lx\n",
83 regs->dx, regs->si, regs->di);
84 printk(KERN_DEFAULT "RBP: %016lx R08: %016lx R09: %016lx\n",
85 regs->bp, regs->r8, regs->r9);
86 printk(KERN_DEFAULT "R10: %016lx R11: %016lx R12: %016lx\n",
87 regs->r10, regs->r11, regs->r12);
88 printk(KERN_DEFAULT "R13: %016lx R14: %016lx R15: %016lx\n",
89 regs->r13, regs->r14, regs->r15);
91 asm("movl %%ds,%0" : "=r" (ds));
92 asm("movl %%cs,%0" : "=r" (cs));
93 asm("movl %%es,%0" : "=r" (es));
94 asm("movl %%fs,%0" : "=r" (fsindex));
95 asm("movl %%gs,%0" : "=r" (gsindex));
97 rdmsrl(MSR_FS_BASE, fs);
98 rdmsrl(MSR_GS_BASE, gs);
99 rdmsrl(MSR_KERNEL_GS_BASE, shadowgs);
109 printk(KERN_DEFAULT "FS: %016lx(%04x) GS:%016lx(%04x) knlGS:%016lx\n",
110 fs, fsindex, gs, gsindex, shadowgs);
111 printk(KERN_DEFAULT "CS: %04x DS: %04x ES: %04x CR0: %016lx\n", cs, ds,
113 printk(KERN_DEFAULT "CR2: %016lx CR3: %016lx CR4: %016lx\n", cr2, cr3,
123 /* Only print out debug registers if they are in their non-default state. */
124 if (!((d0 == 0) && (d1 == 0) && (d2 == 0) && (d3 == 0) &&
125 (d6 == DR6_RESERVED) && (d7 == 0x400))) {
126 printk(KERN_DEFAULT "DR0: %016lx DR1: %016lx DR2: %016lx\n",
128 printk(KERN_DEFAULT "DR3: %016lx DR6: %016lx DR7: %016lx\n",
132 if (boot_cpu_has(X86_FEATURE_OSPKE))
133 printk(KERN_DEFAULT "PKRU: %08x\n", read_pkru());
136 void release_thread(struct task_struct *dead_task)
139 #ifdef CONFIG_MODIFY_LDT_SYSCALL
140 if (dead_task->mm->context.ldt) {
141 pr_warn("WARNING: dead process %s still has LDT? <%p/%d>\n",
143 dead_task->mm->context.ldt->entries,
144 dead_task->mm->context.ldt->nr_entries);
151 enum which_selector {
157 * Saves the FS or GS base for an outgoing thread if FSGSBASE extensions are
158 * not available. The goal is to be reasonably fast on non-FSGSBASE systems.
159 * It's forcibly inlined because it'll generate better code and this function
162 static __always_inline void save_base_legacy(struct task_struct *prev_p,
163 unsigned short selector,
164 enum which_selector which)
166 if (likely(selector == 0)) {
168 * On Intel (without X86_BUG_NULL_SEG), the segment base could
169 * be the pre-existing saved base or it could be zero. On AMD
170 * (with X86_BUG_NULL_SEG), the segment base could be almost
173 * This branch is very hot (it's hit twice on almost every
174 * context switch between 64-bit programs), and avoiding
175 * the RDMSR helps a lot, so we just assume that whatever
176 * value is already saved is correct. This matches historical
177 * Linux behavior, so it won't break existing applications.
179 * To avoid leaking state, on non-X86_BUG_NULL_SEG CPUs, if we
180 * report that the base is zero, it needs to actually be zero:
181 * see the corresponding logic in load_seg_legacy.
185 * If the selector is 1, 2, or 3, then the base is zero on
186 * !X86_BUG_NULL_SEG CPUs and could be anything on
187 * X86_BUG_NULL_SEG CPUs. In the latter case, Linux
188 * has never attempted to preserve the base across context
191 * If selector > 3, then it refers to a real segment, and
192 * saving the base isn't necessary.
195 prev_p->thread.fsbase = 0;
197 prev_p->thread.gsbase = 0;
201 static __always_inline void save_fsgs(struct task_struct *task)
203 savesegment(fs, task->thread.fsindex);
204 savesegment(gs, task->thread.gsindex);
205 save_base_legacy(task, task->thread.fsindex, FS);
206 save_base_legacy(task, task->thread.gsindex, GS);
209 static __always_inline void loadseg(enum which_selector which,
213 loadsegment(fs, sel);
218 static __always_inline void load_seg_legacy(unsigned short prev_index,
219 unsigned long prev_base,
220 unsigned short next_index,
221 unsigned long next_base,
222 enum which_selector which)
224 if (likely(next_index <= 3)) {
226 * The next task is using 64-bit TLS, is not using this
227 * segment at all, or is having fun with arcane CPU features.
229 if (next_base == 0) {
231 * Nasty case: on AMD CPUs, we need to forcibly zero
234 if (static_cpu_has_bug(X86_BUG_NULL_SEG)) {
235 loadseg(which, __USER_DS);
236 loadseg(which, next_index);
239 * We could try to exhaustively detect cases
240 * under which we can skip the segment load,
241 * but there's really only one case that matters
242 * for performance: if both the previous and
243 * next states are fully zeroed, we can skip
246 * (This assumes that prev_base == 0 has no
247 * false positives. This is the case on
250 if (likely(prev_index | next_index | prev_base))
251 loadseg(which, next_index);
254 if (prev_index != next_index)
255 loadseg(which, next_index);
256 wrmsrl(which == FS ? MSR_FS_BASE : MSR_KERNEL_GS_BASE,
261 * The next task is using a real segment. Loading the selector
264 loadseg(which, next_index);
268 int copy_thread_tls(unsigned long clone_flags, unsigned long sp,
269 unsigned long arg, struct task_struct *p, unsigned long tls)
272 struct pt_regs *childregs;
273 struct fork_frame *fork_frame;
274 struct inactive_task_frame *frame;
275 struct task_struct *me = current;
277 childregs = task_pt_regs(p);
278 fork_frame = container_of(childregs, struct fork_frame, regs);
279 frame = &fork_frame->frame;
281 frame->ret_addr = (unsigned long) ret_from_fork;
282 p->thread.sp = (unsigned long) fork_frame;
283 p->thread.io_bitmap_ptr = NULL;
285 savesegment(gs, p->thread.gsindex);
286 p->thread.gsbase = p->thread.gsindex ? 0 : me->thread.gsbase;
287 savesegment(fs, p->thread.fsindex);
288 p->thread.fsbase = p->thread.fsindex ? 0 : me->thread.fsbase;
289 savesegment(es, p->thread.es);
290 savesegment(ds, p->thread.ds);
291 memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps));
293 if (unlikely(p->flags & PF_KTHREAD)) {
295 memset(childregs, 0, sizeof(struct pt_regs));
296 frame->bx = sp; /* function */
301 *childregs = *current_pt_regs();
308 if (unlikely(test_tsk_thread_flag(me, TIF_IO_BITMAP))) {
309 p->thread.io_bitmap_ptr = kmemdup(me->thread.io_bitmap_ptr,
310 IO_BITMAP_BYTES, GFP_KERNEL);
311 if (!p->thread.io_bitmap_ptr) {
312 p->thread.io_bitmap_max = 0;
315 set_tsk_thread_flag(p, TIF_IO_BITMAP);
319 * Set a new TLS for the child thread?
321 if (clone_flags & CLONE_SETTLS) {
322 #ifdef CONFIG_IA32_EMULATION
323 if (in_ia32_syscall())
324 err = do_set_thread_area(p, -1,
325 (struct user_desc __user *)tls, 0);
328 err = do_arch_prctl_64(p, ARCH_SET_FS, tls);
334 if (err && p->thread.io_bitmap_ptr) {
335 kfree(p->thread.io_bitmap_ptr);
336 p->thread.io_bitmap_max = 0;
343 start_thread_common(struct pt_regs *regs, unsigned long new_ip,
344 unsigned long new_sp,
345 unsigned int _cs, unsigned int _ss, unsigned int _ds)
347 WARN_ON_ONCE(regs != current_pt_regs());
349 if (static_cpu_has(X86_BUG_NULL_SEG)) {
350 /* Loading zero below won't clear the base. */
351 loadsegment(fs, __USER_DS);
352 load_gs_index(__USER_DS);
356 loadsegment(es, _ds);
357 loadsegment(ds, _ds);
364 regs->flags = X86_EFLAGS_IF;
369 start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
371 start_thread_common(regs, new_ip, new_sp,
372 __USER_CS, __USER_DS, 0);
376 void compat_start_thread(struct pt_regs *regs, u32 new_ip, u32 new_sp)
378 start_thread_common(regs, new_ip, new_sp,
379 test_thread_flag(TIF_X32)
380 ? __USER_CS : __USER32_CS,
381 __USER_DS, __USER_DS);
386 * switch_to(x,y) should switch tasks from x to y.
388 * This could still be optimized:
389 * - fold all the options into a flag word and test it with a single test.
390 * - could test fs/gs bitsliced
392 * Kprobes not supported here. Set the probe on schedule instead.
393 * Function graph tracer not supported too.
395 __visible __notrace_funcgraph struct task_struct *
396 __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
398 struct thread_struct *prev = &prev_p->thread;
399 struct thread_struct *next = &next_p->thread;
400 struct fpu *prev_fpu = &prev->fpu;
401 struct fpu *next_fpu = &next->fpu;
402 int cpu = smp_processor_id();
403 struct tss_struct *tss = &per_cpu(cpu_tss, cpu);
405 WARN_ON_ONCE(IS_ENABLED(CONFIG_DEBUG_ENTRY) &&
406 this_cpu_read(irq_count) != -1);
408 switch_fpu_prepare(prev_fpu, cpu);
410 /* We must save %fs and %gs before load_TLS() because
411 * %fs and %gs may be cleared by load_TLS().
413 * (e.g. xen_load_tls())
418 * Load TLS before restoring any segments so that segment loads
419 * reference the correct GDT entries.
424 * Leave lazy mode, flushing any hypercalls made here. This
425 * must be done after loading TLS entries in the GDT but before
426 * loading segments that might reference them, and and it must
427 * be done before fpu__restore(), so the TS bit is up to
430 arch_end_context_switch(next_p);
434 * Reading them only returns the selectors, but writing them (if
435 * nonzero) loads the full descriptor from the GDT or LDT. The
436 * LDT for next is loaded in switch_mm, and the GDT is loaded
439 * We therefore need to write new values to the segment
440 * registers on every context switch unless both the new and old
443 * Note that we don't need to do anything for CS and SS, as
444 * those are saved and restored as part of pt_regs.
446 savesegment(es, prev->es);
447 if (unlikely(next->es | prev->es))
448 loadsegment(es, next->es);
450 savesegment(ds, prev->ds);
451 if (unlikely(next->ds | prev->ds))
452 loadsegment(ds, next->ds);
454 load_seg_legacy(prev->fsindex, prev->fsbase,
455 next->fsindex, next->fsbase, FS);
456 load_seg_legacy(prev->gsindex, prev->gsbase,
457 next->gsindex, next->gsbase, GS);
459 switch_fpu_finish(next_fpu, cpu);
462 * Switch the PDA and FPU contexts.
464 this_cpu_write(current_task, next_p);
470 * Now maybe reload the debug registers and handle I/O bitmaps
472 if (unlikely(task_thread_info(next_p)->flags & _TIF_WORK_CTXSW_NEXT ||
473 task_thread_info(prev_p)->flags & _TIF_WORK_CTXSW_PREV))
474 __switch_to_xtra(prev_p, next_p, tss);
478 * On Xen PV, IOPL bits in pt_regs->flags have no effect, and
479 * current_pt_regs()->flags may not match the current task's
480 * intended IOPL. We need to switch it manually.
482 if (unlikely(static_cpu_has(X86_FEATURE_XENPV) &&
483 prev->iopl != next->iopl))
484 xen_set_iopl_mask(next->iopl);
487 if (static_cpu_has_bug(X86_BUG_SYSRET_SS_ATTRS)) {
489 * AMD CPUs have a misfeature: SYSRET sets the SS selector but
490 * does not update the cached descriptor. As a result, if we
491 * do SYSRET while SS is NULL, we'll end up in user mode with
492 * SS apparently equal to __USER_DS but actually unusable.
494 * The straightforward workaround would be to fix it up just
495 * before SYSRET, but that would slow down the system call
496 * fast paths. Instead, we ensure that SS is never NULL in
497 * system call context. We do this by replacing NULL SS
498 * selectors at every context switch. SYSCALL sets up a valid
499 * SS, so the only way to get NULL is to re-enter the kernel
500 * from CPL 3 through an interrupt. Since that can't happen
501 * in the same task as a running syscall, we are guaranteed to
502 * context switch between every interrupt vector entry and a
505 * We read SS first because SS reads are much faster than
506 * writes. Out of caution, we force SS to __KERNEL_DS even if
507 * it previously had a different non-NULL value.
509 unsigned short ss_sel;
510 savesegment(ss, ss_sel);
511 if (ss_sel != __KERNEL_DS)
512 loadsegment(ss, __KERNEL_DS);
515 /* Load the Intel cache allocation PQR MSR. */
516 intel_rdt_sched_in();
521 void set_personality_64bit(void)
523 /* inherit personality from parent */
525 /* Make sure to be in 64bit mode */
526 clear_thread_flag(TIF_IA32);
527 clear_thread_flag(TIF_ADDR32);
528 clear_thread_flag(TIF_X32);
529 /* Pretend that this comes from a 64bit execve */
530 task_pt_regs(current)->orig_ax = __NR_execve;
532 /* Ensure the corresponding mm is not marked. */
534 current->mm->context.ia32_compat = 0;
536 /* TBD: overwrites user setup. Should have two bits.
537 But 64bit processes have always behaved this way,
538 so it's not too bad. The main problem is just that
539 32bit childs are affected again. */
540 current->personality &= ~READ_IMPLIES_EXEC;
543 static void __set_personality_x32(void)
545 #ifdef CONFIG_X86_X32
546 clear_thread_flag(TIF_IA32);
547 set_thread_flag(TIF_X32);
549 current->mm->context.ia32_compat = TIF_X32;
550 current->personality &= ~READ_IMPLIES_EXEC;
552 * in_compat_syscall() uses the presence of the x32 syscall bit
553 * flag to determine compat status. The x86 mmap() code relies on
554 * the syscall bitness so set x32 syscall bit right here to make
555 * in_compat_syscall() work during exec().
557 * Pretend to come from a x32 execve.
559 task_pt_regs(current)->orig_ax = __NR_x32_execve | __X32_SYSCALL_BIT;
560 current->thread.status &= ~TS_COMPAT;
564 static void __set_personality_ia32(void)
566 #ifdef CONFIG_IA32_EMULATION
567 set_thread_flag(TIF_IA32);
568 clear_thread_flag(TIF_X32);
570 current->mm->context.ia32_compat = TIF_IA32;
571 current->personality |= force_personality32;
572 /* Prepare the first "return" to user space */
573 task_pt_regs(current)->orig_ax = __NR_ia32_execve;
574 current->thread.status |= TS_COMPAT;
578 void set_personality_ia32(bool x32)
580 /* Make sure to be in 32bit mode */
581 set_thread_flag(TIF_ADDR32);
584 __set_personality_x32();
586 __set_personality_ia32();
588 EXPORT_SYMBOL_GPL(set_personality_ia32);
590 #ifdef CONFIG_CHECKPOINT_RESTORE
591 static long prctl_map_vdso(const struct vdso_image *image, unsigned long addr)
595 ret = map_vdso_once(image, addr);
599 return (long)image->size;
603 long do_arch_prctl_64(struct task_struct *task, int option, unsigned long arg2)
606 int doit = task == current;
611 if (arg2 >= TASK_SIZE_MAX)
614 task->thread.gsindex = 0;
615 task->thread.gsbase = arg2;
618 ret = wrmsrl_safe(MSR_KERNEL_GS_BASE, arg2);
623 /* Not strictly needed for fs, but do it for symmetry
625 if (arg2 >= TASK_SIZE_MAX)
628 task->thread.fsindex = 0;
629 task->thread.fsbase = arg2;
631 /* set the selector to 0 to not confuse __switch_to */
633 ret = wrmsrl_safe(MSR_FS_BASE, arg2);
641 rdmsrl(MSR_FS_BASE, base);
643 base = task->thread.fsbase;
644 ret = put_user(base, (unsigned long __user *)arg2);
651 rdmsrl(MSR_KERNEL_GS_BASE, base);
653 base = task->thread.gsbase;
654 ret = put_user(base, (unsigned long __user *)arg2);
658 #ifdef CONFIG_CHECKPOINT_RESTORE
659 # ifdef CONFIG_X86_X32_ABI
660 case ARCH_MAP_VDSO_X32:
661 return prctl_map_vdso(&vdso_image_x32, arg2);
663 # if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION
664 case ARCH_MAP_VDSO_32:
665 return prctl_map_vdso(&vdso_image_32, arg2);
667 case ARCH_MAP_VDSO_64:
668 return prctl_map_vdso(&vdso_image_64, arg2);
679 SYSCALL_DEFINE2(arch_prctl, int, option, unsigned long, arg2)
683 ret = do_arch_prctl_64(current, option, arg2);
685 ret = do_arch_prctl_common(current, option, arg2);
690 #ifdef CONFIG_IA32_EMULATION
691 COMPAT_SYSCALL_DEFINE2(arch_prctl, int, option, unsigned long, arg2)
693 return do_arch_prctl_common(current, option, arg2);
697 unsigned long KSTK_ESP(struct task_struct *task)
699 return task_pt_regs(task)->sp;