1 #include <linux/errno.h>
2 #include <linux/kernel.h>
5 #include <linux/prctl.h>
6 #include <linux/slab.h>
7 #include <linux/sched.h>
8 #include <linux/module.h>
10 #include <linux/clockchips.h>
11 #include <linux/random.h>
12 #include <linux/user-return-notifier.h>
13 #include <linux/dmi.h>
14 #include <linux/utsname.h>
15 #include <trace/events/power.h>
16 #include <linux/hw_breakpoint.h>
18 #include <asm/system.h>
20 #include <asm/syscalls.h>
22 #include <asm/uaccess.h>
24 #include <asm/debugreg.h>
26 struct kmem_cache *task_xstate_cachep;
27 EXPORT_SYMBOL_GPL(task_xstate_cachep);
29 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
34 if (fpu_allocated(&src->thread.fpu)) {
35 memset(&dst->thread.fpu, 0, sizeof(dst->thread.fpu));
36 ret = fpu_alloc(&dst->thread.fpu);
39 fpu_copy(&dst->thread.fpu, &src->thread.fpu);
44 void free_thread_xstate(struct task_struct *tsk)
46 fpu_free(&tsk->thread.fpu);
49 void free_thread_info(struct thread_info *ti)
51 free_thread_xstate(ti->task);
52 free_pages((unsigned long)ti, get_order(THREAD_SIZE));
55 void arch_task_cache_init(void)
58 kmem_cache_create("task_xstate", xstate_size,
59 __alignof__(union thread_xstate),
60 SLAB_PANIC | SLAB_NOTRACK, NULL);
64 * Free current thread data structures etc..
66 void exit_thread(void)
68 struct task_struct *me = current;
69 struct thread_struct *t = &me->thread;
70 unsigned long *bp = t->io_bitmap_ptr;
73 struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
75 t->io_bitmap_ptr = NULL;
76 clear_thread_flag(TIF_IO_BITMAP);
78 * Careful, clear this in the TSS too:
80 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
87 void show_regs(struct pt_regs *regs)
90 show_trace(NULL, regs, (unsigned long *)kernel_stack_pointer(regs));
93 void show_regs_common(void)
95 const char *board, *product;
97 board = dmi_get_system_info(DMI_BOARD_NAME);
100 product = dmi_get_system_info(DMI_PRODUCT_NAME);
104 printk(KERN_CONT "\n");
105 printk(KERN_DEFAULT "Pid: %d, comm: %.20s %s %s %.*s %s/%s\n",
106 current->pid, current->comm, print_tainted(),
107 init_utsname()->release,
108 (int)strcspn(init_utsname()->version, " "),
109 init_utsname()->version, board, product);
112 void flush_thread(void)
114 struct task_struct *tsk = current;
116 flush_ptrace_hw_breakpoint(tsk);
117 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
119 * Forget coprocessor state..
121 tsk->fpu_counter = 0;
126 static void hard_disable_TSC(void)
128 write_cr4(read_cr4() | X86_CR4_TSD);
131 void disable_TSC(void)
134 if (!test_and_set_thread_flag(TIF_NOTSC))
136 * Must flip the CPU state synchronously with
137 * TIF_NOTSC in the current running context.
143 static void hard_enable_TSC(void)
145 write_cr4(read_cr4() & ~X86_CR4_TSD);
148 static void enable_TSC(void)
151 if (test_and_clear_thread_flag(TIF_NOTSC))
153 * Must flip the CPU state synchronously with
154 * TIF_NOTSC in the current running context.
160 int get_tsc_mode(unsigned long adr)
164 if (test_thread_flag(TIF_NOTSC))
165 val = PR_TSC_SIGSEGV;
169 return put_user(val, (unsigned int __user *)adr);
172 int set_tsc_mode(unsigned int val)
174 if (val == PR_TSC_SIGSEGV)
176 else if (val == PR_TSC_ENABLE)
184 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
185 struct tss_struct *tss)
187 struct thread_struct *prev, *next;
189 prev = &prev_p->thread;
190 next = &next_p->thread;
192 if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^
193 test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) {
194 unsigned long debugctl = get_debugctlmsr();
196 debugctl &= ~DEBUGCTLMSR_BTF;
197 if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP))
198 debugctl |= DEBUGCTLMSR_BTF;
200 update_debugctlmsr(debugctl);
203 if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
204 test_tsk_thread_flag(next_p, TIF_NOTSC)) {
205 /* prev and next are different */
206 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
212 if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
214 * Copy the relevant range of the IO bitmap.
215 * Normally this is 128 bytes or less:
217 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
218 max(prev->io_bitmap_max, next->io_bitmap_max));
219 } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
221 * Clear any possible leftover bits:
223 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
225 propagate_user_return_notify(prev_p, next_p);
228 int sys_fork(struct pt_regs *regs)
230 return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL);
234 * This is trivial, and on the face of it looks like it
235 * could equally well be done in user mode.
237 * Not so, for quite unobvious reasons - register pressure.
238 * In user mode vfork() cannot have a stack frame, and if
239 * done by calling the "clone()" system call directly, you
240 * do not have enough call-clobbered registers to hold all
241 * the information you need.
243 int sys_vfork(struct pt_regs *regs)
245 return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0,
250 sys_clone(unsigned long clone_flags, unsigned long newsp,
251 void __user *parent_tid, void __user *child_tid, struct pt_regs *regs)
255 return do_fork(clone_flags, newsp, regs, 0, parent_tid, child_tid);
259 * This gets run with %si containing the
260 * function to call, and %di containing
263 extern void kernel_thread_helper(void);
266 * Create a kernel thread
268 int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
272 memset(®s, 0, sizeof(regs));
274 regs.si = (unsigned long) fn;
275 regs.di = (unsigned long) arg;
280 regs.fs = __KERNEL_PERCPU;
281 regs.gs = __KERNEL_STACK_CANARY;
283 regs.ss = __KERNEL_DS;
287 regs.ip = (unsigned long) kernel_thread_helper;
288 regs.cs = __KERNEL_CS | get_kernel_rpl();
289 regs.flags = X86_EFLAGS_IF | 0x2;
291 /* Ok, create the new process.. */
292 return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, ®s, 0, NULL, NULL);
294 EXPORT_SYMBOL(kernel_thread);
297 * sys_execve() executes a new program.
299 long sys_execve(const char __user *name,
300 const char __user *const __user *argv,
301 const char __user *const __user *envp, struct pt_regs *regs)
306 filename = getname(name);
307 error = PTR_ERR(filename);
308 if (IS_ERR(filename))
310 error = do_execve(filename, argv, envp, regs);
314 /* Make sure we don't return using sysenter.. */
315 set_thread_flag(TIF_IRET);
324 * Idle related variables and functions
326 unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
327 EXPORT_SYMBOL(boot_option_idle_override);
330 * Powermanagement idle function, if any..
332 void (*pm_idle)(void);
333 EXPORT_SYMBOL(pm_idle);
337 * This halt magic was a workaround for ancient floppy DMA
338 * wreckage. It should be safe to remove.
340 static int hlt_counter;
341 void disable_hlt(void)
345 EXPORT_SYMBOL(disable_hlt);
347 void enable_hlt(void)
351 EXPORT_SYMBOL(enable_hlt);
353 static inline int hlt_use_halt(void)
355 return (!hlt_counter && boot_cpu_data.hlt_works_ok);
358 static inline int hlt_use_halt(void)
365 * We use this if we don't have any better
368 void default_idle(void)
370 if (hlt_use_halt()) {
371 trace_power_start(POWER_CSTATE, 1, smp_processor_id());
372 trace_cpu_idle(1, smp_processor_id());
373 current_thread_info()->status &= ~TS_POLLING;
375 * TS_POLLING-cleared state must be visible before we
381 safe_halt(); /* enables interrupts racelessly */
384 current_thread_info()->status |= TS_POLLING;
385 trace_power_end(smp_processor_id());
386 trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
389 /* loop is done by the caller */
393 #ifdef CONFIG_APM_MODULE
394 EXPORT_SYMBOL(default_idle);
397 void stop_this_cpu(void *dummy)
403 set_cpu_online(smp_processor_id(), false);
404 disable_local_APIC();
407 if (hlt_works(smp_processor_id()))
412 static void do_nothing(void *unused)
417 * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
418 * pm_idle and update to new pm_idle value. Required while changing pm_idle
419 * handler on SMP systems.
421 * Caller must have changed pm_idle to the new value before the call. Old
422 * pm_idle value will not be used by any CPU after the return of this function.
424 void cpu_idle_wait(void)
427 /* kick all the CPUs so that they exit out of pm_idle */
428 smp_call_function(do_nothing, NULL, 1);
430 EXPORT_SYMBOL_GPL(cpu_idle_wait);
433 * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
434 * which can obviate IPI to trigger checking of need_resched.
435 * We execute MONITOR against need_resched and enter optimized wait state
436 * through MWAIT. Whenever someone changes need_resched, we would be woken
437 * up from MWAIT (without an IPI).
439 * New with Core Duo processors, MWAIT can take some hints based on CPU
442 void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
444 if (!need_resched()) {
445 if (cpu_has(__this_cpu_ptr(&cpu_info), X86_FEATURE_CLFLUSH_MONITOR))
446 clflush((void *)¤t_thread_info()->flags);
448 __monitor((void *)¤t_thread_info()->flags, 0, 0);
455 /* Default MONITOR/MWAIT with no hints, used for default C1 state */
456 static void mwait_idle(void)
458 if (!need_resched()) {
459 trace_power_start(POWER_CSTATE, 1, smp_processor_id());
460 trace_cpu_idle(1, smp_processor_id());
461 if (cpu_has(__this_cpu_ptr(&cpu_info), X86_FEATURE_CLFLUSH_MONITOR))
462 clflush((void *)¤t_thread_info()->flags);
464 __monitor((void *)¤t_thread_info()->flags, 0, 0);
470 trace_power_end(smp_processor_id());
471 trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
477 * On SMP it's slightly faster (but much more power-consuming!)
478 * to poll the ->work.need_resched flag instead of waiting for the
479 * cross-CPU IPI to arrive. Use this option with caution.
481 static void poll_idle(void)
483 trace_power_start(POWER_CSTATE, 0, smp_processor_id());
484 trace_cpu_idle(0, smp_processor_id());
486 while (!need_resched())
488 trace_power_end(smp_processor_id());
489 trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
493 * mwait selection logic:
495 * It depends on the CPU. For AMD CPUs that support MWAIT this is
496 * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
497 * then depend on a clock divisor and current Pstate of the core. If
498 * all cores of a processor are in halt state (C1) the processor can
499 * enter the C1E (C1 enhanced) state. If mwait is used this will never
502 * idle=mwait overrides this decision and forces the usage of mwait.
505 #define MWAIT_INFO 0x05
506 #define MWAIT_ECX_EXTENDED_INFO 0x01
507 #define MWAIT_EDX_C1 0xf0
509 int mwait_usable(const struct cpuinfo_x86 *c)
511 u32 eax, ebx, ecx, edx;
513 if (boot_option_idle_override == IDLE_FORCE_MWAIT)
516 if (c->cpuid_level < MWAIT_INFO)
519 cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
520 /* Check, whether EDX has extended info about MWAIT */
521 if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
525 * edx enumeratios MONITOR/MWAIT extensions. Check, whether
528 return (edx & MWAIT_EDX_C1);
532 EXPORT_SYMBOL(c1e_detected);
534 static cpumask_var_t c1e_mask;
536 void c1e_remove_cpu(int cpu)
538 if (c1e_mask != NULL)
539 cpumask_clear_cpu(cpu, c1e_mask);
543 * C1E aware idle routine. We check for C1E active in the interrupt
544 * pending message MSR. If we detect C1E, then we handle it the same
545 * way as C3 power states (local apic timer and TSC stop)
547 static void c1e_idle(void)
555 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
557 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
559 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
560 mark_tsc_unstable("TSC halt in AMD C1E");
561 printk(KERN_INFO "System has AMD C1E enabled\n");
566 int cpu = smp_processor_id();
568 if (!cpumask_test_cpu(cpu, c1e_mask)) {
569 cpumask_set_cpu(cpu, c1e_mask);
571 * Force broadcast so ACPI can not interfere.
573 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
575 printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
578 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
583 * The switch back from broadcast mode needs to be
584 * called with interrupts disabled.
587 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
593 void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
596 if (pm_idle == poll_idle && smp_num_siblings > 1) {
597 printk_once(KERN_WARNING "WARNING: polling idle and HT enabled,"
598 " performance may degrade.\n");
604 if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
606 * One CPU supports mwait => All CPUs supports mwait
608 printk(KERN_INFO "using mwait in idle threads.\n");
609 pm_idle = mwait_idle;
610 } else if (cpu_has_amd_erratum(amd_erratum_400)) {
611 /* E400: APIC timer interrupt does not wake up CPU from C1e */
612 printk(KERN_INFO "using C1E aware idle routine\n");
615 pm_idle = default_idle;
618 void __init init_c1e_mask(void)
620 /* If we're using c1e_idle, we need to allocate c1e_mask. */
621 if (pm_idle == c1e_idle)
622 zalloc_cpumask_var(&c1e_mask, GFP_KERNEL);
625 static int __init idle_setup(char *str)
630 if (!strcmp(str, "poll")) {
631 printk("using polling idle threads.\n");
633 boot_option_idle_override = IDLE_POLL;
634 } else if (!strcmp(str, "mwait")) {
635 boot_option_idle_override = IDLE_FORCE_MWAIT;
636 } else if (!strcmp(str, "halt")) {
638 * When the boot option of idle=halt is added, halt is
639 * forced to be used for CPU idle. In such case CPU C2/C3
640 * won't be used again.
641 * To continue to load the CPU idle driver, don't touch
642 * the boot_option_idle_override.
644 pm_idle = default_idle;
645 boot_option_idle_override = IDLE_HALT;
646 } else if (!strcmp(str, "nomwait")) {
648 * If the boot option of "idle=nomwait" is added,
649 * it means that mwait will be disabled for CPU C2/C3
650 * states. In such case it won't touch the variable
651 * of boot_option_idle_override.
653 boot_option_idle_override = IDLE_NOMWAIT;
659 early_param("idle", idle_setup);
661 unsigned long arch_align_stack(unsigned long sp)
663 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
664 sp -= get_random_int() % 8192;
668 unsigned long arch_randomize_brk(struct mm_struct *mm)
670 unsigned long range_end = mm->brk + 0x02000000;
671 return randomize_range(mm->brk, range_end, 0) ? : mm->brk;