1 // SPDX-License-Identifier: GPL-2.0
2 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
4 #include <linux/errno.h>
5 #include <linux/kernel.h>
8 #include <linux/prctl.h>
9 #include <linux/slab.h>
10 #include <linux/sched.h>
11 #include <linux/sched/idle.h>
12 #include <linux/sched/debug.h>
13 #include <linux/sched/task.h>
14 #include <linux/sched/task_stack.h>
15 #include <linux/init.h>
16 #include <linux/export.h>
18 #include <linux/tick.h>
19 #include <linux/random.h>
20 #include <linux/user-return-notifier.h>
21 #include <linux/dmi.h>
22 #include <linux/utsname.h>
23 #include <linux/stackprotector.h>
24 #include <linux/cpuidle.h>
25 #include <linux/acpi.h>
26 #include <linux/elf-randomize.h>
27 #include <trace/events/power.h>
28 #include <linux/hw_breakpoint.h>
31 #include <linux/uaccess.h>
32 #include <asm/mwait.h>
33 #include <asm/fpu/internal.h>
34 #include <asm/debugreg.h>
36 #include <asm/tlbflush.h>
39 #include <asm/switch_to.h>
41 #include <asm/prctl.h>
42 #include <asm/spec-ctrl.h>
43 #include <asm/io_bitmap.h>
44 #include <asm/proto.h>
45 #include <asm/frame.h>
50 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
51 * no more per-task TSS's. The TSS size is kept cacheline-aligned
52 * so they are allowed to end up in the .data..cacheline_aligned
53 * section. Since TSS's are completely CPU-local, we want them
54 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
56 __visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = {
59 * .sp0 is only used when entering ring 0 from a lower
60 * privilege level. Since the init task never runs anything
61 * but ring 0 code, there is no need for a valid value here.
64 .sp0 = (1UL << (BITS_PER_LONG-1)) + 1,
67 .sp1 = TOP_OF_INIT_STACK,
72 .io_bitmap_base = IO_BITMAP_OFFSET_INVALID,
75 EXPORT_PER_CPU_SYMBOL(cpu_tss_rw);
77 DEFINE_PER_CPU(bool, __tss_limit_invalid);
78 EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid);
81 * this gets called so that we can store lazy state into memory and copy the
82 * current task into the new thread.
84 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
86 memcpy(dst, src, arch_task_struct_size);
88 dst->thread.vm86 = NULL;
90 return fpu_clone(dst);
94 * Free thread data structures etc..
96 void exit_thread(struct task_struct *tsk)
98 struct thread_struct *t = &tsk->thread;
99 struct fpu *fpu = &t->fpu;
101 if (test_thread_flag(TIF_IO_BITMAP))
109 static int set_new_tls(struct task_struct *p, unsigned long tls)
111 struct user_desc __user *utls = (struct user_desc __user *)tls;
113 if (in_ia32_syscall())
114 return do_set_thread_area(p, -1, utls, 0);
116 return do_set_thread_area_64(p, ARCH_SET_FS, tls);
119 int copy_thread(unsigned long clone_flags, unsigned long sp, unsigned long arg,
120 struct task_struct *p, unsigned long tls)
122 struct inactive_task_frame *frame;
123 struct fork_frame *fork_frame;
124 struct pt_regs *childregs;
127 childregs = task_pt_regs(p);
128 fork_frame = container_of(childregs, struct fork_frame, regs);
129 frame = &fork_frame->frame;
131 frame->bp = encode_frame_pointer(childregs);
132 frame->ret_addr = (unsigned long) ret_from_fork;
133 p->thread.sp = (unsigned long) fork_frame;
134 p->thread.io_bitmap = NULL;
135 memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps));
139 p->thread.fsindex = current->thread.fsindex;
140 p->thread.fsbase = current->thread.fsbase;
141 p->thread.gsindex = current->thread.gsindex;
142 p->thread.gsbase = current->thread.gsbase;
144 savesegment(es, p->thread.es);
145 savesegment(ds, p->thread.ds);
147 p->thread.sp0 = (unsigned long) (childregs + 1);
149 * Clear all status flags including IF and set fixed bit. 64bit
150 * does not have this initialization as the frame does not contain
151 * flags. The flags consistency (especially vs. AC) is there
152 * ensured via objtool, which lacks 32bit support.
154 frame->flags = X86_EFLAGS_FIXED;
157 /* Kernel thread ? */
158 if (unlikely(p->flags & PF_KTHREAD)) {
159 memset(childregs, 0, sizeof(struct pt_regs));
160 kthread_frame_init(frame, sp, arg);
165 *childregs = *current_pt_regs();
171 task_user_gs(p) = get_user_gs(current_pt_regs());
174 if (unlikely(p->flags & PF_IO_WORKER)) {
176 * An IO thread is a user space thread, but it doesn't
177 * return to ret_after_fork().
179 * In order to indicate that to tools like gdb,
180 * we reset the stack and instruction pointers.
182 * It does the same kernel frame setup to return to a kernel
183 * function that a kernel thread does.
187 kthread_frame_init(frame, sp, arg);
191 /* Set a new TLS for the child thread? */
192 if (clone_flags & CLONE_SETTLS)
193 ret = set_new_tls(p, tls);
195 if (!ret && unlikely(test_tsk_thread_flag(current, TIF_IO_BITMAP)))
201 void flush_thread(void)
203 struct task_struct *tsk = current;
205 flush_ptrace_hw_breakpoint(tsk);
206 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
208 fpu__clear_all(&tsk->thread.fpu);
211 void disable_TSC(void)
214 if (!test_and_set_thread_flag(TIF_NOTSC))
216 * Must flip the CPU state synchronously with
217 * TIF_NOTSC in the current running context.
219 cr4_set_bits(X86_CR4_TSD);
223 static void enable_TSC(void)
226 if (test_and_clear_thread_flag(TIF_NOTSC))
228 * Must flip the CPU state synchronously with
229 * TIF_NOTSC in the current running context.
231 cr4_clear_bits(X86_CR4_TSD);
235 int get_tsc_mode(unsigned long adr)
239 if (test_thread_flag(TIF_NOTSC))
240 val = PR_TSC_SIGSEGV;
244 return put_user(val, (unsigned int __user *)adr);
247 int set_tsc_mode(unsigned int val)
249 if (val == PR_TSC_SIGSEGV)
251 else if (val == PR_TSC_ENABLE)
259 DEFINE_PER_CPU(u64, msr_misc_features_shadow);
261 static void set_cpuid_faulting(bool on)
265 msrval = this_cpu_read(msr_misc_features_shadow);
266 msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT;
267 msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT);
268 this_cpu_write(msr_misc_features_shadow, msrval);
269 wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval);
272 static void disable_cpuid(void)
275 if (!test_and_set_thread_flag(TIF_NOCPUID)) {
277 * Must flip the CPU state synchronously with
278 * TIF_NOCPUID in the current running context.
280 set_cpuid_faulting(true);
285 static void enable_cpuid(void)
288 if (test_and_clear_thread_flag(TIF_NOCPUID)) {
290 * Must flip the CPU state synchronously with
291 * TIF_NOCPUID in the current running context.
293 set_cpuid_faulting(false);
298 static int get_cpuid_mode(void)
300 return !test_thread_flag(TIF_NOCPUID);
303 static int set_cpuid_mode(struct task_struct *task, unsigned long cpuid_enabled)
305 if (!boot_cpu_has(X86_FEATURE_CPUID_FAULT))
317 * Called immediately after a successful exec.
319 void arch_setup_new_exec(void)
321 /* If cpuid was previously disabled for this task, re-enable it. */
322 if (test_thread_flag(TIF_NOCPUID))
326 * Don't inherit TIF_SSBD across exec boundary when
327 * PR_SPEC_DISABLE_NOEXEC is used.
329 if (test_thread_flag(TIF_SSBD) &&
330 task_spec_ssb_noexec(current)) {
331 clear_thread_flag(TIF_SSBD);
332 task_clear_spec_ssb_disable(current);
333 task_clear_spec_ssb_noexec(current);
334 speculation_ctrl_update(task_thread_info(current)->flags);
338 #ifdef CONFIG_X86_IOPL_IOPERM
339 static inline void switch_to_bitmap(unsigned long tifp)
342 * Invalidate I/O bitmap if the previous task used it. This prevents
343 * any possible leakage of an active I/O bitmap.
345 * If the next task has an I/O bitmap it will handle it on exit to
348 if (tifp & _TIF_IO_BITMAP)
349 tss_invalidate_io_bitmap();
352 static void tss_copy_io_bitmap(struct tss_struct *tss, struct io_bitmap *iobm)
355 * Copy at least the byte range of the incoming tasks bitmap which
356 * covers the permitted I/O ports.
358 * If the previous task which used an I/O bitmap had more bits
359 * permitted, then the copy needs to cover those as well so they
362 memcpy(tss->io_bitmap.bitmap, iobm->bitmap,
363 max(tss->io_bitmap.prev_max, iobm->max));
366 * Store the new max and the sequence number of this bitmap
367 * and a pointer to the bitmap itself.
369 tss->io_bitmap.prev_max = iobm->max;
370 tss->io_bitmap.prev_sequence = iobm->sequence;
374 * tss_update_io_bitmap - Update I/O bitmap before exiting to usermode
376 void native_tss_update_io_bitmap(void)
378 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
379 struct thread_struct *t = ¤t->thread;
380 u16 *base = &tss->x86_tss.io_bitmap_base;
382 if (!test_thread_flag(TIF_IO_BITMAP)) {
383 native_tss_invalidate_io_bitmap();
387 if (IS_ENABLED(CONFIG_X86_IOPL_IOPERM) && t->iopl_emul == 3) {
388 *base = IO_BITMAP_OFFSET_VALID_ALL;
390 struct io_bitmap *iobm = t->io_bitmap;
393 * Only copy bitmap data when the sequence number differs. The
394 * update time is accounted to the incoming task.
396 if (tss->io_bitmap.prev_sequence != iobm->sequence)
397 tss_copy_io_bitmap(tss, iobm);
399 /* Enable the bitmap */
400 *base = IO_BITMAP_OFFSET_VALID_MAP;
404 * Make sure that the TSS limit is covering the IO bitmap. It might have
405 * been cut down by a VMEXIT to 0x67 which would cause a subsequent I/O
406 * access from user space to trigger a #GP because tbe bitmap is outside
411 #else /* CONFIG_X86_IOPL_IOPERM */
412 static inline void switch_to_bitmap(unsigned long tifp) { }
418 struct ssb_state *shared_state;
420 unsigned int disable_state;
421 unsigned long local_state;
426 static DEFINE_PER_CPU(struct ssb_state, ssb_state);
428 void speculative_store_bypass_ht_init(void)
430 struct ssb_state *st = this_cpu_ptr(&ssb_state);
431 unsigned int this_cpu = smp_processor_id();
437 * Shared state setup happens once on the first bringup
438 * of the CPU. It's not destroyed on CPU hotunplug.
440 if (st->shared_state)
443 raw_spin_lock_init(&st->lock);
446 * Go over HT siblings and check whether one of them has set up the
447 * shared state pointer already.
449 for_each_cpu(cpu, topology_sibling_cpumask(this_cpu)) {
453 if (!per_cpu(ssb_state, cpu).shared_state)
456 /* Link it to the state of the sibling: */
457 st->shared_state = per_cpu(ssb_state, cpu).shared_state;
462 * First HT sibling to come up on the core. Link shared state of
463 * the first HT sibling to itself. The siblings on the same core
464 * which come up later will see the shared state pointer and link
465 * themselves to the state of this CPU.
467 st->shared_state = st;
471 * Logic is: First HT sibling enables SSBD for both siblings in the core
472 * and last sibling to disable it, disables it for the whole core. This how
473 * MSR_SPEC_CTRL works in "hardware":
475 * CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL
477 static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
479 struct ssb_state *st = this_cpu_ptr(&ssb_state);
480 u64 msr = x86_amd_ls_cfg_base;
482 if (!static_cpu_has(X86_FEATURE_ZEN)) {
483 msr |= ssbd_tif_to_amd_ls_cfg(tifn);
484 wrmsrl(MSR_AMD64_LS_CFG, msr);
488 if (tifn & _TIF_SSBD) {
490 * Since this can race with prctl(), block reentry on the
493 if (__test_and_set_bit(LSTATE_SSB, &st->local_state))
496 msr |= x86_amd_ls_cfg_ssbd_mask;
498 raw_spin_lock(&st->shared_state->lock);
499 /* First sibling enables SSBD: */
500 if (!st->shared_state->disable_state)
501 wrmsrl(MSR_AMD64_LS_CFG, msr);
502 st->shared_state->disable_state++;
503 raw_spin_unlock(&st->shared_state->lock);
505 if (!__test_and_clear_bit(LSTATE_SSB, &st->local_state))
508 raw_spin_lock(&st->shared_state->lock);
509 st->shared_state->disable_state--;
510 if (!st->shared_state->disable_state)
511 wrmsrl(MSR_AMD64_LS_CFG, msr);
512 raw_spin_unlock(&st->shared_state->lock);
516 static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
518 u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn);
520 wrmsrl(MSR_AMD64_LS_CFG, msr);
524 static __always_inline void amd_set_ssb_virt_state(unsigned long tifn)
527 * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL,
528 * so ssbd_tif_to_spec_ctrl() just works.
530 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn));
534 * Update the MSRs managing speculation control, during context switch.
536 * tifp: Previous task's thread flags
537 * tifn: Next task's thread flags
539 static __always_inline void __speculation_ctrl_update(unsigned long tifp,
542 unsigned long tif_diff = tifp ^ tifn;
543 u64 msr = x86_spec_ctrl_base;
546 lockdep_assert_irqs_disabled();
548 /* Handle change of TIF_SSBD depending on the mitigation method. */
549 if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) {
550 if (tif_diff & _TIF_SSBD)
551 amd_set_ssb_virt_state(tifn);
552 } else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) {
553 if (tif_diff & _TIF_SSBD)
554 amd_set_core_ssb_state(tifn);
555 } else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
556 static_cpu_has(X86_FEATURE_AMD_SSBD)) {
557 updmsr |= !!(tif_diff & _TIF_SSBD);
558 msr |= ssbd_tif_to_spec_ctrl(tifn);
561 /* Only evaluate TIF_SPEC_IB if conditional STIBP is enabled. */
562 if (IS_ENABLED(CONFIG_SMP) &&
563 static_branch_unlikely(&switch_to_cond_stibp)) {
564 updmsr |= !!(tif_diff & _TIF_SPEC_IB);
565 msr |= stibp_tif_to_spec_ctrl(tifn);
569 wrmsrl(MSR_IA32_SPEC_CTRL, msr);
572 static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk)
574 if (test_and_clear_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE)) {
575 if (task_spec_ssb_disable(tsk))
576 set_tsk_thread_flag(tsk, TIF_SSBD);
578 clear_tsk_thread_flag(tsk, TIF_SSBD);
580 if (task_spec_ib_disable(tsk))
581 set_tsk_thread_flag(tsk, TIF_SPEC_IB);
583 clear_tsk_thread_flag(tsk, TIF_SPEC_IB);
585 /* Return the updated threadinfo flags*/
586 return task_thread_info(tsk)->flags;
589 void speculation_ctrl_update(unsigned long tif)
593 /* Forced update. Make sure all relevant TIF flags are different */
594 local_irq_save(flags);
595 __speculation_ctrl_update(~tif, tif);
596 local_irq_restore(flags);
599 /* Called from seccomp/prctl update */
600 void speculation_ctrl_update_current(void)
603 speculation_ctrl_update(speculation_ctrl_update_tif(current));
607 static inline void cr4_toggle_bits_irqsoff(unsigned long mask)
609 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4);
613 this_cpu_write(cpu_tlbstate.cr4, newval);
618 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p)
620 unsigned long tifp, tifn;
622 tifn = READ_ONCE(task_thread_info(next_p)->flags);
623 tifp = READ_ONCE(task_thread_info(prev_p)->flags);
625 switch_to_bitmap(tifp);
627 propagate_user_return_notify(prev_p, next_p);
629 if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) &&
630 arch_has_block_step()) {
631 unsigned long debugctl, msk;
633 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
634 debugctl &= ~DEBUGCTLMSR_BTF;
635 msk = tifn & _TIF_BLOCKSTEP;
636 debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT;
637 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
640 if ((tifp ^ tifn) & _TIF_NOTSC)
641 cr4_toggle_bits_irqsoff(X86_CR4_TSD);
643 if ((tifp ^ tifn) & _TIF_NOCPUID)
644 set_cpuid_faulting(!!(tifn & _TIF_NOCPUID));
646 if (likely(!((tifp | tifn) & _TIF_SPEC_FORCE_UPDATE))) {
647 __speculation_ctrl_update(tifp, tifn);
649 speculation_ctrl_update_tif(prev_p);
650 tifn = speculation_ctrl_update_tif(next_p);
652 /* Enforce MSR update to ensure consistent state */
653 __speculation_ctrl_update(~tifn, tifn);
656 if ((tifp ^ tifn) & _TIF_SLD)
661 * Idle related variables and functions
663 unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
664 EXPORT_SYMBOL(boot_option_idle_override);
666 static void (*x86_idle)(void);
669 static inline void play_dead(void)
675 void arch_cpu_idle_enter(void)
677 tsc_verify_tsc_adjust(false);
681 void arch_cpu_idle_dead(void)
687 * Called from the generic idle code.
689 void arch_cpu_idle(void)
695 * We use this if we don't have any better idle routine..
697 void __cpuidle default_idle(void)
701 #if defined(CONFIG_APM_MODULE) || defined(CONFIG_HALTPOLL_CPUIDLE_MODULE)
702 EXPORT_SYMBOL(default_idle);
706 bool xen_set_default_idle(void)
708 bool ret = !!x86_idle;
710 x86_idle = default_idle;
716 void stop_this_cpu(void *dummy)
722 set_cpu_online(smp_processor_id(), false);
723 disable_local_APIC();
724 mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
727 * Use wbinvd on processors that support SME. This provides support
728 * for performing a successful kexec when going from SME inactive
729 * to SME active (or vice-versa). The cache must be cleared so that
730 * if there are entries with the same physical address, both with and
731 * without the encryption bit, they don't race each other when flushed
732 * and potentially end up with the wrong entry being committed to
735 if (boot_cpu_has(X86_FEATURE_SME))
739 * Use native_halt() so that memory contents don't change
740 * (stack usage and variables) after possibly issuing the
741 * native_wbinvd() above.
748 * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power
749 * states (local apic timer and TSC stop).
751 * XXX this function is completely buggered vs RCU and tracing.
753 static void amd_e400_idle(void)
756 * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E
757 * gets set after static_cpu_has() places have been converted via
760 if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
765 tick_broadcast_enter();
770 * The switch back from broadcast mode needs to be called with
771 * interrupts disabled.
773 raw_local_irq_disable();
774 tick_broadcast_exit();
775 raw_local_irq_enable();
779 * Intel Core2 and older machines prefer MWAIT over HALT for C1.
780 * We can't rely on cpuidle installing MWAIT, because it will not load
781 * on systems that support only C1 -- so the boot default must be MWAIT.
783 * Some AMD machines are the opposite, they depend on using HALT.
785 * So for default C1, which is used during boot until cpuidle loads,
786 * use MWAIT-C1 on Intel HW that has it, else use HALT.
788 static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
790 if (c->x86_vendor != X86_VENDOR_INTEL)
793 if (!cpu_has(c, X86_FEATURE_MWAIT) || boot_cpu_has_bug(X86_BUG_MONITOR))
800 * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT
801 * with interrupts enabled and no flags, which is backwards compatible with the
802 * original MWAIT implementation.
804 static __cpuidle void mwait_idle(void)
806 if (!current_set_polling_and_test()) {
807 if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
809 clflush((void *)¤t_thread_info()->flags);
813 __monitor((void *)¤t_thread_info()->flags, 0, 0);
817 raw_local_irq_enable();
819 raw_local_irq_enable();
821 __current_clr_polling();
824 void select_idle_routine(const struct cpuinfo_x86 *c)
827 if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
828 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
830 if (x86_idle || boot_option_idle_override == IDLE_POLL)
833 if (boot_cpu_has_bug(X86_BUG_AMD_E400)) {
834 pr_info("using AMD E400 aware idle routine\n");
835 x86_idle = amd_e400_idle;
836 } else if (prefer_mwait_c1_over_halt(c)) {
837 pr_info("using mwait in idle threads\n");
838 x86_idle = mwait_idle;
840 x86_idle = default_idle;
843 void amd_e400_c1e_apic_setup(void)
845 if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
846 pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id());
848 tick_broadcast_force();
853 void __init arch_post_acpi_subsys_init(void)
857 if (!boot_cpu_has_bug(X86_BUG_AMD_E400))
861 * AMD E400 detection needs to happen after ACPI has been enabled. If
862 * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in
863 * MSR_K8_INT_PENDING_MSG.
865 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
866 if (!(lo & K8_INTP_C1E_ACTIVE_MASK))
869 boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E);
871 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
872 mark_tsc_unstable("TSC halt in AMD C1E");
873 pr_info("System has AMD C1E enabled\n");
876 static int __init idle_setup(char *str)
881 if (!strcmp(str, "poll")) {
882 pr_info("using polling idle threads\n");
883 boot_option_idle_override = IDLE_POLL;
884 cpu_idle_poll_ctrl(true);
885 } else if (!strcmp(str, "halt")) {
887 * When the boot option of idle=halt is added, halt is
888 * forced to be used for CPU idle. In such case CPU C2/C3
889 * won't be used again.
890 * To continue to load the CPU idle driver, don't touch
891 * the boot_option_idle_override.
893 x86_idle = default_idle;
894 boot_option_idle_override = IDLE_HALT;
895 } else if (!strcmp(str, "nomwait")) {
897 * If the boot option of "idle=nomwait" is added,
898 * it means that mwait will be disabled for CPU C2/C3
899 * states. In such case it won't touch the variable
900 * of boot_option_idle_override.
902 boot_option_idle_override = IDLE_NOMWAIT;
908 early_param("idle", idle_setup);
910 unsigned long arch_align_stack(unsigned long sp)
912 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
913 sp -= get_random_int() % 8192;
917 unsigned long arch_randomize_brk(struct mm_struct *mm)
919 return randomize_page(mm->brk, 0x02000000);
923 * Called from fs/proc with a reference on @p to find the function
924 * which called into schedule(). This needs to be done carefully
925 * because the task might wake up and we might look at a stack
928 unsigned long get_wchan(struct task_struct *p)
930 unsigned long start, bottom, top, sp, fp, ip, ret = 0;
933 if (p == current || p->state == TASK_RUNNING)
936 if (!try_get_task_stack(p))
939 start = (unsigned long)task_stack_page(p);
944 * Layout of the stack page:
946 * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long)
948 * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING
950 * ----------- bottom = start
952 * The tasks stack pointer points at the location where the
953 * framepointer is stored. The data on the stack is:
954 * ... IP FP ... IP FP
956 * We need to read FP and IP, so we need to adjust the upper
957 * bound by another unsigned long.
959 top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;
960 top -= 2 * sizeof(unsigned long);
963 sp = READ_ONCE(p->thread.sp);
964 if (sp < bottom || sp > top)
967 fp = READ_ONCE_NOCHECK(((struct inactive_task_frame *)sp)->bp);
969 if (fp < bottom || fp > top)
971 ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long)));
972 if (!in_sched_functions(ip)) {
976 fp = READ_ONCE_NOCHECK(*(unsigned long *)fp);
977 } while (count++ < 16 && p->state != TASK_RUNNING);
984 long do_arch_prctl_common(struct task_struct *task, int option,
985 unsigned long cpuid_enabled)
989 return get_cpuid_mode();
991 return set_cpuid_mode(task, cpuid_enabled);