2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * SGI UV APIC functions (note: not an Intel compatible APIC)
8 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
11 #include <linux/kernel.h>
12 #include <linux/threads.h>
13 #include <linux/cpumask.h>
14 #include <linux/string.h>
15 #include <linux/ctype.h>
16 #include <linux/init.h>
17 #include <linux/sched.h>
18 #include <linux/bootmem.h>
19 #include <linux/module.h>
20 #include <linux/hardirq.h>
23 #include <asm/genapic.h>
24 #include <asm/pgtable.h>
25 #include <asm/uv/uv_mmrs.h>
26 #include <asm/uv/uv_hub.h>
27 #include <asm/uv/bios.h>
29 DEFINE_PER_CPU(int, x2apic_extra_bits);
31 static enum uv_system_type uv_system_type;
33 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
35 if (!strcmp(oem_id, "SGI")) {
36 if (!strcmp(oem_table_id, "UVL"))
37 uv_system_type = UV_LEGACY_APIC;
38 else if (!strcmp(oem_table_id, "UVX"))
39 uv_system_type = UV_X2APIC;
40 else if (!strcmp(oem_table_id, "UVH")) {
41 uv_system_type = UV_NON_UNIQUE_APIC;
48 enum uv_system_type get_uv_system_type(void)
50 return uv_system_type;
53 int is_uv_system(void)
55 return uv_system_type != UV_NONE;
57 EXPORT_SYMBOL_GPL(is_uv_system);
59 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
60 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
62 struct uv_blade_info *uv_blade_info;
63 EXPORT_SYMBOL_GPL(uv_blade_info);
65 short *uv_node_to_blade;
66 EXPORT_SYMBOL_GPL(uv_node_to_blade);
68 short *uv_cpu_to_blade;
69 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
71 short uv_possible_blades;
72 EXPORT_SYMBOL_GPL(uv_possible_blades);
74 unsigned long sn_rtc_cycles_per_second;
75 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
77 /* Start with all IRQs pointing to boot CPU. IRQ balancing will shift them. */
79 static cpumask_t uv_target_cpus(void)
81 return cpumask_of_cpu(0);
84 static cpumask_t uv_vector_allocation_domain(int cpu)
86 cpumask_t domain = CPU_MASK_NONE;
91 int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip)
96 pnode = uv_apicid_to_pnode(phys_apicid);
97 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
98 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
99 (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
101 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
104 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
105 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
106 (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
108 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
112 static void uv_send_IPI_one(int cpu, int vector)
114 unsigned long val, apicid, lapicid;
117 apicid = per_cpu(x86_cpu_to_apicid, cpu);
118 lapicid = apicid & 0x3f; /* ZZZ macro needed */
119 pnode = uv_apicid_to_pnode(apicid);
121 (1UL << UVH_IPI_INT_SEND_SHFT) | (lapicid <<
122 UVH_IPI_INT_APIC_ID_SHFT) |
123 (vector << UVH_IPI_INT_VECTOR_SHFT);
124 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
127 static void uv_send_IPI_mask(cpumask_t mask, int vector)
131 for_each_possible_cpu(cpu)
132 if (cpu_isset(cpu, mask))
133 uv_send_IPI_one(cpu, vector);
136 static void uv_send_IPI_allbutself(int vector)
138 cpumask_t mask = cpu_online_map;
140 cpu_clear(smp_processor_id(), mask);
142 if (!cpus_empty(mask))
143 uv_send_IPI_mask(mask, vector);
146 static void uv_send_IPI_all(int vector)
148 uv_send_IPI_mask(cpu_online_map, vector);
151 static int uv_apic_id_registered(void)
156 static void uv_init_apic_ldr(void)
160 static unsigned int uv_cpu_mask_to_apicid(cpumask_t cpumask)
165 * We're using fixed IRQ delivery, can only return one phys APIC ID.
166 * May as well be the first.
168 cpu = first_cpu(cpumask);
169 if ((unsigned)cpu < nr_cpu_ids)
170 return per_cpu(x86_cpu_to_apicid, cpu);
175 static unsigned int get_apic_id(unsigned long x)
179 WARN_ON(preemptible() && num_online_cpus() > 1);
180 id = x | __get_cpu_var(x2apic_extra_bits);
185 static unsigned long set_apic_id(unsigned int id)
189 /* maskout x2apic_extra_bits ? */
194 static unsigned int uv_read_apic_id(void)
197 return get_apic_id(apic_read(APIC_ID));
200 static unsigned int phys_pkg_id(int index_msb)
202 return uv_read_apic_id() >> index_msb;
205 static void uv_send_IPI_self(int vector)
207 apic_write(APIC_SELF_IPI, vector);
210 struct genapic apic_x2apic_uv_x = {
211 .name = "UV large system",
212 .acpi_madt_oem_check = uv_acpi_madt_oem_check,
213 .int_delivery_mode = dest_Fixed,
214 .int_dest_mode = (APIC_DEST_PHYSICAL != 0),
215 .target_cpus = uv_target_cpus,
216 .vector_allocation_domain = uv_vector_allocation_domain,
217 .apic_id_registered = uv_apic_id_registered,
218 .init_apic_ldr = uv_init_apic_ldr,
219 .send_IPI_all = uv_send_IPI_all,
220 .send_IPI_allbutself = uv_send_IPI_allbutself,
221 .send_IPI_mask = uv_send_IPI_mask,
222 .send_IPI_self = uv_send_IPI_self,
223 .cpu_mask_to_apicid = uv_cpu_mask_to_apicid,
224 .phys_pkg_id = phys_pkg_id,
225 .get_apic_id = get_apic_id,
226 .set_apic_id = set_apic_id,
227 .apic_id_mask = (0xFFFFFFFFu),
230 static __cpuinit void set_x2apic_extra_bits(int pnode)
232 __get_cpu_var(x2apic_extra_bits) = (pnode << 6);
236 * Called on boot cpu.
238 static __init int boot_pnode_to_blade(int pnode)
242 for (blade = 0; blade < uv_num_possible_blades(); blade++)
243 if (pnode == uv_blade_info[blade].pnode)
249 unsigned long redirect;
253 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
255 static __initdata struct redir_addr redir_addrs[] = {
256 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
257 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
258 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
261 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
263 union uvh_si_alias0_overlay_config_u alias;
264 union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
267 for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
268 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
269 if (alias.s.base == 0) {
270 *size = (1UL << alias.s.m_alias);
271 redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
272 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
279 static __init void map_low_mmrs(void)
281 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
282 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
285 enum map_type {map_wb, map_uc};
287 static __init void map_high(char *id, unsigned long base, int shift,
288 int max_pnode, enum map_type map_type)
290 unsigned long bytes, paddr;
292 paddr = base << shift;
293 bytes = (1UL << shift) * (max_pnode + 1);
294 printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
296 if (map_type == map_uc)
297 init_extra_mapping_uc(paddr, bytes);
299 init_extra_mapping_wb(paddr, bytes);
302 static __init void map_gru_high(int max_pnode)
304 union uvh_rh_gam_gru_overlay_config_mmr_u gru;
305 int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
307 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
309 map_high("GRU", gru.s.base, shift, max_pnode, map_wb);
312 static __init void map_config_high(int max_pnode)
314 union uvh_rh_gam_cfg_overlay_config_mmr_u cfg;
315 int shift = UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT;
317 cfg.v = uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR);
319 map_high("CONFIG", cfg.s.base, shift, max_pnode, map_uc);
322 static __init void map_mmr_high(int max_pnode)
324 union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
325 int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
327 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
329 map_high("MMR", mmr.s.base, shift, max_pnode, map_uc);
332 static __init void map_mmioh_high(int max_pnode)
334 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
335 int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
337 mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
339 map_high("MMIOH", mmioh.s.base, shift, max_pnode, map_uc);
342 static __init void uv_rtc_init(void)
344 long status, ticks_per_sec, drift;
347 x86_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec,
349 if (status != 0 || ticks_per_sec < 100000) {
351 "unable to determine platform RTC clock frequency, "
353 /* BIOS gives wrong value for clock freq. so guess */
354 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
356 sn_rtc_cycles_per_second = ticks_per_sec;
360 * Called on each cpu to initialize the per_cpu UV data area.
361 * ZZZ hotplug not supported yet
363 void __cpuinit uv_cpu_init(void)
365 /* CPU 0 initilization will be done via uv_system_init. */
369 uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
371 if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
372 set_x2apic_extra_bits(uv_hub_info->pnode);
376 void __init uv_system_init(void)
378 union uvh_si_addr_map_config_u m_n_config;
379 union uvh_node_id_u node_id;
380 unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
381 int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
383 unsigned long mmr_base, present;
387 m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
388 m_val = m_n_config.s.m_skt;
389 n_val = m_n_config.s.n_skt;
391 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
393 printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
395 for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
396 uv_possible_blades +=
397 hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
398 printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
400 bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
401 uv_blade_info = alloc_bootmem_pages(bytes);
403 get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
405 bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
406 uv_node_to_blade = alloc_bootmem_pages(bytes);
407 memset(uv_node_to_blade, 255, bytes);
409 bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
410 uv_cpu_to_blade = alloc_bootmem_pages(bytes);
411 memset(uv_cpu_to_blade, 255, bytes);
414 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
415 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
416 for (j = 0; j < 64; j++) {
417 if (!test_bit(j, &present))
419 uv_blade_info[blade].pnode = (i * 64 + j);
420 uv_blade_info[blade].nr_possible_cpus = 0;
421 uv_blade_info[blade].nr_online_cpus = 0;
426 node_id.v = uv_read_local_mmr(UVH_NODE_ID);
427 gnode_upper = (((unsigned long)node_id.s.node_id) &
428 ~((1 << n_val) - 1)) << m_val;
433 for_each_present_cpu(cpu) {
434 nid = cpu_to_node(cpu);
435 pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu));
436 blade = boot_pnode_to_blade(pnode);
437 lcpu = uv_blade_info[blade].nr_possible_cpus;
438 uv_blade_info[blade].nr_possible_cpus++;
440 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
441 uv_cpu_hub_info(cpu)->lowmem_remap_top =
442 lowmem_redir_base + lowmem_redir_size;
443 uv_cpu_hub_info(cpu)->m_val = m_val;
444 uv_cpu_hub_info(cpu)->n_val = m_val;
445 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
446 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
447 uv_cpu_hub_info(cpu)->pnode = pnode;
448 uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) - 1;
449 uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
450 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
451 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
452 uv_cpu_hub_info(cpu)->coherency_domain_number = 0;/* ZZZ */
453 uv_node_to_blade[nid] = blade;
454 uv_cpu_to_blade[cpu] = blade;
455 max_pnode = max(pnode, max_pnode);
457 printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, "
458 "lcpu %d, blade %d\n",
459 cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid,
463 map_gru_high(max_pnode);
464 map_mmr_high(max_pnode);
465 map_config_high(max_pnode);
466 map_mmioh_high(max_pnode);