arch/x86/kernel/fpu/core.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  Copyright (C) 1994 Linus Torvalds
   4  *
   5  *  Pentium III FXSR, SSE support
   6  *  General FPU state handling cleanups
   7  *      Gareth Hughes <gareth@valinux.com>, May 2000
   8  */
   9 #include <asm/fpu/api.h>
  10 #include <asm/fpu/regset.h>
  11 #include <asm/fpu/sched.h>
  12 #include <asm/fpu/signal.h>
  13 #include <asm/fpu/types.h>
  14 #include <asm/traps.h>
  15 #include <asm/irq_regs.h>
  16
  17 #include <linux/hardirq.h>
  18 #include <linux/pkeys.h>
  19 #include <linux/vmalloc.h>
  20
  21 #include "context.h"
  22 #include "internal.h"
  23 #include "legacy.h"
  24 #include "xstate.h"
  25
  26 #define CREATE_TRACE_POINTS
  27 #include <asm/trace/fpu.h>
  28
  29 #ifdef CONFIG_X86_64
  30 DEFINE_STATIC_KEY_FALSE(__fpu_state_size_dynamic);
  31 DEFINE_PER_CPU(u64, xfd_state);
  32 #endif
  33
  34 /* The FPU state configuration data for kernel and user space */
  35 struct fpu_state_config fpu_kernel_cfg __ro_after_init;
  36 struct fpu_state_config fpu_user_cfg __ro_after_init;
  37
  38 /*
  39  * Represents the initial FPU state. It's mostly (but not completely) zeroes,
  40  * depending on the FPU hardware format:
  41  */
  42 struct fpstate init_fpstate __ro_after_init;
  43
  44 /*
  45  * Track whether the kernel is using the FPU state
  46  * currently.
  47  *
  48  * This flag is used:
  49  *
  50  *   - by IRQ context code to potentially use the FPU
  51  *     if it's unused.
  52  *
  53  *   - to debug kernel_fpu_begin()/end() correctness
  54  */
  55 static DEFINE_PER_CPU(bool, in_kernel_fpu);
  56
  57 /*
  58  * Track which context is using the FPU on the CPU:
  59  */
  60 DEFINE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx);
  61
  62 static bool kernel_fpu_disabled(void)
  63 {
  64         return this_cpu_read(in_kernel_fpu);
  65 }
  66
  67 static bool interrupted_kernel_fpu_idle(void)
  68 {
  69         return !kernel_fpu_disabled();
  70 }
  71
  72 /*
  73  * Were we in user mode (or vm86 mode) when we were
  74  * interrupted?
  75  *
  76  * Doing kernel_fpu_begin/end() is ok if we are running
  77  * in an interrupt context from user mode - we'll just
  78  * save the FPU state as required.
  79  */
  80 static bool interrupted_user_mode(void)
  81 {
  82         struct pt_regs *regs = get_irq_regs();
  83         return regs && user_mode(regs);
  84 }
  85
  86 /*
  87  * Can we use the FPU in kernel mode with the
  88  * whole "kernel_fpu_begin/end()" sequence?
  89  *
  90  * It's always ok in process context (ie "not interrupt")
  91  * but it is sometimes ok even from an irq.
  92  */
  93 bool irq_fpu_usable(void)
  94 {
  95         return !in_interrupt() ||
  96                 interrupted_user_mode() ||
  97                 interrupted_kernel_fpu_idle();
  98 }
  99 EXPORT_SYMBOL(irq_fpu_usable);
 100
 101 /*
 102  * Track AVX512 state use because it is known to slow the max clock
 103  * speed of the core.
 104  */
 105 static void update_avx_timestamp(struct fpu *fpu)
 106 {
 107
 108 #define AVX512_TRACKING_MASK    (XFEATURE_MASK_ZMM_Hi256 | XFEATURE_MASK_Hi16_ZMM)
 109
 110         if (fpu->fpstate->regs.xsave.header.xfeatures & AVX512_TRACKING_MASK)
 111                 fpu->avx512_timestamp = jiffies;
 112 }
 113
 114 /*
 115  * Save the FPU register state in fpu->fpstate->regs. The register state is
 116  * preserved.
 117  *
 118  * Must be called with fpregs_lock() held.
 119  *
 120  * The legacy FNSAVE instruction clears all FPU state unconditionally, so
 121  * register state has to be reloaded. That might be a pointless exercise
 122  * when the FPU is going to be used by another task right after that. But
 123  * this only affects 20+ years old 32bit systems and avoids conditionals all
 124  * over the place.
 125  *
 126  * FXSAVE and all XSAVE variants preserve the FPU register state.
 127  */
 128 void save_fpregs_to_fpstate(struct fpu *fpu)
 129 {
 130         if (likely(use_xsave())) {
 131                 os_xsave(fpu->fpstate);
 132                 update_avx_timestamp(fpu);
 133                 return;
 134         }
 135
 136         if (likely(use_fxsr())) {
 137                 fxsave(&fpu->fpstate->regs.fxsave);
 138                 return;
 139         }
 140
 141         /*
 142          * Legacy FPU register saving, FNSAVE always clears FPU registers,
 143          * so we have to reload them from the memory state.
 144          */
 145         asm volatile("fnsave %[fp]; fwait" : [fp] "=m" (fpu->fpstate->regs.fsave));
 146         frstor(&fpu->fpstate->regs.fsave);
 147 }
 148
 149 void restore_fpregs_from_fpstate(struct fpstate *fpstate, u64 mask)
 150 {
 151         /*
 152          * AMD K7/K8 and later CPUs up to Zen don't save/restore
 153          * FDP/FIP/FOP unless an exception is pending. Clear the x87 state
 154          * here by setting it to fixed values.  "m" is a random variable
 155          * that should be in L1.
 156          */
 157         if (unlikely(static_cpu_has_bug(X86_BUG_FXSAVE_LEAK))) {
 158                 asm volatile(
 159                         "fnclex\n\t"
 160                         "emms\n\t"
 161                         "fildl %P[addr]"        /* set F?P to defined value */
 162                         : : [addr] "m" (fpstate));
 163         }
 164
 165         if (use_xsave()) {
 166                 /*
 167                  * Dynamically enabled features are enabled in XCR0, but
 168                  * usage requires also that the corresponding bits in XFD
 169                  * are cleared.  If the bits are set then using a related
 170                  * instruction will raise #NM. This allows to do the
 171                  * allocation of the larger FPU buffer lazy from #NM or if
 172                  * the task has no permission to kill it which would happen
 173                  * via #UD if the feature is disabled in XCR0.
 174                  *
 175                  * XFD state is following the same life time rules as
 176                  * XSTATE and to restore state correctly XFD has to be
 177                  * updated before XRSTORS otherwise the component would
 178                  * stay in or go into init state even if the bits are set
 179                  * in fpstate::regs::xsave::xfeatures.
 180                  */
 181                 xfd_update_state(fpstate);
 182
 183                 /*
 184                  * Restoring state always needs to modify all features
 185                  * which are in @mask even if the current task cannot use
 186                  * extended features.
 187                  *
 188                  * So fpstate->xfeatures cannot be used here, because then
 189                  * a feature for which the task has no permission but was
 190                  * used by the previous task would not go into init state.
 191                  */
 192                 mask = fpu_kernel_cfg.max_features & mask;
 193
 194                 os_xrstor(fpstate, mask);
 195         } else {
 196                 if (use_fxsr())
 197                         fxrstor(&fpstate->regs.fxsave);
 198                 else
 199                         frstor(&fpstate->regs.fsave);
 200         }
 201 }
 202
 203 void fpu_reset_from_exception_fixup(void)
 204 {
 205         restore_fpregs_from_fpstate(&init_fpstate, XFEATURE_MASK_FPSTATE);
 206 }
 207
 208 #if IS_ENABLED(CONFIG_KVM)
 209 static void __fpstate_reset(struct fpstate *fpstate);
 210
 211 bool fpu_alloc_guest_fpstate(struct fpu_guest *gfpu)
 212 {
 213         struct fpstate *fpstate;
 214         unsigned int size;
 215
 216         size = fpu_user_cfg.default_size + ALIGN(offsetof(struct fpstate, regs), 64);
 217         fpstate = vzalloc(size);
 218         if (!fpstate)
 219                 return false;
 220
 221         __fpstate_reset(fpstate);
 222         fpstate_init_user(fpstate);
 223         fpstate->is_valloc      = true;
 224         fpstate->is_guest       = true;
 225
 226         gfpu->fpstate = fpstate;
 227         return true;
 228 }
 229 EXPORT_SYMBOL_GPL(fpu_alloc_guest_fpstate);
 230
 231 void fpu_free_guest_fpstate(struct fpu_guest *gfpu)
 232 {
 233         struct fpstate *fps = gfpu->fpstate;
 234
 235         if (!fps)
 236                 return;
 237
 238         if (WARN_ON_ONCE(!fps->is_valloc || !fps->is_guest || fps->in_use))
 239                 return;
 240
 241         gfpu->fpstate = NULL;
 242         vfree(fps);
 243 }
 244 EXPORT_SYMBOL_GPL(fpu_free_guest_fpstate);
 245
 246 int fpu_swap_kvm_fpstate(struct fpu_guest *guest_fpu, bool enter_guest)
 247 {
 248         struct fpstate *guest_fps = guest_fpu->fpstate;
 249         struct fpu *fpu = &current->thread.fpu;
 250         struct fpstate *cur_fps = fpu->fpstate;
 251
 252         fpregs_lock();
 253         if (!cur_fps->is_confidential && !test_thread_flag(TIF_NEED_FPU_LOAD))
 254                 save_fpregs_to_fpstate(fpu);
 255
 256         /* Swap fpstate */
 257         if (enter_guest) {
 258                 fpu->__task_fpstate = cur_fps;
 259                 fpu->fpstate = guest_fps;
 260                 guest_fps->in_use = true;
 261         } else {
 262                 guest_fps->in_use = false;
 263                 fpu->fpstate = fpu->__task_fpstate;
 264                 fpu->__task_fpstate = NULL;
 265         }
 266
 267         cur_fps = fpu->fpstate;
 268
 269         if (!cur_fps->is_confidential) {
 270                 /* Includes XFD update */
 271                 restore_fpregs_from_fpstate(cur_fps, XFEATURE_MASK_FPSTATE);
 272         } else {
 273                 /*
 274                  * XSTATE is restored by firmware from encrypted
 275                  * memory. Make sure XFD state is correct while
 276                  * running with guest fpstate
 277                  */
 278                 xfd_update_state(cur_fps);
 279         }
 280
 281         fpregs_mark_activate();
 282         fpregs_unlock();
 283         return 0;
 284 }
 285 EXPORT_SYMBOL_GPL(fpu_swap_kvm_fpstate);
 286
 287 void fpu_copy_guest_fpstate_to_uabi(struct fpu_guest *gfpu, void *buf,
 288                                     unsigned int size, u32 pkru)
 289 {
 290         struct fpstate *kstate = gfpu->fpstate;
 291         union fpregs_state *ustate = buf;
 292         struct membuf mb = { .p = buf, .left = size };
 293
 294         if (cpu_feature_enabled(X86_FEATURE_XSAVE)) {
 295                 __copy_xstate_to_uabi_buf(mb, kstate, pkru, XSTATE_COPY_XSAVE);
 296         } else {
 297                 memcpy(&ustate->fxsave, &kstate->regs.fxsave,
 298                        sizeof(ustate->fxsave));
 299                 /* Make it restorable on a XSAVE enabled host */
 300                 ustate->xsave.header.xfeatures = XFEATURE_MASK_FPSSE;
 301         }
 302 }
 303 EXPORT_SYMBOL_GPL(fpu_copy_guest_fpstate_to_uabi);
 304
 305 int fpu_copy_uabi_to_guest_fpstate(struct fpu_guest *gfpu, const void *buf,
 306                                    u64 xcr0, u32 *vpkru)
 307 {
 308         struct fpstate *kstate = gfpu->fpstate;
 309         const union fpregs_state *ustate = buf;
 310         struct pkru_state *xpkru;
 311         int ret;
 312
 313         if (!cpu_feature_enabled(X86_FEATURE_XSAVE)) {
 314                 if (ustate->xsave.header.xfeatures & ~XFEATURE_MASK_FPSSE)
 315                         return -EINVAL;
 316                 if (ustate->fxsave.mxcsr & ~mxcsr_feature_mask)
 317                         return -EINVAL;
 318                 memcpy(&kstate->regs.fxsave, &ustate->fxsave, sizeof(ustate->fxsave));
 319                 return 0;
 320         }
 321
 322         if (ustate->xsave.header.xfeatures & ~xcr0)
 323                 return -EINVAL;
 324
 325         ret = copy_uabi_from_kernel_to_xstate(kstate, ustate);
 326         if (ret)
 327                 return ret;
 328
 329         /* Retrieve PKRU if not in init state */
 330         if (kstate->regs.xsave.header.xfeatures & XFEATURE_MASK_PKRU) {
 331                 xpkru = get_xsave_addr(&kstate->regs.xsave, XFEATURE_PKRU);
 332                 *vpkru = xpkru->pkru;
 333         }
 334
 335         /* Ensure that XCOMP_BV is set up for XSAVES */
 336         xstate_init_xcomp_bv(&kstate->regs.xsave, kstate->xfeatures);
 337         return 0;
 338 }
 339 EXPORT_SYMBOL_GPL(fpu_copy_uabi_to_guest_fpstate);
 340 #endif /* CONFIG_KVM */
 341
 342 void kernel_fpu_begin_mask(unsigned int kfpu_mask)
 343 {
 344         preempt_disable();
 345
 346         WARN_ON_FPU(!irq_fpu_usable());
 347         WARN_ON_FPU(this_cpu_read(in_kernel_fpu));
 348
 349         this_cpu_write(in_kernel_fpu, true);
 350
 351         if (!(current->flags & PF_KTHREAD) &&
 352             !test_thread_flag(TIF_NEED_FPU_LOAD)) {
 353                 set_thread_flag(TIF_NEED_FPU_LOAD);
 354                 save_fpregs_to_fpstate(&current->thread.fpu);
 355         }
 356         __cpu_invalidate_fpregs_state();
 357
 358         /* Put sane initial values into the control registers. */
 359         if (likely(kfpu_mask & KFPU_MXCSR) && boot_cpu_has(X86_FEATURE_XMM))
 360                 ldmxcsr(MXCSR_DEFAULT);
 361
 362         if (unlikely(kfpu_mask & KFPU_387) && boot_cpu_has(X86_FEATURE_FPU))
 363                 asm volatile ("fninit");
 364 }
 365 EXPORT_SYMBOL_GPL(kernel_fpu_begin_mask);
 366
 367 void kernel_fpu_end(void)
 368 {
 369         WARN_ON_FPU(!this_cpu_read(in_kernel_fpu));
 370
 371         this_cpu_write(in_kernel_fpu, false);
 372         preempt_enable();
 373 }
 374 EXPORT_SYMBOL_GPL(kernel_fpu_end);
 375
 376 /*
 377  * Sync the FPU register state to current's memory register state when the
 378  * current task owns the FPU. The hardware register state is preserved.
 379  */
 380 void fpu_sync_fpstate(struct fpu *fpu)
 381 {
 382         WARN_ON_FPU(fpu != &current->thread.fpu);
 383
 384         fpregs_lock();
 385         trace_x86_fpu_before_save(fpu);
 386
 387         if (!test_thread_flag(TIF_NEED_FPU_LOAD))
 388                 save_fpregs_to_fpstate(fpu);
 389
 390         trace_x86_fpu_after_save(fpu);
 391         fpregs_unlock();
 392 }
 393
 394 static inline unsigned int init_fpstate_copy_size(void)
 395 {
 396         if (!use_xsave())
 397                 return fpu_kernel_cfg.default_size;
 398
 399         /* XSAVE(S) just needs the legacy and the xstate header part */
 400         return sizeof(init_fpstate.regs.xsave);
 401 }
 402
 403 static inline void fpstate_init_fxstate(struct fpstate *fpstate)
 404 {
 405         fpstate->regs.fxsave.cwd = 0x37f;
 406         fpstate->regs.fxsave.mxcsr = MXCSR_DEFAULT;
 407 }
 408
 409 /*
 410  * Legacy x87 fpstate state init:
 411  */
 412 static inline void fpstate_init_fstate(struct fpstate *fpstate)
 413 {
 414         fpstate->regs.fsave.cwd = 0xffff037fu;
 415         fpstate->regs.fsave.swd = 0xffff0000u;
 416         fpstate->regs.fsave.twd = 0xffffffffu;
 417         fpstate->regs.fsave.fos = 0xffff0000u;
 418 }
 419
 420 /*
 421  * Used in two places:
 422  * 1) Early boot to setup init_fpstate for non XSAVE systems
 423  * 2) fpu_init_fpstate_user() which is invoked from KVM
 424  */
 425 void fpstate_init_user(struct fpstate *fpstate)
 426 {
 427         if (!cpu_feature_enabled(X86_FEATURE_FPU)) {
 428                 fpstate_init_soft(&fpstate->regs.soft);
 429                 return;
 430         }
 431
 432         xstate_init_xcomp_bv(&fpstate->regs.xsave, fpstate->xfeatures);
 433
 434         if (cpu_feature_enabled(X86_FEATURE_FXSR))
 435                 fpstate_init_fxstate(fpstate);
 436         else
 437                 fpstate_init_fstate(fpstate);
 438 }
 439
 440 static void __fpstate_reset(struct fpstate *fpstate)
 441 {
 442         /* Initialize sizes and feature masks */
 443         fpstate->size           = fpu_kernel_cfg.default_size;
 444         fpstate->user_size      = fpu_user_cfg.default_size;
 445         fpstate->xfeatures      = fpu_kernel_cfg.default_features;
 446         fpstate->user_xfeatures = fpu_user_cfg.default_features;
 447         fpstate->xfd            = init_fpstate.xfd;
 448 }
 449
 450 void fpstate_reset(struct fpu *fpu)
 451 {
 452         /* Set the fpstate pointer to the default fpstate */
 453         fpu->fpstate = &fpu->__fpstate;
 454         __fpstate_reset(fpu->fpstate);
 455
 456         /* Initialize the permission related info in fpu */
 457         fpu->perm.__state_perm          = fpu_kernel_cfg.default_features;
 458         fpu->perm.__state_size          = fpu_kernel_cfg.default_size;
 459         fpu->perm.__user_state_size     = fpu_user_cfg.default_size;
 460 }
 461
 462 static inline void fpu_inherit_perms(struct fpu *dst_fpu)
 463 {
 464         if (fpu_state_size_dynamic()) {
 465                 struct fpu *src_fpu = &current->group_leader->thread.fpu;
 466
 467                 spin_lock_irq(&current->sighand->siglock);
 468                 /* Fork also inherits the permissions of the parent */
 469                 dst_fpu->perm = src_fpu->perm;
 470                 spin_unlock_irq(&current->sighand->siglock);
 471         }
 472 }
 473
 474 /* Clone current's FPU state on fork */
 475 int fpu_clone(struct task_struct *dst, unsigned long clone_flags)
 476 {
 477         struct fpu *src_fpu = &current->thread.fpu;
 478         struct fpu *dst_fpu = &dst->thread.fpu;
 479
 480         /* The new task's FPU state cannot be valid in the hardware. */
 481         dst_fpu->last_cpu = -1;
 482
 483         fpstate_reset(dst_fpu);
 484
 485         if (!cpu_feature_enabled(X86_FEATURE_FPU))
 486                 return 0;
 487
 488         /*
 489          * Enforce reload for user space tasks and prevent kernel threads
 490          * from trying to save the FPU registers on context switch.
 491          */
 492         set_tsk_thread_flag(dst, TIF_NEED_FPU_LOAD);
 493
 494         /*
 495          * No FPU state inheritance for kernel threads and IO
 496          * worker threads.
 497          */
 498         if (dst->flags & (PF_KTHREAD | PF_IO_WORKER)) {
 499                 /* Clear out the minimal state */
 500                 memcpy(&dst_fpu->fpstate->regs, &init_fpstate.regs,
 501                        init_fpstate_copy_size());
 502                 return 0;
 503         }
 504
 505         /*
 506          * If a new feature is added, ensure all dynamic features are
 507          * caller-saved from here!
 508          */
 509         BUILD_BUG_ON(XFEATURE_MASK_USER_DYNAMIC != XFEATURE_MASK_XTILE_DATA);
 510
 511         /*
 512          * Save the default portion of the current FPU state into the
 513          * clone. Assume all dynamic features to be defined as caller-
 514          * saved, which enables skipping both the expansion of fpstate
 515          * and the copying of any dynamic state.
 516          *
 517          * Do not use memcpy() when TIF_NEED_FPU_LOAD is set because
 518          * copying is not valid when current uses non-default states.
 519          */
 520         fpregs_lock();
 521         if (test_thread_flag(TIF_NEED_FPU_LOAD))
 522                 fpregs_restore_userregs();
 523         save_fpregs_to_fpstate(dst_fpu);
 524         if (!(clone_flags & CLONE_THREAD))
 525                 fpu_inherit_perms(dst_fpu);
 526         fpregs_unlock();
 527
 528         trace_x86_fpu_copy_src(src_fpu);
 529         trace_x86_fpu_copy_dst(dst_fpu);
 530
 531         return 0;
 532 }
 533
 534 /*
 535  * Whitelist the FPU register state embedded into task_struct for hardened
 536  * usercopy.
 537  */
 538 void fpu_thread_struct_whitelist(unsigned long *offset, unsigned long *size)
 539 {
 540         *offset = offsetof(struct thread_struct, fpu.__fpstate.regs);
 541         *size = fpu_kernel_cfg.default_size;
 542 }
 543
 544 /*
 545  * Drops current FPU state: deactivates the fpregs and
 546  * the fpstate. NOTE: it still leaves previous contents
 547  * in the fpregs in the eager-FPU case.
 548  *
 549  * This function can be used in cases where we know that
 550  * a state-restore is coming: either an explicit one,
 551  * or a reschedule.
 552  */
 553 void fpu__drop(struct fpu *fpu)
 554 {
 555         preempt_disable();
 556
 557         if (fpu == &current->thread.fpu) {
 558                 /* Ignore delayed exceptions from user space */
 559                 asm volatile("1: fwait\n"
 560                              "2:\n"
 561                              _ASM_EXTABLE(1b, 2b));
 562                 fpregs_deactivate(fpu);
 563         }
 564
 565         trace_x86_fpu_dropped(fpu);
 566
 567         preempt_enable();
 568 }
 569
 570 /*
 571  * Clear FPU registers by setting them up from the init fpstate.
 572  * Caller must do fpregs_[un]lock() around it.
 573  */
 574 static inline void restore_fpregs_from_init_fpstate(u64 features_mask)
 575 {
 576         if (use_xsave())
 577                 os_xrstor(&init_fpstate, features_mask);
 578         else if (use_fxsr())
 579                 fxrstor(&init_fpstate.regs.fxsave);
 580         else
 581                 frstor(&init_fpstate.regs.fsave);
 582
 583         pkru_write_default();
 584 }
 585
 586 /*
 587  * Reset current->fpu memory state to the init values.
 588  */
 589 static void fpu_reset_fpregs(void)
 590 {
 591         struct fpu *fpu = &current->thread.fpu;
 592
 593         fpregs_lock();
 594         fpu__drop(fpu);
 595         /*
 596          * This does not change the actual hardware registers. It just
 597          * resets the memory image and sets TIF_NEED_FPU_LOAD so a
 598          * subsequent return to usermode will reload the registers from the
 599          * task's memory image.
 600          *
 601          * Do not use fpstate_init() here. Just copy init_fpstate which has
 602          * the correct content already except for PKRU.
 603          *
 604          * PKRU handling does not rely on the xstate when restoring for
 605          * user space as PKRU is eagerly written in switch_to() and
 606          * flush_thread().
 607          */
 608         memcpy(&fpu->fpstate->regs, &init_fpstate.regs, init_fpstate_copy_size());
 609         set_thread_flag(TIF_NEED_FPU_LOAD);
 610         fpregs_unlock();
 611 }
 612
 613 /*
 614  * Reset current's user FPU states to the init states.  current's
 615  * supervisor states, if any, are not modified by this function.  The
 616  * caller guarantees that the XSTATE header in memory is intact.
 617  */
 618 void fpu__clear_user_states(struct fpu *fpu)
 619 {
 620         WARN_ON_FPU(fpu != &current->thread.fpu);
 621
 622         fpregs_lock();
 623         if (!cpu_feature_enabled(X86_FEATURE_FPU)) {
 624                 fpu_reset_fpregs();
 625                 fpregs_unlock();
 626                 return;
 627         }
 628
 629         /*
 630          * Ensure that current's supervisor states are loaded into their
 631          * corresponding registers.
 632          */
 633         if (xfeatures_mask_supervisor() &&
 634             !fpregs_state_valid(fpu, smp_processor_id()))
 635                 os_xrstor_supervisor(fpu->fpstate);
 636
 637         /* Reset user states in registers. */
 638         restore_fpregs_from_init_fpstate(XFEATURE_MASK_USER_RESTORE);
 639
 640         /*
 641          * Now all FPU registers have their desired values.  Inform the FPU
 642          * state machine that current's FPU registers are in the hardware
 643          * registers. The memory image does not need to be updated because
 644          * any operation relying on it has to save the registers first when
 645          * current's FPU is marked active.
 646          */
 647         fpregs_mark_activate();
 648         fpregs_unlock();
 649 }
 650
 651 void fpu_flush_thread(void)
 652 {
 653         fpstate_reset(&current->thread.fpu);
 654         fpu_reset_fpregs();
 655 }
 656 /*
 657  * Load FPU context before returning to userspace.
 658  */
 659 void switch_fpu_return(void)
 660 {
 661         if (!static_cpu_has(X86_FEATURE_FPU))
 662                 return;
 663
 664         fpregs_restore_userregs();
 665 }
 666 EXPORT_SYMBOL_GPL(switch_fpu_return);
 667
 668 #ifdef CONFIG_X86_DEBUG_FPU
 669 /*
 670  * If current FPU state according to its tracking (loaded FPU context on this
 671  * CPU) is not valid then we must have TIF_NEED_FPU_LOAD set so the context is
 672  * loaded on return to userland.
 673  */
 674 void fpregs_assert_state_consistent(void)
 675 {
 676         struct fpu *fpu = &current->thread.fpu;
 677
 678         if (test_thread_flag(TIF_NEED_FPU_LOAD))
 679                 return;
 680
 681         WARN_ON_FPU(!fpregs_state_valid(fpu, smp_processor_id()));
 682 }
 683 EXPORT_SYMBOL_GPL(fpregs_assert_state_consistent);
 684 #endif
 685
 686 void fpregs_mark_activate(void)
 687 {
 688         struct fpu *fpu = &current->thread.fpu;
 689
 690         fpregs_activate(fpu);
 691         fpu->last_cpu = smp_processor_id();
 692         clear_thread_flag(TIF_NEED_FPU_LOAD);
 693 }
 694
 695 /*
 696  * x87 math exception handling:
 697  */
 698
 699 int fpu__exception_code(struct fpu *fpu, int trap_nr)
 700 {
 701         int err;
 702
 703         if (trap_nr == X86_TRAP_MF) {
 704                 unsigned short cwd, swd;
 705                 /*
 706                  * (~cwd & swd) will mask out exceptions that are not set to unmasked
 707                  * status.  0x3f is the exception bits in these regs, 0x200 is the
 708                  * C1 reg you need in case of a stack fault, 0x040 is the stack
 709                  * fault bit.  We should only be taking one exception at a time,
 710                  * so if this combination doesn't produce any single exception,
 711                  * then we have a bad program that isn't synchronizing its FPU usage
 712                  * and it will suffer the consequences since we won't be able to
 713                  * fully reproduce the context of the exception.
 714                  */
 715                 if (boot_cpu_has(X86_FEATURE_FXSR)) {
 716                         cwd = fpu->fpstate->regs.fxsave.cwd;
 717                         swd = fpu->fpstate->regs.fxsave.swd;
 718                 } else {
 719                         cwd = (unsigned short)fpu->fpstate->regs.fsave.cwd;
 720                         swd = (unsigned short)fpu->fpstate->regs.fsave.swd;
 721                 }
 722
 723                 err = swd & ~cwd;
 724         } else {
 725                 /*
 726                  * The SIMD FPU exceptions are handled a little differently, as there
 727                  * is only a single status/control register.  Thus, to determine which
 728                  * unmasked exception was caught we must mask the exception mask bits
 729                  * at 0x1f80, and then use these to mask the exception bits at 0x3f.
 730                  */
 731                 unsigned short mxcsr = MXCSR_DEFAULT;
 732
 733                 if (boot_cpu_has(X86_FEATURE_XMM))
 734                         mxcsr = fpu->fpstate->regs.fxsave.mxcsr;
 735
 736                 err = ~(mxcsr >> 7) & mxcsr;
 737         }
 738
 739         if (err & 0x001) {      /* Invalid op */
 740                 /*
 741                  * swd & 0x240 == 0x040: Stack Underflow
 742                  * swd & 0x240 == 0x240: Stack Overflow
 743                  * User must clear the SF bit (0x40) if set
 744                  */
 745                 return FPE_FLTINV;
 746         } else if (err & 0x004) { /* Divide by Zero */
 747                 return FPE_FLTDIV;
 748         } else if (err & 0x008) { /* Overflow */
 749                 return FPE_FLTOVF;
 750         } else if (err & 0x012) { /* Denormal, Underflow */
 751                 return FPE_FLTUND;
 752         } else if (err & 0x020) { /* Precision */
 753                 return FPE_FLTRES;
 754         }
 755
 756         /*
 757          * If we're using IRQ 13, or supposedly even some trap
 758          * X86_TRAP_MF implementations, it's possible
 759          * we get a spurious trap, which is not an error.
 760          */
 761         return 0;
 762 }