1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 1994 Linus Torvalds
5 * Pentium III FXSR, SSE support
6 * General FPU state handling cleanups
7 * Gareth Hughes <gareth@valinux.com>, May 2000
9 #include <asm/fpu/api.h>
10 #include <asm/fpu/regset.h>
11 #include <asm/fpu/sched.h>
12 #include <asm/fpu/signal.h>
13 #include <asm/fpu/types.h>
14 #include <asm/traps.h>
15 #include <asm/irq_regs.h>
17 #include <linux/hardirq.h>
18 #include <linux/pkeys.h>
19 #include <linux/vmalloc.h>
26 #define CREATE_TRACE_POINTS
27 #include <asm/trace/fpu.h>
30 DEFINE_STATIC_KEY_FALSE(__fpu_state_size_dynamic);
31 DEFINE_PER_CPU(u64, xfd_state);
34 /* The FPU state configuration data for kernel and user space */
35 struct fpu_state_config fpu_kernel_cfg __ro_after_init;
36 struct fpu_state_config fpu_user_cfg __ro_after_init;
39 * Represents the initial FPU state. It's mostly (but not completely) zeroes,
40 * depending on the FPU hardware format:
42 struct fpstate init_fpstate __ro_after_init;
45 * Track whether the kernel is using the FPU state
50 * - by IRQ context code to potentially use the FPU
53 * - to debug kernel_fpu_begin()/end() correctness
55 static DEFINE_PER_CPU(bool, in_kernel_fpu);
58 * Track which context is using the FPU on the CPU:
60 DEFINE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx);
62 static bool kernel_fpu_disabled(void)
64 return this_cpu_read(in_kernel_fpu);
67 static bool interrupted_kernel_fpu_idle(void)
69 return !kernel_fpu_disabled();
73 * Were we in user mode (or vm86 mode) when we were
76 * Doing kernel_fpu_begin/end() is ok if we are running
77 * in an interrupt context from user mode - we'll just
78 * save the FPU state as required.
80 static bool interrupted_user_mode(void)
82 struct pt_regs *regs = get_irq_regs();
83 return regs && user_mode(regs);
87 * Can we use the FPU in kernel mode with the
88 * whole "kernel_fpu_begin/end()" sequence?
90 * It's always ok in process context (ie "not interrupt")
91 * but it is sometimes ok even from an irq.
93 bool irq_fpu_usable(void)
95 return !in_interrupt() ||
96 interrupted_user_mode() ||
97 interrupted_kernel_fpu_idle();
99 EXPORT_SYMBOL(irq_fpu_usable);
102 * Track AVX512 state use because it is known to slow the max clock
105 static void update_avx_timestamp(struct fpu *fpu)
108 #define AVX512_TRACKING_MASK (XFEATURE_MASK_ZMM_Hi256 | XFEATURE_MASK_Hi16_ZMM)
110 if (fpu->fpstate->regs.xsave.header.xfeatures & AVX512_TRACKING_MASK)
111 fpu->avx512_timestamp = jiffies;
115 * Save the FPU register state in fpu->fpstate->regs. The register state is
118 * Must be called with fpregs_lock() held.
120 * The legacy FNSAVE instruction clears all FPU state unconditionally, so
121 * register state has to be reloaded. That might be a pointless exercise
122 * when the FPU is going to be used by another task right after that. But
123 * this only affects 20+ years old 32bit systems and avoids conditionals all
126 * FXSAVE and all XSAVE variants preserve the FPU register state.
128 void save_fpregs_to_fpstate(struct fpu *fpu)
130 if (likely(use_xsave())) {
131 os_xsave(fpu->fpstate);
132 update_avx_timestamp(fpu);
136 if (likely(use_fxsr())) {
137 fxsave(&fpu->fpstate->regs.fxsave);
142 * Legacy FPU register saving, FNSAVE always clears FPU registers,
143 * so we have to reload them from the memory state.
145 asm volatile("fnsave %[fp]; fwait" : [fp] "=m" (fpu->fpstate->regs.fsave));
146 frstor(&fpu->fpstate->regs.fsave);
149 void restore_fpregs_from_fpstate(struct fpstate *fpstate, u64 mask)
152 * AMD K7/K8 and later CPUs up to Zen don't save/restore
153 * FDP/FIP/FOP unless an exception is pending. Clear the x87 state
154 * here by setting it to fixed values. "m" is a random variable
155 * that should be in L1.
157 if (unlikely(static_cpu_has_bug(X86_BUG_FXSAVE_LEAK))) {
161 "fildl %P[addr]" /* set F?P to defined value */
162 : : [addr] "m" (fpstate));
167 * Dynamically enabled features are enabled in XCR0, but
168 * usage requires also that the corresponding bits in XFD
169 * are cleared. If the bits are set then using a related
170 * instruction will raise #NM. This allows to do the
171 * allocation of the larger FPU buffer lazy from #NM or if
172 * the task has no permission to kill it which would happen
173 * via #UD if the feature is disabled in XCR0.
175 * XFD state is following the same life time rules as
176 * XSTATE and to restore state correctly XFD has to be
177 * updated before XRSTORS otherwise the component would
178 * stay in or go into init state even if the bits are set
179 * in fpstate::regs::xsave::xfeatures.
181 xfd_update_state(fpstate);
184 * Restoring state always needs to modify all features
185 * which are in @mask even if the current task cannot use
188 * So fpstate->xfeatures cannot be used here, because then
189 * a feature for which the task has no permission but was
190 * used by the previous task would not go into init state.
192 mask = fpu_kernel_cfg.max_features & mask;
194 os_xrstor(fpstate, mask);
197 fxrstor(&fpstate->regs.fxsave);
199 frstor(&fpstate->regs.fsave);
203 void fpu_reset_from_exception_fixup(void)
205 restore_fpregs_from_fpstate(&init_fpstate, XFEATURE_MASK_FPSTATE);
208 #if IS_ENABLED(CONFIG_KVM)
209 static void __fpstate_reset(struct fpstate *fpstate, u64 xfd);
211 static void fpu_init_guest_permissions(struct fpu_guest *gfpu)
213 struct fpu_state_perm *fpuperm;
216 if (!IS_ENABLED(CONFIG_X86_64))
219 spin_lock_irq(¤t->sighand->siglock);
220 fpuperm = ¤t->group_leader->thread.fpu.guest_perm;
221 perm = fpuperm->__state_perm;
223 /* First fpstate allocation locks down permissions. */
224 WRITE_ONCE(fpuperm->__state_perm, perm | FPU_GUEST_PERM_LOCKED);
226 spin_unlock_irq(¤t->sighand->siglock);
228 gfpu->perm = perm & ~FPU_GUEST_PERM_LOCKED;
231 bool fpu_alloc_guest_fpstate(struct fpu_guest *gfpu)
233 struct fpstate *fpstate;
236 size = fpu_user_cfg.default_size + ALIGN(offsetof(struct fpstate, regs), 64);
237 fpstate = vzalloc(size);
241 /* Leave xfd to 0 (the reset value defined by spec) */
242 __fpstate_reset(fpstate, 0);
243 fpstate_init_user(fpstate);
244 fpstate->is_valloc = true;
245 fpstate->is_guest = true;
247 gfpu->fpstate = fpstate;
248 gfpu->xfeatures = fpu_user_cfg.default_features;
249 gfpu->perm = fpu_user_cfg.default_features;
250 gfpu->uabi_size = fpu_user_cfg.default_size;
251 fpu_init_guest_permissions(gfpu);
255 EXPORT_SYMBOL_GPL(fpu_alloc_guest_fpstate);
257 void fpu_free_guest_fpstate(struct fpu_guest *gfpu)
259 struct fpstate *fps = gfpu->fpstate;
264 if (WARN_ON_ONCE(!fps->is_valloc || !fps->is_guest || fps->in_use))
267 gfpu->fpstate = NULL;
270 EXPORT_SYMBOL_GPL(fpu_free_guest_fpstate);
273 * fpu_enable_guest_xfd_features - Check xfeatures against guest perm and enable
274 * @guest_fpu: Pointer to the guest FPU container
275 * @xfeatures: Features requested by guest CPUID
277 * Enable all dynamic xfeatures according to guest perm and requested CPUID.
279 * Return: 0 on success, error code otherwise
281 int fpu_enable_guest_xfd_features(struct fpu_guest *guest_fpu, u64 xfeatures)
283 lockdep_assert_preemption_enabled();
285 /* Nothing to do if all requested features are already enabled. */
286 xfeatures &= ~guest_fpu->xfeatures;
290 return __xfd_enable_feature(xfeatures, guest_fpu);
292 EXPORT_SYMBOL_GPL(fpu_enable_guest_xfd_features);
295 void fpu_update_guest_xfd(struct fpu_guest *guest_fpu, u64 xfd)
298 guest_fpu->fpstate->xfd = xfd;
299 if (guest_fpu->fpstate->in_use)
300 xfd_update_state(guest_fpu->fpstate);
303 EXPORT_SYMBOL_GPL(fpu_update_guest_xfd);
306 * fpu_sync_guest_vmexit_xfd_state - Synchronize XFD MSR and software state
308 * Must be invoked from KVM after a VMEXIT before enabling interrupts when
309 * XFD write emulation is disabled. This is required because the guest can
310 * freely modify XFD and the state at VMEXIT is not guaranteed to be the
311 * same as the state on VMENTER. So software state has to be udpated before
312 * any operation which depends on it can take place.
314 * Note: It can be invoked unconditionally even when write emulation is
315 * enabled for the price of a then pointless MSR read.
317 void fpu_sync_guest_vmexit_xfd_state(void)
319 struct fpstate *fps = current->thread.fpu.fpstate;
321 lockdep_assert_irqs_disabled();
322 if (fpu_state_size_dynamic()) {
323 rdmsrl(MSR_IA32_XFD, fps->xfd);
324 __this_cpu_write(xfd_state, fps->xfd);
327 EXPORT_SYMBOL_GPL(fpu_sync_guest_vmexit_xfd_state);
328 #endif /* CONFIG_X86_64 */
330 int fpu_swap_kvm_fpstate(struct fpu_guest *guest_fpu, bool enter_guest)
332 struct fpstate *guest_fps = guest_fpu->fpstate;
333 struct fpu *fpu = ¤t->thread.fpu;
334 struct fpstate *cur_fps = fpu->fpstate;
337 if (!cur_fps->is_confidential && !test_thread_flag(TIF_NEED_FPU_LOAD))
338 save_fpregs_to_fpstate(fpu);
342 fpu->__task_fpstate = cur_fps;
343 fpu->fpstate = guest_fps;
344 guest_fps->in_use = true;
346 guest_fps->in_use = false;
347 fpu->fpstate = fpu->__task_fpstate;
348 fpu->__task_fpstate = NULL;
351 cur_fps = fpu->fpstate;
353 if (!cur_fps->is_confidential) {
354 /* Includes XFD update */
355 restore_fpregs_from_fpstate(cur_fps, XFEATURE_MASK_FPSTATE);
358 * XSTATE is restored by firmware from encrypted
359 * memory. Make sure XFD state is correct while
360 * running with guest fpstate
362 xfd_update_state(cur_fps);
365 fpregs_mark_activate();
369 EXPORT_SYMBOL_GPL(fpu_swap_kvm_fpstate);
371 void fpu_copy_guest_fpstate_to_uabi(struct fpu_guest *gfpu, void *buf,
372 unsigned int size, u32 pkru)
374 struct fpstate *kstate = gfpu->fpstate;
375 union fpregs_state *ustate = buf;
376 struct membuf mb = { .p = buf, .left = size };
378 if (cpu_feature_enabled(X86_FEATURE_XSAVE)) {
379 __copy_xstate_to_uabi_buf(mb, kstate, pkru, XSTATE_COPY_XSAVE);
381 memcpy(&ustate->fxsave, &kstate->regs.fxsave,
382 sizeof(ustate->fxsave));
383 /* Make it restorable on a XSAVE enabled host */
384 ustate->xsave.header.xfeatures = XFEATURE_MASK_FPSSE;
387 EXPORT_SYMBOL_GPL(fpu_copy_guest_fpstate_to_uabi);
389 int fpu_copy_uabi_to_guest_fpstate(struct fpu_guest *gfpu, const void *buf,
390 u64 xcr0, u32 *vpkru)
392 struct fpstate *kstate = gfpu->fpstate;
393 const union fpregs_state *ustate = buf;
394 struct pkru_state *xpkru;
397 if (!cpu_feature_enabled(X86_FEATURE_XSAVE)) {
398 if (ustate->xsave.header.xfeatures & ~XFEATURE_MASK_FPSSE)
400 if (ustate->fxsave.mxcsr & ~mxcsr_feature_mask)
402 memcpy(&kstate->regs.fxsave, &ustate->fxsave, sizeof(ustate->fxsave));
406 if (ustate->xsave.header.xfeatures & ~xcr0)
409 ret = copy_uabi_from_kernel_to_xstate(kstate, ustate);
413 /* Retrieve PKRU if not in init state */
414 if (kstate->regs.xsave.header.xfeatures & XFEATURE_MASK_PKRU) {
415 xpkru = get_xsave_addr(&kstate->regs.xsave, XFEATURE_PKRU);
416 *vpkru = xpkru->pkru;
419 /* Ensure that XCOMP_BV is set up for XSAVES */
420 xstate_init_xcomp_bv(&kstate->regs.xsave, kstate->xfeatures);
423 EXPORT_SYMBOL_GPL(fpu_copy_uabi_to_guest_fpstate);
424 #endif /* CONFIG_KVM */
426 void kernel_fpu_begin_mask(unsigned int kfpu_mask)
430 WARN_ON_FPU(!irq_fpu_usable());
431 WARN_ON_FPU(this_cpu_read(in_kernel_fpu));
433 this_cpu_write(in_kernel_fpu, true);
435 if (!(current->flags & PF_KTHREAD) &&
436 !test_thread_flag(TIF_NEED_FPU_LOAD)) {
437 set_thread_flag(TIF_NEED_FPU_LOAD);
438 save_fpregs_to_fpstate(¤t->thread.fpu);
440 __cpu_invalidate_fpregs_state();
442 /* Put sane initial values into the control registers. */
443 if (likely(kfpu_mask & KFPU_MXCSR) && boot_cpu_has(X86_FEATURE_XMM))
444 ldmxcsr(MXCSR_DEFAULT);
446 if (unlikely(kfpu_mask & KFPU_387) && boot_cpu_has(X86_FEATURE_FPU))
447 asm volatile ("fninit");
449 EXPORT_SYMBOL_GPL(kernel_fpu_begin_mask);
451 void kernel_fpu_end(void)
453 WARN_ON_FPU(!this_cpu_read(in_kernel_fpu));
455 this_cpu_write(in_kernel_fpu, false);
458 EXPORT_SYMBOL_GPL(kernel_fpu_end);
461 * Sync the FPU register state to current's memory register state when the
462 * current task owns the FPU. The hardware register state is preserved.
464 void fpu_sync_fpstate(struct fpu *fpu)
466 WARN_ON_FPU(fpu != ¤t->thread.fpu);
469 trace_x86_fpu_before_save(fpu);
471 if (!test_thread_flag(TIF_NEED_FPU_LOAD))
472 save_fpregs_to_fpstate(fpu);
474 trace_x86_fpu_after_save(fpu);
478 static inline unsigned int init_fpstate_copy_size(void)
481 return fpu_kernel_cfg.default_size;
483 /* XSAVE(S) just needs the legacy and the xstate header part */
484 return sizeof(init_fpstate.regs.xsave);
487 static inline void fpstate_init_fxstate(struct fpstate *fpstate)
489 fpstate->regs.fxsave.cwd = 0x37f;
490 fpstate->regs.fxsave.mxcsr = MXCSR_DEFAULT;
494 * Legacy x87 fpstate state init:
496 static inline void fpstate_init_fstate(struct fpstate *fpstate)
498 fpstate->regs.fsave.cwd = 0xffff037fu;
499 fpstate->regs.fsave.swd = 0xffff0000u;
500 fpstate->regs.fsave.twd = 0xffffffffu;
501 fpstate->regs.fsave.fos = 0xffff0000u;
505 * Used in two places:
506 * 1) Early boot to setup init_fpstate for non XSAVE systems
507 * 2) fpu_init_fpstate_user() which is invoked from KVM
509 void fpstate_init_user(struct fpstate *fpstate)
511 if (!cpu_feature_enabled(X86_FEATURE_FPU)) {
512 fpstate_init_soft(&fpstate->regs.soft);
516 xstate_init_xcomp_bv(&fpstate->regs.xsave, fpstate->xfeatures);
518 if (cpu_feature_enabled(X86_FEATURE_FXSR))
519 fpstate_init_fxstate(fpstate);
521 fpstate_init_fstate(fpstate);
524 static void __fpstate_reset(struct fpstate *fpstate, u64 xfd)
526 /* Initialize sizes and feature masks */
527 fpstate->size = fpu_kernel_cfg.default_size;
528 fpstate->user_size = fpu_user_cfg.default_size;
529 fpstate->xfeatures = fpu_kernel_cfg.default_features;
530 fpstate->user_xfeatures = fpu_user_cfg.default_features;
534 void fpstate_reset(struct fpu *fpu)
536 /* Set the fpstate pointer to the default fpstate */
537 fpu->fpstate = &fpu->__fpstate;
538 __fpstate_reset(fpu->fpstate, init_fpstate.xfd);
540 /* Initialize the permission related info in fpu */
541 fpu->perm.__state_perm = fpu_kernel_cfg.default_features;
542 fpu->perm.__state_size = fpu_kernel_cfg.default_size;
543 fpu->perm.__user_state_size = fpu_user_cfg.default_size;
544 /* Same defaults for guests */
545 fpu->guest_perm = fpu->perm;
548 static inline void fpu_inherit_perms(struct fpu *dst_fpu)
550 if (fpu_state_size_dynamic()) {
551 struct fpu *src_fpu = ¤t->group_leader->thread.fpu;
553 spin_lock_irq(¤t->sighand->siglock);
554 /* Fork also inherits the permissions of the parent */
555 dst_fpu->perm = src_fpu->perm;
556 dst_fpu->guest_perm = src_fpu->guest_perm;
557 spin_unlock_irq(¤t->sighand->siglock);
561 /* Clone current's FPU state on fork */
562 int fpu_clone(struct task_struct *dst, unsigned long clone_flags)
564 struct fpu *src_fpu = ¤t->thread.fpu;
565 struct fpu *dst_fpu = &dst->thread.fpu;
567 /* The new task's FPU state cannot be valid in the hardware. */
568 dst_fpu->last_cpu = -1;
570 fpstate_reset(dst_fpu);
572 if (!cpu_feature_enabled(X86_FEATURE_FPU))
576 * Enforce reload for user space tasks and prevent kernel threads
577 * from trying to save the FPU registers on context switch.
579 set_tsk_thread_flag(dst, TIF_NEED_FPU_LOAD);
582 * No FPU state inheritance for kernel threads and IO
585 if (dst->flags & (PF_KTHREAD | PF_IO_WORKER)) {
586 /* Clear out the minimal state */
587 memcpy(&dst_fpu->fpstate->regs, &init_fpstate.regs,
588 init_fpstate_copy_size());
593 * If a new feature is added, ensure all dynamic features are
594 * caller-saved from here!
596 BUILD_BUG_ON(XFEATURE_MASK_USER_DYNAMIC != XFEATURE_MASK_XTILE_DATA);
599 * Save the default portion of the current FPU state into the
600 * clone. Assume all dynamic features to be defined as caller-
601 * saved, which enables skipping both the expansion of fpstate
602 * and the copying of any dynamic state.
604 * Do not use memcpy() when TIF_NEED_FPU_LOAD is set because
605 * copying is not valid when current uses non-default states.
608 if (test_thread_flag(TIF_NEED_FPU_LOAD))
609 fpregs_restore_userregs();
610 save_fpregs_to_fpstate(dst_fpu);
611 if (!(clone_flags & CLONE_THREAD))
612 fpu_inherit_perms(dst_fpu);
615 trace_x86_fpu_copy_src(src_fpu);
616 trace_x86_fpu_copy_dst(dst_fpu);
622 * Whitelist the FPU register state embedded into task_struct for hardened
625 void fpu_thread_struct_whitelist(unsigned long *offset, unsigned long *size)
627 *offset = offsetof(struct thread_struct, fpu.__fpstate.regs);
628 *size = fpu_kernel_cfg.default_size;
632 * Drops current FPU state: deactivates the fpregs and
633 * the fpstate. NOTE: it still leaves previous contents
634 * in the fpregs in the eager-FPU case.
636 * This function can be used in cases where we know that
637 * a state-restore is coming: either an explicit one,
640 void fpu__drop(struct fpu *fpu)
644 if (fpu == ¤t->thread.fpu) {
645 /* Ignore delayed exceptions from user space */
646 asm volatile("1: fwait\n"
648 _ASM_EXTABLE(1b, 2b));
649 fpregs_deactivate(fpu);
652 trace_x86_fpu_dropped(fpu);
658 * Clear FPU registers by setting them up from the init fpstate.
659 * Caller must do fpregs_[un]lock() around it.
661 static inline void restore_fpregs_from_init_fpstate(u64 features_mask)
664 os_xrstor(&init_fpstate, features_mask);
666 fxrstor(&init_fpstate.regs.fxsave);
668 frstor(&init_fpstate.regs.fsave);
670 pkru_write_default();
674 * Reset current->fpu memory state to the init values.
676 static void fpu_reset_fpregs(void)
678 struct fpu *fpu = ¤t->thread.fpu;
683 * This does not change the actual hardware registers. It just
684 * resets the memory image and sets TIF_NEED_FPU_LOAD so a
685 * subsequent return to usermode will reload the registers from the
686 * task's memory image.
688 * Do not use fpstate_init() here. Just copy init_fpstate which has
689 * the correct content already except for PKRU.
691 * PKRU handling does not rely on the xstate when restoring for
692 * user space as PKRU is eagerly written in switch_to() and
695 memcpy(&fpu->fpstate->regs, &init_fpstate.regs, init_fpstate_copy_size());
696 set_thread_flag(TIF_NEED_FPU_LOAD);
701 * Reset current's user FPU states to the init states. current's
702 * supervisor states, if any, are not modified by this function. The
703 * caller guarantees that the XSTATE header in memory is intact.
705 void fpu__clear_user_states(struct fpu *fpu)
707 WARN_ON_FPU(fpu != ¤t->thread.fpu);
710 if (!cpu_feature_enabled(X86_FEATURE_FPU)) {
717 * Ensure that current's supervisor states are loaded into their
718 * corresponding registers.
720 if (xfeatures_mask_supervisor() &&
721 !fpregs_state_valid(fpu, smp_processor_id()))
722 os_xrstor_supervisor(fpu->fpstate);
724 /* Reset user states in registers. */
725 restore_fpregs_from_init_fpstate(XFEATURE_MASK_USER_RESTORE);
728 * Now all FPU registers have their desired values. Inform the FPU
729 * state machine that current's FPU registers are in the hardware
730 * registers. The memory image does not need to be updated because
731 * any operation relying on it has to save the registers first when
732 * current's FPU is marked active.
734 fpregs_mark_activate();
738 void fpu_flush_thread(void)
740 fpstate_reset(¤t->thread.fpu);
744 * Load FPU context before returning to userspace.
746 void switch_fpu_return(void)
748 if (!static_cpu_has(X86_FEATURE_FPU))
751 fpregs_restore_userregs();
753 EXPORT_SYMBOL_GPL(switch_fpu_return);
755 #ifdef CONFIG_X86_DEBUG_FPU
757 * If current FPU state according to its tracking (loaded FPU context on this
758 * CPU) is not valid then we must have TIF_NEED_FPU_LOAD set so the context is
759 * loaded on return to userland.
761 void fpregs_assert_state_consistent(void)
763 struct fpu *fpu = ¤t->thread.fpu;
765 if (test_thread_flag(TIF_NEED_FPU_LOAD))
768 WARN_ON_FPU(!fpregs_state_valid(fpu, smp_processor_id()));
770 EXPORT_SYMBOL_GPL(fpregs_assert_state_consistent);
773 void fpregs_mark_activate(void)
775 struct fpu *fpu = ¤t->thread.fpu;
777 fpregs_activate(fpu);
778 fpu->last_cpu = smp_processor_id();
779 clear_thread_flag(TIF_NEED_FPU_LOAD);
783 * x87 math exception handling:
786 int fpu__exception_code(struct fpu *fpu, int trap_nr)
790 if (trap_nr == X86_TRAP_MF) {
791 unsigned short cwd, swd;
793 * (~cwd & swd) will mask out exceptions that are not set to unmasked
794 * status. 0x3f is the exception bits in these regs, 0x200 is the
795 * C1 reg you need in case of a stack fault, 0x040 is the stack
796 * fault bit. We should only be taking one exception at a time,
797 * so if this combination doesn't produce any single exception,
798 * then we have a bad program that isn't synchronizing its FPU usage
799 * and it will suffer the consequences since we won't be able to
800 * fully reproduce the context of the exception.
802 if (boot_cpu_has(X86_FEATURE_FXSR)) {
803 cwd = fpu->fpstate->regs.fxsave.cwd;
804 swd = fpu->fpstate->regs.fxsave.swd;
806 cwd = (unsigned short)fpu->fpstate->regs.fsave.cwd;
807 swd = (unsigned short)fpu->fpstate->regs.fsave.swd;
813 * The SIMD FPU exceptions are handled a little differently, as there
814 * is only a single status/control register. Thus, to determine which
815 * unmasked exception was caught we must mask the exception mask bits
816 * at 0x1f80, and then use these to mask the exception bits at 0x3f.
818 unsigned short mxcsr = MXCSR_DEFAULT;
820 if (boot_cpu_has(X86_FEATURE_XMM))
821 mxcsr = fpu->fpstate->regs.fxsave.mxcsr;
823 err = ~(mxcsr >> 7) & mxcsr;
826 if (err & 0x001) { /* Invalid op */
828 * swd & 0x240 == 0x040: Stack Underflow
829 * swd & 0x240 == 0x240: Stack Overflow
830 * User must clear the SF bit (0x40) if set
833 } else if (err & 0x004) { /* Divide by Zero */
835 } else if (err & 0x008) { /* Overflow */
837 } else if (err & 0x012) { /* Denormal, Underflow */
839 } else if (err & 0x020) { /* Precision */
844 * If we're using IRQ 13, or supposedly even some trap
845 * X86_TRAP_MF implementations, it's possible
846 * we get a spurious trap, which is not an error.