1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 1994 Linus Torvalds
5 * Pentium III FXSR, SSE support
6 * General FPU state handling cleanups
7 * Gareth Hughes <gareth@valinux.com>, May 2000
9 #include <asm/fpu/api.h>
10 #include <asm/fpu/regset.h>
11 #include <asm/fpu/sched.h>
12 #include <asm/fpu/signal.h>
13 #include <asm/fpu/types.h>
14 #include <asm/traps.h>
15 #include <asm/irq_regs.h>
17 #include <uapi/asm/kvm.h>
19 #include <linux/hardirq.h>
20 #include <linux/pkeys.h>
21 #include <linux/vmalloc.h>
28 #define CREATE_TRACE_POINTS
29 #include <asm/trace/fpu.h>
32 DEFINE_STATIC_KEY_FALSE(__fpu_state_size_dynamic);
33 DEFINE_PER_CPU(u64, xfd_state);
36 /* The FPU state configuration data for kernel and user space */
37 struct fpu_state_config fpu_kernel_cfg __ro_after_init;
38 struct fpu_state_config fpu_user_cfg __ro_after_init;
41 * Represents the initial FPU state. It's mostly (but not completely) zeroes,
42 * depending on the FPU hardware format:
44 struct fpstate init_fpstate __ro_after_init;
46 /* Track in-kernel FPU usage */
47 static DEFINE_PER_CPU(bool, in_kernel_fpu);
50 * Track which context is using the FPU on the CPU:
52 DEFINE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx);
55 * Can we use the FPU in kernel mode with the
56 * whole "kernel_fpu_begin/end()" sequence?
58 bool irq_fpu_usable(void)
60 if (WARN_ON_ONCE(in_nmi()))
63 /* In kernel FPU usage already active? */
64 if (this_cpu_read(in_kernel_fpu))
68 * When not in NMI or hard interrupt context, FPU can be used in:
70 * - Task context except from within fpregs_lock()'ed critical
73 * - Soft interrupt processing context which cannot happen
74 * while in a fpregs_lock()'ed critical region.
80 * In hard interrupt context it's safe when soft interrupts
81 * are enabled, which means the interrupt did not hit in
82 * a fpregs_lock()'ed critical region.
84 return !softirq_count();
86 EXPORT_SYMBOL(irq_fpu_usable);
89 * Track AVX512 state use because it is known to slow the max clock
92 static void update_avx_timestamp(struct fpu *fpu)
95 #define AVX512_TRACKING_MASK (XFEATURE_MASK_ZMM_Hi256 | XFEATURE_MASK_Hi16_ZMM)
97 if (fpu->fpstate->regs.xsave.header.xfeatures & AVX512_TRACKING_MASK)
98 fpu->avx512_timestamp = jiffies;
102 * Save the FPU register state in fpu->fpstate->regs. The register state is
105 * Must be called with fpregs_lock() held.
107 * The legacy FNSAVE instruction clears all FPU state unconditionally, so
108 * register state has to be reloaded. That might be a pointless exercise
109 * when the FPU is going to be used by another task right after that. But
110 * this only affects 20+ years old 32bit systems and avoids conditionals all
113 * FXSAVE and all XSAVE variants preserve the FPU register state.
115 void save_fpregs_to_fpstate(struct fpu *fpu)
117 if (likely(use_xsave())) {
118 os_xsave(fpu->fpstate);
119 update_avx_timestamp(fpu);
123 if (likely(use_fxsr())) {
124 fxsave(&fpu->fpstate->regs.fxsave);
129 * Legacy FPU register saving, FNSAVE always clears FPU registers,
130 * so we have to reload them from the memory state.
132 asm volatile("fnsave %[fp]; fwait" : [fp] "=m" (fpu->fpstate->regs.fsave));
133 frstor(&fpu->fpstate->regs.fsave);
136 void restore_fpregs_from_fpstate(struct fpstate *fpstate, u64 mask)
139 * AMD K7/K8 and later CPUs up to Zen don't save/restore
140 * FDP/FIP/FOP unless an exception is pending. Clear the x87 state
141 * here by setting it to fixed values. "m" is a random variable
142 * that should be in L1.
144 if (unlikely(static_cpu_has_bug(X86_BUG_FXSAVE_LEAK))) {
148 "fildl %P[addr]" /* set F?P to defined value */
149 : : [addr] "m" (fpstate));
154 * Dynamically enabled features are enabled in XCR0, but
155 * usage requires also that the corresponding bits in XFD
156 * are cleared. If the bits are set then using a related
157 * instruction will raise #NM. This allows to do the
158 * allocation of the larger FPU buffer lazy from #NM or if
159 * the task has no permission to kill it which would happen
160 * via #UD if the feature is disabled in XCR0.
162 * XFD state is following the same life time rules as
163 * XSTATE and to restore state correctly XFD has to be
164 * updated before XRSTORS otherwise the component would
165 * stay in or go into init state even if the bits are set
166 * in fpstate::regs::xsave::xfeatures.
168 xfd_update_state(fpstate);
171 * Restoring state always needs to modify all features
172 * which are in @mask even if the current task cannot use
175 * So fpstate->xfeatures cannot be used here, because then
176 * a feature for which the task has no permission but was
177 * used by the previous task would not go into init state.
179 mask = fpu_kernel_cfg.max_features & mask;
181 os_xrstor(fpstate, mask);
184 fxrstor(&fpstate->regs.fxsave);
186 frstor(&fpstate->regs.fsave);
190 void fpu_reset_from_exception_fixup(void)
192 restore_fpregs_from_fpstate(&init_fpstate, XFEATURE_MASK_FPSTATE);
195 #if IS_ENABLED(CONFIG_KVM)
196 static void __fpstate_reset(struct fpstate *fpstate, u64 xfd);
198 static void fpu_init_guest_permissions(struct fpu_guest *gfpu)
200 struct fpu_state_perm *fpuperm;
203 if (!IS_ENABLED(CONFIG_X86_64))
206 spin_lock_irq(¤t->sighand->siglock);
207 fpuperm = ¤t->group_leader->thread.fpu.guest_perm;
208 perm = fpuperm->__state_perm;
210 /* First fpstate allocation locks down permissions. */
211 WRITE_ONCE(fpuperm->__state_perm, perm | FPU_GUEST_PERM_LOCKED);
213 spin_unlock_irq(¤t->sighand->siglock);
215 gfpu->perm = perm & ~FPU_GUEST_PERM_LOCKED;
218 bool fpu_alloc_guest_fpstate(struct fpu_guest *gfpu)
220 struct fpstate *fpstate;
223 size = fpu_user_cfg.default_size + ALIGN(offsetof(struct fpstate, regs), 64);
224 fpstate = vzalloc(size);
228 /* Leave xfd to 0 (the reset value defined by spec) */
229 __fpstate_reset(fpstate, 0);
230 fpstate_init_user(fpstate);
231 fpstate->is_valloc = true;
232 fpstate->is_guest = true;
234 gfpu->fpstate = fpstate;
235 gfpu->xfeatures = fpu_user_cfg.default_features;
236 gfpu->perm = fpu_user_cfg.default_features;
239 * KVM sets the FP+SSE bits in the XSAVE header when copying FPU state
240 * to userspace, even when XSAVE is unsupported, so that restoring FPU
241 * state on a different CPU that does support XSAVE can cleanly load
242 * the incoming state using its natural XSAVE. In other words, KVM's
243 * uABI size may be larger than this host's default size. Conversely,
244 * the default size should never be larger than KVM's base uABI size;
245 * all features that can expand the uABI size must be opt-in.
247 gfpu->uabi_size = sizeof(struct kvm_xsave);
248 if (WARN_ON_ONCE(fpu_user_cfg.default_size > gfpu->uabi_size))
249 gfpu->uabi_size = fpu_user_cfg.default_size;
251 fpu_init_guest_permissions(gfpu);
255 EXPORT_SYMBOL_GPL(fpu_alloc_guest_fpstate);
257 void fpu_free_guest_fpstate(struct fpu_guest *gfpu)
259 struct fpstate *fps = gfpu->fpstate;
264 if (WARN_ON_ONCE(!fps->is_valloc || !fps->is_guest || fps->in_use))
267 gfpu->fpstate = NULL;
270 EXPORT_SYMBOL_GPL(fpu_free_guest_fpstate);
273 * fpu_enable_guest_xfd_features - Check xfeatures against guest perm and enable
274 * @guest_fpu: Pointer to the guest FPU container
275 * @xfeatures: Features requested by guest CPUID
277 * Enable all dynamic xfeatures according to guest perm and requested CPUID.
279 * Return: 0 on success, error code otherwise
281 int fpu_enable_guest_xfd_features(struct fpu_guest *guest_fpu, u64 xfeatures)
283 lockdep_assert_preemption_enabled();
285 /* Nothing to do if all requested features are already enabled. */
286 xfeatures &= ~guest_fpu->xfeatures;
290 return __xfd_enable_feature(xfeatures, guest_fpu);
292 EXPORT_SYMBOL_GPL(fpu_enable_guest_xfd_features);
295 void fpu_update_guest_xfd(struct fpu_guest *guest_fpu, u64 xfd)
298 guest_fpu->fpstate->xfd = xfd;
299 if (guest_fpu->fpstate->in_use)
300 xfd_update_state(guest_fpu->fpstate);
303 EXPORT_SYMBOL_GPL(fpu_update_guest_xfd);
306 * fpu_sync_guest_vmexit_xfd_state - Synchronize XFD MSR and software state
308 * Must be invoked from KVM after a VMEXIT before enabling interrupts when
309 * XFD write emulation is disabled. This is required because the guest can
310 * freely modify XFD and the state at VMEXIT is not guaranteed to be the
311 * same as the state on VMENTER. So software state has to be udpated before
312 * any operation which depends on it can take place.
314 * Note: It can be invoked unconditionally even when write emulation is
315 * enabled for the price of a then pointless MSR read.
317 void fpu_sync_guest_vmexit_xfd_state(void)
319 struct fpstate *fps = current->thread.fpu.fpstate;
321 lockdep_assert_irqs_disabled();
322 if (fpu_state_size_dynamic()) {
323 rdmsrl(MSR_IA32_XFD, fps->xfd);
324 __this_cpu_write(xfd_state, fps->xfd);
327 EXPORT_SYMBOL_GPL(fpu_sync_guest_vmexit_xfd_state);
328 #endif /* CONFIG_X86_64 */
330 int fpu_swap_kvm_fpstate(struct fpu_guest *guest_fpu, bool enter_guest)
332 struct fpstate *guest_fps = guest_fpu->fpstate;
333 struct fpu *fpu = ¤t->thread.fpu;
334 struct fpstate *cur_fps = fpu->fpstate;
337 if (!cur_fps->is_confidential && !test_thread_flag(TIF_NEED_FPU_LOAD))
338 save_fpregs_to_fpstate(fpu);
342 fpu->__task_fpstate = cur_fps;
343 fpu->fpstate = guest_fps;
344 guest_fps->in_use = true;
346 guest_fps->in_use = false;
347 fpu->fpstate = fpu->__task_fpstate;
348 fpu->__task_fpstate = NULL;
351 cur_fps = fpu->fpstate;
353 if (!cur_fps->is_confidential) {
354 /* Includes XFD update */
355 restore_fpregs_from_fpstate(cur_fps, XFEATURE_MASK_FPSTATE);
358 * XSTATE is restored by firmware from encrypted
359 * memory. Make sure XFD state is correct while
360 * running with guest fpstate
362 xfd_update_state(cur_fps);
365 fpregs_mark_activate();
369 EXPORT_SYMBOL_GPL(fpu_swap_kvm_fpstate);
371 void fpu_copy_guest_fpstate_to_uabi(struct fpu_guest *gfpu, void *buf,
372 unsigned int size, u32 pkru)
374 struct fpstate *kstate = gfpu->fpstate;
375 union fpregs_state *ustate = buf;
376 struct membuf mb = { .p = buf, .left = size };
378 if (cpu_feature_enabled(X86_FEATURE_XSAVE)) {
379 __copy_xstate_to_uabi_buf(mb, kstate, pkru, XSTATE_COPY_XSAVE);
381 memcpy(&ustate->fxsave, &kstate->regs.fxsave,
382 sizeof(ustate->fxsave));
383 /* Make it restorable on a XSAVE enabled host */
384 ustate->xsave.header.xfeatures = XFEATURE_MASK_FPSSE;
387 EXPORT_SYMBOL_GPL(fpu_copy_guest_fpstate_to_uabi);
389 int fpu_copy_uabi_to_guest_fpstate(struct fpu_guest *gfpu, const void *buf,
390 u64 xcr0, u32 *vpkru)
392 struct fpstate *kstate = gfpu->fpstate;
393 const union fpregs_state *ustate = buf;
395 if (!cpu_feature_enabled(X86_FEATURE_XSAVE)) {
396 if (ustate->xsave.header.xfeatures & ~XFEATURE_MASK_FPSSE)
398 if (ustate->fxsave.mxcsr & ~mxcsr_feature_mask)
400 memcpy(&kstate->regs.fxsave, &ustate->fxsave, sizeof(ustate->fxsave));
404 if (ustate->xsave.header.xfeatures & ~xcr0)
408 * Nullify @vpkru to preserve its current value if PKRU's bit isn't set
409 * in the header. KVM's odd ABI is to leave PKRU untouched in this
410 * case (all other components are eventually re-initialized).
412 if (!(ustate->xsave.header.xfeatures & XFEATURE_MASK_PKRU))
415 return copy_uabi_from_kernel_to_xstate(kstate, ustate, vpkru);
417 EXPORT_SYMBOL_GPL(fpu_copy_uabi_to_guest_fpstate);
418 #endif /* CONFIG_KVM */
420 void kernel_fpu_begin_mask(unsigned int kfpu_mask)
424 WARN_ON_FPU(!irq_fpu_usable());
425 WARN_ON_FPU(this_cpu_read(in_kernel_fpu));
427 this_cpu_write(in_kernel_fpu, true);
429 if (!(current->flags & (PF_KTHREAD | PF_IO_WORKER)) &&
430 !test_thread_flag(TIF_NEED_FPU_LOAD)) {
431 set_thread_flag(TIF_NEED_FPU_LOAD);
432 save_fpregs_to_fpstate(¤t->thread.fpu);
434 __cpu_invalidate_fpregs_state();
436 /* Put sane initial values into the control registers. */
437 if (likely(kfpu_mask & KFPU_MXCSR) && boot_cpu_has(X86_FEATURE_XMM))
438 ldmxcsr(MXCSR_DEFAULT);
440 if (unlikely(kfpu_mask & KFPU_387) && boot_cpu_has(X86_FEATURE_FPU))
441 asm volatile ("fninit");
443 EXPORT_SYMBOL_GPL(kernel_fpu_begin_mask);
445 void kernel_fpu_end(void)
447 WARN_ON_FPU(!this_cpu_read(in_kernel_fpu));
449 this_cpu_write(in_kernel_fpu, false);
452 EXPORT_SYMBOL_GPL(kernel_fpu_end);
455 * Sync the FPU register state to current's memory register state when the
456 * current task owns the FPU. The hardware register state is preserved.
458 void fpu_sync_fpstate(struct fpu *fpu)
460 WARN_ON_FPU(fpu != ¤t->thread.fpu);
463 trace_x86_fpu_before_save(fpu);
465 if (!test_thread_flag(TIF_NEED_FPU_LOAD))
466 save_fpregs_to_fpstate(fpu);
468 trace_x86_fpu_after_save(fpu);
472 static inline unsigned int init_fpstate_copy_size(void)
475 return fpu_kernel_cfg.default_size;
477 /* XSAVE(S) just needs the legacy and the xstate header part */
478 return sizeof(init_fpstate.regs.xsave);
481 static inline void fpstate_init_fxstate(struct fpstate *fpstate)
483 fpstate->regs.fxsave.cwd = 0x37f;
484 fpstate->regs.fxsave.mxcsr = MXCSR_DEFAULT;
488 * Legacy x87 fpstate state init:
490 static inline void fpstate_init_fstate(struct fpstate *fpstate)
492 fpstate->regs.fsave.cwd = 0xffff037fu;
493 fpstate->regs.fsave.swd = 0xffff0000u;
494 fpstate->regs.fsave.twd = 0xffffffffu;
495 fpstate->regs.fsave.fos = 0xffff0000u;
499 * Used in two places:
500 * 1) Early boot to setup init_fpstate for non XSAVE systems
501 * 2) fpu_init_fpstate_user() which is invoked from KVM
503 void fpstate_init_user(struct fpstate *fpstate)
505 if (!cpu_feature_enabled(X86_FEATURE_FPU)) {
506 fpstate_init_soft(&fpstate->regs.soft);
510 xstate_init_xcomp_bv(&fpstate->regs.xsave, fpstate->xfeatures);
512 if (cpu_feature_enabled(X86_FEATURE_FXSR))
513 fpstate_init_fxstate(fpstate);
515 fpstate_init_fstate(fpstate);
518 static void __fpstate_reset(struct fpstate *fpstate, u64 xfd)
520 /* Initialize sizes and feature masks */
521 fpstate->size = fpu_kernel_cfg.default_size;
522 fpstate->user_size = fpu_user_cfg.default_size;
523 fpstate->xfeatures = fpu_kernel_cfg.default_features;
524 fpstate->user_xfeatures = fpu_user_cfg.default_features;
528 void fpstate_reset(struct fpu *fpu)
530 /* Set the fpstate pointer to the default fpstate */
531 fpu->fpstate = &fpu->__fpstate;
532 __fpstate_reset(fpu->fpstate, init_fpstate.xfd);
534 /* Initialize the permission related info in fpu */
535 fpu->perm.__state_perm = fpu_kernel_cfg.default_features;
536 fpu->perm.__state_size = fpu_kernel_cfg.default_size;
537 fpu->perm.__user_state_size = fpu_user_cfg.default_size;
538 /* Same defaults for guests */
539 fpu->guest_perm = fpu->perm;
542 static inline void fpu_inherit_perms(struct fpu *dst_fpu)
544 if (fpu_state_size_dynamic()) {
545 struct fpu *src_fpu = ¤t->group_leader->thread.fpu;
547 spin_lock_irq(¤t->sighand->siglock);
548 /* Fork also inherits the permissions of the parent */
549 dst_fpu->perm = src_fpu->perm;
550 dst_fpu->guest_perm = src_fpu->guest_perm;
551 spin_unlock_irq(¤t->sighand->siglock);
555 /* Clone current's FPU state on fork */
556 int fpu_clone(struct task_struct *dst, unsigned long clone_flags, bool minimal)
558 struct fpu *src_fpu = ¤t->thread.fpu;
559 struct fpu *dst_fpu = &dst->thread.fpu;
561 /* The new task's FPU state cannot be valid in the hardware. */
562 dst_fpu->last_cpu = -1;
564 fpstate_reset(dst_fpu);
566 if (!cpu_feature_enabled(X86_FEATURE_FPU))
570 * Enforce reload for user space tasks and prevent kernel threads
571 * from trying to save the FPU registers on context switch.
573 set_tsk_thread_flag(dst, TIF_NEED_FPU_LOAD);
576 * No FPU state inheritance for kernel threads and IO
580 /* Clear out the minimal state */
581 memcpy(&dst_fpu->fpstate->regs, &init_fpstate.regs,
582 init_fpstate_copy_size());
587 * If a new feature is added, ensure all dynamic features are
588 * caller-saved from here!
590 BUILD_BUG_ON(XFEATURE_MASK_USER_DYNAMIC != XFEATURE_MASK_XTILE_DATA);
593 * Save the default portion of the current FPU state into the
594 * clone. Assume all dynamic features to be defined as caller-
595 * saved, which enables skipping both the expansion of fpstate
596 * and the copying of any dynamic state.
598 * Do not use memcpy() when TIF_NEED_FPU_LOAD is set because
599 * copying is not valid when current uses non-default states.
602 if (test_thread_flag(TIF_NEED_FPU_LOAD))
603 fpregs_restore_userregs();
604 save_fpregs_to_fpstate(dst_fpu);
606 if (!(clone_flags & CLONE_THREAD))
607 fpu_inherit_perms(dst_fpu);
610 * Children never inherit PASID state.
611 * Force it to have its init value:
614 dst_fpu->fpstate->regs.xsave.header.xfeatures &= ~XFEATURE_MASK_PASID;
616 trace_x86_fpu_copy_src(src_fpu);
617 trace_x86_fpu_copy_dst(dst_fpu);
623 * Whitelist the FPU register state embedded into task_struct for hardened
626 void fpu_thread_struct_whitelist(unsigned long *offset, unsigned long *size)
628 *offset = offsetof(struct thread_struct, fpu.__fpstate.regs);
629 *size = fpu_kernel_cfg.default_size;
633 * Drops current FPU state: deactivates the fpregs and
634 * the fpstate. NOTE: it still leaves previous contents
635 * in the fpregs in the eager-FPU case.
637 * This function can be used in cases where we know that
638 * a state-restore is coming: either an explicit one,
641 void fpu__drop(struct fpu *fpu)
645 if (fpu == ¤t->thread.fpu) {
646 /* Ignore delayed exceptions from user space */
647 asm volatile("1: fwait\n"
649 _ASM_EXTABLE(1b, 2b));
650 fpregs_deactivate(fpu);
653 trace_x86_fpu_dropped(fpu);
659 * Clear FPU registers by setting them up from the init fpstate.
660 * Caller must do fpregs_[un]lock() around it.
662 static inline void restore_fpregs_from_init_fpstate(u64 features_mask)
665 os_xrstor(&init_fpstate, features_mask);
667 fxrstor(&init_fpstate.regs.fxsave);
669 frstor(&init_fpstate.regs.fsave);
671 pkru_write_default();
675 * Reset current->fpu memory state to the init values.
677 static void fpu_reset_fpregs(void)
679 struct fpu *fpu = ¤t->thread.fpu;
684 * This does not change the actual hardware registers. It just
685 * resets the memory image and sets TIF_NEED_FPU_LOAD so a
686 * subsequent return to usermode will reload the registers from the
687 * task's memory image.
689 * Do not use fpstate_init() here. Just copy init_fpstate which has
690 * the correct content already except for PKRU.
692 * PKRU handling does not rely on the xstate when restoring for
693 * user space as PKRU is eagerly written in switch_to() and
696 memcpy(&fpu->fpstate->regs, &init_fpstate.regs, init_fpstate_copy_size());
697 set_thread_flag(TIF_NEED_FPU_LOAD);
702 * Reset current's user FPU states to the init states. current's
703 * supervisor states, if any, are not modified by this function. The
704 * caller guarantees that the XSTATE header in memory is intact.
706 void fpu__clear_user_states(struct fpu *fpu)
708 WARN_ON_FPU(fpu != ¤t->thread.fpu);
711 if (!cpu_feature_enabled(X86_FEATURE_FPU)) {
718 * Ensure that current's supervisor states are loaded into their
719 * corresponding registers.
721 if (xfeatures_mask_supervisor() &&
722 !fpregs_state_valid(fpu, smp_processor_id()))
723 os_xrstor_supervisor(fpu->fpstate);
725 /* Reset user states in registers. */
726 restore_fpregs_from_init_fpstate(XFEATURE_MASK_USER_RESTORE);
729 * Now all FPU registers have their desired values. Inform the FPU
730 * state machine that current's FPU registers are in the hardware
731 * registers. The memory image does not need to be updated because
732 * any operation relying on it has to save the registers first when
733 * current's FPU is marked active.
735 fpregs_mark_activate();
739 void fpu_flush_thread(void)
741 fpstate_reset(¤t->thread.fpu);
745 * Load FPU context before returning to userspace.
747 void switch_fpu_return(void)
749 if (!static_cpu_has(X86_FEATURE_FPU))
752 fpregs_restore_userregs();
754 EXPORT_SYMBOL_GPL(switch_fpu_return);
756 #ifdef CONFIG_X86_DEBUG_FPU
758 * If current FPU state according to its tracking (loaded FPU context on this
759 * CPU) is not valid then we must have TIF_NEED_FPU_LOAD set so the context is
760 * loaded on return to userland.
762 void fpregs_assert_state_consistent(void)
764 struct fpu *fpu = ¤t->thread.fpu;
766 if (test_thread_flag(TIF_NEED_FPU_LOAD))
769 WARN_ON_FPU(!fpregs_state_valid(fpu, smp_processor_id()));
771 EXPORT_SYMBOL_GPL(fpregs_assert_state_consistent);
774 void fpregs_mark_activate(void)
776 struct fpu *fpu = ¤t->thread.fpu;
778 fpregs_activate(fpu);
779 fpu->last_cpu = smp_processor_id();
780 clear_thread_flag(TIF_NEED_FPU_LOAD);
784 * x87 math exception handling:
787 int fpu__exception_code(struct fpu *fpu, int trap_nr)
791 if (trap_nr == X86_TRAP_MF) {
792 unsigned short cwd, swd;
794 * (~cwd & swd) will mask out exceptions that are not set to unmasked
795 * status. 0x3f is the exception bits in these regs, 0x200 is the
796 * C1 reg you need in case of a stack fault, 0x040 is the stack
797 * fault bit. We should only be taking one exception at a time,
798 * so if this combination doesn't produce any single exception,
799 * then we have a bad program that isn't synchronizing its FPU usage
800 * and it will suffer the consequences since we won't be able to
801 * fully reproduce the context of the exception.
803 if (boot_cpu_has(X86_FEATURE_FXSR)) {
804 cwd = fpu->fpstate->regs.fxsave.cwd;
805 swd = fpu->fpstate->regs.fxsave.swd;
807 cwd = (unsigned short)fpu->fpstate->regs.fsave.cwd;
808 swd = (unsigned short)fpu->fpstate->regs.fsave.swd;
814 * The SIMD FPU exceptions are handled a little differently, as there
815 * is only a single status/control register. Thus, to determine which
816 * unmasked exception was caught we must mask the exception mask bits
817 * at 0x1f80, and then use these to mask the exception bits at 0x3f.
819 unsigned short mxcsr = MXCSR_DEFAULT;
821 if (boot_cpu_has(X86_FEATURE_XMM))
822 mxcsr = fpu->fpstate->regs.fxsave.mxcsr;
824 err = ~(mxcsr >> 7) & mxcsr;
827 if (err & 0x001) { /* Invalid op */
829 * swd & 0x240 == 0x040: Stack Underflow
830 * swd & 0x240 == 0x240: Stack Overflow
831 * User must clear the SF bit (0x40) if set
834 } else if (err & 0x004) { /* Divide by Zero */
836 } else if (err & 0x008) { /* Overflow */
838 } else if (err & 0x012) { /* Denormal, Underflow */
840 } else if (err & 0x020) { /* Precision */
845 * If we're using IRQ 13, or supposedly even some trap
846 * X86_TRAP_MF implementations, it's possible
847 * we get a spurious trap, which is not an error.
853 * Initialize register state that may prevent from entering low-power idle.
854 * This function will be invoked from the cpuidle driver only when needed.
856 void fpu_idle_fpregs(void)
858 /* Note: AMX_TILE being enabled implies XGETBV1 support */
859 if (cpu_feature_enabled(X86_FEATURE_AMX_TILE) &&
860 (xfeatures_in_use() & XFEATURE_MASK_XTILE)) {
862 fpregs_deactivate(¤t->thread.fpu);